Processor Specific Files
mark.langsdorf at amd.com
mark.langsdorf at amd.com
Wed Aug 23 17:59:43 EDT 2000
I'm using an Elan Sc520 with 16 megs of AMD CFI compliant
flash on it. The flash is arranged into two banks, each
built from 4 interleaved 8-bit flash chips. Each bank is
separately mapped into physically memory using a Programmable
Address Region (PAR), and the BIOS sets these up and makes
them write-cacheable by default.
My problem is that the cfi_probe() code fails if the PARS
are write-cacheable, since the return value of an earlier
probe is cached, and then returned for the 4x8 probe. It's
possible to reprogram the PARs, but I'm not sure where to
do it. Should I put it in physmap.c, at the start of the
initialization routine? Someplace else? Create a specific
module for my processor and do it there? What's the best
way to handle this?
Mark Langsdorf
Advanced Micro Devices, Inc Tel: 512.602.3756
5204 E. Ben White Blvd. M/S 590 Fax: 512.602.5051
Austin, TX 78741 mark.langsdorf at amd.com
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