mtd: nand: fsl_ifc: Fix nand waitfunc return value
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Fri Mar 23 00:59:01 PDT 2018
Gitweb: http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=fa8e6d58c5bc260f4369c6699683d69695daed0a
Commit: fa8e6d58c5bc260f4369c6699683d69695daed0a
Parent: 6de564939e14327148e31ddcf769e34105176447
Author: Jagdish Gediya <jagdish.gediya at nxp.com>
AuthorDate: Wed Mar 21 04:31:36 2018 +0530
Committer: Boris Brezillon <boris.brezillon at bootlin.com>
CommitDate: Wed Mar 21 10:13:13 2018 +0100
mtd: nand: fsl_ifc: Fix nand waitfunc return value
As per the IFC hardware manual, Most significant 2 bytes in
nand_fsr register are the outcome of NAND READ STATUS command.
So status value need to be shifted and aligned as per the nand
framework requirement.
Fixes: 82771882d960 ("NAND Machine support for Integrated Flash Controller")
Cc: stable at vger.kernel.org # v3.18+
Signed-off-by: Jagdish Gediya <jagdish.gediya at nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
Signed-off-by: Boris Brezillon <boris.brezillon at bootlin.com>
---
drivers/mtd/nand/fsl_ifc_nand.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 4872a7ba6503..b6a3ba445cfb 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -626,6 +626,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
u32 nand_fsr;
+ int status;
/* Use READ_STATUS command, but wait for the device to be ready */
ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
@@ -640,12 +641,12 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
fsl_ifc_run_command(mtd);
nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
-
+ status = nand_fsr >> 24;
/*
* The chip always seems to report that it is
* write-protected, even when it is not.
*/
- return nand_fsr | NAND_STATUS_WP;
+ return status | NAND_STATUS_WP;
}
/*
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