mtd: nand: davinci: set ECC algorithm explicitly for HW based ECC

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=19d8ccc42b148d75284a3809f1eb1eba13a81677
Commit:     19d8ccc42b148d75284a3809f1eb1eba13a81677
Parent:     0b2f93dc0099e3b8a739b8918eeb995e12520940
Author:     Alexander Couzens <lynxis at fe80.eu>
AuthorDate: Tue May 2 11:47:36 2017 +0200
Committer:  Boris Brezillon <boris.brezillon at free-electrons.com>
CommitDate: Mon May 15 12:00:46 2017 +0200

    mtd: nand: davinci: set ECC algorithm explicitly for HW based ECC
    
    If ECC strength is 4bits/512bytes the algorithm of the ECC engine is
    BCH, otherwise (1bit/512bytes) Hamming is used.
    
    Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
    Signed-off-by: Boris Brezillon <boris.brezillon at free-electrons.com>
---
 drivers/mtd/nand/davinci_nand.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 531c519..7b26e53 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -771,11 +771,14 @@ static int nand_davinci_probe(struct platform_device *pdev)
 			info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
 			info->chip.ecc.bytes = 10;
 			info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
+			info->chip.ecc.algo = NAND_ECC_BCH;
 		} else {
+			/* 1bit ecc hamming */
 			info->chip.ecc.calculate = nand_davinci_calculate_1bit;
 			info->chip.ecc.correct = nand_davinci_correct_1bit;
 			info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
 			info->chip.ecc.bytes = 3;
+			info->chip.ecc.algo = NAND_ECC_HAMMING;
 		}
 		info->chip.ecc.size = 512;
 		info->chip.ecc.strength = pdata->ecc_bits;