mtd: nand: sunxi: adapt clk_rate to tWB, tADL, tWHR and tRHW timings

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=5abcd95d8c69008c72d54d7763e0ee2b5df84ac4
Commit:     5abcd95d8c69008c72d54d7763e0ee2b5df84ac4
Parent:     2d43457f79e48ee427666fdbfe9a53f35d3a1672
Author:     Boris Brezillon <boris.brezillon at free-electrons.com>
AuthorDate: Wed Nov 11 22:30:30 2015 +0100
Committer:  Boris Brezillon <boris.brezillon at free-electrons.com>
CommitDate: Tue Apr 19 22:05:38 2016 +0200

    mtd: nand: sunxi: adapt clk_rate to tWB, tADL, tWHR and tRHW timings
    
    Adapt the NAND controller clk rate to the tWB, tADL, tWHR and tRHW
    timings instead of returning an error when the maximum clk divisor is
    not big enough to provide an appropriate timing.
    
    Signed-off-by: Boris Brezillon <boris.brezillon at free-electrons.com>
---
 drivers/mtd/nand/sunxi_nand.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index b906fc5..e30276d 100644
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -1163,6 +1163,18 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
 		min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
 
 	/* T16 - T19 + tCAD */
+	if (timings->tWB_max > (min_clk_period * 20))
+		min_clk_period = DIV_ROUND_UP(timings->tWB_max, 20);
+
+	if (timings->tADL_min > (min_clk_period * 32))
+		min_clk_period = DIV_ROUND_UP(timings->tADL_min, 32);
+
+	if (timings->tWHR_min > (min_clk_period * 32))
+		min_clk_period = DIV_ROUND_UP(timings->tWHR_min, 32);
+
+	if (timings->tRHW_min > (min_clk_period * 20))
+		min_clk_period = DIV_ROUND_UP(timings->tRHW_min, 20);
+
 	tWB  = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
 					min_clk_period);
 	if (tWB < 0) {