mtd: nand: omap: Update DT binding documentation

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=51735caad3db6237fa9d31a2ce8b54cbd42ff6f0
Commit:     51735caad3db6237fa9d31a2ce8b54cbd42ff6f0
Parent:     c9711ec5250b22fd94e9b34c17c095e001a90e66
Author:     Roger Quadros <rogerq at ti.com>
AuthorDate: Mon May 26 11:54:45 2014 +0300
Committer:  Roger Quadros <rogerq at ti.com>
CommitDate: Fri Apr 15 11:53:46 2016 +0300

    mtd: nand: omap: Update DT binding documentation
    
    Add compatible id and interrupts. The NAND interrupts are
    provided by the GPMC controller node.
    
    Signed-off-by: Roger Quadros <rogerq at ti.com>
    Acked-by: Rob Herring <robh at kernel.org>
    Acked-by: Brian Norris <computersforpeace at gmail.com>
    Acked-by: Tony Lindgren <tony at atomide.com>
---
 Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index fb733c4..ff3215d2 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -13,7 +13,11 @@ Documentation/devicetree/bindings/mtd/nand.txt
 
 Required properties:
 
- - reg:		The CS line the peripheral is connected to
+ - compatible:	"ti,omap2-nand"
+ - reg:		range id (CS number), base offset and length of the
+		NAND I/O space
+ - interrupt-parent: must point to gpmc node
+ - interrupts:	Two interrupt specifiers, one for fifoevent, one for termcount.
 
 Optional properties:
 
@@ -55,17 +59,22 @@ Example for an AM33xx board:
 	gpmc: gpmc at 50000000 {
 		compatible = "ti,am3352-gpmc";
 		ti,hwmods = "gpmc";
-		reg = <0x50000000 0x1000000>;
+		reg = <0x50000000 0x36c>;
 		interrupts = <100>;
 		gpmc,num-cs = <8>;
 		gpmc,num-waitpins = <2>;
 		#address-cells = <2>;
 		#size-cells = <1>;
-		ranges = <0 0 0x08000000 0x2000>;	/* CS0: NAND */
+		ranges = <0 0 0x08000000 0x1000000>;	/* CS0 space, 16MB */
 		elm_id = <&elm>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
 
 		nand at 0,0 {
-			reg = <0 0 0>; /* CS0, offset 0 */
+			compatible = "ti,omap2-nand";
+			reg = <0 0 4>;		/* CS0, offset 0, NAND I/O window 4 */
+			interrupt-parent = <&gpmc>;
+			interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE NONE>;
 			nand-bus-width = <16>;
 			ti,nand-ecc-opt = "bch8";
 			ti,nand-xfer-type = "polled";