doc: dt: mtd: brcmnand: Add brcm,bcm6368-nand device tree binding

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=d135d1c158618c73346a898b6a08018013e43715
Commit:     d135d1c158618c73346a898b6a08018013e43715
Parent:     d5c5620167d0fde476a0c0d8bb1f5751bcc1e495
Author:     Simon Arlott <simon at fire.lp0.eu>
AuthorDate: Wed Dec 9 20:40:58 2015 +0000
Committer:  Brian Norris <computersforpeace at gmail.com>
CommitDate: Wed Dec 9 18:28:41 2015 -0800

    doc: dt: mtd: brcmnand: Add brcm,bcm6368-nand device tree binding
    
    Add device tree binding for NAND on the BCM6368.
    
    The BCM6368 has a NAND interrupt register with combined status and enable
    registers. It also requires a clock, so add an optional clock to the
    common brcmnand binding.
    
    Signed-off-by: Simon Arlott <simon at fire.lp0.eu>
    Reviewed-by: Florian Fainelli <f.fainelli at gmail.com>
    Acked-by: Rob Herring <robh at kernel.org>
    Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 .../devicetree/bindings/mtd/brcm,brcmnand.txt      | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
index 4ff7128..c2546ce 100644
--- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
+++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
@@ -45,6 +45,8 @@ Required properties:
 - #size-cells      : <0>
 
 Optional properties:
+- clock                     : reference to the clock for the NAND controller
+- clock-names               : "nand" (required for the above clock)
 - brcm,nand-has-wp          : Some versions of this IP include a write-protect
                               (WP) control bit. It is always available on >=
                               v7.0. Use this property to describe the rare
@@ -72,6 +74,12 @@ we define additional 'compatible' properties and associated register resources w
        and enable registers
      - reg-names: (required) "nand-int-base"
 
+   * "brcm,nand-bcm6368"
+     - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"
+     - reg: (required) the 'NAND_INTR_BASE' register range, with combined status
+       and enable registers, and boot address registers
+     - reg-names: (required) "nand-int-base"
+
    * "brcm,nand-iproc"
      - reg: (required) the "IDM" register range, for interrupt enable and APB
        bus access endianness configuration, and the "EXT" register range,
@@ -148,3 +156,27 @@ nand at f0442800 {
 		};
 	};
 };
+
+nand at 10000200 {
+	compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
+		"brcm,brcmnand-v4.0", "brcm,brcmnand";
+	reg = <0x10000200 0x180>,
+	      <0x10000600 0x200>,
+	      <0x100000b0 0x10>;
+	reg-names = "nand", "nand-cache", "nand-int-base";
+	interrupt-parent = <&periph_intc>;
+	interrupts = <50>;
+	clocks = <&periph_clk 20>;
+	clock-names = "nand";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nand0: nandcs at 0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+		nand-on-flash-bbt;
+		nand-ecc-strength = <1>;
+		nand-ecc-step-size = <512>;
+	};
+};