mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=b58439916bdc4c4a5d782e6104e6a4e354bc3022
Commit:     b58439916bdc4c4a5d782e6104e6a4e354bc3022
Parent:     422485da15e7e9e6f71a5efd1aa2248595cb486d
Author:     Graham Moore <grmoore at opensource.altera.com>
AuthorDate: Sat Jun 4 02:39:33 2016 +0200
Committer:  Brian Norris <computersforpeace at gmail.com>
CommitDate: Mon Jul 18 09:58:16 2016 -0700

    mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver
    
    Add binding document for the Cadence QSPI controller.
    
    Signed-off-by: Graham Moore <grmoore at opensource.altera.com>
    Signed-off-by: Marek Vasut <marex at denx.de>
    Cc: Alan Tull <atull at opensource.altera.com>
    Cc: Brian Norris <computersforpeace at gmail.com>
    Cc: David Woodhouse <dwmw2 at infradead.org>
    Cc: Dinh Nguyen <dinguyen at opensource.altera.com>
    Cc: Graham Moore <grmoore at opensource.altera.com>
    Cc: Vignesh R <vigneshr at ti.com>
    Cc: Yves Vandervennet <yvanderv at opensource.altera.com>
    Cc: devicetree at vger.kernel.org
    Acked-by: Rob Herring <robh at kernel.org>
    Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 .../devicetree/bindings/mtd/cadence-quadspi.txt    | 56 ++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
new file mode 100644
index 0000000..f248056
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -0,0 +1,56 @@
+* Cadence Quad SPI controller
+
+Required properties:
+- compatible : Should be "cdns,qspi-nor".
+- reg : Contains two entries, each of which is a tuple consisting of a
+	physical address and length. The first entry is the address and
+	length of the controller register set. The second entry is the
+	address and length of the QSPI Controller data area.
+- interrupts : Unit interrupt specifier for the controller interrupt.
+- clocks : phandle to the Quad SPI clock.
+- cdns,fifo-depth : Size of the data FIFO in words.
+- cdns,fifo-width : Bus width of the data FIFO in bytes.
+- cdns,trigger-address : 32-bit indirect AHB trigger address.
+
+Optional properties:
+- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
+
+Optional subnodes:
+Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
+custom properties:
+- cdns,read-delay : Delay for read capture logic, in clock cycles
+- cdns,tshsl-ns : Delay in nanoseconds for the length that the master
+                  mode chip select outputs are de-asserted between
+		  transactions.
+- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being
+                  de-activated and the activation of another.
+- cdns,tchsh-ns : Delay in nanoseconds between last bit of current
+                  transaction and deasserting the device chip select
+		  (qspi_n_ss_out).
+- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
+                  and first bit transfer.
+
+Example:
+
+	qspi: spi at ff705000 {
+		compatible = "cdns,qspi-nor";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0xff705000 0x1000>,
+		      <0xffa00000 0x1000>;
+		interrupts = <0 151 4>;
+		clocks = <&qspi_clk>;
+		cdns,is-decoded-cs;
+		cdns,fifo-depth = <128>;
+		cdns,fifo-width = <4>;
+		cdns,trigger-address = <0x00000000>;
+
+		flash0: n25q00 at 0 {
+			...
+			cdns,read-delay = <4>;
+			cdns,tshsl-ns = <50>;
+			cdns,tsd2d-ns = <50>;
+			cdns,tchsh-ns = <4>;
+			cdns,tslch-ns = <4>;
+		};
+	};