mtd: nand: pxa3xx-nand: fix random command timeouts

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=21fc0ef9652f0c809dc0d3e0a67f1e1bf6ff8255
Commit:     21fc0ef9652f0c809dc0d3e0a67f1e1bf6ff8255
Parent:     0b14392db2e998157d924085d7913e537ec26121
Author:     Robert Jarzmik <robert.jarzmik at free.fr>
AuthorDate: Wed Aug 19 20:30:15 2015 +0200
Committer:  Brian Norris <computersforpeace at gmail.com>
CommitDate: Wed Aug 19 15:25:32 2015 -0700

    mtd: nand: pxa3xx-nand: fix random command timeouts
    
    When 2 commands are submitted in a row, and the second is very quick,
    the completion of the second command might never come. This happens
    especially if the second command is quick, such as a status read after
    an erase.
    
    The issue is that in the interrupt handler, the status bits are cleared
    after the new command is issued. There is a small temporal window where
    this happens :
     - the previous command has set the command done bit
     - the ready for a command bit is set
     - the handler submits the next command
       - just then, the command completes, and the command done bit is still
         set
     - the handler clears the "previous" command done bit
     - the handler exits
    
    In this flow, the "command done" of the next command will never trigger
    a new interrupt to finish the status command, as it was cleared for both
    commands.
    
    Fix this by clearing the status bit before submitting a new command.
    
    Signed-off-by: Robert Jarzmik <robert.jarzmik at free.fr>
    Acked-by: Ezequiel Garcia <ezequiel at vanguardiasur.com.ar>
    Tested-by: Ezequiel Garcia <ezequiel at vanguardiasur.com.ar>
    Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/nand/pxa3xx_nand.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index faf056b..51f8a58 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -678,8 +678,14 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 		is_ready = 1;
 	}
 
+	/*
+	 * Clear all status bit before issuing the next command, which
+	 * can and will alter the status bits and will deserve a new
+	 * interrupt on its own. This lets the controller exit the IRQ
+	 */
+	nand_writel(info, NDSR, status);
+
 	if (status & NDSR_WRCMDREQ) {
-		nand_writel(info, NDSR, NDSR_WRCMDREQ);
 		status &= ~NDSR_WRCMDREQ;
 		info->state = STATE_CMD_HANDLE;
 
@@ -700,8 +706,6 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 			nand_writel(info, NDCB0, info->ndcb3);
 	}
 
-	/* clear NDSR to let the controller exit the IRQ */
-	nand_writel(info, NDSR, status);
 	if (is_completed)
 		complete(&info->cmd_complete);
 	if (is_ready)