mtd: fsl-quadspi: Actually clear TX FIFO upon write

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=038761dfe4ce145f0f080cc08ee43f6e0ab3ae2f
Commit:     038761dfe4ce145f0f080cc08ee43f6e0ab3ae2f
Parent:     cef1ed9c6bcf69245c0b9eb89b3f3a45049ba10c
Author:     Alexander Stein <alexander.stein at systec-electronic.com>
AuthorDate: Thu Jul 2 11:37:56 2015 +0200
Committer:  Brian Norris <computersforpeace at gmail.com>
CommitDate: Mon Jul 20 10:41:33 2015 -0700

    mtd: fsl-quadspi: Actually clear TX FIFO upon write
    
    QUADSPI_MCR_CLR_TXF_MASK is the correct mask for clearing the TX FIFO.
    
    Signed-off-by: Alexander Stein <alexander.stein at systec-electronic.com>
    Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 4fe13dd..1946c6d 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -539,7 +539,7 @@ static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
 
 	/* clear the TX FIFO. */
 	tmp = readl(q->iobase + QUADSPI_MCR);
-	writel(tmp | QUADSPI_MCR_CLR_RXF_MASK, q->iobase + QUADSPI_MCR);
+	writel(tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
 
 	/* fill the TX data to the FIFO */
 	for (j = 0, i = ((count + 3) / 4); j < i; j++) {