mtd: nand: pxa3xx: Switch FIFO draining to jiffies-based timeout
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linux-mtd at lists.infradead.org
Tue Jun 23 10:59:02 PDT 2015
Gitweb: http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=afca11ec13066d53c7b21fdd02dff2662a86eef5
Commit: afca11ec13066d53c7b21fdd02dff2662a86eef5
Parent: 818a45b1d7fbd8c55a4248fe6cd0995e06db04be
Author: Maxime Ripard <maxime.ripard at free-electrons.com>
AuthorDate: Tue Apr 7 15:32:45 2015 +0200
Committer: Brian Norris <computersforpeace at gmail.com>
CommitDate: Thu May 7 00:04:27 2015 -0700
mtd: nand: pxa3xx: Switch FIFO draining to jiffies-based timeout
Now that the driver handles the FIFO draining in a threaded interrupt, we can
base our timeout on jiffies and sleeping, instead of using mdelay.
Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
drivers/mtd/nand/pxa3xx_nand.c | 20 +++++++++-----------
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index a4615fc..6798fae 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -22,6 +22,7 @@
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/of.h>
@@ -483,7 +484,8 @@ static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
{
if (info->ecc_bch) {
- int timeout;
+ u32 val;
+ int ret;
/*
* According to the datasheet, when reading from NDDB
@@ -496,16 +498,12 @@ static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
while (len > 8) {
__raw_readsl(info->mmio_base + NDDB, data, 8);
- for (timeout = 0;
- !(nand_readl(info, NDSR) & NDSR_RDDREQ);
- timeout++) {
- if (timeout >= 5) {
- dev_err(&info->pdev->dev,
- "Timeout on RDDREQ while draining the FIFO\n");
- return;
- }
-
- mdelay(1);
+ ret = readl_relaxed_poll_timeout(info->mmio_base + NDSR, val,
+ val & NDSR_RDDREQ, 1000, 5000);
+ if (ret) {
+ dev_err(&info->pdev->dev,
+ "Timeout on RDDREQ while draining the FIFO\n");
+ return;
}
data += 32;
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