mtd: nand: pxa3xx: Fix PIO FIFO draining

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=8dad0386b97c4bd6edd56752ca7f2e735fe5beb4
Commit:     8dad0386b97c4bd6edd56752ca7f2e735fe5beb4
Parent:     c517d838eb7d07bbe9507871fab3931deccff539
Author:     Maxime Ripard <maxime.ripard at free-electrons.com>
AuthorDate: Wed Feb 18 11:32:07 2015 +0100
Committer:  Brian Norris <computersforpeace at gmail.com>
CommitDate: Sat Feb 28 00:53:50 2015 -0800

    mtd: nand: pxa3xx: Fix PIO FIFO draining
    
    The NDDB register holds the data that are needed by the read and write
    commands.
    
    However, during a read PIO access, the datasheet specifies that after each 32
    bytes read in that register, when BCH is enabled, we have to make sure that the
    RDDREQ bit is set in the NDSR register.
    
    This fixes an issue that was seen on the Armada 385, and presumably other mvebu
    SoCs, when a read on a newly erased page would end up in the driver reporting a
    timeout from the NAND.
    
    Cc: <stable at vger.kernel.org> # v3.14
    Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
    Reviewed-by: Boris Brezillon <boris.brezillon at free-electrons.com>
    Acked-by: Ezequiel Garcia <ezequiel.garcia at free-electrons.com>
    Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/nand/pxa3xx_nand.c | 48 ++++++++++++++++++++++++++++++++++++------
 1 file changed, 42 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 96b0b1d..bc67736 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -480,6 +480,42 @@ static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 	nand_writel(info, NDCR, ndcr | int_mask);
 }
 
+static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
+{
+	if (info->ecc_bch) {
+		int timeout;
+
+		/*
+		 * According to the datasheet, when reading from NDDB
+		 * with BCH enabled, after each 32 bytes reads, we
+		 * have to make sure that the NDSR.RDDREQ bit is set.
+		 *
+		 * Drain the FIFO 8 32 bits reads at a time, and skip
+		 * the polling on the last read.
+		 */
+		while (len > 8) {
+			__raw_readsl(info->mmio_base + NDDB, data, 8);
+
+			for (timeout = 0;
+			     !(nand_readl(info, NDSR) & NDSR_RDDREQ);
+			     timeout++) {
+				if (timeout >= 5) {
+					dev_err(&info->pdev->dev,
+						"Timeout on RDDREQ while draining the FIFO\n");
+					return;
+				}
+
+				mdelay(1);
+			}
+
+			data += 32;
+			len -= 8;
+		}
+	}
+
+	__raw_readsl(info->mmio_base + NDDB, data, len);
+}
+
 static void handle_data_pio(struct pxa3xx_nand_info *info)
 {
 	unsigned int do_bytes = min(info->data_size, info->chunk_size);
@@ -496,14 +532,14 @@ static void handle_data_pio(struct pxa3xx_nand_info *info)
 				      DIV_ROUND_UP(info->oob_size, 4));
 		break;
 	case STATE_PIO_READING:
-		__raw_readsl(info->mmio_base + NDDB,
-			     info->data_buff + info->data_buff_pos,
-			     DIV_ROUND_UP(do_bytes, 4));
+		drain_fifo(info,
+			   info->data_buff + info->data_buff_pos,
+			   DIV_ROUND_UP(do_bytes, 4));
 
 		if (info->oob_size > 0)
-			__raw_readsl(info->mmio_base + NDDB,
-				     info->oob_buff + info->oob_buff_pos,
-				     DIV_ROUND_UP(info->oob_size, 4));
+			drain_fifo(info,
+				   info->oob_buff + info->oob_buff_pos,
+				   DIV_ROUND_UP(info->oob_size, 4));
 		break;
 	default:
 		dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,