mtd: nand: add sunxi NFC dt bindings doc
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Mon Dec 15 19:59:04 PST 2014
Gitweb: http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=5935946c6a1180dcb495fffb2c45eddedfa09064
Commit: 5935946c6a1180dcb495fffb2c45eddedfa09064
Parent: 1fef62c1423b694da517b18dc80d59a7eaf7dd74
Author: Boris BREZILLON <boris.brezillon at free-electrons.com>
AuthorDate: Tue Oct 21 15:08:42 2014 +0200
Committer: Brian Norris <computersforpeace at gmail.com>
CommitDate: Wed Oct 29 10:08:01 2014 -0700
mtd: nand: add sunxi NFC dt bindings doc
Add the sunxi NAND Flash Controller dt bindings documentation.
Signed-off-by: Boris Brezillon <boris.brezillon at free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
.../devicetree/bindings/mtd/sunxi-nand.txt | 45 ++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
new file mode 100644
index 0000000..0273adb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
@@ -0,0 +1,45 @@
+Allwinner NAND Flash Controller (NFC)
+
+Required properties:
+- compatible : "allwinner,sun4i-a10-nand".
+- reg : shall contain registers location and length for data and reg.
+- interrupts : shall define the nand controller interrupt.
+- #address-cells: shall be set to 1. Encode the nand CS.
+- #size-cells : shall be set to 0.
+- clocks : shall reference nand controller clocks.
+- clock-names : nand controller internal clock names. Shall contain :
+ * "ahb" : AHB gating clock
+ * "mod" : nand controller clock
+
+Optional children nodes:
+Children nodes represent the available nand chips.
+
+Optional properties:
+- allwinner,rb : shall contain the native Ready/Busy ids.
+ or
+- rb-gpios : shall contain the gpios used as R/B pins.
+- nand-ecc-mode : one of the supported ECC modes ("hw", "hw_syndrome", "soft",
+ "soft_bch" or "none")
+
+see Documentation/devicetree/mtd/nand.txt for generic bindings.
+
+
+Examples:
+nfc: nand at 01c03000 {
+ compatible = "allwinner,sun4i-a10-nand";
+ reg = <0x01c03000 0x1000>;
+ interrupts = <0 37 1>;
+ clocks = <&ahb_gates 13>, <&nand_clk>;
+ clock-names = "ahb", "mod";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
+ status = "okay";
+
+ nand at 0 {
+ reg = <0>;
+ allwinner,rb = <0>;
+ nand-ecc-mode = "soft_bch";
+ };
+};
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