mtd: st_spi_fsm: Provide a method to put the chip into 32bit addressing mode

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=0de08e43cdda9a2acbd3310491a7882ec43b24b3
Commit:     0de08e43cdda9a2acbd3310491a7882ec43b24b3
Parent:     0ea7d70693431842b6b5c1808f59aa49e3fca6b1
Author:     Lee Jones <lee.jones at linaro.org>
AuthorDate: Thu Mar 20 09:20:51 2014 +0000
Committer:  Brian Norris <computersforpeace at gmail.com>
CommitDate: Thu Mar 20 04:17:18 2014 -0700

    mtd: st_spi_fsm: Provide a method to put the chip into 32bit addressing mode
    
    Most Serial Flash chips support 24bit addressing as a default but more
    recent incarnations can support 32bit. Based on information provided
    though platform specific data and capabilities we can determine whether
    or not our current chip can. This patch provides a means to setup the
    FSM message sequence to put the chip into 32bit mode.
    
    Acked-by Angus Clark <angus.clark at st.com>
    Signed-off-by: Lee Jones <lee.jones at linaro.org>
    Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/devices/st_spi_fsm.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index 7cc4425..0a5b702 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -375,6 +375,8 @@ static struct flash_info flash_types[] = {
 	{ NULL, 0x000000, 0, 0, 0, 0, 0, NULL },
 };
 
+static struct stfsm_seq stfsm_seq_en_32bit_addr;/* Dynamically populated */
+
 static struct stfsm_seq stfsm_seq_read_jedec = {
 	.data_size = TRANSFER_SIZE(8),
 	.seq_opc[0] = (SEQ_OPC_PADS_1 |
@@ -523,6 +525,23 @@ static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf,
 	}
 }
 
+static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter)
+{
+	struct stfsm_seq *seq = &stfsm_seq_en_32bit_addr;
+	uint32_t cmd = enter ? FLASH_CMD_EN4B_ADDR : FLASH_CMD_EX4B_ADDR;
+
+	seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
+			   SEQ_OPC_CYCLES(8) |
+			   SEQ_OPC_OPCODE(cmd) |
+			   SEQ_OPC_CSDEASSERT);
+
+	stfsm_load_seq(fsm, seq);
+
+	stfsm_wait_seq(fsm);
+
+	return 0;
+}
+
 /*
  * SoC reset on 'boot-from-spi' systems
  *