i915: Use 120MHz LVDS SSC clock for gen5/gen6/gen7

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=f69e515699d8e9b1c25dcfe1c4c6f435087495d2
Commit:     f69e515699d8e9b1c25dcfe1c4c6f435087495d2
Parent:     7bd40c16ccb2cb6877dd00b0e66249c171e6fa43
Author:     Duncan Laurie <dlaurie at chromium.org>
AuthorDate: Wed Nov 13 17:59:43 2013 -0800
Committer:  Daniel Vetter <daniel.vetter at ffwll.ch>
CommitDate: Fri Nov 15 00:38:44 2013 +0100

    i915: Use 120MHz LVDS SSC clock for gen5/gen6/gen7
    
    We had been using a DMI table workaround to select the right
    frequency for devices, but this is fragile and must be updated
    with every new platform.
    
    Instead the default case when VBT is missing is changed to use
    120MHz clock for LVDS SSC for these generations.
    
    The docs for 2010-Core, SandyBridge, and IvyBridge all indicate
    that the reference frequency for LVDS is 120MHz:
    
    "2010 Core"
    http://intellinuxgraphics.org/IHD_OS_Vol3_Part3r2.pdf
    page 38
    Reference Frequency: 120MHz for CRT and LVDS.  100MHz for the FDI.
    
    "2011 SandyBridge"
    http://intellinuxgraphics.org/documentation/SNB/IHD_OS_Vol3_Part3.pdf
    page 33
    Reference Frequency: 120MHz for CRT, HDMI, LVDS.  100MHz for the FDI.
    
    "2012 IvyBridge"
    http://intellinuxgraphics.org/documentation/IVB/IHD_OS_Vol3_Part4.pdf
    page 27
    Reference Frequency: 120 MHz for CRT, HDMI, LVDS, 100MHz for the FDI.
    
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    [olof: Fixup for recent base, switched from if/else to single call]
    Signed-off-by: Olof Johansson <olof at lixom.net>
    Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
    Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
 drivers/gpu/drm/i915/intel_bios.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 6dd622d..e4fba39 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -790,7 +790,12 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
 
 	/* Default to using SSC */
 	dev_priv->vbt.lvds_use_ssc = 1;
-	dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
+	/*
+	 * Core/SandyBridge/IvyBridge use alternative (120MHz) reference
+	 * clock for LVDS.
+	 */
+	dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev,
+			!HAS_PCH_SPLIT(dev));
 	DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->vbt.lvds_ssc_freq);
 
 	for (port = PORT_A; port < I915_MAX_PORTS; port++) {