powerpc/eeh: Enable PCI_COMMAND_MASTER for PCI bridges

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=bf898ec5cbd33be11147743bee27b66b10cb2f85
Commit:     bf898ec5cbd33be11147743bee27b66b10cb2f85
Parent:     b4789b8e6be3151a955ade74872822f30e8cd914
Author:     Gavin Shan <shangw at linux.vnet.ibm.com>
AuthorDate: Tue Nov 12 14:49:21 2013 +0800
Committer:  Benjamin Herrenschmidt <benh at kernel.crashing.org>
CommitDate: Thu Nov 21 10:33:35 2013 +1100

    powerpc/eeh: Enable PCI_COMMAND_MASTER for PCI bridges
    
    On PHB3, we will fail to fetch IODA tables without PCI_COMMAND_MASTER
    on PCI bridges. According to one experiment I had, the MSIx interrupts
    didn't raise from the adapter without the bit applied to all upstream
    PCI bridges including root port of the adapter. The patch forces to
    have that bit enabled accordingly.
    
    Signed-off-by: Gavin Shan <shangw at linux.vnet.ibm.com>
    CC: <stable at vger.kernel.org>
    Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
---
 arch/powerpc/kernel/eeh.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index 6713020..4bd687d 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -686,6 +686,15 @@ void eeh_save_bars(struct eeh_dev *edev)
 
 	for (i = 0; i < 16; i++)
 		eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]);
+
+	/*
+	 * For PCI bridges including root port, we need enable bus
+	 * master explicitly. Otherwise, it can't fetch IODA table
+	 * entries correctly. So we cache the bit in advance so that
+	 * we can restore it after reset, either PHB range or PE range.
+	 */
+	if (edev->mode & EEH_DEV_BRIDGE)
+		edev->config_space[1] |= PCI_COMMAND_MASTER;
 }
 
 /**