mtd: nand: add the "bits per cell" info for legacy ID NAND

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=1c195e909cbe335b02a5dd01075ba65448927ae6
Commit:     1c195e909cbe335b02a5dd01075ba65448927ae6
Parent:     7db906b79f69b6ed936a1ef1d788f02e3ad42462
Author:     Huang Shijie <b32955 at freescale.com>
AuthorDate: Wed Sep 25 14:58:12 2013 +0800
Committer:  Brian Norris <computersforpeace at gmail.com>
CommitDate: Sun Oct 27 16:27:05 2013 -0700

    mtd: nand: add the "bits per cell" info for legacy ID NAND
    
    The legacy ID NAND are all SLC.
    This patch sets 1 to the @bits_per_cell for the legacy ID NAND,
    which means they are all SLC.
    
    Signed-off-by: Huang Shijie <b32955 at freescale.com>
    Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/nand/nand_base.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 5fb0095..aebc7ea 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -3238,6 +3238,9 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
 	mtd->oobsize = mtd->writesize / 32;
 	*busw = type->options & NAND_BUSWIDTH_16;
 
+	/* All legacy ID NAND are small-page, SLC */
+	chip->bits_per_cell = 1;
+
 	/*
 	 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
 	 * some Spansion chips have erasesize that conflicts with size