mtd: fsl_ifc_nand: set NAND_NO_SUBPAGE_WRITE

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=20cd0008bb01ea0f5dd5779896bf6f069aab9c8a
Commit:     20cd0008bb01ea0f5dd5779896bf6f069aab9c8a
Parent:     435796889d714ffaf90923cfea868d8b5d28008c
Author:     Scott Wood <scottwood at freescale.com>
AuthorDate: Wed Apr 10 17:34:37 2013 -0500
Committer:  David Woodhouse <David.Woodhouse at intel.com>
CommitDate: Mon Aug 5 19:09:39 2013 +0100

    mtd: fsl_ifc_nand: set NAND_NO_SUBPAGE_WRITE
    
    This controller only does ECC on full-page accesses, even though the
    ECC consists of multiple steps.  fsl_elbc_nand can get away with this
    because the ECC of an all-0xff region will be all-0xff, but this is not
    true with the ECC algorithms used by IFC.
    
    Signed-off-by: Scott Wood <scottwood at freescale.com>
    Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
    Signed-off-by: David Woodhouse <David.Woodhouse at intel.com>
---
 drivers/mtd/nand/fsl_ifc_nand.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 180bfa7..317a771 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -823,7 +823,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 
 	/* set up nand options */
 	chip->bbt_options = NAND_BBT_USE_FLASH;
-
+	chip->options = NAND_NO_SUBPAGE_WRITE;
 
 	if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
 		chip->read_byte = fsl_ifc_read_byte16;