[MTD] [NAND] fsl_elbc_nand: fix OOB workability for large page NAND chips

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=452db2724351ff3d9416a183a7955e00ab4e6ab4
Commit:     452db2724351ff3d9416a183a7955e00ab4e6ab4
Parent:     bd5a43822b438f297f4088f1cfd3514e32e56328
Author:     Anton Vorontsov <avorontsov at ru.mvista.com>
AuthorDate: Fri Jun 27 23:04:04 2008 +0400
Committer:  David Woodhouse <David.Woodhouse at intel.com>
CommitDate: Fri Jul 11 18:12:01 2008 +0100

    [MTD] [NAND] fsl_elbc_nand: fix OOB workability for large page NAND chips
    
    For large page chips, nand_bbt is looking into OOB area, and checking
    for "0xff 0xff" pattern at OOB offset 0. That is, two bytes should be
    reserved for bbt means.
    
    But ELBC driver is specifying ecclayout so that oobfree area starts at
    offset 1, so only one byte left for the bbt purposes.
    
    This causes problems with any OOB users, namely JFFS2: after first mount
    JFFS2 will fill all OOBs with "erased marker", so OOBs will contain:
    
      OOB Data: ff 19 85 20 03 00 ff ff ff 00 00 08 ff ff ff ff
      OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
      OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
      OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
    
    And on the next boot, NAND core will rescan for bad blocks, then will
    see "0xff 0x19" pattern, and will mark all blocks as bad ones.
    
    To fix the issue we should implement our own bad block pattern: just one
    byte at OOB start. Though, this will work only for x8 chips. For x16
    chips two bytes must be checked. Since ELBC driver does not support x16
    NANDs (yet), we're safe for now.
    
    Signed-off-by: Anton Vorontsov <avorontsov at ru.mvista.com>
    Acked-by: Scott Wood <scottwood at freescale.com>
    Signed-off-by: David Woodhouse <David.Woodhouse at intel.com>
---
 drivers/mtd/nand/fsl_elbc_nand.c |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 1b06d29..99dc2be 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -116,6 +116,20 @@ static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 	.oobavail = 48,
 };
 
+/*
+ * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
+ * 1, so we have to adjust bad block pattern. This pattern should be used for
+ * x8 chips only. So far hardware does not support x16 chips anyway.
+ */
+static u8 scan_ff_pattern[] = { 0xff, };
+
+static struct nand_bbt_descr largepage_memorybased = {
+	.options = 0,
+	.offs = 0,
+	.len = 1,
+	.pattern = scan_ff_pattern,
+};
+
 /*=================================*/
 
 /*
@@ -687,6 +701,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
 			chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 			                   &fsl_elbc_oob_lp_eccm1 :
 			                   &fsl_elbc_oob_lp_eccm0;
+			chip->badblock_pattern = &largepage_memorybased;
 			mtd->ecclayout = chip->ecc.layout;
 			mtd->oobavail = chip->ecc.layout->oobavail;
 		}