mtd/drivers/mtd/nand au1550nd.c,1.8,1.9

[ppopov at infradead.org]

Update of /home/cvs/mtd/drivers/mtd/nand
In directory phoenix.infradead.org:/tmp/cvs-serv17240/drivers/mtd/nand

Modified Files:
	au1550nd.c 
Log Message:
Cleaned up Db1550 define; added a check for kernel version to 
include the proper files for 2.4 and 2.6. This is ugly and needs to be
revisited.


Index: au1550nd.c
===================================================================
RCS file: /home/cvs/mtd/drivers/mtd/nand/au1550nd.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -r1.8 -r1.9
--- au1550nd.c	16 Sep 2004 23:27:14 -0000	1.8
+++ au1550nd.c	20 Oct 2004 05:58:30 -0000	1.9
@@ -18,6 +18,17 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <asm/io.h>
+
+/* fixme: this is ugly */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 0)
+#include <asm/mach-au1x00/au1000.h>
+#ifdef CONFIG_MIPS_PB1550
+#include <asm/mach-pb1x00/pb1550.h> 
+#endif
+#ifdef CONFIG_MIPS_DB1550
+#include <asm/mach-db1x00/db1x00.h> 
+#endif
+#else
 #include <asm/au1000.h>
 #ifdef CONFIG_MIPS_PB1550
 #include <asm/pb1550.h> 
@@ -25,7 +36,7 @@
 #ifdef CONFIG_MIPS_DB1550
 #include <asm/db1x00.h> 
 #endif
-
+#endif
 
 /*
  * MTD structure for NAND controller
@@ -34,6 +45,8 @@
 static void __iomem *p_nand;
 static int nand_width = 1; /* default x8*/
 
+#define NAND_CS 1
+
 /*
  * Define partitions for flash device
  */
@@ -295,18 +308,18 @@
 	case NAND_CTL_CLRALE: 
 		this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; 
 		/* FIXME: Nobody knows why this is neccecary, 
-		 * but it works onlythat way */
+		 * but it works only that way */
 		udelay(1); 
 		break;
 
 	case NAND_CTL_SETNCE: 
 		/* assert (force assert) chip enable */
-		au_writel(au_readl(MEM_STNDCTL) | 0x20 , MEM_STNDCTL);
+		au_writel(au_readl(MEM_STNDCTL) | (1<<(4+NAND_CS)) , MEM_STNDCTL);
 		break;
 
 	case NAND_CTL_CLRNCE: 
  		/* deassert chip enable */
-		au_writel(au_readl(MEM_STNDCTL) & ~0x20 , MEM_STNDCTL);
+		au_writel(au_readl(MEM_STNDCTL) & ~(1<<(4+NAND_CS)), MEM_STNDCTL);
 		break;
 	}
 
@@ -330,7 +343,6 @@
 {
 	struct nand_chip *this;
 	u16 boot_swapboot = 0; /* default value */
-	u32 mem_time;
 	int retval;
 
 	/* Allocate memory for MTD device structure and private data */
@@ -351,9 +363,10 @@
 	/* Link the private data with the MTD structure */
 	au1550_mtd->priv = this;
 
+
+	/* MEM_STNDCTL: disable ints, disable nand boot */
 	/* disable interrupts */
 	au_writel(au_readl(MEM_STNDCTL) & ~(1<<8), MEM_STNDCTL);
-
 	/* disable NAND boot */
 	au_writel(au_readl(MEM_STNDCTL) & ~(1<<0), MEM_STNDCTL);
 
@@ -385,33 +398,19 @@
 			retval = -EINVAL;
 			goto outmem;
 	}
+#endif
 
 	/* Configure RCE1 - should be done by YAMON */
-	au_writel(0x5 | (nand_width << 22), MEM_STCFG1);
-	au_writel(NAND_TIMING, MEM_STTIME1);
-	mem_time = au_readl(MEM_STTIME1);
+	au_writel(0x5 | (nand_width << 22), 0xB4001010); /* MEM_STCFG1 */
+	au_writel(NAND_TIMING, 0xB4001014); /* MEM_STTIME1 */
 	au_sync();
 
-	/* setup and enable chip select */
+	/* setup and enable chip select, MEM_STADDR1 */
 	/* we really need to decode offsets only up till 0x20 */
 	au_writel((1<<28) | (NAND_PHYS_ADDR>>4) | 
 			(((NAND_PHYS_ADDR + 0x1000)-1) & (0x3fff<<18)>>18), 
 			MEM_STADDR1);
 	au_sync();
-#endif
-
-#ifdef CONFIG_MIPS_DB1550
-	/* FIXME: should be done by the bootloader
-	 *  
-	 * tglx: stcfg1 was set to 0x00400005. I changed
-	 * this as it does not work with all chips.
-	 * someone should look into the correct timing
-	 * values, as bit 8 does a clock / 4 prescale
-	*/
-	au_writel(0x00400105, MEM_STCFG1);
-	au_writel(0x00007774, MEM_STTIME1);
-	au_writel(0x12003FFF, MEM_STADDR1);
-#endif
 
 	p_nand = (void __iomem *)ioremap(NAND_PHYS_ADDR, 0x1000);