mtd/drivers/mtd/nand rtc_from4.c,1.4,1.5

gleixner at infradead.org gleixner at infradead.org
Fri Oct 1 17:45:33 EDT 2004


Update of /home/cvs/mtd/drivers/mtd/nand
In directory phoenix.infradead.org:/tmp/cvs-serv8240

Modified Files:
	rtc_from4.c 
Log Message:
Use the syndrome provided by the FPGA

Index: rtc_from4.c
===================================================================
RCS file: /home/cvs/mtd/drivers/mtd/nand/rtc_from4.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -r1.4 -r1.5
--- rtc_from4.c	20 Sep 2004 11:41:52 -0000	1.4
+++ rtc_from4.c	1 Oct 2004 21:45:30 -0000	1.5
@@ -159,38 +159,38 @@
  * of the ecc byte which we get from the FPGA
  */
 static uint8_t revbits[256] = {
-	0xff, 0x7f, 0xbf, 0x3f, 0xdf, 0x5f, 0x9f, 0x1f,
-	0xef, 0x6f, 0xaf, 0x2f, 0xcf, 0x4f, 0x8f, 0x0f,
-	0xf7, 0x77, 0xb7, 0x37, 0xd7, 0x57, 0x97, 0x17,
-	0xe7, 0x67, 0xa7, 0x27, 0xc7, 0x47, 0x87, 0x07,
-	0xfb, 0x7b, 0xbb, 0x3b, 0xdb, 0x5b, 0x9b, 0x1b,
-	0xeb, 0x6b, 0xab, 0x2b, 0xcb, 0x4b, 0x8b, 0x0b,
-	0xf3, 0x73, 0xb3, 0x33, 0xd3, 0x53, 0x93, 0x13,
-	0xe3, 0x63, 0xa3, 0x23, 0xc3, 0x43, 0x83, 0x03,
-	0xfd, 0x7d, 0xbd, 0x3d, 0xdd, 0x5d, 0x9d, 0x1d,
-	0xed, 0x6d, 0xad, 0x2d, 0xcd, 0x4d, 0x8d, 0x0d,
-	0xf5, 0x75, 0xb5, 0x35, 0xd5, 0x55, 0x95, 0x15,
-	0xe5, 0x65, 0xa5, 0x25, 0xc5, 0x45, 0x85, 0x05,
-	0xf9, 0x79, 0xb9, 0x39, 0xd9, 0x59, 0x99, 0x19,
-	0xe9, 0x69, 0xa9, 0x29, 0xc9, 0x49, 0x89, 0x09,
-	0xf1, 0x71, 0xb1, 0x31, 0xd1, 0x51, 0x91, 0x11,
-	0xe1, 0x61, 0xa1, 0x21, 0xc1, 0x41, 0x81, 0x01,
-	0xfe, 0x7e, 0xbe, 0x3e, 0xde, 0x5e, 0x9e, 0x1e,
-	0xee, 0x6e, 0xae, 0x2e, 0xce, 0x4e, 0x8e, 0x0e,
-	0xf6, 0x76, 0xb6, 0x36, 0xd6, 0x56, 0x96, 0x16,
-	0xe6, 0x66, 0xa6, 0x26, 0xc6, 0x46, 0x86, 0x06,
-	0xfa, 0x7a, 0xba, 0x3a, 0xda, 0x5a, 0x9a, 0x1a,
-	0xea, 0x6a, 0xaa, 0x2a, 0xca, 0x4a, 0x8a, 0x0a,
-	0xf2, 0x72, 0xb2, 0x32, 0xd2, 0x52, 0x92, 0x12,
-	0xe2, 0x62, 0xa2, 0x22, 0xc2, 0x42, 0x82, 0x02,
-	0xfc, 0x7c, 0xbc, 0x3c, 0xdc, 0x5c, 0x9c, 0x1c,
-	0xec, 0x6c, 0xac, 0x2c, 0xcc, 0x4c, 0x8c, 0x0c,
-	0xf4, 0x74, 0xb4, 0x34, 0xd4, 0x54, 0x94, 0x14,
-	0xe4, 0x64, 0xa4, 0x24, 0xc4, 0x44, 0x84, 0x04,
-	0xf8, 0x78, 0xb8, 0x38, 0xd8, 0x58, 0x98, 0x18,
-	0xe8, 0x68, 0xa8, 0x28, 0xc8, 0x48, 0x88, 0x08,
-	0xf0, 0x70, 0xb0, 0x30, 0xd0, 0x50, 0x90, 0x10,
-	0xe0, 0x60, 0xa0, 0x20, 0xc0, 0x40, 0x80, 0x00,
+        0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
+        0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
+        0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
+        0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
+        0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
+        0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
+        0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
+        0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
+        0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
+        0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
+        0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
+        0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
+        0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
+        0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
+        0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
+        0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
+        0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
+        0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
+        0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
+        0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
+        0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
+        0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
+        0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
+        0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
+        0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
+        0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
+        0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
+        0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
+        0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
+        0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
+        0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
+        0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
 };
 
 #endif
@@ -358,6 +358,8 @@
 	ecc_code[7] |= 0x0f;	/* set the last four bits (not used) */
 }
 
+/* Make the rslib macros work */
+#define rs rs_decoder
 
 /*
  * rtc_from4_correct_data - hardware specific code to correct data using ECC code
@@ -375,10 +377,11 @@
  */
 static int rtc_from4_correct_data(struct mtd_info *mtd, const u_char *buf, u_char *ecc1, u_char *ecc2)
 {
-	int i, res;
+	int i, j, res;
 	unsigned short status; 
-	uint16_t rpar[6];
+	uint16_t par[6], syn[6], tmp;
 	uint8_t ecc[8];
+        volatile unsigned short *rs_ecc;
 
 	status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CHK));
 
@@ -386,29 +389,38 @@
 		return 0;
 	}
 
-	/* Reverse bits and invert the codes */
-	for (i = 0; i < 8; i++) {
-		ecc[i] = revbits[ecc1[i]];
+	/* Read the syndrom pattern from the FPGA and correct the bitorder */
+	rs_ecc = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC);
+        for (i = 0; i < 8; i++) {
+                ecc[i] = revbits[(*rs_ecc) & 0xFF];
+                rs_ecc++;
+        }
+
+	/* convert into 6 10bit syndrome fields */
+	par[5] = INDEX_OF[(((uint16_t)ecc[0] >> 0) & 0x0ff) | (((uint16_t)ecc[1] << 8) & 0x300)];
+	par[4] = INDEX_OF[(((uint16_t)ecc[1] >> 2) & 0x03f) | (((uint16_t)ecc[2] << 6) & 0x3c0)];
+	par[3] = INDEX_OF[(((uint16_t)ecc[2] >> 4) & 0x00f) | (((uint16_t)ecc[3] << 4) & 0x3f0)];
+	par[2] = INDEX_OF[(((uint16_t)ecc[3] >> 6) & 0x003) | (((uint16_t)ecc[4] << 2) & 0x3fc)];
+	par[1] = INDEX_OF[(((uint16_t)ecc[5] >> 0) & 0x0ff) | (((uint16_t)ecc[6] << 8) & 0x300)];
+	par[0] = (((uint16_t)ecc[6] >> 2) & 0x03f) | (((uint16_t)ecc[7] << 6) & 0x3c0);
+
+	/* Convert to computable syndrome */
+	for (i = 0; i < 6; i++) {
+		syn[i] = par[0];
+		for (j = 1; j < 6; j++)
+			if (par[j] != A0)
+				syn[i] ^= ALPHA_TO[MODNN(par[j] + i * j)];
+
+		/* Convert to index form */
+		syn[i] = INDEX_OF[syn[i]];
 	}
 
-	/* convert into 6 10bit parity fields */
-	rpar[0] =  ((uint16_t)ecc[0])               | (((uint16_t)ecc[1] << 8) & 0x300);
-	rpar[1] = (((uint16_t)ecc[1] >> 2) & 0x03f) | (((uint16_t)ecc[2] << 6) & 0x3c0);
-	rpar[2] = (((uint16_t)ecc[2] >> 4) & 0x00f) | (((uint16_t)ecc[3] << 4) & 0x3f0);
-	rpar[3] = (((uint16_t)ecc[3] >> 6) & 0x003) | (((uint16_t)ecc[4] << 2) & 0x3fc);
-	rpar[4] =  ((uint16_t)ecc[5])               | (((uint16_t)ecc[6] << 8) & 0x300);
-	rpar[5] = (((uint16_t)ecc[6] >> 2) & 0x03f) | (((uint16_t)ecc[7] << 6) & 0x3c0);
-
-	/* Let the library code do its magic. 
-	 * Set the data inversion mask to 0xff, as the FPGA inverts data on read
-	 * except for the virtual bits 9 /10 which are tied low
-	 */
-	res = decode_rs8 (rs_decoder, buf, rpar, 512, NULL, 0, NULL, 0xff);
+	/* Let the library code do its magic.*/
+	res = decode_rs8 (rs_decoder, buf, par, 512, syn, 0, NULL, 0xff, NULL);
 	if (res > 0) {
 		DEBUG (MTD_DEBUG_LEVEL0, "rtc_from4_correct_data: " 
 			"ECC corrected %d errors on read\n", res);
 	}
-
 	return res;
 }
 #endif





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