mtd/drivers/mtd/nand au1550nd.c,1.3,1.4

[ppopov at infradead.org]

Update of /home/cvs/mtd/drivers/mtd/nand
In directory phoenix.infradead.org:/tmp/cvs-serv25641/drivers/mtd/nand

Modified Files:
	au1550nd.c 
Log Message:
- Added DB1550 support.
- Fixed a bug in freeing a static array in the _cleanup function.


Index: au1550nd.c
===================================================================
RCS file: /home/cvs/mtd/drivers/mtd/nand/au1550nd.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -r1.3 -r1.4
--- au1550nd.c	10 May 2004 07:28:18 -0000	1.3
+++ au1550nd.c	12 May 2004 06:23:58 -0000	1.4
@@ -20,18 +20,20 @@
 #include <asm/io.h>
 #include <asm/au1000.h>
 #ifdef CONFIG_MIPS_PB1550
-#include <asm/pb1550.h>
+/* for timings, should be done by YAMON */
+#include <asm/pb1550.h> 
+#endif
+#ifdef CONFIG_MIPS_DB1550
+#include <asm/db1x00.h> 
 #endif
 
-#define NAND_PHYS_ADDR   0x20000000 
-#define NUM_PARTITIONS            2
 
 /*
  * MTD structure for Pb1550 board
  */
 static struct mtd_info *au1550_mtd = NULL;
 static volatile u32 p_nand;
-static int nand_width;
+static int nand_width = 1; /* default, only x8 supported for now */
 
 /* Internal buffers. Page buffer and oob buffer for one block*/
 static u_char data_buf[512 + 16];
@@ -40,7 +42,9 @@
 /*
  * Define partitions for flash device
  */
-const static struct mtd_partition partition_info[NUM_PARTITIONS] = {
+const static struct mtd_partition partition_info[] = {
+#ifdef CONFIG_MIPS_PB1550
+#define NUM_PARTITIONS            2
 	{ 
 		.name = "Pb1550 NAND FS 0",
 	  	.offset = 0,
@@ -51,6 +55,20 @@
 		.offset =  MTDPART_OFS_APPEND,
  		.size =    MTDPART_SIZ_FULL
 	}
+#endif
+#ifdef CONFIG_MIPS_DB1550
+#define NUM_PARTITIONS            2
+	{ 
+		.name = "Db1550 NAND FS 0",
+	  	.offset = 0,
+	  	.size = 8*1024*1024 
+	},
+	{ 
+		.name = "Db1550 NAND FS 1",
+		.offset =  MTDPART_OFS_APPEND,
+ 		.size =    MTDPART_SIZ_FULL
+	}
+#endif
 };
 
 static inline void write_cmd_reg(u8 cmd)
@@ -258,13 +276,13 @@
 	/* Link the private data with the MTD structure */
 	au1550_mtd->priv = this;
 
-	/* set gpio206 high */
-	au_writel(au_readl(GPIO2_DIR) & ~(1<<6), GPIO2_DIR);
-
 	/* disable interrupts */
 	au_writel(au_readl(MEM_STNDCTL) & ~(1<<8), MEM_STNDCTL);
 
 #ifdef CONFIG_MIPS_PB1550
+	/* set gpio206 high */
+	au_writel(au_readl(GPIO2_DIR) & ~(1<<6), GPIO2_DIR);
+
 	boot_swapboot = (au_readl(MEM_STSTAT) & (0x7<<1)) | 
 		((bcsr->status >> 6)  & 0x1);
 	switch (boot_swapboot) {
@@ -275,6 +293,7 @@
 		case 0xD:
 			/* x16 NAND Flash */
 			nand_width = 0;
+			printk("Pb1550 NAND: 16-bit NAND not supported by MTD\n");
 			break;
 		case 1:
 		case 9:
@@ -289,7 +308,6 @@
 			kfree(au1550_mtd);
 			return 1;
 	}
-#endif
 
 	au_writel(0x5 | (nand_width << 22), MEM_STCFG1);
 	au_writel(NAND_TIMING, MEM_STTIME1);
@@ -302,6 +320,14 @@
 			(((NAND_PHYS_ADDR + 0x1000)-1) & (0x3fff<<18)>>18), 
 			MEM_STADDR1);
 	au_sync();
+#endif
+
+#ifdef CONFIG_MIPS_DB1550
+	au_writel(0x00400005, MEM_STCFG1);
+	au_writel(0x00007774, MEM_STTIME1);
+	au_writel(0x12000FFF, MEM_STADDR1);
+	au_sync();
+#endif
 
 	p_nand = (volatile struct nand_regs *)ioremap(NAND_PHYS_ADDR, 0x1000);
 
@@ -353,9 +379,6 @@
 
 	/* Unregister the device */
 	del_mtd_device (au1550_mtd);
-
-	/* Free internal data buffer */
-	kfree (this->data_buf);
 
 	/* Free the MTD device structure */
 	kfree (au1550_mtd);