mtd/drivers/mtd/nand au1550nd.c,1.5,1.6
gleixner at infradead.org
gleixner at infradead.org
Fri Aug 27 10:21:31 EDT 2004
Update of /home/cvs/mtd/drivers/mtd/nand
In directory phoenix.infradead.org:/tmp/cvs-serv31708
Modified Files:
au1550nd.c
Log Message:
fix and cleanup driver
Index: au1550nd.c
===================================================================
RCS file: /home/cvs/mtd/drivers/mtd/nand/au1550nd.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -r1.5 -r1.6
--- au1550nd.c 17 May 2004 07:19:35 -0000 1.5
+++ au1550nd.c 27 Aug 2004 14:21:28 -0000 1.6
@@ -32,11 +32,7 @@
*/
static struct mtd_info *au1550_mtd = NULL;
static volatile u32 p_nand;
-static int nand_width = 1; /* default, only x8 supported for now */
-
-/* Internal buffers. Page buffer and oob buffer for one block*/
-static u_char data_buf[512 + 16];
-static u_char oob_buf[16 * 32];
+static int nand_width = 1; /* default x8*/
/*
* Define partitions for flash device
@@ -70,183 +66,39 @@
#endif
};
-static inline void write_cmd_reg(u8 cmd)
-{
- if (nand_width)
- *((volatile u8 *)(p_nand + MEM_STNAND_CMD)) = cmd;
- else
- *((volatile u16 *)(p_nand + MEM_STNAND_CMD)) = cmd;
- au_sync();
-}
-
-static inline void write_addr_reg(u8 addr)
-{
- if (nand_width)
- *((volatile u8 *)(p_nand + MEM_STNAND_ADDR)) = addr;
- else
- *((volatile u16 *)(p_nand + MEM_STNAND_ADDR)) = addr;
- au_sync();
-}
-
-static inline void write_data_reg(u8 data)
-{
- if (nand_width)
- *((volatile u8 *)(p_nand + MEM_STNAND_DATA)) = data;
- else
- *((volatile u16 *)(p_nand + MEM_STNAND_DATA)) = data;
- au_sync();
-}
-
-static inline u32 read_data_reg(void)
-{
- u32 data;
- if (nand_width) {
- data = *((volatile u8 *)(p_nand + MEM_STNAND_DATA));
- au_sync();
- }
- else {
- data = *((volatile u16 *)(p_nand + MEM_STNAND_DATA));
- au_sync();
- }
- return data;
-}
-
void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
{
-}
-
-int au1550_device_ready(struct mtd_info *mtd)
-{
- int ready;
- ready = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
- return ready;
-}
-
-static u_char au1550_nand_read_byte(struct mtd_info *mtd)
-{
- u_char ret;
- ret = read_data_reg();
- return ret;
-}
-
-static void au1550_nand_write_byte(struct mtd_info *mtd, u_char byte)
-{
- write_data_reg((u8)byte);
-}
-
-static void
-au1550_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- int i;
-
- for (i=0; i<len; i++)
- write_data_reg(buf[i]);
-}
-
-static void
-au1550_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
-{
- int i;
+ register struct nand_chip *this = mtd->priv;
- for (i=0; i<len; i++)
- buf[i] = (u_char)read_data_reg();
-}
+ switch(cmd){
-static int
-au1550_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- int i;
+ case NAND_CTL_SETCLE: this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
+ case NAND_CTL_CLRCLE: this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
- for (i=0; i<len; i++)
- if (buf[i] != (u_char)read_data_reg())
- return -EFAULT;
+ case NAND_CTL_SETALE: this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
+ case NAND_CTL_CLRALE: this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
- return 0;
-}
-
-static void au1550_nand_select_chip(struct mtd_info *mtd, int chip)
-{
- switch(chip) {
- case -1:
- /* deassert chip enable */
- au_writel(au_readl(MEM_STNDCTL) & ~0x20 , MEM_STNDCTL);
- break;
- case 0:
+ case NAND_CTL_SETNCE:
/* assert (force assert) chip enable */
au_writel(au_readl(MEM_STNDCTL) | 0x20 , MEM_STNDCTL);
break;
- default:
- BUG();
- }
-}
-
-static void au1550_nand_command (struct mtd_info *mtd, unsigned command,
- int column, int page_addr)
-{
- register struct nand_chip *this = mtd->priv;
-
- /*
- * Write out the command to the device.
- */
- if (command == NAND_CMD_SEQIN) {
- int readcmd;
-
- if (column >= mtd->oobblock) {
- /* OOB area */
- column -= mtd->oobblock;
- readcmd = NAND_CMD_READOOB;
- } else if (column < 256) {
- /* First 256 bytes --> READ0 */
- readcmd = NAND_CMD_READ0;
- } else {
- column -= 256;
- readcmd = NAND_CMD_READ1;
- }
- write_cmd_reg(readcmd);
- }
- write_cmd_reg(command);
-
- if (column != -1 || page_addr != -1) {
-
- /* Serially input address */
- if (column != -1)
- write_addr_reg(column);
- if (page_addr != -1) {
- write_addr_reg((unsigned char) (page_addr & 0xff));
- write_addr_reg(((page_addr >> 8) & 0xff));
- /* One more address cycle for higher density devices */
- if (mtd->size & 0x0c000000)
- write_addr_reg((unsigned char) ((page_addr >> 16) & 0x0f));
- }
- }
-
- switch (command) {
-
- case NAND_CMD_PAGEPROG:
- case NAND_CMD_ERASE1:
- case NAND_CMD_ERASE2:
- case NAND_CMD_SEQIN:
- case NAND_CMD_STATUS:
+ case NAND_CTL_CLRNCE:
+ /* deassert chip enable */
+ au_writel(au_readl(MEM_STNDCTL) & ~0x20 , MEM_STNDCTL);
break;
-
- case NAND_CMD_RESET:
- if (this->dev_ready)
- break;
- udelay(this->chip_delay);
- write_cmd_reg(NAND_CMD_STATUS);
- while ( !(read_data_reg() & 0x40));
- return;
-
- /* This applies to read commands */
- default:
- udelay (this->chip_delay);
}
+
+ this->IO_ADDR_R = this->IO_ADDR_W;
- /* wait until command is processed */
- while (!this->dev_ready(mtd));
+ /* Drain the io/pipeline */
+ au_sync();
}
+int au1550_device_ready(struct mtd_info *mtd)
+{
+ return (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
+}
/*
* Main initialization routine
@@ -256,6 +108,7 @@
struct nand_chip *this;
u16 boot_swapboot = 0; /* default value */
u32 mem_time;
+ int retval;
/* Allocate memory for MTD device structure and private data */
au1550_mtd = kmalloc (sizeof(struct mtd_info) +
@@ -295,7 +148,6 @@
case 0xD:
/* x16 NAND Flash */
nand_width = 0;
- printk("Pb1550 NAND: 16-bit NAND not supported by MTD\n");
break;
case 1:
case 9:
@@ -307,8 +159,8 @@
break;
default:
printk("Pb1550 NAND: bad boot:swap\n");
- kfree(au1550_mtd);
- return 1;
+ retval = -EINVAL;
+ goto outmem;
}
/* Configure RCE1 - should be done by YAMON */
@@ -326,8 +178,13 @@
#endif
#ifdef CONFIG_MIPS_DB1550
- /* Configure RCE1 - should be done by YAMON */
- au_writel(0x00400005, MEM_STCFG1);
+ /* Configure RCE1 - should be done by YAMON
+ * tglx: stcfg1 was set to 0x00400005. I changed
+ * this as it does not work with all chips.
+ * someone should look into the correct timing
+ * values, as bit 8 does a clock / 4 prescale
+ */
+ au_writel(0x00400105, MEM_STCFG1);
au_writel(0x00007774, MEM_STTIME1);
au_writel(0x12000FFF, MEM_STADDR1);
#endif
@@ -339,30 +196,30 @@
this->dev_ready = au1550_device_ready;
/* 30 us command delay time */
this->chip_delay = 30;
-
- this->cmdfunc = au1550_nand_command;
- this->select_chip = au1550_nand_select_chip;
- this->write_byte = au1550_nand_write_byte;
- this->read_byte = au1550_nand_read_byte;
- this->write_buf = au1550_nand_write_buf;
- this->read_buf = au1550_nand_read_buf;
- this->verify_buf = au1550_nand_verify_buf;
this->eccmode = NAND_ECC_SOFT;
- /* Set internal data buffer */
- this->data_buf = data_buf;
- this->oob_buf = oob_buf;
+ this->options = NAND_NO_AUTOINCR;
+
+ if (!nand_width)
+ this->options |= NAND_BUSWIDTH_16;
/* Scan to find existence of the device */
if (nand_scan (au1550_mtd, 1)) {
- kfree (au1550_mtd);
- return -ENXIO;
+ retval = -ENXIO;
+ goto outio;
}
/* Register the partitions */
add_mtd_partitions(au1550_mtd, partition_info, NUM_PARTITIONS);
return 0;
+
+ outio:
+ iounmap ((void *)p_nand);
+
+ outmem:
+ kfree (au1550_mtd);
+ return retval;
}
module_init(au1550_init);
@@ -375,16 +232,14 @@
{
struct nand_chip *this = (struct nand_chip *) &au1550_mtd[1];
- iounmap ((void *)p_nand);
-
- /* Unregister partitions */
- del_mtd_partitions(au1550_mtd);
-
- /* Unregister the device */
- del_mtd_device (au1550_mtd);
+ /* Release resources, unregister device */
+ nand_release (au1550_mtd);
/* Free the MTD device structure */
kfree (au1550_mtd);
+
+ /* Unmap */
+ iounmap ((void *)p_nand);
}
module_exit(au1550_cleanup);
#endif
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