mtd/drivers/mtd/nand nand.c,1.45,1.46

[gleixner at infradead.org]

Update of /home/cvs/mtd/drivers/mtd/nand
In directory phoenix.infradead.org:/tmp/cvs-serv23440

Modified Files:
	nand.c 
Log Message:
include compatmac.h and fix write_verify

Index: nand.c
===================================================================
RCS file: /home/cvs/mtd/drivers/mtd/nand/nand.c,v
retrieving revision 1.45
retrieving revision 1.46
diff -u -r1.45 -r1.46
--- nand.c	20 May 2003 21:01:30 -0000	1.45
+++ nand.c	4 Jun 2003 17:10:36 -0000	1.46
@@ -124,7 +124,13 @@
  +		a structure, which will be supplied by a filesystem driver
  *		If NULL is given, then the defaults (none or defaults
  *		supplied by ioctl (MEMSETOOBSEL) are used.
- *		For partitions the partition defaults are used (mtdpart.c)		
+ *		For partitions the partition defaults are used (mtdpart.c)
+ *
+ *  06-04-2003  tglx: fix compile errors and fix write verify problem for
+ *		some chips, which need either a delay between the readback
+ *		and the next write command or have the CE removed. The
+ *		CE disable/enable is much faster than a 20us delay and
+ *		it should work on all available chips.
  *	
  * $Id$
  *
@@ -141,6 +147,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/compatmac.h>
 #include <linux/interrupt.h>
 #include <asm/io.h>
 
@@ -510,6 +517,13 @@
 			}
 		}
 	}
+	/* 
+	 * Terminate the read command. This is faster than sending a reset command or 
+	 * applying a 20us delay before issuing the next programm sequence.
+	 * This is not a problem for all chips, but I have found a bunch of them.
+	 */
+	nand_deselect();
+	nand_select();
 #endif
 	return 0;
 }