mtd/drivers/mtd/maps scb2_flash.c,1.1,1.2

[David Woodhouse]

Update of /home/cvs/mtd/drivers/mtd/maps
In directory phoenix.infradead.org:/tmp/cvs-serv21655

Modified Files:
	scb2_flash.c 
Log Message:
Pedantry.


Index: scb2_flash.c
===================================================================
RCS file: /home/cvs/mtd/drivers/mtd/maps/scb2_flash.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -r1.1 -r1.2
--- scb2_flash.c	23 Sep 2002 18:25:52 -0000	1.1
+++ scb2_flash.c	24 Jan 2003 13:09:56 -0000	1.2
@@ -10,20 +10,20 @@
  * Hopefully, Intel has not introducted too many unaccounted variables in the
  * making of this board.
  *
- * The BIOS marks it's own memory region as 'reserved' in the e820 map.  We
+ * The BIOS marks its own memory region as 'reserved' in the e820 map.  We
  * try to request it here, but if it fails, we carry on anyway.
  *
  * This is how the chip is attached, so said the schematic:
- * * a 4 MB (32 Mb) 16 bit chip
- * * a 1 MB memory region
+ * * a 4 MiB (32 Mb) 16 bit chip
+ * * a 1 MiB memory region
  * * A20 and A21 pulled up
  * * D8-D15 ignored
  * What this means is that, while we are addressing bytes linearly, we are
  * really addressing words, and discarding the other byte.  This means that
- * the chip MUST BE at least 2 MB.  This also means that every block is
+ * the chip MUST BE at least 2 MiB.  This also means that every block is
  * actually half as big as the chip reports.  It also means that accesses of
  * logical address 0 hit higher-address sections of the chip, not physical 0.
- * One can only hope that these 4MB x16 chips were a lot cheaper than 1MB x8
+ * One can only hope that these 4MiB x16 chips were a lot cheaper than 1MiB x8
  * chips.
  *
  * This driver assumes the chip is not write-protected by an external signal.