From b2c29ea45d5df714e94bb278d53daafe9274f596 Mon Sep 17 00:00:00 2001 From: Kristian Evensen Date: Sun, 29 Apr 2018 17:07:36 +0200 Subject: [PATCH] U7623 4.14 patch --- .../mediatek/base-files/etc/board.d/02_network | 3 +- .../mediatek/base-files/lib/upgrade/platform.sh | 3 +- target/linux/mediatek/image/32.mk | 2 + .../mediatek/patches-4.14/0065-u7623-dts.patch | 676 +++++++++++++++++++++ 4 files changed, 682 insertions(+), 2 deletions(-) create mode 100644 target/linux/mediatek/patches-4.14/0065-u7623-dts.patch diff --git a/target/linux/mediatek/base-files/etc/board.d/02_network b/target/linux/mediatek/base-files/etc/board.d/02_network index 8015cf3cc2..39d9ca8cc5 100755 --- a/target/linux/mediatek/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/base-files/etc/board.d/02_network @@ -13,7 +13,8 @@ mediatek_setup_interfaces() ucidef_set_interface_lan "lan0 lan1 lan2 lan3" ucidef_set_interface_wan eth1 ;; - 'bananapi,bpi-r2') + 'bananapi,bpi-r2'|\ + 'unielec,u7623') ucidef_set_interface_lan "lan0 lan1 lan2 lan3" ucidef_set_interface_wan wan ;; diff --git a/target/linux/mediatek/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/base-files/lib/upgrade/platform.sh index 0429ca8b89..de78193f37 100755 --- a/target/linux/mediatek/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/base-files/lib/upgrade/platform.sh @@ -29,7 +29,8 @@ platform_check_image() { case "$board" in bananapi,bpi-r2 |\ - mediatek,mt7623a-rfb-emmc) + mediatek,mt7623a-rfb-emmc |\ + unielec,u7623) local kernel_length=`(tar xf $tar_file sysupgrade-$board/kernel -O | wc -c) 2> /dev/null` local rootfs_length=`(tar xf $tar_file sysupgrade-$board/root -O | wc -c) 2> /dev/null` ;; diff --git a/target/linux/mediatek/image/32.mk b/target/linux/mediatek/image/32.mk index 7b7e303124..83127592ed 100644 --- a/target/linux/mediatek/image/32.mk +++ b/target/linux/mediatek/image/32.mk @@ -22,6 +22,7 @@ endef COMPAT_BPI-R2:=bananapi,bpi-r2 COMPAT_EMMC:=mediatek,mt7623a-rfb-emmc +COMPAT_U7623:=unielec,u7623 define Image/Build/squashfs $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) @@ -29,4 +30,5 @@ define Image/Build/squashfs $(call Image/Build/SysupgradeCombined,mt7623n-bananapi-bpi-r2,squashfs,$$(COMPAT_BPI-R2)) $(call Image/Build/SysupgradeCombined,mt7623a-rfb-emmc,squashfs,$$(COMPAT_EMMC)) + $(call Image/Build/SysupgradeCombined,mt7623a-unielec-u7623,squashfs,$$(COMPAT_U7623)) endef diff --git a/target/linux/mediatek/patches-4.14/0065-u7623-dts.patch b/target/linux/mediatek/patches-4.14/0065-u7623-dts.patch new file mode 100644 index 0000000000..4368f7ba2e --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0065-u7623-dts.patch @@ -0,0 +1,676 @@ +From 8b580250d31b679f9e3a71f5f9dc2edd883b0a34 Mon Sep 17 00:00:00 2001 +From: Kristian Evensen +Date: Sun, 29 Apr 2018 17:01:58 +0200 +Subject: [PATCH] Add U7623 DTS + +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/mt7623.dtsi | 104 ++++++ + arch/arm/boot/dts/mt7623a-unielec-u7623.dts | 528 ++++++++++++++++++++++++++++ + 3 files changed, 633 insertions(+) + create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623.dts + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 3fec84fa0..3fdda8427 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -1062,6 +1062,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt6589-aquaris5.dtb \ + mt6592-evb.dtb \ + mt7623a-rfb-emmc.dtb \ ++ mt7623a-unielec-u7623.dtb \ + mt7623n-rfb-nand.dtb \ + mt7623n-bananapi-bpi-r2.dtb \ + mt8127-moose.dtb \ +diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi +index 09798f37a..a027a4975 100644 +--- a/arch/arm/boot/dts/mt7623.dtsi ++++ b/arch/arm/boot/dts/mt7623.dtsi +@@ -670,6 +670,110 @@ + #reset-cells = <1>; + }; + ++ pcie: pcie@1a140000 { ++ compatible = "mediatek,mt7623-pcie"; ++ device_type = "pci"; ++ reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ ++ <0 0x1a142000 0 0x1000>, /* Port0 registers */ ++ <0 0x1a143000 0 0x1000>, /* Port1 registers */ ++ <0 0x1a144000 0 0x1000>; /* Port2 registers */ ++ reg-names = "subsys", "port0", "port1", "port2"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0xf800 0 0 0>; ++ interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, ++ <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, ++ <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&topckgen CLK_TOP_ETHIF_SEL>, ++ <&hifsys CLK_HIFSYS_PCIE0>, ++ <&hifsys CLK_HIFSYS_PCIE1>, ++ <&hifsys CLK_HIFSYS_PCIE2>; ++ clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; ++ resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, ++ <&hifsys MT2701_HIFSYS_PCIE1_RST>, ++ <&hifsys MT2701_HIFSYS_PCIE2_RST>; ++ reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; ++ phys = <&pcie0_port PHY_TYPE_PCIE>, ++ <&pcie1_port PHY_TYPE_PCIE>, ++ <&u3port1 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; ++ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; ++ bus-range = <0x00 0xff>; ++ status = "disabled"; ++ ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 ++ 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; ++ ++ pcie@0,0 { ++ reg = <0x0000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; ++ ranges; ++ num-lanes = <1>; ++ status = "disabled"; ++ }; ++ pcie@1,0 { ++ reg = <0x0800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; ++ ranges; ++ num-lanes = <1>; ++ status = "disabled"; ++ }; ++ ++ pcie@2,0 { ++ reg = <0x1000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; ++ ranges; ++ num-lanes = <1>; ++ status = "disabled"; ++ }; ++ }; ++ ++ pcie0_phy: pcie-phy@1a149000 { ++ compatible = "mediatek,generic-tphy-v1"; ++ reg = <0 0x1a149000 0 0x0700>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ pcie0_port: pcie-phy@1a149900 { ++ reg = <0 0x1a149900 0 0x0700>; ++ clocks = <&clk26m>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ status = "okay"; ++ }; ++ }; ++ ++ pcie1_phy: pcie-phy@1a14a000 { ++ compatible = "mediatek,generic-tphy-v1"; ++ reg = <0 0x1a14a000 0 0x0700>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ pcie1_port: pcie-phy@1a14a900 { ++ reg = <0 0x1a14a900 0 0x0700>; ++ clocks = <&clk26m>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ status = "okay"; ++ }; ++ }; ++ + usb1: usb@1a1c0000 { + compatible = "mediatek,mt7623-xhci", + "mediatek,mt8173-xhci"; +diff --git a/arch/arm/boot/dts/mt7623a-unielec-u7623.dts b/arch/arm/boot/dts/mt7623a-unielec-u7623.dts +new file mode 100644 +index 000000000..066b25bb4 +--- /dev/null ++++ b/arch/arm/boot/dts/mt7623a-unielec-u7623.dts +@@ -0,0 +1,528 @@ ++/* ++ * Copyright 2017 Sean Wang ++ * ++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ */ ++ ++/dts-v1/; ++#include ++#include "mt7623.dtsi" ++#include "mt6323.dtsi" ++ ++/ { ++ model = "Unielec U7623 512MB RAM/8GB eMMC"; ++ compatible = "unielec,u7623", "mediatek,mt7623"; ++ ++ aliases { ++ serial2 = &uart2; ++ }; ++ ++ chosen { ++ bootargs = "earlyprintk block2mtd.block2mtd=/dev/mmcblk0,65536,eMMC,5 mtdparts=eMMC:256k(mbr)ro,512k(uboot)ro,256k(config)ro,256k(factory)ro,32M(kernel),32M(recovery),1024M(rootfs),6144M(userdata),-(bmtpool) root=/dev/mtdblock6 rootfstype=squashfs,jffs2"; ++ stdout-path = "serial2:115200n8"; ++ }; ++ ++ memory { ++ reg = <0 0x80000000 0 0x10000000>; ++ }; ++ ++ cpus { ++ cpu@0 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ ++ cpu@1 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ ++ cpu@2 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ ++ cpu@3 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_5v: regulator-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ memory@80000000 { ++ reg = <0 0x80000000 0 0x40000000>; ++ }; ++ ++ mt7530: switch@0 { ++ compatible = "mediatek,mt7530"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++}; ++ ++&crypto { ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ ++ gmac0: mac@0 { ++ compatible = "mediatek,eth-mac"; ++ reg = <0>; ++ phy-mode = "trgmii"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ pause; ++ }; ++ }; ++ ++ mdio: mdio-bus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ phy5: ethernet-phy@5 { ++ reg = <5>; ++ phy-mode = "rgmii-rxid"; ++ }; ++ }; ++}; ++ ++&mt7530 { ++ compatible = "mediatek,mt7530"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ pinctrl-names = "default"; ++ mediatek,mcm; ++ resets = <ðsys 2>; ++ reset-names = "mcm"; ++ core-supply = <&mt6323_vpa_reg>; ++ io-supply = <&mt6323_vemc3v3_reg>; ++ ++ dsa,mii-bus = <&mdio>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ port@0 { ++ reg = <0>; ++ label = "lan0"; ++ cpu = <&cpu_port0>; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ label = "lan1"; ++ cpu = <&cpu_port0>; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ label = "lan2"; ++ cpu = <&cpu_port0>; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ label = "lan3"; ++ cpu = <&cpu_port0>; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ label = "wan"; ++ cpu = <&cpu_port0>; ++ }; ++ ++ cpu_port0: port@6 { ++ reg = <6>; ++ label = "cpu"; ++ ethernet = <&gmac0>; ++ phy-mode = "trgmii"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins_a>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins_b>; ++ status = "okay"; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins_b>; ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ pinctrl-1 = <&mmc0_pins_uhs>; ++ status = "okay"; ++ bus-width = <8>; ++ max-frequency = <50000000>; ++ cap-mmc-highspeed; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_1p8v>; ++ non-removable; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc1_pins_default>; ++ pinctrl-1 = <&mmc1_pins_uhs>; ++ status = "okay"; ++ bus-width = <4>; ++ max-frequency = <50000000>; ++ cap-sd-highspeed; ++ cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_3p3v>; ++}; ++ ++&pio { ++ cir_pins_a:cir@0 { ++ pins_cir { ++ pinmux = ; ++ bias-disable; ++ }; ++ }; ++ ++ i2c0_pins_a: i2c@0 { ++ pins_i2c0 { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ }; ++ ++ i2c1_pins_b: i2c@1 { ++ pin_i2c1 { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ }; ++ ++ i2c2_pins_b: i2c@2 { ++ pin_i2c2 { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ }; ++ ++ i2s0_pins_a: i2s@0 { ++ pin_i2s0 { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ drive-strength = ; ++ bias-pull-down; ++ }; ++ }; ++ ++ i2s1_pins_a: i2s@1 { ++ pin_i2s1 { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ drive-strength = ; ++ bias-pull-down; ++ }; ++ }; ++ ++ mmc0_pins_default: mmc0default { ++ pins_cmd_dat { ++ pinmux = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ input-enable; ++ bias-pull-up; ++ }; ++ ++ pins_clk { ++ pinmux = ; ++ bias-pull-down; ++ }; ++ ++ pins_rst { ++ pinmux = ; ++ bias-pull-up; ++ }; ++ }; ++ ++ mmc0_pins_uhs: mmc0 { ++ pins_cmd_dat { ++ pinmux = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ input-enable; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ pins_clk { ++ pinmux = ; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; ++ ++ pins_rst { ++ pinmux = ; ++ bias-pull-up; ++ }; ++ }; ++ ++ mmc1_pins_default: mmc1default { ++ pins_cmd_dat { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ input-enable; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ pins_clk { ++ pinmux = ; ++ bias-pull-down; ++ drive-strength = ; ++ }; ++ ++ pins_wp { ++ pinmux = ; ++ input-enable; ++ bias-pull-up; ++ }; ++ ++ pins_insert { ++ pinmux = ; ++ bias-pull-up; ++ }; ++ }; ++ ++ mmc1_pins_uhs: mmc1 { ++ pins_cmd_dat { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ input-enable; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ pins_clk { ++ pinmux = ; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; ++ }; ++ ++ pwm_pins_a: pwm@0 { ++ pins_pwm { ++ pinmux = , ++ , ++ , ++ , ++ ; ++ }; ++ }; ++ ++ spi0_pins_a: spi@0 { ++ pins_spi { ++ pinmux = , ++ , ++ , ++ ; ++ bias-disable; ++ }; ++ }; ++ ++ spi1_pins_a: spi@1 { ++ pins_spi { ++ pinmux = , ++ , ++ , ++ ; ++ bias-disable; ++ }; ++ }; ++ ++ uart0_pins_a: uart@0 { ++ pins_dat { ++ pinmux = , ++ ; ++ }; ++ }; ++ ++ uart1_pins_a: uart@1 { ++ pins_dat { ++ pinmux = , ++ ; ++ }; ++ }; ++ ++ uart2_pins_b: uart@2 { ++ pins_dat { ++ pinmux = , ++ ; ++ }; ++ }; ++ ++ pcie_default: pcie_pin_default { ++ pins_cmd_dat { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins_a>; ++ status = "okay"; ++}; ++ ++&pwrap { ++ mt6323 { ++ mt6323led: led { ++ compatible = "mediatek,mt6323-led"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ led@0 { ++ reg = <0>; ++ label = "led0"; ++ default-state = "off"; ++ }; ++ ++ led@1 { ++ reg = <1>; ++ label = "led1"; ++ default-state = "off"; ++ }; ++ ++ led@2 { ++ reg = <2>; ++ label = "led2"; ++ default-state = "off"; ++ }; ++ }; ++ }; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins_a>; ++ status = "okay"; ++}; ++ ++&spi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins_a>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins_b>; ++ status = "okay"; ++}; ++ ++&usb1 { ++ vusb33-supply = <®_3p3v>; ++ vbus-supply = <®_3p3v>; ++ status = "okay"; ++}; ++ ++&u3phy1 { ++ status = "okay"; ++}; ++ ++/*&usb2 { ++ vusb33-supply = <®_3p3v>; ++ vbus-supply = <®_3p3v>; ++ status = "okay"; ++}; ++ ++&u3phy2 { ++ status = "okay"; ++};*/ ++ ++&pcie { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_default>; ++ status = "okay"; ++ ++ pcie@1,0 { ++ status = "okay"; ++ }; ++ ++/* pcie@2,0 { ++ status = "okay"; ++ };*/ ++}; ++ ++&pcie1_phy { ++ status = "okay"; ++}; +-- +2.14.1 + -- 2.14.1