[PATCH 2/2] clk: mediatek: mt6795: fix the FHCTL DDS mask width

[AngeloGioacchino Del Regno]

On 9/25/26 15:13, Jerome Brunet wrote:
> On lun. 14 sept. 2026 at 10:16, AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com> wrote:
> 
>> On 9/12/26 08:40, Ryan Brue wrote:
>>> All eight PLLs in mt6795's pllfhs[] have pcwbits = 21, so the FHCTL DDS
>>> field is bits 20:0, but _FH() declares .dds_mask = GENMASK(21, 0). As on
>>> MT8173, new_dds from mtk_pll_calc_values() is always 21-bit, so admitting
>>> bit 21 of FHCTL_MON into the poll in hopping_hw_flow() can only make it
>>> time out. The same mask feeds the CON1 write-back and fhctl_set_ssc_regs().
>>>
>>> Unlike MT8173 this path has a user: mt6795-sony-xperia-m5.dts switches
>>> FHCTL on for mainpll, mpll and msdcpll, with SSC.
>>>
>>> Found by inspection while fixing MT8173. I have no MT6795 hardware, so
>>> this one is untested.
>>>
>>> Fixes: f222a1baec5f ("clk: mediatek: mt6795: Add support for frequency hopping through FHCTL")
>>> Assisted-by: LLM
>>> Signed-off-by: Ryan Brue <ryanbrue.dev at gmail.com>
>>
>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> 
> Hey Angelo,
> 
> Will you collect the MTK changes yourself and send us a PR or should
> we collect the changes you've reviewed for this cycle ?
> 

Please collect the changes that I've reviewed for this cycle... I'll start
sending PRs from the next one.

Thanks!

Cheers,
Angelo