[PATCH 2/2] phy: mediatek: phy-mtk-hdmi-mt8195: Fix TMDS clk bit ratio setting

[AngeloGioacchino Del Regno]

On 9/9/26 17:06, Manivannan Sadhasivam wrote:
> On Wed, Jul 01, 2026 at 02:19:36PM +0200, AngeloGioacchino Del Regno wrote:
>> The comment in the mtk_phy_tmds_clk_ratio() function clearly and
>> correctly explains that the TMDS ratio has to be 1/10 for data
>> rates under 3.4Gbps, and 1/40 over that.
>>
>> Unfortunately though, the TXC_DIV register setting was wrong, as
>> in value 3 means to divide by 8 and, in order to achieve the in
>> spec 1/40 (tmds) data rate, this has to divide by 4 instead!
>> In order to achieve the correct 1/40 (tmds) data rate, this has
> 
> This statement is cut-off!
> 

Oh oops. It's just a forgotten line that has to be removed....

Should I resend or can you simply remove the line
"In order to achieve the correct 1/40 (tmds) data rate, this has"
while applying?

Thanks,
Angelo

>>
>> Add definitions for the TXC_DIV register values clearly explaining
>> the meanings (DIV2, DIV4, DIV8), and program the correct, DIV 4,
>> value to the register in mtk_phy_tmds_clk_ratio().
>>
>> This fixes out of spec clocking and, with this change, SoCs using
>> the MT8195 class HDMI PHYs can now successfully be configured to
>> output 3840x2160 at 60Hz over HDMI.
>>
>> Fixes: 45810d486bb4 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> 
> With above comment addressed,
> 
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at oss.qualcomm.com>
> 
> - Mani
>