[PATCH v3 06/12] phy: phy-mtk-dp: Support set_lanes in configure and properly cleanup

[Manivannan Sadhasivam]

On Tue, Jul 07, 2026 at 05:42:39PM +0200, AngeloGioacchino Del Regno wrote:
> Add support for enabling a specifically requested number of lanes
> in the .configure() callback and disable all lanes in power off
> and reset callbacks for proper hardware cleanup.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> ---
>  drivers/phy/mediatek/phy-mtk-dp.c | 75 ++++++++++++++++++++++++++++---
>  1 file changed, 68 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
> index f6b0e83d4833..2c8bc0b37486 100644
> --- a/drivers/phy/mediatek/phy-mtk-dp.c
> +++ b/drivers/phy/mediatek/phy-mtk-dp.c
> @@ -10,6 +10,7 @@
>   *                     AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
>   */
>  
> +#include <linux/bitfield.h>
>  #include <linux/delay.h>
>  #include <linux/io.h>
>  #include <linux/mfd/syscon.h>
> @@ -50,6 +51,9 @@
>  #define DRIVING_PARAM_1_DEFAULT	0x0
>  #define DRIVING_PARAM_2_DEFAULT	0x0
>  
> +/* DP_PHYD_TX_CTL_0 */
> +#define PHYD_TX_LN_EN			GENMASK(7, 4)
> +
>  #define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT	BIT(4)
>  #define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT	(BIT(10) | BIT(12))
>  #define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT	GENMASK(20, 19)
> @@ -113,6 +117,7 @@ enum mtk_dp_phyd_dig_glb_regidx {
>  	DP_PHYD_SW_RST,
>  	DP_PHYD_BIT_RATE,
>  	DP_PHYD_AUX_RX_CTL,
> +	DP_PHYD_TX_CTL_0,
>  	DP_PHYD_GLOBAL_MAX
>  };
>  
> @@ -131,6 +136,7 @@ static const u8 mt8195_phy_dig_glb_regs[DP_PHYD_GLOBAL_MAX] = {
>  	[DP_PHYD_SW_RST] = 0x38,
>  	[DP_PHYD_BIT_RATE] = 0x3c,
>  	[DP_PHYD_AUX_RX_CTL] = 0x40,
> +	[DP_PHYD_TX_CTL_0] = 0x44,
>  };
>  
>  /**
> @@ -200,6 +206,7 @@ static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
>  	struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
>  	const struct mtk_dp_phy_pdata *pdata = dp_phy->pdata;
>  	u32 val;
> +	int i;
>  
>  	if (opts->dp.set_rate) {
>  		const u32 reg_bit_rate = pdata->regs_dig_glb[DP_PHYD_BIT_RATE];
> @@ -226,6 +233,17 @@ static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
>  		regmap_write(dp_phy->regmap, pdata->off_dig_glb + reg_bit_rate, val);
>  	}
>  
> +	if (opts->dp.set_lanes) {
> +		const u32 reg_dig_tx_ctl = pdata->regs_dig_glb[DP_PHYD_TX_CTL_0];
> +
> +		val = 0;
> +		for (i = 0; i < opts->dp.lanes; i++)
> +			val |= FIELD_PREP(PHYD_TX_LN_EN, BIT(i));
> +
> +		regmap_update_bits(dp_phy->regmap, pdata->off_dig_glb + reg_dig_tx_ctl,
> +				   PHYD_TX_LN_EN, val);
> +	}
> +
>  	regmap_update_bits(dp_phy->regmap,
>  			   pdata->off_dig_glb + pdata->regs_dig_glb[DP_PHYD_PLL_CTL_1],
>  			   TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0);
> @@ -263,31 +281,68 @@ static int mtk_dp_phy_power_on(struct phy *phy)
>  	return 0;
>  }
>  
> +static int mtk_dp_phy_disable_all_lanes(struct mtk_dp_phy *dp_phy)
> +{
> +	const struct mtk_dp_phy_pdata *pdata = dp_phy->pdata;
> +	const u8 *regs = pdata->regs_dig_glb;
> +	int ret;
> +	u32 val;
> +
> +	ret = regmap_read(dp_phy->regmap, pdata->off_dig_glb + regs[DP_PHYD_TX_CTL_0], &val);
> +	if (ret)
> +		return ret;

Same comment as previous patch.

- Mani

-- 
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