[PATCH 1/2] phy: mediatek: phy-mtk-hdmi-mt8195: Fix PLL calc divisor overflow

[Manivannan Sadhasivam]

On Wed, Jul 01, 2026 at 02:19:35PM +0200, AngeloGioacchino Del Regno wrote:
> When trying to calculate a PLL rate for target display resolutions
> above 2560x1440, 24bpp, 30Hz, the pixel clock value will be more
> than 32-bits long but the division to finally calculate the digital
> clock divider is being done with div_u64(), which expects a 32bit
> unsigned divisor.
> 
> Fix the overflow by using div64_u64() instead.
> 
> Fixes: 9d9ff3d2a4a5 ("phy: mediatek: hdmi: mt8195: fix wrong pll calculus")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at oss.qualcomm.com>

- Mani

-- 
மணிவண்ணன் சதாசிவம்