[PATCH] clk: mediatek: mt7981: fix "emmc_400m_sel" clock mux sources

[Shiji Yang]

According to the document "MT7981B Platform: Registers Part 1", the
4th clock source of "emmc_400m_sel" group is "cb_net2_d4".

Fixes: 813c3b53b55b ("clk: mediatek: add MT7981 clock support")
Signed-off-by: Shiji Yang <yangshiji66 at outlook.com>
---
 drivers/clk/mediatek/clk-mt7981-topckgen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-mt7981-topckgen.c b/drivers/clk/mediatek/clk-mt7981-topckgen.c
index e71ae8fadd5d..8df0dcfe30c6 100644
--- a/drivers/clk/mediatek/clk-mt7981-topckgen.c
+++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
@@ -173,7 +173,7 @@ static const char * const emmc_400m_parents[] __initconst = {
 	"cb_cksq_40m",
 	"cb_net2_d2",
 	"cb_mm_d2",
-	"cb_net2_d2"
+	"cb_net2_d4"
 };
 
 static const char * const csw_f26m_parents[] __initconst = {
-- 
2.53.0