[PATCH v2 04/12] pinctrl: airoha: an7581: fix muxing of pcie_reset pins
Mikhail Kshevetskiy
mikhail.kshevetskiy at iopsys.eu
Mon Jun 15 21:19:31 PDT 2026
In the an7581 case
* gpio44 and pcie_reset0 shares pin 57,
* gpio45 and pcie_reset1 shares pin 58,
* gpio46 and pcie_reset2 shares pin 59.
but current driver treat them as different pins. This is wrong.
Also current an7581 pinmux implementation have following issues:
* pins 57--59 can't be set as pcie_reset, current pcie_reset code will
sets pins to gpio mode instead.
* there is no proper way to set pins 57--59 to gpio mode.
* pins 57--59 can't be actually set as pwm pins. These pins must be
muxed to gpio mode as well.
This patch fixes above issues.
Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy at iopsys.eu>
---
drivers/pinctrl/airoha/pinctrl-airoha.c | 89 ++++++++++++++++++++-----
1 file changed, 74 insertions(+), 15 deletions(-)
diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index cad56ac3c061..97b6d46ccb2b 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -466,12 +466,9 @@ static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
PINCTRL_PIN(54, "gpio41"),
PINCTRL_PIN(55, "gpio42"),
PINCTRL_PIN(56, "gpio43"),
- PINCTRL_PIN(57, "gpio44"),
- PINCTRL_PIN(58, "gpio45"),
- PINCTRL_PIN(59, "gpio46"),
- PINCTRL_PIN(61, "pcie_reset0"),
- PINCTRL_PIN(62, "pcie_reset1"),
- PINCTRL_PIN(63, "pcie_reset2"),
+ PINCTRL_PIN(57, "pcie_reset0"),
+ PINCTRL_PIN(58, "pcie_reset1"),
+ PINCTRL_PIN(59, "pcie_reset2"),
};
static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
@@ -554,9 +551,9 @@ static const int en7581_gpio43_pins[] = { 56 };
static const int en7581_gpio44_pins[] = { 57 };
static const int en7581_gpio45_pins[] = { 58 };
static const int en7581_gpio46_pins[] = { 59 };
-static const int en7581_pcie_reset0_pins[] = { 61 };
-static const int en7581_pcie_reset1_pins[] = { 62 };
-static const int en7581_pcie_reset2_pins[] = { 63 };
+static const int en7581_pcie_reset0_pins[] = { 57 };
+static const int en7581_pcie_reset1_pins[] = { 58 };
+static const int en7581_pcie_reset2_pins[] = { 59 };
static const struct pingroup en7581_pinctrl_groups[] = {
PINCTRL_PIN_GROUP("pon", en7581_pon),
@@ -882,6 +879,7 @@ static const char *const an7583_pcm_spi_groups[] = { "pcm_spi",
static const char *const i2s_groups[] = { "i2s" };
static const char *const emmc_groups[] = { "emmc" };
static const char *const pnand_groups[] = { "pnand" };
+static const char *const gpio_groups[] = { "gpio44", "gpio45", "gpio46" };
static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
"pcie_reset2" };
static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
@@ -1405,6 +1403,45 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = {
},
};
+#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ 0 \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+static const struct airoha_pinctrl_func_group gpio_func_group[] = {
+ AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET2_MASK),
+};
+
static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
{
.name = "pcie_reset0",
@@ -1412,7 +1449,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
AIROHA_FUNC_MUX,
REG_GPIO_PON_MODE,
GPIO_PCIE_RESET0_MASK,
- GPIO_PCIE_RESET0_MASK
+ 0
},
.regmap_size = 1,
}, {
@@ -1421,7 +1458,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
AIROHA_FUNC_MUX,
REG_GPIO_PON_MODE,
GPIO_PCIE_RESET1_MASK,
- GPIO_PCIE_RESET1_MASK
+ 0
},
.regmap_size = 1,
}, {
@@ -1430,7 +1467,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
AIROHA_FUNC_MUX,
REG_GPIO_PON_MODE,
GPIO_PCIE_RESET2_MASK,
- GPIO_PCIE_RESET2_MASK
+ 0
},
.regmap_size = 1,
},
@@ -1483,6 +1520,24 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
.regmap_size = 1, \
} \
+#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
static const struct airoha_pinctrl_func_group pwm_func_group[] = {
AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
@@ -1524,9 +1579,12 @@ static const struct airoha_pinctrl_func_group pwm_func_group[] = {
AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET2_MASK),
};
static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
@@ -1803,6 +1861,7 @@ static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("i2s", i2s),
PINCTRL_FUNC_DESC("emmc", emmc),
PINCTRL_FUNC_DESC("pnand", pnand),
+ PINCTRL_FUNC_DESC("gpio", gpio),
PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
PINCTRL_FUNC_DESC("pwm", pwm),
PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
--
2.53.0
More information about the Linux-mediatek
mailing list