[PATCH v7 17/34] pinctrl: airoha: fix edge-triggered interrupts handling

[Lorenzo Bianconi]

> Edge-triggered interrupts are handled incorrectly because of
>  * no irq_ack() handler was defined,
>  * no handle_level_irq() handler was used,
> 
> This patch probably fixes an issue
> 
> Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy at iopsys.eu>

Acked-by: Lorenzo Bianconi <lorenzo at kernel.org>

> ---
>  drivers/pinctrl/airoha/pinctrl-airoha.c | 38 +++++++++++++++++++++----
>  1 file changed, 33 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index d218a1f01648b..df3a1d7c7b571 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -2613,11 +2613,28 @@ static void airoha_irq_mask(struct irq_data *data)
>  	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
>  	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
>  
> +	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
> +		return;
> +
>  	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
>  	regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);
>  	gpiochip_disable_irq(gc, irqd_to_hwirq(data));
>  }
>  
> +static void airoha_irq_ack(struct irq_data *data)
> +{
> +	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
> +	struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
> +	struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
> +	u8 offset = data->hwirq % AIROHA_PIN_BANK_SIZE;
> +	u8 index = data->hwirq / AIROHA_PIN_BANK_SIZE;
> +
> +	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
> +		return;
> +
> +	regmap_write(pinctrl->regmap, gpiochip->status[index], BIT(offset));
> +}
> +
>  static int airoha_irq_type(struct irq_data *data, unsigned int type)
>  {
>  	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
> @@ -2627,13 +2644,25 @@ static int airoha_irq_type(struct irq_data *data, unsigned int type)
>  	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
>  		return -EINVAL;
>  
> +	if (type == IRQ_TYPE_NONE) {
> +		gpiochip->irq_type[data->hwirq] = IRQ_TYPE_NONE;
> +		irq_set_handler_locked(data, handle_bad_irq);
> +
> +		return 0;
> +	}
> +
>  	if (type == IRQ_TYPE_PROBE) {
>  		if (gpiochip->irq_type[data->hwirq])
>  			return 0;
>  
> -		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
> +		type = IRQ_TYPE_EDGE_BOTH;
>  	}
> +
>  	gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK;
> +	if (type & IRQ_TYPE_EDGE_BOTH)
> +		irq_set_handler_locked(data, handle_edge_irq);
> +	else
> +		irq_set_handler_locked(data, handle_level_irq);
>  
>  	return 0;
>  }
> @@ -2658,8 +2687,7 @@ static irqreturn_t airoha_irq_handler(int irq, void *data)
>  		for_each_set_bit(irq, &status, AIROHA_PIN_BANK_SIZE) {
>  			u32 offset = irq + i * AIROHA_PIN_BANK_SIZE;
>  
> -			generic_handle_irq(irq_find_mapping(girq->domain,
> -							    offset));
> +			generic_handle_domain_irq(girq->domain, offset);
>  			regmap_write(pinctrl->regmap,
>  				     pinctrl->gpiochip.status[i], BIT(irq));
>  		}
> @@ -2673,7 +2701,7 @@ static const struct irq_chip airoha_gpio_irq_chip = {
>  	.name = "airoha-gpio-irq",
>  	.irq_unmask = airoha_irq_unmask,
>  	.irq_mask = airoha_irq_mask,
> -	.irq_mask_ack = airoha_irq_mask,
> +	.irq_ack = airoha_irq_ack,
>  	.irq_set_type = airoha_irq_type,
>  	.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
>  	GPIOCHIP_IRQ_RESOURCE_HELPERS,
> @@ -2708,7 +2736,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
>  	gc->ngpio = AIROHA_NUM_PINS;
>  
>  	girq->default_type = IRQ_TYPE_NONE;
> -	girq->handler = handle_simple_irq;
> +	girq->handler = handle_bad_irq;
>  	gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip);
>  
>  	irq = platform_get_irq(pdev, 0);
> -- 
> 2.53.0
> 
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