[PATCH v4 4/4] PCI: mediatek-gen3: Add 2-lanes mode support for Airoha AN7581

[Bjorn Helgaas]

On Thu, Jul 23, 2026 at 08:40:03PM +0200, Christian Marangi wrote:
> On Wed, Jul 22, 2026 at 12:40:10PM -0500, Bjorn Helgaas wrote:
> > On Tue, Jul 14, 2026 at 01:58:46PM +0200, Christian Marangi wrote:
> > > The Airoha AN7581 SoC supports configuring the first PCIe0 lane to 2-lanes
> > > mode (2x link) by bonding it with the second PCIe lane (PCIe1). This is
> > > done by configuring the PCIe MUX in the SCU register.
> ...

> > > -	 * Airoha EN7581 performs PCIe reset via clk callbacks since it has a
> > > -	 * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to
> > > -	 * complete the PCIe reset.
> > > +	 * Old Airoha EN7581 clock driver performed PCIe reset via
> > > +	 * clk callbacks since it has a hw issue with PCIE_PE_RSTB signal.
> > > +	 * This is now handled by dedicated PERSTOUT resets with clk
> > > +	 * driver only enabling the refclk.
> > 
> > This reference to the "old Airoha EN7581 clock driver" makes me think
> > there's a dependency between a EN7581 clock driver change and this
> > PERSTOUT change.  If so, please mention the commit SHA1 for the EN7581
> > clock driver change so they're connected and people backporting to
> > older kernels know to be careful to get both of them.
> > 
> > It sounds like this PERSTOUT change might be independent of the x2
> > configuration support.  If so, it should be done in a separate patch.
> 
> thanks for the review. The clock change can go on a separate patch but
> since the hash will change when it will get merged what should I use as
> reference? Also any hint on the tag to use or the format?

Where is the clock change?  Is it the one in this series ([PATCH v4
2/4] clk: en7523: add support for dedicated PCIe PERSTOUT reset)?

If so, perhaps this PERSTOUT change and the clk-en7523.c PERSTOUT
change could be in the same patch?  It would just require an ack from
the clk folks and then we could merge it via PCI.