[PATCH] drm/mediatek: mtk_dsi: enable hs clock during pre-enable

[AngeloGioacchino Del Regno]

On 7/15/26 14:53, Esben Haabendal wrote:
> Gary Bisson <bisson.gary at gmail.com> writes:
> 
>> Some bridges, such as the TI SN65DSI83, require the HS clock to be
>> running in order to lock its PLL during its own pre-enable function.
>>
>> Without this change, the bridge gives the following error:
>> sn65dsi83 14-002c: failed to lock PLL, ret=-110
>> sn65dsi83 14-002c: Unexpected link status 0x01
>> sn65dsi83 14-002c: reset the pipe
>>
>> Move the necessary functions from enable to pre-enable.
>>
>> Signed-off-by: Gary Bisson <bisson.gary at gmail.com>
> 
> Hi
> 
> I have run into the same problem, but in combination with another
> pipeline. I am seeing same problem with an i.MX8 using the nwl-dsi
> bridge and the dcss driver.
> 
> I have submitted a fix that adresses the problem in the ti-sn65dsi83
> driver instead. With a bit of luck, it can replace the fix proposed in
> this thread.
> 
> See https://lore.kernel.org/all/20260711-ti-sn65dsi83-fixes-v1-2-d85eb5342b98@geanix.com/
> 
> /Esben

That clarifies a lot of things.

The patch on mtk_dsi shall be reverted then.

Cheers,
Angelo