[PATCH v2 3/4] arm64: dts: mediatek: add Genio 720-EVK board
Chen-Yu Tsai
wenst at chromium.org
Tue Jul 7 23:22:01 PDT 2026
On Thu, Jul 2, 2026 at 12:36 AM Louis-Alexis Eyraud
<louisalexis.eyraud at collabora.com> wrote:
>
> Add support for MediaTek MT8189 SoC and its variants, and a devicetree
> for the basic hardware enablement of the Genio 720-EVK board, based on
> MT8391 SoC.
>
> MT8391 SoC is a variant of MT8189 SoC with a difference for the Arm
> Cortex-A78 CPU core maximum frequency (2.6 Ghz for MT8391, 3 Ghz for
> MT8189). MT8391 hardware register maps are identical to MT8189.
>
> The Genio 720-EVK board has following features:
> - MT8391 SoC
> - MT6365 PMIC
> - MT6319 Buck IC
> - MT6375 Charger IC
> - 8GB LPDDR5 RAM
> - 64GB eMMC 5.1
> - 128GB UFS
> - 20V DC Jack
> - USB Type-C Power Adapter
> - Micro SD card slot
> - Push Button x 4 (Power, Reset, Download and Home Key)
> - LED x 3 (System Power, Reset, DC-IN Power)
> - USB Type-C Connector (USB 3.2) x 2
> - USB Type-C Connector (USB 2.0) x 1
> - 3.5mm Earphone Jack x 1 (with Microphone Input)
> - 3.5mm Line Out Audio Jack x 1
> - Analog Microphone x 1
> - Digital Microphone x 2
> - Gigabit Ethernet with RJ45 connector
> - DP x 1 (Mode over USB Type-C)
> - LVDS port x 1
> - eDP port x 1
> - UART x2 with serial-to-usb converters and USB Type-C connectors
> - UART Port x 2 on Pin Header
> - M.2 Slot x 2
> - I2C Capacitive Touch Pad
> - 4-Lane DSI x 1
> - 4-Data Lane CSI x 2
> - I2S Pin header
> - 40-Pin 2.54mm Pin Header x 1
> - CAN Bus x 1 (RS232 Connector)
>
> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8189.dtsi | 920 +++++++++++++++++++++
> .../boot/dts/mediatek/mt8391-genio-720-evk.dts | 27 +
> .../boot/dts/mediatek/mt8391-genio-common.dtsi | 673 +++++++++++++++
> 4 files changed, 1621 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index a86fb313b1a9..5c75ea1ef09a 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -173,6 +173,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk-ufs.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-tungsten-smarc.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8391-genio-720-evk.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo
> diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
> new file mode 100644
> index 000000000000..272b1b34c953
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
> @@ -0,0 +1,920 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2025 MediaTek Inc.
> + *
> + * Copyright (c) 2025 Collabora Ltd.
> + * Author: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>
> + */
> +
> +#include <dt-bindings/clock/mediatek,mt8189-clk.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/power/mediatek,mt8189-power.h>
> +#include <dt-bindings/phy/phy.h>
> +
> +/ {
[...]
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
> +
> + performance: performance-controller at 108d78 {
> + compatible = "mediatek,cpufreq-hw";
> + reg = <0 0x00108d78 0 0x120>, <0 0x00108e98 0 0x120>;
> + #performance-domain-cells = <1>;
> + };
> +
> + gic: interrupt-controller at c000000 {
> + compatible = "arm,gic-v3";
> + reg = <0 0xc000000 0 0x40000>, /* distributor */
> + <0 0xc040000 0 0x200000>; /* redistributor */
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-controller;
> + #interrupt-cells = <4>;
> + #redistributor-regions = <1>;
> +
> + ppi-partitions {
> + ppi_cluster0: interrupt-partition-0 {
> + affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
> + };
> +
> + ppi_cluster1: interrupt-partition-1 {
> + affinity = <&cpu6 &cpu7>;
> + };
> + };
> + };
> +
> + apdma: dma-controller at 11300b00 {
> + compatible = "mediatek,mt8189-uart-dma", "mediatek,mt6985-uart-dma";
> + reg = <0 0x11300b00 0 0x80>,
> + <0 0x11300b80 0 0x80>,
> + <0 0x11300c00 0 0x80>,
> + <0 0x11300c80 0 0x80>,
> + <0 0x11300d00 0 0x80>,
> + <0 0x11300d80 0 0x80>,
> + <0 0x11300e00 0 0x80>,
> + <0 0x11300e80 0 0x80>;
> + interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&peri_ao CLK_PERAO_DMA_B>;
> + clock-names = "apdma";
> + dma-requests = <8>;
> + #dma-cells = <1>;
> + };
> +
> + auxadc: adc at 11019000 {
The .dtsi file's device nodes should be sorted by base address.
This file's device node order is inconsistent.
ChenYu
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