[PATCH v5 2/2] PCI: mediatek-gen3: Add 2-lanes mode support for Airoha AN7581

[Manivannan Sadhasivam]

On Thu, Aug 13, 2026 at 09:30:54PM +0200, Christian Marangi wrote:
> On Thu, Aug 13, 2026 at 12:08:20PM -0500, Bjorn Helgaas wrote:
> > On Thu, Aug 06, 2026 at 06:53:32PM +0200, Christian Marangi wrote:
> > > The Airoha AN7581 SoC supports configuring the first PCIe0 lane to 2-lanes
> > > mode (x2 link) by bonding it with the second PCIe lane (PCIe1). This is
> > > done by configuring the PCIe MUX in the SCU register.
> > > 
> > > To correctly configure PCIe0 in x2 link, define in DT the following
> > > additional properties:
> > > 
> > >   - additional reg, 'sec-pcie-mac' for the secondary PCIe.
> > >   - PERSTOUT reset for both main and secondary PCIE0, called 'perstout' and
> > >     'sec-perstout'
> > >   - 'airoha,scu' property to correctly configure the SCU register for the
> > >     PCIe MUX
> > >   - 'num-lanes' set to '2' to enable PCIe0 in x2 link
> > > 
> > > In such configuration the EQ preset are configured to the same values.
> > > 
> > > To permit correct configuration of the PCIe link, additional logic is added
> > > to assert and deassert the PERSTOUT resets. Support of these additional
> > > reset was introduced in Airoha clk driver with commit
> > > 6712f48eb3a1 ("clk: en7523: add support for dedicated PCIe PERSTOUT reset")
> > > and on backporting of this commit also the clk driver change will be
> > > needed.
> > 
> > I don't see 6712f48eb3a1 in upstream or linux-next.  Is this SHA1
> > going to valid if we merge this for v7.3?
> 
> I picked that sha1 from the git pull for the staging clk tree.
> 

Ah, I missed it. In this case the SHA should be dropped and maybe we can refer
the lore link of the patch?

- Mani

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