[PATCH 1/4] dt-bindings: clock: mediatek: Add clocks for MT8196 mfgpll

[Nicolas Frattaroli]

The clock controllers for mfgpll, mfgpll-sc0, and mfgpll-sc1 all need
CLK_TOP_MFG_EB to be on if their clock control registers are touched in
any way.

This was not known at the time this binding was written, as this
dependency only came to light when I started poking at the MFlexGraphics
hardware, where this undocumented peculiarity made itself known through
SErrors being thrown during register reads.

Add a clocks property to the binding to describe this relationship, and
mark it as required for the affected clocks.

Fixes: dd240e95f1be ("dt-bindings: clock: mediatek: Describe MT8196 clock controllers")
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli at collabora.com>
---
 .../bindings/clock/mediatek,mt8196-sys-clock.yaml  | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
index 660ab64f390d2e722b7d3e25cf057926da318bc0..41aacd8d5f69050eebdf8392f7b652427632f491 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
@@ -45,6 +45,9 @@ properties:
   reg:
     maxItems: 1
 
+  clocks:
+    maxItems: 1
+
   '#clock-cells':
     const: 1
 
@@ -90,6 +93,23 @@ required:
 
 additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - mediatek,mt8196-mfgpll-pll-ctrl
+              - mediatek,mt8196-mfgpll-sc0-pll-ctrl
+              - mediatek,mt8196-mfgpll-sc1-pll-ctrl
+    then:
+      properties:
+        clocks:
+          items:
+            - description: mfg_eb clock
+      required:
+        - clocks
+
 examples:
   - |
     apmixedsys_clk: syscon at 10000800 {
@@ -104,4 +124,12 @@ examples:
         mediatek,hardware-voter = <&scp_hwv>;
         #clock-cells = <1>;
     };
+  - |
+    #include <dt-bindings/clock/mediatek,mt8196-clock.h>
 
+    clock-controller at 4b810000 {
+        compatible = "mediatek,mt8196-mfgpll-pll-ctrl", "syscon";
+        reg = <0x4b810000 0x400>;
+        clocks = <&topckgen CLK_TOP_MFG_EB>;
+        #clock-cells = <1>;
+    };

-- 
2.51.0