[PATCH 34/38] arm64: dts: mediatek: mt8195: Fix ranges for jpeg enc/decoder nodes

[Matthias Brugger]

On 24/07/2025 10:39, AngeloGioacchino Del Regno wrote:
> The jpeg decoder main node is under the soc bus but currently has
> no ranges or reg specified, while the children do, and this is
> wrong in multiple aspects.
> 
> The very same is also valid for the jpeg encoder node.
> 
> Rename the decoder and encoder nodes to "jpeg-decoder at 1a040000"
> and to "jpeg-encoder at 1a030000" respectively, and change their
> children to use the newly defined ranges.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

Applied, thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 30 +++++++++++++-----------
>   1 file changed, 16 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index dd065b1bf94a..35b10082bb89 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -3014,7 +3014,7 @@ venc: video-codec at 1a020000 {
>   			#size-cells = <2>;
>   		};
>   
> -		jpgdec-master {
> +		jpeg-decoder at 1a040000 {
>   			compatible = "mediatek,mt8195-jpgdec";
>   			power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
>   			iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
> @@ -3025,11 +3025,12 @@ jpgdec-master {
>   				 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
>   			#address-cells = <2>;
>   			#size-cells = <2>;
> -			ranges;
> +			ranges = <0 0 0 0x1a040000 0 0x20000>,
> +				 <1 0 0 0x1b040000 0 0x10000>;
>   
> -			jpgdec at 1a040000 {
> +			jpgdec at 0,0 {
>   				compatible = "mediatek,mt8195-jpgdec-hw";
> -				reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
> +				reg = <0 0 0 0x10000>;/* JPGDEC_C0 */
>   				iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
>   					 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
>   					 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
> @@ -3042,9 +3043,9 @@ jpgdec at 1a040000 {
>   				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
>   			};
>   
> -			jpgdec at 1a050000 {
> +			jpgdec at 0,10000 {
>   				compatible = "mediatek,mt8195-jpgdec-hw";
> -				reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
> +				reg = <0 0 0x10000 0x10000>;/* JPGDEC_C1 */
>   				iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
>   					 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
>   					 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
> @@ -3057,9 +3058,9 @@ jpgdec at 1a050000 {
>   				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
>   			};
>   
> -			jpgdec at 1b040000 {
> +			jpgdec at 1,0 {
>   				compatible = "mediatek,mt8195-jpgdec-hw";
> -				reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
> +				reg = <1 0 0 0x10000>;/* JPGDEC_C2 */
>   				iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
>   					 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
>   					 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
> @@ -3088,7 +3089,7 @@ vdosys0: syscon at 1c01a000 {
>   		};
>   
>   
> -		jpgenc-master {
> +		jpeg-encoder at 1a030000 {
>   			compatible = "mediatek,mt8195-jpgenc";
>   			power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
>   			iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
> @@ -3097,11 +3098,12 @@ jpgenc-master {
>   					<&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
>   			#address-cells = <2>;
>   			#size-cells = <2>;
> -			ranges;
> +			ranges = <0 0 0 0x1a030000 0 0x10000>,
> +				 <1 0 0 0x1b030000 0 0x10000>;
>   
> -			jpgenc at 1a030000 {
> +			jpgenc at 0,0 {
>   				compatible = "mediatek,mt8195-jpgenc-hw";
> -				reg = <0 0x1a030000 0 0x10000>;
> +				reg = <0 0 0 0x10000>;
>   				iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
>   						<&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
>   						<&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
> @@ -3112,9 +3114,9 @@ jpgenc at 1a030000 {
>   				power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
>   			};
>   
> -			jpgenc at 1b030000 {
> +			jpgenc at 1,0 {
>   				compatible = "mediatek,mt8195-jpgenc-hw";
> -				reg = <0 0x1b030000 0 0x10000>;
> +				reg = <1 0 0 0x10000>;
>   				iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
>   						<&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
>   						<&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,