[PATCH v4 1/4] arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700
AngeloGioacchino Del Regno
angelogioacchino.delregno at collabora.com
Tue Sep 9 01:19:51 PDT 2025
Il 08/09/25 15:05, Mateusz Koza ha scritto:
> Add support for Grinn GenioSBC-700. The Grinn GenioSBC-700 is a
> single-board computer based on the MediaTek Genio 700 SoC. Its device
> tree is split into separate SoM (.dtsi) and SBC (.dtsi) files, which are
> combined in the SoC-specific .dts file.
>
> More details about the hardware:
> - https://grinn-global.com/products/grinn-geniosom-700
> - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc
>
> Reviewed-by: Andrew Lunn <andrew at lunn.ch>
> Signed-off-by: Mateusz Koza <mateusz.koza at grinn-global.com>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> .../mediatek/mt8390-grinn-genio-700-sbc.dts | 19 +
> .../dts/mediatek/mt8390-grinn-genio-sbc.dtsi | 538 ++++++++++++++++++
> .../dts/mediatek/mt8390-grinn-genio-som.dtsi | 209 +++++++
> 4 files changed, 767 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index a4df4c21399e..b37a8c65e724 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo
> diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts
> new file mode 100644
> index 000000000000..a37507a5a5d0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2025 Grinn sp. z o.o.
> + * Author: Mateusz Koza <mateusz.koza at grinn-global.com>
> + */
> +/dts-v1/;
> +
> +#include "mt8188.dtsi"
> +#include "mt8390-grinn-genio-som.dtsi"
> +#include "mt8390-grinn-genio-sbc.dtsi"
> +
> +/ {
> + model = "Grinn GenioSBC-700";
> + compatible = "grinn,genio-700-sbc", "mediatek,mt8390", "mediatek,mt8188";
Just a nit: please leave one blank line here.
> + memory at 40000000 {
> + device_type = "memory";
> + reg = <0 0x40000000 1 0x00000000>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi
> new file mode 100644
> index 000000000000..0e6006cd8ed9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi
> @@ -0,0 +1,538 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2025 Grinn sp. z o.o.
> + * Author: Mateusz Koza <mateusz.koza at grinn-global.com>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + chassis-type = "embedded";
> + aliases {
> + ethernet0 = ð
> + i2c0 = &i2c0;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c5 = &i2c5;
> + i2c6 = &i2c6;
> + serial0 = &uart0;
> + };
> +
Please move chassis-type here.
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +
> + firmware {
> + optee {
> + compatible = "linaro,optee-tz";
> + method = "smc";
> + };
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /*
> + * 12 MiB reserved for OP-TEE (BL32)
> + * +-----------------------+ 0x43e0_0000
> + * | SHMEM 2MiB |
> + * +-----------------------+ 0x43c0_0000
> + * | | TA_RAM 8MiB |
> + * + TZDRAM +--------------+ 0x4340_0000
> + * | | TEE_RAM 2MiB |
> + * +-----------------------+ 0x4320_0000
> + */
> + optee_reserved: optee at 43200000 {
> + no-map;
> + reg = <0 0x43200000 0 0x00c00000>;
> + };
> +
> + scp_mem: memory at 50000000 {
> + compatible = "shared-dma-pool";
> + reg = <0 0x50000000 0 0x2900000>;
> + no-map;
> + };
> +
> + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
> + bl31_secmon_reserved: memory at 54600000 {
> + no-map;
> + reg = <0 0x54600000 0x0 0x200000>;
> + };
> +
> + apu_mem: memory at 55000000 {
> + compatible = "shared-dma-pool";
> + reg = <0 0x55000000 0 0x1400000>; /* 20 MB */
> + };
> +
> + vpu_mem: memory at 57000000 {
> + compatible = "shared-dma-pool";
> + reg = <0 0x57000000 0 0x1400000>; /* 20 MB */
> + };
> +
> + adsp_mem: memory at 60000000 {
> + compatible = "shared-dma-pool";
> + reg = <0 0x60000000 0 0xf00000>;
> + no-map;
> + };
> +
> + afe_dma_mem: memory at 60f00000 {
> + compatible = "shared-dma-pool";
> + reg = <0 0x60f00000 0 0x100000>;
> + no-map;
> + };
> +
> + adsp_dma_mem: memory at 61000000 {
> + compatible = "shared-dma-pool";
> + reg = <0 0x61000000 0 0x100000>;
> + no-map;
> + };
> + };
> +
> + reg_sbc_vsys: regulator-vsys {
> + compatible = "regulator-fixed";
> + regulator-name = "vsys";
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + reg_fixed_5v: regulator-0 {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed_5v";
Can we please avoid underscores?
regulator-name = "fixed-5v0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-always-on;
> + vin-supply = <®_sbc_vsys>;
> + };
> +
> + reg_fixed_4v2: regulator-1 {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed_4v2";
fixed-4v2
> + regulator-min-microvolt = <4200000>;
> + regulator-max-microvolt = <4200000>;
> + enable-active-high;
> + regulator-always-on;
> + vin-supply = <®_sbc_vsys>;
> + };
> +
> + reg_fixed_3v3: regulator-2 {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed_3v3";
fixed-3v3
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + regulator-always-on;
> + vin-supply = <®_sbc_vsys>;
> + };
> +};
> +
> +&pio {
> + gpio-line-names =
> + /* 0 - 4 */ "RPI_GPIO0", "RPI_GPIO1", "", "", "RPI_GPIO4",
> + /* 5 - 9 */ "", "RPI_GPIO6", "", "", "RPI_GPIO9",
> + /* 10 - 14 */ "RPI_GPIO10", "RPI_GPIO11", "", "", "",
> + /* 15 - 19 */ "", "", "", "", "",
> + /* 20 - 24 */ "", "RPI_GPIO21", "", "RPI_GPIO23", "",
> + /* 25 - 29 */ "", "", "", "", "",
> + /* 30 - 34 */ "RPI_GPIO30", "", "", "", "",
> + /* 35 - 39 */ "RPI_GPIO35", "RPI_GPIO36", "", "", "",
> + /* 40 - 44 */ "", "", "", "", "",
> + /* 45 - 49 */ "", "", "", "", "",
> + /* 50 - 54 */ "", "", "", "", "",
> + /* 55 - 59 */ "RPI_GPIO55", "RPI_GPIO56", "", "", "RPI_GPIO59",
> + /* 60 - 64 */ "RPI_GPIO60", "", "", "", "",
> + /* 65 - 69 */ "", "", "", "", "RPI_GPIO69",
> + /* 70 - 74 */ "", "", "RPI_GPIO72", "RPI_GPIO73", "RPI_GPIO74",
> + /* 75 - 79 */ "", "", "", "", "RPI_GPIO79",
> + /* 80 - 84 */ "RPI_GPIO80", "RPI_GPIO81", "RPI_GPIO82", "", "",
> + /* 85 - 89 */ "", "", "", "", "",
> + /* 90 - 94 */ "", "", "", "", "",
> + /* 95 - 99 */ "", "", "", "", "",
> + /*100 - 104 */ "", "", "", "", "",
> + /*105 - 109 */ "", "", "", "", "",
> + /*110 - 114 */ "", "", "", "", "",
> + /*115 - 119 */ "", "", "", "", "",
> + /*120 - 124 */ "", "RPI_GPIO121", "RPI_GPIO122", "RPI_GPIO123", "RPI_GPIO124";
> +
> + i2c0_pins: i2c0-pins {
> + pins {
> + pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>,
> + <PINMUX_GPIO55__FUNC_B1_SCL0>;
> + bias-pull-up = <MTK_PULL_SET_RSEL_011>;
> + drive-strength-microamp = <1000>;
> + };
> + };
> +
> + i2c2_pins: i2c2-pins {
> + pins {
> + pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>,
> + <PINMUX_GPIO59__FUNC_B1_SCL2>;
> + bias-pull-up = <MTK_PULL_SET_RSEL_011>;
> + drive-strength-microamp = <1000>;
> + };
> + };
> +
> + i2c3_pins: i2c3-pins {
> + pins {
> + pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>,
> + <PINMUX_GPIO61__FUNC_B1_SCL3>;
> + bias-pull-up = <MTK_PULL_SET_RSEL_011>;
> + drive-strength-microamp = <1000>;
> + };
> + };
> +
> + i2c5_pins: i2c5-pins {
> + pins {
> + pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>,
> + <PINMUX_GPIO65__FUNC_B1_SCL5>;
> + bias-pull-up = <MTK_PULL_SET_RSEL_011>;
> + drive-strength-microamp = <1000>;
> + };
> + };
> +
> + i2c6_pins: i2c6-pins {
> + pins {
> + pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>,
> + <PINMUX_GPIO67__FUNC_B1_SCL6>;
> + bias-pull-up = <MTK_PULL_SET_RSEL_011>;
> + drive-strength-microamp = <1000>;
> + };
> + };
> +
> + uart0_pins: uart0-pins {
> + pins {
> + pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>,
> + <PINMUX_GPIO32__FUNC_I1_URXD0>;
> + bias-pull-up;
> + };
> + };
> +
> + uart1_pins: uart1-pins {
> + pins {
> + pinmux = <PINMUX_GPIO86__FUNC_O_UTXD1>,
> + <PINMUX_GPIO87__FUNC_I1_URXD1>;
> + bias-pull-up;
> + };
> + };
> +
> + uart2_pins: uart2-pins {
> + pins {
> + pinmux = <PINMUX_GPIO35__FUNC_O_UTXD2>,
> + <PINMUX_GPIO36__FUNC_I1_URXD2>;
> + bias-pull-up;
> + };
> + };
> +
> + pcie_pins_default: pcie-default {
> + mux {
> + pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>,
> + <PINMUX_GPIO48__FUNC_O_PERSTN>,
> + <PINMUX_GPIO49__FUNC_B1_CLKREQN>;
> + bias-pull-up;
> + };
> + };
> +
> + eth_default_pins: eth-default-pins {
> + pins-cc {
> + pinmux = <PINMUX_GPIO139__FUNC_B0_GBE_TXC>,
> + <PINMUX_GPIO140__FUNC_I0_GBE_RXC>,
> + <PINMUX_GPIO141__FUNC_I0_GBE_RXDV>,
> + <PINMUX_GPIO142__FUNC_O_GBE_TXEN>;
> + drive-strength = <8>;
> + };
> +
> + pins-mdio {
> + pinmux = <PINMUX_GPIO143__FUNC_O_GBE_MDC>,
> + <PINMUX_GPIO144__FUNC_B1_GBE_MDIO>;
> + drive-strength = <8>;
> + input-enable;
> + };
> +
> + pins-power {
> + pinmux = <PINMUX_GPIO145__FUNC_B_GPIO145>,
> + <PINMUX_GPIO146__FUNC_B_GPIO146>;
> + output-high;
> + };
> +
> + pins-rxd {
> + pinmux = <PINMUX_GPIO135__FUNC_I0_GBE_RXD3>,
> + <PINMUX_GPIO136__FUNC_I0_GBE_RXD2>,
> + <PINMUX_GPIO137__FUNC_I0_GBE_RXD1>,
> + <PINMUX_GPIO138__FUNC_I0_GBE_RXD0>;
> + drive-strength = <8>;
> + };
> +
> + pins-txd {
> + pinmux = <PINMUX_GPIO131__FUNC_O_GBE_TXD3>,
> + <PINMUX_GPIO132__FUNC_O_GBE_TXD2>,
> + <PINMUX_GPIO133__FUNC_O_GBE_TXD1>,
> + <PINMUX_GPIO134__FUNC_O_GBE_TXD0>;
> + drive-strength = <8>;
> + };
> + };
> +
> + eth_sleep_pins: eth-sleep-pins {
> + pins-cc {
> + pinmux = <PINMUX_GPIO139__FUNC_B_GPIO139>,
> + <PINMUX_GPIO140__FUNC_B_GPIO140>,
> + <PINMUX_GPIO141__FUNC_B_GPIO141>,
> + <PINMUX_GPIO142__FUNC_B_GPIO142>;
> + };
> +
> + pins-mdio {
> + pinmux = <PINMUX_GPIO143__FUNC_B_GPIO143>,
> + <PINMUX_GPIO144__FUNC_B_GPIO144>;
> + input-disable;
> + bias-disable;
> + };
> +
> + pins-rxd {
> + pinmux = <PINMUX_GPIO135__FUNC_B_GPIO135>,
> + <PINMUX_GPIO136__FUNC_B_GPIO136>,
> + <PINMUX_GPIO137__FUNC_B_GPIO137>,
> + <PINMUX_GPIO138__FUNC_B_GPIO138>;
> + };
> +
> + pins-txd {
> + pinmux = <PINMUX_GPIO131__FUNC_B_GPIO131>,
> + <PINMUX_GPIO132__FUNC_B_GPIO132>,
> + <PINMUX_GPIO133__FUNC_B_GPIO133>,
> + <PINMUX_GPIO134__FUNC_B_GPIO134>;
> + };
> + };
> +
> + spi2_pins: spi2-pins {
> + pins-spi {
> + pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>,
> + <PINMUX_GPIO80__FUNC_O_SPIM2_CLK>,
> + <PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>,
> + <PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>;
> + bias-disable;
> + };
> + };
> +
> + audio_default_pins: audio-default-pins {
> + pins-cmd-dat {
> + pinmux = <PINMUX_GPIO121__FUNC_B0_PCM_CLK>,
> + <PINMUX_GPIO122__FUNC_B0_PCM_SYNC>,
> + <PINMUX_GPIO123__FUNC_O_PCM_DO>,
> + <PINMUX_GPIO124__FUNC_I0_PCM_DI>;
> + };
> + };
> +
> + usb_default_pins: usb-default-pins {
> + pins-valid {
> + pinmux = <PINMUX_GPIO85__FUNC_I0_VBUSVALID>;
> + input-enable;
> + };
> + };
> +};
> +
> +ð {
Please reorder the nodes per type (generic first, vendor specific last) and
alphabetically, like so:
> + phy-mode = "rgmii-id";
> + phy-handle = <ðernet_phy0>;
pinctrl-names
pinctrl-0
pinctrl-1
mediatek,.....
snps,.....
status = "okay";
> + snps,reset-active-low;
> + snps,reset-delays-us = <0 11000 200000>;
> + mediatek,tx-delay-ps = <30>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <ð_default_pins>;
> + pinctrl-1 = <ð_sleep_pins>;
> + mediatek,mac-wol;
> + snps,reset-gpio = <&pio 147 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +};
> +
> +ð_mdio {
> + ethernet_phy0: ethernet-phy at 3 {
compatible
reg
interrupts-extended
eee-broken-1000t;
> + reg = <3>;
> + compatible = "ethernet-phy-ieee802.3-c22";
> + eee-broken-1000t;
> + interrupts-extended = <&pio 148 IRQ_TYPE_LEVEL_LOW>;
> + };
> +};
> +
> +&xhci1 {
#address-cells
#size-cells
vusb33-supply
status = "okay"
subnodes
> + status = "okay";
> + vusb33-supply = <&mt6359_vusb_ldo_reg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + hub_2_0: hub at 1 {
> + compatible = "usb451,8027";
> + reg = <1>;
> + peer-hub = <&hub_3_0>;
> + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
> + vdd-supply = <®_fixed_3v3>;
> + };
> +
> + hub_3_0: hub at 2 {
> + compatible = "usb451,8025";
> + reg = <2>;
> + peer-hub = <&hub_2_0>;
> + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
> + vdd-supply = <®_fixed_3v3>;
> + };
> +};
> +
> +&xhci2 {
> + status = "okay";
> + vusb33-supply = <&mt6359_vusb_ldo_reg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
same here
> +
> + hub at 1 {
> + compatible = "microchip,usb2513bi";
> + reg = <1>;
> + vdd-supply = <®_fixed_3v3>;
> + };
> +};
> +
> +&ssusb0 {
> + status = "okay";
> + dr_mode = "peripheral";
> + vusb33-supply = <&mt6359_vusb_ldo_reg>;
> + pinctrl-0 = <&usb_default_pins>;
> + pinctrl-names = "default";
dr_mode
pinctrl
vusb
status
> +};
> +
> +&ssusb1 {
> + status = "okay";
> + dr_mode = "host";
> + vusb33-supply = <&mt6359_vusb_ldo_reg>;
> + maximum-speed = "super-speed";
dr_mode
maximum-speed
vusb
status
> +};
> +
> +&ssusb2 {
> + status = "okay";
> + dr_mode = "host";
> + vusb33-supply = <&mt6359_vusb_ldo_reg>;
> + maximum-speed = "high-speed";
same here
> +};
> +
> +&scp_cluster {
> + status = "okay";
> +};
> +
> +&scp_c0 {
> + firmware-name = "mediatek/mt8188/scp.img";
please drop firmware-name, unfortunately this is not acceptable upstream.
> + memory-region = <&scp_mem>;
> + status = "okay";
> +};
> +
> +&gpu {
> + mali-supply = <&mt6359_vproc2_buck_reg>;
> + status = "okay";
> +};
> +
> +&adsp {
> + memory-region = <&adsp_dma_mem>, <&adsp_mem>;
> + status = "okay";
> +};
> +
> +&afe {
> + memory-region = <&afe_dma_mem>;
> + status = "okay";
> +};
> +
> +&sound {
> + compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb";
> + model = "mt8390-evk";
> + pinctrl-names = "default";
> + pinctrl-0 = <&audio_default_pins>;
> + audio-routing =
> + "Headphone", "Headphone L",
> + "Headphone", "Headphone R",
> + "AP DMIC", "AUDGLB",
> + "AP DMIC", "MIC_BIAS_0",
> + "AP DMIC", "MIC_BIAS_2",
> + "DMIC_INPUT", "AP DMIC";
> +
> + mediatek,adsp = <&adsp>;
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi
> new file mode 100644
> index 000000000000..d88481beff9d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi
> @@ -0,0 +1,209 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2025 Grinn sp. z o.o.
> + * Author: Mateusz Koza <mateusz.koza at grinn-global.com>
> + */
> +
> +#include "mt6359.dtsi"
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> + aliases {
> + i2c1 = &i2c1;
> + mmc0 = &mmc0;
> + };
> +};
> +
..snip..
> +
> +&pmic {
> + interrupt-parent = <&pio>;
> + interrupts = <222 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
> +
> + mt6359keys: keys {
(drop handle) keys {
> + compatible = "mediatek,mt6359-keys";
> + mediatek,long-press-mode = <1>;
> + power-off-time-sec = <0>;
> +
> + power-key {
> + linux,keycodes = <KEY_POWER>;
> + wakeup-source;
> + };
> + };
> +};
Cheers,
Angelo
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