[PATCH v5 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENC

[Chen-Yu Tsai]

On Fri, Aug 29, 2025 at 5:20 PM Laura Nao <laura.nao at collabora.com> wrote:
>
> MT8196 uses set/clr/upd registers for mux gate enable/disable control,
> along with a FENC bit to check the status. Add new set of mux gate
> clock operations with support for set/clr/upd and FENC status logic.
>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado at collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Signed-off-by: Laura Nao <laura.nao at collabora.com>

Reviewed-by: Chen-Yu Tsai <wenst at chromium.org>