[PATCH] gpu: drm: mediatek: correct clk setting AUX_RX_UI_CNT_THR_AUX_FOR_26M

[CK Hu (胡俊光)]

On Mon, 2025-08-18 at 16:34 +0800, payne.lin wrote:
> From: Bincai Liu <bincai.liu at mediatek.com>
> 
> Updated the definition of AUX_RX_UI_CNT_THR_AUX_FOR_26M from 13 to 14.
> No other code or logic changes were made; only the macro value was modified.
> This change affects the timing configuration for AUX RX at 26MHz.
> The formula is xtal_clk / 2 + 1.

I still don't understand why need this patch.
If it fix a bug, describe what the bug is.
If it provide more stability, describe what's the difference of 13 and 14.
You just show a formula xtal_clk / 2 + 1, but what's the relation with the value 13 and 14?

Regards,
CK

> 
> Signed-off-by: Bincai Liu <bincai.liu at mediatek.com>
> Signed-off-by: Payne Lin <payne.lin at mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dp_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> index 8ad7a9cc259e..f8c7b3c0935f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> @@ -301,7 +301,7 @@
>  #define AUX_TIMEOUT_THR_AUX_TX_P0_VAL			0x1595
>  #define MTK_DP_AUX_P0_3614			0x3614
>  #define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK		GENMASK(6, 0)
> -#define AUX_RX_UI_CNT_THR_AUX_FOR_26M			13
> +#define AUX_RX_UI_CNT_THR_AUX_FOR_26M			14
>  #define MTK_DP_AUX_P0_3618			0x3618
>  #define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK			BIT(9)
>  #define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK	GENMASK(3, 0)