[PATCH v1 01/10] dt-bindings: media: Add MediaTek mt8188 ImgSys components
Olivia Wen
olivia.wen at mediatek.com
Sat May 24 04:49:53 PDT 2025
Introduce more Image System (ImgSys) components present in MT8188.
Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
---
.../bindings/media/mediatek,imgsys.yaml | 180 ++++++++++++++++++
1 file changed, 180 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,imgsys.yaml
diff --git a/Documentation/devicetree/bindings/media/mediatek,imgsys.yaml b/Documentation/devicetree/bindings/media/mediatek,imgsys.yaml
new file mode 100644
index 000000000000..c2899c4b227b
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,imgsys.yaml
@@ -0,0 +1,180 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,imgsys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Camera Image System
+
+maintainers:
+ - Olivia Wen <olivia.wen at mediatek.com>
+
+description:
+ MediaTek Camera Image System is the image processing hardware present in MediaTek SoCs
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8188-isp-imgsys
+
+ reg:
+ minItems: 1
+ maxItems: 17
+
+ clocks:
+ minItems: 1
+ maxItems: 17
+
+ clock-names:
+ minItems: 1
+ maxItems: 17
+
+ assigned-clocks: true
+
+ assigned-clock-parents: true
+
+ '#address-cells':
+ const: 2
+
+ '#size-cells':
+ const: 2
+
+ iommus:
+ minItems: 1
+ maxItems: 30
+
+ mediatek,larbs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 32
+ items:
+ maxItems: 1
+ description: |
+ List of phandle to the local arbiters in the current Socs.
+ Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
+ according to the local arbiter index, like larb0, larb1, larb2...
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - iommus
+ - mediatek,larbs
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - mediatek,mt8188-isp-imgsys
+
+ then:
+ required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - iommus
+ - mediatek,larbs
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mediatek,mt8188-clk.h>
+ #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
+
+ imgsys_fw: imgsys-fw at 15000000 {
+ compatible = "mediatek,mt8188-isp-imgsys";
+ reg = <0 0x15000000 0 0x4000>, /* 0 IMGSYS_TOP */
+ <0 0x15020000 0 0x10000>, /* 1 IMGSYS_TRAW */
+ <0 0x15040000 0 0x10000>, /* 2 IMGSYS_LTRAW */
+ <0 0x15640000 0 0x10000>, /* 3 IMGSYS_XTRAW */
+ <0 0x15100000 0 0x10000>, /* 4 IMGSYS_DIP */
+ <0 0x15150000 0 0x10000>, /* 5 IMGSYS_DIP_NR */
+ <0 0x15210000 0 0x10000>, /* 6 IMGSYS_PQDIP_A */
+ <0 0x15510000 0 0x10000>, /* 7 IMGSYS_PQDIP_B */
+ <0 0x15200000 0 0x10000>, /* 8 IMGSYS_WPE_EIS */
+ <0 0x15500000 0 0x10000>, /* 9 IMGSYS_WPE_TNR */
+ <0 0x15600000 0 0x10000>, /* 10 IMGSYS_WPE_LITE */
+ <0 0x15220000 0 0x00100>, /* 11 IMGSYS_WPE1_DIP1 */
+ <0 0x15320000 0 0x10000>, /* 12 IMGSYS_ME */
+ <0 0x15520000 0 0x00100>, /* 13 IMGSYS_WPE2_DIP1 */
+ <0 0x15620000 0 0x00100>, /* 14 IMGSYS_WPE3_DIP1 */
+ <0 0x15110000 0 0x00100>, /* 15 IMGSYS_DIP_TOP */
+ <0 0x15130000 0 0x00100>; /* 16 IMGSYS_DIP_TOP_NR */
+
+ assigned-clocks = <&topckgen CLK_TOP_IMG>;
+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_IMGPLL>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ clocks = <&imgsys CLK_IMGSYS_MAIN_TRAW0>,
+ <&imgsys CLK_IMGSYS_MAIN_TRAW1>,
+ <&imgsys CLK_IMGSYS_MAIN_VCORE_GALS>,
+ <&imgsys CLK_IMGSYS_MAIN_DIP0>,
+ <&imgsys CLK_IMGSYS_MAIN_WPE0>,
+ <&imgsys CLK_IMGSYS_MAIN_WPE1>,
+ <&imgsys CLK_IMGSYS_MAIN_WPE2>,
+ <&imgsys CLK_IMGSYS_MAIN_GALS>,
+ <&imgsys1_dip_top CLK_IMGSYS1_DIP_TOP_DIP_TOP>,
+ <&imgsys1_dip_nr CLK_IMGSYS1_DIP_NR_DIP_NR>,
+ <&imgsys_wpe1 CLK_IMGSYS_WPE1>,
+ <&imgsys_wpe2 CLK_IMGSYS_WPE2>,
+ <&imgsys_wpe3 CLK_IMGSYS_WPE3>,
+ <&imgsys CLK_IMGSYS_MAIN_IPE>,
+ <&ipesys CLK_IPESYS_TOP>,
+ <&ipesys CLK_IPE_ME>,
+ <&ipesys CLK_IPE_SMI_LARB12>;
+ clock-names = "IMGSYS_CG_IMG_TRAW0",
+ "IMGSYS_CG_IMG_TRAW1",
+ "IMGSYS_CG_IMG_VCORE_GALS",
+ "IMGSYS_CG_IMG_DIP0",
+ "IMGSYS_CG_IMG_WPE0",
+ "IMGSYS_CG_IMG_WPE1",
+ "IMGSYS_CG_IMG_WPE2",
+ "IMGSYS_CG_IMG_GALS",
+ "DIP_TOP_DIP_TOP",
+ "DIP_NR_DIP_NR",
+ "WPE1_CG_DIP1_WPE",
+ "WPE2_CG_DIP1_WPE",
+ "WPE3_CG_DIP1_WPE",
+ "ME_CG_IPE",
+ "ME_CG_IPE_TOP",
+ "ME_CG",
+ "ME_CG_LARB12";
+
+ iommus = <&vdo_iommu M4U_PORT_L9_IMGI_T1_A>,
+ <&vdo_iommu M4U_PORT_L9_UFDI_T1_A>,
+ <&vdo_iommu M4U_PORT_L9_IMGBI_T1_A>,
+ <&vdo_iommu M4U_PORT_L9_IMGCI_T1_A>,
+ <&vdo_iommu M4U_PORT_L9_SMTI_T1_A>,
+ <&vdo_iommu M4U_PORT_L9_SMTI_T4_A>,
+ <&vdo_iommu M4U_PORT_L9_TNCSTI_T1_A>,
+ <&vdo_iommu M4U_PORT_L9_TNCSTI_T4_A>,
+ <&vdo_iommu M4U_PORT_L9_YUVO_T1_A>,
+ <&vdo_iommu M4U_PORT_L9_YUVBO_T1_A>,
+ <&vdo_iommu M4U_PORT_L9_YUVCO_T1_A>,
+ <&vdo_iommu M4U_PORT_L9_TIMGO_T1_A>,
+ <&vdo_iommu M4U_PORT_L9_YUVO_T2_A>,
+ <&vdo_iommu M4U_PORT_L9_YUVO_T5_A>,
+ <&vdo_iommu M4U_PORT_L9_IMGI_T1_B>,
+ <&vdo_iommu M4U_PORT_L9_IMGBI_T1_B>,
+ <&vdo_iommu M4U_PORT_L9_IMGCI_T1_B>,
+ <&vdo_iommu M4U_PORT_L9_SMTI_T4_B>,
+ <&vdo_iommu M4U_PORT_L9_TNCSO_T1_A>,
+ <&vdo_iommu M4U_PORT_L9_SMTO_T1_A>,
+ <&vdo_iommu M4U_PORT_L9_SMTO_T4_A>,
+ <&vdo_iommu M4U_PORT_L9_TNCSTO_T1_A>,
+ <&vdo_iommu M4U_PORT_L9_YUVO_T2_B>,
+ <&vdo_iommu M4U_PORT_L9_YUVO_T5_B>,
+ <&vdo_iommu M4U_PORT_L9_SMTO_T4_B>;
+
+ mediatek,larbs = <&larb9>,
+ <&larb10>,
+ <&larb11a>,
+ <&larb11b>,
+ <&larb11c>,
+ <&larb15>,
+ <&larb12>;
+ };
--
2.45.2
More information about the Linux-mediatek
mailing list