From krzk at kernel.org  Thu May  1 03:58:48 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Thu, 1 May 2025 12:58:48 +0200
Subject: [PATCH v4 1/7] dt-bindings: timer: Add EcoNet EN751221 "HPT" CPU
 Timer
In-Reply-To: <20250430133433.22222-2-cjd@cjdns.fr>
References: <20250430133433.22222-1-cjd@cjdns.fr>
 <20250430133433.22222-2-cjd@cjdns.fr>
Message-ID: <20250501-ludicrous-idealistic-camel-7bf8aa@kuoka>

On Wed, Apr 30, 2025 at 01:34:27PM GMT, Caleb James DeLisle wrote:
> Add device tree bindings for the so-called high-precision timer (HPT)
> in the EcoNet EN751221 SoC.
> 
> Signed-off-by: Caleb James DeLisle <cjd at cjdns.fr>
> ---
>  .../bindings/timer/econet,en751221-timer.yaml | 80 +++++++++++++++++++
>  1 file changed, 80 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
> 

What changed? Nothing explains dropping the tag.

<form letter>
This is a friendly reminder during the review process.

It looks like you received a tag and forgot to add it.

If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions of patchset, under or above your Signed-off-by tag, unless
patch changed significantly (e.g. new properties added to the DT
bindings). Tag is "received", when provided in a message replied to you
on the mailing list. Tools like b4 can help here. However, there's no
need to repost patches *only* to add the tags. The upstream maintainer
will do that for tags received on the version they apply.

Please read:
https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst#L577

If a tag was not added on purpose, please state why and what changed.
</form letter>

Best regards,
Krzysztof



From lee at kernel.org  Thu May  1 05:00:06 2025
From: lee at kernel.org (Lee Jones)
Date: Thu, 01 May 2025 13:00:06 +0100
Subject: (subset) [PATCH v4 5/8] dt-bindings: mfd: syscon: Add
 mt7988-topmisc
In-Reply-To: <20250422132438.15735-6-linux@fw-web.de>
References: <20250422132438.15735-1-linux@fw-web.de>
 <20250422132438.15735-6-linux@fw-web.de>
Message-ID: <174610080698.3792828.16129247055603832189.b4-ty@kernel.org>

On Tue, 22 Apr 2025 15:24:28 +0200, Frank Wunderlich wrote:
> Add compatible for Mediatek mt7988 topmisc syscon.
> This hardware block contains 2 functional blocks
> 
> - a powercontroller which is not needed (switched by atf)
> - a multiplexer for high-speed Combo-Phy
> 
> This compatible is only for the multiplexer part.
> 
> [...]

Applied, thanks!

[5/8] dt-bindings: mfd: syscon: Add mt7988-topmisc
      commit: 4d54ce40400c215127ce24aa3a684a20e7d8493a

--
Lee Jones [???]



From linux at fw-web.de  Thu May  1 05:57:02 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Thu,  1 May 2025 14:57:02 +0200
Subject: [RFC,net-next v1] net: phy: mediatek: do not require syscon compatible for pio property
Message-ID: <20250501125703.55224-1-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Current implementation requires syscon compatible for pio property
which is used for driving the switch leds on mt7988.

Replace syscon_regmap_lookup_by_phandle with of_parse_phandle and
device_node_to_regmap to get the regmap already assigned by pinctrl
driver.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 drivers/net/phy/mediatek/mtk-ge-soc.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediatek/mtk-ge-soc.c
index 175cf5239bba..21975ef946d5 100644
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -7,6 +7,7 @@
 #include <linux/pinctrl/consumer.h>
 #include <linux/phy.h>
 #include <linux/regmap.h>
+#include <linux/of.h>
 
 #include "../phylib.h"
 #include "mtk.h"
@@ -1319,6 +1320,7 @@ static int mt7988_phy_probe_shared(struct phy_device *phydev)
 {
 	struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
 	struct mtk_socphy_shared *shared = phy_package_get_priv(phydev);
+	struct device_node *pio_np;
 	struct regmap *regmap;
 	u32 reg;
 	int ret;
@@ -1336,7 +1338,13 @@ static int mt7988_phy_probe_shared(struct phy_device *phydev)
 	 * The 4 bits in TPBANK0 are kept as package shared data and are used to
 	 * set LED polarity for each of the LED0.
 	 */
-	regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
+	pio_np = of_parse_phandle(np, "mediatek,pio", 0);
+	if (!pio_np)
+		return -ENODEV;
+
+	regmap = device_node_to_regmap(pio_np);
+	of_node_put(pio_np);
+
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
-- 
2.43.0



From hannes at cmpxchg.org  Thu May  1 07:02:26 2025
From: hannes at cmpxchg.org (Johannes Weiner)
Date: Thu, 1 May 2025 10:02:26 -0400
Subject: [PATCH] mm: Add Kcompressd for accelerated memory compression
In-Reply-To: <20250430082651.3152444-1-qun-wei.lin@mediatek.com>
References: <20250430082651.3152444-1-qun-wei.lin@mediatek.com>
Message-ID: <20250501140226.GE2020@cmpxchg.org>

On Wed, Apr 30, 2025 at 04:26:41PM +0800, Qun-Wei Lin wrote:
> This patch series introduces a new mechanism called kcompressd to
> improve the efficiency of memory reclaiming in the operating system.
> 
> Problem:
>   In the current system, the kswapd thread is responsible for both scanning
>   the LRU pages and handling memory compression tasks (such as those
>   involving ZSWAP/ZRAM, if enabled). This combined responsibility can lead
>   to significant performance bottlenecks, especially under high memory
>   pressure. The kswapd thread becomes a single point of contention, causing
>   delays in memory reclaiming and overall system performance degradation.
> 
> Solution:
>   Introduced kcompressd to handle asynchronous compression during memory
>   reclaim, improving efficiency by offloading compression tasks from
>   kswapd. This allows kswapd to focus on its primary task of page reclaim
>   without being burdened by the additional overhead of compression.
> 
> In our handheld devices, we found that applying this mechanism under high
> memory pressure scenarios can increase the rate of pgsteal_anon per second
> by over 260% compared to the situation with only kswapd. Additionally, we
> observed a reduction of over 50% in page allocation stall occurrences,
> further demonstrating the effectiveness of kcompressd in alleviating memory
> pressure and improving system responsiveness.

Yes, I think parallelizing this work makes a lot of sense.

> Co-developed-by: Barry Song <21cnbao at gmail.com>
> Signed-off-by: Barry Song <21cnbao at gmail.com>
> Signed-off-by: Qun-Wei Lin <qun-wei.lin at mediatek.com>
> Reference: Re: [PATCH 0/2] Improve Zram by separating compression context from kswapd - Barry Song
>            https://lore.kernel.org/lkml/20250313093005.13998-1-21cnbao at gmail.com/
> ---
>  include/linux/mmzone.h |  6 ++++
>  mm/mm_init.c           |  1 +
>  mm/page_io.c           | 71 ++++++++++++++++++++++++++++++++++++++++++
>  mm/swap.h              |  6 ++++
>  mm/vmscan.c            | 25 +++++++++++++++
>  5 files changed, 109 insertions(+)
> 
> diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
> index 6ccec1bf2896..93c9195a54ae 100644
> --- a/include/linux/mmzone.h
> +++ b/include/linux/mmzone.h
> @@ -23,6 +23,7 @@
>  #include <linux/page-flags.h>
>  #include <linux/local_lock.h>
>  #include <linux/zswap.h>
> +#include <linux/kfifo.h>
>  #include <asm/page.h>
>  
>  /* Free memory management - zoned buddy allocator.  */
> @@ -1398,6 +1399,11 @@ typedef struct pglist_data {
>  
>  	int kswapd_failures;		/* Number of 'reclaimed == 0' runs */
>  
> +#define KCOMPRESS_FIFO_SIZE 256
> +	wait_queue_head_t kcompressd_wait;
> +	struct task_struct *kcompressd;
> +	struct kfifo kcompress_fifo;

The way you implemented this adds time-and-space overhead even on
systems that don't have any sort of swap compression enabled.

That seems unnecessary. There is an existing method for asynchronous
writeback, and pageout() is naturally fully set up to handle this.

IMO the better way to do this is to make zswap_store() (and
zram_bio_write()?) asynchronous. Make those functions queue the work
and wake the compression daemon, and then have the daemon call
folio_end_writeback() / bio_endio() when it's done with it.


From patchwork-bot+netdevbpf at kernel.org  Thu May  1 07:10:33 2025
From: patchwork-bot+netdevbpf at kernel.org (patchwork-bot+netdevbpf at kernel.org)
Date: Thu, 01 May 2025 14:10:33 +0000
Subject: [PATCH v3] net: use sock_gen_put() when sk_state is TCP_TIME_WAIT
In-Reply-To: <20250429020412.14163-1-shiming.cheng@mediatek.com>
References: <20250429020412.14163-1-shiming.cheng@mediatek.com>
Message-ID: <174610863349.2990404.8599127748454819839.git-patchwork-notify@kernel.org>

Hello:

This patch was applied to netdev/net.git (main)
by Jakub Kicinski <kuba at kernel.org>:

On Tue, 29 Apr 2025 09:59:48 +0800 you wrote:
> From: Jibin Zhang <jibin.zhang at mediatek.com>
> 
> It is possible for a pointer of type struct inet_timewait_sock to be
> returned from the functions __inet_lookup_established() and
> __inet6_lookup_established(). This can cause a crash when the
> returned pointer is of type struct inet_timewait_sock and
> sock_put() is called on it. The following is a crash call stack that
> shows sk->sk_wmem_alloc being accessed in sk_free() during the call to
> sock_put() on a struct inet_timewait_sock pointer. To avoid this issue,
> use sock_gen_put() instead of sock_put() when sk->sk_state
> is TCP_TIME_WAIT.
> 
> [...]

Here is the summary with links:
  - [v3] net: use sock_gen_put() when sk_state is TCP_TIME_WAIT
    https://git.kernel.org/netdev/net/c/f920436a4429

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html




From kuba at kernel.org  Thu May  1 07:15:18 2025
From: kuba at kernel.org (Jakub Kicinski)
Date: Thu, 1 May 2025 07:15:18 -0700
Subject: [PATCH net v4] net: airoha: Add missing filed to ppe_mbox_data
 struct
In-Reply-To: <20250429-airoha-en7581-fix-ppe_mbox_data-v4-1-d2a8b901dad0@kernel.org>
References: <20250429-airoha-en7581-fix-ppe_mbox_data-v4-1-d2a8b901dad0@kernel.org>
Message-ID: <20250501071518.50c92e8c@kernel.org>

On Tue, 29 Apr 2025 16:17:41 +0200 Lorenzo Bianconi wrote:
> Moreover, add __packed attribute to ppe_mbox_data struct definition and
> make the fw layout padding explicit in init_info struct.

Why? everything looks naturally packed now :(
__packed also forces the compiler to assume the data is unaligned AFAIU.
The recommended way to ensure the compiler doesn't insert padding is
to do a compile time assert.


From nphamcs at gmail.com  Thu May  1 08:12:48 2025
From: nphamcs at gmail.com (Nhat Pham)
Date: Thu, 1 May 2025 08:12:48 -0700
Subject: [PATCH] mm: Add Kcompressd for accelerated memory compression
In-Reply-To: <20250501140226.GE2020@cmpxchg.org>
References: <20250430082651.3152444-1-qun-wei.lin@mediatek.com> <20250501140226.GE2020@cmpxchg.org>
Message-ID: <CAKEwX=MsP6LGjMRNyaHnO5MkE_ne-u-cKLbGfVQcSR-ALoxBwA@mail.gmail.com>

On Thu, May 1, 2025 at 7:02?AM Johannes Weiner <hannes at cmpxchg.org> wrote:
>
>
> The way you implemented this adds time-and-space overhead even on
> systems that don't have any sort of swap compression enabled.
>
> That seems unnecessary. There is an existing method for asynchronous
> writeback, and pageout() is naturally fully set up to handle this.
>
> IMO the better way to do this is to make zswap_store() (and
> zram_bio_write()?) asynchronous. Make those functions queue the work
> and wake the compression daemon, and then have the daemon call
> folio_end_writeback() / bio_endio() when it's done with it.

+1.


From nphamcs at gmail.com  Thu May  1 08:50:24 2025
From: nphamcs at gmail.com (Nhat Pham)
Date: Thu, 1 May 2025 08:50:24 -0700
Subject: [PATCH] mm: Add Kcompressd for accelerated memory compression
In-Reply-To: <20250430082651.3152444-1-qun-wei.lin@mediatek.com>
References: <20250430082651.3152444-1-qun-wei.lin@mediatek.com>
Message-ID: <CAKEwX=MNVwd_Z1PyBt7swd2VhUVivRN-5E+kHm-3XAPka0d84w@mail.gmail.com>

On Wed, Apr 30, 2025 at 1:27?AM Qun-Wei Lin <qun-wei.lin at mediatek.com> wrote:
>
> This patch series introduces a new mechanism called kcompressd to
> improve the efficiency of memory reclaiming in the operating system.
>
> Problem:
>   In the current system, the kswapd thread is responsible for both scanning
>   the LRU pages and handling memory compression tasks (such as those
>   involving ZSWAP/ZRAM, if enabled). This combined responsibility can lead
>   to significant performance bottlenecks, especially under high memory
>   pressure. The kswapd thread becomes a single point of contention, causing
>   delays in memory reclaiming and overall system performance degradation.
>
> Solution:
>   Introduced kcompressd to handle asynchronous compression during memory
>   reclaim, improving efficiency by offloading compression tasks from
>   kswapd. This allows kswapd to focus on its primary task of page reclaim
>   without being burdened by the additional overhead of compression.
>
> In our handheld devices, we found that applying this mechanism under high
> memory pressure scenarios can increase the rate of pgsteal_anon per second
> by over 260% compared to the situation with only kswapd. Additionally, we
> observed a reduction of over 50% in page allocation stall occurrences,
> further demonstrating the effectiveness of kcompressd in alleviating memory
> pressure and improving system responsiveness.
>

Oh btw, testing this on a simple kernel building task triggers this:

[  133.349908] WARNING: CPU: 0 PID: 50 at mm/memcontrol.c:5330
obj_cgroup_charge_zswap+0x22e/0x250
[  133.350505] Modules linked in: virtio_net pata_acpi net_failover
failover virtio_rng rng_core ata_piix libata scsi_mod scsi_common
[  133.351366] CPU: 0 UID: 0 PID: 50 Comm: kcompressd0 Not tainted
6.14.0-ge65b549702a5 #218
[  133.351940] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996),
BIOS rel-1.16.0-0-gd239552ce722-prebuilt.qemu.org 04/01/2014
[  133.352717] RIP: 0010:obj_cgroup_charge_zswap+0x22e/0x250
[  133.353118] Code: d2 ff 85 c0 0f 85 7a fe ff ff be ff ff ff ff 48
c7 c7 88 da f1 91 e8 a1 b4 a3 00 85 c0 0f 85 61 fe ff ff 0f 0b e9 5a
fe ff ff <0f> 0b e9 f5 fd ff ff e8 36 ae a3 00 e9 78 fe ff ff e8 2c ae
a3 00
[  133.354372] RSP: 0018:ffff9f99803bbc00 EFLAGS: 00010246
[  133.354782] RAX: ffff970f42a9a900 RBX: 000000000000013e RCX: 0000000000000002
[  133.355269] RDX: 0000000000000000 RSI: 000000000000013e RDI: ffff970f475eab40
[  133.355774] RBP: ffff970f475eab40 R08: 0000000000000000 R09: 0000000000000000
[  133.356269] R10: ffffffff90a21205 R11: ffffffff90a211ab R12: ffffffff90a21205
[  133.356782] R13: ffffc4984041ff40 R14: ffff970f42e66000 R15: 000000000000013e
[  133.357279] FS:  0000000000000000(0000) GS:ffff970fbdc00000(0000)
knlGS:0000000000000000
[  133.357807] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  133.358186] CR2: 00007f33950c5030 CR3: 00000000038ea000 CR4: 00000000000006f0
[  133.358656] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[  133.359121] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[  133.359597] Call Trace:
[  133.359767]  <TASK>
[  133.359914]  ? __warn+0x94/0x190
[  133.360136]  ? obj_cgroup_charge_zswap+0x22e/0x250
[  133.360476]  ? report_bug+0x168/0x170
[  133.360742]  ? handle_bug+0x53/0x90
[  133.360982]  ? exc_invalid_op+0x18/0x70
[  133.361240]  ? asm_exc_invalid_op+0x1a/0x20
[  133.361536]  ? zswap_store+0x755/0xf80
[  133.361798]  ? zswap_store+0x6fb/0xf80
[  133.362071]  ? zswap_store+0x755/0xf80
[  133.362338]  ? obj_cgroup_charge_zswap+0x22e/0x250
[  133.362661]  ? zswap_store+0x755/0xf80
[  133.362943]  zswap_store+0x7e7/0xf80
[  133.363203]  ? __pfx_kcompressd+0x10/0x10
[  133.363472]  kcompressd+0xb1/0x180
[  133.363724]  ? __pfx_autoremove_wake_function+0x10/0x10
[  133.364082]  kthread+0xef/0x230
[  133.364298]  ? __pfx_kthread+0x10/0x10
[  133.364548]  ret_from_fork+0x34/0x50
[  133.364810]  ? __pfx_kthread+0x10/0x10
[  133.365063]  ret_from_fork_asm+0x1a/0x30
[  133.365321]  </TASK>
[  133.365471] irq event stamp: 18
[  133.365680] hardirqs last  enabled at (17): [<ffffffff914bd0ef>]
_raw_spin_unlock_irqrestore+0x4f/0x60
[  133.366289] hardirqs last disabled at (18): [<ffffffff914b2031>]
__schedule+0x6b1/0xe80
[  133.366824] softirqs last  enabled at (0): [<ffffffff906b1caf>]
copy_process+0x9af/0x2b50
[  133.367366] softirqs last disabled at (0): [<0000000000000000>] 0x0
[  133.367844] ---[ end trace 0000000000000000 ]---

Seems like we're trigger this warning in the zswap cgroup check (see
obj_cgroup_may_zswap() in mm/memcontrol.c for more details):

VM_WARN_ON_ONCE(!(current->flags & PF_MEMALLOC));

Might wanna fix this...


From krzysztof.kozlowski at linaro.org  Thu May  1 09:02:28 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Thu,  1 May 2025 18:02:28 +0200
Subject: [PATCH RESEND] arm64: dts: mediatek: mt8183: Switch to undeprecated qcom,calibration-variant
Message-ID: <20250501160227.96609-2-krzysztof.kozlowski@linaro.org>

The property qcom,ath10k-calibration-variant was deprecated in favor of
recently introduced generic qcom,calibration-variant, common to all
Qualcomm Atheros WiFi bindings.

Change will affect out of tree users, like other projects, of this DTS.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---

Resending with tag after dependency got merged. This can be applied as
is.
---
 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts     | 2 +-
 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts      | 2 +-
 .../boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts      | 2 +-
 .../boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts      | 2 +-
 .../boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts      | 2 +-
 .../boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts    | 2 +-
 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts  | 2 +-
 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi  | 2 +-
 .../boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts      | 2 +-
 .../boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts      | 2 +-
 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi   | 2 +-
 arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi           | 2 +-
 arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts       | 2 +-
 arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts       | 2 +-
 arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi           | 2 +-
 arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi            | 2 +-
 16 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts
index 83bbcfe62083..f2303d9f125f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts
@@ -35,5 +35,5 @@ trackpad at 2c {
 };
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "GO_COZMO";
+	qcom,calibration-variant = "GO_COZMO";
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
index 7bc7c2687d6f..ebcfaa0498f9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
@@ -28,7 +28,7 @@ &mt6358codec {
 };
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "GO_DAMU";
+	qcom,calibration-variant = "GO_DAMU";
 };
 
 &i2c2 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
index 863f3e403de8..21d1a80125ca 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
@@ -36,6 +36,6 @@ &touchscreen {
 };
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "GO_FENNEL";
+	qcom,calibration-variant = "GO_FENNEL";
 };
 
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
index e0a583ce4a0b..5280ba22b96d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
@@ -24,6 +24,6 @@ &touchscreen {
 
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "GO_FENNEL";
+	qcom,calibration-variant = "GO_FENNEL";
 };
 
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts
index 7874c9a20e12..f3049f3f51f9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts
@@ -24,6 +24,6 @@ &touchscreen {
 
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "GO_FENNEL";
+	qcom,calibration-variant = "GO_FENNEL";
 };
 
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts
index 877256eab262..3a81786084da 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts
@@ -14,5 +14,5 @@ / {
 };
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "GO_FENNEL14";
+	qcom,calibration-variant = "GO_FENNEL14";
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts
index b981dd31a430..959c4d3d9707 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts
@@ -14,5 +14,5 @@ / {
 };
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "GO_FENNEL14";
+	qcom,calibration-variant = "GO_FENNEL14";
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi
index 078bc765646f..4788edaeab87 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi
@@ -22,6 +22,6 @@ trackpad at 2c {
 };
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "GO_JUNIPER";
+	qcom,calibration-variant = "GO_JUNIPER";
 };
 
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts
index ddb993521bbf..01cd59993a7c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts
@@ -14,7 +14,7 @@ / {
 };
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "GO_FENNEL14";
+	qcom,calibration-variant = "GO_FENNEL14";
 };
 
 &mmc1_pins_uhs {
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts
index 10c4f920a7d8..c939ef3965ec 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts
@@ -14,7 +14,7 @@ / {
 };
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "GO_FENNEL14";
+	qcom,calibration-variant = "GO_FENNEL14";
 };
 
 &mmc1_pins_uhs {
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
index c942e461a177..14d03419b92c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
@@ -37,5 +37,5 @@ trackpad at 2c {
 };
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "GO_JUNIPER";
+	qcom,calibration-variant = "GO_JUNIPER";
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
index ff02f63bac29..c4c08c0f715e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
@@ -370,7 +370,7 @@ keyboard-controller {
 };
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "GO_KAKADU";
+	qcom,calibration-variant = "GO_KAKADU";
 };
 
 &panel {
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts
index 2b5a8d1f900e..7428efec95a0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts
@@ -32,5 +32,5 @@ &panel {
 };
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "GO_KATSU";
+	qcom,calibration-variant = "GO_KATSU";
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts
index 75fadf2c7059..a36b6ddb71f6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts
@@ -32,7 +32,7 @@ &panel {
 };
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "GO_KATSU";
+	qcom,calibration-variant = "GO_KATSU";
 };
 
 &sound {
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi
index da6e767b4cee..2b283a55f653 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi
@@ -349,7 +349,7 @@ keyboard-controller {
 };
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "GO_KODAMA";
+	qcom,calibration-variant = "GO_KODAMA";
 };
 
 &i2c_tunnel {
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi
index 8b56b8564ed7..00da50a41574 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi
@@ -353,7 +353,7 @@ keyboard-controller {
 };
 
 &qca_wifi {
-	qcom,ath10k-calibration-variant = "LE_Krane";
+	qcom,calibration-variant = "LE_Krane";
 };
 
 &sound {
-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Thu May  1 09:36:54 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Thu, 01 May 2025 18:36:54 +0200
Subject: [PATCH RESEND v2 0/3] iommu: omap: Simplify few things
Message-ID: <20250501-syscon-phandle-args-iommu-v2-0-5a3cab296972@linaro.org>

Changes in v2:
- Combine patches #1 and #2, add dev_err_probe() and drop the comment
  (resolving Robin's comment)
- New patch: iommu: mtk_iommu_v1: Simplify by dropping local 'mtk_mapping' variable
- Rb tag
- Link to resend of v1: https://lore.kernel.org/r/20250212-syscon-phandle-args-iommu-v1-0-c3fab486b426 at linaro.org
- Link to v1: https://lore.kernel.org/r/20250111-syscon-phandle-args-iommu-v1-0-3767dee585a6 at linaro.org

Few code simplifications without functional impact.  Not tested on
hardware.

Best regards,
Krzysztof

---
Krzysztof Kozlowski (3):
      iommu: omap: Drop redundant check if ti,syscon-mmuconfig exists
      iommu: omap: Use syscon_regmap_lookup_by_phandle_args
      iommu: mtk_iommu_v1: Simplify by dropping local 'mtk_mapping' variable

 drivers/iommu/mtk_iommu_v1.c |  4 +---
 drivers/iommu/omap-iommu.c   | 24 +++++-------------------
 2 files changed, 6 insertions(+), 22 deletions(-)
---
base-commit: 393d0c54cae31317deaa9043320c5fd9454deabc
change-id: 20250111-syscon-phandle-args-iommu-2ea162b223a4

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>



From krzysztof.kozlowski at linaro.org  Thu May  1 09:36:55 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Thu, 01 May 2025 18:36:55 +0200
Subject: [PATCH RESEND v2 1/3] iommu: omap: Drop redundant check if
 ti,syscon-mmuconfig exists
In-Reply-To: <20250501-syscon-phandle-args-iommu-v2-0-5a3cab296972@linaro.org>
References: <20250501-syscon-phandle-args-iommu-v2-0-5a3cab296972@linaro.org>
Message-ID: <20250501-syscon-phandle-args-iommu-v2-1-5a3cab296972@linaro.org>

The syscon_regmap_lookup_by_phandle() will fail if property does not
exist, so doing of_property_read_bool() earlier is redundant.  Drop that
check and move error message to syscon_regmap_lookup_by_phandle() error
case while converting it to dev_err_probe().

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/iommu/omap-iommu.c | 14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c
index 3c62337f43c67720a15b67e8b610da7886f6f39c..4448c0a512137c79195112eea25d762266c77bc3 100644
--- a/drivers/iommu/omap-iommu.c
+++ b/drivers/iommu/omap-iommu.c
@@ -1123,23 +1123,15 @@ static int omap_iommu_dra7_get_dsp_system_cfg(struct platform_device *pdev,
 					      struct omap_iommu *obj)
 {
 	struct device_node *np = pdev->dev.of_node;
-	int ret;
 
 	if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
 		return 0;
 
-	if (!of_property_read_bool(np, "ti,syscon-mmuconfig")) {
-		dev_err(&pdev->dev, "ti,syscon-mmuconfig property is missing\n");
-		return -EINVAL;
-	}
-
 	obj->syscfg =
 		syscon_regmap_lookup_by_phandle(np, "ti,syscon-mmuconfig");
-	if (IS_ERR(obj->syscfg)) {
-		/* can fail with -EPROBE_DEFER */
-		ret = PTR_ERR(obj->syscfg);
-		return ret;
-	}
+	if (IS_ERR(obj->syscfg))
+		return dev_err_probe(&pdev->dev, PTR_ERR(obj->syscfg),
+				     "ti,syscon-mmuconfig property is missing\n");
 
 	if (of_property_read_u32_index(np, "ti,syscon-mmuconfig", 1,
 				       &obj->id)) {

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Thu May  1 09:36:56 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Thu, 01 May 2025 18:36:56 +0200
Subject: [PATCH RESEND v2 2/3] iommu: omap: Use
 syscon_regmap_lookup_by_phandle_args
In-Reply-To: <20250501-syscon-phandle-args-iommu-v2-0-5a3cab296972@linaro.org>
References: <20250501-syscon-phandle-args-iommu-v2-0-5a3cab296972@linaro.org>
Message-ID: <20250501-syscon-phandle-args-iommu-v2-2-5a3cab296972@linaro.org>

Use syscon_regmap_lookup_by_phandle_args() which is a wrapper over
syscon_regmap_lookup_by_phandle() combined with getting the syscon
argument.  Except simpler code this annotates within one line that given
phandle has arguments, so grepping for code would be easier.

There is also no real benefit in printing errors on missing syscon
argument, because this is done just too late: runtime check on
static/build-time data.  Dtschema and Devicetree bindings offer the
static/build-time check for this already.

Reviewed-by: Robin Murphy <robin.murphy at arm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/iommu/omap-iommu.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c
index 4448c0a512137c79195112eea25d762266c77bc3..30fdbabbc9c652990e6cd31d3c0a1a06633df9e6 100644
--- a/drivers/iommu/omap-iommu.c
+++ b/drivers/iommu/omap-iommu.c
@@ -1127,18 +1127,12 @@ static int omap_iommu_dra7_get_dsp_system_cfg(struct platform_device *pdev,
 	if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
 		return 0;
 
-	obj->syscfg =
-		syscon_regmap_lookup_by_phandle(np, "ti,syscon-mmuconfig");
+	obj->syscfg = syscon_regmap_lookup_by_phandle_args(np, "ti,syscon-mmuconfig",
+							   1, &obj->id);
 	if (IS_ERR(obj->syscfg))
 		return dev_err_probe(&pdev->dev, PTR_ERR(obj->syscfg),
 				     "ti,syscon-mmuconfig property is missing\n");
 
-	if (of_property_read_u32_index(np, "ti,syscon-mmuconfig", 1,
-				       &obj->id)) {
-		dev_err(&pdev->dev, "couldn't get the IOMMU instance id within subsystem\n");
-		return -EINVAL;
-	}
-
 	if (obj->id != 0 && obj->id != 1) {
 		dev_err(&pdev->dev, "invalid IOMMU instance id\n");
 		return -EINVAL;

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Thu May  1 09:36:57 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Thu, 01 May 2025 18:36:57 +0200
Subject: [PATCH RESEND v2 3/3] iommu: mtk_iommu_v1: Simplify by dropping
 local 'mtk_mapping' variable
In-Reply-To: <20250501-syscon-phandle-args-iommu-v2-0-5a3cab296972@linaro.org>
References: <20250501-syscon-phandle-args-iommu-v2-0-5a3cab296972@linaro.org>
Message-ID: <20250501-syscon-phandle-args-iommu-v2-3-5a3cab296972@linaro.org>

Storing 'data->mapping' in local variable in
mtk_iommu_v1_probe_finalize() does not make the code easier to read.
Use the 'data->mapping' directly.

ARM64 W=1 builds also complain with:

  mtk_iommu_v1.c:512:28: error: variable 'mtk_mapping' set but not used [-Werror,-Wunused-but-set-variable]

but this is not being fixed here and 'data' still won't be used in such
compile test.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

---

Old warning is change now to:

  error: variable 'data' set but not used [-Werror,-Wunused-but-set-variable]
---
 drivers/iommu/mtk_iommu_v1.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c
index 66824982e05fbfdda224276ad41b90f9d5f9ca4e..bbe3e9d901c69ac6405d9549a4481fc80f1adb80 100644
--- a/drivers/iommu/mtk_iommu_v1.c
+++ b/drivers/iommu/mtk_iommu_v1.c
@@ -509,14 +509,12 @@ static struct iommu_device *mtk_iommu_v1_probe_device(struct device *dev)
 
 static void mtk_iommu_v1_probe_finalize(struct device *dev)
 {
-	struct dma_iommu_mapping *mtk_mapping;
 	struct mtk_iommu_v1_data *data;
 	int err;
 
 	data        = dev_iommu_priv_get(dev);
-	mtk_mapping = data->mapping;
 
-	err = arm_iommu_attach_device(dev, mtk_mapping);
+	err = arm_iommu_attach_device(dev, data->mapping);
 	if (err)
 		dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n");
 }

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Thu May  1 09:39:06 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Thu, 1 May 2025 18:39:06 +0200
Subject: [PATCH RESEND v2 0/3] iommu: omap: Simplify few things
In-Reply-To: <20250501-syscon-phandle-args-iommu-v2-0-5a3cab296972@linaro.org>
References: <20250501-syscon-phandle-args-iommu-v2-0-5a3cab296972@linaro.org>
Message-ID: <af3e3007-edfc-4fdc-82cb-38457ba60d3f@linaro.org>

On 01/05/2025 18:36, Krzysztof Kozlowski wrote:
> Changes in v2:
> - Combine patches #1 and #2, add dev_err_probe() and drop the comment
>   (resolving Robin's comment)
> - New patch: iommu: mtk_iommu_v1: Simplify by dropping local 'mtk_mapping' variable
> - Rb tag
> - Link to resend of v1: https://lore.kernel.org/r/20250212-syscon-phandle-args-iommu-v1-0-c3fab486b426 at linaro.org
> - Link to v1: https://lore.kernel.org/r/20250111-syscon-phandle-args-iommu-v1-0-3767dee585a6 at linaro.org
> 
> Few code simplifications without functional impact.  Not tested on
> hardware.

I forgot to drop the subject prefix from b4 - this is not a resend, just
v2. Apologies.

Best regards,
Krzysztof


From krzysztof.kozlowski at linaro.org  Thu May  1 09:39:10 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Thu, 1 May 2025 18:39:10 +0200
Subject: [PATCH RESEND v2 0/3] iommu: omap: Simplify few things
In-Reply-To: <20250501-syscon-phandle-args-iommu-v2-0-5a3cab296972@linaro.org>
References: <20250501-syscon-phandle-args-iommu-v2-0-5a3cab296972@linaro.org>
Message-ID: <53e51779-1e05-48d9-971a-efe8f907e12e@linaro.org>

On 01/05/2025 18:36, Krzysztof Kozlowski wrote:
> Changes in v2:
> - Combine patches #1 and #2, add dev_err_probe() and drop the comment
>   (resolving Robin's comment)
> - New patch: iommu: mtk_iommu_v1: Simplify by dropping local 'mtk_mapping' variable
> - Rb tag
> - Link to resend of v1: https://lore.kernel.org/r/20250212-syscon-phandle-args-iommu-v1-0-c3fab486b426 at linaro.org
> - Link to v1: https://lore.kernel.org/r/20250111-syscon-phandle-args-iommu-v1-0-3767dee585a6 at linaro.org
> 
> Few code simplifications without functional impact.  Not tested on
> hardware.

I forgot to drop the subject prefix from b4 - this is not a resend, just
v2. Apologies.

Best regards,
Krzysztof


From nicolas.dufresne at collabora.com  Thu May  1 10:20:44 2025
From: nicolas.dufresne at collabora.com (Nicolas Dufresne)
Date: Thu, 01 May 2025 13:20:44 -0400
Subject: [PATCH v8 1/1] media: mediatek: jpeg: support 34bits
In-Reply-To: <20250424090824.5309-1-jianhua.lin@mediatek.com>
References: <20250424090824.5309-1-jianhua.lin@mediatek.com>
Message-ID: <b3ae9171a07b1af86160cc5094c24f7a05572be6.camel@collabora.com>

Le jeudi 24 avril 2025 ? 17:08 +0800, Jianhua Lin a ?crit?:
> The HW iommu is able to support a 34-bit iova address-space (16GB),
> enable this feature for the encoder/decoder driver by shifting the
> address by two bits and setting the extended address registers.
> 
> Signed-off-by: Jianhua Lin <jianhua.lin at mediatek.com>

Reviewed-by: Nicolas Dufresne <nicolas.dufresne at collabora.com>

> ---
> Changes compared with v7:
> - Fix reviewer's comments
> 	- Add lower_32_bits() to explicity write the lower 32bits address
> 
> ?.../platform/mediatek/jpeg/mtk_jpeg_core.c??? |? 5 +-
> ?.../platform/mediatek/jpeg/mtk_jpeg_core.h??? |? 4 +
> ?.../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c? | 73 ++++++++++++++-----
> ?.../platform/mediatek/jpeg/mtk_jpeg_dec_hw.h? |? 1 +
> ?.../platform/mediatek/jpeg/mtk_jpeg_dec_reg.h |? 8 ++
> ?.../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c? | 33 +++++++--
> ?.../platform/mediatek/jpeg/mtk_jpeg_enc_hw.h? |? 7 +-
> ?7 files changed, 104 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> index 7dd652e5b6d4..23692cd91e2c 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> @@ -1026,6 +1026,7 @@ static void mtk_jpeg_dec_device_run(void *priv)
> ?	spin_lock_irqsave(&jpeg->hw_lock, flags);
> ?	mtk_jpeg_dec_reset(jpeg->reg_base);
> ?	mtk_jpeg_dec_set_config(jpeg->reg_base,
> +				jpeg->variant->support_34bit,
> ?				&jpeg_src_buf->dec_param,
> ?				jpeg_src_buf->bs_size,
> ?				&bs,
> @@ -1570,7 +1571,8 @@ static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg_dev *jpeg)
> ?	src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
> ?	dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
> ?
> -	result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base);
> +	result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base,
> +						 jpeg->variant->support_34bit);
> ?	vb2_set_plane_payload(&dst_buf->vb2_buf, 0, result_size);
> ?
> ?	buf_state = VB2_BUF_STATE_DONE;
> @@ -1770,6 +1772,7 @@ static void mtk_jpegdec_worker(struct work_struct *work)
> ?	ctx->total_frame_num++;
> ?	mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base);
> ?	mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base,
> +				jpeg->variant->support_34bit,
> ?				&jpeg_src_buf->dec_param,
> ?				jpeg_src_buf->bs_size,
> ?				&bs,
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> index 8877eb39e807..02ed0ed5b736 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> @@ -34,6 +34,8 @@
> ?
> ?#define MTK_JPEG_MAX_EXIF_SIZE	(64 * 1024)
> ?
> +#define MTK_JPEG_ADDR_MASK GENMASK(1, 0)
> +
> ?/**
> ? * enum mtk_jpeg_ctx_state - states of the context state machine
> ? * @MTK_JPEG_INIT:		current state is initialized
> @@ -62,6 +64,7 @@ enum mtk_jpeg_ctx_state {
> ? * @cap_q_default_fourcc:	capture queue default fourcc
> ? * @multi_core:		mark jpeg hw is multi_core or not
> ? * @jpeg_worker:		jpeg dec or enc worker
> + * @support_34bit:	flag to check support for 34-bit DMA address
> ? */
> ?struct mtk_jpeg_variant {
> ?	struct clk_bulk_data *clks;
> @@ -78,6 +81,7 @@ struct mtk_jpeg_variant {
> ?	u32 cap_q_default_fourcc;
> ?	bool multi_core;
> ?	void (*jpeg_worker)(struct work_struct *work);
> +	bool support_34bit;
> ?};
> ?
> ?struct mtk_jpeg_src_buf {
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> index 2c5d74939d0a..e78e1d11093c 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> @@ -5,6 +5,8 @@
> ? *???????? Rick Chang <rick.chang at mediatek.com>
> ? */
> ?
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> ?#include <linux/clk.h>
> ?#include <linux/interrupt.h>
> ?#include <linux/irq.h>
> @@ -279,23 +281,43 @@ static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w,
> ?	writel(val, base + JPGDEC_REG_BRZ_FACTOR);
> ?}
> ?
> -static void mtk_jpeg_dec_set_dst_bank0(void __iomem *base, u32 addr_y,
> -				?????? u32 addr_u, u32 addr_v)
> +static void mtk_jpeg_dec_set_dst_bank0(void __iomem *base, bool support_34bit,
> +				?????? dma_addr_t addr_y, dma_addr_t addr_u, dma_addr_t addr_v)
> ?{
> +	u32 val;
> +
> ?	mtk_jpeg_verify_align(addr_y, 16, JPGDEC_REG_DEST_ADDR0_Y);
> -	writel(addr_y, base + JPGDEC_REG_DEST_ADDR0_Y);
> +	writel(lower_32_bits(addr_y), base + JPGDEC_REG_DEST_ADDR0_Y);
> ?	mtk_jpeg_verify_align(addr_u, 16, JPGDEC_REG_DEST_ADDR0_U);
> -	writel(addr_u, base + JPGDEC_REG_DEST_ADDR0_U);
> +	writel(lower_32_bits(addr_u), base + JPGDEC_REG_DEST_ADDR0_U);
> ?	mtk_jpeg_verify_align(addr_v, 16, JPGDEC_REG_DEST_ADDR0_V);
> -	writel(addr_v, base + JPGDEC_REG_DEST_ADDR0_V);
> +	writel(lower_32_bits(addr_v), base + JPGDEC_REG_DEST_ADDR0_V);
> +	if (support_34bit) {
> +		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_y));
> +		writel(val, base + JPGDEC_REG_DEST_ADDR0_Y_EXT);
> +		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_u));
> +		writel(val, base + JPGDEC_REG_DEST_ADDR0_U_EXT);
> +		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_v));
> +		writel(val, base + JPGDEC_REG_DEST_ADDR0_V_EXT);
> +	}
> ?}
> ?
> -static void mtk_jpeg_dec_set_dst_bank1(void __iomem *base, u32 addr_y,
> -				?????? u32 addr_u, u32 addr_v)
> +static void mtk_jpeg_dec_set_dst_bank1(void __iomem *base, bool support_34bit,
> +				?????? dma_addr_t addr_y, dma_addr_t addr_u, dma_addr_t addr_v)
> ?{
> -	writel(addr_y, base + JPGDEC_REG_DEST_ADDR1_Y);
> -	writel(addr_u, base + JPGDEC_REG_DEST_ADDR1_U);
> -	writel(addr_v, base + JPGDEC_REG_DEST_ADDR1_V);
> +	u32 val;
> +
> +	writel(lower_32_bits(addr_y), base + JPGDEC_REG_DEST_ADDR1_Y);
> +	writel(lower_32_bits(addr_u), base + JPGDEC_REG_DEST_ADDR1_U);
> +	writel(lower_32_bits(addr_v), base + JPGDEC_REG_DEST_ADDR1_V);
> +	if (support_34bit) {
> +		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_y));
> +		writel(val, base + JPGDEC_REG_DEST_ADDR1_Y_EXT);
> +		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_u));
> +		writel(val, base + JPGDEC_REG_DEST_ADDR1_U_EXT);
> +		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_v));
> +		writel(val, base + JPGDEC_REG_DEST_ADDR1_V_EXT);
> +	}
> ?}
> ?
> ?static void mtk_jpeg_dec_set_mem_stride(void __iomem *base, u32 stride_y,
> @@ -322,18 +344,30 @@ static void mtk_jpeg_dec_set_dec_mode(void __iomem *base, u32 mode)
> ?	writel(mode & 0x03, base + JPGDEC_REG_OPERATION_MODE);
> ?}
> ?
> -static void mtk_jpeg_dec_set_bs_write_ptr(void __iomem *base, u32 ptr)
> +static void mtk_jpeg_dec_set_bs_write_ptr(void __iomem *base, bool support_34bit, dma_addr_t ptr)
> ?{
> +	u32 val;
> +
> ?	mtk_jpeg_verify_align(ptr, 16, JPGDEC_REG_FILE_BRP);
> -	writel(ptr, base + JPGDEC_REG_FILE_BRP);
> +	writel(lower_32_bits(ptr), base + JPGDEC_REG_FILE_BRP);
> +	if (support_34bit) {
> +		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(ptr));
> +		writel(val, base + JPGDEC_REG_FILE_BRP_EXT);
> +	}
> ?}
> ?
> -static void mtk_jpeg_dec_set_bs_info(void __iomem *base, u32 addr, u32 size,
> -				???? u32 bitstream_size)
> +static void mtk_jpeg_dec_set_bs_info(void __iomem *base, bool support_34bit,
> +				???? dma_addr_t addr, u32 size, u32 bitstream_size)
> ?{
> +	u32 val;
> +
> ?	mtk_jpeg_verify_align(addr, 16, JPGDEC_REG_FILE_ADDR);
> ?	mtk_jpeg_verify_align(size, 128, JPGDEC_REG_FILE_TOTAL_SIZE);
> -	writel(addr, base + JPGDEC_REG_FILE_ADDR);
> +	writel(lower_32_bits(addr), base + JPGDEC_REG_FILE_ADDR);
> +	if (support_34bit) {
> +		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr));
> +		writel(val, base + JPGDEC_REG_FILE_ADDR_EXT);
> +	}
> ?	writel(size, base + JPGDEC_REG_FILE_TOTAL_SIZE);
> ?	writel(bitstream_size, base + JPGDEC_REG_BIT_STREAM_SIZE);
> ?}
> @@ -404,6 +438,7 @@ static void mtk_jpeg_dec_set_sampling_factor(void __iomem *base, u32 comp_num,
> ?}
> ?
> ?void mtk_jpeg_dec_set_config(void __iomem *base,
> +			???? bool support_34bits,
> ?			???? struct mtk_jpeg_dec_param *cfg,
> ?			???? u32 bitstream_size,
> ?			???? struct mtk_jpeg_bs *bs,
> @@ -413,8 +448,8 @@ void mtk_jpeg_dec_set_config(void __iomem *base,
> ?	mtk_jpeg_dec_set_dec_mode(base, 0);
> ?	mtk_jpeg_dec_set_comp0_du(base, cfg->unit_num);
> ?	mtk_jpeg_dec_set_total_mcu(base, cfg->total_mcu);
> -	mtk_jpeg_dec_set_bs_info(base, bs->str_addr, bs->size, bitstream_size);
> -	mtk_jpeg_dec_set_bs_write_ptr(base, bs->end_addr);
> +	mtk_jpeg_dec_set_bs_info(base, support_34bits, bs->str_addr, bs->size, bitstream_size);
> +	mtk_jpeg_dec_set_bs_write_ptr(base, support_34bits, bs->end_addr);
> ?	mtk_jpeg_dec_set_du_membership(base, cfg->membership, 1,
> ?				?????? (cfg->comp_num == 1) ? 1 : 0);
> ?	mtk_jpeg_dec_set_comp_id(base, cfg->comp_id[0], cfg->comp_id[1],
> @@ -432,9 +467,9 @@ void mtk_jpeg_dec_set_config(void __iomem *base,
> ?				??? cfg->mem_stride[1]);
> ?	mtk_jpeg_dec_set_img_stride(base, cfg->img_stride[0],
> ?				??? cfg->img_stride[1]);
> -	mtk_jpeg_dec_set_dst_bank0(base, fb->plane_addr[0],
> +	mtk_jpeg_dec_set_dst_bank0(base, support_34bits, fb->plane_addr[0],
> ?				?? fb->plane_addr[1], fb->plane_addr[2]);
> -	mtk_jpeg_dec_set_dst_bank1(base, 0, 0, 0);
> +	mtk_jpeg_dec_set_dst_bank1(base, support_34bits, 0, 0, 0);
> ?	mtk_jpeg_dec_set_dma_group(base, cfg->dma_mcu, cfg->dma_group,
> ?				?? cfg->dma_last_mcu);
> ?	mtk_jpeg_dec_set_pause_mcu_idx(base, cfg->total_mcu);
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h
> index 8c31c6b12417..2948c9c300a4 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h
> @@ -71,6 +71,7 @@ int mtk_jpeg_dec_fill_param(struct mtk_jpeg_dec_param *param);
> ?u32 mtk_jpeg_dec_get_int_status(void __iomem *dec_reg_base);
> ?u32 mtk_jpeg_dec_enum_result(u32 irq_result);
> ?void mtk_jpeg_dec_set_config(void __iomem *base,
> +			???? bool support_34bits,
> ?			???? struct mtk_jpeg_dec_param *cfg,
> ?			???? u32 bitstream_size,
> ?			???? struct mtk_jpeg_bs *bs,
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h
> index 27b7711ca341..e94f52de7c69 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h
> @@ -46,5 +46,13 @@
> ?#define JPGDEC_REG_INTERRUPT_STATUS	0x0274
> ?#define JPGDEC_REG_STATUS		0x0278
> ?#define JPGDEC_REG_BIT_STREAM_SIZE	0x0344
> +#define JPGDEC_REG_DEST_ADDR0_Y_EXT	0x0360
> +#define JPGDEC_REG_DEST_ADDR0_U_EXT	0x0364
> +#define JPGDEC_REG_DEST_ADDR0_V_EXT	0x0368
> +#define JPGDEC_REG_DEST_ADDR1_Y_EXT	0x036c
> +#define JPGDEC_REG_DEST_ADDR1_U_EXT	0x0370
> +#define JPGDEC_REG_DEST_ADDR1_V_EXT	0x0374
> +#define JPGDEC_REG_FILE_ADDR_EXT	0x0378
> +#define JPGDEC_REG_FILE_BRP_EXT		0x037c
> ?
> ?#endif /* _MTK_JPEG_REG_H */
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
> index f8fa3b841ccf..9ab27aee302a 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
> @@ -5,6 +5,8 @@
> ? *
> ? */
> ?
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> ?#include <linux/clk.h>
> ?#include <linux/interrupt.h>
> ?#include <linux/irq.h>
> @@ -62,9 +64,9 @@ void mtk_jpeg_enc_reset(void __iomem *base)
> ?}
> ?EXPORT_SYMBOL_GPL(mtk_jpeg_enc_reset);
> ?
> -u32 mtk_jpeg_enc_get_file_size(void __iomem *base)
> +u32 mtk_jpeg_enc_get_file_size(void __iomem *base, bool support_34bit)
> ?{
> -	return readl(base + JPEG_ENC_DMA_ADDR0) -
> +	return (readl(base + JPEG_ENC_DMA_ADDR0) << ((support_34bit) ? 2 : 0)) -
> ?	?????? readl(base + JPEG_ENC_DST_ADDR0);
> ?}
> ?EXPORT_SYMBOL_GPL(mtk_jpeg_enc_get_file_size);
> @@ -84,14 +86,24 @@ void mtk_jpeg_set_enc_src(struct mtk_jpeg_ctx *ctx,? void __iomem *base,
> ?{
> ?	int i;
> ?	dma_addr_t dma_addr;
> +	u32 addr_ext;
> +	bool support_34bit = ctx->jpeg->variant->support_34bit;
> ?
> ?	for (i = 0; i < src_buf->num_planes; i++) {
> ?		dma_addr = vb2_dma_contig_plane_dma_addr(src_buf, i) +
> ?			?? src_buf->planes[i].data_offset;
> -		if (!i)
> -			writel(dma_addr, base + JPEG_ENC_SRC_LUMA_ADDR);
> +		if (i == 0)
> +			writel(lower_32_bits(dma_addr), base + JPEG_ENC_SRC_LUMA_ADDR);
> ?		else
> -			writel(dma_addr, base + JPEG_ENC_SRC_CHROMA_ADDR);
> +			writel(lower_32_bits(dma_addr), base + JPEG_ENC_SRC_CHROMA_ADDR);
> +
> +		if (support_34bit) {
> +			addr_ext = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(dma_addr));
> +			if (i == 0)
> +				writel(addr_ext, base + JPEG_ENC_SRC_LUMA_ADDR_EXT);
> +			else
> +				writel(addr_ext, base + JPEG_ENC_SRC_CHRO_ADDR_EXT);
> +		}
> ?	}
> ?}
> ?EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_src);
> @@ -103,6 +115,8 @@ void mtk_jpeg_set_enc_dst(struct mtk_jpeg_ctx *ctx, void __iomem *base,
> ?	size_t size;
> ?	u32 dma_addr_offset;
> ?	u32 dma_addr_offsetmask;
> +	u32 addr_ext;
> +	bool support_34bit = ctx->jpeg->variant->support_34bit;
> ?
> ?	dma_addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
> ?	dma_addr_offset = ctx->enable_exif ? MTK_JPEG_MAX_EXIF_SIZE : 0;
> @@ -113,6 +127,12 @@ void mtk_jpeg_set_enc_dst(struct mtk_jpeg_ctx *ctx, void __iomem *base,
> ?	writel(dma_addr_offsetmask & 0xf, base + JPEG_ENC_BYTE_OFFSET_MASK);
> ?	writel(dma_addr & ~0xf, base + JPEG_ENC_DST_ADDR0);
> ?	writel((dma_addr + size) & ~0xf, base + JPEG_ENC_STALL_ADDR0);
> +
> +	if (support_34bit) {
> +		addr_ext = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(dma_addr));
> +		writel(addr_ext, base + JPEG_ENC_DEST_ADDR0_EXT);
> +		writel(addr_ext + size, base + JPEG_ENC_STALL_ADDR0_EXT);
> +	}
> ?}
> ?EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_dst);
> ?
> @@ -278,7 +298,8 @@ static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
> ?	if (!(irq_status & JPEG_ENC_INT_STATUS_DONE))
> ?		dev_warn(jpeg->dev, "Jpg Enc occurs unknown Err.");
> ?
> -	result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base);
> +	result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base,
> +						 ctx->jpeg->variant->support_34bit);
> ?	vb2_set_plane_payload(&dst_buf->vb2_buf, 0, result_size);
> ?	buf_state = VB2_BUF_STATE_DONE;
> ?	v4l2_m2m_buf_done(src_buf, buf_state);
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.h
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.h
> index 61c60e4e58ea..31ec9030ae88 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.h
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.h
> @@ -68,6 +68,11 @@
> ?#define JPEG_ENC_DCM_CTRL		0x300
> ?#define JPEG_ENC_CODEC_SEL		0x314
> ?#define JPEG_ENC_ULTRA_THRES		0x318
> +#define JPEG_ENC_SRC_LUMA_ADDR_EXT????? 0x584
> +#define JPEG_ENC_SRC_CHRO_ADDR_EXT????? 0x588
> +#define JPEG_ENC_Q_TBL_ADDR_EXT???????? 0x58C
> +#define JPEG_ENC_DEST_ADDR0_EXT???????? 0x590
> +#define JPEG_ENC_STALL_ADDR0_EXT??????? 0x594
> ?
> ?/**
> ? * struct mtk_jpeg_enc_qlt - JPEG encoder quality data
> @@ -80,7 +85,7 @@ struct mtk_jpeg_enc_qlt {
> ?};
> ?
> ?void mtk_jpeg_enc_reset(void __iomem *base);
> -u32 mtk_jpeg_enc_get_file_size(void __iomem *base);
> +u32 mtk_jpeg_enc_get_file_size(void __iomem *base, bool support_34bit);
> ?void mtk_jpeg_enc_start(void __iomem *enc_reg_base);
> ?void mtk_jpeg_set_enc_src(struct mtk_jpeg_ctx *ctx,? void __iomem *base,
> ?			? struct vb2_buffer *src_buf);


From sven at svenpeter.dev  Thu May  1 12:07:44 2025
From: sven at svenpeter.dev (Sven Peter)
Date: Thu, 01 May 2025 21:07:44 +0200
Subject: [PATCH 3/7] iommu: Remove ops.pgsize_bitmap from drivers that don't use it
In-Reply-To: <3-v1-7c5282b0c334+2db-iommu_rm_ops_pgsize_jgg@nvidia.com>
References: <3-v1-7c5282b0c334+2db-iommu_rm_ops_pgsize_jgg@nvidia.com>
Message-ID: <38706b77-4e58-4dfb-add3-814746f4a3c5@app.fastmail.com>

On Tue, Apr 29, 2025, at 16:34, Jason Gunthorpe wrote:
> These drivers all set the domain->pgsize_bitmap in their
> domain_alloc_paging() functions, so the ops value is never used. Delete
> it.
>
> Signed-off-by: Jason Gunthorpe <jgg at nvidia.com>
> ---
>  drivers/iommu/apple-dart.c       | 1 -
>  drivers/iommu/intel/iommu.c      | 1 -
>  drivers/iommu/iommufd/selftest.c | 1 -
>  drivers/iommu/riscv/iommu.c      | 1 -
>  drivers/iommu/virtio-iommu.c     | 6 ++----
>  5 files changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/iommu/apple-dart.c b/drivers/iommu/apple-dart.c
> index 757d24f67ad45a..190f28d7661515 100644
> --- a/drivers/iommu/apple-dart.c
> +++ b/drivers/iommu/apple-dart.c
> @@ -991,7 +991,6 @@ static const struct iommu_ops apple_dart_iommu_ops = {
>  	.of_xlate = apple_dart_of_xlate,
>  	.def_domain_type = apple_dart_def_domain_type,
>  	.get_resv_regions = apple_dart_get_resv_regions,
> -	.pgsize_bitmap = -1UL, /* Restricted during dart probe */
>  	.owner = THIS_MODULE,
>  	.default_domain_ops = &(const struct iommu_domain_ops) {
>  		.attach_dev	= apple_dart_attach_dev_paging,

Reviewed-by: Sven Peter <sven at svenpeter.dev> # for Apple DART



Best,


Sven


From patchwork-bot+bluetooth at kernel.org  Thu May  1 12:10:28 2025
From: patchwork-bot+bluetooth at kernel.org (patchwork-bot+bluetooth at kernel.org)
Date: Thu, 01 May 2025 19:10:28 +0000
Subject: [PATCH v1] Bluetooth: btusb: Add new VID/PID 13d3/3630 for MT7925
In-Reply-To: <20250429101605.2862004-1-jiande.lu@mediatek.com>
References: <20250429101605.2862004-1-jiande.lu@mediatek.com>
Message-ID: <174612662826.3052720.2548130502833643921.git-patchwork-notify@kernel.org>

Hello:

This patch was applied to bluetooth/bluetooth-next.git (master)
by Luiz Augusto von Dentz <luiz.von.dentz at intel.com>:

On Tue, 29 Apr 2025 18:16:05 +0800 you wrote:
> Add VID 13d3 & PID 3630 for MediaTek MT7925 USB Bluetooth chip.
> 
> The information in /sys/kernel/debug/usb/devices about the Bluetooth
> device is listed as the below.
> 
> T:  Bus=07 Lev=01 Prnt=01 Port=10 Cnt=02 Dev#=  2 Spd=480  MxCh= 0
> D:  Ver= 2.10 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs=  1
> P:  Vendor=13d3 ProdID=3630 Rev= 1.00
> S:  Manufacturer=MediaTek Inc.
> S:  Product=Wireless_Device
> S:  SerialNumber=000000000
> C:* #Ifs= 3 Cfg#= 1 Atr=e0 MxPwr=100mA
> A:  FirstIf#= 0 IfCount= 3 Cls=e0(wlcon) Sub=01 Prot=01
> I:* If#= 0 Alt= 0 #EPs= 3 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb
> E:  Ad=81(I) Atr=03(Int.) MxPS=  16 Ivl=125us
> E:  Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
> E:  Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
> I:* If#= 1 Alt= 0 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb
> E:  Ad=83(I) Atr=01(Isoc) MxPS=   0 Ivl=1ms
> E:  Ad=03(O) Atr=01(Isoc) MxPS=   0 Ivl=1ms
> I:  If#= 1 Alt= 1 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb
> E:  Ad=83(I) Atr=01(Isoc) MxPS=   9 Ivl=1ms
> E:  Ad=03(O) Atr=01(Isoc) MxPS=   9 Ivl=1ms
> I:  If#= 1 Alt= 2 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb
> E:  Ad=83(I) Atr=01(Isoc) MxPS=  17 Ivl=1ms
> E:  Ad=03(O) Atr=01(Isoc) MxPS=  17 Ivl=1ms
> I:  If#= 1 Alt= 3 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb
> E:  Ad=83(I) Atr=01(Isoc) MxPS=  25 Ivl=1ms
> E:  Ad=03(O) Atr=01(Isoc) MxPS=  25 Ivl=1ms
> I:  If#= 1 Alt= 4 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb
> E:  Ad=83(I) Atr=01(Isoc) MxPS=  33 Ivl=1ms
> E:  Ad=03(O) Atr=01(Isoc) MxPS=  33 Ivl=1ms
> I:  If#= 1 Alt= 5 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb
> E:  Ad=83(I) Atr=01(Isoc) MxPS=  49 Ivl=1ms
> E:  Ad=03(O) Atr=01(Isoc) MxPS=  49 Ivl=1ms
> I:  If#= 1 Alt= 6 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb
> E:  Ad=83(I) Atr=01(Isoc) MxPS=  63 Ivl=1ms
> E:  Ad=03(O) Atr=01(Isoc) MxPS=  63 Ivl=1ms
> I:* If#= 2 Alt= 0 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=(none)
> E:  Ad=8a(I) Atr=03(Int.) MxPS=  64 Ivl=125us
> E:  Ad=0a(O) Atr=03(Int.) MxPS=  64 Ivl=125us
> I:  If#= 2 Alt= 1 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=(none)
> E:  Ad=8a(I) Atr=03(Int.) MxPS= 512 Ivl=125us
> E:  Ad=0a(O) Atr=03(Int.) MxPS= 512 Ivl=125us
> 
> [...]

Here is the summary with links:
  - [v1] Bluetooth: btusb: Add new VID/PID 13d3/3630 for MT7925
    https://git.kernel.org/bluetooth/bluetooth-next/c/c03e896217f7

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
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From lorenzo at kernel.org  Thu May  1 13:47:06 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Thu, 1 May 2025 22:47:06 +0200
Subject: [PATCH net v4] net: airoha: Add missing filed to ppe_mbox_data
 struct
In-Reply-To: <20250501071518.50c92e8c@kernel.org>
References: <20250429-airoha-en7581-fix-ppe_mbox_data-v4-1-d2a8b901dad0@kernel.org>
 <20250501071518.50c92e8c@kernel.org>
Message-ID: <aBPdyn580lxUMJKz@lore-desk>

On May 01, Jakub Kicinski wrote:
> On Tue, 29 Apr 2025 16:17:41 +0200 Lorenzo Bianconi wrote:
> > Moreover, add __packed attribute to ppe_mbox_data struct definition and
> > make the fw layout padding explicit in init_info struct.
> 
> Why? everything looks naturally packed now :(

What I mean here is the padding in the ppe_mbox_data struct used by the fw running
on the NPU, not in the version used by the airoha_eth driver, got my point?
Sorry, re-reading it, it was not so clear, I agree.

Regards,
Lorenzo

> __packed also forces the compiler to assume the data is unaligned AFAIU.
> The recommended way to ensure the compiler doesn't insert padding is
> to do a compile time assert.
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From cjd at cjdns.fr  Thu May  1 16:28:42 2025
From: cjd at cjdns.fr (Caleb James DeLisle)
Date: Fri, 2 May 2025 01:28:42 +0200
Subject: [PATCH v4 1/7] dt-bindings: timer: Add EcoNet EN751221 "HPT" CPU
 Timer
In-Reply-To: <20250501-ludicrous-idealistic-camel-7bf8aa@kuoka>
References: <20250430133433.22222-1-cjd@cjdns.fr>
 <20250430133433.22222-2-cjd@cjdns.fr>
 <20250501-ludicrous-idealistic-camel-7bf8aa@kuoka>
Message-ID: <47aae905-1a89-44aa-a31f-6cbfc0eb6726@cjdns.fr>


On 01/05/2025 12:58, Krzysztof Kozlowski wrote:
> On Wed, Apr 30, 2025 at 01:34:27PM GMT, Caleb James DeLisle wrote:
>> Add device tree bindings for the so-called high-precision timer (HPT)
>> in the EcoNet EN751221 SoC.
>>
>> Signed-off-by: Caleb James DeLisle <cjd at cjdns.fr>
>> ---
>>   .../bindings/timer/econet,en751221-timer.yaml | 80 +++++++++++++++++++
>>   1 file changed, 80 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
>>
> What changed? Nothing explains dropping the tag.


Sorry I lost track of it, I will re-send with it attached again.

Thanks,

Caleb


>
> <form letter>
> This is a friendly reminder during the review process.
>
> It looks like you received a tag and forgot to add it.
>
> If you do not know the process, here is a short explanation:
> Please add Acked-by/Reviewed-by/Tested-by tags when posting new
> versions of patchset, under or above your Signed-off-by tag, unless
> patch changed significantly (e.g. new properties added to the DT
> bindings). Tag is "received", when provided in a message replied to you
> on the mailing list. Tools like b4 can help here. However, there's no
> need to repost patches *only* to add the tags. The upstream maintainer
> will do that for tags received on the version they apply.
>
> Please read:
> https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst#L577
>
> If a tag was not added on purpose, please state why and what changed.
> </form letter>
>
> Best regards,
> Krzysztof
>
>


From kuba at kernel.org  Thu May  1 17:41:40 2025
From: kuba at kernel.org (Jakub Kicinski)
Date: Thu, 1 May 2025 17:41:40 -0700
Subject: [PATCH net v4] net: airoha: Add missing filed to ppe_mbox_data
 struct
In-Reply-To: <aBPdyn580lxUMJKz@lore-desk>
References: <20250429-airoha-en7581-fix-ppe_mbox_data-v4-1-d2a8b901dad0@kernel.org>
	<20250501071518.50c92e8c@kernel.org>
	<aBPdyn580lxUMJKz@lore-desk>
Message-ID: <20250501174140.6dc31b36@kernel.org>

On Thu, 1 May 2025 22:47:06 +0200 Lorenzo Bianconi wrote:
> On May 01, Jakub Kicinski wrote:
> > On Tue, 29 Apr 2025 16:17:41 +0200 Lorenzo Bianconi wrote:  
> > > Moreover, add __packed attribute to ppe_mbox_data struct definition and
> > > make the fw layout padding explicit in init_info struct.  
> > 
> > Why? everything looks naturally packed now :(  
> 
> What I mean here is the padding in the ppe_mbox_data struct used by the fw running
> on the NPU, not in the version used by the airoha_eth driver, got my point?
> Sorry, re-reading it, it was not so clear, I agree.

You mean adding the "u8 rsv[3];" ? that is fine.
I don't get why we also need to add the 3 __packed


From patchwork-bot+netdevbpf at kernel.org  Thu May  1 18:10:37 2025
From: patchwork-bot+netdevbpf at kernel.org (patchwork-bot+netdevbpf at kernel.org)
Date: Fri, 02 May 2025 01:10:37 +0000
Subject: [PATCH net-next v2] net: ethernet: mtk_eth_soc: add support for
 MT7988 internal 2.5G PHY
In-Reply-To: <9072cefbff6db969720672ec98ed5cef65e8218c.1745715380.git.daniel@makrotopia.org>
References: <9072cefbff6db969720672ec98ed5cef65e8218c.1745715380.git.daniel@makrotopia.org>
Message-ID: <174614823799.3123530.13600729204126295734.git-patchwork-notify@kernel.org>

Hello:

This patch was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba at kernel.org>:

On Sun, 27 Apr 2025 02:01:29 +0100 you wrote:
> The MediaTek MT7988 SoC comes with an single built-in Ethernet PHY for
> 2500Base-T/1000Base-T/100Base-TX/10Base-T link partners in addition to
> the built-in 1GE switch. The built-in PHY only supports full duplex.
> 
> Add muxes allowing to select GMAC2->2.5G PHY path and add basic support
> for XGMAC as the built-in 2.5G PHY is internally connected via XGMII.
> The XGMAC features will also be used by 5GBase-R, 10GBase-R and USXGMII
> SerDes modes which are going to be added once support for standalone PCS
> drivers is in place.
> 
> [...]

Here is the summary with links:
  - [net-next,v2] net: ethernet: mtk_eth_soc: add support for MT7988 internal 2.5G PHY
    https://git.kernel.org/netdev/net-next/c/51cf06ddafc9

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html




From ck.hu at mediatek.com  Thu May  1 23:11:54 2025
From: ck.hu at mediatek.com (=?utf-8?B?Q0sgSHUgKOiDoeS/iuWFiSk=?=)
Date: Fri, 2 May 2025 06:11:54 +0000
Subject: [PATCH v2 4/5] drm/mediatek: Add MDP-RSZ component support for
 MT8196
In-Reply-To: <20250421133835.508863-5-sunny.shen@mediatek.com>
References: <20250421133835.508863-1-sunny.shen@mediatek.com>
	 <20250421133835.508863-5-sunny.shen@mediatek.com>
Message-ID: <d5ba3c060744ab6ad188399550598718d036abfc.camel@mediatek.com>

On Mon, 2025-04-21 at 21:38 +0800, Sunny Shen wrote:
> Add MDP-RSZ component support for MT8196.

Reviewed-by: CK Hu <ck.hu at mediatek.com>

> 
> Signed-off-by: Sunny Shen <sunny.shen at mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 ++++++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  1 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 ++
>  3 files changed, 27 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> index 6628f5cd732a..04f13ca3601b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> @@ -46,6 +46,9 @@
>  #define DSC_BYPASS				BIT(4)
>  #define DSC_UFOE_SEL				BIT(16)
>  
> +#define DISP_REG_MDP_RSZ_INPUT_SIZE		0x0010
> +#define DISP_REG_MDP_RSZ_OUTPUT_SIZE		0x0014
> +
>  #define DISP_REG_OD_EN				0x0000
>  #define DISP_REG_OD_CFG				0x0020
>  #define OD_RELAYMODE				BIT(0)
> @@ -235,6 +238,19 @@ static void mtk_od_start(struct device *dev)
>  	writel(1, priv->regs + DISP_REG_OD_EN);
>  }
>  
> +static void mtk_mdp_rsz_config(struct device *dev, unsigned int w,
> +			       unsigned int h, unsigned int vrefresh,
> +			       unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> +	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +	/* Set size = 0 for bypass mode */
> +	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> +		      DISP_REG_MDP_RSZ_INPUT_SIZE);
> +	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> +		      DISP_REG_MDP_RSZ_OUTPUT_SIZE);
> +}
> +
>  static void mtk_postmask_config(struct device *dev, unsigned int w,
>  				unsigned int h, unsigned int vrefresh,
>  				unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -393,6 +409,12 @@ static const struct mtk_ddp_comp_funcs ddp_ovlsys_adaptor = {
>  	.get_num_formats = mtk_ovlsys_adaptor_get_num_formats,
>  };
>  
> +static const struct mtk_ddp_comp_funcs ddp_mdp_rsz = {
> +	.clk_enable = mtk_ddp_clk_enable,
> +	.clk_disable = mtk_ddp_clk_disable,
> +	.config = mtk_mdp_rsz_config,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_postmask = {
>  	.clk_enable = mtk_ddp_clk_enable,
>  	.clk_disable = mtk_ddp_clk_disable,
> @@ -456,6 +478,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>  	[MTK_DISP_DITHER] = "dither",
>  	[MTK_DISP_DSC] = "dsc",
>  	[MTK_DISP_GAMMA] = "gamma",
> +	[MTK_DISP_MDP_RSZ] = "mdp-rsz",
>  	[MTK_DISP_MERGE] = "merge",
>  	[MTK_DISP_MUTEX] = "mutex",
>  	[MTK_DISP_OD] = "od",
> @@ -515,6 +538,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
>  	[DDP_COMPONENT_DSI2]		= { MTK_DSI,			2, &ddp_dsi },
>  	[DDP_COMPONENT_DSI3]		= { MTK_DSI,			3, &ddp_dsi },
>  	[DDP_COMPONENT_GAMMA]		= { MTK_DISP_GAMMA,		0, &ddp_gamma },
> +	[DDP_COMPONENT_MDP_RSZ0]	= { MTK_DISP_MDP_RSZ,		0, &ddp_mdp_rsz},
>  	[DDP_COMPONENT_MERGE0]		= { MTK_DISP_MERGE,		0, &ddp_merge },
>  	[DDP_COMPONENT_MERGE1]		= { MTK_DISP_MERGE,		1, &ddp_merge },
>  	[DDP_COMPONENT_MERGE2]		= { MTK_DISP_MERGE,		2, &ddp_merge },
> diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> index badb42bd4f7c..87f573fcc903 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
>  	MTK_DISP_OVLSYS_ADAPTOR,
>  	MTK_DISP_OVL_2L,
>  	MTK_DISP_OVL_ADAPTOR,
> +	MTK_DISP_MDP_RSZ,
>  	MTK_DISP_POSTMASK,
>  	MTK_DISP_PWM,
>  	MTK_DISP_RDMA,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 70a7e6d06d4f..aa7eec1fc7e6 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -975,6 +975,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DSI },
>  	{ .compatible = "mediatek,mt8188-dsi",
>  	  .data = (void *)MTK_DSI },
> +	{ .compatible = "mediatek,mt8196-mdp-rsz",
> +	  .data = (void *)MTK_DISP_MDP_RSZ },
>  	{ }
>  };
>  


From lorenzo at kernel.org  Fri May  2 00:24:49 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Fri, 2 May 2025 09:24:49 +0200
Subject: [PATCH net v4] net: airoha: Add missing filed to ppe_mbox_data
 struct
In-Reply-To: <20250501174140.6dc31b36@kernel.org>
References: <20250429-airoha-en7581-fix-ppe_mbox_data-v4-1-d2a8b901dad0@kernel.org>
 <20250501071518.50c92e8c@kernel.org>
 <aBPdyn580lxUMJKz@lore-desk>
 <20250501174140.6dc31b36@kernel.org>
Message-ID: <aBRzQaonAK0IyAsu@lore-desk>

> On Thu, 1 May 2025 22:47:06 +0200 Lorenzo Bianconi wrote:
> > On May 01, Jakub Kicinski wrote:
> > > On Tue, 29 Apr 2025 16:17:41 +0200 Lorenzo Bianconi wrote:  
> > > > Moreover, add __packed attribute to ppe_mbox_data struct definition and
> > > > make the fw layout padding explicit in init_info struct.  
> > > 
> > > Why? everything looks naturally packed now :(  
> > 
> > What I mean here is the padding in the ppe_mbox_data struct used by the fw running
> > on the NPU, not in the version used by the airoha_eth driver, got my point?
> > Sorry, re-reading it, it was not so clear, I agree.
> 
> You mean adding the "u8 rsv[3];" ? that is fine.
> I don't get why we also need to add the 3 __packed

I agree the __packed attributes are not mandatory at the moment, we just agreed
with Jacob that is fine to add them. Do you prefer to get rid of them?

Regards,
Lorenzo
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From krzk at kernel.org  Fri May  2 01:34:42 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Fri, 2 May 2025 10:34:42 +0200
Subject: [PATCH v4 1/7] dt-bindings: timer: Add EcoNet EN751221 "HPT" CPU
 Timer
In-Reply-To: <20250430133433.22222-2-cjd@cjdns.fr>
References: <20250430133433.22222-1-cjd@cjdns.fr>
 <20250430133433.22222-2-cjd@cjdns.fr>
Message-ID: <6ae54415-aadb-4f26-bdae-63a036bff112@kernel.org>

On 30/04/2025 15:34, Caleb James DeLisle wrote:
> Add device tree bindings for the so-called high-precision timer (HPT)
> in the EcoNet EN751221 SoC.
> 
> Signed-off-by: Caleb James DeLisle <cjd at cjdns.fr>

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Best regards,
Krzysztof


From Qun-wei.Lin at mediatek.com  Fri May  2 02:16:01 2025
From: Qun-wei.Lin at mediatek.com (=?utf-8?B?UXVuLXdlaSBMaW4gKOael+e+pOW0tCk=?=)
Date: Fri, 2 May 2025 09:16:01 +0000
Subject: [PATCH] mm: Add Kcompressd for accelerated memory compression
In-Reply-To: <20250501140226.GE2020@cmpxchg.org>
References: <20250430082651.3152444-1-qun-wei.lin@mediatek.com>
	 <20250501140226.GE2020@cmpxchg.org>
Message-ID: <bf1db02cc0e7682e8f6eea4d0d61f6f249536163.camel@mediatek.com>

On Thu, 2025-05-01 at 10:02 -0400, Johannes Weiner wrote:


> External email : Please do not click links or open attachments until
you have verified the sender or the content.
> 
> 
> On Wed, Apr 30, 2025 at 04:26:41PM +0800, Qun-Wei Lin wrote:
> 
> > This patch series introduces a new mechanism called kcompressd to
> > improve the efficiency of memory reclaiming in the operating
system.
> > 
> > Problem:
> > ? In the current system, the kswapd thread is responsible for both
scanning
> > ? the LRU pages and handling memory compression tasks (such as
those
> > ? involving ZSWAP/ZRAM, if enabled). This combined responsibility
can lead
> > ? to significant performance bottlenecks, especially under high
memory
> > ? pressure. The kswapd thread becomes a single point of contention,
causing
> > ? delays in memory reclaiming and overall system performance
degradation.
> > 
> > Solution:
> > ? Introduced kcompressd to handle asynchronous compression during
memory
> > ? reclaim, improving efficiency by offloading compression tasks
from
> > ? kswapd. This allows kswapd to focus on its primary task of page
reclaim
> > ? without being burdened by the additional overhead of compression.
> > 
> > In our handheld devices, we found that applying this mechanism
under high
> > memory pressure scenarios can increase the rate of pgsteal_anon per
second
> > by over 260% compared to the situation with only kswapd.
Additionally, we
> > observed a reduction of over 50% in page allocation stall
occurrences,
> > further demonstrating the effectiveness of kcompressd in
alleviating memory
> > pressure and improving system responsiveness.
> 
> 
> Yes, I think parallelizing this work makes a lot of sense.
> 
> 
> > Co-developed-by: Barry Song
<[21cnbao at gmail.com](mailto:21cnbao at gmail.com)>
> > Signed-off-by: Barry Song
<[21cnbao at gmail.com](mailto:21cnbao at gmail.com)>
> > Signed-off-by: Qun-Wei Lin
<[qun-wei.lin at mediatek.com](mailto:qun-wei.lin at mediatek.com)>
> > Reference: Re: [PATCH 0/2] Improve Zram by separating compression
context from kswapd - Barry Song
> > ??????????
[https://lore.kernel.org/lkml/20250313093005.13998-1-21cnbao at gmail.com/](https://lore.kernel.org/lkml/20250313093005.13998-1-21cnbao at gmail.com/)
> > ---
> > ?include/linux/mmzone.h |? 6 ++++
> > ?mm/mm_init.c?????????? |? 1 +
> > ?mm/page_io.c?????????? | 71
++++++++++++++++++++++++++++++++++++++++++
> > ?mm/swap.h????????????? |? 6 ++++
> > ?mm/vmscan.c??????????? | 25 +++++++++++++++
> > ?5 files changed, 109 insertions(+)
> > 
> > diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
> > index 6ccec1bf2896..93c9195a54ae 100644
> > --- a/include/linux/mmzone.h
> > +++ b/include/linux/mmzone.h
> > @@ -23,6 +23,7 @@
> > ?#include <linux/page-flags.h>
> > ?#include <linux/local_lock.h>
> > ?#include <linux/zswap.h>
> > +#include <linux/kfifo.h>
> > ?#include <asm/page.h>
> > 
> > ?/* Free memory management - zoned buddy allocator.? */
> > @@ -1398,6 +1399,11 @@ typedef struct pglist_data {
> > 
> > ????? int kswapd_failures;??????????? /* Number of 'reclaimed == 0'
runs */
> > 
> > +#define KCOMPRESS_FIFO_SIZE 256
> > +???? wait_queue_head_t kcompressd_wait;
> > +???? struct task_struct *kcompressd;
> > +???? struct kfifo kcompress_fifo;
> 
> 
> The way you implemented this adds time-and-space overhead even on
> systems that don't have any sort of swap compression enabled.
>


To address the overhead concern, perhaps we can embed only a single
kcompressd pointer within pglist_data and perform lazy initialization
only when a zram device is added or zswap is enabled.


> That seems unnecessary. There is an existing method for asynchronous
> writeback, and pageout() is naturally fully set up to handle this.
> 
> IMO the better way to do this is to make zswap_store() (and
> zram_bio_write()?) asynchronous. Make those functions queue the work
> and wake the compression daemon, and then have the daemon call
> folio_end_writeback() / bio_endio() when it's done with it.



Perhaps we could add an enqueue/wake-upkcompressd interface and call it
within zswap_store() and zram_bio_write(). This would leverage the
existing obj_cgroup_may_zswap() check in zswap_store(), it solved the
problem that zswap is re-compressed too soon. as mentioned by Nhat.

In outline:

1. Per-node pointer in pglist_data:  

   typedef struct pglist_data {  
   ...  
   struct kcompressd_node *kcompressd;  
   ...  
   }

2. Global register/unregister hooks:  

   kcompressd_register_backend(): Register a new backend (zram/zswap).
   Initialize the kcompressd structure and kfifo if this is the first 
   call.
   
   kcompressd_unregister_backend(): Unregister a backend (zram/zswap).
   Use a per-node refcount and bitmap to track how manyzswap/zram   
   instances are active. If the last backend is unregistered, free   
   the kcompressd resources.

> > A net loss is possible, but kswapd can sometimes enter sleep
> > contexts,
> > allowing the parallel kcompressd thread to continue compression.
> > This could actually be a win. But I agree that additional testing
on
> > single-CPU machines may be necessary.
> 
> It could be disabled by the following if we discover any regression
> on
> single-CPU machines?
> 
> if (num_online_cpus() == 1)
>      return false;
>

   We can add this check in the register/unregister function.

3. Enqueue API:  

   kcompressd_enqueue_folio(folio) /kcompressd_enqueue_bio(bio): Push a
   job to the kcompressd?s FIFO and wake up the kcompressd daemon.

With this approach, there is zero runtime cost on nodes when no backend
is active and only one allocation per node.


Thank you for your feedback!  
Please let me know what you think.

Best Regards,  
Qun-wei




From jic23 at kernel.org  Fri May  2 02:25:10 2025
From: jic23 at kernel.org (Jonathan Cameron)
Date: Fri, 2 May 2025 10:25:10 +0100
Subject: [PATCH] dt-bindings: iio: adc: Add compatible for Dimensity
 1200 MT6893
In-Reply-To: <174527153072.2973088.9157423165074778113.robh@kernel.org>
References: <20250416120235.147889-1-angelogioacchino.delregno@collabora.com>
	<174527153072.2973088.9157423165074778113.robh@kernel.org>
Message-ID: <20250502102510.05a37520@jic23-huawei>

On Mon, 21 Apr 2025 16:38:51 -0500
"Rob Herring (Arm)" <robh at kernel.org> wrote:

> On Wed, 16 Apr 2025 14:02:35 +0200, AngeloGioacchino Del Regno wrote:
> > Add a compatible for the Dimensity 1200 (MT6893) SoC; The AUXADC
> > IP in this chip is fully compatible with the one found in MT8173.
> > 
> > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> > ---
> >  .../devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml      | 1 +
> >  1 file changed, 1 insertion(+)
> >   
> 
> Acked-by: Rob Herring (Arm) <robh at kernel.org>
> 

Applied.


From louisalexis.eyraud at collabora.com  Fri May  2 05:17:15 2025
From: louisalexis.eyraud at collabora.com (Louis-Alexis Eyraud)
Date: Fri, 02 May 2025 14:17:15 +0200
Subject: [PATCH v5 0/3] Add Mali GPU support for Mediatek MT8370 SoC
Message-ID: <20250502-mt8370-enable-gpu-v5-0-98e247b30151@collabora.com>

This patchset adds the support of the ARM Mali G57 MC2 GPU (Valhall-JM,
dual core), integrated in the Mediatek MT8370 SoC, to the panfrost
driver and to the mt8370.dtsi include file.

Since v4 patchset was sent, the [1] patchset adds in panfrost driver
the AARCH64_4K page table format support and enablement for Mediatek
SoC with integrated Arm Mali-G57, already supported in panfrost driver
(like MT8188, MT8192, MT8195, MT8390, MT8395...).
As MT8370 SoC is a less powerful variant of MT8390 (same GPU but with
one less core for MT8370), I've reworked the second patch
('drm/panfrost: Add support for Mali on the MT8370 SoC') to enable the
AARCH64_4K mode on this SoC as well by adding specific MT8370 platform
data to set the needed flag.
The previous patch revision uses MT8186 platform data because despite
having different GPU architecture (Mali G52 2EE MC2 for MT8186, making
them not compatible), using the same plaform data, for describing the
same power management features only, was okay.
But now, the platform data also contains the GPU configuration quirk
bitfield that needs to be modified to enable the AARCH64_4K page table
format, and in order not to change MT8186 behaviour, I add specific
MT8370 platform data.
I also dropped previous code-review trailers that this patch got
previously.

I've tested this patchset on a Mediatek Genio 510 EVK board,
with a kernel based on linux-next (tag: next-20250501).

The panfrost driver probed with the following messages:
```
panfrost 13000000.gpu: clock rate = 390000000
panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x0 status 0x0
panfrost 13000000.gpu: features: 00000000,000019f7, issues: 00000003,
  80000400
panfrost 13000000.gpu: Features: L2:0x08130206 Shader:0x00000000
  Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
panfrost 13000000.gpu: shader_present=0x5 l2_present=0x1
[drm] Initialized panfrost 1.3.0 for 13000000.gpu on minor 0
```

Running glmark2-es2-drm is also OK:
```
=======================================================
    glmark2 2023.01
=======================================================
    OpenGL Information
    GL_VENDOR:      Mesa
    GL_RENDERER:    Mali-G57 (Panfrost)
    GL_VERSION:     OpenGL ES 3.1 Mesa 25.0.3-1
    Surface Config: buf=32 r=8 g=8 b=8 a=8 depth=24 stencil=0 samples=0
    Surface Size:   1200x1920 fullscreen
=======================================================
[build] use-vbo=false: FPS: 952 FrameTime: 1.051 ms
[build] use-vbo=true: FPS: 983 FrameTime: 1.018 ms
[texture] texture-filter=nearest: FPS: 906 FrameTime: 1.105 ms
[texture] texture-filter=linear: FPS: 908 FrameTime: 1.102 ms
[texture] texture-filter=mipmap: FPS: 883 FrameTime: 1.134 ms
[shading] shading=gouraud: FPS: 838 FrameTime: 1.194 ms
[shading] shading=blinn-phong-inf: FPS: 778 FrameTime: 1.287 ms
[shading] shading=phong: FPS: 583 FrameTime: 1.717 ms
[shading] shading=cel: FPS: 553 FrameTime: 1.809 ms
[bump] bump-render=high-poly: FPS: 573 FrameTime: 1.747 ms
[bump] bump-render=normals: FPS: 868 FrameTime: 1.153 ms
[bump] bump-render=height: FPS: 707 FrameTime: 1.415 ms
[effect2d] kernel=0,1,0;1,-4,1;0,1,0;: FPS: 454 FrameTime: 2.204 ms
[effect2d] kernel=1,1,1,1,1;1,1,1,1,1;1,1,1,1,1;: FPS: 172 FrameTime:
  5.843 ms
[pulsar] light=false:quads=5:texture=false: FPS: 770 FrameTime:
  1.300 ms
[desktop] blur-radius=5:effect=blur:passes=1:separable=true:windows=4:
  FPS: 161 FrameTime: 6.235 ms
[desktop] effect=shadow:windows=4: FPS: 484 FrameTime: 2.069 ms
[buffer] columns=200:interleave=false:update-dispersion=0.9:update-fraction
  =0.5:update-method=map: FPS: 512 FrameTime: 1.955 ms
[buffer] columns=200:interleave=false:update-dispersion=0.9:update-fraction
  =0.5:update-method=subdata: FPS: 513 FrameTime: 1.952 ms
[buffer] columns=200:interleave=true:update-dispersion=0.9:update-fraction
  =0.5:update-method=map: FPS: 577 FrameTime: 1.735 ms
[ideas] speed=duration: FPS: 448 FrameTime: 2.235 ms
[jellyfish] <default>: FPS: 226 FrameTime: 4.440 ms
[terrain] <default>: FPS: 38 FrameTime: 26.861 ms
[shadow] <default>: FPS: 328 FrameTime: 3.051 ms
[refract] <default>: FPS: 72 FrameTime: 13.937 ms
[conditionals] fragment-steps=0:vertex-steps=0: FPS: 844 FrameTime:
  1.186 ms
[conditionals] fragment-steps=5:vertex-steps=0: FPS: 685 FrameTime: 
  1.462 ms
[conditionals] fragment-steps=0:vertex-steps=5: FPS: 833 FrameTime:
  1.201 ms
[function] fragment-complexity=low:fragment-steps=5: FPS: 830 FrameTime:
  1.205 ms
[function] fragment-complexity=medium:fragment-steps=5: FPS: 525 FrameTime:
  1.905 ms
[loop] fragment-loop=false:fragment-steps=5:vertex-steps=5: FPS: 837
  FrameTime: 1.195 ms
[loop] fragment-steps=5:fragment-uniform=false:vertex-steps=5: FPS: 835 
  FrameTime: 1.199 ms
[loop] fragment-steps=5:fragment-uniform=true:vertex-steps=5: FPS: 550
  FrameTime: 1.820 ms
=======================================================
                                  glmark2 Score: 611 
=======================================================
```

[1] https://lore.kernel.org/dri-devel/20250324185801.168664-1-ariel.dalessandro at collabora.com/

Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>
---
Changes in v5:
- Rebase on linux-next (tqg: next-2020501)
- Rework 'drm/panfrost: Add support for Mali on the MT8370 SoC' patch
  to have MT8370 support with its AARCH64_4K page table format support enabled 
- Drop code-review trailers from 'drm/panfrost: Add support for Mali on
  the MT8370 SoC' patch due to major changes in content and commit message
- Add ack trailer for 'dt-bindings: gpu: mali-bifrost: Add compatible 
  for MT8370 SoC' patch
- Add glmark2-es2-drm benchmark results in cover letter
- Link to v4: https://lore.kernel.org/r/20250211-mt8370-enable-gpu-v4-0-77deb7a75c23 at collabora.com

Changes in v4:
- Add warning comment in mt8370.dtsi about GPU node override
- Reword "dt-bindings: gpu: mali-bifrost: Add compatible for MT8370
  SoC" commit message
- Add code-review trailers
- Link to v3: https://lore.kernel.org/r/20250207-mt8370-enable-gpu-v3-0-75e9b902f9c1 at collabora.com

Changes in v3:
- Rebased on linux-next (tag: next-20250207)
- Remove prerequisite change/patch ids
- Reword commit messages to better explicit compatible needs
- Link to v2: https://lore.kernel.org/r/20250130-mt8370-enable-gpu-v2-0-c154d0815db5 at collabora.com

Changes in v2:
- Rework "drm/panfrost: Add support for Mali on the MT8370 SoC" to avoid
  data structure duplication, as requested by Krzysztof Kozlowski
- Reword commit messages to use imperative mood and make new compatible
  need more explicit
- Link to v1: https://lore.kernel.org/r/20250116-mt8370-enable-gpu-v1-0-0a6b78e925c8 at collabora.com

---
Louis-Alexis Eyraud (3):
      dt-bindings: gpu: mali-bifrost: Add compatible for MT8370 SoC
      drm/panfrost: Add support for Mali on the MT8370 SoC
      arm64: dts: mediatek: mt8370: Enable gpu support

 .../devicetree/bindings/gpu/arm,mali-bifrost.yaml        |  5 ++++-
 arch/arm64/boot/dts/mediatek/mt8370.dtsi                 | 16 ++++++++++++++++
 drivers/gpu/drm/panfrost/panfrost_drv.c                  | 11 +++++++++++
 3 files changed, 31 insertions(+), 1 deletion(-)
---
base-commit: 1c51b1ba38c07e4f999802eb708bf798dd5f5d1b
change-id: 20250115-mt8370-enable-gpu-3b6f595fa63d

Best regards,
-- 
Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>



From louisalexis.eyraud at collabora.com  Fri May  2 05:17:16 2025
From: louisalexis.eyraud at collabora.com (Louis-Alexis Eyraud)
Date: Fri, 02 May 2025 14:17:16 +0200
Subject: [PATCH v5 1/3] dt-bindings: gpu: mali-bifrost: Add compatible for
 MT8370 SoC
In-Reply-To: <20250502-mt8370-enable-gpu-v5-0-98e247b30151@collabora.com>
References: <20250502-mt8370-enable-gpu-v5-0-98e247b30151@collabora.com>
Message-ID: <20250502-mt8370-enable-gpu-v5-1-98e247b30151@collabora.com>

Add a compatible for the MediaTek MT8370 SoC, with an
integrated ARM Mali G57 MC2 GPU (Valhall-JM, dual core).
None of the already existing SoC specific compatibles is usable as
fallback, as those either do not match the number of cores (and number
of power domains), or are for a different GPU architecture.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Acked-by: Conor Dooley <conor.dooley at microchip.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>
---
 Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
index 019bd28a29f19bb4f7a9c32434b208b6d04db221..5726b79fd0f9de8914f724929f462409e088ec31 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
@@ -40,6 +40,7 @@ properties:
           - enum:
               - mediatek,mt8188-mali
               - mediatek,mt8192-mali
+              - mediatek,mt8370-mali
           - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
 
   reg:
@@ -221,7 +222,9 @@ allOf:
       properties:
         compatible:
           contains:
-            const: mediatek,mt8186-mali
+            enum:
+              - mediatek,mt8186-mali
+              - mediatek,mt8370-mali
     then:
       properties:
         power-domains:

-- 
2.49.0



From louisalexis.eyraud at collabora.com  Fri May  2 05:17:17 2025
From: louisalexis.eyraud at collabora.com (Louis-Alexis Eyraud)
Date: Fri, 02 May 2025 14:17:17 +0200
Subject: [PATCH v5 2/3] drm/panfrost: Add support for Mali on the MT8370
 SoC
In-Reply-To: <20250502-mt8370-enable-gpu-v5-0-98e247b30151@collabora.com>
References: <20250502-mt8370-enable-gpu-v5-0-98e247b30151@collabora.com>
Message-ID: <20250502-mt8370-enable-gpu-v5-2-98e247b30151@collabora.com>

Add a compatible for the MediaTek MT8370 SoC, with an integrated ARM
Mali G57 MC2 GPU (Valhall-JM, dual core), with new platform data for
its support in the panfrost driver.
It uses the same data as MT8186 for the power management features to
describe power supplies, pm_domains and enablement (one regulator, two
power domains) but also sets the FORCE_AARCH64_PGTABLE flag in the GPU
configuration quirks bitfield to enable AARCH64 4K page table format
mode.
As MT8186 and MT8370 SoC have different GPU architecture (Mali G52 2EE
MC2 for MT8186), making them not compatible, and this mode is only
enabled for Mediatek SoC that are Mali G57 based (compatible with
mediatek,mali-mt8188 or mediatek,mali-8192), having specific platform
data allows to set this flag for MT8370 without modifying MT8186
configuration and behaviour.

Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>
---
 drivers/gpu/drm/panfrost/panfrost_drv.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
index f1ec3b02f15a0029d20c7d81046ded59854e885c..8e0a1ae6940c73b7b60233950ae3abdfa843cc8e 100644
--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
@@ -846,6 +846,16 @@ static const struct panfrost_compatible mediatek_mt8192_data = {
 	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
 };
 
+/* MT8370 uses the same power domains and power supplies as MT8186 */
+static const struct panfrost_compatible mediatek_mt8370_data = {
+	.num_supplies = ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1,
+	.supply_names = mediatek_mt8183_b_supplies,
+	.num_pm_domains = ARRAY_SIZE(mediatek_mt8186_pm_domains),
+	.pm_domain_names = mediatek_mt8186_pm_domains,
+	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
+	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
+};
+
 static const struct of_device_id dt_match[] = {
 	/* Set first to probe before the generic compatibles */
 	{ .compatible = "amlogic,meson-gxm-mali",
@@ -868,6 +878,7 @@ static const struct of_device_id dt_match[] = {
 	{ .compatible = "mediatek,mt8186-mali", .data = &mediatek_mt8186_data },
 	{ .compatible = "mediatek,mt8188-mali", .data = &mediatek_mt8188_data },
 	{ .compatible = "mediatek,mt8192-mali", .data = &mediatek_mt8192_data },
+	{ .compatible = "mediatek,mt8370-mali", .data = &mediatek_mt8370_data },
 	{ .compatible = "allwinner,sun50i-h616-mali", .data = &allwinner_h616_data },
 	{}
 };

-- 
2.49.0



From louisalexis.eyraud at collabora.com  Fri May  2 05:17:18 2025
From: louisalexis.eyraud at collabora.com (Louis-Alexis Eyraud)
Date: Fri, 02 May 2025 14:17:18 +0200
Subject: [PATCH v5 3/3] arm64: dts: mediatek: mt8370: Enable gpu support
In-Reply-To: <20250502-mt8370-enable-gpu-v5-0-98e247b30151@collabora.com>
References: <20250502-mt8370-enable-gpu-v5-0-98e247b30151@collabora.com>
Message-ID: <20250502-mt8370-enable-gpu-v5-3-98e247b30151@collabora.com>

Add a new gpu node in mt8370.dtsi to enable support for the
ARM Mali G57 MC2 GPU (Valhall-JM) found on the MT8370 SoC, using the
Panfrost driver.

On a Mediatek Genio 510 EVK board, the panfrost driver probed with the
following message:
```
panfrost 13000000.gpu: clock rate = 390000000
panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x0 status 0x0
panfrost 13000000.gpu: features: 00000000,000019f7, issues: 00000003,
   80000400
panfrost 13000000.gpu: Features: L2:0x08130206 Shader:0x00000000
   Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
panfrost 13000000.gpu: shader_present=0x5 l2_present=0x1
[drm] Initialized panfrost 1.3.0 for 13000000.gpu on minor 0
```

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8370.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8370.dtsi b/arch/arm64/boot/dts/mediatek/mt8370.dtsi
index cf1a3759451ff899ce9e63e5a00f192fb483f6e5..7ac8b8d0349455922a73f35db607b2b27cad23d7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8370.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8370.dtsi
@@ -59,6 +59,22 @@ &cpu_little3_cooling_map0 {
 				<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 };
 
+/*
+ * Please note that overriding compatibles is a discouraged practice and is a
+ * clear indication of nodes not being, well, compatible!
+ *
+ * This is a special case, where the GPU is the same as MT8188, but with one
+ * of the cores fused out in this lower-binned SoC.
+ */
+&gpu {
+	compatible = "mediatek,mt8370-mali", "arm,mali-valhall-jm";
+
+	power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
+			<&spm MT8188_POWER_DOMAIN_MFG3>;
+
+	power-domain-names = "core0", "core1";
+};
+
 &ppi_cluster0 {
 	affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
 };

-- 
2.49.0



From nfraprado at collabora.com  Fri May  2 05:42:56 2025
From: nfraprado at collabora.com (=?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?=)
Date: Fri, 02 May 2025 08:42:56 -0400
Subject: [PATCH] arm64: dts: mediatek: mt8395-genio-1200-evk: Disable
 unused backlight
Message-ID: <20250502-genio-1200-disable-backlight-lcd1-v1-1-c021d2c9e48e@collabora.com>

The builtin panel on the Genio 1200 EVK board uses the backlight_lcm0
node for its backlight. Though the backlight_lcd1 is currently left
enabled, it is unused, and its pwm input, disp_pwm1, is disabled, so it
fails probe. Disable this unused node.

Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
index dc884e2e95c70309407798e6a51b595e441e6369..be5e5f339e811728e91b1ffec45ada25f9b0208b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
@@ -106,6 +106,7 @@ backlight_lcd1: backlight-lcd1 {
 		brightness-levels = <0 1023>;
 		num-interpolated-steps = <1023>;
 		default-brightness-level = <576>;
+		status = "disabled";
 	};
 
 	can_clk: can-clk {

---
base-commit: 37ff6e9a2ce321b7932d3987701757fb4d87b0e6
change-id: 20250502-genio-1200-disable-backlight-lcd1-b10ef0424a51

Best regards,
-- 
N?colas F. R. A. Prado <nfraprado at collabora.com>



From louisalexis.eyraud at collabora.com  Fri May  2 06:17:19 2025
From: louisalexis.eyraud at collabora.com (Louis-Alexis Eyraud)
Date: Fri, 02 May 2025 15:17:19 +0200
Subject: [PATCH v2] arm64: dts: mediatek: mt8390-genio-common: Set ssusb2
 default dual role mode to host
Message-ID: <20250502-mtk-genio-510-700-fix-bt-detection-v2-1-870aa2145480@collabora.com>

On the Mediatek Genio 510-EVK and 700-EVK boards, ssusb2 controller is
one but has two ports: one is routed to the M.2 slot, the other is on
the RPi header who does support full OTG.
Since Mediatek Genio 700-EVK USB support was added, dual role mode
property is set to otg for ssusb2. This config prevents the M.2
Wifi/Bluetooth module, present on those boards and exposing Bluetooth
as an USB device to be properly detected at startup as the default role
is device.
To keep the OTG functionality and make the M.2 module be detected at
the same time, add role-switch-default-mode property set to host and
also fix the polarity of GPIO associated to the USB connector, so the
ssusb2 controller role is properly set to host when the other port is
unused.

Fixes: 1afaeca17238 ("arm64: dts: mediatek: mt8390-genio-700: Add USB, TypeC Controller, MUX")
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>
---
I've tested this patch on Mediatek Genio 510-EVK board with a kernel
based on linux-next (tag: next-20250502).
---
Changes in v2:
- Remove dr_mode property change and add role-switch-default-mode one
  instead, as suggested by AngeloGioacchino Del Regno
- Fix USB connector GPIO polarity
- Reword comment in ssusb2 node to match v2 fix
- Reword commit message and title
- Rebase on linux-next (tag: next-20250502)
- Link to v1: https://lore.kernel.org/r/20250331-mtk-genio-510-700-fix-bt-detection-v1-1-34ea2cf137f3 at collabora.com
---
 arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
index 127764c4d6be81767ef534a7cb228989f471b3bd..aa8dd12a84ea9d8e0e879067c45f59563455b077 100644
--- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
@@ -1333,8 +1333,18 @@ xhci_ss_ep: endpoint {
 };
 
 &ssusb2 {
+	/*
+	 * the ssusb2 controller is one but we got two ports : one is routed
+	 * to the M.2 slot, the other is on the RPi header who does support
+	 * full OTG.
+	 * As the controller is shared between them, the role switch default
+	 * mode is set to host to make any peripheral inserted in the M.2
+	 * slot (i.e BT/WIFI module) be detected when the other port is
+	 * unused.
+	 */
 	dr_mode = "otg";
 	maximum-speed = "high-speed";
+	role-switch-default-mode = "host";
 	usb-role-switch;
 	vusb33-supply = <&mt6359_vusb_ldo_reg>;
 	wakeup-source;
@@ -1345,7 +1355,7 @@ &ssusb2 {
 	connector {
 		compatible = "gpio-usb-b-connector", "usb-b-connector";
 		type = "micro";
-		id-gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
+		id-gpios = <&pio 89 GPIO_ACTIVE_LOW>;
 		vbus-supply = <&usb_p2_vbus>;
 	};
 };

---
base-commit: 1c51b1ba38c07e4f999802eb708bf798dd5f5d1b
change-id: 20250328-mtk-genio-510-700-fix-bt-detection-2711cbcbb2e4

Best regards,
-- 
Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>



From christophe.jaillet at wanadoo.fr  Fri May  2 07:51:22 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Fri,  2 May 2025 16:51:22 +0200
Subject: [PATCH] leds: rgb: leds-mt6370-rgb: Improve definition of some struct linear_range
Message-ID: <1ce4245107e0a51dce502a007a69899bda018d5f.1746197460.git.christophe.jaillet@wanadoo.fr>

Use LINEAR_RANGE() instead of hand-writing it. It is more robust, should
the layout of the structure change one day.

Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
---
 drivers/leds/rgb/leds-mt6370-rgb.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/leds/rgb/leds-mt6370-rgb.c b/drivers/leds/rgb/leds-mt6370-rgb.c
index ebd3ba878dd5..c5927d0eb830 100644
--- a/drivers/leds/rgb/leds-mt6370-rgb.c
+++ b/drivers/leds/rgb/leds-mt6370-rgb.c
@@ -199,17 +199,17 @@ static const struct reg_field mt6372_reg_fields[F_MAX_FIELDS] = {
 
 /* Current unit: microamp, time unit: millisecond */
 static const struct linear_range common_led_ranges[R_MAX_RANGES] = {
-	[R_LED123_CURR]	= { 4000, 1, 6, 4000 },
-	[R_LED4_CURR]	= { 2000, 1, 3, 2000 },
-	[R_LED_TRFON]	= { 125, 0, 15, 200 },
-	[R_LED_TOFF]	= { 250, 0, 15, 400 },
+	[R_LED123_CURR]	= LINEAR_RANGE(4000, 1, 6, 4000),
+	[R_LED4_CURR]	= LINEAR_RANGE(2000, 1, 3, 2000),
+	[R_LED_TRFON]	= LINEAR_RANGE(125, 0, 15, 200),
+	[R_LED_TOFF]	= LINEAR_RANGE(250, 0, 15, 400),
 };
 
 static const struct linear_range mt6372_led_ranges[R_MAX_RANGES] = {
-	[R_LED123_CURR]	= { 2000, 1, 14, 2000 },
-	[R_LED4_CURR]	= { 2000, 1, 14, 2000 },
-	[R_LED_TRFON]	= { 125, 0, 15, 250 },
-	[R_LED_TOFF]	= { 250, 0, 15, 500 },
+	[R_LED123_CURR]	= LINEAR_RANGE(2000, 1, 14, 2000),
+	[R_LED4_CURR]	= LINEAR_RANGE(2000, 1, 14, 2000),
+	[R_LED_TRFON]	= LINEAR_RANGE(125, 0, 15, 250),
+	[R_LED_TOFF]	= LINEAR_RANGE(250, 0, 15, 500),
 };
 
 static const unsigned int common_tfreqs[] = {
-- 
2.49.0



From nfraprado at collabora.com  Fri May  2 08:32:10 2025
From: nfraprado at collabora.com (=?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?=)
Date: Fri, 02 May 2025 11:32:10 -0400
Subject: [PATCH] arm64: dts: mediatek: mt6357: Drop regulator-fixed
 compatibles
Message-ID: <20250502-mt6357-regulator-fixed-compatibles-removal-v1-1-a582c16743fe@collabora.com>

Some of the regulators in the MT6357 PMIC dtsi have compatible set to
regulator-fixed, even though they don't serve any purpose: all those
regulators are handled as a whole by the mt6357-regulator driver. In
fact this is the only dtsi in this family of chips where this is the
case: mt6359 and mt6358 don't have any such compatibles.

A side-effect caused by this is that the DT kselftest, which is supposed
to identify nodes with compatibles that can be probed, but haven't,
shows these nodes as failures.

Remove the useless compatibles to move the dtsi in line with the others
in its family and fix the DT kselftest failures.

Fixes: 55749bb478f8 ("arm64: dts: mediatek: add mt6357 device-tree")
Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6357.dtsi | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt6357.dtsi b/arch/arm64/boot/dts/mediatek/mt6357.dtsi
index 5fafa842d312f3b01e7d71ddc04ef48ca52bc89d..dca4e5c3d8e210c1e118539153e77e2822066da3 100644
--- a/arch/arm64/boot/dts/mediatek/mt6357.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6357.dtsi
@@ -60,7 +60,6 @@ mt6357_vpa_reg: buck-vpa {
 			};
 
 			mt6357_vfe28_reg: ldo-vfe28 {
-				compatible = "regulator-fixed";
 				regulator-name = "vfe28";
 				regulator-min-microvolt = <2800000>;
 				regulator-max-microvolt = <2800000>;
@@ -75,7 +74,6 @@ mt6357_vxo22_reg: ldo-vxo22 {
 			};
 
 			mt6357_vrf18_reg: ldo-vrf18 {
-				compatible = "regulator-fixed";
 				regulator-name = "vrf18";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
@@ -83,7 +81,6 @@ mt6357_vrf18_reg: ldo-vrf18 {
 			};
 
 			mt6357_vrf12_reg: ldo-vrf12 {
-				compatible = "regulator-fixed";
 				regulator-name = "vrf12";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <1200000>;
@@ -112,7 +109,6 @@ mt6357_vcn33_wifi_reg: ldo-vcn33-wifi {
 			};
 
 			mt6357_vcn28_reg: ldo-vcn28 {
-				compatible = "regulator-fixed";
 				regulator-name = "vcn28";
 				regulator-min-microvolt = <2800000>;
 				regulator-max-microvolt = <2800000>;
@@ -120,7 +116,6 @@ mt6357_vcn28_reg: ldo-vcn28 {
 			};
 
 			mt6357_vcn18_reg: ldo-vcn18 {
-				compatible = "regulator-fixed";
 				regulator-name = "vcn18";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
@@ -142,7 +137,6 @@ mt6357_vcamd_reg: ldo-vcamd {
 			};
 
 			mt6357_vcamio_reg: ldo-vcamio18 {
-				compatible = "regulator-fixed";
 				regulator-name = "vcamio";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
@@ -175,7 +169,6 @@ mt6357_vsram_proc_reg: ldo-vsram-proc {
 			};
 
 			mt6357_vaux18_reg: ldo-vaux18 {
-				compatible = "regulator-fixed";
 				regulator-name = "vaux18";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
@@ -183,7 +176,6 @@ mt6357_vaux18_reg: ldo-vaux18 {
 			};
 
 			mt6357_vaud28_reg: ldo-vaud28 {
-				compatible = "regulator-fixed";
 				regulator-name = "vaud28";
 				regulator-min-microvolt = <2800000>;
 				regulator-max-microvolt = <2800000>;
@@ -191,7 +183,6 @@ mt6357_vaud28_reg: ldo-vaud28 {
 			};
 
 			mt6357_vio28_reg: ldo-vio28 {
-				compatible = "regulator-fixed";
 				regulator-name = "vio28";
 				regulator-min-microvolt = <2800000>;
 				regulator-max-microvolt = <2800000>;
@@ -199,7 +190,6 @@ mt6357_vio28_reg: ldo-vio28 {
 			};
 
 			mt6357_vio18_reg: ldo-vio18 {
-				compatible = "regulator-fixed";
 				regulator-name = "vio18";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;

---
base-commit: 37ff6e9a2ce321b7932d3987701757fb4d87b0e6
change-id: 20250502-mt6357-regulator-fixed-compatibles-removal-16737b35cbc3

Best regards,
-- 
N?colas F. R. A. Prado <nfraprado at collabora.com>



From nfraprado at collabora.com  Fri May  2 09:43:20 2025
From: nfraprado at collabora.com (=?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?=)
Date: Fri, 02 May 2025 12:43:20 -0400
Subject: [PATCH 0/2] Correct MT8365's infracfg-nao DT node description as a
 pure syscon
Message-ID: <20250502-mt8365-infracfg-nao-compatible-v1-0-e40394573f98@collabora.com>

Introduce a new compatible to the binding and use it in the infracfg-nao
node in the mt8365.dtsi to correctly describe the node and prevent probe
errors.

Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
---
N?colas F. R. A. Prado (2):
      dt-bindings: mfd: syscon: Add mediatek,mt8365-infracfg-nao
      arm64: dts: mediatek: mt8365: Describe infracfg-nao as a pure syscon

 Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
 arch/arm64/boot/dts/mediatek/mt8365.dtsi          | 5 ++---
 2 files changed, 3 insertions(+), 3 deletions(-)
---
base-commit: 37ff6e9a2ce321b7932d3987701757fb4d87b0e6
change-id: 20250502-mt8365-infracfg-nao-compatible-46d4db7f54f7

Best regards,
-- 
N?colas F. R. A. Prado <nfraprado at collabora.com>



From nfraprado at collabora.com  Fri May  2 09:43:21 2025
From: nfraprado at collabora.com (=?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?=)
Date: Fri, 02 May 2025 12:43:21 -0400
Subject: [PATCH 1/2] dt-bindings: mfd: syscon: Add
 mediatek,mt8365-infracfg-nao
In-Reply-To: <20250502-mt8365-infracfg-nao-compatible-v1-0-e40394573f98@collabora.com>
References: <20250502-mt8365-infracfg-nao-compatible-v1-0-e40394573f98@collabora.com>
Message-ID: <20250502-mt8365-infracfg-nao-compatible-v1-1-e40394573f98@collabora.com>

The register space described by DT node of compatible
mediatek,mt8365-infracfg-nao exposes a variety of unrelated registers,
including registers for controlling bus protection on the MT8365 SoC,
which is used by the power domain controller through a syscon.

Add this compatible to the syscon binding.

Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
---
 Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index c6bbb19c3e3e2245b4a823df06e7f361da311000..f655ec18cc2d96028d17e19d704b62f6d898fea4 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -190,6 +190,7 @@ properties:
           - mediatek,mt8135-pctl-a-syscfg
           - mediatek,mt8135-pctl-b-syscfg
           - mediatek,mt8173-pctl-a-syscfg
+          - mediatek,mt8365-infracfg-nao
           - mediatek,mt8365-syscfg
           - microchip,lan966x-cpu-syscon
           - microchip,mpfs-sysreg-scb

-- 
2.49.0



From nfraprado at collabora.com  Fri May  2 09:43:22 2025
From: nfraprado at collabora.com (=?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?=)
Date: Fri, 02 May 2025 12:43:22 -0400
Subject: [PATCH 2/2] arm64: dts: mediatek: mt8365: Describe infracfg-nao as
 a pure syscon
In-Reply-To: <20250502-mt8365-infracfg-nao-compatible-v1-0-e40394573f98@collabora.com>
References: <20250502-mt8365-infracfg-nao-compatible-v1-0-e40394573f98@collabora.com>
Message-ID: <20250502-mt8365-infracfg-nao-compatible-v1-2-e40394573f98@collabora.com>

The infracfg-nao register space at 0x1020e000 has different registers
than the infracfg space at 0x10001000, and most importantly, doesn't
contain any clock controls. Therefore it shouldn't use the same
compatible used for the mt8365 infracfg clocks driver:
mediatek,mt8365-infracfg. Since it currently does, probe errors are
reported in the kernel logs:

  [    0.245959] Failed to register clk ifr_pmic_tmr: -EEXIST
  [    0.245998] clk-mt8365 1020e000.infracfg: probe with driver clk-mt8365 failed with error -17

This register space is used only as a syscon for bus control by the
power domain controller, so in order to properly describe it and fix the
errors, set its compatible to a distinct compatible used exclusively as
a syscon, drop the clock-cells, and while at it rename the node to
'syscon' following the naming convention.

Fixes: 6ff945376556 ("arm64: dts: mediatek: Initial mt8365-evk support")
Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8365.dtsi | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index e6d2b3221a3b7a855129258b379ae4bc2fd05449..49ad4dee9c4cf563743dc55d5e0b055cfb69986a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -495,10 +495,9 @@ iommu: iommu at 10205000 {
 			#iommu-cells = <1>;
 		};
 
-		infracfg_nao: infracfg at 1020e000 {
-			compatible = "mediatek,mt8365-infracfg", "syscon";
+		infracfg_nao: syscon at 1020e000 {
+			compatible = "mediatek,mt8365-infracfg-nao", "syscon";
 			reg = <0 0x1020e000 0 0x1000>;
-			#clock-cells = <1>;
 		};
 
 		rng: rng at 1020f000 {

-- 
2.49.0



From kuba at kernel.org  Fri May  2 18:12:10 2025
From: kuba at kernel.org (Jakub Kicinski)
Date: Fri, 2 May 2025 18:12:10 -0700
Subject: [PATCH net v4] net: airoha: Add missing filed to ppe_mbox_data
 struct
In-Reply-To: <aBRzQaonAK0IyAsu@lore-desk>
References: <20250429-airoha-en7581-fix-ppe_mbox_data-v4-1-d2a8b901dad0@kernel.org>
	<20250501071518.50c92e8c@kernel.org>
	<aBPdyn580lxUMJKz@lore-desk>
	<20250501174140.6dc31b36@kernel.org>
	<aBRzQaonAK0IyAsu@lore-desk>
Message-ID: <20250502181210.75b9d144@kernel.org>

On Fri, 2 May 2025 09:24:49 +0200 Lorenzo Bianconi wrote:
> > > What I mean here is the padding in the ppe_mbox_data struct used by the fw running
> > > on the NPU, not in the version used by the airoha_eth driver, got my point?
> > > Sorry, re-reading it, it was not so clear, I agree.  
> > 
> > You mean adding the "u8 rsv[3];" ? that is fine.
> > I don't get why we also need to add the 3 __packed  
> 
> I agree the __packed attributes are not mandatory at the moment, we just agreed
> with Jacob that is fine to add them. Do you prefer to get rid of them?

Yes, they also imply the structure may not be aligned, AFAIU.
__packed used to be one of DaveM's big no-nos back in the day.
Especially in vendor drivers it gets sprinkled everywhere without
thinking. So maybe it's all school of me, but yes, please remove.


From lorenzo at kernel.org  Sat May  3 01:39:39 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Sat, 3 May 2025 10:39:39 +0200
Subject: [PATCH net v4] net: airoha: Add missing filed to ppe_mbox_data
 struct
In-Reply-To: <20250502181210.75b9d144@kernel.org>
References: <20250429-airoha-en7581-fix-ppe_mbox_data-v4-1-d2a8b901dad0@kernel.org>
 <20250501071518.50c92e8c@kernel.org>
 <aBPdyn580lxUMJKz@lore-desk>
 <20250501174140.6dc31b36@kernel.org>
 <aBRzQaonAK0IyAsu@lore-desk>
 <20250502181210.75b9d144@kernel.org>
Message-ID: <aBXWSzhXv9RDiJ5L@lore-desk>

On May 02, Jakub Kicinski wrote:
> On Fri, 2 May 2025 09:24:49 +0200 Lorenzo Bianconi wrote:
> > > > What I mean here is the padding in the ppe_mbox_data struct used by the fw running
> > > > on the NPU, not in the version used by the airoha_eth driver, got my point?
> > > > Sorry, re-reading it, it was not so clear, I agree.  
> > > 
> > > You mean adding the "u8 rsv[3];" ? that is fine.
> > > I don't get why we also need to add the 3 __packed  
> > 
> > I agree the __packed attributes are not mandatory at the moment, we just agreed
> > with Jacob that is fine to add them. Do you prefer to get rid of them?
> 
> Yes, they also imply the structure may not be aligned, AFAIU.
> __packed used to be one of DaveM's big no-nos back in the day.
> Especially in vendor drivers it gets sprinkled everywhere without
> thinking. So maybe it's all school of me, but yes, please remove.

ack, fine. I will get rid of them in v5.

Regards,
Lorenzo
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From daniel at makrotopia.org  Sat May  3 08:24:02 2025
From: daniel at makrotopia.org (Daniel Golle)
Date: Sat, 3 May 2025 16:24:02 +0100
Subject: [PATCH net 1/2] net: ethernet: mtk_eth_soc: reset all TX queues on
 DMA free
Message-ID: <27713d0004ead6e57d070f9e19c0d13709ba2512.1746285649.git.daniel@makrotopia.org>

The purpose of resetting the TX queue is to reset the
byte and packet count as well as to clear the software
flow control XOFF bit.

MediaTek developers pointed out that netdev_reset_queue would only
resets queue 0 of the network device.

Queues that are not reset may cause unexpected issues.

Packets may stop being sent after reset and "transmit timeout" log may
be displayed.

Import fix from MediaTek's SDK to resolve this issue.

Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/319c0d9905579a46dc448579f892f364f1f84818
Fixes: f63959c7eec31 ("net: ethernet: mtk_eth_soc: implement multi-queue support for per-port queues")
Signed-off-by: Daniel Golle <daniel at makrotopia.org>
---
 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 217355d79bbb7..d6d4c2daebab0 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3274,11 +3274,19 @@ static int mtk_dma_init(struct mtk_eth *eth)
 static void mtk_dma_free(struct mtk_eth *eth)
 {
 	const struct mtk_soc_data *soc = eth->soc;
-	int i;
+	int i, j, txqs = 1;
+
+	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
+		txqs = MTK_QDMA_NUM_QUEUES;
+
+	for (i = 0; i < MTK_MAX_DEVS; i++) {
+		if (!eth->netdev[i])
+			continue;
+
+		for (j = 0; j < txqs; j++)
+			netdev_tx_reset_queue(netdev_get_tx_queue(eth->netdev[i], j));
+	}
 
-	for (i = 0; i < MTK_MAX_DEVS; i++)
-		if (eth->netdev[i])
-			netdev_reset_queue(eth->netdev[i]);
 	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
 		dma_free_coherent(eth->dma_dev,
 				  MTK_QDMA_RING_SIZE * soc->tx.desc_size,
-- 
2.49.0


From daniel at makrotopia.org  Sat May  3 08:24:21 2025
From: daniel at makrotopia.org (Daniel Golle)
Date: Sat, 3 May 2025 16:24:21 +0100
Subject: [PATCH net 2/2] net: mediatek: do not reset PSE when seting FE
 register
In-Reply-To: <27713d0004ead6e57d070f9e19c0d13709ba2512.1746285649.git.daniel@makrotopia.org>
References: <27713d0004ead6e57d070f9e19c0d13709ba2512.1746285649.git.daniel@makrotopia.org>
Message-ID: <226fada6d179db1655751e689ab30a1cbd682f49.1746285649.git.daniel@makrotopia.org>

From: Frank Wunderlich <frank-w at public-files.de>

Remove redundant PSE reset.
When setting FE register there is no need to reset PSE,
doing so may cause FE to work abnormal.

Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/3a5223473e086a4b54a2b9a44df7d9ddcc2bc75a
Fixes: dee4dd10c79aa ("net: ethernet: mtk_eth_soc: ppe: add support for multiple PPEs")
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index d6d4c2daebab0..6b5f36ccb3fec 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3561,9 +3561,6 @@ static int mtk_open(struct net_device *dev)
 			}
 			mtk_gdm_config(eth, target_mac->id, gdm_config);
 		}
-		/* Reset and enable PSE */
-		mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
-		mtk_w32(eth, 0, MTK_RST_GL);
 
 		napi_enable(&eth->tx_napi);
 		napi_enable(&eth->rx_napi);
-- 
2.49.0


From lorenzo at kernel.org  Sat May  3 10:14:34 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Sat, 3 May 2025 19:14:34 +0200
Subject: [PATCH net 1/2] net: ethernet: mtk_eth_soc: reset all TX queues
 on DMA free
In-Reply-To: <27713d0004ead6e57d070f9e19c0d13709ba2512.1746285649.git.daniel@makrotopia.org>
References: <27713d0004ead6e57d070f9e19c0d13709ba2512.1746285649.git.daniel@makrotopia.org>
Message-ID: <aBZO-nmFoKLx5E5w@lore-desk>

> The purpose of resetting the TX queue is to reset the
> byte and packet count as well as to clear the software
> flow control XOFF bit.
> 
> MediaTek developers pointed out that netdev_reset_queue would only
> resets queue 0 of the network device.
> 
> Queues that are not reset may cause unexpected issues.
> 
> Packets may stop being sent after reset and "transmit timeout" log may
> be displayed.
> 
> Import fix from MediaTek's SDK to resolve this issue.
> 
> Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/319c0d9905579a46dc448579f892f364f1f84818
> Fixes: f63959c7eec31 ("net: ethernet: mtk_eth_soc: implement multi-queue support for per-port queues")
> Signed-off-by: Daniel Golle <daniel at makrotopia.org>
> ---
>  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 16 ++++++++++++----
>  1 file changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> index 217355d79bbb7..d6d4c2daebab0 100644
> --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> @@ -3274,11 +3274,19 @@ static int mtk_dma_init(struct mtk_eth *eth)
>  static void mtk_dma_free(struct mtk_eth *eth)
>  {
>  	const struct mtk_soc_data *soc = eth->soc;
> -	int i;
> +	int i, j, txqs = 1;
> +
> +	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
> +		txqs = MTK_QDMA_NUM_QUEUES;
> +
> +	for (i = 0; i < MTK_MAX_DEVS; i++) {
> +		if (!eth->netdev[i])
> +			continue;
> +
> +		for (j = 0; j < txqs; j++)
> +			netdev_tx_reset_queue(netdev_get_tx_queue(eth->netdev[i], j));

nit: you can use netdev_tx_reset_subqueue() here.

Regards,
Lorenzo

> +	}
>  
> -	for (i = 0; i < MTK_MAX_DEVS; i++)
> -		if (eth->netdev[i])
> -			netdev_reset_queue(eth->netdev[i]);
>  	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
>  		dma_free_coherent(eth->dma_dev,
>  				  MTK_QDMA_RING_SIZE * soc->tx.desc_size,
> -- 
> 2.49.0
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From niks at kernel.org  Sat May  3 15:39:52 2025
From: niks at kernel.org (Niklas Schnelle)
Date: Sun, 04 May 2025 00:39:52 +0200
Subject: [REGRESSION][BISECTED][STABLE] MT7925: mDNS and IPv6 broken in
 kernel 6.14.3 and above
In-Reply-To: <f73dec60b60dd7bb3be40c1feefbe223c7afe19b.camel@mediatek.com>
References: <EmWnO5b-acRH1TXbGnkx41eJw654vmCR-8_xMBaPMwexCnfkvKCdlU5u19CGbaapJ3KRu-l3B-tSUhf8CCQwL0odjo6Cd5YG5lvNeB-vfdg=@pm.me>
	 <f73dec60b60dd7bb3be40c1feefbe223c7afe19b.camel@mediatek.com>
Message-ID: <5ae1ef34c9844d6d0f5fb167dd596a4c43321367.camel@kernel.org>

On Wed, 2025-04-30 at 06:47 +0000, Mingyen Hsieh (???) wrote:
> On Wed, 2025-04-30 at 01:14 +0000, fossben at pm.me wrote:
> > 
> > External email : Please do not click links or open attachments until
> > you have verified the sender or the content.
> > 
> > 
> > Hello all,
> > 
> > After upgrading to 6.14.3 on my PC with a MT7925 chip, I noticed that
> > I could no longer ping *.local addresses provided by Avahi. In
> > addition, I also noticed that I was not able to get a DHCP IPv6
> > address from my router, no matter how many times I rebooted the
> > router or reconnected with NetworkManager.
> > 
> > Reverting to 6.14.2 fixes both mDNS and IPv6 addresses immediately.
> > Going back to 6.14.3 immediately breaks mDNS again, but the IPv6
> > address will stay there for a while before disappearing later,
> > possibly because the DHCP lease expired? I am not sure exactly when
> > it stops working.
> > 
> > I've done a kernel bisect between 6.14.2 and 6.14.3 and found the
> > offending commit that causes mDNS to fail:
> > 
> > commit 80007d3f92fd018d0a052a706400e976b36e3c87
> > Author: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
> > Date:?? Tue Mar 4 16:08:50 2025 -0800
> > 
> > ??? wifi: mt76: mt7925: integrate *mlo_sta_cmd and *sta_cmd
> > 
> > ??? commit cb1353ef34735ec1e5d9efa1fe966f05ff1dc1e1 upstream.
> > 
> > ??? Integrate *mlo_sta_cmd and *sta_cmd for the MLO firmware.
> > 
> > ??? Fixes: 86c051f2c418 ("wifi: mt76: mt7925: enabling MLO when the
> > firmware supports it")
> > 
> > ?drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 59 ++++-----------
> > --------------------------------------------
> > ?1 file changed, 4 insertions(+), 55 deletions(-)
> > 
> > I do not know if this same commit is also causing the IPv6 issues as
> > testing that requires quite a bit of time to reproduce. What I do
> > know with certainty as of this moment is that it definitely breaks in
> > kernel 6.14.3.
> > 
> > I've attached my hardware info as well as dmesg logs from the last
> > working kernel from the bisect and 6.14.4 which exhibits the issue.
> > Please let me know if there's any other info you need.
> > 
> > Thanks!
> > Benjamin Xiao
> 
> Hi,
> 
> Thanks for reporting this issue, we will aim into this.
> 
> Can you provide me with your testing steps?
> 
> Best Regards,
> Yen.
> 

Hi Yan,

I see the same IPv6 issue on my Framework 13 (Ryzen 5 AI 340) with an
mt7925e WiFI module.?My setup is just a home router with native IPv6
both for my uplink and in the LAN. The problems with IPv6 can already
be seen just in the LAN for example by checking which IP was used for
SSH, in my setup it should always be IPv6 but falls back to IPv4 in the
broken state.

As another data point, I tried reverting cb1353ef3473 ("wifi: mt76:
mt7925: integrate *mlo_sta_cmd and *sta_cmd") on top of 6.15.-rc4. This
fully restores IPv6 for me. Also note I'm running this with the mt7925
firmware version 20250425073330 from linux-firmware's master branch as
I had some dropped connections with earlier firmware.

So it definitely looks like that commit also broke IPv6 and not just
mDNS. Note that if if I use DHCPv6 instead of router advertisements, on
the latest firmware, but without the revert, I get a global IPv6
address added to the interface but then native IPv6 addresses are still
uncreachable. With the offending patch reverted my SSH session to an
IPv6 only host works fine and is stable. Also I'd be willing to test a
proper fix as I rely on IPv6 heavily due to having to use CGNAT for
IPv4 but not for IPv6.


Thanks,
Niklas


From krzk at kernel.org  Sun May  4 06:40:32 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Sun, 4 May 2025 15:40:32 +0200
Subject: [PATCH v7 2/2] memory: mtk-smi: mt8188: Add SMI reset and clamp
 for MT8188
In-Reply-To: <20250430094545.23932-3-friday.yang@mediatek.com>
References: <20250430094545.23932-1-friday.yang@mediatek.com>
 <20250430094545.23932-3-friday.yang@mediatek.com>
Message-ID: <9f01a9a4-89b2-4bfc-97cd-827be989ef16@kernel.org>

On 30/04/2025 11:45, Friday Yang wrote:
> From: "Friday Yang" <friday.yang at mediatek.com>
> 
> To prevent handling glitch signals during MTCMOS on/off transitions,
> SMI requires clamp and reset operations. Parse the reset settings for
> SMI LARBs and the clamp settings for the SMI Sub-Common. Register
> genpd callback for the SMI LARBs located in image, camera and IPE
> subsystems, and apply reset and clamp operations within the callback.
> 
> Signed-off-by: Friday Yang <friday.yang at mediatek.com>
> Tested-by: Friday Yang <friday.yang at mediatek.com>

How is this possible? Are you claiming that none of other authors test
their patches? How testing would be not implied by authorship?

> Reviewed-by: Yong Wu <yong.wu at mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Acked-by: Rob Herring <robh at kernel.org>

Changelog says that v7 has only following changes:

  - Remove the 'devm_pm_runtime_enable' change.

While v6 had no such tags.

No clue what happened here, but looks like mess with the tags and really
incomplete changelog.

Best regards,
Krzysztof


From krzk at kernel.org  Sun May  4 06:42:23 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Sun, 4 May 2025 15:42:23 +0200
Subject: [PATCH v7 1/2] dt-bindings: memory: mediatek: Add SMI reset and
 clamp for MT8188
In-Reply-To: <20250430094545.23932-2-friday.yang@mediatek.com>
References: <20250430094545.23932-1-friday.yang@mediatek.com>
 <20250430094545.23932-2-friday.yang@mediatek.com>
Message-ID: <c448ce68-16e9-41b7-a69d-e28c1043f8ae@kernel.org>

On 30/04/2025 11:45, Friday Yang wrote:
> From: "Friday Yang" <friday.yang at mediatek.com>
> 
> Add 'resets' and 'reset-names' properties for SMI LARBs to support
> SMI reset operations.
> On the MediaTek platform, some SMI LARBs are directly connected to
> the SMI Common, while others are connected to the SMI Sub-Common,
> which in turn is connected to the SMI Common. The hardware block
> diagram can be described as follows.
> 
>              SMI-Common(Smart Multimedia Interface Common)
>                  |
>          +----------------+------------------+
>          |                |                  |
>          |                |                  |
>          |                |                  |
>          |                |                  |
>          |                |                  |
>        larb0       SMI-Sub-Common0     SMI-Sub-Common1
>                    |      |     |      |             |
>                   larb1  larb2 larb3  larb7       larb9
> 
> Signed-off-by: Friday Yang <friday.yang at mediatek.com>
> Tested-by: Friday Yang <friday.yang at mediatek.com>

That's not possible. Otherwise explain me how do you test bindings (and
using static checkers is not testing).


> Reviewed-by: Yong Wu <yong.wu at mediatek.com>

Where? Provide lore link. That's a v7 so I expect all your work to be
done public.


Best regards,
Krzysztof


From daniel at makrotopia.org  Sun May  4 18:07:32 2025
From: daniel at makrotopia.org (Daniel Golle)
Date: Mon, 5 May 2025 02:07:32 +0100
Subject: [PATCH net v2 1/2] net: ethernet: mtk_eth_soc: reset all TX queues
 on DMA free
Message-ID: <c9ff9adceac4f152239a0f65c397f13547639175.1746406763.git.daniel@makrotopia.org>

The purpose of resetting the TX queue is to reset the byte and packet
count as well as to clear the software flow control XOFF bit.

MediaTek developers pointed out that netdev_reset_queue would only
resets queue 0 of the network device.

Queues that are not reset may cause unexpected issues.

Packets may stop being sent after reset and "transmit timeout" log may
be displayed.

Import fix from MediaTek's SDK to resolve this issue.

Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/319c0d9905579a46dc448579f892f364f1f84818
Fixes: f63959c7eec31 ("net: ethernet: mtk_eth_soc: implement multi-queue support for per-port queues")
Signed-off-by: Daniel Golle <daniel at makrotopia.org>
---
v2: Use netdev_tx_reset_subqueue()

 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 8fda4ce80d811..53c39561b6d9a 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3186,11 +3186,19 @@ static int mtk_dma_init(struct mtk_eth *eth)
 static void mtk_dma_free(struct mtk_eth *eth)
 {
 	const struct mtk_soc_data *soc = eth->soc;
-	int i;
+	int i, j, txqs = 1;
+
+	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
+		txqs = MTK_QDMA_NUM_QUEUES;
+
+	for (i = 0; i < MTK_MAX_DEVS; i++) {
+		if (!eth->netdev[i])
+			continue;
+
+		for (j = 0; j < txqs; j++)
+			netdev_tx_reset_subqueue(eth->netdev[i], j);
+	}
 
-	for (i = 0; i < MTK_MAX_DEVS; i++)
-		if (eth->netdev[i])
-			netdev_reset_queue(eth->netdev[i]);
 	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
 		dma_free_coherent(eth->dma_dev,
 				  MTK_QDMA_RING_SIZE * soc->tx.desc_size,
-- 
2.49.0


From daniel at makrotopia.org  Sun May  4 18:07:58 2025
From: daniel at makrotopia.org (Daniel Golle)
Date: Mon, 5 May 2025 02:07:58 +0100
Subject: [PATCH net v2 2/2] net: ethernet: mtk_eth_soc: do not reset PSE when
 setting FE
In-Reply-To: <c9ff9adceac4f152239a0f65c397f13547639175.1746406763.git.daniel@makrotopia.org>
References: <c9ff9adceac4f152239a0f65c397f13547639175.1746406763.git.daniel@makrotopia.org>
Message-ID: <18f0ac7d83f82defa3342c11ef0d1362f6b81e88.1746406763.git.daniel@makrotopia.org>

From: Frank Wunderlich <frank-w at public-files.de>

Remove redundant PSE reset.
When setting FE register there is no need to reset PSE,
doing so may cause FE to work abnormal.

Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/3a5223473e086a4b54a2b9a44df7d9ddcc2bc75a
Fixes: dee4dd10c79aa ("net: ethernet: mtk_eth_soc: ppe: add support for multiple PPEs")
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
v2: fix commit title

 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 53c39561b6d9a..22a532695fb0d 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3473,9 +3473,6 @@ static int mtk_open(struct net_device *dev)
 			}
 			mtk_gdm_config(eth, target_mac->id, gdm_config);
 		}
-		/* Reset and enable PSE */
-		mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
-		mtk_w32(eth, 0, MTK_RST_GL);
 
 		napi_enable(&eth->tx_napi);
 		napi_enable(&eth->rx_napi);
-- 
2.49.0


From arnd at kernel.org  Sun May  4 22:20:52 2025
From: arnd at kernel.org (Arnd Bergmann)
Date: Mon,  5 May 2025 07:20:52 +0200
Subject: [PATCH] ASoC: mediatek: mt8188-mt6359: select CONFIG_SND_SOC_MT6359_ACCDET
Message-ID: <20250505052106.1811802-1-arnd@kernel.org>

From: Arnd Bergmann <arnd at arndb.de>

The driver support was added without selecting the codec, which leads to
a link failure:

aarch64-linux-ld: sound/soc/mediatek/mt8188/mt8188-mt6359.o: in function `mt8188_mt6359_init':
mt8188-mt6359.c:(.text+0x19f0): undefined reference to `mt6359_accdet_enable_jack_detect'

Fixes: f35d834d67ad ("ASoC: mediatek: mt8188-mt6359: Add accdet headset jack detect support")
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 sound/soc/mediatek/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig
index 3033e2d3fe16..e148d4d94160 100644
--- a/sound/soc/mediatek/Kconfig
+++ b/sound/soc/mediatek/Kconfig
@@ -229,6 +229,7 @@ config SND_SOC_MT8188_MT6359
 	tristate "ASoC Audio driver for MT8188 with MT6359 and I2S codecs"
 	depends on SND_SOC_MT8188 && MTK_PMIC_WRAP
 	depends on I2C
+	select SND_SOC_MT6359_ACCDET
 	select SND_SOC_MT6359
 	select SND_SOC_HDMI_CODEC
 	select SND_SOC_DMIC
-- 
2.39.5



From arnd at kernel.org  Sun May  4 22:24:52 2025
From: arnd at kernel.org (Arnd Bergmann)
Date: Mon,  5 May 2025 07:24:52 +0200
Subject: [PATCH] thermal/drivers/mediatek/lvts: remove unused lvts_debugfs_exit
Message-ID: <20250505052502.1812867-1-arnd@kernel.org>

From: Arnd Bergmann <arnd at arndb.de>

When debugfs is disabled, the function has no reference any more:

drivers/thermal/mediatek/lvts_thermal.c:266:13: error: 'lvts_debugfs_exit' defined but not used [-Werror=unused-function]
  266 | static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { }
      |             ^~~~~~~~~~~~~~~~~

Fixes: ef280c17a840 ("thermal/drivers/mediatek/lvts: Fix debugfs unregister on failure")
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/thermal/mediatek/lvts_thermal.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index c0be4ca55c7b..985925147ac0 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -263,8 +263,6 @@ static inline int lvts_debugfs_init(struct device *dev,
 	return 0;
 }
 
-static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { }
-
 #endif
 
 static int lvts_raw_to_temp(u32 raw_temp, int temp_factor)
-- 
2.39.5



From daniel.lezcano at linaro.org  Sun May  4 22:35:44 2025
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Mon, 5 May 2025 07:35:44 +0200
Subject: [PATCH] thermal/drivers/mediatek/lvts: remove unused
 lvts_debugfs_exit
In-Reply-To: <20250505052502.1812867-1-arnd@kernel.org>
References: <20250505052502.1812867-1-arnd@kernel.org>
Message-ID: <c3a3ab95-0129-4cae-9494-817d7e2b49be@linaro.org>

On 05/05/2025 07:24, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> When debugfs is disabled, the function has no reference any more:
> 
> drivers/thermal/mediatek/lvts_thermal.c:266:13: error: 'lvts_debugfs_exit' defined but not used [-Werror=unused-function]
>    266 | static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { }
>        |             ^~~~~~~~~~~~~~~~~
> 
> Fixes: ef280c17a840 ("thermal/drivers/mediatek/lvts: Fix debugfs unregister on failure")
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---

Applied, thanks


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From Mingyen.Hsieh at mediatek.com  Sun May  4 22:48:30 2025
From: Mingyen.Hsieh at mediatek.com (=?utf-8?B?TWluZ3llbiBIc2llaCAo6Kyd5piO6Ku6KQ==?=)
Date: Mon, 5 May 2025 05:48:30 +0000
Subject: [REGRESSION][BISECTED][STABLE] MT7925: mDNS and IPv6 broken in
 kernel 6.14.3 and above
In-Reply-To: <5ae1ef34c9844d6d0f5fb167dd596a4c43321367.camel@kernel.org>
References: <EmWnO5b-acRH1TXbGnkx41eJw654vmCR-8_xMBaPMwexCnfkvKCdlU5u19CGbaapJ3KRu-l3B-tSUhf8CCQwL0odjo6Cd5YG5lvNeB-vfdg=@pm.me>
	 <f73dec60b60dd7bb3be40c1feefbe223c7afe19b.camel@mediatek.com>
	 <5ae1ef34c9844d6d0f5fb167dd596a4c43321367.camel@kernel.org>
Message-ID: <28ef2cc608d071d1530902d7b5df045555ab5651.camel@mediatek.com>

On Sun, 2025-05-04 at 00:39 +0200, Niklas Schnelle wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On Wed, 2025-04-30 at 06:47 +0000, Mingyen Hsieh (???) wrote:
> > On Wed, 2025-04-30 at 01:14 +0000, fossben at pm.me?wrote:
> > > 
> > > External email : Please do not click links or open attachments
> > > until
> > > you have verified the sender or the content.
> > > 
> > > 
> > > Hello all,
> > > 
> > > After upgrading to 6.14.3 on my PC with a MT7925 chip, I noticed
> > > that
> > > I could no longer ping *.local addresses provided by Avahi. In
> > > addition, I also noticed that I was not able to get a DHCP IPv6
> > > address from my router, no matter how many times I rebooted the
> > > router or reconnected with NetworkManager.
> > > 
> > > Reverting to 6.14.2 fixes both mDNS and IPv6 addresses
> > > immediately.
> > > Going back to 6.14.3 immediately breaks mDNS again, but the IPv6
> > > address will stay there for a while before disappearing later,
> > > possibly because the DHCP lease expired? I am not sure exactly
> > > when
> > > it stops working.
> > > 
> > > I've done a kernel bisect between 6.14.2 and 6.14.3 and found the
> > > offending commit that causes mDNS to fail:
> > > 
> > > commit 80007d3f92fd018d0a052a706400e976b36e3c87
> > > Author: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
> > > Date:?? Tue Mar 4 16:08:50 2025 -0800
> > > 
> > > ??? wifi: mt76: mt7925: integrate *mlo_sta_cmd and *sta_cmd
> > > 
> > > ??? commit cb1353ef34735ec1e5d9efa1fe966f05ff1dc1e1 upstream.
> > > 
> > > ??? Integrate *mlo_sta_cmd and *sta_cmd for the MLO firmware.
> > > 
> > > ??? Fixes: 86c051f2c418 ("wifi: mt76: mt7925: enabling MLO when
> > > the
> > > firmware supports it")
> > > 
> > > ?drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 59 ++++-------
> > > ----
> > > --------------------------------------------
> > > ?1 file changed, 4 insertions(+), 55 deletions(-)
> > > 
> > > I do not know if this same commit is also causing the IPv6 issues
> > > as
> > > testing that requires quite a bit of time to reproduce. What I do
> > > know with certainty as of this moment is that it definitely
> > > breaks in
> > > kernel 6.14.3.
> > > 
> > > I've attached my hardware info as well as dmesg logs from the
> > > last
> > > working kernel from the bisect and 6.14.4 which exhibits the
> > > issue.
> > > Please let me know if there's any other info you need.
> > > 
> > > Thanks!
> > > Benjamin Xiao
> > 
> > Hi,
> > 
> > Thanks for reporting this issue, we will aim into this.
> > 
> > Can you provide me with your testing steps?
> > 
> > Best Regards,
> > Yen.
> > 
> 
> Hi Yan,
> 
> I see the same IPv6 issue on my Framework 13 (Ryzen 5 AI 340) with an
> mt7925e WiFI module. My setup is just a home router with native IPv6
> both for my uplink and in the LAN. The problems with IPv6 can already
> be seen just in the LAN for example by checking which IP was used for
> SSH, in my setup it should always be IPv6 but falls back to IPv4 in
> the
> broken state.
> 
> As another data point, I tried reverting cb1353ef3473 ("wifi: mt76:
> mt7925: integrate *mlo_sta_cmd and *sta_cmd") on top of 6.15.-rc4.
> This
> fully restores IPv6 for me. Also note I'm running this with the
> mt7925
> firmware version 20250425073330 from linux-firmware's master branch
> as
> I had some dropped connections with earlier firmware.
> 
> So it definitely looks like that commit also broke IPv6 and not just
> mDNS. Note that if if I use DHCPv6 instead of router advertisements,
> on
> the latest firmware, but without the revert, I get a global IPv6
> address added to the interface but then native IPv6 addresses are
> still
> uncreachable. With the offending patch reverted my SSH session to an
> IPv6 only host works fine and is stable. Also I'd be willing to test
> a
> proper fix as I rely on IPv6 heavily due to having to use CGNAT for
> IPv4 but not for IPv6.
> 
> 
> Thanks,
> Niklas

Hi Benjamin & Niklas,

Can you help to try this patch? I can get IPv6 address through this
patch.

If it can work at your environment as well, i will upstream it and add
test tag with you.

diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
index a42b584634ab..fd756f0d18f8 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
@@ -2183,14 +2183,14 @@ mt7925_mcu_sta_cmd(struct mt76_phy *phy,
                        mt7925_mcu_sta_mld_tlv(skb, info->vif, info-
>link_sta->sta);
                        mt7925_mcu_sta_eht_mld_tlv(skb, info->vif,
info->link_sta->sta);
                }
-
-               mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info-
>link_sta);
        }

        if (!info->enable) {
                mt7925_mcu_sta_remove_tlv(skb);
                mt76_connac_mcu_add_tlv(skb, STA_REC_MLD_OFF,
                                        sizeof(struct tlv));
+       } else {
+               mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info-
>link_sta);
        }

        return mt76_mcu_skb_send_msg(dev, skb, info->cmd, true);


Thanks~
Yen.



From mripard at kernel.org  Sun May  4 23:23:26 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Mon, 5 May 2025 08:23:26 +0200
Subject: [PATCH v2 34/34] drm/bridge: panel: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250428172516.79058e22@booty>
References: <20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b@bootlin.com>
 <20250424-drm-bridge-convert-to-alloc-api-v2-34-8f91a404d86b@bootlin.com>
 <20250428-wild-condor-of-defiance-cadf60@houat>
 <20250428172516.79058e22@booty>
Message-ID: <20250505-beneficial-fossa-of-weather-67c676@houat>

On Mon, Apr 28, 2025 at 05:25:16PM +0200, Luca Ceresoli wrote:
> Hi Maxime,
> 
> On Mon, 28 Apr 2025 13:39:23 +0200
> Maxime Ripard <mripard at kernel.org> wrote:
> 
> > On Thu, Apr 24, 2025 at 10:05:49PM +0200, Luca Ceresoli wrote:
> > > This is the new API for allocating DRM bridges.
> > > 
> > > The devm lifetime management of this driver is peculiar. The underlying
> > > device for the panel_bridge is the panel, and the devm lifetime is tied the
> > > panel device (panel->dev). However the panel_bridge allocation is not
> > > performed by the panel driver, but rather by a separate entity (typically
> > > the previous bridge in the encoder chain).
> > > 
> > > Thus when that separate entoty is destroyed, the panel_bridge is not
> > > removed automatically by devm, so it is rather done explicitly by calling
> > > drm_panel_bridge_remove(). This is the function that does devm_kfree() the
> > > panel_bridge in current code, so update it as well to put the bridge
> > > reference instead.
> > > 
> > > Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>  
> > 
> > This looks fine, but we need a TODO entry to clean this up later on, and
> > a comment on devm_drm_put_bridge that this is inherently unsafe and
> > must not be used.
> 
> Ah, I see, OK.
> 
> Quick draft:
> 
>  /**
>   * devm_drm_put_bridge - Release a bridge reference obtained via devm
>   * @dev: device that got the bridge via devm
>   * @bridge: pointer to a struct drm_bridge obtained via devm
>   *
>   * Same as drm_bridge_put() for bridge pointers obtained via devm functions
>   * such as devm_drm_bridge_alloc().
> + *
> + * This function is a temporary workaround and MUST NOT be used. Manual
> + * handling of bridge lifetime is inherently unsafe.
>   */

That part looks good to me

> and:
> 
> -	devm_kfree(panel_bridge->panel->dev, bridge);
> +       /* TODO remove this after reworking panel_bridge lifetime */
> +	devm_drm_put_bridge(panel_bridge->panel->dev, bridge);
>  }
> 
> Does it look good enough?

That too, but I was talking about an entry in
https://www.kernel.org/doc/html/latest/gpu/todo.html

Maxime
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From angelogioacchino.delregno at collabora.com  Mon May  5 00:20:30 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Mon, 5 May 2025 09:20:30 +0200
Subject: [PATCH] ASoC: mediatek: mt8188-mt6359: select
 CONFIG_SND_SOC_MT6359_ACCDET
In-Reply-To: <20250505052106.1811802-1-arnd@kernel.org>
References: <20250505052106.1811802-1-arnd@kernel.org>
Message-ID: <97b93862-8572-45fb-ba02-96a0bb747700@collabora.com>

Il 05/05/25 07:20, Arnd Bergmann ha scritto:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> The driver support was added without selecting the codec, which leads to
> a link failure:
> 
> aarch64-linux-ld: sound/soc/mediatek/mt8188/mt8188-mt6359.o: in function `mt8188_mt6359_init':
> mt8188-mt6359.c:(.text+0x19f0): undefined reference to `mt6359_accdet_enable_jack_detect'
> 
> Fixes: f35d834d67ad ("ASoC: mediatek: mt8188-mt6359: Add accdet headset jack detect support")
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>




From allan.wang at mediatek.com  Mon May  5 00:37:34 2025
From: allan.wang at mediatek.com (Allan Wang)
Date: Mon, 5 May 2025 15:37:34 +0800
Subject: [PATCH] wifi: mt76: mt7925: add rfkill_poll for hardware rfkill
Message-ID: <20250505073734.3923790-1-allan.wang@mediatek.com>

Add mac80211 rfkill_poll ops to monitor hardware rfkill state
and state change will be updated.

Signed-off-by: Allan Wang <allan.wang at mediatek.com>
---
 .../wireless/mediatek/mt76/mt76_connac_mcu.h  |  1 +
 .../net/wireless/mediatek/mt76/mt7925/main.c  | 16 ++++++++
 .../net/wireless/mediatek/mt76/mt7925/mcu.c   | 39 +++++++++++++++++++
 .../wireless/mediatek/mt76/mt7925/mt7925.h    |  1 +
 .../net/wireless/mediatek/mt76/mt7925/pci.c   |  4 ++
 5 files changed, 61 insertions(+)

diff --git a/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h b/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h
index 478cd1886736..e195d69f61f6 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h
@@ -1298,6 +1298,7 @@ enum {
 	MCU_UNI_CMD_PER_STA_INFO = 0x6d,
 	MCU_UNI_CMD_ALL_STA_INFO = 0x6e,
 	MCU_UNI_CMD_ASSERT_DUMP = 0x6f,
+	MCU_UNI_CMD_RADIO_STATUS = 0x80,
 	MCU_UNI_CMD_SDO = 0x88,
 };
 
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/main.c b/drivers/net/wireless/mediatek/mt76/mt7925/main.c
index 83f93f9e002c..65bf9aef2b5e 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/main.c
@@ -334,6 +334,9 @@ int __mt7925_start(struct mt792x_phy *phy)
 	ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work,
 				     MT792x_WATCHDOG_TIME);
 
+	if (phy->chip_cap & MT792x_CHIP_CAP_WF_RF_PIN_CTRL_EVT_EN)
+		wiphy_rfkill_start_polling(mphy->hw->wiphy);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(__mt7925_start);
@@ -2205,6 +2208,18 @@ static void mt7925_unassign_vif_chanctx(struct ieee80211_hw *hw,
 	mutex_unlock(&dev->mt76.mutex);
 }
 
+static void mt7925_rfkill_poll(struct ieee80211_hw *hw)
+{
+	struct mt792x_phy *phy = mt792x_hw_phy(hw);
+	int ret = 0;
+
+	mt792x_mutex_acquire(phy->dev);
+	ret = mt7925_mcu_wf_rf_pin_ctrl(phy);
+	mt792x_mutex_release(phy->dev);
+
+	wiphy_rfkill_set_hw_state(hw->wiphy, ret ? false : true);
+}
+
 const struct ieee80211_ops mt7925_ops = {
 	.tx = mt792x_tx,
 	.start = mt7925_start,
@@ -2265,6 +2280,7 @@ const struct ieee80211_ops mt7925_ops = {
 	.link_info_changed = mt7925_link_info_changed,
 	.change_vif_links = mt7925_change_vif_links,
 	.change_sta_links = mt7925_change_sta_links,
+	.rfkill_poll = mt7925_rfkill_poll,
 };
 EXPORT_SYMBOL_GPL(mt7925_ops);
 
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
index 286f602623c0..31fa092d2c8c 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
@@ -3633,6 +3633,45 @@ int mt7925_mcu_set_rate_txpower(struct mt76_phy *phy)
 	return 0;
 }
 
+int mt7925_mcu_wf_rf_pin_ctrl(struct mt792x_phy *phy)
+{
+#define UNI_CMD_RADIO_STATUS_GET	0
+	struct mt792x_dev *dev = phy->dev;
+	struct sk_buff *skb;
+	int ret;
+
+	struct {
+		__le16 tag;
+		__le16 len;
+		u8 rsv[4];
+	} __packed req = {
+		.tag = UNI_CMD_RADIO_STATUS_GET,
+		.len = cpu_to_le16(sizeof(req)),
+	};
+
+	struct mt7925_radio_status_event {
+		__le16 tag;
+		__le16 len;
+
+		u8 data;
+		u8 rsv[3];
+	} __packed * status;
+
+	ret = mt76_mcu_send_and_get_msg(&dev->mt76,
+					MCU_UNI_CMD(RADIO_STATUS),
+					&req, sizeof(req), true, &skb);
+	if (ret)
+		return ret;
+
+	skb_pull(skb, sizeof(struct tlv));
+	status = (struct mt7925_radio_status_event *)skb->data;
+	ret = (int)status->data;
+
+	dev_kfree_skb(skb);
+
+	return ret;
+}
+
 int mt7925_mcu_set_rxfilter(struct mt792x_dev *dev, u32 fif,
 			    u8 bit_op, u32 bit_map)
 {
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h b/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
index 4e50f2597ccd..283a40badd28 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
@@ -365,5 +365,6 @@ int mt7925_mcu_wtbl_update_hdr_trans(struct mt792x_dev *dev,
 				     struct ieee80211_vif *vif,
 				     struct ieee80211_sta *sta,
 				     int link_id);
+int mt7925_mcu_wf_rf_pin_ctrl(struct mt792x_phy *phy);
 
 #endif
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/pci.c b/drivers/net/wireless/mediatek/mt76/mt7925/pci.c
index c7b5dc1dbb34..b997cd8bf8d0 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/pci.c
@@ -31,6 +31,10 @@ static void mt7925e_unregister_device(struct mt792x_dev *dev)
 {
 	int i;
 	struct mt76_connac_pm *pm = &dev->pm;
+	struct ieee80211_hw *hw = mt76_hw(dev);
+
+	if (dev->phy.chip_cap & MT792x_CHIP_CAP_WF_RF_PIN_CTRL_EVT_EN)
+		wiphy_rfkill_stop_polling(hw->wiphy);
 
 	cancel_work_sync(&dev->init_work);
 	mt76_unregister_device(&dev->mt76);
-- 
2.45.2



From filip.gerlowski at bizotrix.pl  Mon May  5 01:00:54 2025
From: filip.gerlowski at bizotrix.pl (Filip Gerlowski)
Date: Mon,  5 May 2025 08:00:54 GMT
Subject: =?UTF-8?Q?S=C5=82owa_kluczowe_do_wypozycjonowania_?=
Message-ID: <20250505084500-0.1.9x.k2i5.0.smbkmfr9tw@bizotrix.pl>

Dzie? dobry,

zapozna?em si? z Pa?stwa stron? i z przyjemno?ci? przyznaj?, ?e przyci?ga uwag? i zach?ca do dalszych rozm?w. 

Pomy?la?em, ?e mo?e m?g?bym mie? sw?j wk?ad w Pa?stwa rozw?j i pom?c dotrze? z t? ofert? do wi?kszego grona odbiorc?w. Pozycjonuj? strony www, dzi?ki czemu generuj? ?wietny ruch w sieci.

Mo?emy porozmawia? w najbli?szym czasie?


Pozdrawiam
Filip Gerlowski


From michael-cy.lee at mediatek.com  Mon May  5 01:19:46 2025
From: michael-cy.lee at mediatek.com (Michael-CY Lee)
Date: Mon, 5 May 2025 16:19:46 +0800
Subject: [PATCH] wifi: mac80211: fix the type of status_code for negotiated TID to Link Mapping
Message-ID: <20250505081946.3927214-1-michael-cy.lee@mediatek.com>

The status code should be type of __le16.

Fixes: 83e897a961b8 ("wifi: ieee80211: add definitions for negotiated TID to Link map")
Fixes: 8f500fbc6c65 ("wifi: mac80211: process and save negotiated TID to Link mapping request")
Signed-off-by: Michael-CY Lee <michael-cy.lee at mediatek.com>
---
 include/linux/ieee80211.h |  2 +-
 net/mac80211/mlme.c       | 13 +++++++------
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h
index 508d466de1cc..457b4fba88bd 100644
--- a/include/linux/ieee80211.h
+++ b/include/linux/ieee80211.h
@@ -1526,7 +1526,7 @@ struct ieee80211_mgmt {
 				struct {
 					u8 action_code;
 					u8 dialog_token;
-					u8 status_code;
+					__le16 status_code;
 					u8 variable[];
 				} __packed ttlm_res;
 				struct {
diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c
index c010bb3d24e3..5d1cd42160a0 100644
--- a/net/mac80211/mlme.c
+++ b/net/mac80211/mlme.c
@@ -7675,6 +7675,7 @@ ieee80211_send_neg_ttlm_res(struct ieee80211_sub_if_data *sdata,
 	int hdr_len = offsetofend(struct ieee80211_mgmt, u.action.u.ttlm_res);
 	int ttlm_max_len = 2 + 1 + sizeof(struct ieee80211_ttlm_elem) + 1 +
 		2 * 2 * IEEE80211_TTLM_NUM_TIDS;
+	u16 status_code;
 
 	skb = dev_alloc_skb(local->tx_headroom + hdr_len + ttlm_max_len);
 	if (!skb)
@@ -7697,19 +7698,18 @@ ieee80211_send_neg_ttlm_res(struct ieee80211_sub_if_data *sdata,
 		WARN_ON(1);
 		fallthrough;
 	case NEG_TTLM_RES_REJECT:
-		mgmt->u.action.u.ttlm_res.status_code =
-			WLAN_STATUS_DENIED_TID_TO_LINK_MAPPING;
+		status_code = WLAN_STATUS_DENIED_TID_TO_LINK_MAPPING;
 		break;
 	case NEG_TTLM_RES_ACCEPT:
-		mgmt->u.action.u.ttlm_res.status_code = WLAN_STATUS_SUCCESS;
+		status_code = WLAN_STATUS_SUCCESS;
 		break;
 	case NEG_TTLM_RES_SUGGEST_PREFERRED:
-		mgmt->u.action.u.ttlm_res.status_code =
-			WLAN_STATUS_PREF_TID_TO_LINK_MAPPING_SUGGESTED;
+		status_code = WLAN_STATUS_PREF_TID_TO_LINK_MAPPING_SUGGESTED;
 		ieee80211_neg_ttlm_add_suggested_map(skb, neg_ttlm);
 		break;
 	}
 
+	mgmt->u.action.u.ttlm_res.status_code = cpu_to_le16(status_code);
 	ieee80211_tx_skb(sdata, skb);
 }
 
@@ -7875,7 +7875,8 @@ void ieee80211_process_neg_ttlm_res(struct ieee80211_sub_if_data *sdata,
 	 * This can be better implemented in the future, to handle request
 	 * rejections.
 	 */
-	if (mgmt->u.action.u.ttlm_res.status_code != WLAN_STATUS_SUCCESS)
+	if (le16_to_cpu(mgmt->u.action.u.ttlm_res.status_code) !=
+	    WLAN_STATUS_SUCCESS)
 		__ieee80211_disconnect(sdata);
 }
 
-- 
2.25.1



From fossben at pm.me  Mon May  5 01:20:16 2025
From: fossben at pm.me (fossben at pm.me)
Date: Mon, 05 May 2025 08:20:16 +0000
Subject: [REGRESSION][BISECTED][STABLE] MT7925: mDNS and IPv6 broken in kernel 6.14.3 and above
In-Reply-To: <28ef2cc608d071d1530902d7b5df045555ab5651.camel@mediatek.com>
References: <EmWnO5b-acRH1TXbGnkx41eJw654vmCR-8_xMBaPMwexCnfkvKCdlU5u19CGbaapJ3KRu-l3B-tSUhf8CCQwL0odjo6Cd5YG5lvNeB-vfdg=@pm.me> <f73dec60b60dd7bb3be40c1feefbe223c7afe19b.camel@mediatek.com> <5ae1ef34c9844d6d0f5fb167dd596a4c43321367.camel@kernel.org> <28ef2cc608d071d1530902d7b5df045555ab5651.camel@mediatek.com>
Message-ID: <Q8fBN4506NOX9rrFspv9q0xuQRlE1YcHDbwfRUlXy7if-Lv-kGyIXPrNN2kOMoWENMYCfTmOhAhnSCs4gtUvpzEf0O_JZ_BV__V3B_A7iU8=@pm.me>

On Monday, May 5th, 2025 at 12:48 AM, Mingyen Hsieh <Mingyen.Hsieh at mediatek.com> wrote:

> On Sun, 2025-05-04 at 00:39 +0200, Niklas Schnelle wrote:
> > 
> > External email : Please do not click links or open attachments until
> > you have verified the sender or the content.
> > 
> > 
> > On Wed, 2025-04-30 at 06:47 +0000, Mingyen Hsieh (???) wrote:
> > > On Wed, 2025-04-30 at 01:14 +0000, fossben at pm.me?wrote:
> > > > 
> > > > External email : Please do not click links or open attachments
> > > > until
> > > > you have verified the sender or the content.
> > > > 
> > > > 
> > > > Hello all,
> > > > 
> > > > After upgrading to 6.14.3 on my PC with a MT7925 chip, I noticed
> > > > that
> > > > I could no longer ping *.local addresses provided by Avahi. In
> > > > addition, I also noticed that I was not able to get a DHCP IPv6
> > > > address from my router, no matter how many times I rebooted the
> > > > router or reconnected with NetworkManager.
> > > > 
> > > > Reverting to 6.14.2 fixes both mDNS and IPv6 addresses
> > > > immediately.
> > > > Going back to 6.14.3 immediately breaks mDNS again, but the IPv6
> > > > address will stay there for a while before disappearing later,
> > > > possibly because the DHCP lease expired? I am not sure exactly
> > > > when
> > > > it stops working.
> > > > 
> > > > I've done a kernel bisect between 6.14.2 and 6.14.3 and found the
> > > > offending commit that causes mDNS to fail:
> > > > 
> > > > commit 80007d3f92fd018d0a052a706400e976b36e3c87
> > > > Author: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
> > > > Date:?? Tue Mar 4 16:08:50 2025 -0800
> > > > 
> > > > ??? wifi: mt76: mt7925: integrate *mlo_sta_cmd and *sta_cmd
> > > > 
> > > > ??? commit cb1353ef34735ec1e5d9efa1fe966f05ff1dc1e1 upstream.
> > > > 
> > > > ??? Integrate *mlo_sta_cmd and *sta_cmd for the MLO firmware.
> > > > 
> > > > ??? Fixes: 86c051f2c418 ("wifi: mt76: mt7925: enabling MLO when
> > > > the
> > > > firmware supports it")
> > > > 
> > > > ?drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 59 ++++-------
> > > > ----
> > > > --------------------------------------------
> > > > ?1 file changed, 4 insertions(+), 55 deletions(-)
> > > > 
> > > > I do not know if this same commit is also causing the IPv6 issues
> > > > as
> > > > testing that requires quite a bit of time to reproduce. What I do
> > > > know with certainty as of this moment is that it definitely
> > > > breaks in
> > > > kernel 6.14.3.
> > > > 
> > > > I've attached my hardware info as well as dmesg logs from the
> > > > last
> > > > working kernel from the bisect and 6.14.4 which exhibits the
> > > > issue.
> > > > Please let me know if there's any other info you need.
> > > > 
> > > > Thanks!
> > > > Benjamin Xiao
> > > 
> > > Hi,
> > > 
> > > Thanks for reporting this issue, we will aim into this.
> > > 
> > > Can you provide me with your testing steps?
> > > 
> > > Best Regards,
> > > Yen.
> > > 
> > 
> > Hi Yan,
> > 
> > I see the same IPv6 issue on my Framework 13 (Ryzen 5 AI 340) with an
> > mt7925e WiFI module. My setup is just a home router with native IPv6
> > both for my uplink and in the LAN. The problems with IPv6 can already
> > be seen just in the LAN for example by checking which IP was used for
> > SSH, in my setup it should always be IPv6 but falls back to IPv4 in
> > the
> > broken state.
> > 
> > As another data point, I tried reverting cb1353ef3473 ("wifi: mt76:
> > mt7925: integrate *mlo_sta_cmd and *sta_cmd") on top of 6.15.-rc4.
> > This
> > fully restores IPv6 for me. Also note I'm running this with the
> > mt7925
> > firmware version 20250425073330 from linux-firmware's master branch
> > as
> > I had some dropped connections with earlier firmware.
> > 
> > So it definitely looks like that commit also broke IPv6 and not just
> > mDNS. Note that if if I use DHCPv6 instead of router advertisements,
> > on
> > the latest firmware, but without the revert, I get a global IPv6
> > address added to the interface but then native IPv6 addresses are
> > still
> > uncreachable. With the offending patch reverted my SSH session to an
> > IPv6 only host works fine and is stable. Also I'd be willing to test
> > a
> > proper fix as I rely on IPv6 heavily due to having to use CGNAT for
> > IPv4 but not for IPv6.
> > 
> > 
> > Thanks,
> > Niklas
> 
> Hi Benjamin & Niklas,
> 
> Can you help to try this patch? I can get IPv6 address through this
> patch.
> 
> If it can work at your environment as well, i will upstream it and add
> test tag with you.
> 
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> index a42b584634ab..fd756f0d18f8 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> @@ -2183,14 +2183,14 @@ mt7925_mcu_sta_cmd(struct mt76_phy *phy,
>                         mt7925_mcu_sta_mld_tlv(skb, info->vif, info-
> >link_sta->sta);
>                         mt7925_mcu_sta_eht_mld_tlv(skb, info->vif,
> info->link_sta->sta);
>                 }
> -
> -               mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info-
> >link_sta);
>         }
> 
>         if (!info->enable) {
>                 mt7925_mcu_sta_remove_tlv(skb);
>                 mt76_connac_mcu_add_tlv(skb, STA_REC_MLD_OFF,
>                                         sizeof(struct tlv));
> +       } else {
> +               mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info-
> >link_sta);
>         }
> 
>         return mt76_mcu_skb_send_msg(dev, skb, info->cmd, true);
> 
> 
> Thanks~
> Yen.

Hi Yen,

I manually applied the changes on top of 6.14.5 and mDNS seems to work along with IPv6! I will do more testing for the rest of the day to see if the issue is completely fixed but so far looks good at least for the 5 minutes I've been testing it.

Thanks for the fix,
Ben


From luca.ceresoli at bootlin.com  Mon May  5 04:06:48 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Mon, 5 May 2025 13:06:48 +0200
Subject: (subset) [PATCH v2 00/34] drm: convert all bridges to
 devm_drm_bridge_alloc()
In-Reply-To: <20250430-arrogant-marmoset-of-justice-92ced3@houat>
References: <20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b@bootlin.com>
	<174591887152.961603.7706063017853945511.b4-ty@bootlin.com>
	<832a9db0-cf8a-4d35-8a98-08053fbd6723@bootlin.com>
	<20250430-arrogant-marmoset-of-justice-92ced3@houat>
Message-ID: <20250505130648.22ec8716@booty>

Inki, Kyungmin, Seung-Woo, Alim,

On Wed, 30 Apr 2025 10:08:14 +0200
Maxime Ripard <mripard at kernel.org> wrote:

> Inki, Kyungmin, Seung-Woo, sorry for the mishap. Do you agree with the
> following patch, and it going through drm-misc?
> 
> https://lore.kernel.org/dri-devel/20250424-drm-bridge-convert-to-alloc-api-v2-14-8f91a404d86b at bootlin.com/
> 
> If not, we'll revert.

Did you have a chance to have a look at the patch mentioned by Maxime?

It was applied to drm-misc-next by mistake. Not your mistake of course,
but now it's there so if you don't reply anything it will have to be
reverted, and then sent again to go through all the review process to
be hopefully re-applied in the future.

If you agree with keeping it in drm-misc-next, that would be less noise
for everybody.

I'm going to send v3 very soon, so it would be good to decide what to
do before that.

Best regards,
Luca

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


From philmd at linaro.org  Mon May  5 04:16:58 2025
From: philmd at linaro.org (=?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?=)
Date: Mon, 5 May 2025 13:16:58 +0200
Subject: [PATCH v4 5/7] dt-bindings: vendor-prefixes: Add SmartFiber
In-Reply-To: <20250430133433.22222-6-cjd@cjdns.fr>
References: <20250430133433.22222-1-cjd@cjdns.fr>
 <20250430133433.22222-6-cjd@cjdns.fr>
Message-ID: <9b93c67c-b163-4026-be7a-a8761a0f21f0@linaro.org>

On 30/4/25 15:34, Caleb James DeLisle wrote:
> Add "smartfiber" vendor prefix for manufactorer of EcoNet based boards.
> 
> Signed-off-by: Caleb James DeLisle <cjd at cjdns.fr>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> ---
>   Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>   1 file changed, 2 insertions(+)

Reviewed-by: Philippe Mathieu-Daud? <philmd at linaro.org>



From philmd at linaro.org  Mon May  5 04:17:56 2025
From: philmd at linaro.org (=?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?=)
Date: Mon, 5 May 2025 13:17:56 +0200
Subject: [PATCH v4 7/7] MAINTAINERS: Add entry for newly added EcoNet
 platform.
In-Reply-To: <20250430133433.22222-8-cjd@cjdns.fr>
References: <20250430133433.22222-1-cjd@cjdns.fr>
 <20250430133433.22222-8-cjd@cjdns.fr>
Message-ID: <33708722-6986-40d2-92c8-38832467b857@linaro.org>

On 30/4/25 15:34, Caleb James DeLisle wrote:
> Add a MAINTAINERS entry as part of integration of the EcoNet MIPS platform.
> 
> Signed-off-by: Caleb James DeLisle <cjd at cjdns.fr>
> ---
>   MAINTAINERS | 12 ++++++++++++
>   1 file changed, 12 insertions(+)

Reviewed-by: Philippe Mathieu-Daud? <philmd at linaro.org>



From dmitry.baryshkov at oss.qualcomm.com  Mon May  5 04:58:58 2025
From: dmitry.baryshkov at oss.qualcomm.com (Dmitry Baryshkov)
Date: Mon, 5 May 2025 14:58:58 +0300
Subject: (subset) [PATCH v2 00/34] drm: convert all bridges to
 devm_drm_bridge_alloc()
In-Reply-To: <20250505130648.22ec8716@booty>
References: <20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b@bootlin.com>
 <174591887152.961603.7706063017853945511.b4-ty@bootlin.com>
 <832a9db0-cf8a-4d35-8a98-08053fbd6723@bootlin.com>
 <20250430-arrogant-marmoset-of-justice-92ced3@houat>
 <20250505130648.22ec8716@booty>
Message-ID: <9afd098c-edd3-44fa-8efe-99f2e9c9a525@oss.qualcomm.com>

On 05/05/2025 14:06, Luca Ceresoli wrote:
> Inki, Kyungmin, Seung-Woo, Alim,
> 
> On Wed, 30 Apr 2025 10:08:14 +0200
> Maxime Ripard <mripard at kernel.org> wrote:
> 
>> Inki, Kyungmin, Seung-Woo, sorry for the mishap. Do you agree with the
>> following patch, and it going through drm-misc?
>>
>> https://lore.kernel.org/dri-devel/20250424-drm-bridge-convert-to-alloc-api-v2-14-8f91a404d86b at bootlin.com/
>>
>> If not, we'll revert.
> 
> Did you have a chance to have a look at the patch mentioned by Maxime?
> 
> It was applied to drm-misc-next by mistake. Not your mistake of course,
> but now it's there so if you don't reply anything it will have to be
> reverted, and then sent again to go through all the review process to
> be hopefully re-applied in the future.
> 
> If you agree with keeping it in drm-misc-next, that would be less noise
> for everybody.
> 
> I'm going to send v3 very soon, so it would be good to decide what to
> do before that.

For the record: even though I'm not happy with msm-related patches going 
through drm-misc without additional ack from our side, I think reverting 
those and reapplying them later will create a bigger mess. So, I'm fine 
with keeping drm/msm/* bridged patches in.

-- 
With best wishes
Dmitry


From sirius.wang at mediatek.com  Mon May  5 05:15:44 2025
From: sirius.wang at mediatek.com (Sirius Wang)
Date: Mon, 5 May 2025 20:15:44 +0800
Subject: [PATCH 0/2] Add mt8189 dts evaluation board and Mafefile
Message-ID: <20250505121627.3944728-1-sirius.wang@mediatek.com>

MT8189 is a SoC based on 64bit ARMv8 architecture. It contains 6 CA55
and 2 CA78 cores. MT8189 share many HW IP with MT8188 series.

We add basic chip support for MediaTek MT8189 on evaluation board.

In this series, we also add dt-bindings document definition for MT8189.

Sirius Wang (2):
  WIP: dt-bindings: arm: Add compatible for MediaTek MT8189
  WIP: arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile

 .../devicetree/bindings/arm/mediatek.yaml     |   4 +
 arch/arm64/boot/dts/mediatek/Makefile         |   1 +
 arch/arm64/boot/dts/mediatek/mt8189-evb.dts   |  20 +
 arch/arm64/boot/dts/mediatek/mt8189.dtsi      | 441 ++++++++++++++++++
 4 files changed, 466 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi

-- 
2.45.2



From sirius.wang at mediatek.com  Mon May  5 05:15:45 2025
From: sirius.wang at mediatek.com (Sirius Wang)
Date: Mon, 5 May 2025 20:15:45 +0800
Subject: [PATCH 1/2] WIP: dt-bindings: arm: Add compatible for MediaTek MT8189
In-Reply-To: <20250505121627.3944728-1-sirius.wang@mediatek.com>
References: <20250505121627.3944728-1-sirius.wang@mediatek.com>
Message-ID: <20250505121627.3944728-2-sirius.wang@mediatek.com>

This commit adds dt-binding documentation for the MediaTek MT8189
reference board.

BUG=b:387230785
BUG=b:387229727
BUG=b:362203280

TEST=emerge-skywalker chromeos-kernel-6_6

Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>
---
 Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index fa1646bc0bac..05e827076a7f 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -372,6 +372,10 @@ properties:
           - enum:
               - mediatek,mt8188-evb
           - const: mediatek,mt8188
+      - items:
+          - enum:
+              - mediatek,mt8189-evb
+          - const: mediatek,mt8189
       - description: Google Hayato
         items:
           - const: google,hayato-rev1
-- 
2.45.2



From sirius.wang at mediatek.com  Mon May  5 05:15:46 2025
From: sirius.wang at mediatek.com (Sirius Wang)
Date: Mon, 5 May 2025 20:15:46 +0800
Subject: [PATCH 2/2] WIP: arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile
In-Reply-To: <20250505121627.3944728-1-sirius.wang@mediatek.com>
References: <20250505121627.3944728-1-sirius.wang@mediatek.com>
Message-ID: <20250505121627.3944728-3-sirius.wang@mediatek.com>

MT8189 is a SoC based on 64bit ARMv8 architecture. It contains 6 CA55
and 2 CA78 cores. MT8189 share many HW IP with MT8188 series.

We add basic chip support for MediaTek MT8189 on evaluation board.

BUG=b:387230785
TEST=emerge-skywalker chromeos-kernel-6_6

Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>
---
 arch/arm64/boot/dts/mediatek/Makefile       |   1 +
 arch/arm64/boot/dts/mediatek/mt8189-evb.dts |  20 +
 arch/arm64/boot/dts/mediatek/mt8189.dtsi    | 441 ++++++++++++++++++++
 3 files changed, 462 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 3aa06476c6c0..ad2ac9e1bb79 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8189-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
new file mode 100644
index 000000000000..e5d9ce1b8e61
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ * Author: Sirius Wang <sirius.wang at mediatek.com>
+ */
+/dts-v1/;
+#include "mt8189.dtsi"
+
+/ {
+	model = "MediaTek MT8189 evaluation board";
+	compatible = "mediatek,mt8189-evb", "mediatek,mt8189";
+
+	chosen: chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
new file mode 100644
index 000000000000..de59d858bcf3
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
@@ -0,0 +1,441 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset/ti-syscon.h>
+
+/ {
+	compatible = "mediatek,mt8189";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x000>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu1: cpu at 100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu2: cpu at 200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu3: cpu at 300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu4: cpu at 400 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x400>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu5: cpu at 500 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x500>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu6: cpu at 600 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78";
+			reg = <0x600>;
+			enable-method = "psci";
+			clock-frequency = <3000000000>;
+			capacity-dmips-mhz = <958>;
+			cpu-idle-states = <&cpuoff_m &clusteroff_m &mcusysoff_m &system_vcore &s2idle>;
+			i-cache-size = <65536>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <65536>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_1>;
+			performance-domains = <&performance 1>;
+			#cooling-cells = <2>;
+		};
+
+		cpu7: cpu at 700 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78";
+			reg = <0x700>;
+			enable-method = "psci";
+			clock-frequency = <3000000000>;
+			capacity-dmips-mhz = <958>;
+			cpu-idle-states = <&cpuoff_m &clusteroff_m &mcusysoff_m &system_vcore &s2idle>;
+			i-cache-size = <65536>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <65536>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_1>;
+			performance-domains = <&performance 1>;
+			#cooling-cells = <2>;
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+				core4 {
+					cpu = <&cpu4>;
+				};
+				core5 {
+					cpu = <&cpu5>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu6>;
+				};
+				core1 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		idle-states {
+			entry-method = "arm,psci";
+
+			cpuoff_l: cpuoff-l {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x00010000>;
+				local-timer-stop;
+				entry-latency-us = <97>;
+				exit-latency-us = <252>;
+				min-residency-us = <6710>;
+			};
+
+			cpuoff_m: cpuoff-m {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x00010000>;
+				local-timer-stop;
+				entry-latency-us = <53>;
+				exit-latency-us = <143>;
+				min-residency-us = <2120>;
+			};
+
+			cpuoff_b: cpuoff-b {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x00010000>;
+				local-timer-stop;
+				entry-latency-us = <40>;
+				exit-latency-us = <107>;
+				min-residency-us = <2580>;
+			};
+
+			clusteroff_l: clusteroff-l {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x01010001>;
+				local-timer-stop;
+				entry-latency-us = <109>;
+				exit-latency-us = <325>;
+				min-residency-us = <6710>;
+			};
+
+			clusteroff_m: clusteroff-m {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x01010001>;
+				local-timer-stop;
+				entry-latency-us = <59>;
+				exit-latency-us = <188>;
+				min-residency-us = <2120>;
+			};
+
+			clusteroff_b: clusteroff-b {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x01010001>;
+				local-timer-stop;
+				entry-latency-us = <43>;
+				exit-latency-us = <138>;
+				min-residency-us = <2580>;
+			};
+
+			mcusysoff_l: mcusysoff-l {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x02010007>;
+				local-timer-stop;
+				entry-latency-us = <1357>;
+				exit-latency-us = <835>;
+				min-residency-us = <6710>;
+			};
+
+			mcusysoff_m: mcusysoff-m {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x02010007>;
+				local-timer-stop;
+				entry-latency-us = <1202>;
+				exit-latency-us = <679>;
+				min-residency-us = <2120>;
+			};
+
+			mcusysoff_b: mcusysoff-b {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x02010007>;
+				local-timer-stop;
+				entry-latency-us = <1143>;
+				exit-latency-us = <611>;
+				min-residency-us = <2580>;
+			};
+
+			system_vcore: system-vcore {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x020100ff>;
+				local-timer-stop;
+				entry-latency-us = <940>;
+				exit-latency-us = <3500>;
+				min-residency-us = <35200>;
+			};
+
+			s2idle: s2idle {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x020180ff>;
+				local-timer-stop;
+				entry-latency-us = <10000>;
+				exit-latency-us = <10000>;
+				min-residency-us = <4294967295>;
+			};
+		};
+
+		l2_0: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <131072>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			next-level-cache = <&l3_0>;
+			cache-unified;
+		};
+
+		l2_1: l2-cache1 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <262144>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			next-level-cache = <&l3_0>;
+			cache-unified;
+		};
+
+		l3_0: l3-cache {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-size = <1048576>;
+			cache-line-size = <64>;
+			cache-sets = <2048>;
+			cache-unified;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	clocks {
+		clk_null: clk-null {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+
+		clk32k: clk32k {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32000>;
+		};
+
+		clk26m: clk26m {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <26000000>;
+		};
+
+		clk13m: clk13m {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <13000000>;
+		};
+
+		ulposc: ulposc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <520000000>;
+		};
+
+		ulposc3: ulposc3 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <26000000>;
+		};
+
+		clk104m: clk104m {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <104000000>;
+		};
+	};
+
+	memory: memory {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0xC0000000>;
+	};
+
+	timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+				<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+				<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+				<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+		clock-frequency = <13000000>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+
+		performance: performance-controller at 11bc10 {
+			compatible = "mediatek,cpufreq-hw";
+			reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+			#performance-domain-cells = <1>;
+		};
+
+		gic: interrupt-controller at c000000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <4>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			#redistributor-regions = <1>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			reg = <0 0xc000000 0 0x40000>, /* distributor */
+			      <0 0xc040000 0 0x200000>; /* redistributor */
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+		};
+
+		uart0: serial at 11001000 {
+			compatible = "mediatek,mt6577-uart";
+			reg = <0 0x11001000 0 0x1000>;
+			interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&clk26m>;
+			clock-names = "baud", "bus";
+			uart-line = <0>;
+		};
+	};
+};
-- 
2.45.2



From luca.ceresoli at bootlin.com  Mon May  5 05:31:58 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Mon, 5 May 2025 14:31:58 +0200
Subject: (subset) [PATCH v2 00/34] drm: convert all bridges to
 devm_drm_bridge_alloc()
In-Reply-To: <9afd098c-edd3-44fa-8efe-99f2e9c9a525@oss.qualcomm.com>
References: <20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b@bootlin.com>
	<174591887152.961603.7706063017853945511.b4-ty@bootlin.com>
	<832a9db0-cf8a-4d35-8a98-08053fbd6723@bootlin.com>
	<20250430-arrogant-marmoset-of-justice-92ced3@houat>
	<20250505130648.22ec8716@booty>
	<9afd098c-edd3-44fa-8efe-99f2e9c9a525@oss.qualcomm.com>
Message-ID: <20250505143158.75541d7c@booty>

Hi Dmitry,

On Mon, 5 May 2025 14:58:58 +0300
Dmitry Baryshkov <dmitry.baryshkov at oss.qualcomm.com> wrote:

> On 05/05/2025 14:06, Luca Ceresoli wrote:
> > Inki, Kyungmin, Seung-Woo, Alim,
> > 
> > On Wed, 30 Apr 2025 10:08:14 +0200
> > Maxime Ripard <mripard at kernel.org> wrote:
> >   
> >> Inki, Kyungmin, Seung-Woo, sorry for the mishap. Do you agree with the
> >> following patch, and it going through drm-misc?
> >>
> >> https://lore.kernel.org/dri-devel/20250424-drm-bridge-convert-to-alloc-api-v2-14-8f91a404d86b at bootlin.com/
> >>
> >> If not, we'll revert.  
> > 
> > Did you have a chance to have a look at the patch mentioned by Maxime?
> > 
> > It was applied to drm-misc-next by mistake. Not your mistake of course,
> > but now it's there so if you don't reply anything it will have to be
> > reverted, and then sent again to go through all the review process to
> > be hopefully re-applied in the future.
> > 
> > If you agree with keeping it in drm-misc-next, that would be less noise
> > for everybody.
> > 
> > I'm going to send v3 very soon, so it would be good to decide what to
> > do before that.  
> 
> For the record: even though I'm not happy with msm-related patches going 
> through drm-misc without additional ack from our side, I think reverting 
> those and reapplying them later will create a bigger mess. So, I'm fine 
> with keeping drm/msm/* bridged patches in.

That was my understanding of your previous e-mail, but thanks for
having made it explicit.

Luca

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


From julien.massot at collabora.com  Mon May  5 06:23:36 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Mon, 05 May 2025 15:23:36 +0200
Subject: [PATCH 0/4] mt8395/mt6359: Fix several dtb-check errors
Message-ID: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>

Hi,
This patch series addresses several dtb-check errors reported for the mt8395-genio-1200-evk.dtb and mt8395-radxa-nio-12l.dtb device trees.

The fixes include:
- Adding the missing #sound-dai-cells property in the mt6397 binding.
- Allowing up to 5 interrupts in the MediaTek IOMMU binding to support MT8395 properly.
- Defining the required compatible property in the regulators node of the mt6359.dtsi.
- Renaming the rtc node to match expected schema naming.

Signed-off-by: Julien Massot <julien.massot at collabora.com>
---
Julien Massot (4):
      dt-bindings: mfd: mediatek: mt6397: Add #sound-dai-cells property
      dt-bindings: iommu: mediatek: mt8195 Accept up to 5 interrupts
      arm64: dts: mt6359: Add missing 'compatible' property to regulators node
      arm64: dts: mt6359: Rename RTC node to match binding expectations

 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 3 ++-
 Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml  | 3 +++
 arch/arm64/boot/dts/mediatek/mt6359.dtsi                    | 4 +++-
 3 files changed, 8 insertions(+), 2 deletions(-)
---
base-commit: 407f60a151df3c44397e5afc0111eb9b026c38d3
change-id: 20250505-mt8395-dtb-errors-0847ffc12f44

Best regards,
-- 
Julien Massot <julien.massot at collabora.com>



From julien.massot at collabora.com  Mon May  5 06:23:37 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Mon, 05 May 2025 15:23:37 +0200
Subject: [PATCH 1/4] dt-bindings: mfd: mediatek: mt6397: Add
 #sound-dai-cells property
In-Reply-To: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
Message-ID: <20250505-mt8395-dtb-errors-v1-1-9c4714dcdcdb@collabora.com>

The 'mt6359.dtsi' file already uses the '#sound-dai-cells' property.
Add the corresponding property to the binding to fix the following
dtb-check error:

mediatek/mt8395-radxa-nio-12l.dtb: pmic: '#sound-dai-cells', 'mt6359rtc' do not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6397.yaml#

Fixes: 9bc8353be720 ("arm64: dts: mt6359: Add #sound-dai-cells property")
Signed-off-by: Julien Massot <julien.massot at collabora.com>
---
 Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
index 6a89b479d10fad3c8b61cab5a3af1453baca4d1a..86fc1b5db3b075ea0f6e35f58ecbca7956d230c4 100644
--- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
+++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
@@ -53,6 +53,9 @@ properties:
   "#interrupt-cells":
     const: 2
 
+  '#sound-dai-cells':
+    const: 1
+
   rtc:
     type: object
     $ref: /schemas/rtc/rtc.yaml#

-- 
2.49.0



From julien.massot at collabora.com  Mon May  5 06:23:38 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Mon, 05 May 2025 15:23:38 +0200
Subject: [PATCH 2/4] dt-bindings: iommu: mediatek: mt8195 Accept up to 5
 interrupts
In-Reply-To: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
Message-ID: <20250505-mt8395-dtb-errors-v1-2-9c4714dcdcdb@collabora.com>

Some Mediatek IOMMU can have up to five interrupts so increase
the 'maxItems' to 5.

Fix the following dtb-check error:

mediatek/mt8395-radxa-nio-12l.dtb: infra-iommu at 10315000: interrupts:
[[0, 795, 4, 0], [0, 796, 4, 0], [0, 797, 4, 0], [0, 798, 4, 0], [0, 799, 4, 0]] is too long

Fixes: 3b5838d1d82e3 ("arm64: dts: mt8195: Add iommu and smi nodes")
Signed-off-by: Julien Massot <julien.massot at collabora.com>
---
 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index 75750c64157c868725c087500ac81be4e282c829..035941c2db32170e9a69a5363d8c05ef767bb251 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -97,7 +97,8 @@ properties:
     maxItems: 1
 
   interrupts:
-    maxItems: 1
+    minItems: 1
+    maxItems: 5
 
   clocks:
     items:

-- 
2.49.0



From julien.massot at collabora.com  Mon May  5 06:23:39 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Mon, 05 May 2025 15:23:39 +0200
Subject: [PATCH 3/4] arm64: dts: mt6359: Add missing 'compatible' property
 to regulators node
In-Reply-To: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
Message-ID: <20250505-mt8395-dtb-errors-v1-3-9c4714dcdcdb@collabora.com>

The 'compatible' property is required by the
'mfd/mediatek,mt6397.yaml' binding. Add it to fix the following
dtb-check error:
mediatek/mt8395-radxa-nio-12l.dtb: pmic: regulators:
'compatible' is a required property

Fixes: 3b7d143be4b7 ("arm64: dts: mt6359: add PMIC MT6359 related nodes")
Signed-off-by: Julien Massot <julien.massot at collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6359.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi
index 7b10f9c59819a9ad02319f00938f35c931091f9f..0c479404b3fe3adc9789386e34bda4dc580b5abd 100644
--- a/arch/arm64/boot/dts/mediatek/mt6359.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi
@@ -20,6 +20,8 @@ mt6359codec: audio-codec {
 		};
 
 		regulators {
+			compatible = "mediatek,mt6359-regulator";
+
 			mt6359_vs1_buck_reg: buck_vs1 {
 				regulator-name = "vs1";
 				regulator-min-microvolt = <800000>;

-- 
2.49.0



From julien.massot at collabora.com  Mon May  5 06:23:40 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Mon, 05 May 2025 15:23:40 +0200
Subject: [PATCH 4/4] arm64: dts: mt6359: Rename RTC node to match binding
 expectations
In-Reply-To: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
Message-ID: <20250505-mt8395-dtb-errors-v1-4-9c4714dcdcdb@collabora.com>

Rename the node 'mt6359rtc' to 'rtc', as required by the binding.

Fix the following dtb-check error:

mediatek/mt8395-radxa-nio-12l.dtb: pmic: 'mt6359rtc' do not match
any of the regexes: 'pinctrl-[0-9]+'

Fixes: 3b7d143be4b7 ("arm64: dts: mt6359: add PMIC MT6359 related nodes")
---
 arch/arm64/boot/dts/mediatek/mt6359.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi
index 0c479404b3fe3adc9789386e34bda4dc580b5abd..467d8a4c2aa7f16ade92a287ecdeed5089302045 100644
--- a/arch/arm64/boot/dts/mediatek/mt6359.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi
@@ -300,7 +300,7 @@ mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub {
 			};
 		};
 
-		mt6359rtc: mt6359rtc {
+		mt6359rtc: rtc {
 			compatible = "mediatek,mt6358-rtc";
 		};
 	};

-- 
2.49.0



From robh at kernel.org  Mon May  5 07:44:04 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Mon, 05 May 2025 09:44:04 -0500
Subject: [PATCH] arm64: dts: mediatek: mt6357: Drop regulator-fixed
 compatibles
In-Reply-To: <20250502-mt6357-regulator-fixed-compatibles-removal-v1-1-a582c16743fe@collabora.com>
References: <20250502-mt6357-regulator-fixed-compatibles-removal-v1-1-a582c16743fe@collabora.com>
Message-ID: <174645593877.1245991.13955388800540703785.robh@kernel.org>


On Fri, 02 May 2025 11:32:10 -0400, N?colas F. R. A. Prado wrote:
> Some of the regulators in the MT6357 PMIC dtsi have compatible set to
> regulator-fixed, even though they don't serve any purpose: all those
> regulators are handled as a whole by the mt6357-regulator driver. In
> fact this is the only dtsi in this family of chips where this is the
> case: mt6359 and mt6358 don't have any such compatibles.
> 
> A side-effect caused by this is that the DT kselftest, which is supposed
> to identify nodes with compatibles that can be probed, but haven't,
> shows these nodes as failures.
> 
> Remove the useless compatibles to move the dtsi in line with the others
> in its family and fix the DT kselftest failures.
> 
> Fixes: 55749bb478f8 ("arm64: dts: mediatek: add mt6357 device-tree")
> Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt6357.dtsi | 10 ----------
>  1 file changed, 10 deletions(-)
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: using specified base-commit 37ff6e9a2ce321b7932d3987701757fb4d87b0e6

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/mediatek/' for 20250502-mt6357-regulator-fixed-compatibles-removal-v1-1-a582c16743fe at collabora.com:

arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vfe28: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vfe28: 'power-domains' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vfe28: 'required-opps' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vfe28: 'compatible' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vrf18: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vrf18: 'power-domains' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vrf18: 'required-opps' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vrf18: 'compatible' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vrf12: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vrf12: 'power-domains' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vrf12: 'required-opps' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vrf12: 'compatible' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vcn28: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vcn28: 'power-domains' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vcn28: 'required-opps' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vcn28: 'compatible' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vcn18: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vcn18: 'power-domains' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vcn18: 'required-opps' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vcn18: 'compatible' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vcamio18: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vcamio18: 'power-domains' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vcamio18: 'required-opps' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vcamio18: 'compatible' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vaux18: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vaux18: 'power-domains' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vaux18: 'required-opps' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vaux18: 'compatible' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vaud28: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vaud28: 'power-domains' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vaud28: 'required-opps' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vaud28: 'compatible' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vio28: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vio28: 'power-domains' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vio28: 'required-opps' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vio28: 'compatible' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vio18: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vio18: 'power-domains' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vio18: 'required-opps' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb: pmic (mediatek,mt6357): regulators:ldo-vio18: 'compatible' is a required property
	from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml#







From robh at kernel.org  Mon May  5 07:44:10 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Mon, 05 May 2025 09:44:10 -0500
Subject: [PATCH 0/2] Add mt8189 dts evaluation board and Mafefile
In-Reply-To: <20250505121627.3944728-1-sirius.wang@mediatek.com>
References: <20250505121627.3944728-1-sirius.wang@mediatek.com>
Message-ID: <174645594319.1246809.14814085003624998764.robh@kernel.org>


On Mon, 05 May 2025 20:15:44 +0800, Sirius Wang wrote:
> MT8189 is a SoC based on 64bit ARMv8 architecture. It contains 6 CA55
> and 2 CA78 cores. MT8189 share many HW IP with MT8188 series.
> 
> We add basic chip support for MediaTek MT8189 on evaluation board.
> 
> In this series, we also add dt-bindings document definition for MT8189.
> 
> Sirius Wang (2):
>   WIP: dt-bindings: arm: Add compatible for MediaTek MT8189
>   WIP: arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile
> 
>  .../devicetree/bindings/arm/mediatek.yaml     |   4 +
>  arch/arm64/boot/dts/mediatek/Makefile         |   1 +
>  arch/arm64/boot/dts/mediatek/mt8189-evb.dts   |  20 +
>  arch/arm64/boot/dts/mediatek/mt8189.dtsi      | 441 ++++++++++++++++++
>  4 files changed, 466 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi
> 
> --
> 2.45.2
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: attempting to guess base-commit...
 Base: tags/next-20250505 (exact match)

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/mediatek/' for 20250505121627.3944728-1-sirius.wang at mediatek.com:

arch/arm64/boot/dts/mediatek/mt8189-evb.dtb: / (mediatek,mt8189-evb): memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 1073741824, 0, 3221225472]]}
	from schema $id: http://devicetree.org/schemas/root-node.yaml#
arch/arm64/boot/dts/mediatek/mt8189-evb.dtb: idle-states: 'clusteroff-b', 'clusteroff-l', 'clusteroff-m', 'cpuoff-b', 'cpuoff-l', 'cpuoff-m', 'mcusysoff-b', 'mcusysoff-l', 'mcusysoff-m', 's2idle', 'system-vcore' do not match any of the regexes: '^(cpu|cluster)-', '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
arch/arm64/boot/dts/mediatek/mt8189-evb.dtb: idle-states: entry-method:0: 'psci' was expected
	from schema $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
arch/arm64/boot/dts/mediatek/mt8189-evb.dtb: serial at 11001000 (mediatek,mt6577-uart): Unevaluated properties are not allowed ('uart-line' was unexpected)
	from schema $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#







From luca.ceresoli at bootlin.com  Mon May  5 08:20:27 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Mon, 5 May 2025 17:20:27 +0200
Subject: [PATCH v2 34/34] drm/bridge: panel: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250505-beneficial-fossa-of-weather-67c676@houat>
References: <20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b@bootlin.com>
	<20250424-drm-bridge-convert-to-alloc-api-v2-34-8f91a404d86b@bootlin.com>
	<20250428-wild-condor-of-defiance-cadf60@houat>
	<20250428172516.79058e22@booty>
	<20250505-beneficial-fossa-of-weather-67c676@houat>
Message-ID: <20250505172027.25af7721@booty>

On Mon, 5 May 2025 08:23:26 +0200
Maxime Ripard <mripard at kernel.org> wrote:

> On Mon, Apr 28, 2025 at 05:25:16PM +0200, Luca Ceresoli wrote:
> > Hi Maxime,
> > 
> > On Mon, 28 Apr 2025 13:39:23 +0200
> > Maxime Ripard <mripard at kernel.org> wrote:
> >   
> > > On Thu, Apr 24, 2025 at 10:05:49PM +0200, Luca Ceresoli wrote:  
> > > > This is the new API for allocating DRM bridges.
> > > > 
> > > > The devm lifetime management of this driver is peculiar. The underlying
> > > > device for the panel_bridge is the panel, and the devm lifetime is tied the
> > > > panel device (panel->dev). However the panel_bridge allocation is not
> > > > performed by the panel driver, but rather by a separate entity (typically
> > > > the previous bridge in the encoder chain).
> > > > 
> > > > Thus when that separate entoty is destroyed, the panel_bridge is not
> > > > removed automatically by devm, so it is rather done explicitly by calling
> > > > drm_panel_bridge_remove(). This is the function that does devm_kfree() the
> > > > panel_bridge in current code, so update it as well to put the bridge
> > > > reference instead.
> > > > 
> > > > Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>    
> > > 
> > > This looks fine, but we need a TODO entry to clean this up later on, and
> > > a comment on devm_drm_put_bridge that this is inherently unsafe and
> > > must not be used.  
> > 
> > Ah, I see, OK.
> > 
> > Quick draft:
> > 
> >  /**
> >   * devm_drm_put_bridge - Release a bridge reference obtained via devm
> >   * @dev: device that got the bridge via devm
> >   * @bridge: pointer to a struct drm_bridge obtained via devm
> >   *
> >   * Same as drm_bridge_put() for bridge pointers obtained via devm functions
> >   * such as devm_drm_bridge_alloc().
> > + *
> > + * This function is a temporary workaround and MUST NOT be used. Manual
> > + * handling of bridge lifetime is inherently unsafe.
> >   */  
> 
> That part looks good to me
> 
> > and:
> > 
> > -	devm_kfree(panel_bridge->panel->dev, bridge);
> > +       /* TODO remove this after reworking panel_bridge lifetime */
> > +	devm_drm_put_bridge(panel_bridge->panel->dev, bridge);
> >  }
> > 
> > Does it look good enough?  
> 
> That too, but I was talking about an entry in
> https://www.kernel.org/doc/html/latest/gpu/todo.html

Ah, sure!

I queued this for v3, if you have better suggestions don't hesitate to
let me know:

-----8<-----

Remove devm_drm_put_bridge()
----------------------------

Due to how the panel bridge handles the drm_bridge object lifetime, special
care must be taken to dispose of the drm_bridge object when the
panel_bridge is removed. This is currently managed using
devm_drm_put_bridge(), but that is an unsafe, temporary workaround. To fix
that, the DRM panel lifetime needs to be reworked. After the rework is
done, remove devm_drm_put_bridge() and the TODO in drm_panel_bridge_remove().

Contact: Maxime Ripard <mripard at kernel.org>,
         Luca Ceresoli <luca.ceresoli at bootlin.com>

Level: Intermediate

-----8<-----

Luca

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


From daniel.lezcano at linaro.org  Mon May  5 09:36:22 2025
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Mon, 5 May 2025 18:36:22 +0200
Subject: [PATCH v4 2/7] clocksource/drivers: Add EcoNet Timer HPT driver
In-Reply-To: <20250430133433.22222-3-cjd@cjdns.fr>
References: <20250430133433.22222-1-cjd@cjdns.fr>
 <20250430133433.22222-3-cjd@cjdns.fr>
Message-ID: <aBjpBpJAIP89oiit@mai.linaro.org>

On Wed, Apr 30, 2025 at 01:34:28PM +0000, Caleb James DeLisle wrote:
> Introduce a clocksource driver for the so-called high-precision timer (HPT)
> in the EcoNet EN751221 MIPS SoC.

As a new driver, please document the timer (up - down ?, SPI/PPI, etc
...) that will help to understand the code more easily, especially the
reg_* functions (purposes?).

> Signed-off-by: Caleb James DeLisle <cjd at cjdns.fr>
> ---
>  drivers/clocksource/Kconfig                 |   8 +
>  drivers/clocksource/Makefile                |   1 +
>  drivers/clocksource/timer-econet-en751221.c | 216 ++++++++++++++++++++
>  3 files changed, 225 insertions(+)
>  create mode 100644 drivers/clocksource/timer-econet-en751221.c
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 487c85259967..976afb0b2312 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -73,6 +73,14 @@ config DW_APB_TIMER_OF
>  	select DW_APB_TIMER
>  	select TIMER_OF
>  
> +config ECONET_EN751221_TIMER
> +	bool "EcoNet EN751221 High Precision Timer" if COMPILE_TEST
> +	depends on HAS_IOMEM
> +	select CLKSRC_MMIO
> +	select TIMER_OF
> +	help
> +	  Support for CPU timer found on EcoNet MIPS based SoCs.
> +
>  config FTTMR010_TIMER
>  	bool "Faraday Technology timer driver" if COMPILE_TEST
>  	depends on HAS_IOMEM
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 43ef16a4efa6..d2998601eda5 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -17,6 +17,7 @@ obj-$(CONFIG_CLKBLD_I8253)	+= i8253.o
>  obj-$(CONFIG_CLKSRC_MMIO)	+= mmio.o
>  obj-$(CONFIG_DAVINCI_TIMER)	+= timer-davinci.o
>  obj-$(CONFIG_DIGICOLOR_TIMER)	+= timer-digicolor.o
> +obj-$(CONFIG_ECONET_EN751221_TIMER)	+= timer-econet-en751221.o
>  obj-$(CONFIG_OMAP_DM_TIMER)	+= timer-ti-dm.o
>  obj-$(CONFIG_OMAP_DM_SYSTIMER)	+= timer-ti-dm-systimer.o
>  obj-$(CONFIG_DW_APB_TIMER)	+= dw_apb_timer.o
> diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksource/timer-econet-en751221.c
> new file mode 100644
> index 000000000000..9cfeead09377
> --- /dev/null
> +++ b/drivers/clocksource/timer-econet-en751221.c
> @@ -0,0 +1,216 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Timer present on EcoNet EN75xx MIPS based SoCs.
> + *
> + * Copyright (C) 2025 by Caleb James DeLisle <cjd at cjdns.fr>
> + */
> +
> +#include <linux/io.h>
> +#include <linux/cpumask.h>
> +#include <linux/interrupt.h>
> +#include <linux/clockchips.h>
> +#include <linux/sched_clock.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
> +#include <linux/cpuhotplug.h>
> +#include <linux/clk.h>
> +
> +#define ECONET_BITS			32
> +#define ECONET_MIN_DELTA		0x00001000
> +#define ECONET_MAX_DELTA		GENMASK(ECONET_BITS - 2, 0)
> +/* 34Kc hardware has 1 block and 1004Kc has 2. */
> +#define ECONET_NUM_BLOCKS		DIV_ROUND_UP(NR_CPUS, 2)
> +
> +static struct {
> +	void __iomem	*membase[ECONET_NUM_BLOCKS];
> +	u32		freq_hz;
> +} econet_timer __ro_after_init;
> +
> +static DEFINE_PER_CPU(struct clock_event_device, econet_timer_pcpu);
> +
> +/* Each memory block has 2 timers, the order of registers is:
> + * CTL, CMR0, CNT0, CMR1, CNT1
> + */
> +static inline void __iomem *reg_ctl(u32 timer_n)
> +{
> +	return econet_timer.membase[timer_n >> 1];
> +}
> +
> +static inline void __iomem *reg_compare(u32 timer_n)
> +{
> +	return econet_timer.membase[timer_n >> 1] + (timer_n & 1) * 0x08 + 0x04;
> +}
> +
> +static inline void __iomem *reg_count(u32 timer_n)
> +{
> +	return econet_timer.membase[timer_n >> 1] + (timer_n & 1) * 0x08 + 0x08;
> +}
> +
> +static inline u32 ctl_bit_enabled(u32 timer_n)
> +{
> +	return 1U << (timer_n & 1);
> +}
> +
> +static inline u32 ctl_bit_pending(u32 timer_n)
> +{
> +	return 1U << ((timer_n & 1) + 16);
> +}
> +
> +static bool cevt_is_pending(int cpu_id)
> +{
> +	return ioread32(reg_ctl(cpu_id)) & ctl_bit_pending(cpu_id);
> +}
> +
> +static irqreturn_t cevt_interrupt(int irq, void *dev_id)
> +{
> +	struct clock_event_device *dev = this_cpu_ptr(&econet_timer_pcpu);
> +	int cpu = cpumask_first(dev->cpumask);
> +
> +	if (!cevt_is_pending(cpu)) {
> +		pr_debug("%s IRQ %d on CPU %d is not pending\n", __func__, irq, cpu);
> +		return IRQ_NONE;
> +	}

How this can happen ? Can this interrupt be shared ?

The system will account this as a spurious interrupt, the debug
message is not needed.

> +	iowrite32(ioread32(reg_count(cpu)), reg_compare(cpu));
> +	dev->event_handler(dev);
> +	return IRQ_HANDLED;
> +}
> +
> +static int cevt_set_next_event(ulong delta, struct clock_event_device *dev)
> +{
> +	u32 next;
> +	int cpu;
> +
> +	cpu = cpumask_first(dev->cpumask);
> +	next = ioread32(reg_count(cpu)) + delta;
> +	iowrite32(next, reg_compare(cpu));
> +
> +	if ((s32)(next - ioread32(reg_count(cpu))) < ECONET_MIN_DELTA / 2)
> +		return -ETIME;
> +
> +	return 0;
> +}
> +
> +static int cevt_init_cpu(uint cpu)
> +{
> +	struct clock_event_device *cd = &per_cpu(econet_timer_pcpu, cpu);
> +	u32 reg;
> +
> +	pr_info("%s: Setting up clockevent for CPU %d\n", cd->name, cpu);

That is more debug information

> +	reg = ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu);
> +	iowrite32(reg, reg_ctl(cpu));
> +
> +	enable_percpu_irq(cd->irq, IRQ_TYPE_NONE);
> +
> +	/* Do this last because it synchronously configures the timer */
> +	clockevents_config_and_register(
> +		cd, econet_timer.freq_hz,
> +		ECONET_MIN_DELTA, ECONET_MAX_DELTA);
> +
> +	return 0;
> +}
> +
> +static u64 notrace sched_clock_read(void)
> +{
> +	/* Always read from clock zero no matter the CPU */
> +	return (u64)ioread32(reg_count(0));
> +}
> +
> +/* Init */
> +
> +static void __init cevt_dev_init(uint cpu)
> +{
> +	iowrite32(0, reg_count(cpu));
> +	iowrite32(U32_MAX, reg_compare(cpu));
> +}
> +
> +static int __init cevt_init(struct device_node *np)
> +{
> +	int i, irq, ret;
> +
> +	irq = irq_of_parse_and_map(np, 0);
> +	if (irq <= 0) {
> +		pr_err("%pOFn: irq_of_parse_and_map failed", np);
> +		return -EINVAL;
> +	}
> +
> +	ret = request_percpu_irq(irq, cevt_interrupt, np->name, &econet_timer_pcpu);
> +
> +	if (ret < 0) {
> +		pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, irq, ret);
> +		goto err_unmap_irq;
> +	}
> +
> +	for_each_possible_cpu(i) {
> +		struct clock_event_device *cd = &per_cpu(econet_timer_pcpu, i);
> +
> +		cd->rating		= 310,
> +		cd->features		= CLOCK_EVT_FEAT_ONESHOT |
> +					  CLOCK_EVT_FEAT_C3STOP |
> +					  CLOCK_EVT_FEAT_PERCPU;
> +		cd->set_next_event	= cevt_set_next_event;
> +		cd->irq			= irq;
> +		cd->cpumask		= cpumask_of(i);
> +		cd->name		= np->name;
> +
> +		cevt_dev_init(i);
> +	}
> +
> +	cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING,
> +			  "clockevents/en75/timer:starting",
> +			  cevt_init_cpu, NULL);

cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, ... ) ?

> +	return 0;
> +
> +err_unmap_irq:
> +	irq_dispose_mapping(irq);
> +	return ret;
> +}
> +
> +static int __init timer_init(struct device_node *np)
> +{
> +	int num_blocks = DIV_ROUND_UP(num_possible_cpus(), 2);
> +	struct clk *clk;
> +	int ret;
> +
> +	clk = of_clk_get(np, 0);
> +	if (IS_ERR(clk)) {
> +		pr_err("%pOFn: Failed to get CPU clock from DT %ld\n", np, PTR_ERR(clk));
> +		return PTR_ERR(clk);
> +	}
> +
> +	econet_timer.freq_hz = clk_get_rate(clk);
> +
> +	for (int i = 0; i < num_blocks; i++) {
> +		econet_timer.membase[i] = of_iomap(np, i);
> +		if (!econet_timer.membase[i]) {
> +			pr_err("%pOFn: failed to map register [%d]\n", np, i);
> +			return -ENXIO;
> +		}
> +	}
> +
> +	/* For clocksource purposes always read clock zero, whatever the CPU */
> +	ret = clocksource_mmio_init(reg_count(0), np->name,
> +				    econet_timer.freq_hz, 301, ECONET_BITS,
> +				    clocksource_mmio_readl_up);
> +	if (ret) {
> +		pr_err("%pOFn: clocksource_mmio_init failed: %d", np, ret);
> +		return ret;
> +	}
> +
> +	ret = cevt_init(np);
> +	if (ret < 0)
> +		return ret;
> +
> +	sched_clock_register(sched_clock_read, ECONET_BITS,
> +			     econet_timer.freq_hz);
> +
> +	pr_info("%pOFn: using %u.%03u MHz high precision timer\n", np,
> +		econet_timer.freq_hz / 1000000,
> +		(econet_timer.freq_hz / 1000) % 1000);
> +
> +	return 0;
> +}
> +
> +TIMER_OF_DECLARE(econet_timer_hpt, "econet,en751221-timer", timer_init);
> -- 
> 2.39.5
> 

-- 

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From niks at kernel.org  Mon May  5 10:18:29 2025
From: niks at kernel.org (Niklas Schnelle)
Date: Mon, 05 May 2025 19:18:29 +0200
Subject: [REGRESSION][BISECTED][STABLE] MT7925: mDNS and IPv6 broken in
 kernel 6.14.3 and above
In-Reply-To: <28ef2cc608d071d1530902d7b5df045555ab5651.camel@mediatek.com>
References: <EmWnO5b-acRH1TXbGnkx41eJw654vmCR-8_xMBaPMwexCnfkvKCdlU5u19CGbaapJ3KRu-l3B-tSUhf8CCQwL0odjo6Cd5YG5lvNeB-vfdg=@pm.me>
				 <f73dec60b60dd7bb3be40c1feefbe223c7afe19b.camel@mediatek.com>
				 <5ae1ef34c9844d6d0f5fb167dd596a4c43321367.camel@kernel.org>
			 <28ef2cc608d071d1530902d7b5df045555ab5651.camel@mediatek.com>
Message-ID: <0736898d8d53e6249d5be637c9b7e7c81398218a.camel@kernel.org>

On Mon, 2025-05-05 at 05:48 +0000, Mingyen Hsieh (???) wrote:
> On Sun, 2025-05-04 at 00:39 +0200, Niklas Schnelle wrote:
> > 
> > External email : Please do not click links or open attachments until
> > you have verified the sender or the content.
> > 
> > 
> > On Wed, 2025-04-30 at 06:47 +0000, Mingyen Hsieh (???) wrote:
> > > On Wed, 2025-04-30 at 01:14 +0000, fossben at pm.me?wrote:
> > > > 
> > > > External email : Please do not click links or open attachments
> > > > until
> > > > you have verified the sender or the content.
> > > > 
> > > > 
> > > > Hello all,
> > > > 
> > > > After upgrading to 6.14.3 on my PC with a MT7925 chip, I noticed
> > > > that
> > > > I could no longer ping *.local addresses provided by Avahi. In
> > > > addition, I also noticed that I was not able to get a DHCP IPv6
> > > > address from my router, no matter how many times I rebooted the
> > > > router or reconnected with NetworkManager.
> > > > 
> > > > Reverting to 6.14.2 fixes both mDNS and IPv6 addresses
> > > > immediately.
> > > > Going back to 6.14.3 immediately breaks mDNS again, but the IPv6
> > > > address will stay there for a while before disappearing later,
> > > > possibly because the DHCP lease expired? I am not sure exactly
> > > > when
> > > > it stops working.
> > > > 
> > > > I've done a kernel bisect between 6.14.2 and 6.14.3 and found the
> > > > offending commit that causes mDNS to fail:
> > > > 
> > > > commit 80007d3f92fd018d0a052a706400e976b36e3c87
> > > > Author: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
> > > > Date:?? Tue Mar 4 16:08:50 2025 -0800
> > > > 
> > > > ??? wifi: mt76: mt7925: integrate *mlo_sta_cmd and *sta_cmd
> > > > 
> > > > ??? commit cb1353ef34735ec1e5d9efa1fe966f05ff1dc1e1 upstream.
> > > > 
> > > > ??? Integrate *mlo_sta_cmd and *sta_cmd for the MLO firmware.
> > > > 
> > > > ??? Fixes: 86c051f2c418 ("wifi: mt76: mt7925: enabling MLO when
> > > > the
> > > > firmware supports it")
> > > > 
> > > > ?drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 59 ++++-------
> > > > ----
> > > > --------------------------------------------
> > > > ?1 file changed, 4 insertions(+), 55 deletions(-)
> > > > 
> > > > I do not know if this same commit is also causing the IPv6 issues
> > > > as
> > > > testing that requires quite a bit of time to reproduce. What I do
> > > > know with certainty as of this moment is that it definitely
> > > > breaks in
> > > > kernel 6.14.3.
> > > > 
> > > > I've attached my hardware info as well as dmesg logs from the
> > > > last
> > > > working kernel from the bisect and 6.14.4 which exhibits the
> > > > issue.
> > > > Please let me know if there's any other info you need.
> > > > 
> > > > Thanks!
> > > > Benjamin Xiao
> > > 
> > > Hi,
> > > 
> > > Thanks for reporting this issue, we will aim into this.
> > > 
> > > Can you provide me with your testing steps?
> > > 
> > > Best Regards,
> > > Yen.
> > > 
> > 
> > Hi Yan,
> > 
> > I see the same IPv6 issue on my Framework 13 (Ryzen 5 AI 340) with an
> > mt7925e WiFI module. My setup is just a home router with native IPv6
> > both for my uplink and in the LAN. The problems with IPv6 can already
> > be seen just in the LAN for example by checking which IP was used for
> > SSH, in my setup it should always be IPv6 but falls back to IPv4 in
> > the
> > broken state.
> > 
> > As another data point, I tried reverting cb1353ef3473 ("wifi: mt76:
> > mt7925: integrate *mlo_sta_cmd and *sta_cmd") on top of 6.15.-rc4.
> > This
> > fully restores IPv6 for me. Also note I'm running this with the
> > mt7925
> > firmware version 20250425073330 from linux-firmware's master branch
> > as
> > I had some dropped connections with earlier firmware.
> > 
> > So it definitely looks like that commit also broke IPv6 and not just
> > mDNS. Note that if if I use DHCPv6 instead of router advertisements,
> > on
> > the latest firmware, but without the revert, I get a global IPv6
> > address added to the interface but then native IPv6 addresses are
> > still
> > uncreachable. With the offending patch reverted my SSH session to an
> > IPv6 only host works fine and is stable. Also I'd be willing to test
> > a
> > proper fix as I rely on IPv6 heavily due to having to use CGNAT for
> > IPv4 but not for IPv6.
> > 
> > 
> > Thanks,
> > Niklas
> 
> Hi Benjamin & Niklas,
> 
> Can you help to try this patch? I can get IPv6 address through this
> patch.
> 
> If it can work at your environment as well, i will upstream it and add
> test tag with you.
> 
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> index a42b584634ab..fd756f0d18f8 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> @@ -2183,14 +2183,14 @@ mt7925_mcu_sta_cmd(struct mt76_phy *phy,
>                         mt7925_mcu_sta_mld_tlv(skb, info->vif, info-
> > link_sta->sta);
>                         mt7925_mcu_sta_eht_mld_tlv(skb, info->vif,
> info->link_sta->sta);
>                 }
> -
> -               mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info-
> > link_sta);
>         }
> 
>         if (!info->enable) {
>                 mt7925_mcu_sta_remove_tlv(skb);
>                 mt76_connac_mcu_add_tlv(skb, STA_REC_MLD_OFF,
>                                         sizeof(struct tlv));
> +       } else {
> +               mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info-
> > link_sta);
>         }
> 
>         return mt76_mcu_skb_send_msg(dev, skb, info->cmd, true);
> 
> 
> Thanks~
> Yen.
> 

Hi Yen,

As the patch didn't apply, I edited mt7925_mcu_sta_cmd() manually on
top of v6.15-rc5 according to the diff. With that IPv6 works fine for
me.

If it were me, I'd probably structure the if different. I'd leave
the?mt7925_mcu_sta_hdr_trans_tlv() where it is but have an inner if
(info->link_sta) inside just if (!info->enable), then the !info->enable
case becomes just an else. I'd maybe even put the if (info->link_sta)
body in its own static function if that makes sense semantically, but I
don't know enough (anything) about the driver to know. Anyway, that's
all a matter of taste and actually makes the patch quite a bit larger.

So whichever way you decide on feel free to add:

Tested-by: Niklas Schnelle <niks at kernel.org>

Thanks,
Niklas


From cjd at cjdns.fr  Mon May  5 11:09:47 2025
From: cjd at cjdns.fr (Caleb James DeLisle)
Date: Mon, 5 May 2025 20:09:47 +0200
Subject: [PATCH v4 2/7] clocksource/drivers: Add EcoNet Timer HPT driver
In-Reply-To: <aBjpBpJAIP89oiit@mai.linaro.org>
References: <20250430133433.22222-1-cjd@cjdns.fr>
 <20250430133433.22222-3-cjd@cjdns.fr> <aBjpBpJAIP89oiit@mai.linaro.org>
Message-ID: <92cd3689-3409-4d43-8db1-8633d35f779a@cjdns.fr>


On 05/05/2025 18:36, Daniel Lezcano wrote:
> On Wed, Apr 30, 2025 at 01:34:28PM +0000, Caleb James DeLisle wrote:
>> Introduce a clocksource driver for the so-called high-precision timer (HPT)
>> in the EcoNet EN751221 MIPS SoC.
> As a new driver, please document the timer (up - down ?, SPI/PPI, etc
> ...) that will help to understand the code more easily, especially the
> reg_* functions (purposes?).


Sure thing, I can elaborate the comment in the header of
timer-econet-en751221.c. Let me know if you'd like it described
somewhere else as well, such as the help of config ECONET_EN751221_TIMER.


>
>> Signed-off-by: Caleb James DeLisle <cjd at cjdns.fr>
>> ---
>>   drivers/clocksource/Kconfig                 |   8 +
>>   drivers/clocksource/Makefile                |   1 +
>>   drivers/clocksource/timer-econet-en751221.c | 216 ++++++++++++++++++++
>>   3 files changed, 225 insertions(+)
>>   create mode 100644 drivers/clocksource/timer-econet-en751221.c
>>
>> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
>> index 487c85259967..976afb0b2312 100644
>> --- a/drivers/clocksource/Kconfig
>> +++ b/drivers/clocksource/Kconfig
>> @@ -73,6 +73,14 @@ config DW_APB_TIMER_OF
>>   	select DW_APB_TIMER
>>   	select TIMER_OF
>>   
>> +config ECONET_EN751221_TIMER
>> +	bool "EcoNet EN751221 High Precision Timer" if COMPILE_TEST
>> +	depends on HAS_IOMEM
>> +	select CLKSRC_MMIO
>> +	select TIMER_OF
>> +	help
>> +	  Support for CPU timer found on EcoNet MIPS based SoCs.
>> +
>>   config FTTMR010_TIMER
>>   	bool "Faraday Technology timer driver" if COMPILE_TEST
>>   	depends on HAS_IOMEM
>> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
>> index 43ef16a4efa6..d2998601eda5 100644
>> --- a/drivers/clocksource/Makefile
>> +++ b/drivers/clocksource/Makefile
>> @@ -17,6 +17,7 @@ obj-$(CONFIG_CLKBLD_I8253)	+= i8253.o
>>   obj-$(CONFIG_CLKSRC_MMIO)	+= mmio.o
>>   obj-$(CONFIG_DAVINCI_TIMER)	+= timer-davinci.o
>>   obj-$(CONFIG_DIGICOLOR_TIMER)	+= timer-digicolor.o
>> +obj-$(CONFIG_ECONET_EN751221_TIMER)	+= timer-econet-en751221.o
>>   obj-$(CONFIG_OMAP_DM_TIMER)	+= timer-ti-dm.o
>>   obj-$(CONFIG_OMAP_DM_SYSTIMER)	+= timer-ti-dm-systimer.o
>>   obj-$(CONFIG_DW_APB_TIMER)	+= dw_apb_timer.o
>> diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksource/timer-econet-en751221.c
>> new file mode 100644
>> index 000000000000..9cfeead09377
>> --- /dev/null
>> +++ b/drivers/clocksource/timer-econet-en751221.c
>> @@ -0,0 +1,216 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Timer present on EcoNet EN75xx MIPS based SoCs.
>> + *
>> + * Copyright (C) 2025 by Caleb James DeLisle <cjd at cjdns.fr>
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/cpumask.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/clockchips.h>
>> +#include <linux/sched_clock.h>
>> +#include <linux/of.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/of_address.h>
>> +#include <linux/cpuhotplug.h>
>> +#include <linux/clk.h>
>> +
>> +#define ECONET_BITS			32
>> +#define ECONET_MIN_DELTA		0x00001000
>> +#define ECONET_MAX_DELTA		GENMASK(ECONET_BITS - 2, 0)
>> +/* 34Kc hardware has 1 block and 1004Kc has 2. */
>> +#define ECONET_NUM_BLOCKS		DIV_ROUND_UP(NR_CPUS, 2)
>> +
>> +static struct {
>> +	void __iomem	*membase[ECONET_NUM_BLOCKS];
>> +	u32		freq_hz;
>> +} econet_timer __ro_after_init;
>> +
>> +static DEFINE_PER_CPU(struct clock_event_device, econet_timer_pcpu);
>> +
>> +/* Each memory block has 2 timers, the order of registers is:
>> + * CTL, CMR0, CNT0, CMR1, CNT1
>> + */
>> +static inline void __iomem *reg_ctl(u32 timer_n)
>> +{
>> +	return econet_timer.membase[timer_n >> 1];
>> +}
>> +
>> +static inline void __iomem *reg_compare(u32 timer_n)
>> +{
>> +	return econet_timer.membase[timer_n >> 1] + (timer_n & 1) * 0x08 + 0x04;
>> +}
>> +
>> +static inline void __iomem *reg_count(u32 timer_n)
>> +{
>> +	return econet_timer.membase[timer_n >> 1] + (timer_n & 1) * 0x08 + 0x08;
>> +}
>> +
>> +static inline u32 ctl_bit_enabled(u32 timer_n)
>> +{
>> +	return 1U << (timer_n & 1);
>> +}
>> +
>> +static inline u32 ctl_bit_pending(u32 timer_n)
>> +{
>> +	return 1U << ((timer_n & 1) + 16);
>> +}
>> +
>> +static bool cevt_is_pending(int cpu_id)
>> +{
>> +	return ioread32(reg_ctl(cpu_id)) & ctl_bit_pending(cpu_id);
>> +}
>> +
>> +static irqreturn_t cevt_interrupt(int irq, void *dev_id)
>> +{
>> +	struct clock_event_device *dev = this_cpu_ptr(&econet_timer_pcpu);
>> +	int cpu = cpumask_first(dev->cpumask);
>> +
>> +	if (!cevt_is_pending(cpu)) {
>> +		pr_debug("%s IRQ %d on CPU %d is not pending\n", __func__, irq, cpu);
>> +		return IRQ_NONE;
>> +	}
> How this can happen ? Can this interrupt be shared ?
To my knowledge it can't, but vendor code does it and I wasn't feeling
bold enough to gamble.
> The system will account this as a spurious interrupt, the debug
> message is not needed.
Good point, will remove.
>
>> +	iowrite32(ioread32(reg_count(cpu)), reg_compare(cpu));
>> +	dev->event_handler(dev);
>> +	return IRQ_HANDLED;
>> +}
>> +
>> +static int cevt_set_next_event(ulong delta, struct clock_event_device *dev)
>> +{
>> +	u32 next;
>> +	int cpu;
>> +
>> +	cpu = cpumask_first(dev->cpumask);
>> +	next = ioread32(reg_count(cpu)) + delta;
>> +	iowrite32(next, reg_compare(cpu));
>> +
>> +	if ((s32)(next - ioread32(reg_count(cpu))) < ECONET_MIN_DELTA / 2)
>> +		return -ETIME;
>> +
>> +	return 0;
>> +}
>> +
>> +static int cevt_init_cpu(uint cpu)
>> +{
>> +	struct clock_event_device *cd = &per_cpu(econet_timer_pcpu, cpu);
>> +	u32 reg;
>> +
>> +	pr_info("%s: Setting up clockevent for CPU %d\n", cd->name, cpu);
> That is more debug information
Fair enough, will change.
>> +	reg = ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu);
>> +	iowrite32(reg, reg_ctl(cpu));
>> +
>> +	enable_percpu_irq(cd->irq, IRQ_TYPE_NONE);
>> +
>> +	/* Do this last because it synchronously configures the timer */
>> +	clockevents_config_and_register(
>> +		cd, econet_timer.freq_hz,
>> +		ECONET_MIN_DELTA, ECONET_MAX_DELTA);
>> +
>> +	return 0;
>> +}
>> +
>> +static u64 notrace sched_clock_read(void)
>> +{
>> +	/* Always read from clock zero no matter the CPU */
>> +	return (u64)ioread32(reg_count(0));
>> +}
>> +
>> +/* Init */
>> +
>> +static void __init cevt_dev_init(uint cpu)
>> +{
>> +	iowrite32(0, reg_count(cpu));
>> +	iowrite32(U32_MAX, reg_compare(cpu));
>> +}
>> +
>> +static int __init cevt_init(struct device_node *np)
>> +{
>> +	int i, irq, ret;
>> +
>> +	irq = irq_of_parse_and_map(np, 0);
>> +	if (irq <= 0) {
>> +		pr_err("%pOFn: irq_of_parse_and_map failed", np);
>> +		return -EINVAL;
>> +	}
>> +
>> +	ret = request_percpu_irq(irq, cevt_interrupt, np->name, &econet_timer_pcpu);
>> +
>> +	if (ret < 0) {
>> +		pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, irq, ret);
>> +		goto err_unmap_irq;
>> +	}
>> +
>> +	for_each_possible_cpu(i) {
>> +		struct clock_event_device *cd = &per_cpu(econet_timer_pcpu, i);
>> +
>> +		cd->rating		= 310,
>> +		cd->features		= CLOCK_EVT_FEAT_ONESHOT |
>> +					  CLOCK_EVT_FEAT_C3STOP |
>> +					  CLOCK_EVT_FEAT_PERCPU;
>> +		cd->set_next_event	= cevt_set_next_event;
>> +		cd->irq			= irq;
>> +		cd->cpumask		= cpumask_of(i);
>> +		cd->name		= np->name;
>> +
>> +		cevt_dev_init(i);
>> +	}
>> +
>> +	cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING,
>> +			  "clockevents/en75/timer:starting",
>> +			  cevt_init_cpu, NULL);
> cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, ... ) ?

I see that Ingenic does this. This is the only timer so until it's up,
sleeping causes a hang. If sleeping is prior to CPUHP_AP_ONLINE_DYN is
considered a bug then this should be okay, but I'm not informed enough
to say whether that is the case so I'll follow your guidance here.


Thanks,

Caleb


>
>> +	return 0;
>> +
>> +err_unmap_irq:
>> +	irq_dispose_mapping(irq);
>> +	return ret;
>> +}
>> +
>> +static int __init timer_init(struct device_node *np)
>> +{
>> +	int num_blocks = DIV_ROUND_UP(num_possible_cpus(), 2);
>> +	struct clk *clk;
>> +	int ret;
>> +
>> +	clk = of_clk_get(np, 0);
>> +	if (IS_ERR(clk)) {
>> +		pr_err("%pOFn: Failed to get CPU clock from DT %ld\n", np, PTR_ERR(clk));
>> +		return PTR_ERR(clk);
>> +	}
>> +
>> +	econet_timer.freq_hz = clk_get_rate(clk);
>> +
>> +	for (int i = 0; i < num_blocks; i++) {
>> +		econet_timer.membase[i] = of_iomap(np, i);
>> +		if (!econet_timer.membase[i]) {
>> +			pr_err("%pOFn: failed to map register [%d]\n", np, i);
>> +			return -ENXIO;
>> +		}
>> +	}
>> +
>> +	/* For clocksource purposes always read clock zero, whatever the CPU */
>> +	ret = clocksource_mmio_init(reg_count(0), np->name,
>> +				    econet_timer.freq_hz, 301, ECONET_BITS,
>> +				    clocksource_mmio_readl_up);
>> +	if (ret) {
>> +		pr_err("%pOFn: clocksource_mmio_init failed: %d", np, ret);
>> +		return ret;
>> +	}
>> +
>> +	ret = cevt_init(np);
>> +	if (ret < 0)
>> +		return ret;
>> +
>> +	sched_clock_register(sched_clock_read, ECONET_BITS,
>> +			     econet_timer.freq_hz);
>> +
>> +	pr_info("%pOFn: using %u.%03u MHz high precision timer\n", np,
>> +		econet_timer.freq_hz / 1000000,
>> +		(econet_timer.freq_hz / 1000) % 1000);
>> +
>> +	return 0;
>> +}
>> +
>> +TIMER_OF_DECLARE(econet_timer_hpt, "econet,en751221-timer", timer_init);
>> -- 
>> 2.39.5
>>


From robh at kernel.org  Mon May  5 11:43:43 2025
From: robh at kernel.org (Rob Herring)
Date: Mon, 5 May 2025 13:43:43 -0500
Subject: [PATCH v2 11/17] arm64: dts: amlogic: Drop redundant CPU "clock-latency"
In-Reply-To: <20250410-dt-cpu-schema-v2-11-63d7dc9ddd0a@kernel.org>
References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org> <20250410-dt-cpu-schema-v2-11-63d7dc9ddd0a@kernel.org>
Message-ID: <CAL_JsqLGHQ4YBqGGEdyirtgaBnJKRxOxOKTaQLv2jm-g8TNndA@mail.gmail.com>

On Thu, Apr 10, 2025 at 10:50?AM Rob Herring (Arm) <robh at kernel.org> wrote:
>
> The "clock-latency" property is part of the deprecated opp-v1 binding
> and is redundant if the opp-v2 table has equal or larger values in any
> "clock-latency-ns". Add any missing "clock-latency-ns" properties and
> remove "clock-latency".
>
> Signed-off-by: Rob Herring (Arm) <robh at kernel.org>
> Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>
> ---

Ping!

>  arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts             | 4 ----
>  arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts         | 4 ----
>  arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts             | 4 ----
>  arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts               | 4 ----
>  arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts            | 4 ----
>  arch/arm64/boot/dts/amlogic/meson-g12a.dtsi                   | 1 +
>  arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts | 6 ------
>  arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi             | 2 ++
>  arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi      | 6 ------
>  arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi          | 6 ------
>  arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi       | 6 ------
>  arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts    | 6 ------
>  arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi            | 6 ------
>  arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts        | 6 ------
>  arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi             | 2 ++
>  arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi              | 6 ------
>  arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi              | 4 ----
>  arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi           | 4 ----
>  arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts        | 4 ----
>  arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi             | 4 ----
>  arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts | 4 ----
>  arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts              | 4 ----
>  arch/arm64/boot/dts/amlogic/meson-sm1.dtsi                    | 1 +
>  23 files changed, 6 insertions(+), 92 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts
> index 9aa36f17ffa2..d0a3b4b9229c 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts
> @@ -267,28 +267,24 @@ &cpu0 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu2 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu3 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &ethmac {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
> index 952b8d02e5c2..4353485c6f26 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
> @@ -220,28 +220,24 @@ &cpu0 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu2 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu3 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cvbs_vdac_port {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
> index 52fbc5103e45..f39fcabc763f 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
> @@ -314,28 +314,24 @@ &cpu0 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu2 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu3 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cvbs_vdac_port {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> index 5407049d2647..b5bf8ecc91e6 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> @@ -407,28 +407,24 @@ &cpu0 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu2 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu3 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &clkc_audio {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
> index 01da83658ae3..5ab460a3e637 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
> @@ -263,28 +263,24 @@ &cpu0 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu2 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu3 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cvbs_vdac_port {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> index 543e70669df5..deee61dbe074 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> @@ -62,6 +62,7 @@ cpu_opp_table: opp-table {
>                 opp-1000000000 {
>                         opp-hz = /bits/ 64 <1000000000>;
>                         opp-microvolt = <731000>;
> +                       clock-latency-ns = <50000>;
>                 };
>
>                 opp-1200000000 {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts
> index adedc1340c78..415248931ab1 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts
> @@ -76,42 +76,36 @@ &cpu0 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu100 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu101 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu102 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu103 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &pwm_ab {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi
> index 8e9ad1e51d66..8ecb5bd125c1 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi
> @@ -14,6 +14,7 @@ cpu_opp_table_0: opp-table-0 {
>                 opp-1000000000 {
>                         opp-hz = /bits/ 64 <1000000000>;
>                         opp-microvolt = <761000>;
> +                       clock-latency-ns = <50000>;
>                 };
>
>                 opp-1200000000 {
> @@ -54,6 +55,7 @@ cpub_opp_table_1: opp-table-1 {
>                 opp-1000000000 {
>                         opp-hz = /bits/ 64 <1000000000>;
>                         opp-microvolt = <731000>;
> +                       clock-latency-ns = <50000>;
>                 };
>
>                 opp-1200000000 {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi
> index 92e8b26ecccc..39011b645128 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi
> @@ -155,42 +155,36 @@ &cpu0 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu100 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu101 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu102 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu103 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &ext_mdio {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi
> index 54663c55a20e..1b08303c4282 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi
> @@ -263,42 +263,36 @@ &cpu0 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu100 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu101 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu102 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu103 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &ethmac {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
> index 48650bad230d..fc737499f207 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
> @@ -51,42 +51,36 @@ &cpu0 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu100 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu101 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu102 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu103 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &pwm_ab {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts
> index e21831dfceee..d5938a4a6da3 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts
> @@ -281,42 +281,36 @@ &cpu0 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu100 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu101 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu102 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu103 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  /* RK817 only supports 12.5mV steps, round up the values */
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi
> index 7e8964bacfce..3298d59833b6 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi
> @@ -227,42 +227,36 @@ &cpu0 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu100 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu101 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu102 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu103 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu_thermal {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts
> index fc05ecf90714..1e5c6f984945 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts
> @@ -259,42 +259,36 @@ &cpu0 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu100 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu101 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu102 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu103 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu_thermal {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi
> index 44c23c984034..19cad93a6889 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi
> @@ -14,6 +14,7 @@ cpu_opp_table_0: opp-table-0 {
>                 opp-1000000000 {
>                         opp-hz = /bits/ 64 <1000000000>;
>                         opp-microvolt = <731000>;
> +                       clock-latency-ns = <50000>;
>                 };
>
>                 opp-1200000000 {
> @@ -59,6 +60,7 @@ cpub_opp_table_1: opp-table-1 {
>                 opp-1000000000 {
>                         opp-hz = /bits/ 64 <1000000000>;
>                         opp-microvolt = <771000>;
> +                       clock-latency-ns = <50000>;
>                 };
>
>                 opp-1200000000 {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
> index a7a0fc264cdc..9b6d780eada7 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
> @@ -213,42 +213,36 @@ &cpu0 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table_0>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu100 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu101 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu102 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu103 {
>         cpu-supply = <&vddcpu_a>;
>         operating-points-v2 = <&cpub_opp_table_1>;
>         clocks = <&clkc CLKID_CPUB_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cvbs_vdac_port {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi
> index a3463149db3d..9be3084b090d 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi
> @@ -147,28 +147,24 @@ &cpu0 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU1_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu2 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU2_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu3 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU3_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cvbs_vdac_port {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
> index 40db95f64636..538b35036954 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
> @@ -185,28 +185,24 @@ &cpu0 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU1_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu2 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU2_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu3 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU3_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &ext_mdio {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
> index 5d75ad3f3e46..a3d9b66b6878 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
> @@ -51,28 +51,24 @@ &cpu0 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU1_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu2 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU2_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu3 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU3_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &pwm_AO_cd {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
> index ad8d07883760..c4524eb4f099 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
> @@ -250,28 +250,24 @@ &cpu0 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU1_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu2 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU2_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu3 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU3_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &ext_mdio {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts
> index 537370db360f..5daadfb170b4 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts
> @@ -64,26 +64,22 @@ &cpu0 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU1_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu2 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU2_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu3 {
>         cpu-supply = <&vddcpu_b>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU3_CLK>;
> -       clock-latency = <50000>;
>  };
> diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
> index 37d7f64b6d5d..024d2eb8e6ee 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
> @@ -359,28 +359,24 @@ &cpu0 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu1 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU1_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu2 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU2_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &cpu3 {
>         cpu-supply = <&vddcpu>;
>         operating-points-v2 = <&cpu_opp_table>;
>         clocks = <&clkc CLKID_CPU3_CLK>;
> -       clock-latency = <50000>;
>  };
>
>  &ethmac {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
> index 97e4b52066dc..966ebb19cc55 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
> @@ -100,6 +100,7 @@ cpu_opp_table: opp-table {
>                 opp-1000000000 {
>                         opp-hz = /bits/ 64 <1000000000>;
>                         opp-microvolt = <770000>;
> +                       clock-latency-ns = <50000>;
>                 };
>
>                 opp-1200000000 {
>
> --
> 2.47.2
>
>


From robh at kernel.org  Mon May  5 11:50:37 2025
From: robh at kernel.org (Rob Herring)
Date: Mon, 5 May 2025 13:50:37 -0500
Subject: [PATCH v2 11/17] arm64: dts: amlogic: Drop redundant CPU "clock-latency"
In-Reply-To: <CAL_JsqLGHQ4YBqGGEdyirtgaBnJKRxOxOKTaQLv2jm-g8TNndA@mail.gmail.com>
References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org>
 <20250410-dt-cpu-schema-v2-11-63d7dc9ddd0a@kernel.org> <CAL_JsqLGHQ4YBqGGEdyirtgaBnJKRxOxOKTaQLv2jm-g8TNndA@mail.gmail.com>
Message-ID: <CAL_JsqKr8784O_-p6=EUqTxkVe1JkS8O+KWEfpVoWvy5NYC8DA@mail.gmail.com>

On Mon, May 5, 2025 at 1:43?PM Rob Herring <robh at kernel.org> wrote:
>
> On Thu, Apr 10, 2025 at 10:50?AM Rob Herring (Arm) <robh at kernel.org> wrote:
> >
> > The "clock-latency" property is part of the deprecated opp-v1 binding
> > and is redundant if the opp-v2 table has equal or larger values in any
> > "clock-latency-ns". Add any missing "clock-latency-ns" properties and
> > remove "clock-latency".
> >
> > Signed-off-by: Rob Herring (Arm) <robh at kernel.org>
> > Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>
> > ---
>
> Ping!

NM, I see it now in linux-next.


From robh at kernel.org  Mon May  5 11:54:30 2025
From: robh at kernel.org (Rob Herring)
Date: Mon, 5 May 2025 13:54:30 -0500
Subject: [PATCH] arm/arm64: dts: mediatek: Add missing "#sound-dai-cells"
 to linux,bt-sco
In-Reply-To: <20250409205001.1522009-1-robh@kernel.org>
References: <20250409205001.1522009-1-robh@kernel.org>
Message-ID: <CAL_JsqJ4whU81jRLD+N+oiKD-VMSYbrQnSCs-6GfUsk+MNJfpw@mail.gmail.com>

On Wed, Apr 9, 2025 at 3:50?PM Rob Herring (Arm) <robh at kernel.org> wrote:
>
> Add missing "#sound-dai-cells" which is required by the linux,bt-sco
> binding.
>
> Signed-off-by: Rob Herring (Arm) <robh at kernel.org>
> ---
>  arch/arm/boot/dts/mediatek/mt2701-evb.dts      | 1 +
>  arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 +
>  2 files changed, 2 insertions(+)

Ping.

> diff --git a/arch/arm/boot/dts/mediatek/mt2701-evb.dts b/arch/arm/boot/dts/mediatek/mt2701-evb.dts
> index 4c76366aa938..e97dc37f716c 100644
> --- a/arch/arm/boot/dts/mediatek/mt2701-evb.dts
> +++ b/arch/arm/boot/dts/mediatek/mt2701-evb.dts
> @@ -50,6 +50,7 @@ sound:sound {
>
>         bt_sco_codec:bt_sco_codec {
>                 compatible = "linux,bt-sco";
> +               #sound-dai-cells = <0>;
>         };
>
>         backlight_lcd: backlight_lcd {
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> index e1495f1900a7..9f53344fa83e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> @@ -105,6 +105,7 @@ sound: mt8183-sound {
>
>         btsco: bt-sco {
>                 compatible = "linux,bt-sco";
> +               #sound-dai-cells = <0>;
>         };
>
>         wifi_pwrseq: wifi-pwrseq {
> --
> 2.47.2
>


From sashal at kernel.org  Mon May  5 15:04:17 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:04:17 -0400
Subject: [PATCH AUTOSEL 6.14 041/642] thermal/drivers/mediatek/lvts: Start sensor interrupts disabled
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-41-sashal@kernel.org>

From: N?colas F. R. A. Prado <nfraprado at collabora.com>

[ Upstream commit 2738fb3ec6838a10d2c4ce65cefdb3b90b11bd61 ]

Interrupts are enabled per sensor in lvts_update_irq_mask() as needed,
there's no point in enabling all of them during initialization. Change
the MONINT register initial value so all sensor interrupts start
disabled.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
Link: https://lore.kernel.org/r/20250113-mt8192-lvts-filtered-suspend-fix-v2-4-07a25200c7c6 at collabora.com
Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/thermal/mediatek/lvts_thermal.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index 0aaa44b734ca4..d0901d8ac85da 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -65,7 +65,6 @@
 #define LVTS_HW_FILTER				0x0
 #define LVTS_TSSEL_CONF				0x13121110
 #define LVTS_CALSCALE_CONF			0x300
-#define LVTS_MONINT_CONF			0x0300318C
 
 #define LVTS_MONINT_OFFSET_SENSOR0		0xC
 #define LVTS_MONINT_OFFSET_SENSOR1		0x180
@@ -929,7 +928,7 @@ static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl)
 	 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS
 	 * register, except we set the bits to enable the interrupt.
 	 */
-	writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base));
+	writel(0, LVTS_MONINT(lvts_ctrl->base));
 
 	return 0;
 }
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:04:19 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:04:19 -0400
Subject: [PATCH AUTOSEL 6.14 043/642] Bluetooth: btmtksdio: Prevent enabling interrupts after IRQ handler removal
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-43-sashal@kernel.org>

From: Sean Wang <sean.wang at mediatek.com>

[ Upstream commit 6ac4233afb9a389a7629b7f812395d1d1eca5a83 ]

Ensure interrupts are not re-enabled when the IRQ handler has already been
removed. This prevents unexpected IRQ handler execution due to stale or
unhandled interrupts.

Modify btmtksdio_txrx_work to check if bdev->func->irq_handler exists
before calling sdio_writel to enable interrupts.

Co-developed-by: Pedro Tsai <pedro.tsai at mediatek.com>
Signed-off-by: Pedro Tsai <pedro.tsai at mediatek.com>
Co-developed-by: Felix Freimann <felix.freimann at mediatek.com>
Signed-off-by: Felix Freimann <felix.freimann at mediatek.com>
Signed-off-by: Sean Wang <sean.wang at mediatek.com>
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz at intel.com>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/bluetooth/btmtksdio.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/bluetooth/btmtksdio.c b/drivers/bluetooth/btmtksdio.c
index bd5464bde174f..edd5eead1e93b 100644
--- a/drivers/bluetooth/btmtksdio.c
+++ b/drivers/bluetooth/btmtksdio.c
@@ -610,7 +610,8 @@ static void btmtksdio_txrx_work(struct work_struct *work)
 	} while (int_status || time_is_before_jiffies(txrx_timeout));
 
 	/* Enable interrupt */
-	sdio_writel(bdev->func, C_INT_EN_SET, MTK_REG_CHLPCR, NULL);
+	if (bdev->func->irq_handler)
+		sdio_writel(bdev->func, C_INT_EN_SET, MTK_REG_CHLPCR, NULL);
 
 	sdio_release_host(bdev->func);
 
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:04:20 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:04:20 -0400
Subject: [PATCH AUTOSEL 6.14 044/642] Bluetooth: btmtk: Remove the resetting step before downloading the fw
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-44-sashal@kernel.org>

From: Hao Qin <hao.qin at mediatek.com>

[ Upstream commit 33634e2ab7c6369391e0ca4b9b97dc861e33d20e ]

Remove the resetting step before downloading the fw, as it may cause
other usb devices to fail to initialise when connected during boot
on kernels 6.11 and newer.

Signed-off-by: Hao Qin <hao.qin at mediatek.com>
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz at intel.com>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/bluetooth/btmtk.c | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/drivers/bluetooth/btmtk.c b/drivers/bluetooth/btmtk.c
index 68846c5bd4f79..4390fd571dbd1 100644
--- a/drivers/bluetooth/btmtk.c
+++ b/drivers/bluetooth/btmtk.c
@@ -1330,13 +1330,6 @@ int btmtk_usb_setup(struct hci_dev *hdev)
 		break;
 	case 0x7922:
 	case 0x7925:
-		/* Reset the device to ensure it's in the initial state before
-		 * downloading the firmware to ensure.
-		 */
-
-		if (!test_bit(BTMTK_FIRMWARE_LOADED, &btmtk_data->flags))
-			btmtk_usb_subsys_reset(hdev, dev_id);
-		fallthrough;
 	case 0x7961:
 		btmtk_fw_get_filename(fw_bin_name, sizeof(fw_bin_name), dev_id,
 				      fw_version, fw_flavor);
@@ -1345,12 +1338,9 @@ int btmtk_usb_setup(struct hci_dev *hdev)
 						btmtk_usb_hci_wmt_sync);
 		if (err < 0) {
 			bt_dev_err(hdev, "Failed to set up firmware (%d)", err);
-			clear_bit(BTMTK_FIRMWARE_LOADED, &btmtk_data->flags);
 			return err;
 		}
 
-		set_bit(BTMTK_FIRMWARE_LOADED, &btmtk_data->flags);
-
 		/* It's Device EndPoint Reset Option Register */
 		err = btmtk_usb_uhw_reg_write(hdev, MTK_EP_RST_OPT,
 					      MTK_EP_RST_IN_OUT_OPT);
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:04:48 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:04:48 -0400
Subject: [PATCH AUTOSEL 6.14 072/642] wifi: mt76: Check link_conf pointer in mt76_connac_mcu_sta_basic_tlv()
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-72-sashal@kernel.org>

From: Shayne Chen <shayne.chen at mediatek.com>

[ Upstream commit 9890624c1b3948c1c7f1d0e19ef0bb7680b8c80d ]

This is a preliminary patch to introduce MLO support for MT7996 driver.

Signed-off-by: Shayne Chen <shayne.chen at mediatek.com>
Link: https://patch.msgid.link/20250311-mt7996-mlo-v2-10-31df6972519b at kernel.org
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c b/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c
index d0e49d68c5dbf..bafcf5a279e23 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c
@@ -391,7 +391,7 @@ void mt76_connac_mcu_sta_basic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
 		basic->conn_type = cpu_to_le32(CONNECTION_INFRA_BC);
 
 		if (vif->type == NL80211_IFTYPE_STATION &&
-		    !is_zero_ether_addr(link_conf->bssid)) {
+		    link_conf && !is_zero_ether_addr(link_conf->bssid)) {
 			memcpy(basic->peer_addr, link_conf->bssid, ETH_ALEN);
 			basic->aid = cpu_to_le16(vif->cfg.aid);
 		} else {
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:04:50 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:04:50 -0400
Subject: [PATCH AUTOSEL 6.14 074/642] wifi: mt76: mt7996: implement driver specific get_txpower function
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-74-sashal@kernel.org>

From: Felix Fietkau <nbd at nbd.name>

[ Upstream commit 86db2c5d4ed390b97a5b455a97e2cd9c4f3eff2b ]

Fixes reporting tx power for vifs that don't have a channel context
assigned. Report the tx power of a phy that is covered by the vif's
radio mask.

Link: https://patch.msgid.link/20250311103646.43346-7-nbd at nbd.name
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 .../net/wireless/mediatek/mt76/mt7996/main.c  | 29 ++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/main.c b/drivers/net/wireless/mediatek/mt76/mt7996/main.c
index 69dd565d83190..980a059b3b38f 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/main.c
@@ -601,6 +601,33 @@ static void mt7996_configure_filter(struct ieee80211_hw *hw,
 	mutex_unlock(&dev->mt76.mutex);
 }
 
+static int
+mt7996_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
+		   unsigned int link_id, int *dbm)
+{
+	struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv;
+	struct mt7996_phy *phy = mt7996_vif_link_phy(&mvif->deflink);
+	struct mt7996_dev *dev = mt7996_hw_dev(hw);
+	struct wireless_dev *wdev;
+	int n_chains, delta, i;
+
+	if (!phy) {
+		wdev = ieee80211_vif_to_wdev(vif);
+		for (i = 0; i < hw->wiphy->n_radio; i++)
+			if (wdev->radio_mask & BIT(i))
+				phy = dev->radio_phy[i];
+
+		if (!phy)
+			return -EINVAL;
+	}
+
+	n_chains = hweight16(phy->mt76->chainmask);
+	delta = mt76_tx_power_nss_delta(n_chains);
+	*dbm = DIV_ROUND_UP(phy->mt76->txpower_cur + delta, 2);
+
+	return 0;
+}
+
 static u8
 mt7996_get_rates_table(struct mt7996_phy *phy, struct ieee80211_bss_conf *conf,
 		       bool beacon, bool mcast)
@@ -1650,7 +1677,7 @@ const struct ieee80211_ops mt7996_ops = {
 	.remain_on_channel = mt76_remain_on_channel,
 	.cancel_remain_on_channel = mt76_cancel_remain_on_channel,
 	.release_buffered_frames = mt76_release_buffered_frames,
-	.get_txpower = mt76_get_txpower,
+	.get_txpower = mt7996_get_txpower,
 	.channel_switch_beacon = mt7996_channel_switch_beacon,
 	.get_stats = mt7996_get_stats,
 	.get_et_sset_count = mt7996_get_et_sset_count,
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:04:49 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:04:49 -0400
Subject: [PATCH AUTOSEL 6.14 073/642] wifi: mt76: scan: fix setting tx_info fields
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-73-sashal@kernel.org>

From: Felix Fietkau <nbd at nbd.name>

[ Upstream commit 5b5f1ca9ce73ab6c35e5cd3348f8432ba190d7f4 ]

ieee80211_tx_prepare_skb initializes the skb cb, so fields need to be set
afterwards.

Link: https://patch.msgid.link/20250311103646.43346-8-nbd at nbd.name
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/mediatek/mt76/scan.c | 21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/scan.c b/drivers/net/wireless/mediatek/mt76/scan.c
index 1c4f9deaaada5..9b20ccbeb8cf1 100644
--- a/drivers/net/wireless/mediatek/mt76/scan.c
+++ b/drivers/net/wireless/mediatek/mt76/scan.c
@@ -52,11 +52,6 @@ mt76_scan_send_probe(struct mt76_dev *dev, struct cfg80211_ssid *ssid)
 		ether_addr_copy(hdr->addr3, req->bssid);
 	}
 
-	info = IEEE80211_SKB_CB(skb);
-	if (req->no_cck)
-		info->flags |= IEEE80211_TX_CTL_NO_CCK_RATE;
-	info->control.flags |= IEEE80211_TX_CTRL_DONT_USE_RATE_MASK;
-
 	if (req->ie_len)
 		skb_put_data(skb, req->ie, req->ie_len);
 
@@ -64,10 +59,20 @@ mt76_scan_send_probe(struct mt76_dev *dev, struct cfg80211_ssid *ssid)
 	skb_set_queue_mapping(skb, IEEE80211_AC_VO);
 
 	rcu_read_lock();
-	if (ieee80211_tx_prepare_skb(phy->hw, vif, skb, band, NULL))
-		mt76_tx(phy, NULL, mvif->wcid, skb);
-	else
+
+	if (!ieee80211_tx_prepare_skb(phy->hw, vif, skb, band, NULL)) {
 		ieee80211_free_txskb(phy->hw, skb);
+		goto out;
+	}
+
+	info = IEEE80211_SKB_CB(skb);
+	if (req->no_cck)
+		info->flags |= IEEE80211_TX_CTL_NO_CCK_RATE;
+	info->control.flags |= IEEE80211_TX_CTRL_DONT_USE_RATE_MASK;
+
+	mt76_tx(phy, NULL, mvif->wcid, skb);
+
+out:
 	rcu_read_unlock();
 }
 
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:04:51 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:04:51 -0400
Subject: [PATCH AUTOSEL 6.14 075/642] wifi: mt76: only mark tx-status-failed frames as ACKed on mt76x0/2
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-75-sashal@kernel.org>

From: Felix Fietkau <nbd at nbd.name>

[ Upstream commit 0c5a89ceddc1728a40cb3313948401dd70e3c649 ]

The interrupt status polling is unreliable, which can cause status events
to get lost. On all newer chips, txs-timeout is an indication that the
packet was either never sent, or never acked.
Fixes issues with inactivity polling.

Link: https://patch.msgid.link/20250311103646.43346-6-nbd at nbd.name
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/mediatek/mt76/mt76.h       | 1 +
 drivers/net/wireless/mediatek/mt76/mt76x0/pci.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/mt76x2/pci.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/mt76x2/usb.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/tx.c         | 3 ++-
 6 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt76.h b/drivers/net/wireless/mediatek/mt76/mt76.h
index 05651efb549ec..8714418f3906c 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76.h
@@ -491,6 +491,7 @@ struct mt76_hw_cap {
 #define MT_DRV_RX_DMA_HDR		BIT(3)
 #define MT_DRV_HW_MGMT_TXQ		BIT(4)
 #define MT_DRV_AMSDU_OFFLOAD		BIT(5)
+#define MT_DRV_IGNORE_TXS_FAILED	BIT(6)
 
 struct mt76_driver_ops {
 	u32 drv_flags;
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c b/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
index b456ccd00d581..11c16d1fc70fc 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
@@ -156,7 +156,8 @@ mt76x0e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	static const struct mt76_driver_ops drv_ops = {
 		.txwi_size = sizeof(struct mt76x02_txwi),
 		.drv_flags = MT_DRV_TX_ALIGNED4_SKBS |
-			     MT_DRV_SW_RX_AIRTIME,
+			     MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.set_channel = mt76x0_set_channel,
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c b/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c
index b031c500b7415..90e5666c0857d 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c
@@ -214,7 +214,8 @@ static int mt76x0u_probe(struct usb_interface *usb_intf,
 			 const struct usb_device_id *id)
 {
 	static const struct mt76_driver_ops drv_ops = {
-		.drv_flags = MT_DRV_SW_RX_AIRTIME,
+		.drv_flags = MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.set_channel = mt76x0_set_channel,
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c b/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
index 727bfdd00b400..2303019670e2c 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
@@ -22,7 +22,8 @@ mt76x2e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	static const struct mt76_driver_ops drv_ops = {
 		.txwi_size = sizeof(struct mt76x02_txwi),
 		.drv_flags = MT_DRV_TX_ALIGNED4_SKBS |
-			     MT_DRV_SW_RX_AIRTIME,
+			     MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.set_channel = mt76x2e_set_channel,
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c b/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c
index a4f4d12f904e7..84ef80ab4afbf 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c
@@ -30,7 +30,8 @@ static int mt76x2u_probe(struct usb_interface *intf,
 			 const struct usb_device_id *id)
 {
 	static const struct mt76_driver_ops drv_ops = {
-		.drv_flags = MT_DRV_SW_RX_AIRTIME,
+		.drv_flags = MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.set_channel = mt76x2u_set_channel,
diff --git a/drivers/net/wireless/mediatek/mt76/tx.c b/drivers/net/wireless/mediatek/mt76/tx.c
index af0c50c983ec1..513916469ca2f 100644
--- a/drivers/net/wireless/mediatek/mt76/tx.c
+++ b/drivers/net/wireless/mediatek/mt76/tx.c
@@ -100,7 +100,8 @@ __mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, u8 flags,
 		return;
 
 	/* Tx status can be unreliable. if it fails, mark the frame as ACKed */
-	if (flags & MT_TX_CB_TXS_FAILED) {
+	if (flags & MT_TX_CB_TXS_FAILED &&
+	    (dev->drv->drv_flags & MT_DRV_IGNORE_TXS_FAILED)) {
 		info->status.rates[0].count = 0;
 		info->status.rates[0].idx = -1;
 		info->flags |= IEEE80211_TX_STAT_ACK;
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:04:52 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:04:52 -0400
Subject: [PATCH AUTOSEL 6.14 076/642] wifi: mt76: mt7996: use the correct vif link for scanning/roc
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-76-sashal@kernel.org>

From: Felix Fietkau <nbd at nbd.name>

[ Upstream commit 13b4c81083cc4b59fb639a511c0a9a7c38efde7e ]

Use the newly added offchannel_link pointer in vif data

Link: https://patch.msgid.link/20250311103646.43346-5-nbd at nbd.name
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 .../net/wireless/mediatek/mt76/mt7996/mac.c   | 40 +++++++++++++------
 .../net/wireless/mediatek/mt76/mt7996/main.c  |  1 +
 2 files changed, 28 insertions(+), 13 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
index 019c925ae600e..88f9d9059d5f2 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
@@ -832,7 +832,8 @@ void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
 	u8 band_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2;
 	u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0;
 	bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP;
-	struct mt76_vif_link *mvif;
+	struct mt76_vif_link *mlink = NULL;
+	struct mt7996_vif *mvif;
 	u16 tx_count = 15;
 	u32 val;
 	bool inband_disc = !!(changed & (BSS_CHANGED_UNSOL_BCAST_PROBE_RESP |
@@ -840,11 +841,18 @@ void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
 	bool beacon = !!(changed & (BSS_CHANGED_BEACON |
 				    BSS_CHANGED_BEACON_ENABLED)) && (!inband_disc);
 
-	mvif = vif ? (struct mt76_vif_link *)vif->drv_priv : NULL;
-	if (mvif) {
-		omac_idx = mvif->omac_idx;
-		wmm_idx = mvif->wmm_idx;
-		band_idx = mvif->band_idx;
+	if (vif) {
+		mvif = (struct mt7996_vif *)vif->drv_priv;
+		if (wcid->offchannel)
+			mlink = rcu_dereference(mvif->mt76.offchannel_link);
+		if (!mlink)
+			mlink = &mvif->deflink.mt76;
+	}
+
+	if (mlink) {
+		omac_idx = mlink->omac_idx;
+		wmm_idx = mlink->wmm_idx;
+		band_idx = mlink->band_idx;
 	}
 
 	if (inband_disc) {
@@ -910,13 +918,13 @@ void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
 			     is_multicast_ether_addr(hdr->addr1);
 		u8 idx = MT7996_BASIC_RATES_TBL;
 
-		if (mvif) {
-			if (mcast && mvif->mcast_rates_idx)
-				idx = mvif->mcast_rates_idx;
-			else if (beacon && mvif->beacon_rates_idx)
-				idx = mvif->beacon_rates_idx;
+		if (mlink) {
+			if (mcast && mlink->mcast_rates_idx)
+				idx = mlink->mcast_rates_idx;
+			else if (beacon && mlink->beacon_rates_idx)
+				idx = mlink->beacon_rates_idx;
 			else
-				idx = mvif->basic_rates_idx;
+				idx = mlink->basic_rates_idx;
 		}
 
 		val = FIELD_PREP(MT_TXD6_TX_RATE, idx) | MT_TXD6_FIXED_BW;
@@ -984,8 +992,14 @@ int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
 
 	if (vif) {
 		struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv;
+		struct mt76_vif_link *mlink = NULL;
+
+		if (wcid->offchannel)
+			mlink = rcu_dereference(mvif->mt76.offchannel_link);
+		if (!mlink)
+			mlink = &mvif->deflink.mt76;
 
-		txp->fw.bss_idx = mvif->deflink.mt76.idx;
+		txp->fw.bss_idx = mlink->idx;
 	}
 
 	txp->fw.token = cpu_to_le16(id);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/main.c b/drivers/net/wireless/mediatek/mt76/mt7996/main.c
index 980a059b3b38f..b01cc7ef47999 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/main.c
@@ -249,6 +249,7 @@ int mt7996_vif_link_add(struct mt76_phy *mphy, struct ieee80211_vif *vif,
 	mlink->band_idx = band_idx;
 	mlink->wmm_idx = vif->type == NL80211_IFTYPE_AP ? 0 : 3;
 	mlink->wcid = &link->sta.wcid;
+	mlink->wcid->offchannel = mlink->offchannel;
 
 	ret = mt7996_mcu_add_dev_info(phy, vif, link_conf, mlink, true);
 	if (ret)
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:04:53 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:04:53 -0400
Subject: [PATCH AUTOSEL 6.14 077/642] wifi: mt76: scan: set vif offchannel link for scanning/roc
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-77-sashal@kernel.org>

From: Felix Fietkau <nbd at nbd.name>

[ Upstream commit 3ba20af886d1f604dceeb4d4c8ff872e2c4e885e ]

The driver needs to know what vif link to use

Link: https://patch.msgid.link/20250311103646.43346-4-nbd at nbd.name
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/mediatek/mt76/channel.c | 3 +++
 drivers/net/wireless/mediatek/mt76/mt76.h    | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/net/wireless/mediatek/mt76/channel.c b/drivers/net/wireless/mediatek/mt76/channel.c
index 6a35c6ebd823e..e7b839e742903 100644
--- a/drivers/net/wireless/mediatek/mt76/channel.c
+++ b/drivers/net/wireless/mediatek/mt76/channel.c
@@ -293,6 +293,7 @@ struct mt76_vif_link *mt76_get_vif_phy_link(struct mt76_phy *phy,
 		kfree(mlink);
 		return ERR_PTR(ret);
 	}
+	rcu_assign_pointer(mvif->offchannel_link, mlink);
 
 	return mlink;
 }
@@ -301,10 +302,12 @@ void mt76_put_vif_phy_link(struct mt76_phy *phy, struct ieee80211_vif *vif,
 			   struct mt76_vif_link *mlink)
 {
 	struct mt76_dev *dev = phy->dev;
+	struct mt76_vif_data *mvif = mlink->mvif;
 
 	if (IS_ERR_OR_NULL(mlink) || !mlink->offchannel)
 		return;
 
+	rcu_assign_pointer(mvif->offchannel_link, NULL);
 	dev->drv->vif_link_remove(phy, vif, &vif->bss_conf, mlink);
 	kfree(mlink);
 }
diff --git a/drivers/net/wireless/mediatek/mt76/mt76.h b/drivers/net/wireless/mediatek/mt76/mt76.h
index 8714418f3906c..e4ecd9cde36dc 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76.h
@@ -351,6 +351,7 @@ struct mt76_wcid {
 	u8 hw_key_idx;
 	u8 hw_key_idx2;
 
+	u8 offchannel:1;
 	u8 sta:1;
 	u8 sta_disabled:1;
 	u8 amsdu:1;
@@ -788,6 +789,7 @@ struct mt76_vif_link {
 
 struct mt76_vif_data {
 	struct mt76_vif_link __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS];
+	struct mt76_vif_link __rcu *offchannel_link;
 
 	struct mt76_phy *roc_phy;
 	u16 valid_links;
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:04:54 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:04:54 -0400
Subject: [PATCH AUTOSEL 6.14 078/642] wifi: mt76: mt7996: fix SER reset trigger on WED reset
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-78-sashal@kernel.org>

From: Rex Lu <rex.lu at mediatek.com>

[ Upstream commit 8d38abdf6c182225c5c0a81451fa51b7b36a635d ]

The firmware needs a specific trigger when WED is being reset due to an
ethernet reset condition. This helps prevent further L1 SER failure.

Signed-off-by: Rex Lu <rex.lu at mediatek.com>
Link: https://patch.msgid.link/20250311103646.43346-2-nbd at nbd.name
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/mediatek/mt76/mt7996/mcu.h  | 3 ++-
 drivers/net/wireless/mediatek/mt76/mt7996/mmio.c | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mcu.h b/drivers/net/wireless/mediatek/mt76/mt7996/mcu.h
index 43468bcaffc6d..a75e1c9435bb0 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mcu.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mcu.h
@@ -908,7 +908,8 @@ enum {
 	UNI_CMD_SER_SET_RECOVER_L3_TX_DISABLE,
 	UNI_CMD_SER_SET_RECOVER_L3_BF,
 	UNI_CMD_SER_SET_RECOVER_L4_MDP,
-	UNI_CMD_SER_SET_RECOVER_FULL,
+	UNI_CMD_SER_SET_RECOVER_FROM_ETH,
+	UNI_CMD_SER_SET_RECOVER_FULL = 8,
 	UNI_CMD_SER_SET_SYSTEM_ASSERT,
 	/* action */
 	UNI_CMD_SER_ENABLE = 1,
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mmio.c b/drivers/net/wireless/mediatek/mt76/mt7996/mmio.c
index 7a8ee6c75cf2b..9d37f82387464 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mmio.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mmio.c
@@ -281,7 +281,7 @@ static int mt7996_mmio_wed_reset(struct mtk_wed_device *wed)
 	if (test_and_set_bit(MT76_STATE_WED_RESET, &mphy->state))
 		return -EBUSY;
 
-	ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, UNI_CMD_SER_SET_RECOVER_L1,
+	ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, UNI_CMD_SER_SET_RECOVER_FROM_ETH,
 				 mphy->band_idx);
 	if (ret)
 		goto out;
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:04:55 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:04:55 -0400
Subject: [PATCH AUTOSEL 6.14 079/642] wifi: mt76: mt7996: revise TXS size
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-79-sashal@kernel.org>

From: Benjamin Lin <benjamin-jw.lin at mediatek.com>

[ Upstream commit 593c829b4326f7b3b15a69e97c9044ecbad3c319 ]

Size of MPDU/PPDU TXS is 12 DWs.
In mt7996/mt7992, last 4 DWs are reserved, so TXS size was mistakenly
considered to be 8 DWs. However, in mt7990, 9th DW of TXS starts to be used.

Signed-off-by: Benjamin Lin <benjamin-jw.lin at mediatek.com>
Link: https://patch.msgid.link/20250311103646.43346-1-nbd at nbd.name
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h | 3 +++
 drivers/net/wireless/mediatek/mt76/mt7996/mac.c       | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h b/drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h
index db0c29e65185c..487ad716f872a 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h
@@ -314,6 +314,9 @@ enum tx_frag_idx {
 #define MT_TXFREE_INFO_COUNT		GENMASK(27, 24)
 #define MT_TXFREE_INFO_STAT		GENMASK(29, 28)
 
+#define MT_TXS_HDR_SIZE			4 /* Unit: DW */
+#define MT_TXS_SIZE			12 /* Unit: DW */
+
 #define MT_TXS0_BW			GENMASK(31, 29)
 #define MT_TXS0_TID			GENMASK(28, 26)
 #define MT_TXS0_AMPDU			BIT(25)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
index 88f9d9059d5f2..c7e8336027334 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
@@ -1413,7 +1413,7 @@ bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len)
 		mt7996_mac_tx_free(dev, data, len);
 		return false;
 	case PKT_TYPE_TXS:
-		for (rxd += 4; rxd + 8 <= end; rxd += 8)
+		for (rxd += MT_TXS_HDR_SIZE; rxd + MT_TXS_SIZE <= end; rxd += MT_TXS_SIZE)
 			mt7996_mac_add_txs(dev, rxd);
 		return false;
 	case PKT_TYPE_RX_FW_MONITOR:
@@ -1456,7 +1456,7 @@ void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
 		mt7996_mcu_rx_event(dev, skb);
 		break;
 	case PKT_TYPE_TXS:
-		for (rxd += 4; rxd + 8 <= end; rxd += 8)
+		for (rxd += MT_TXS_HDR_SIZE; rxd + MT_TXS_SIZE <= end; rxd += MT_TXS_SIZE)
 			mt7996_mac_add_txs(dev, rxd);
 		dev_kfree_skb(skb);
 		break;
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:04:56 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:04:56 -0400
Subject: [PATCH AUTOSEL 6.14 080/642] wifi: mt76: mt7925: load the appropriate CLC data based on hardware type
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-80-sashal@kernel.org>

From: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>

[ Upstream commit f2027ef3f733d3f0bb7f27fa3343784058f946ab ]

Read the EEPROM to determine the hardware type and uses this to load the
correct CLC data.

Signed-off-by: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
Link: https://patch.msgid.link/20250304113649.867387-1-mingyen.hsieh at mediatek.com
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 .../net/wireless/mediatek/mt76/mt7925/mcu.c   | 61 ++++++++++++++++++-
 .../wireless/mediatek/mt76/mt7925/mt7925.h    |  3 +
 2 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
index b8cd7cd3d832b..a1d6fd5888f54 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
@@ -631,6 +631,54 @@ int mt7925_mcu_uni_rx_ba(struct mt792x_dev *dev,
 				 enable, false);
 }
 
+static int mt7925_mcu_read_eeprom(struct mt792x_dev *dev, u32 offset, u8 *val)
+{
+	struct {
+		u8 rsv[4];
+
+		__le16 tag;
+		__le16 len;
+
+		__le32 addr;
+		__le32 valid;
+		u8 data[MT7925_EEPROM_BLOCK_SIZE];
+	} __packed req = {
+		.tag = cpu_to_le16(1),
+		.len = cpu_to_le16(sizeof(req) - 4),
+		.addr = cpu_to_le32(round_down(offset,
+				    MT7925_EEPROM_BLOCK_SIZE)),
+	};
+	struct evt {
+		u8 rsv[4];
+
+		__le16 tag;
+		__le16 len;
+
+		__le32 ver;
+		__le32 addr;
+		__le32 valid;
+		__le32 size;
+		__le32 magic_num;
+		__le32 type;
+		__le32 rsv1[4];
+		u8 data[32];
+	} __packed *res;
+	struct sk_buff *skb;
+	int ret;
+
+	ret = mt76_mcu_send_and_get_msg(&dev->mt76, MCU_WM_UNI_CMD_QUERY(EFUSE_CTRL),
+					&req, sizeof(req), true, &skb);
+	if (ret)
+		return ret;
+
+	res = (struct evt *)skb->data;
+	*val = res->data[offset % MT7925_EEPROM_BLOCK_SIZE];
+
+	dev_kfree_skb(skb);
+
+	return 0;
+}
+
 static int mt7925_load_clc(struct mt792x_dev *dev, const char *fw_name)
 {
 	const struct mt76_connac2_fw_trailer *hdr;
@@ -639,13 +687,20 @@ static int mt7925_load_clc(struct mt792x_dev *dev, const char *fw_name)
 	struct mt76_dev *mdev = &dev->mt76;
 	struct mt792x_phy *phy = &dev->phy;
 	const struct firmware *fw;
+	u8 *clc_base = NULL, hw_encap = 0;
 	int ret, i, len, offset = 0;
-	u8 *clc_base = NULL;
 
 	if (mt7925_disable_clc ||
 	    mt76_is_usb(&dev->mt76))
 		return 0;
 
+	if (mt76_is_mmio(&dev->mt76)) {
+		ret = mt7925_mcu_read_eeprom(dev, MT_EE_HW_TYPE, &hw_encap);
+		if (ret)
+			return ret;
+		hw_encap = u8_get_bits(hw_encap, MT_EE_HW_TYPE_ENCAP);
+	}
+
 	ret = request_firmware(&fw, fw_name, mdev->dev);
 	if (ret)
 		return ret;
@@ -690,6 +745,10 @@ static int mt7925_load_clc(struct mt792x_dev *dev, const char *fw_name)
 		if (phy->clc[clc->idx])
 			continue;
 
+		/* header content sanity */
+		if (u8_get_bits(clc->type, MT_EE_HW_TYPE_ENCAP) != hw_encap)
+			continue;
+
 		phy->clc[clc->idx] = devm_kmemdup(mdev->dev, clc,
 						  le32_to_cpu(clc->len),
 						  GFP_KERNEL);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h b/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
index cb7b1a49fbd14..073e433069e0e 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
@@ -167,9 +167,12 @@ enum mt7925_eeprom_field {
 	MT_EE_CHIP_ID =		0x000,
 	MT_EE_VERSION =		0x002,
 	MT_EE_MAC_ADDR =	0x004,
+	MT_EE_HW_TYPE =		0xa71,
 	__MT_EE_MAX =		0x9ff
 };
 
+#define MT_EE_HW_TYPE_ENCAP     GENMASK(1, 0)
+
 enum {
 	TXPWR_USER,
 	TXPWR_EEPROM,
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:04:57 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:04:57 -0400
Subject: [PATCH AUTOSEL 6.14 081/642] wifi: mt76: mt7925: Simplify HIF suspend handling to avoid suspend fail
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-81-sashal@kernel.org>

From: Quan Zhou <quan.zhou at mediatek.com>

[ Upstream commit bf39813599b0375a3eebbbc6837f728554b3883a ]

System suspend failures may occur due to inappropriate
handling of traffic not idle event by the WiFi driver.
The WiFi firmware's traffic not idle indication does
not need to be tied to suspend. Fix the flow to ensuring
the system can suspend properly.

Signed-off-by: Quan Zhou <quan.zhou at mediatek.com>
Link: https://patch.msgid.link/34208c7280325f57a651363d339399eb1744d3b7.1740400998.git.quan.zhou at mediatek.com
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
index a1d6fd5888f54..e6d053c0cdbd2 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
@@ -348,14 +348,10 @@ mt7925_mcu_handle_hif_ctrl_basic(struct mt792x_dev *dev, struct tlv *tlv)
 	basic = (struct mt7925_mcu_hif_ctrl_basic_tlv *)tlv;
 
 	if (basic->hifsuspend) {
-		if (basic->hif_tx_traffic_status == HIF_TRAFFIC_IDLE &&
-		    basic->hif_rx_traffic_status == HIF_TRAFFIC_IDLE)
-			/* success */
-			dev->hif_idle = true;
-		else
-			/* busy */
-			/* invalid */
-			dev->hif_idle = false;
+		dev->hif_idle = true;
+		if (!(basic->hif_tx_traffic_status == HIF_TRAFFIC_IDLE &&
+		      basic->hif_rx_traffic_status == HIF_TRAFFIC_IDLE))
+			dev_info(dev->mt76.dev, "Hif traffic not idle.\n");
 	} else {
 		dev->hif_resumed = true;
 	}
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:04:58 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:04:58 -0400
Subject: [PATCH AUTOSEL 6.14 082/642] wifi: mt76: mt7925: fix fails to enter low power mode in suspend state
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-82-sashal@kernel.org>

From: Quan Zhou <quan.zhou at mediatek.com>

[ Upstream commit 2d5630b0c9466ac6549495828aa7dce7424a272a ]

The mt7925 sometimes fails to enter low power mode during suspend.
This is caused by the chip firmware sending an additional ACK event
to the host after processing the suspend command. Due to timing issues,
this event may not reach the host, causing the chip to get stuck.
To resolve this, the ACK flag in the suspend command is removed,
as it is not needed in the MT7925 architecture. This prevents the
firmware from sending the additional ACK event, ensuring the device
can reliably enter low power mode during suspend.

Signed-off-by: Quan Zhou <quan.zhou at mediatek.com>
Link: https://patch.msgid.link/d056938144a3a0336c3a4e3cec6f271899f32bf7.1736775666.git.quan.zhou at mediatek.com
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
index e6d053c0cdbd2..8dc5dc0af1b1b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
@@ -3294,6 +3294,9 @@ int mt7925_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb,
 		else
 			uni_txd->option = MCU_CMD_UNI_EXT_ACK;
 
+		if (cmd == MCU_UNI_CMD(HIF_CTRL))
+			uni_txd->option &= ~MCU_CMD_ACK;
+
 		goto exit;
 	}
 
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:05:54 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:05:54 -0400
Subject: [PATCH AUTOSEL 6.14 138/642] ASoC: mediatek: mt6359: Add stub for mt6359_accdet_enable_jack_detect
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-138-sashal@kernel.org>

From: N?colas F. R. A. Prado <nfraprado at collabora.com>

[ Upstream commit 0116a7d84b32537a10d9bea1fd1bfc06577ef527 ]

Add a stub for mt6359_accdet_enable_jack_detect() to prevent linker
failures in the machine sound drivers calling it when
CONFIG_SND_SOC_MT6359_ACCDET is not enabled.

Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
Link: https://patch.msgid.link/20250306-mt8188-accdet-v3-3-7828e835ff4b at collabora.com
Signed-off-by: Mark Brown <broonie at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 sound/soc/codecs/mt6359-accdet.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/sound/soc/codecs/mt6359-accdet.h b/sound/soc/codecs/mt6359-accdet.h
index c234f2f4276a1..78ada3a5bfae5 100644
--- a/sound/soc/codecs/mt6359-accdet.h
+++ b/sound/soc/codecs/mt6359-accdet.h
@@ -123,6 +123,15 @@ struct mt6359_accdet {
 	struct workqueue_struct *jd_workqueue;
 };
 
+#if IS_ENABLED(CONFIG_SND_SOC_MT6359_ACCDET)
 int mt6359_accdet_enable_jack_detect(struct snd_soc_component *component,
 				     struct snd_soc_jack *jack);
+#else
+static inline int
+mt6359_accdet_enable_jack_detect(struct snd_soc_component *component,
+				 struct snd_soc_jack *jack)
+{
+	return -EOPNOTSUPP;
+}
+#endif
 #endif
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:07:35 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:07:35 -0400
Subject: [PATCH AUTOSEL 6.14 239/642] soc: mediatek: mtk-mutex: Add DPI1 SOF/EOF to MT8188 mutex tables
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-239-sashal@kernel.org>

From: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

[ Upstream commit 694e0b7c1747603243da874de9cbbf8cb806ca44 ]

MT8188 uses DPI1 to output to the HDMI controller: add the
Start of Frame and End of Frame configuration for the DPI1
IP to the tables to unblock generation and sending of these
signals to the GCE.

Link: https://lore.kernel.org/r/20250212100012.33001-2-angelogioacchino.delregno at collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/soc/mediatek/mtk-mutex.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 5250c1d702eb9..aaa965d4b050a 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -155,6 +155,7 @@
 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3	23
 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4	24
 #define MT8188_MUTEX_MOD_DISP1_DISP_MIXER	30
+#define MT8188_MUTEX_MOD_DISP1_DPI1		38
 #define MT8188_MUTEX_MOD_DISP1_DP_INTF1		39
 
 #define MT8195_MUTEX_MOD_DISP_OVL0		0
@@ -289,6 +290,7 @@
 #define MT8188_MUTEX_SOF_DSI0			1
 #define MT8188_MUTEX_SOF_DP_INTF0		3
 #define MT8188_MUTEX_SOF_DP_INTF1		4
+#define MT8188_MUTEX_SOF_DPI1			5
 #define MT8195_MUTEX_SOF_DSI0			1
 #define MT8195_MUTEX_SOF_DSI1			2
 #define MT8195_MUTEX_SOF_DP_INTF0		3
@@ -301,6 +303,7 @@
 #define MT8188_MUTEX_EOF_DSI0			(MT8188_MUTEX_SOF_DSI0 << 7)
 #define MT8188_MUTEX_EOF_DP_INTF0		(MT8188_MUTEX_SOF_DP_INTF0 << 7)
 #define MT8188_MUTEX_EOF_DP_INTF1		(MT8188_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8188_MUTEX_EOF_DPI1			(MT8188_MUTEX_SOF_DPI1 << 7)
 #define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)
 #define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)
 #define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)
@@ -472,6 +475,7 @@ static const u8 mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
 	[DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
 	[DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
+	[DDP_COMPONENT_DPI1] = MT8188_MUTEX_MOD_DISP1_DPI1,
 	[DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
 	[DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
 	[DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
@@ -686,6 +690,8 @@ static const u16 mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] =
 		MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
+	[MUTEX_SOF_DPI1] =
+		MT8188_MUTEX_SOF_DPI1 | MT8188_MUTEX_EOF_DPI1,
 	[MUTEX_SOF_DP_INTF0] =
 		MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
 	[MUTEX_SOF_DP_INTF1] =
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:08:23 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:08:23 -0400
Subject: [PATCH AUTOSEL 6.14 287/642] drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-287-sashal@kernel.org>

From: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

[ Upstream commit 8c9da7cd0bbcc90ab444454fecf535320456a312 ]

In preparation for adding support for newer DPI instances which
do support direct-pin but do not have any H_FRE_CON register,
like the one found in MT8195 and MT8188, add a branch to check
if the reg_h_fre_con variable was declared in the mtk_dpi_conf
structure for the probed SoC DPI version.

As a note, this is useful specifically only for cases in which
the support_direct_pin variable is true, so mt8195-dpintf is
not affected by any issue.

Reviewed-by: CK Hu <ck.hu at mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-6-angelogioacchino.delregno at collabora.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index a12ef24c77423..b7d90574df9a6 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -410,12 +410,13 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
 
 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 {
-	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
+	if (dpi->conf->reg_h_fre_con)
+		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
 {
-	if (dpi->conf->edge_sel_en)
+	if (dpi->conf->edge_sel_en && dpi->conf->reg_h_fre_con)
 		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
 }
 
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:08:44 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:08:44 -0400
Subject: [PATCH AUTOSEL 6.14 308/642] net: ethernet: mtk_ppe_offload: Allow QinQ, double ETH_P_8021Q only
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-308-sashal@kernel.org>

From: Eric Woudstra <ericwouds at gmail.com>

[ Upstream commit 7fe0353606d77a32c4c7f2814833dd1c043ebdd2 ]

mtk_foe_entry_set_vlan() in mtk_ppe.c already supports double vlan
tagging, but mtk_flow_offload_replace() in mtk_ppe_offload.c only allows
for 1 vlan tag, optionally in combination with pppoe and dsa tags.

However, mtk_foe_entry_set_vlan() only allows for setting the vlan id.
The protocol cannot be set, it is always ETH_P_8021Q, for inner and outer
tag. This patch adds QinQ support to mtk_flow_offload_replace(), only in
the case that both inner and outer tags are ETH_P_8021Q.

Only PPPoE-in-Q (as before) and Q-in-Q are allowed. A combination
of PPPoE and Q-in-Q is not allowed.

Signed-off-by: Eric Woudstra <ericwouds at gmail.com>
Link: https://patch.msgid.link/20250225201509.20843-1-ericwouds at gmail.com
Signed-off-by: Paolo Abeni <pabeni at redhat.com>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 .../net/ethernet/mediatek/mtk_ppe_offload.c   | 22 +++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
index f20bb390df3ad..c855fb799ce14 100644
--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
@@ -34,8 +34,10 @@ struct mtk_flow_data {
 	u16 vlan_in;
 
 	struct {
-		u16 id;
-		__be16 proto;
+		struct {
+			u16 id;
+			__be16 proto;
+		} vlans[2];
 		u8 num;
 	} vlan;
 	struct {
@@ -349,18 +351,19 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f,
 		case FLOW_ACTION_CSUM:
 			break;
 		case FLOW_ACTION_VLAN_PUSH:
-			if (data.vlan.num == 1 ||
+			if (data.vlan.num + data.pppoe.num == 2 ||
 			    act->vlan.proto != htons(ETH_P_8021Q))
 				return -EOPNOTSUPP;
 
-			data.vlan.id = act->vlan.vid;
-			data.vlan.proto = act->vlan.proto;
+			data.vlan.vlans[data.vlan.num].id = act->vlan.vid;
+			data.vlan.vlans[data.vlan.num].proto = act->vlan.proto;
 			data.vlan.num++;
 			break;
 		case FLOW_ACTION_VLAN_POP:
 			break;
 		case FLOW_ACTION_PPPOE_PUSH:
-			if (data.pppoe.num == 1)
+			if (data.pppoe.num == 1 ||
+			    data.vlan.num == 2)
 				return -EOPNOTSUPP;
 
 			data.pppoe.sid = act->pppoe.sid;
@@ -450,12 +453,9 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f,
 	if (offload_type == MTK_PPE_PKT_TYPE_BRIDGE)
 		foe.bridge.vlan = data.vlan_in;
 
-	if (data.vlan.num == 1) {
-		if (data.vlan.proto != htons(ETH_P_8021Q))
-			return -EOPNOTSUPP;
+	for (i = 0; i < data.vlan.num; i++)
+		mtk_foe_entry_set_vlan(eth, &foe, data.vlan.vlans[i].id);
 
-		mtk_foe_entry_set_vlan(eth, &foe, data.vlan.id);
-	}
 	if (data.pppoe.num == 1)
 		mtk_foe_entry_set_pppoe(eth, &foe, data.pppoe.sid);
 
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:09:03 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:09:03 -0400
Subject: [PATCH AUTOSEL 6.14 327/642] ASoC: mediatek: mt8188: Treat DMIC_GAINx_CUR as non-volatile
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-327-sashal@kernel.org>

From: N?colas F. R. A. Prado <nfraprado at collabora.com>

[ Upstream commit 7d87bde21c73731ddaf15e572020f80999c38ee3 ]

The DMIC_GAINx_CUR registers contain the current (as in present) gain of
each DMIC. During capture, this gain will ramp up until a target value
is reached, and therefore the register is volatile since it is updated
automatically by hardware.

However, after capture the register's value returns to the value that
was written to it. So reading these registers returns the current gain,
and writing configures the initial gain for every capture.

>From an audio configuration perspective, reading the instantaneous gain
is not really useful. Instead, reading back the initial gain that was
configured is the desired behavior. For that reason, consider the
DMIC_GAINx_CUR registers as non-volatile, so the regmap's cache can be
used to retrieve the values, rather than requiring pm runtime resuming
the device.

Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Link: https://patch.msgid.link/20250225-genio700-dmic-v2-3-3076f5b50ef7 at collabora.com
Signed-off-by: Mark Brown <broonie at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 sound/soc/mediatek/mt8188/mt8188-afe-pcm.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c b/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
index 73e5c63aeec87..d36520c6272dd 100644
--- a/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
@@ -2855,10 +2855,6 @@ static bool mt8188_is_volatile_reg(struct device *dev, unsigned int reg)
 	case AFE_DMIC3_SRC_DEBUG_MON0:
 	case AFE_DMIC3_UL_SRC_MON0:
 	case AFE_DMIC3_UL_SRC_MON1:
-	case DMIC_GAIN1_CUR:
-	case DMIC_GAIN2_CUR:
-	case DMIC_GAIN3_CUR:
-	case DMIC_GAIN4_CUR:
 	case ETDM_IN1_MONITOR:
 	case ETDM_IN2_MONITOR:
 	case ETDM_OUT1_MONITOR:
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:09:04 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:09:04 -0400
Subject: [PATCH AUTOSEL 6.14 328/642] ASoC: mediatek: mt8188: Add reference for dmic clocks
In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org>
References: <20250505221419.2672473-1-sashal@kernel.org>
Message-ID: <20250505221419.2672473-328-sashal@kernel.org>

From: N?colas F. R. A. Prado <nfraprado at collabora.com>

[ Upstream commit bf1800073f4d55f08191b034c86b95881e99b6fd ]

Add the names for the dmic clocks, aud_afe_dmic* and aud_dmic_hires*, so
they can be acquired and enabled by the platform driver.

Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Link: https://patch.msgid.link/20250225-genio700-dmic-v2-2-3076f5b50ef7 at collabora.com
Signed-off-by: Mark Brown <broonie at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 sound/soc/mediatek/mt8188/mt8188-afe-clk.c | 8 ++++++++
 sound/soc/mediatek/mt8188/mt8188-afe-clk.h | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
index e69c1bb2cb239..7f411b8577823 100644
--- a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
@@ -58,7 +58,15 @@ static const char *aud_clks[MT8188_CLK_NUM] = {
 	[MT8188_CLK_AUD_ADC] = "aud_adc",
 	[MT8188_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
 	[MT8188_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
+	[MT8188_CLK_AUD_AFE_DMIC1] = "aud_afe_dmic1",
+	[MT8188_CLK_AUD_AFE_DMIC2] = "aud_afe_dmic2",
+	[MT8188_CLK_AUD_AFE_DMIC3] = "aud_afe_dmic3",
+	[MT8188_CLK_AUD_AFE_DMIC4] = "aud_afe_dmic4",
 	[MT8188_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
+	[MT8188_CLK_AUD_DMIC_HIRES1] = "aud_dmic_hires1",
+	[MT8188_CLK_AUD_DMIC_HIRES2] = "aud_dmic_hires2",
+	[MT8188_CLK_AUD_DMIC_HIRES3] = "aud_dmic_hires3",
+	[MT8188_CLK_AUD_DMIC_HIRES4] = "aud_dmic_hires4",
 	[MT8188_CLK_AUD_I2SIN] = "aud_i2sin",
 	[MT8188_CLK_AUD_TDM_IN] = "aud_tdm_in",
 	[MT8188_CLK_AUD_I2S_OUT] = "aud_i2s_out",
diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-clk.h b/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
index ec53c171c170a..c6c78d684f3ee 100644
--- a/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
@@ -54,7 +54,15 @@ enum {
 	MT8188_CLK_AUD_ADC,
 	MT8188_CLK_AUD_DAC_HIRES,
 	MT8188_CLK_AUD_A1SYS_HP,
+	MT8188_CLK_AUD_AFE_DMIC1,
+	MT8188_CLK_AUD_AFE_DMIC2,
+	MT8188_CLK_AUD_AFE_DMIC3,
+	MT8188_CLK_AUD_AFE_DMIC4,
 	MT8188_CLK_AUD_ADC_HIRES,
+	MT8188_CLK_AUD_DMIC_HIRES1,
+	MT8188_CLK_AUD_DMIC_HIRES2,
+	MT8188_CLK_AUD_DMIC_HIRES3,
+	MT8188_CLK_AUD_DMIC_HIRES4,
 	MT8188_CLK_AUD_I2SIN,
 	MT8188_CLK_AUD_TDM_IN,
 	MT8188_CLK_AUD_I2S_OUT,
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:31:53 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:31:53 -0400
Subject: [PATCH AUTOSEL 6.12 037/486] thermal/drivers/mediatek/lvts: Start sensor interrupts disabled
In-Reply-To: <20250505223922.2682012-1-sashal@kernel.org>
References: <20250505223922.2682012-1-sashal@kernel.org>
Message-ID: <20250505223922.2682012-37-sashal@kernel.org>

From: N?colas F. R. A. Prado <nfraprado at collabora.com>

[ Upstream commit 2738fb3ec6838a10d2c4ce65cefdb3b90b11bd61 ]

Interrupts are enabled per sensor in lvts_update_irq_mask() as needed,
there's no point in enabling all of them during initialization. Change
the MONINT register initial value so all sensor interrupts start
disabled.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
Link: https://lore.kernel.org/r/20250113-mt8192-lvts-filtered-suspend-fix-v2-4-07a25200c7c6 at collabora.com
Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/thermal/mediatek/lvts_thermal.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index 4b3225377e8f8..3295b27ab70d2 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -65,7 +65,6 @@
 #define LVTS_HW_FILTER				0x0
 #define LVTS_TSSEL_CONF				0x13121110
 #define LVTS_CALSCALE_CONF			0x300
-#define LVTS_MONINT_CONF			0x0300318C
 
 #define LVTS_MONINT_OFFSET_SENSOR0		0xC
 #define LVTS_MONINT_OFFSET_SENSOR1		0x180
@@ -929,7 +928,7 @@ static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl)
 	 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS
 	 * register, except we set the bits to enable the interrupt.
 	 */
-	writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base));
+	writel(0, LVTS_MONINT(lvts_ctrl->base));
 
 	return 0;
 }
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:31:55 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:31:55 -0400
Subject: [PATCH AUTOSEL 6.12 039/486] Bluetooth: btmtksdio: Prevent enabling interrupts after IRQ handler removal
In-Reply-To: <20250505223922.2682012-1-sashal@kernel.org>
References: <20250505223922.2682012-1-sashal@kernel.org>
Message-ID: <20250505223922.2682012-39-sashal@kernel.org>

From: Sean Wang <sean.wang at mediatek.com>

[ Upstream commit 6ac4233afb9a389a7629b7f812395d1d1eca5a83 ]

Ensure interrupts are not re-enabled when the IRQ handler has already been
removed. This prevents unexpected IRQ handler execution due to stale or
unhandled interrupts.

Modify btmtksdio_txrx_work to check if bdev->func->irq_handler exists
before calling sdio_writel to enable interrupts.

Co-developed-by: Pedro Tsai <pedro.tsai at mediatek.com>
Signed-off-by: Pedro Tsai <pedro.tsai at mediatek.com>
Co-developed-by: Felix Freimann <felix.freimann at mediatek.com>
Signed-off-by: Felix Freimann <felix.freimann at mediatek.com>
Signed-off-by: Sean Wang <sean.wang at mediatek.com>
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz at intel.com>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/bluetooth/btmtksdio.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/bluetooth/btmtksdio.c b/drivers/bluetooth/btmtksdio.c
index 11d33cd7b08fc..d4ea1ff07b3e7 100644
--- a/drivers/bluetooth/btmtksdio.c
+++ b/drivers/bluetooth/btmtksdio.c
@@ -610,7 +610,8 @@ static void btmtksdio_txrx_work(struct work_struct *work)
 	} while (int_status || time_is_before_jiffies(txrx_timeout));
 
 	/* Enable interrupt */
-	sdio_writel(bdev->func, C_INT_EN_SET, MTK_REG_CHLPCR, NULL);
+	if (bdev->func->irq_handler)
+		sdio_writel(bdev->func, C_INT_EN_SET, MTK_REG_CHLPCR, NULL);
 
 	sdio_release_host(bdev->func);
 
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:32:16 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:32:16 -0400
Subject: [PATCH AUTOSEL 6.12 060/486] wifi: mt76: only mark tx-status-failed frames as ACKed on mt76x0/2
In-Reply-To: <20250505223922.2682012-1-sashal@kernel.org>
References: <20250505223922.2682012-1-sashal@kernel.org>
Message-ID: <20250505223922.2682012-60-sashal@kernel.org>

From: Felix Fietkau <nbd at nbd.name>

[ Upstream commit 0c5a89ceddc1728a40cb3313948401dd70e3c649 ]

The interrupt status polling is unreliable, which can cause status events
to get lost. On all newer chips, txs-timeout is an indication that the
packet was either never sent, or never acked.
Fixes issues with inactivity polling.

Link: https://patch.msgid.link/20250311103646.43346-6-nbd at nbd.name
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/mediatek/mt76/mt76.h       | 1 +
 drivers/net/wireless/mediatek/mt76/mt76x0/pci.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/mt76x2/pci.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/mt76x2/usb.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/tx.c         | 3 ++-
 6 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt76.h b/drivers/net/wireless/mediatek/mt76/mt76.h
index e2e9b5ece74e2..a6ac8e5512eba 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76.h
@@ -489,6 +489,7 @@ struct mt76_hw_cap {
 #define MT_DRV_RX_DMA_HDR		BIT(3)
 #define MT_DRV_HW_MGMT_TXQ		BIT(4)
 #define MT_DRV_AMSDU_OFFLOAD		BIT(5)
+#define MT_DRV_IGNORE_TXS_FAILED	BIT(6)
 
 struct mt76_driver_ops {
 	u32 drv_flags;
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c b/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
index 1eb955f3ca130..911e162a45980 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
@@ -156,7 +156,8 @@ mt76x0e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	static const struct mt76_driver_ops drv_ops = {
 		.txwi_size = sizeof(struct mt76x02_txwi),
 		.drv_flags = MT_DRV_TX_ALIGNED4_SKBS |
-			     MT_DRV_SW_RX_AIRTIME,
+			     MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.set_channel = mt76x0_set_channel,
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c b/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c
index b031c500b7415..90e5666c0857d 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c
@@ -214,7 +214,8 @@ static int mt76x0u_probe(struct usb_interface *usb_intf,
 			 const struct usb_device_id *id)
 {
 	static const struct mt76_driver_ops drv_ops = {
-		.drv_flags = MT_DRV_SW_RX_AIRTIME,
+		.drv_flags = MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.set_channel = mt76x0_set_channel,
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c b/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
index 67c9d1caa0bd6..55f076231bdc5 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
@@ -22,7 +22,8 @@ mt76x2e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	static const struct mt76_driver_ops drv_ops = {
 		.txwi_size = sizeof(struct mt76x02_txwi),
 		.drv_flags = MT_DRV_TX_ALIGNED4_SKBS |
-			     MT_DRV_SW_RX_AIRTIME,
+			     MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.set_channel = mt76x2e_set_channel,
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c b/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c
index a4f4d12f904e7..84ef80ab4afbf 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c
@@ -30,7 +30,8 @@ static int mt76x2u_probe(struct usb_interface *intf,
 			 const struct usb_device_id *id)
 {
 	static const struct mt76_driver_ops drv_ops = {
-		.drv_flags = MT_DRV_SW_RX_AIRTIME,
+		.drv_flags = MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.set_channel = mt76x2u_set_channel,
diff --git a/drivers/net/wireless/mediatek/mt76/tx.c b/drivers/net/wireless/mediatek/mt76/tx.c
index ce193e625666b..065a1e4537457 100644
--- a/drivers/net/wireless/mediatek/mt76/tx.c
+++ b/drivers/net/wireless/mediatek/mt76/tx.c
@@ -100,7 +100,8 @@ __mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, u8 flags,
 		return;
 
 	/* Tx status can be unreliable. if it fails, mark the frame as ACKed */
-	if (flags & MT_TX_CB_TXS_FAILED) {
+	if (flags & MT_TX_CB_TXS_FAILED &&
+	    (dev->drv->drv_flags & MT_DRV_IGNORE_TXS_FAILED)) {
 		info->status.rates[0].count = 0;
 		info->status.rates[0].idx = -1;
 		info->flags |= IEEE80211_TX_STAT_ACK;
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:32:17 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:32:17 -0400
Subject: [PATCH AUTOSEL 6.12 061/486] wifi: mt76: mt7996: fix SER reset trigger on WED reset
In-Reply-To: <20250505223922.2682012-1-sashal@kernel.org>
References: <20250505223922.2682012-1-sashal@kernel.org>
Message-ID: <20250505223922.2682012-61-sashal@kernel.org>

From: Rex Lu <rex.lu at mediatek.com>

[ Upstream commit 8d38abdf6c182225c5c0a81451fa51b7b36a635d ]

The firmware needs a specific trigger when WED is being reset due to an
ethernet reset condition. This helps prevent further L1 SER failure.

Signed-off-by: Rex Lu <rex.lu at mediatek.com>
Link: https://patch.msgid.link/20250311103646.43346-2-nbd at nbd.name
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/mediatek/mt76/mt7996/mcu.h  | 3 ++-
 drivers/net/wireless/mediatek/mt76/mt7996/mmio.c | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mcu.h b/drivers/net/wireless/mediatek/mt76/mt7996/mcu.h
index 43468bcaffc6d..a75e1c9435bb0 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mcu.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mcu.h
@@ -908,7 +908,8 @@ enum {
 	UNI_CMD_SER_SET_RECOVER_L3_TX_DISABLE,
 	UNI_CMD_SER_SET_RECOVER_L3_BF,
 	UNI_CMD_SER_SET_RECOVER_L4_MDP,
-	UNI_CMD_SER_SET_RECOVER_FULL,
+	UNI_CMD_SER_SET_RECOVER_FROM_ETH,
+	UNI_CMD_SER_SET_RECOVER_FULL = 8,
 	UNI_CMD_SER_SET_SYSTEM_ASSERT,
 	/* action */
 	UNI_CMD_SER_ENABLE = 1,
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mmio.c b/drivers/net/wireless/mediatek/mt76/mt7996/mmio.c
index 442f72450352b..b6209ed1cfe01 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mmio.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mmio.c
@@ -281,7 +281,7 @@ static int mt7996_mmio_wed_reset(struct mtk_wed_device *wed)
 	if (test_and_set_bit(MT76_STATE_WED_RESET, &mphy->state))
 		return -EBUSY;
 
-	ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, UNI_CMD_SER_SET_RECOVER_L1,
+	ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, UNI_CMD_SER_SET_RECOVER_FROM_ETH,
 				 mphy->band_idx);
 	if (ret)
 		goto out;
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:32:18 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:32:18 -0400
Subject: [PATCH AUTOSEL 6.12 062/486] wifi: mt76: mt7996: revise TXS size
In-Reply-To: <20250505223922.2682012-1-sashal@kernel.org>
References: <20250505223922.2682012-1-sashal@kernel.org>
Message-ID: <20250505223922.2682012-62-sashal@kernel.org>

From: Benjamin Lin <benjamin-jw.lin at mediatek.com>

[ Upstream commit 593c829b4326f7b3b15a69e97c9044ecbad3c319 ]

Size of MPDU/PPDU TXS is 12 DWs.
In mt7996/mt7992, last 4 DWs are reserved, so TXS size was mistakenly
considered to be 8 DWs. However, in mt7990, 9th DW of TXS starts to be used.

Signed-off-by: Benjamin Lin <benjamin-jw.lin at mediatek.com>
Link: https://patch.msgid.link/20250311103646.43346-1-nbd at nbd.name
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h | 3 +++
 drivers/net/wireless/mediatek/mt76/mt7996/mac.c       | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h b/drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h
index db0c29e65185c..487ad716f872a 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h
@@ -314,6 +314,9 @@ enum tx_frag_idx {
 #define MT_TXFREE_INFO_COUNT		GENMASK(27, 24)
 #define MT_TXFREE_INFO_STAT		GENMASK(29, 28)
 
+#define MT_TXS_HDR_SIZE			4 /* Unit: DW */
+#define MT_TXS_SIZE			12 /* Unit: DW */
+
 #define MT_TXS0_BW			GENMASK(31, 29)
 #define MT_TXS0_TID			GENMASK(28, 26)
 #define MT_TXS0_AMPDU			BIT(25)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
index f590902fdeea3..ef2d7eaaaffdd 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
@@ -1399,7 +1399,7 @@ bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len)
 		mt7996_mac_tx_free(dev, data, len);
 		return false;
 	case PKT_TYPE_TXS:
-		for (rxd += 4; rxd + 8 <= end; rxd += 8)
+		for (rxd += MT_TXS_HDR_SIZE; rxd + MT_TXS_SIZE <= end; rxd += MT_TXS_SIZE)
 			mt7996_mac_add_txs(dev, rxd);
 		return false;
 	case PKT_TYPE_RX_FW_MONITOR:
@@ -1442,7 +1442,7 @@ void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
 		mt7996_mcu_rx_event(dev, skb);
 		break;
 	case PKT_TYPE_TXS:
-		for (rxd += 4; rxd + 8 <= end; rxd += 8)
+		for (rxd += MT_TXS_HDR_SIZE; rxd + MT_TXS_SIZE <= end; rxd += MT_TXS_SIZE)
 			mt7996_mac_add_txs(dev, rxd);
 		dev_kfree_skb(skb);
 		break;
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:32:19 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:32:19 -0400
Subject: [PATCH AUTOSEL 6.12 063/486] wifi: mt76: mt7925: load the appropriate CLC data based on hardware type
In-Reply-To: <20250505223922.2682012-1-sashal@kernel.org>
References: <20250505223922.2682012-1-sashal@kernel.org>
Message-ID: <20250505223922.2682012-63-sashal@kernel.org>

From: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>

[ Upstream commit f2027ef3f733d3f0bb7f27fa3343784058f946ab ]

Read the EEPROM to determine the hardware type and uses this to load the
correct CLC data.

Signed-off-by: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
Link: https://patch.msgid.link/20250304113649.867387-1-mingyen.hsieh at mediatek.com
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 .../net/wireless/mediatek/mt76/mt7925/mcu.c   | 61 ++++++++++++++++++-
 .../wireless/mediatek/mt76/mt7925/mt7925.h    |  3 +
 2 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
index 8476f9caa98db..5b14bf434df36 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
@@ -616,6 +616,54 @@ int mt7925_mcu_uni_rx_ba(struct mt792x_dev *dev,
 	return ret;
 }
 
+static int mt7925_mcu_read_eeprom(struct mt792x_dev *dev, u32 offset, u8 *val)
+{
+	struct {
+		u8 rsv[4];
+
+		__le16 tag;
+		__le16 len;
+
+		__le32 addr;
+		__le32 valid;
+		u8 data[MT7925_EEPROM_BLOCK_SIZE];
+	} __packed req = {
+		.tag = cpu_to_le16(1),
+		.len = cpu_to_le16(sizeof(req) - 4),
+		.addr = cpu_to_le32(round_down(offset,
+				    MT7925_EEPROM_BLOCK_SIZE)),
+	};
+	struct evt {
+		u8 rsv[4];
+
+		__le16 tag;
+		__le16 len;
+
+		__le32 ver;
+		__le32 addr;
+		__le32 valid;
+		__le32 size;
+		__le32 magic_num;
+		__le32 type;
+		__le32 rsv1[4];
+		u8 data[32];
+	} __packed *res;
+	struct sk_buff *skb;
+	int ret;
+
+	ret = mt76_mcu_send_and_get_msg(&dev->mt76, MCU_WM_UNI_CMD_QUERY(EFUSE_CTRL),
+					&req, sizeof(req), true, &skb);
+	if (ret)
+		return ret;
+
+	res = (struct evt *)skb->data;
+	*val = res->data[offset % MT7925_EEPROM_BLOCK_SIZE];
+
+	dev_kfree_skb(skb);
+
+	return 0;
+}
+
 static int mt7925_load_clc(struct mt792x_dev *dev, const char *fw_name)
 {
 	const struct mt76_connac2_fw_trailer *hdr;
@@ -624,13 +672,20 @@ static int mt7925_load_clc(struct mt792x_dev *dev, const char *fw_name)
 	struct mt76_dev *mdev = &dev->mt76;
 	struct mt792x_phy *phy = &dev->phy;
 	const struct firmware *fw;
+	u8 *clc_base = NULL, hw_encap = 0;
 	int ret, i, len, offset = 0;
-	u8 *clc_base = NULL;
 
 	if (mt7925_disable_clc ||
 	    mt76_is_usb(&dev->mt76))
 		return 0;
 
+	if (mt76_is_mmio(&dev->mt76)) {
+		ret = mt7925_mcu_read_eeprom(dev, MT_EE_HW_TYPE, &hw_encap);
+		if (ret)
+			return ret;
+		hw_encap = u8_get_bits(hw_encap, MT_EE_HW_TYPE_ENCAP);
+	}
+
 	ret = request_firmware(&fw, fw_name, mdev->dev);
 	if (ret)
 		return ret;
@@ -675,6 +730,10 @@ static int mt7925_load_clc(struct mt792x_dev *dev, const char *fw_name)
 		if (phy->clc[clc->idx])
 			continue;
 
+		/* header content sanity */
+		if (u8_get_bits(clc->type, MT_EE_HW_TYPE_ENCAP) != hw_encap)
+			continue;
+
 		phy->clc[clc->idx] = devm_kmemdup(mdev->dev, clc,
 						  le32_to_cpu(clc->len),
 						  GFP_KERNEL);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h b/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
index df3c705d1cb3f..4ad779329b8f0 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
@@ -147,9 +147,12 @@ enum mt7925_eeprom_field {
 	MT_EE_CHIP_ID =		0x000,
 	MT_EE_VERSION =		0x002,
 	MT_EE_MAC_ADDR =	0x004,
+	MT_EE_HW_TYPE =		0xa71,
 	__MT_EE_MAX =		0x9ff
 };
 
+#define MT_EE_HW_TYPE_ENCAP     GENMASK(1, 0)
+
 enum {
 	TXPWR_USER,
 	TXPWR_EEPROM,
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:32:20 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:32:20 -0400
Subject: [PATCH AUTOSEL 6.12 064/486] wifi: mt76: mt7925: fix fails to enter low power mode in suspend state
In-Reply-To: <20250505223922.2682012-1-sashal@kernel.org>
References: <20250505223922.2682012-1-sashal@kernel.org>
Message-ID: <20250505223922.2682012-64-sashal@kernel.org>

From: Quan Zhou <quan.zhou at mediatek.com>

[ Upstream commit 2d5630b0c9466ac6549495828aa7dce7424a272a ]

The mt7925 sometimes fails to enter low power mode during suspend.
This is caused by the chip firmware sending an additional ACK event
to the host after processing the suspend command. Due to timing issues,
this event may not reach the host, causing the chip to get stuck.
To resolve this, the ACK flag in the suspend command is removed,
as it is not needed in the MT7925 architecture. This prevents the
firmware from sending the additional ACK event, ensuring the device
can reliably enter low power mode during suspend.

Signed-off-by: Quan Zhou <quan.zhou at mediatek.com>
Link: https://patch.msgid.link/d056938144a3a0336c3a4e3cec6f271899f32bf7.1736775666.git.quan.zhou at mediatek.com
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
index 5b14bf434df36..2396e1795fe17 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
@@ -3287,6 +3287,9 @@ int mt7925_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb,
 		else
 			uni_txd->option = MCU_CMD_UNI_EXT_ACK;
 
+		if (cmd == MCU_UNI_CMD(HIF_CTRL))
+			uni_txd->option &= ~MCU_CMD_ACK;
+
 		goto exit;
 	}
 
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:33:06 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:33:06 -0400
Subject: [PATCH AUTOSEL 6.12 110/486] ASoC: mediatek: mt6359: Add stub for mt6359_accdet_enable_jack_detect
In-Reply-To: <20250505223922.2682012-1-sashal@kernel.org>
References: <20250505223922.2682012-1-sashal@kernel.org>
Message-ID: <20250505223922.2682012-110-sashal@kernel.org>

From: N?colas F. R. A. Prado <nfraprado at collabora.com>

[ Upstream commit 0116a7d84b32537a10d9bea1fd1bfc06577ef527 ]

Add a stub for mt6359_accdet_enable_jack_detect() to prevent linker
failures in the machine sound drivers calling it when
CONFIG_SND_SOC_MT6359_ACCDET is not enabled.

Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
Link: https://patch.msgid.link/20250306-mt8188-accdet-v3-3-7828e835ff4b at collabora.com
Signed-off-by: Mark Brown <broonie at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 sound/soc/codecs/mt6359-accdet.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/sound/soc/codecs/mt6359-accdet.h b/sound/soc/codecs/mt6359-accdet.h
index c234f2f4276a1..78ada3a5bfae5 100644
--- a/sound/soc/codecs/mt6359-accdet.h
+++ b/sound/soc/codecs/mt6359-accdet.h
@@ -123,6 +123,15 @@ struct mt6359_accdet {
 	struct workqueue_struct *jd_workqueue;
 };
 
+#if IS_ENABLED(CONFIG_SND_SOC_MT6359_ACCDET)
 int mt6359_accdet_enable_jack_detect(struct snd_soc_component *component,
 				     struct snd_soc_jack *jack);
+#else
+static inline int
+mt6359_accdet_enable_jack_detect(struct snd_soc_component *component,
+				 struct snd_soc_jack *jack)
+{
+	return -EOPNOTSUPP;
+}
+#endif
 #endif
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:34:26 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:34:26 -0400
Subject: [PATCH AUTOSEL 6.12 190/486] soc: mediatek: mtk-mutex: Add DPI1 SOF/EOF to MT8188 mutex tables
In-Reply-To: <20250505223922.2682012-1-sashal@kernel.org>
References: <20250505223922.2682012-1-sashal@kernel.org>
Message-ID: <20250505223922.2682012-190-sashal@kernel.org>

From: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

[ Upstream commit 694e0b7c1747603243da874de9cbbf8cb806ca44 ]

MT8188 uses DPI1 to output to the HDMI controller: add the
Start of Frame and End of Frame configuration for the DPI1
IP to the tables to unblock generation and sending of these
signals to the GCE.

Link: https://lore.kernel.org/r/20250212100012.33001-2-angelogioacchino.delregno at collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/soc/mediatek/mtk-mutex.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 5250c1d702eb9..aaa965d4b050a 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -155,6 +155,7 @@
 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3	23
 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4	24
 #define MT8188_MUTEX_MOD_DISP1_DISP_MIXER	30
+#define MT8188_MUTEX_MOD_DISP1_DPI1		38
 #define MT8188_MUTEX_MOD_DISP1_DP_INTF1		39
 
 #define MT8195_MUTEX_MOD_DISP_OVL0		0
@@ -289,6 +290,7 @@
 #define MT8188_MUTEX_SOF_DSI0			1
 #define MT8188_MUTEX_SOF_DP_INTF0		3
 #define MT8188_MUTEX_SOF_DP_INTF1		4
+#define MT8188_MUTEX_SOF_DPI1			5
 #define MT8195_MUTEX_SOF_DSI0			1
 #define MT8195_MUTEX_SOF_DSI1			2
 #define MT8195_MUTEX_SOF_DP_INTF0		3
@@ -301,6 +303,7 @@
 #define MT8188_MUTEX_EOF_DSI0			(MT8188_MUTEX_SOF_DSI0 << 7)
 #define MT8188_MUTEX_EOF_DP_INTF0		(MT8188_MUTEX_SOF_DP_INTF0 << 7)
 #define MT8188_MUTEX_EOF_DP_INTF1		(MT8188_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8188_MUTEX_EOF_DPI1			(MT8188_MUTEX_SOF_DPI1 << 7)
 #define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)
 #define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)
 #define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)
@@ -472,6 +475,7 @@ static const u8 mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
 	[DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
 	[DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
+	[DDP_COMPONENT_DPI1] = MT8188_MUTEX_MOD_DISP1_DPI1,
 	[DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
 	[DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
 	[DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
@@ -686,6 +690,8 @@ static const u16 mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] =
 		MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
+	[MUTEX_SOF_DPI1] =
+		MT8188_MUTEX_SOF_DPI1 | MT8188_MUTEX_EOF_DPI1,
 	[MUTEX_SOF_DP_INTF0] =
 		MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
 	[MUTEX_SOF_DP_INTF1] =
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:35:02 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:35:02 -0400
Subject: [PATCH AUTOSEL 6.12 226/486] drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence
In-Reply-To: <20250505223922.2682012-1-sashal@kernel.org>
References: <20250505223922.2682012-1-sashal@kernel.org>
Message-ID: <20250505223922.2682012-226-sashal@kernel.org>

From: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

[ Upstream commit 8c9da7cd0bbcc90ab444454fecf535320456a312 ]

In preparation for adding support for newer DPI instances which
do support direct-pin but do not have any H_FRE_CON register,
like the one found in MT8195 and MT8188, add a branch to check
if the reg_h_fre_con variable was declared in the mtk_dpi_conf
structure for the probed SoC DPI version.

As a note, this is useful specifically only for cases in which
the support_direct_pin variable is true, so mt8195-dpintf is
not affected by any issue.

Reviewed-by: CK Hu <ck.hu at mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-6-angelogioacchino.delregno at collabora.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 9c11d3158324c..20a50180d4d49 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -410,12 +410,13 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
 
 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 {
-	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
+	if (dpi->conf->reg_h_fre_con)
+		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
 {
-	if (dpi->conf->edge_sel_en)
+	if (dpi->conf->edge_sel_en && dpi->conf->reg_h_fre_con)
 		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
 }
 
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:35:20 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:35:20 -0400
Subject: [PATCH AUTOSEL 6.12 244/486] net: ethernet: mtk_ppe_offload: Allow QinQ, double ETH_P_8021Q only
In-Reply-To: <20250505223922.2682012-1-sashal@kernel.org>
References: <20250505223922.2682012-1-sashal@kernel.org>
Message-ID: <20250505223922.2682012-244-sashal@kernel.org>

From: Eric Woudstra <ericwouds at gmail.com>

[ Upstream commit 7fe0353606d77a32c4c7f2814833dd1c043ebdd2 ]

mtk_foe_entry_set_vlan() in mtk_ppe.c already supports double vlan
tagging, but mtk_flow_offload_replace() in mtk_ppe_offload.c only allows
for 1 vlan tag, optionally in combination with pppoe and dsa tags.

However, mtk_foe_entry_set_vlan() only allows for setting the vlan id.
The protocol cannot be set, it is always ETH_P_8021Q, for inner and outer
tag. This patch adds QinQ support to mtk_flow_offload_replace(), only in
the case that both inner and outer tags are ETH_P_8021Q.

Only PPPoE-in-Q (as before) and Q-in-Q are allowed. A combination
of PPPoE and Q-in-Q is not allowed.

Signed-off-by: Eric Woudstra <ericwouds at gmail.com>
Link: https://patch.msgid.link/20250225201509.20843-1-ericwouds at gmail.com
Signed-off-by: Paolo Abeni <pabeni at redhat.com>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 .../net/ethernet/mediatek/mtk_ppe_offload.c   | 22 +++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
index f20bb390df3ad..c855fb799ce14 100644
--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
@@ -34,8 +34,10 @@ struct mtk_flow_data {
 	u16 vlan_in;
 
 	struct {
-		u16 id;
-		__be16 proto;
+		struct {
+			u16 id;
+			__be16 proto;
+		} vlans[2];
 		u8 num;
 	} vlan;
 	struct {
@@ -349,18 +351,19 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f,
 		case FLOW_ACTION_CSUM:
 			break;
 		case FLOW_ACTION_VLAN_PUSH:
-			if (data.vlan.num == 1 ||
+			if (data.vlan.num + data.pppoe.num == 2 ||
 			    act->vlan.proto != htons(ETH_P_8021Q))
 				return -EOPNOTSUPP;
 
-			data.vlan.id = act->vlan.vid;
-			data.vlan.proto = act->vlan.proto;
+			data.vlan.vlans[data.vlan.num].id = act->vlan.vid;
+			data.vlan.vlans[data.vlan.num].proto = act->vlan.proto;
 			data.vlan.num++;
 			break;
 		case FLOW_ACTION_VLAN_POP:
 			break;
 		case FLOW_ACTION_PPPOE_PUSH:
-			if (data.pppoe.num == 1)
+			if (data.pppoe.num == 1 ||
+			    data.vlan.num == 2)
 				return -EOPNOTSUPP;
 
 			data.pppoe.sid = act->pppoe.sid;
@@ -450,12 +453,9 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f,
 	if (offload_type == MTK_PPE_PKT_TYPE_BRIDGE)
 		foe.bridge.vlan = data.vlan_in;
 
-	if (data.vlan.num == 1) {
-		if (data.vlan.proto != htons(ETH_P_8021Q))
-			return -EOPNOTSUPP;
+	for (i = 0; i < data.vlan.num; i++)
+		mtk_foe_entry_set_vlan(eth, &foe, data.vlan.vlans[i].id);
 
-		mtk_foe_entry_set_vlan(eth, &foe, data.vlan.id);
-	}
 	if (data.pppoe.num == 1)
 		mtk_foe_entry_set_pppoe(eth, &foe, data.pppoe.sid);
 
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:35:31 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:35:31 -0400
Subject: [PATCH AUTOSEL 6.12 255/486] ASoC: mediatek: mt8188: Treat DMIC_GAINx_CUR as non-volatile
In-Reply-To: <20250505223922.2682012-1-sashal@kernel.org>
References: <20250505223922.2682012-1-sashal@kernel.org>
Message-ID: <20250505223922.2682012-255-sashal@kernel.org>

From: N?colas F. R. A. Prado <nfraprado at collabora.com>

[ Upstream commit 7d87bde21c73731ddaf15e572020f80999c38ee3 ]

The DMIC_GAINx_CUR registers contain the current (as in present) gain of
each DMIC. During capture, this gain will ramp up until a target value
is reached, and therefore the register is volatile since it is updated
automatically by hardware.

However, after capture the register's value returns to the value that
was written to it. So reading these registers returns the current gain,
and writing configures the initial gain for every capture.

>From an audio configuration perspective, reading the instantaneous gain
is not really useful. Instead, reading back the initial gain that was
configured is the desired behavior. For that reason, consider the
DMIC_GAINx_CUR registers as non-volatile, so the regmap's cache can be
used to retrieve the values, rather than requiring pm runtime resuming
the device.

Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Link: https://patch.msgid.link/20250225-genio700-dmic-v2-3-3076f5b50ef7 at collabora.com
Signed-off-by: Mark Brown <broonie at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 sound/soc/mediatek/mt8188/mt8188-afe-pcm.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c b/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
index 73e5c63aeec87..d36520c6272dd 100644
--- a/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
@@ -2855,10 +2855,6 @@ static bool mt8188_is_volatile_reg(struct device *dev, unsigned int reg)
 	case AFE_DMIC3_SRC_DEBUG_MON0:
 	case AFE_DMIC3_UL_SRC_MON0:
 	case AFE_DMIC3_UL_SRC_MON1:
-	case DMIC_GAIN1_CUR:
-	case DMIC_GAIN2_CUR:
-	case DMIC_GAIN3_CUR:
-	case DMIC_GAIN4_CUR:
 	case ETDM_IN1_MONITOR:
 	case ETDM_IN2_MONITOR:
 	case ETDM_OUT1_MONITOR:
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:35:32 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:35:32 -0400
Subject: [PATCH AUTOSEL 6.12 256/486] ASoC: mediatek: mt8188: Add reference for dmic clocks
In-Reply-To: <20250505223922.2682012-1-sashal@kernel.org>
References: <20250505223922.2682012-1-sashal@kernel.org>
Message-ID: <20250505223922.2682012-256-sashal@kernel.org>

From: N?colas F. R. A. Prado <nfraprado at collabora.com>

[ Upstream commit bf1800073f4d55f08191b034c86b95881e99b6fd ]

Add the names for the dmic clocks, aud_afe_dmic* and aud_dmic_hires*, so
they can be acquired and enabled by the platform driver.

Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Link: https://patch.msgid.link/20250225-genio700-dmic-v2-2-3076f5b50ef7 at collabora.com
Signed-off-by: Mark Brown <broonie at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 sound/soc/mediatek/mt8188/mt8188-afe-clk.c | 8 ++++++++
 sound/soc/mediatek/mt8188/mt8188-afe-clk.h | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
index e69c1bb2cb239..7f411b8577823 100644
--- a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
@@ -58,7 +58,15 @@ static const char *aud_clks[MT8188_CLK_NUM] = {
 	[MT8188_CLK_AUD_ADC] = "aud_adc",
 	[MT8188_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
 	[MT8188_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
+	[MT8188_CLK_AUD_AFE_DMIC1] = "aud_afe_dmic1",
+	[MT8188_CLK_AUD_AFE_DMIC2] = "aud_afe_dmic2",
+	[MT8188_CLK_AUD_AFE_DMIC3] = "aud_afe_dmic3",
+	[MT8188_CLK_AUD_AFE_DMIC4] = "aud_afe_dmic4",
 	[MT8188_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
+	[MT8188_CLK_AUD_DMIC_HIRES1] = "aud_dmic_hires1",
+	[MT8188_CLK_AUD_DMIC_HIRES2] = "aud_dmic_hires2",
+	[MT8188_CLK_AUD_DMIC_HIRES3] = "aud_dmic_hires3",
+	[MT8188_CLK_AUD_DMIC_HIRES4] = "aud_dmic_hires4",
 	[MT8188_CLK_AUD_I2SIN] = "aud_i2sin",
 	[MT8188_CLK_AUD_TDM_IN] = "aud_tdm_in",
 	[MT8188_CLK_AUD_I2S_OUT] = "aud_i2s_out",
diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-clk.h b/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
index ec53c171c170a..c6c78d684f3ee 100644
--- a/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
@@ -54,7 +54,15 @@ enum {
 	MT8188_CLK_AUD_ADC,
 	MT8188_CLK_AUD_DAC_HIRES,
 	MT8188_CLK_AUD_A1SYS_HP,
+	MT8188_CLK_AUD_AFE_DMIC1,
+	MT8188_CLK_AUD_AFE_DMIC2,
+	MT8188_CLK_AUD_AFE_DMIC3,
+	MT8188_CLK_AUD_AFE_DMIC4,
 	MT8188_CLK_AUD_ADC_HIRES,
+	MT8188_CLK_AUD_DMIC_HIRES1,
+	MT8188_CLK_AUD_DMIC_HIRES2,
+	MT8188_CLK_AUD_DMIC_HIRES3,
+	MT8188_CLK_AUD_DMIC_HIRES4,
 	MT8188_CLK_AUD_I2SIN,
 	MT8188_CLK_AUD_TDM_IN,
 	MT8188_CLK_AUD_I2S_OUT,
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:52:19 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:52:19 -0400
Subject: [PATCH AUTOSEL 6.6 039/294] wifi: mt76: mt7996: revise TXS size
In-Reply-To: <20250505225634.2688578-1-sashal@kernel.org>
References: <20250505225634.2688578-1-sashal@kernel.org>
Message-ID: <20250505225634.2688578-39-sashal@kernel.org>

From: Benjamin Lin <benjamin-jw.lin at mediatek.com>

[ Upstream commit 593c829b4326f7b3b15a69e97c9044ecbad3c319 ]

Size of MPDU/PPDU TXS is 12 DWs.
In mt7996/mt7992, last 4 DWs are reserved, so TXS size was mistakenly
considered to be 8 DWs. However, in mt7990, 9th DW of TXS starts to be used.

Signed-off-by: Benjamin Lin <benjamin-jw.lin at mediatek.com>
Link: https://patch.msgid.link/20250311103646.43346-1-nbd at nbd.name
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h | 3 +++
 drivers/net/wireless/mediatek/mt76/mt7996/mac.c       | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h b/drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h
index 87bfa441a9374..4979012d5abfa 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h
@@ -280,6 +280,9 @@ enum tx_mgnt_type {
 #define MT_TXFREE_INFO_COUNT		GENMASK(27, 24)
 #define MT_TXFREE_INFO_STAT		GENMASK(29, 28)
 
+#define MT_TXS_HDR_SIZE			4 /* Unit: DW */
+#define MT_TXS_SIZE			12 /* Unit: DW */
+
 #define MT_TXS0_BW			GENMASK(31, 29)
 #define MT_TXS0_TID			GENMASK(28, 26)
 #define MT_TXS0_AMPDU			BIT(25)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
index 73d46ec1181ae..35d9673ec0d8f 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
@@ -1354,7 +1354,7 @@ bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len)
 		mt7996_mac_tx_free(dev, data, len);
 		return false;
 	case PKT_TYPE_TXS:
-		for (rxd += 4; rxd + 8 <= end; rxd += 8)
+		for (rxd += MT_TXS_HDR_SIZE; rxd + MT_TXS_SIZE <= end; rxd += MT_TXS_SIZE)
 			mt7996_mac_add_txs(dev, rxd);
 		return false;
 	case PKT_TYPE_RX_FW_MONITOR:
@@ -1391,7 +1391,7 @@ void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
 		mt7996_mcu_rx_event(dev, skb);
 		break;
 	case PKT_TYPE_TXS:
-		for (rxd += 4; rxd + 8 <= end; rxd += 8)
+		for (rxd += MT_TXS_HDR_SIZE; rxd + MT_TXS_SIZE <= end; rxd += MT_TXS_SIZE)
 			mt7996_mac_add_txs(dev, rxd);
 		dev_kfree_skb(skb);
 		break;
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:52:18 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:52:18 -0400
Subject: [PATCH AUTOSEL 6.6 038/294] wifi: mt76: only mark tx-status-failed frames as ACKed on mt76x0/2
In-Reply-To: <20250505225634.2688578-1-sashal@kernel.org>
References: <20250505225634.2688578-1-sashal@kernel.org>
Message-ID: <20250505225634.2688578-38-sashal@kernel.org>

From: Felix Fietkau <nbd at nbd.name>

[ Upstream commit 0c5a89ceddc1728a40cb3313948401dd70e3c649 ]

The interrupt status polling is unreliable, which can cause status events
to get lost. On all newer chips, txs-timeout is an indication that the
packet was either never sent, or never acked.
Fixes issues with inactivity polling.

Link: https://patch.msgid.link/20250311103646.43346-6-nbd at nbd.name
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/mediatek/mt76/mt76.h       | 1 +
 drivers/net/wireless/mediatek/mt76/mt76x0/pci.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/mt76x2/pci.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/mt76x2/usb.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/tx.c         | 3 ++-
 6 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt76.h b/drivers/net/wireless/mediatek/mt76/mt76.h
index 8b620d4fed439..df0ea638370b5 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76.h
@@ -439,6 +439,7 @@ struct mt76_hw_cap {
 #define MT_DRV_RX_DMA_HDR		BIT(3)
 #define MT_DRV_HW_MGMT_TXQ		BIT(4)
 #define MT_DRV_AMSDU_OFFLOAD		BIT(5)
+#define MT_DRV_IGNORE_TXS_FAILED	BIT(6)
 
 struct mt76_driver_ops {
 	u32 drv_flags;
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c b/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
index 9277ff38b7a22..57ae362dad50b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
@@ -152,7 +152,8 @@ mt76x0e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	static const struct mt76_driver_ops drv_ops = {
 		.txwi_size = sizeof(struct mt76x02_txwi),
 		.drv_flags = MT_DRV_TX_ALIGNED4_SKBS |
-			     MT_DRV_SW_RX_AIRTIME,
+			     MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.tx_prepare_skb = mt76x02_tx_prepare_skb,
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c b/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c
index 0422c332354a1..520fd46227a7b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c
@@ -210,7 +210,8 @@ static int mt76x0u_probe(struct usb_interface *usb_intf,
 			 const struct usb_device_id *id)
 {
 	static const struct mt76_driver_ops drv_ops = {
-		.drv_flags = MT_DRV_SW_RX_AIRTIME,
+		.drv_flags = MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.tx_prepare_skb = mt76x02u_tx_prepare_skb,
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c b/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
index df85ebc6e1df0..7e2475b3c278e 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
@@ -22,7 +22,8 @@ mt76x2e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	static const struct mt76_driver_ops drv_ops = {
 		.txwi_size = sizeof(struct mt76x02_txwi),
 		.drv_flags = MT_DRV_TX_ALIGNED4_SKBS |
-			     MT_DRV_SW_RX_AIRTIME,
+			     MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.tx_prepare_skb = mt76x02_tx_prepare_skb,
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c b/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c
index d804309992196..70d3895762b4c 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c
@@ -29,7 +29,8 @@ static int mt76x2u_probe(struct usb_interface *intf,
 			 const struct usb_device_id *id)
 {
 	static const struct mt76_driver_ops drv_ops = {
-		.drv_flags = MT_DRV_SW_RX_AIRTIME,
+		.drv_flags = MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.tx_prepare_skb = mt76x02u_tx_prepare_skb,
diff --git a/drivers/net/wireless/mediatek/mt76/tx.c b/drivers/net/wireless/mediatek/mt76/tx.c
index 1809b03292c3d..47cdccdbed6aa 100644
--- a/drivers/net/wireless/mediatek/mt76/tx.c
+++ b/drivers/net/wireless/mediatek/mt76/tx.c
@@ -100,7 +100,8 @@ __mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, u8 flags,
 		return;
 
 	/* Tx status can be unreliable. if it fails, mark the frame as ACKed */
-	if (flags & MT_TX_CB_TXS_FAILED) {
+	if (flags & MT_TX_CB_TXS_FAILED &&
+	    (dev->drv->drv_flags & MT_DRV_IGNORE_TXS_FAILED)) {
 		info->status.rates[0].count = 0;
 		info->status.rates[0].idx = -1;
 		info->flags |= IEEE80211_TX_STAT_ACK;
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:52:47 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:52:47 -0400
Subject: [PATCH AUTOSEL 6.6 067/294] ASoC: mediatek: mt6359: Add stub for mt6359_accdet_enable_jack_detect
In-Reply-To: <20250505225634.2688578-1-sashal@kernel.org>
References: <20250505225634.2688578-1-sashal@kernel.org>
Message-ID: <20250505225634.2688578-67-sashal@kernel.org>

From: N?colas F. R. A. Prado <nfraprado at collabora.com>

[ Upstream commit 0116a7d84b32537a10d9bea1fd1bfc06577ef527 ]

Add a stub for mt6359_accdet_enable_jack_detect() to prevent linker
failures in the machine sound drivers calling it when
CONFIG_SND_SOC_MT6359_ACCDET is not enabled.

Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
Link: https://patch.msgid.link/20250306-mt8188-accdet-v3-3-7828e835ff4b at collabora.com
Signed-off-by: Mark Brown <broonie at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 sound/soc/codecs/mt6359-accdet.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/sound/soc/codecs/mt6359-accdet.h b/sound/soc/codecs/mt6359-accdet.h
index c234f2f4276a1..78ada3a5bfae5 100644
--- a/sound/soc/codecs/mt6359-accdet.h
+++ b/sound/soc/codecs/mt6359-accdet.h
@@ -123,6 +123,15 @@ struct mt6359_accdet {
 	struct workqueue_struct *jd_workqueue;
 };
 
+#if IS_ENABLED(CONFIG_SND_SOC_MT6359_ACCDET)
 int mt6359_accdet_enable_jack_detect(struct snd_soc_component *component,
 				     struct snd_soc_jack *jack);
+#else
+static inline int
+mt6359_accdet_enable_jack_detect(struct snd_soc_component *component,
+				 struct snd_soc_jack *jack)
+{
+	return -EOPNOTSUPP;
+}
+#endif
 #endif
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:53:54 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:53:54 -0400
Subject: [PATCH AUTOSEL 6.6 134/294] drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence
In-Reply-To: <20250505225634.2688578-1-sashal@kernel.org>
References: <20250505225634.2688578-1-sashal@kernel.org>
Message-ID: <20250505225634.2688578-134-sashal@kernel.org>

From: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

[ Upstream commit 8c9da7cd0bbcc90ab444454fecf535320456a312 ]

In preparation for adding support for newer DPI instances which
do support direct-pin but do not have any H_FRE_CON register,
like the one found in MT8195 and MT8188, add a branch to check
if the reg_h_fre_con variable was declared in the mtk_dpi_conf
structure for the probed SoC DPI version.

As a note, this is useful specifically only for cases in which
the support_direct_pin variable is true, so mt8195-dpintf is
not affected by any issue.

Reviewed-by: CK Hu <ck.hu at mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-6-angelogioacchino.delregno at collabora.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 54fc3f819577e..6391afdf202e2 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -410,12 +410,13 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
 
 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 {
-	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
+	if (dpi->conf->reg_h_fre_con)
+		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
 {
-	if (dpi->conf->edge_sel_en)
+	if (dpi->conf->edge_sel_en && dpi->conf->reg_h_fre_con)
 		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
 }
 
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:54:08 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:54:08 -0400
Subject: [PATCH AUTOSEL 6.6 148/294] net: ethernet: mtk_ppe_offload: Allow QinQ, double ETH_P_8021Q only
In-Reply-To: <20250505225634.2688578-1-sashal@kernel.org>
References: <20250505225634.2688578-1-sashal@kernel.org>
Message-ID: <20250505225634.2688578-148-sashal@kernel.org>

From: Eric Woudstra <ericwouds at gmail.com>

[ Upstream commit 7fe0353606d77a32c4c7f2814833dd1c043ebdd2 ]

mtk_foe_entry_set_vlan() in mtk_ppe.c already supports double vlan
tagging, but mtk_flow_offload_replace() in mtk_ppe_offload.c only allows
for 1 vlan tag, optionally in combination with pppoe and dsa tags.

However, mtk_foe_entry_set_vlan() only allows for setting the vlan id.
The protocol cannot be set, it is always ETH_P_8021Q, for inner and outer
tag. This patch adds QinQ support to mtk_flow_offload_replace(), only in
the case that both inner and outer tags are ETH_P_8021Q.

Only PPPoE-in-Q (as before) and Q-in-Q are allowed. A combination
of PPPoE and Q-in-Q is not allowed.

Signed-off-by: Eric Woudstra <ericwouds at gmail.com>
Link: https://patch.msgid.link/20250225201509.20843-1-ericwouds at gmail.com
Signed-off-by: Paolo Abeni <pabeni at redhat.com>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 .../net/ethernet/mediatek/mtk_ppe_offload.c   | 22 +++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
index a4efbeb162084..889fd26843e60 100644
--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
@@ -34,8 +34,10 @@ struct mtk_flow_data {
 	u16 vlan_in;
 
 	struct {
-		u16 id;
-		__be16 proto;
+		struct {
+			u16 id;
+			__be16 proto;
+		} vlans[2];
 		u8 num;
 	} vlan;
 	struct {
@@ -330,18 +332,19 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f,
 		case FLOW_ACTION_CSUM:
 			break;
 		case FLOW_ACTION_VLAN_PUSH:
-			if (data.vlan.num == 1 ||
+			if (data.vlan.num + data.pppoe.num == 2 ||
 			    act->vlan.proto != htons(ETH_P_8021Q))
 				return -EOPNOTSUPP;
 
-			data.vlan.id = act->vlan.vid;
-			data.vlan.proto = act->vlan.proto;
+			data.vlan.vlans[data.vlan.num].id = act->vlan.vid;
+			data.vlan.vlans[data.vlan.num].proto = act->vlan.proto;
 			data.vlan.num++;
 			break;
 		case FLOW_ACTION_VLAN_POP:
 			break;
 		case FLOW_ACTION_PPPOE_PUSH:
-			if (data.pppoe.num == 1)
+			if (data.pppoe.num == 1 ||
+			    data.vlan.num == 2)
 				return -EOPNOTSUPP;
 
 			data.pppoe.sid = act->pppoe.sid;
@@ -431,12 +434,9 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f,
 	if (offload_type == MTK_PPE_PKT_TYPE_BRIDGE)
 		foe.bridge.vlan = data.vlan_in;
 
-	if (data.vlan.num == 1) {
-		if (data.vlan.proto != htons(ETH_P_8021Q))
-			return -EOPNOTSUPP;
+	for (i = 0; i < data.vlan.num; i++)
+		mtk_foe_entry_set_vlan(eth, &foe, data.vlan.vlans[i].id);
 
-		mtk_foe_entry_set_vlan(eth, &foe, data.vlan.id);
-	}
 	if (data.pppoe.num == 1)
 		mtk_foe_entry_set_pppoe(eth, &foe, data.pppoe.sid);
 
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:54:17 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:54:17 -0400
Subject: [PATCH AUTOSEL 6.6 157/294] ASoC: mediatek: mt8188: Treat DMIC_GAINx_CUR as non-volatile
In-Reply-To: <20250505225634.2688578-1-sashal@kernel.org>
References: <20250505225634.2688578-1-sashal@kernel.org>
Message-ID: <20250505225634.2688578-157-sashal@kernel.org>

From: N?colas F. R. A. Prado <nfraprado at collabora.com>

[ Upstream commit 7d87bde21c73731ddaf15e572020f80999c38ee3 ]

The DMIC_GAINx_CUR registers contain the current (as in present) gain of
each DMIC. During capture, this gain will ramp up until a target value
is reached, and therefore the register is volatile since it is updated
automatically by hardware.

However, after capture the register's value returns to the value that
was written to it. So reading these registers returns the current gain,
and writing configures the initial gain for every capture.

>From an audio configuration perspective, reading the instantaneous gain
is not really useful. Instead, reading back the initial gain that was
configured is the desired behavior. For that reason, consider the
DMIC_GAINx_CUR registers as non-volatile, so the regmap's cache can be
used to retrieve the values, rather than requiring pm runtime resuming
the device.

Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Link: https://patch.msgid.link/20250225-genio700-dmic-v2-3-3076f5b50ef7 at collabora.com
Signed-off-by: Mark Brown <broonie at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 sound/soc/mediatek/mt8188/mt8188-afe-pcm.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c b/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
index 11f30b183520f..4a304bffef8ba 100644
--- a/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
@@ -2855,10 +2855,6 @@ static bool mt8188_is_volatile_reg(struct device *dev, unsigned int reg)
 	case AFE_DMIC3_SRC_DEBUG_MON0:
 	case AFE_DMIC3_UL_SRC_MON0:
 	case AFE_DMIC3_UL_SRC_MON1:
-	case DMIC_GAIN1_CUR:
-	case DMIC_GAIN2_CUR:
-	case DMIC_GAIN3_CUR:
-	case DMIC_GAIN4_CUR:
 	case ETDM_IN1_MONITOR:
 	case ETDM_IN2_MONITOR:
 	case ETDM_OUT1_MONITOR:
-- 
2.39.5



From sashal at kernel.org  Mon May  5 15:54:18 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 18:54:18 -0400
Subject: [PATCH AUTOSEL 6.6 158/294] ASoC: mediatek: mt8188: Add reference for dmic clocks
In-Reply-To: <20250505225634.2688578-1-sashal@kernel.org>
References: <20250505225634.2688578-1-sashal@kernel.org>
Message-ID: <20250505225634.2688578-158-sashal@kernel.org>

From: N?colas F. R. A. Prado <nfraprado at collabora.com>

[ Upstream commit bf1800073f4d55f08191b034c86b95881e99b6fd ]

Add the names for the dmic clocks, aud_afe_dmic* and aud_dmic_hires*, so
they can be acquired and enabled by the platform driver.

Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Link: https://patch.msgid.link/20250225-genio700-dmic-v2-2-3076f5b50ef7 at collabora.com
Signed-off-by: Mark Brown <broonie at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 sound/soc/mediatek/mt8188/mt8188-afe-clk.c | 8 ++++++++
 sound/soc/mediatek/mt8188/mt8188-afe-clk.h | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
index e69c1bb2cb239..7f411b8577823 100644
--- a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
@@ -58,7 +58,15 @@ static const char *aud_clks[MT8188_CLK_NUM] = {
 	[MT8188_CLK_AUD_ADC] = "aud_adc",
 	[MT8188_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
 	[MT8188_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
+	[MT8188_CLK_AUD_AFE_DMIC1] = "aud_afe_dmic1",
+	[MT8188_CLK_AUD_AFE_DMIC2] = "aud_afe_dmic2",
+	[MT8188_CLK_AUD_AFE_DMIC3] = "aud_afe_dmic3",
+	[MT8188_CLK_AUD_AFE_DMIC4] = "aud_afe_dmic4",
 	[MT8188_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
+	[MT8188_CLK_AUD_DMIC_HIRES1] = "aud_dmic_hires1",
+	[MT8188_CLK_AUD_DMIC_HIRES2] = "aud_dmic_hires2",
+	[MT8188_CLK_AUD_DMIC_HIRES3] = "aud_dmic_hires3",
+	[MT8188_CLK_AUD_DMIC_HIRES4] = "aud_dmic_hires4",
 	[MT8188_CLK_AUD_I2SIN] = "aud_i2sin",
 	[MT8188_CLK_AUD_TDM_IN] = "aud_tdm_in",
 	[MT8188_CLK_AUD_I2S_OUT] = "aud_i2s_out",
diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-clk.h b/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
index ec53c171c170a..c6c78d684f3ee 100644
--- a/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
@@ -54,7 +54,15 @@ enum {
 	MT8188_CLK_AUD_ADC,
 	MT8188_CLK_AUD_DAC_HIRES,
 	MT8188_CLK_AUD_A1SYS_HP,
+	MT8188_CLK_AUD_AFE_DMIC1,
+	MT8188_CLK_AUD_AFE_DMIC2,
+	MT8188_CLK_AUD_AFE_DMIC3,
+	MT8188_CLK_AUD_AFE_DMIC4,
 	MT8188_CLK_AUD_ADC_HIRES,
+	MT8188_CLK_AUD_DMIC_HIRES1,
+	MT8188_CLK_AUD_DMIC_HIRES2,
+	MT8188_CLK_AUD_DMIC_HIRES3,
+	MT8188_CLK_AUD_DMIC_HIRES4,
 	MT8188_CLK_AUD_I2SIN,
 	MT8188_CLK_AUD_TDM_IN,
 	MT8188_CLK_AUD_I2S_OUT,
-- 
2.39.5



From sashal at kernel.org  Mon May  5 16:03:46 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 19:03:46 -0400
Subject: [PATCH AUTOSEL 6.1 054/212] ASoC: mediatek: mt6359: Add stub for mt6359_accdet_enable_jack_detect
In-Reply-To: <20250505230624.2692522-1-sashal@kernel.org>
References: <20250505230624.2692522-1-sashal@kernel.org>
Message-ID: <20250505230624.2692522-54-sashal@kernel.org>

From: N?colas F. R. A. Prado <nfraprado at collabora.com>

[ Upstream commit 0116a7d84b32537a10d9bea1fd1bfc06577ef527 ]

Add a stub for mt6359_accdet_enable_jack_detect() to prevent linker
failures in the machine sound drivers calling it when
CONFIG_SND_SOC_MT6359_ACCDET is not enabled.

Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
Link: https://patch.msgid.link/20250306-mt8188-accdet-v3-3-7828e835ff4b at collabora.com
Signed-off-by: Mark Brown <broonie at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 sound/soc/codecs/mt6359-accdet.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/sound/soc/codecs/mt6359-accdet.h b/sound/soc/codecs/mt6359-accdet.h
index c234f2f4276a1..78ada3a5bfae5 100644
--- a/sound/soc/codecs/mt6359-accdet.h
+++ b/sound/soc/codecs/mt6359-accdet.h
@@ -123,6 +123,15 @@ struct mt6359_accdet {
 	struct workqueue_struct *jd_workqueue;
 };
 
+#if IS_ENABLED(CONFIG_SND_SOC_MT6359_ACCDET)
 int mt6359_accdet_enable_jack_detect(struct snd_soc_component *component,
 				     struct snd_soc_jack *jack);
+#else
+static inline int
+mt6359_accdet_enable_jack_detect(struct snd_soc_component *component,
+				 struct snd_soc_jack *jack)
+{
+	return -EOPNOTSUPP;
+}
+#endif
 #endif
-- 
2.39.5



From sashal at kernel.org  Mon May  5 16:04:38 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 19:04:38 -0400
Subject: [PATCH AUTOSEL 6.1 106/212] drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence
In-Reply-To: <20250505230624.2692522-1-sashal@kernel.org>
References: <20250505230624.2692522-1-sashal@kernel.org>
Message-ID: <20250505230624.2692522-106-sashal@kernel.org>

From: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

[ Upstream commit 8c9da7cd0bbcc90ab444454fecf535320456a312 ]

In preparation for adding support for newer DPI instances which
do support direct-pin but do not have any H_FRE_CON register,
like the one found in MT8195 and MT8188, add a branch to check
if the reg_h_fre_con variable was declared in the mtk_dpi_conf
structure for the probed SoC DPI version.

As a note, this is useful specifically only for cases in which
the support_direct_pin variable is true, so mt8195-dpintf is
not affected by any issue.

Reviewed-by: CK Hu <ck.hu at mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-6-angelogioacchino.delregno at collabora.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 1fa958e8c40a1..5ad9c384046cb 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -406,12 +406,13 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
 
 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 {
-	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
+	if (dpi->conf->reg_h_fre_con)
+		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
 {
-	if (dpi->conf->edge_sel_en)
+	if (dpi->conf->edge_sel_en && dpi->conf->reg_h_fre_con)
 		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
 }
 
-- 
2.39.5



From sashal at kernel.org  Mon May  5 16:04:50 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 19:04:50 -0400
Subject: [PATCH AUTOSEL 6.1 118/212] net: ethernet: mtk_ppe_offload: Allow QinQ, double ETH_P_8021Q only
In-Reply-To: <20250505230624.2692522-1-sashal@kernel.org>
References: <20250505230624.2692522-1-sashal@kernel.org>
Message-ID: <20250505230624.2692522-118-sashal@kernel.org>

From: Eric Woudstra <ericwouds at gmail.com>

[ Upstream commit 7fe0353606d77a32c4c7f2814833dd1c043ebdd2 ]

mtk_foe_entry_set_vlan() in mtk_ppe.c already supports double vlan
tagging, but mtk_flow_offload_replace() in mtk_ppe_offload.c only allows
for 1 vlan tag, optionally in combination with pppoe and dsa tags.

However, mtk_foe_entry_set_vlan() only allows for setting the vlan id.
The protocol cannot be set, it is always ETH_P_8021Q, for inner and outer
tag. This patch adds QinQ support to mtk_flow_offload_replace(), only in
the case that both inner and outer tags are ETH_P_8021Q.

Only PPPoE-in-Q (as before) and Q-in-Q are allowed. A combination
of PPPoE and Q-in-Q is not allowed.

Signed-off-by: Eric Woudstra <ericwouds at gmail.com>
Link: https://patch.msgid.link/20250225201509.20843-1-ericwouds at gmail.com
Signed-off-by: Paolo Abeni <pabeni at redhat.com>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 .../net/ethernet/mediatek/mtk_ppe_offload.c   | 22 +++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
index 6a72687d5b83f..8cb8d47227f51 100644
--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
@@ -34,8 +34,10 @@ struct mtk_flow_data {
 	u16 vlan_in;
 
 	struct {
-		u16 id;
-		__be16 proto;
+		struct {
+			u16 id;
+			__be16 proto;
+		} vlans[2];
 		u8 num;
 	} vlan;
 	struct {
@@ -321,18 +323,19 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f)
 		case FLOW_ACTION_CSUM:
 			break;
 		case FLOW_ACTION_VLAN_PUSH:
-			if (data.vlan.num == 1 ||
+			if (data.vlan.num + data.pppoe.num == 2 ||
 			    act->vlan.proto != htons(ETH_P_8021Q))
 				return -EOPNOTSUPP;
 
-			data.vlan.id = act->vlan.vid;
-			data.vlan.proto = act->vlan.proto;
+			data.vlan.vlans[data.vlan.num].id = act->vlan.vid;
+			data.vlan.vlans[data.vlan.num].proto = act->vlan.proto;
 			data.vlan.num++;
 			break;
 		case FLOW_ACTION_VLAN_POP:
 			break;
 		case FLOW_ACTION_PPPOE_PUSH:
-			if (data.pppoe.num == 1)
+			if (data.pppoe.num == 1 ||
+			    data.vlan.num == 2)
 				return -EOPNOTSUPP;
 
 			data.pppoe.sid = act->pppoe.sid;
@@ -422,12 +425,9 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f)
 	if (offload_type == MTK_PPE_PKT_TYPE_BRIDGE)
 		foe.bridge.vlan = data.vlan_in;
 
-	if (data.vlan.num == 1) {
-		if (data.vlan.proto != htons(ETH_P_8021Q))
-			return -EOPNOTSUPP;
+	for (i = 0; i < data.vlan.num; i++)
+		mtk_foe_entry_set_vlan(eth, &foe, data.vlan.vlans[i].id);
 
-		mtk_foe_entry_set_vlan(eth, &foe, data.vlan.id);
-	}
 	if (data.pppoe.num == 1)
 		mtk_foe_entry_set_pppoe(eth, &foe, data.pppoe.sid);
 
-- 
2.39.5



From sashal at kernel.org  Mon May  5 16:11:08 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 19:11:08 -0400
Subject: [PATCH AUTOSEL 5.15 021/153] wifi: mt76: only mark tx-status-failed frames as ACKed on mt76x0/2
In-Reply-To: <20250505231320.2695319-1-sashal@kernel.org>
References: <20250505231320.2695319-1-sashal@kernel.org>
Message-ID: <20250505231320.2695319-21-sashal@kernel.org>

From: Felix Fietkau <nbd at nbd.name>

[ Upstream commit 0c5a89ceddc1728a40cb3313948401dd70e3c649 ]

The interrupt status polling is unreliable, which can cause status events
to get lost. On all newer chips, txs-timeout is an indication that the
packet was either never sent, or never acked.
Fixes issues with inactivity polling.

Link: https://patch.msgid.link/20250311103646.43346-6-nbd at nbd.name
Signed-off-by: Felix Fietkau <nbd at nbd.name>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/mediatek/mt76/mt76.h       | 1 +
 drivers/net/wireless/mediatek/mt76/mt76x0/pci.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/mt76x0/usb.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/mt76x2/pci.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/mt76x2/usb.c | 3 ++-
 drivers/net/wireless/mediatek/mt76/tx.c         | 3 ++-
 6 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt76.h b/drivers/net/wireless/mediatek/mt76/mt76.h
index 27f04fb2796d7..5a90fa556203f 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76.h
@@ -345,6 +345,7 @@ struct mt76_hw_cap {
 #define MT_DRV_RX_DMA_HDR		BIT(3)
 #define MT_DRV_HW_MGMT_TXQ		BIT(4)
 #define MT_DRV_AMSDU_OFFLOAD		BIT(5)
+#define MT_DRV_IGNORE_TXS_FAILED	BIT(6)
 
 struct mt76_driver_ops {
 	u32 drv_flags;
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c b/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
index b795e7245c075..3255f9c0ef71f 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
@@ -151,7 +151,8 @@ mt76x0e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	static const struct mt76_driver_ops drv_ops = {
 		.txwi_size = sizeof(struct mt76x02_txwi),
 		.drv_flags = MT_DRV_TX_ALIGNED4_SKBS |
-			     MT_DRV_SW_RX_AIRTIME,
+			     MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.tx_prepare_skb = mt76x02_tx_prepare_skb,
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c b/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c
index f2b2fa7338457..7a4d62bff28ff 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/usb.c
@@ -209,7 +209,8 @@ static int mt76x0u_probe(struct usb_interface *usb_intf,
 			 const struct usb_device_id *id)
 {
 	static const struct mt76_driver_ops drv_ops = {
-		.drv_flags = MT_DRV_SW_RX_AIRTIME,
+		.drv_flags = MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.tx_prepare_skb = mt76x02u_tx_prepare_skb,
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c b/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
index 5cd0379d86de8..4e369bd87c900 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
@@ -22,7 +22,8 @@ mt76x2e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	static const struct mt76_driver_ops drv_ops = {
 		.txwi_size = sizeof(struct mt76x02_txwi),
 		.drv_flags = MT_DRV_TX_ALIGNED4_SKBS |
-			     MT_DRV_SW_RX_AIRTIME,
+			     MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.tx_prepare_skb = mt76x02_tx_prepare_skb,
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c b/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c
index 9369515f36a3a..09b01e09bcfe0 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/usb.c
@@ -29,7 +29,8 @@ static int mt76x2u_probe(struct usb_interface *intf,
 			 const struct usb_device_id *id)
 {
 	static const struct mt76_driver_ops drv_ops = {
-		.drv_flags = MT_DRV_SW_RX_AIRTIME,
+		.drv_flags = MT_DRV_SW_RX_AIRTIME |
+			     MT_DRV_IGNORE_TXS_FAILED,
 		.survey_flags = SURVEY_INFO_TIME_TX,
 		.update_survey = mt76x02_update_channel,
 		.tx_prepare_skb = mt76x02u_tx_prepare_skb,
diff --git a/drivers/net/wireless/mediatek/mt76/tx.c b/drivers/net/wireless/mediatek/mt76/tx.c
index 134a735a06329..3fbf0153d13ca 100644
--- a/drivers/net/wireless/mediatek/mt76/tx.c
+++ b/drivers/net/wireless/mediatek/mt76/tx.c
@@ -93,7 +93,8 @@ __mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, u8 flags,
 	__skb_unlink(skb, &dev->status_list);
 
 	/* Tx status can be unreliable. if it fails, mark the frame as ACKed */
-	if (flags & MT_TX_CB_TXS_FAILED) {
+	if (flags & MT_TX_CB_TXS_FAILED &&
+	    (dev->drv->drv_flags & MT_DRV_IGNORE_TXS_FAILED)) {
 		info->status.rates[0].count = 0;
 		info->status.rates[0].idx = -1;
 		info->flags |= IEEE80211_TX_STAT_ACK;
-- 
2.39.5



From sashal at kernel.org  Mon May  5 16:11:26 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 19:11:26 -0400
Subject: [PATCH AUTOSEL 5.15 039/153] ASoC: mediatek: mt6359: Add stub for mt6359_accdet_enable_jack_detect
In-Reply-To: <20250505231320.2695319-1-sashal@kernel.org>
References: <20250505231320.2695319-1-sashal@kernel.org>
Message-ID: <20250505231320.2695319-39-sashal@kernel.org>

From: N?colas F. R. A. Prado <nfraprado at collabora.com>

[ Upstream commit 0116a7d84b32537a10d9bea1fd1bfc06577ef527 ]

Add a stub for mt6359_accdet_enable_jack_detect() to prevent linker
failures in the machine sound drivers calling it when
CONFIG_SND_SOC_MT6359_ACCDET is not enabled.

Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
Link: https://patch.msgid.link/20250306-mt8188-accdet-v3-3-7828e835ff4b at collabora.com
Signed-off-by: Mark Brown <broonie at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 sound/soc/codecs/mt6359-accdet.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/sound/soc/codecs/mt6359-accdet.h b/sound/soc/codecs/mt6359-accdet.h
index c234f2f4276a1..78ada3a5bfae5 100644
--- a/sound/soc/codecs/mt6359-accdet.h
+++ b/sound/soc/codecs/mt6359-accdet.h
@@ -123,6 +123,15 @@ struct mt6359_accdet {
 	struct workqueue_struct *jd_workqueue;
 };
 
+#if IS_ENABLED(CONFIG_SND_SOC_MT6359_ACCDET)
 int mt6359_accdet_enable_jack_detect(struct snd_soc_component *component,
 				     struct snd_soc_jack *jack);
+#else
+static inline int
+mt6359_accdet_enable_jack_detect(struct snd_soc_component *component,
+				 struct snd_soc_jack *jack)
+{
+	return -EOPNOTSUPP;
+}
+#endif
 #endif
-- 
2.39.5



From fossben at pm.me  Mon May  5 16:15:27 2025
From: fossben at pm.me (fossben at pm.me)
Date: Mon, 05 May 2025 23:15:27 +0000
Subject: [REGRESSION][BISECTED][STABLE] MT7925: mDNS and IPv6 broken in kernel 6.14.3 and above
In-Reply-To: <Q8fBN4506NOX9rrFspv9q0xuQRlE1YcHDbwfRUlXy7if-Lv-kGyIXPrNN2kOMoWENMYCfTmOhAhnSCs4gtUvpzEf0O_JZ_BV__V3B_A7iU8=@pm.me>
References: <EmWnO5b-acRH1TXbGnkx41eJw654vmCR-8_xMBaPMwexCnfkvKCdlU5u19CGbaapJ3KRu-l3B-tSUhf8CCQwL0odjo6Cd5YG5lvNeB-vfdg=@pm.me> <f73dec60b60dd7bb3be40c1feefbe223c7afe19b.camel@mediatek.com> <5ae1ef34c9844d6d0f5fb167dd596a4c43321367.camel@kernel.org> <28ef2cc608d071d1530902d7b5df045555ab5651.camel@mediatek.com> <Q8fBN4506NOX9rrFspv9q0xuQRlE1YcHDbwfRUlXy7if-Lv-kGyIXPrNN2kOMoWENMYCfTmOhAhnSCs4gtUvpzEf0O_JZ_BV__V3B_A7iU8=@pm.me>
Message-ID: <vCzHyPICbb61hk8jzrTcmvU7H9PJGenEtIAZaKQH9ofNUZPD4aOeD1i-oDl2G2CtieHoTnUWBWYy-uQhNwRo7sT5gj_uyFQs-zIkbCY-qZU=@pm.me>






On Monday, May 5th, 2025 at 3:20 AM, fossben at pm.me <fossben at pm.me> wrote:

> 
> 
> On Monday, May 5th, 2025 at 12:48 AM, Mingyen Hsieh Mingyen.Hsieh at mediatek.com wrote:
> 
> > On Sun, 2025-05-04 at 00:39 +0200, Niklas Schnelle wrote:
> > 
> > > External email : Please do not click links or open attachments until
> > > you have verified the sender or the content.
> > > 
> > > On Wed, 2025-04-30 at 06:47 +0000, Mingyen Hsieh (???) wrote:
> > > 
> > > > On Wed, 2025-04-30 at 01:14 +0000, fossben at pm.me wrote:
> > > > 
> > > > > External email : Please do not click links or open attachments
> > > > > until
> > > > > you have verified the sender or the content.
> > > > > 
> > > > > Hello all,
> > > > > 
> > > > > After upgrading to 6.14.3 on my PC with a MT7925 chip, I noticed
> > > > > that
> > > > > I could no longer ping *.local addresses provided by Avahi. In
> > > > > addition, I also noticed that I was not able to get a DHCP IPv6
> > > > > address from my router, no matter how many times I rebooted the
> > > > > router or reconnected with NetworkManager.
> > > > > 
> > > > > Reverting to 6.14.2 fixes both mDNS and IPv6 addresses
> > > > > immediately.
> > > > > Going back to 6.14.3 immediately breaks mDNS again, but the IPv6
> > > > > address will stay there for a while before disappearing later,
> > > > > possibly because the DHCP lease expired? I am not sure exactly
> > > > > when
> > > > > it stops working.
> > > > > 
> > > > > I've done a kernel bisect between 6.14.2 and 6.14.3 and found the
> > > > > offending commit that causes mDNS to fail:
> > > > > 
> > > > > commit 80007d3f92fd018d0a052a706400e976b36e3c87
> > > > > Author: Ming Yen Hsieh mingyen.hsieh at mediatek.com
> > > > > Date: Tue Mar 4 16:08:50 2025 -0800
> > > > > 
> > > > > wifi: mt76: mt7925: integrate *mlo_sta_cmd and *sta_cmd
> > > > > 
> > > > > commit cb1353ef34735ec1e5d9efa1fe966f05ff1dc1e1 upstream.
> > > > > 
> > > > > Integrate *mlo_sta_cmd and *sta_cmd for the MLO firmware.
> > > > > 
> > > > > Fixes: 86c051f2c418 ("wifi: mt76: mt7925: enabling MLO when
> > > > > the
> > > > > firmware supports it")
> > > > > 
> > > > > drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 59 ++++-------
> > > > > ----
> > > > > --------------------------------------------
> > > > > 1 file changed, 4 insertions(+), 55 deletions(-)
> > > > > 
> > > > > I do not know if this same commit is also causing the IPv6 issues
> > > > > as
> > > > > testing that requires quite a bit of time to reproduce. What I do
> > > > > know with certainty as of this moment is that it definitely
> > > > > breaks in
> > > > > kernel 6.14.3.
> > > > > 
> > > > > I've attached my hardware info as well as dmesg logs from the
> > > > > last
> > > > > working kernel from the bisect and 6.14.4 which exhibits the
> > > > > issue.
> > > > > Please let me know if there's any other info you need.
> > > > > 
> > > > > Thanks!
> > > > > Benjamin Xiao
> > > > 
> > > > Hi,
> > > > 
> > > > Thanks for reporting this issue, we will aim into this.
> > > > 
> > > > Can you provide me with your testing steps?
> > > > 
> > > > Best Regards,
> > > > Yen.
> > > 
> > > Hi Yan,
> > > 
> > > I see the same IPv6 issue on my Framework 13 (Ryzen 5 AI 340) with an
> > > mt7925e WiFI module. My setup is just a home router with native IPv6
> > > both for my uplink and in the LAN. The problems with IPv6 can already
> > > be seen just in the LAN for example by checking which IP was used for
> > > SSH, in my setup it should always be IPv6 but falls back to IPv4 in
> > > the
> > > broken state.
> > > 
> > > As another data point, I tried reverting cb1353ef3473 ("wifi: mt76:
> > > mt7925: integrate *mlo_sta_cmd and *sta_cmd") on top of 6.15.-rc4.
> > > This
> > > fully restores IPv6 for me. Also note I'm running this with the
> > > mt7925
> > > firmware version 20250425073330 from linux-firmware's master branch
> > > as
> > > I had some dropped connections with earlier firmware.
> > > 
> > > So it definitely looks like that commit also broke IPv6 and not just
> > > mDNS. Note that if if I use DHCPv6 instead of router advertisements,
> > > on
> > > the latest firmware, but without the revert, I get a global IPv6
> > > address added to the interface but then native IPv6 addresses are
> > > still
> > > uncreachable. With the offending patch reverted my SSH session to an
> > > IPv6 only host works fine and is stable. Also I'd be willing to test
> > > a
> > > proper fix as I rely on IPv6 heavily due to having to use CGNAT for
> > > IPv4 but not for IPv6.
> > > 
> > > Thanks,
> > > Niklas
> > 
> > Hi Benjamin & Niklas,
> > 
> > Can you help to try this patch? I can get IPv6 address through this
> > patch.
> > 
> > If it can work at your environment as well, i will upstream it and add
> > test tag with you.
> > 
> > diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > index a42b584634ab..fd756f0d18f8 100644
> > --- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > +++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > @@ -2183,14 +2183,14 @@ mt7925_mcu_sta_cmd(struct mt76_phy *phy,
> > mt7925_mcu_sta_mld_tlv(skb, info->vif, info-
> > 
> > > link_sta->sta);
> > > mt7925_mcu_sta_eht_mld_tlv(skb, info->vif,
> > > info->link_sta->sta);
> > > }
> > > -
> > > - mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info-
> > > link_sta);
> > > }
> > 
> > if (!info->enable) {
> > mt7925_mcu_sta_remove_tlv(skb);
> > mt76_connac_mcu_add_tlv(skb, STA_REC_MLD_OFF,
> > sizeof(struct tlv));
> > + } else {
> > + mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info-
> > 
> > > link_sta);
> > > }
> > 
> > return mt76_mcu_skb_send_msg(dev, skb, info->cmd, true);
> > 
> > Thanks~
> > Yen.
> 
> 
> Hi Yen,
> 
> I manually applied the changes on top of 6.14.5 and mDNS seems to work along with IPv6! I will do more testing for the rest of the day to see if the issue is completely fixed but so far looks good at least for the 5 minutes I've been testing it.
> 
> Thanks for the fix,
> Ben

I've now used 6.14.5 with the patch applied for most of the day and it's been working great! mDNS has been rock solid and so has IPv6.

Would appreciate it if this fix got backported to the 6.14 series!

Ben


From sashal at kernel.org  Mon May  5 16:12:04 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 19:12:04 -0400
Subject: [PATCH AUTOSEL 5.15 077/153] drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence
In-Reply-To: <20250505231320.2695319-1-sashal@kernel.org>
References: <20250505231320.2695319-1-sashal@kernel.org>
Message-ID: <20250505231320.2695319-77-sashal@kernel.org>

From: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

[ Upstream commit 8c9da7cd0bbcc90ab444454fecf535320456a312 ]

In preparation for adding support for newer DPI instances which
do support direct-pin but do not have any H_FRE_CON register,
like the one found in MT8195 and MT8188, add a branch to check
if the reg_h_fre_con variable was declared in the mtk_dpi_conf
structure for the probed SoC DPI version.

As a note, this is useful specifically only for cases in which
the support_direct_pin variable is true, so mt8195-dpintf is
not affected by any issue.

Reviewed-by: CK Hu <ck.hu at mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-6-angelogioacchino.delregno at collabora.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 9518672dc21b3..3f39109b69154 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -346,12 +346,13 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
 
 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 {
-	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
+	if (dpi->conf->reg_h_fre_con)
+		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
 {
-	if (dpi->conf->edge_sel_en)
+	if (dpi->conf->edge_sel_en && dpi->conf->reg_h_fre_con)
 		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
 }
 
-- 
2.39.5



From sashal at kernel.org  Mon May  5 16:17:18 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 19:17:18 -0400
Subject: [PATCH AUTOSEL 5.10 055/114] drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence
In-Reply-To: <20250505231817.2697367-1-sashal@kernel.org>
References: <20250505231817.2697367-1-sashal@kernel.org>
Message-ID: <20250505231817.2697367-55-sashal@kernel.org>

From: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

[ Upstream commit 8c9da7cd0bbcc90ab444454fecf535320456a312 ]

In preparation for adding support for newer DPI instances which
do support direct-pin but do not have any H_FRE_CON register,
like the one found in MT8195 and MT8188, add a branch to check
if the reg_h_fre_con variable was declared in the mtk_dpi_conf
structure for the probed SoC DPI version.

As a note, this is useful specifically only for cases in which
the support_direct_pin variable is true, so mt8195-dpintf is
not affected by any issue.

Reviewed-by: CK Hu <ck.hu at mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-6-angelogioacchino.delregno at collabora.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ac75c10aed2f6..3a58d3dfd558f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -340,12 +340,13 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
 
 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 {
-	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
+	if (dpi->conf->reg_h_fre_con)
+		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
 {
-	if (dpi->conf->edge_sel_en)
+	if (dpi->conf->edge_sel_en && dpi->conf->reg_h_fre_con)
 		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
 }
 
-- 
2.39.5



From sashal at kernel.org  Mon May  5 16:21:11 2025
From: sashal at kernel.org (Sasha Levin)
Date: Mon,  5 May 2025 19:21:11 -0400
Subject: [PATCH AUTOSEL 5.4 39/79] drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence
In-Reply-To: <20250505232151.2698893-1-sashal@kernel.org>
References: <20250505232151.2698893-1-sashal@kernel.org>
Message-ID: <20250505232151.2698893-39-sashal@kernel.org>

From: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

[ Upstream commit 8c9da7cd0bbcc90ab444454fecf535320456a312 ]

In preparation for adding support for newer DPI instances which
do support direct-pin but do not have any H_FRE_CON register,
like the one found in MT8195 and MT8188, add a branch to check
if the reg_h_fre_con variable was declared in the mtk_dpi_conf
structure for the probed SoC DPI version.

As a note, this is useful specifically only for cases in which
the support_direct_pin variable is true, so mt8195-dpintf is
not affected by any issue.

Reviewed-by: CK Hu <ck.hu at mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-6-angelogioacchino.delregno at collabora.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu at kernel.org>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 191e0cec004b4..6d105e8aae459 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -337,12 +337,13 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
 
 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 {
-	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
+	if (dpi->conf->reg_h_fre_con)
+		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
 {
-	if (dpi->conf->edge_sel_en)
+	if (dpi->conf->edge_sel_en && dpi->conf->reg_h_fre_con)
 		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
 }
 
-- 
2.39.5



From sean.wang at kernel.org  Mon May  5 16:36:17 2025
From: sean.wang at kernel.org (sean.wang at kernel.org)
Date: Mon,  5 May 2025 16:36:17 -0700
Subject: [PATCH 1/2] wifi: mt76: mt7925: extend MCU support for testmode
Message-ID: <20250505233618.1951021-1-sean.wang@kernel.org>

From: Michael Lo <michael.lo at mediatek.com>

Add MCU command and its handling needed for testmode support on
MT7925. This enables low-level chip testing features such as
continuous TX/RX..

Co-developed-by: Sean Wang <sean.wang at mediatek.com>
Signed-off-by: Sean Wang <sean.wang at mediatek.com>
Signed-off-by: Michael Lo <michael.lo at mediatek.com>
---
 .../wireless/mediatek/mt76/mt76_connac_mcu.h  |  7 +++
 .../net/wireless/mediatek/mt76/mt7925/mcu.c   |  8 ++++
 .../net/wireless/mediatek/mt76/mt7925/mcu.h   | 48 ++++++++++++++++---
 3 files changed, 56 insertions(+), 7 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h b/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h
index 478cd1886736..f93f58eb9bcf 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h
@@ -1183,6 +1183,11 @@ enum {
 #define MCU_UNI_CMD(_t)				(__MCU_CMD_FIELD_UNI |			\
 						 FIELD_PREP(__MCU_CMD_FIELD_ID,		\
 							    MCU_UNI_CMD_##_t))
+
+#define MCU_UNI_QUERY(_t)			(__MCU_CMD_FIELD_UNI | __MCU_CMD_FIELD_QUERY | \
+						 FIELD_PREP(__MCU_CMD_FIELD_ID,		\
+							    MCU_UNI_CMD_##_t))
+
 #define MCU_CE_CMD(_t)				(__MCU_CMD_FIELD_CE |			\
 						 FIELD_PREP(__MCU_CMD_FIELD_ID,		\
 							   MCU_CE_CMD_##_t))
@@ -1288,11 +1293,13 @@ enum {
 	MCU_UNI_CMD_EFUSE_CTRL = 0x2d,
 	MCU_UNI_CMD_RA = 0x2f,
 	MCU_UNI_CMD_MURU = 0x31,
+	MCU_UNI_CMD_TESTMODE_RX_STAT = 0x32,
 	MCU_UNI_CMD_BF = 0x33,
 	MCU_UNI_CMD_CHANNEL_SWITCH = 0x34,
 	MCU_UNI_CMD_THERMAL = 0x35,
 	MCU_UNI_CMD_VOW = 0x37,
 	MCU_UNI_CMD_FIXED_RATE_TABLE = 0x40,
+	MCU_UNI_CMD_TESTMODE_CTRL = 0x46,
 	MCU_UNI_CMD_RRO = 0x57,
 	MCU_UNI_CMD_OFFCH_SCAN_CTRL = 0x58,
 	MCU_UNI_CMD_PER_STA_INFO = 0x6d,
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
index 286f602623c0..df38009e0036 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
@@ -3342,6 +3342,14 @@ int mt7925_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb,
 		if (cmd == MCU_UNI_CMD(HIF_CTRL))
 			uni_txd->option &= ~MCU_CMD_ACK;
 
+		if (mcu_cmd == MCU_UNI_CMD_TESTMODE_CTRL ||
+		    mcu_cmd == MCU_UNI_CMD_TESTMODE_RX_STAT) {
+			if (cmd & __MCU_CMD_FIELD_QUERY)
+				uni_txd->option = 0x2;
+			else
+				uni_txd->option = 0x6;
+		}
+
 		goto exit;
 	}
 
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.h b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.h
index d55ea59bda7d..aed2a1eceac9 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.h
@@ -104,13 +104,6 @@ enum {
 	MT7925_TM_WIFISPECTRUM,
 };
 
-struct mt7925_rftest_cmd {
-	u8 action;
-	u8 rsv[3];
-	__le32 param0;
-	__le32 param1;
-} __packed;
-
 struct mt7925_rftest_evt {
 	__le32 param0;
 	__le32 param1;
@@ -602,6 +595,47 @@ struct roc_acquire_tlv {
 	u8 rsv[3];
 } __packed;
 
+enum ENUM_CMD_TEST_CTRL_ACT {
+	CMD_TEST_CTRL_ACT_SWITCH_MODE = 0,
+	CMD_TEST_CTRL_ACT_SET_AT = 1,
+	CMD_TEST_CTRL_ACT_GET_AT = 2,
+	CMD_TEST_CTRL_ACT_SET_AT_ENG = 3,
+	CMD_TEST_CTRL_ACT_GET_AT_ENG = 4,
+	CMD_TEST_CTRL_ACT_NUM
+};
+
+enum ENUM_CMD_TEST_CTRL_ACT_SWITCH_MODE_OP {
+	CMD_TEST_CTRL_ACT_SWITCH_MODE_NORMAL = 0,
+	CMD_TEST_CTRL_ACT_SWITCH_MODE_RF_TEST = 1,
+	CMD_TEST_CTRL_ACT_SWITCH_MODE_ICAP = 2,
+	CMD_TEST_CTRL_ACT_SWITCH_MODE_NUM
+};
+
+union testmode_data {
+	__le32 op_mode;
+	__le32 channel_freq;
+	u8 rf_at_info[84];
+};
+
+union testmode_evt {
+	__le32 op_mode;
+	__le32 channel_freq;
+	u8 rf_at_info[1024];
+};
+
+struct uni_cmd_testmode_ctrl {
+	u16 tag;
+	u16 length;
+	u8 action;
+	u8 reserved[3];
+	union testmode_data data;
+} __packed;
+
+struct mt7925_rftest_cmd {
+	u8 padding[4];
+	struct uni_cmd_testmode_ctrl ctrl;
+} __packed;
+
 static inline enum connac3_mcu_cipher_type
 mt7925_mcu_get_cipher(int cipher)
 {
-- 
2.25.1



From sean.wang at kernel.org  Mon May  5 16:36:18 2025
From: sean.wang at kernel.org (sean.wang at kernel.org)
Date: Mon,  5 May 2025 16:36:18 -0700
Subject: [PATCH 2/2] wifi: mt76: mt7925: add test mode support
In-Reply-To: <20250505233618.1951021-1-sean.wang@kernel.org>
References: <20250505233618.1951021-1-sean.wang@kernel.org>
Message-ID: <20250505233618.1951021-2-sean.wang@kernel.org>

From: Michael Lo <michael.lo at mediatek.com>

The test mode interface allows controlled execution of chip-level
operations such as continuous transmission, reception tests, and
register access, which are essential during bring-up, diagnostics
, and factory testing.

Co-developed-by: Sean Wang <sean.wang at mediatek.com>
Signed-off-by: Sean Wang <sean.wang at mediatek.com>
Signed-off-by: Michael Lo <michael.lo at mediatek.com>
---
 .../wireless/mediatek/mt76/mt7925/Makefile    |   1 +
 .../net/wireless/mediatek/mt76/mt7925/main.c  |   2 +
 .../wireless/mediatek/mt76/mt7925/mt7925.h    |   5 +
 .../wireless/mediatek/mt76/mt7925/testmode.c  | 204 ++++++++++++++++++
 4 files changed, 212 insertions(+)
 create mode 100644 drivers/net/wireless/mediatek/mt76/mt7925/testmode.c

diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/Makefile b/drivers/net/wireless/mediatek/mt76/mt7925/Makefile
index d321e4ed732f..ade5e647c941 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/Makefile
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/Makefile
@@ -5,5 +5,6 @@ obj-$(CONFIG_MT7925E) += mt7925e.o
 obj-$(CONFIG_MT7925U) += mt7925u.o
 
 mt7925-common-y := mac.o mcu.o main.o init.o debugfs.o
+mt7925-common-$(CONFIG_NL80211_TESTMODE) += testmode.o
 mt7925e-y := pci.o pci_mac.o pci_mcu.o
 mt7925u-y := usb.o
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/main.c b/drivers/net/wireless/mediatek/mt76/mt7925/main.c
index 83f93f9e002c..17fc5f05cb7b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/main.c
@@ -2244,6 +2244,8 @@ const struct ieee80211_ops mt7925_ops = {
 	.sta_statistics = mt792x_sta_statistics,
 	.sched_scan_start = mt7925_start_sched_scan,
 	.sched_scan_stop = mt7925_stop_sched_scan,
+	CFG80211_TESTMODE_CMD(mt7925_testmode_cmd)
+	CFG80211_TESTMODE_DUMP(mt7925_testmode_dump)
 #ifdef CONFIG_PM
 	.suspend = mt7925_suspend,
 	.resume = mt7925_resume,
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h b/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
index 4e50f2597ccd..c507dcae07d4 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
@@ -366,4 +366,9 @@ int mt7925_mcu_wtbl_update_hdr_trans(struct mt792x_dev *dev,
 				     struct ieee80211_sta *sta,
 				     int link_id);
 
+int mt7925_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
+			void *data, int len);
+int mt7925_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *msg,
+			 struct netlink_callback *cb, void *data, int len);
+
 #endif
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/testmode.c b/drivers/net/wireless/mediatek/mt76/mt7925/testmode.c
new file mode 100644
index 000000000000..6a41b95ce56c
--- /dev/null
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/testmode.c
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: ISC
+
+#include "mt7925.h"
+#include "mcu.h"
+
+#define MT7925_EVT_RSP_LEN 512
+
+enum mt7925_testmode_attr {
+	MT7925_TM_ATTR_UNSPEC,
+	MT7925_TM_ATTR_SET,
+	MT7925_TM_ATTR_QUERY,
+	MT7925_TM_ATTR_RSP,
+
+	/* keep last */
+	NUM_MT7925_TM_ATTRS,
+	MT7925_TM_ATTR_MAX = NUM_MT7925_TM_ATTRS - 1,
+};
+
+struct mt7925_tm_cmd {
+	u8 padding[4];
+	struct uni_cmd_testmode_ctrl c;
+} __packed;
+
+struct mt7925_tm_evt {
+	u32 param0;
+	u32 param1;
+} __packed;
+
+static const struct nla_policy mt7925_tm_policy[NUM_MT7925_TM_ATTRS] = {
+	[MT7925_TM_ATTR_SET] = NLA_POLICY_EXACT_LEN(sizeof(struct mt7925_tm_cmd)),
+	[MT7925_TM_ATTR_QUERY] = NLA_POLICY_EXACT_LEN(sizeof(struct mt7925_tm_cmd)),
+};
+
+static int
+mt7925_tm_set(struct mt792x_dev *dev, struct mt7925_tm_cmd *req)
+{
+	struct mt7925_rftest_cmd cmd;
+	struct mt7925_rftest_cmd *pcmd = &cmd;
+	bool testmode = false, normal = false;
+	struct mt76_connac_pm *pm = &dev->pm;
+	struct mt76_phy *phy = &dev->mphy;
+	int ret = -ENOTCONN;
+
+	memset(pcmd, 0, sizeof(*pcmd));
+	memcpy(pcmd, req, sizeof(struct mt7925_tm_cmd));
+
+	mutex_lock(&dev->mt76.mutex);
+
+	if (pcmd->ctrl.action == CMD_TEST_CTRL_ACT_SWITCH_MODE) {
+		if (pcmd->ctrl.data.op_mode == CMD_TEST_CTRL_ACT_SWITCH_MODE_NORMAL)
+			normal = true;
+		else
+			testmode = true;
+	}
+
+	if (testmode) {
+		/* Make sure testmode running on full power mode */
+		pm->enable = false;
+		cancel_delayed_work_sync(&pm->ps_work);
+		cancel_work_sync(&pm->wake_work);
+		__mt792x_mcu_drv_pmctrl(dev);
+
+		phy->test.state = MT76_TM_STATE_ON;
+	}
+
+	if (!mt76_testmode_enabled(phy))
+		goto out;
+
+	ret = mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD(TESTMODE_CTRL), &cmd,
+				sizeof(cmd), false);
+
+	if (ret)
+		goto out;
+
+	if (normal) {
+		/* Switch back to the normal world */
+		phy->test.state = MT76_TM_STATE_OFF;
+		pm->enable = true;
+	}
+out:
+	mutex_unlock(&dev->mt76.mutex);
+
+	return ret;
+}
+
+static int
+mt7925_tm_query(struct mt792x_dev *dev, struct mt7925_tm_cmd *req,
+		char *evt_resp)
+{
+	struct mt7925_rftest_cmd cmd;
+	char *pcmd = (char *)&cmd;
+	struct uni_cmd_testmode_evt *evt;
+	struct sk_buff *skb = NULL;
+	int ret = 1;
+
+	memset(pcmd, 0, sizeof(*pcmd));
+	memcpy(pcmd + 4, (char *)&req->c, sizeof(struct uni_cmd_testmode_ctrl));
+
+	if (*((uint16_t *)req->padding) == MCU_UNI_CMD_TESTMODE_CTRL)
+		ret = mt76_mcu_send_and_get_msg(&dev->mt76, MCU_UNI_QUERY(TESTMODE_CTRL),
+						&cmd, sizeof(cmd), true, &skb);
+	else if (*((uint16_t *)req->padding) == MCU_UNI_CMD_TESTMODE_RX_STAT)
+		ret = mt76_mcu_send_and_get_msg(&dev->mt76, MCU_UNI_QUERY(TESTMODE_RX_STAT),
+						&cmd, sizeof(cmd), true, &skb);
+
+	if (ret)
+		goto out;
+
+	evt = (struct uni_cmd_testmode_evt *)skb->data;
+
+	memcpy((char *)evt_resp, (char *)skb->data + 8, MT7925_EVT_RSP_LEN);
+
+out:
+	dev_kfree_skb(skb);
+
+	return ret;
+}
+
+int mt7925_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
+			void *data, int len)
+{
+	struct nlattr *tb[NUM_MT76_TM_ATTRS];
+	struct mt76_phy *mphy = hw->priv;
+	struct mt792x_phy *phy = mphy->priv;
+	int err;
+
+	if (!test_bit(MT76_STATE_RUNNING, &mphy->state) ||
+	    !(hw->conf.flags & IEEE80211_CONF_MONITOR))
+		return -ENOTCONN;
+
+	err = nla_parse_deprecated(tb, MT76_TM_ATTR_MAX, data, len,
+				   mt76_tm_policy, NULL);
+	if (err)
+		return err;
+
+	if (tb[MT76_TM_ATTR_DRV_DATA]) {
+		struct nlattr *drv_tb[NUM_MT7925_TM_ATTRS], *data;
+		int ret;
+
+		data = tb[MT76_TM_ATTR_DRV_DATA];
+		ret = nla_parse_nested_deprecated(drv_tb,
+						  MT7925_TM_ATTR_MAX,
+						  data, mt7925_tm_policy,
+						  NULL);
+		if (ret)
+			return ret;
+
+		data = drv_tb[MT7925_TM_ATTR_SET];
+		if (data)
+			return mt7925_tm_set(phy->dev, nla_data(data));
+	}
+
+	return -EINVAL;
+}
+
+int mt7925_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *msg,
+			 struct netlink_callback *cb, void *data, int len)
+{
+	struct nlattr *tb[NUM_MT76_TM_ATTRS];
+	struct mt76_phy *mphy = hw->priv;
+	struct mt792x_phy *phy = mphy->priv;
+	int err;
+
+	if (!test_bit(MT76_STATE_RUNNING, &mphy->state) ||
+	    !(hw->conf.flags & IEEE80211_CONF_MONITOR) ||
+	    !mt76_testmode_enabled(mphy))
+		return -ENOTCONN;
+
+	if (cb->args[2]++ > 0)
+		return -ENOENT;
+
+	err = nla_parse_deprecated(tb, MT76_TM_ATTR_MAX, data, len,
+				   mt76_tm_policy, NULL);
+	if (err)
+		return err;
+
+	if (tb[MT76_TM_ATTR_DRV_DATA]) {
+		struct nlattr *drv_tb[NUM_MT7925_TM_ATTRS], *data;
+		int ret;
+
+		data = tb[MT76_TM_ATTR_DRV_DATA];
+		ret = nla_parse_nested_deprecated(drv_tb,
+						  MT7925_TM_ATTR_MAX,
+						  data, mt7925_tm_policy,
+						  NULL);
+		if (ret)
+			return ret;
+
+		data = drv_tb[MT7925_TM_ATTR_QUERY];
+		if (data) {
+			char evt_resp[MT7925_EVT_RSP_LEN];
+
+			err = mt7925_tm_query(phy->dev, nla_data(data),
+					      evt_resp);
+			if (err)
+				return err;
+
+			return nla_put(msg, MT7925_TM_ATTR_RSP,
+				       sizeof(evt_resp), evt_resp);
+		}
+	}
+
+	return -EINVAL;
+}
-- 
2.25.1



From victor.liu at nxp.com  Mon May  5 19:24:18 2025
From: victor.liu at nxp.com (Liu Ying)
Date: Tue, 6 May 2025 10:24:18 +0800
Subject: [PATCH v2 30/34] drm/bridge: imx8qxp-pixel-combiner: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250430112944.1b39caab@booty>
References: <20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b@bootlin.com>
 <20250424-drm-bridge-convert-to-alloc-api-v2-30-8f91a404d86b@bootlin.com>
 <553d62ed-976a-4e17-9678-cdc3d40ce4a7@nxp.com>
 <20250430112944.1b39caab@booty>
Message-ID: <f71d18d2-4271-4bb9-b54f-0e5a585778f3@nxp.com>

On 04/30/2025, Luca Ceresoli wrote:
> Hello Liu,

Hi Luca,

> 
> On Tue, 29 Apr 2025 10:10:55 +0800
> Liu Ying <victor.liu at nxp.com> wrote:
> 
>> Hi,
>>
>> On 04/25/2025, Luca Ceresoli wrote:
>>> This is the new API for allocating DRM bridges.
>>>
>>> This driver embeds an array of channels in the main struct, and each
>>> channel embeds a drm_bridge. This prevents dynamic, refcount-based
>>> deallocation of the bridges.
>>>
>>> To make the new, dynamic bridge allocation possible:
>>>
>>>  * change the array of channels into an array of channel pointers
>>>  * allocate each channel using devm_drm_bridge_alloc()
>>>  * adapt the code wherever using the channels
>>>
>>> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
> 
> [...]
> 
>>> @@ -345,8 +351,8 @@ static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
>>>  free_child:
>>>  	of_node_put(child);
>>>  
>>> -	if (i == 1 && pc->ch[0].next_bridge)
>>> -		drm_bridge_remove(&pc->ch[0].bridge);
>>> +	if (i == 1 && pc->ch[0]->next_bridge)  
>>
>> Since this patch makes pc->ch[0] and pc->ch[1] be allocated separately,
>> pc->ch[0] could be NULL if channel0 is not available, hence a NULL pointer
>> dereference here...
> 
> See below for this.
> 
>>> +		drm_bridge_remove(&pc->ch[0]->bridge);
>>>  
>>>  	pm_runtime_disable(dev);
>>>  	return ret;
>>> @@ -359,7 +365,7 @@ static void imx8qxp_pc_bridge_remove(struct platform_device *pdev)
>>>  	int i;
>>>  
>>>  	for (i = 0; i < 2; i++) {
>>> -		ch = &pc->ch[i];
>>> +		ch = pc->ch[i];
>>>  
>>>  		if (!ch->is_available)  
>>
>> ...and here too.
> 
> This is indeed a bug, I should have checked the pointer for being
> non-NULL.
> 
> Looking at that more closely, I think the is_available flag can be
> entirely removed now. The allocation itself (ch != NULL) now is
> equivalent. Do you think my reasoning is correct?
> 
> Ouch! After writing the previous paragraph I realized you proposed this
> a few lines below! OK, removing is_available. :)
> 
> [...]
> 
>> On top of this patch series, this issue doesn't happen if I apply the below
>> change:
> 
> [...]
> 
>> @@ -351,7 +349,7 @@ static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
>>  free_child:
>>         of_node_put(child);
>>  
>> -       if (i == 1 && pc->ch[0]->next_bridge)
>> +       if (i == 1 && pc->ch[0])
>>                 drm_bridge_remove(&pc->ch[0]->bridge);
> 
> Unrelated to this patch, but as I looked at it more in depth now, I'm
> not sure this whole logic is robust, even in the original code.
> 
> The 'i == 1' check here seems to mean "if some error happened when
> handling channel at 1, that means channel at 0 was successfully initialized,
> so let's clean up channel 0".
> 
> However my understanding of the bindings is that device tree is allowed
> to have the channel at 1 node before the channel at 0 node (or even channel at 1
> without channel at 0, but that's less problematic here).
> 
> In such case (channel at 1 before channel at 0), this would happen:
> 
>  1. alloc and init ch[1], all OK
>  2. alloc and init ch[0], an error happens
>     (e.g. of_graph_get_remote_node() fails)
> 
> So we'd reach the free_child: label, and we should call
> drm_bridge_remove() for ch[1]->bridge, but there's no code to do that.
> 
> To be robust in such a case, I think both channels need to be checked
> independently, as the status of one does not imply the status of the
> other. E.g.:
> 
>   for (i = 0; i < 2; i++)
>       if (pc->ch[i] && pc->ch[i]->next_bridge)
>           drm_bridge_remove(&pc->ch[i]->bridge);
> 
> (which is similar to what .remove() does after the changes discussed in
> this thread, and which I have queued for v3)
> 
> What's your opinion? Do you think I missed anything?

The pixel combiner DT node would be added in imx8-ss-dc{0,1}.dtsi, please
see the case for imx8-ss-dc0.dtsi introduced by an in-flight patch[1].  As
channel@{0,1} child nodes always exist(DT overlay cannot effectively delete
any of them) and channel at 0 always comes first, there is no problematic case.

> 
> Thanks for taking the time to dig into this!

After looking into this patch and patch 31(though I've already provided my A-b)
more closely, I think the imx8qxp_pc and imx8{qm,qxp}_ldb main structures
should have the same life time with the embedded DRM bridges, because for
example the clk_apb clock in struct imx8qxp_pc would be accessed by the
imx8qxp_pc_bridge_mode_set DRM bridge callback.  But, IIUC, your patches extend
the life time for the embedded channel/bridge structures only, but not for the
main structures.  What do you think ?

> 
> Best regards,
> Luca
> 

[1] https://lore.kernel.org/dri-devel/20250414035028.1561475-17-victor.liu at nxp.com/

-- 
Regards,
Liu Ying


From Sirius.Wang at mediatek.com  Mon May  5 21:10:24 2025
From: Sirius.Wang at mediatek.com (=?utf-8?B?U2lyaXVzIFdhbmcgKOeOi+eak+aYsSk=?=)
Date: Tue, 6 May 2025 04:10:24 +0000
Subject: [PATCH 0/2] Add mt8189 dts evaluation board and Mafefile
In-Reply-To: <20250505121627.3944728-1-sirius.wang@mediatek.com>
References: <20250505121627.3944728-1-sirius.wang@mediatek.com>
Message-ID: <231555a744a78096ed3f8247b5536fb58024e205.camel@mediatek.com>

On Mon, 2025-05-05 at 20:15 +0800, Sirius Wang wrote:
> MT8189 is a SoC based on 64bit ARMv8 architecture. It contains 6 CA55
> and 2 CA78 cores. MT8189 share many HW IP with MT8188 series.
> 
> We add basic chip support for MediaTek MT8189 on evaluation board.
> 
> In this series, we also add dt-bindings document definition for
> MT8189.
> 
> Sirius Wang (2):
> ? WIP: dt-bindings: arm: Add compatible for MediaTek MT8189
> ? WIP: arm64: dts: mt8189: Add mt8189 dts evaluation board and
> Mafefile
> 
> ?.../devicetree/bindings/arm/mediatek.yaml???? |?? 4 +
> ?arch/arm64/boot/dts/mediatek/Makefile???????? |?? 1 +
> ?arch/arm64/boot/dts/mediatek/mt8189-evb.dts?? |? 20 +
> ?arch/arm64/boot/dts/mediatek/mt8189.dtsi????? | 441
> ++++++++++++++++++
> ?4 files changed, 466 insertions(+)
> ?create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
> ?create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi
> 
Dear maintainers and reviewers:

I apologize for inconvenience for sending the incorrect version of this
patch.

I will correct the issue and submit the correct version of the patch as
soon as possible.

Thank you for your understanding and patience.

Best regards,

Sirius

From angelogioacchino.delregno at collabora.com  Tue May  6 01:26:48 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 6 May 2025 10:26:48 +0200
Subject: [PATCH 2/2] arm64: dts: mediatek: mt8365: Describe infracfg-nao
 as a pure syscon
In-Reply-To: <20250502-mt8365-infracfg-nao-compatible-v1-2-e40394573f98@collabora.com>
References: <20250502-mt8365-infracfg-nao-compatible-v1-0-e40394573f98@collabora.com>
 <20250502-mt8365-infracfg-nao-compatible-v1-2-e40394573f98@collabora.com>
Message-ID: <0fd0c066-d203-437f-940e-ca355100bbc6@collabora.com>

Il 02/05/25 18:43, N?colas F. R. A. Prado ha scritto:
> The infracfg-nao register space at 0x1020e000 has different registers
> than the infracfg space at 0x10001000, and most importantly, doesn't
> contain any clock controls. Therefore it shouldn't use the same
> compatible used for the mt8365 infracfg clocks driver:
> mediatek,mt8365-infracfg. Since it currently does, probe errors are
> reported in the kernel logs:
> 
>    [    0.245959] Failed to register clk ifr_pmic_tmr: -EEXIST
>    [    0.245998] clk-mt8365 1020e000.infracfg: probe with driver clk-mt8365 failed with error -17
> 
> This register space is used only as a syscon for bus control by the
> power domain controller, so in order to properly describe it and fix the
> errors, set its compatible to a distinct compatible used exclusively as
> a syscon, drop the clock-cells, and while at it rename the node to
> 'syscon' following the naming convention.
> 
> Fixes: 6ff945376556 ("arm64: dts: mediatek: Initial mt8365-evk support")
> Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>




From angelogioacchino.delregno at collabora.com  Tue May  6 01:26:49 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 6 May 2025 10:26:49 +0200
Subject: [PATCH 1/2] dt-bindings: mfd: syscon: Add
 mediatek,mt8365-infracfg-nao
In-Reply-To: <20250502-mt8365-infracfg-nao-compatible-v1-1-e40394573f98@collabora.com>
References: <20250502-mt8365-infracfg-nao-compatible-v1-0-e40394573f98@collabora.com>
 <20250502-mt8365-infracfg-nao-compatible-v1-1-e40394573f98@collabora.com>
Message-ID: <ce48bcb3-1881-41bb-aafe-bf90b78d47e4@collabora.com>

Il 02/05/25 18:43, N?colas F. R. A. Prado ha scritto:
> The register space described by DT node of compatible
> mediatek,mt8365-infracfg-nao exposes a variety of unrelated registers,
> including registers for controlling bus protection on the MT8365 SoC,
> which is used by the power domain controller through a syscon.
> 
> Add this compatible to the syscon binding.
> 
> Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>




From angelogioacchino.delregno at collabora.com  Tue May  6 01:28:33 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 6 May 2025 10:28:33 +0200
Subject: [PATCH v5 2/3] drm/panfrost: Add support for Mali on the MT8370
 SoC
In-Reply-To: <20250502-mt8370-enable-gpu-v5-2-98e247b30151@collabora.com>
References: <20250502-mt8370-enable-gpu-v5-0-98e247b30151@collabora.com>
 <20250502-mt8370-enable-gpu-v5-2-98e247b30151@collabora.com>
Message-ID: <65012c1f-9888-4231-8e7f-c96b7f09053a@collabora.com>

Il 02/05/25 14:17, Louis-Alexis Eyraud ha scritto:
> Add a compatible for the MediaTek MT8370 SoC, with an integrated ARM
> Mali G57 MC2 GPU (Valhall-JM, dual core), with new platform data for
> its support in the panfrost driver.
> It uses the same data as MT8186 for the power management features to
> describe power supplies, pm_domains and enablement (one regulator, two
> power domains) but also sets the FORCE_AARCH64_PGTABLE flag in the GPU
> configuration quirks bitfield to enable AARCH64 4K page table format
> mode.
> As MT8186 and MT8370 SoC have different GPU architecture (Mali G52 2EE
> MC2 for MT8186), making them not compatible, and this mode is only
> enabled for Mediatek SoC that are Mali G57 based (compatible with
> mediatek,mali-mt8188 or mediatek,mali-8192), having specific platform
> data allows to set this flag for MT8370 without modifying MT8186
> configuration and behaviour.
> 
> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>




From angelogioacchino.delregno at collabora.com  Tue May  6 01:33:17 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 06 May 2025 10:33:17 +0200
Subject: [PATCH] arm/arm64: dts: mediatek: Add missing
 "#sound-dai-cells" to linux,bt-sco
In-Reply-To: <20250409205001.1522009-1-robh@kernel.org>
References: <20250409205001.1522009-1-robh@kernel.org>
Message-ID: <174652039790.26427.3827996167340215423.b4-ty@collabora.com>

On Wed, 09 Apr 2025 15:50:00 -0500, Rob Herring (Arm) wrote:
> Add missing "#sound-dai-cells" which is required by the linux,bt-sco
> binding.
> 
> 

Applied to v6.15-next/dts64, thanks!

[1/1] arm/arm64: dts: mediatek: Add missing "#sound-dai-cells" to linux,bt-sco
      commit: b8202a12cdd771b55a9565814022ea8c69572cd7

Cheers,
Angelo




From angelogioacchino.delregno at collabora.com  Tue May  6 01:34:33 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 6 May 2025 10:34:33 +0200
Subject: [PATCH 2/4] dt-bindings: iommu: mediatek: mt8195 Accept up to 5
 interrupts
In-Reply-To: <20250505-mt8395-dtb-errors-v1-2-9c4714dcdcdb@collabora.com>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
 <20250505-mt8395-dtb-errors-v1-2-9c4714dcdcdb@collabora.com>
Message-ID: <cb715936-3a44-4002-8d64-565f8d31820c@collabora.com>

Il 05/05/25 15:23, Julien Massot ha scritto:
> Some Mediatek IOMMU can have up to five interrupts so increase
> the 'maxItems' to 5.
> 
> Fix the following dtb-check error:
> 
> mediatek/mt8395-radxa-nio-12l.dtb: infra-iommu at 10315000: interrupts:
> [[0, 795, 4, 0], [0, 796, 4, 0], [0, 797, 4, 0], [0, 798, 4, 0], [0, 799, 4, 0]] is too long
> 
> Fixes: 3b5838d1d82e3 ("arm64: dts: mt8195: Add iommu and smi nodes")
> Signed-off-by: Julien Massot <julien.massot at collabora.com>
> ---
>   Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> index 75750c64157c868725c087500ac81be4e282c829..035941c2db32170e9a69a5363d8c05ef767bb251 100644
> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> @@ -97,7 +97,8 @@ properties:
>       maxItems: 1
>   
>     interrupts:
> -    maxItems: 1
> +    minItems: 1

Isn't minItems already implicitly 1? :-)

Cheers,
Angelo

> +    maxItems: 5
>   
>     clocks:
>       items:
> 



From angelogioacchino.delregno at collabora.com  Tue May  6 01:35:11 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 6 May 2025 10:35:11 +0200
Subject: [PATCH 4/4] arm64: dts: mt6359: Rename RTC node to match binding
 expectations
In-Reply-To: <20250505-mt8395-dtb-errors-v1-4-9c4714dcdcdb@collabora.com>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
 <20250505-mt8395-dtb-errors-v1-4-9c4714dcdcdb@collabora.com>
Message-ID: <97ceba0b-2a66-4366-8d2e-34dbef0866ea@collabora.com>

Il 05/05/25 15:23, Julien Massot ha scritto:
> Rename the node 'mt6359rtc' to 'rtc', as required by the binding.
> 
> Fix the following dtb-check error:
> 
> mediatek/mt8395-radxa-nio-12l.dtb: pmic: 'mt6359rtc' do not match
> any of the regexes: 'pinctrl-[0-9]+'
> 
> Fixes: 3b7d143be4b7 ("arm64: dts: mt6359: add PMIC MT6359 related nodes")

Your S-o-B is missing....

Cheers,
Angelo


From angelogioacchino.delregno at collabora.com  Tue May  6 01:35:16 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 6 May 2025 10:35:16 +0200
Subject: [PATCH 3/4] arm64: dts: mt6359: Add missing 'compatible' property
 to regulators node
In-Reply-To: <20250505-mt8395-dtb-errors-v1-3-9c4714dcdcdb@collabora.com>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
 <20250505-mt8395-dtb-errors-v1-3-9c4714dcdcdb@collabora.com>
Message-ID: <b0a1ecb5-4a45-498b-8632-368383a10679@collabora.com>

Il 05/05/25 15:23, Julien Massot ha scritto:
> The 'compatible' property is required by the
> 'mfd/mediatek,mt6397.yaml' binding. Add it to fix the following
> dtb-check error:
> mediatek/mt8395-radxa-nio-12l.dtb: pmic: regulators:
> 'compatible' is a required property
> 
> Fixes: 3b7d143be4b7 ("arm64: dts: mt6359: add PMIC MT6359 related nodes")
> Signed-off-by: Julien Massot <julien.massot at collabora.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>



From angelogioacchino.delregno at collabora.com  Tue May  6 01:35:25 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 6 May 2025 10:35:25 +0200
Subject: [PATCH 1/4] dt-bindings: mfd: mediatek: mt6397: Add
 #sound-dai-cells property
In-Reply-To: <20250505-mt8395-dtb-errors-v1-1-9c4714dcdcdb@collabora.com>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
 <20250505-mt8395-dtb-errors-v1-1-9c4714dcdcdb@collabora.com>
Message-ID: <f0f7c044-c8ee-4712-94db-882cdf894653@collabora.com>

Il 05/05/25 15:23, Julien Massot ha scritto:
> The 'mt6359.dtsi' file already uses the '#sound-dai-cells' property.
> Add the corresponding property to the binding to fix the following
> dtb-check error:
> 
> mediatek/mt8395-radxa-nio-12l.dtb: pmic: '#sound-dai-cells', 'mt6359rtc' do not match any of the regexes: 'pinctrl-[0-9]+'
> from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6397.yaml#
> 
> Fixes: 9bc8353be720 ("arm64: dts: mt6359: Add #sound-dai-cells property")
> Signed-off-by: Julien Massot <julien.massot at collabora.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>




From angelogioacchino.delregno at collabora.com  Tue May  6 01:42:50 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 06 May 2025 10:42:50 +0200
Subject: [PATCH] arm64: dts: mediatek: mt6357: Drop regulator-fixed
 compatibles
In-Reply-To: <20250502-mt6357-regulator-fixed-compatibles-removal-v1-1-a582c16743fe@collabora.com>
References: <20250502-mt6357-regulator-fixed-compatibles-removal-v1-1-a582c16743fe@collabora.com>
Message-ID: <174652097090.119919.16240846809714782858.b4-ty@collabora.com>

On Fri, 02 May 2025 11:32:10 -0400, N?colas F. R. A. Prado wrote:
> Some of the regulators in the MT6357 PMIC dtsi have compatible set to
> regulator-fixed, even though they don't serve any purpose: all those
> regulators are handled as a whole by the mt6357-regulator driver. In
> fact this is the only dtsi in this family of chips where this is the
> case: mt6359 and mt6358 don't have any such compatibles.
> 
> A side-effect caused by this is that the DT kselftest, which is supposed
> to identify nodes with compatibles that can be probed, but haven't,
> shows these nodes as failures.
> 
> [...]

Applied to v6.15-next/dts64, thanks!

[1/1] arm64: dts: mediatek: mt6357: Drop regulator-fixed compatibles
      commit: d77e89b7b03fb945b4353f2dcc4a70b34baa7bcb

Cheers,
Angelo




From angelogioacchino.delregno at collabora.com  Tue May  6 01:42:51 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 06 May 2025 10:42:51 +0200
Subject: [PATCH] arm64: dts: mediatek: mt8395-genio-1200-evk: Disable
 unused backlight
In-Reply-To: <20250502-genio-1200-disable-backlight-lcd1-v1-1-c021d2c9e48e@collabora.com>
References: <20250502-genio-1200-disable-backlight-lcd1-v1-1-c021d2c9e48e@collabora.com>
Message-ID: <174652097181.119919.737275230947353640.b4-ty@collabora.com>

On Fri, 02 May 2025 08:42:56 -0400, N?colas F. R. A. Prado wrote:
> The builtin panel on the Genio 1200 EVK board uses the backlight_lcm0
> node for its backlight. Though the backlight_lcd1 is currently left
> enabled, it is unused, and its pwm input, disp_pwm1, is disabled, so it
> fails probe. Disable this unused node.
> 
> 

Applied to v6.15-next/dts64, thanks!

[1/1] arm64: dts: mediatek: mt8395-genio-1200-evk: Disable unused backlight
      commit: 0eae9cee0d74c09f5ee7ccc0dcc6b7fbb669f68b

Cheers,
Angelo




From angelogioacchino.delregno at collabora.com  Tue May  6 01:42:52 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 06 May 2025 10:42:52 +0200
Subject: [PATCH v2] arm64: dts: mediatek: mt8390-genio-common: Set
 ssusb2 default dual role mode to host
In-Reply-To: <20250502-mtk-genio-510-700-fix-bt-detection-v2-1-870aa2145480@collabora.com>
References: <20250502-mtk-genio-510-700-fix-bt-detection-v2-1-870aa2145480@collabora.com>
Message-ID: <174652097261.119919.932042428704090741.b4-ty@collabora.com>

On Fri, 02 May 2025 15:17:19 +0200, Louis-Alexis Eyraud wrote:
> On the Mediatek Genio 510-EVK and 700-EVK boards, ssusb2 controller is
> one but has two ports: one is routed to the M.2 slot, the other is on
> the RPi header who does support full OTG.
> Since Mediatek Genio 700-EVK USB support was added, dual role mode
> property is set to otg for ssusb2. This config prevents the M.2
> Wifi/Bluetooth module, present on those boards and exposing Bluetooth
> as an USB device to be properly detected at startup as the default role
> is device.
> To keep the OTG functionality and make the M.2 module be detected at
> the same time, add role-switch-default-mode property set to host and
> also fix the polarity of GPIO associated to the USB connector, so the
> ssusb2 controller role is properly set to host when the other port is
> unused.
> 
> [...]

Applied to v6.15-next/dts64, thanks!

[1/1] arm64: dts: mediatek: mt8390-genio-common: Set ssusb2 default dual role mode to host
      commit: f9167f15dd4e70b124023a2f7ba2b09401b3b6ff

Cheers,
Angelo




From angelogioacchino.delregno at collabora.com  Tue May  6 01:42:53 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 06 May 2025 10:42:53 +0200
Subject: (subset) [PATCH 0/4] mt8395/mt6359: Fix several dtb-check
 errors
In-Reply-To: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
Message-ID: <174652097340.119919.13115180921625978268.b4-ty@collabora.com>

On Mon, 05 May 2025 15:23:36 +0200, Julien Massot wrote:
> This patch series addresses several dtb-check errors reported for the mt8395-genio-1200-evk.dtb and mt8395-radxa-nio-12l.dtb device trees.
> 
> The fixes include:
> - Adding the missing #sound-dai-cells property in the mt6397 binding.
> - Allowing up to 5 interrupts in the MediaTek IOMMU binding to support MT8395 properly.
> - Defining the required compatible property in the regulators node of the mt6359.dtsi.
> - Renaming the rtc node to match expected schema naming.
> 
> [...]

Applied to v6.15-next/dts64, thanks!

[3/4] arm64: dts: mt6359: Add missing 'compatible' property to regulators node
      commit: 1fe38d2a19950fa6dbc384ee8967c057aef9faf4

Cheers,
Angelo




From daniel.lezcano at linaro.org  Tue May  6 01:54:09 2025
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Tue, 6 May 2025 10:54:09 +0200
Subject: [PATCH v4 2/7] clocksource/drivers: Add EcoNet Timer HPT driver
In-Reply-To: <92cd3689-3409-4d43-8db1-8633d35f779a@cjdns.fr>
References: <20250430133433.22222-1-cjd@cjdns.fr>
 <20250430133433.22222-3-cjd@cjdns.fr> <aBjpBpJAIP89oiit@mai.linaro.org>
 <92cd3689-3409-4d43-8db1-8633d35f779a@cjdns.fr>
Message-ID: <7c08cc9e-f39f-490c-85fe-5738656380e5@linaro.org>

On 05/05/2025 20:09, Caleb James DeLisle wrote:
> 
> On 05/05/2025 18:36, Daniel Lezcano wrote:
>> On Wed, Apr 30, 2025 at 01:34:28PM +0000, Caleb James DeLisle wrote:
>>> Introduce a clocksource driver for the so-called high-precision timer 
>>> (HPT)
>>> in the EcoNet EN751221 MIPS SoC.
>> As a new driver, please document the timer (up - down ?, SPI/PPI, etc
>> ...) that will help to understand the code more easily, especially the
>> reg_* functions (purposes?).
> 
> 
> Sure thing, I can elaborate the comment in the header of
> timer-econet-en751221.c. Let me know if you'd like it described
> somewhere else as well, such as the help of config ECONET_EN751221_TIMER.

It is ok in the changelog, so it is possible to get the description when 
looking for the patch introducing the new timer.

[ ... ]

>>> +
>>> +??? cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING,
>>> +????????????? "clockevents/en75/timer:starting",
>>> +????????????? cevt_init_cpu, NULL);
>> cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, ... ) ?
> 
> I see that Ingenic does this. This is the only timer so until it's up,
> sleeping causes a hang. If sleeping is prior to CPUHP_AP_ONLINE_DYN is
> considered a bug then this should be okay, but I'm not informed enough
> to say whether that is the case so I'll follow your guidance here.

Hmm, hard to say without the platform. May be just give a try with 
CPUHP_AP_ONLINE_DYN to check if it works otherwise stick on 
CPUHP_AP_MIPS_GIC_TIMER_STARTING as it is already defined ?

[ ... ]


-- 
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog


From angelogioacchino.delregno at collabora.com  Tue May  6 02:17:32 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue,  6 May 2025 11:17:32 +0200
Subject: [GIT,PULL,1/2] MediaTek ARM64 DTS updates for v6.16
Message-ID: <20250506091736.125733-1-angelogioacchino.delregno@collabora.com>

The following changes since commit 0af2f6be1b4281385b618cb86ad946eded089ac8:

  Linux 6.15-rc1 (2025-04-06 13:11:33 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux.git tags/mtk-dts64-for-v6.16

for you to fetch changes up to 1fe38d2a19950fa6dbc384ee8967c057aef9faf4:

  arm64: dts: mt6359: Add missing 'compatible' property to regulators node (2025-05-06 10:35:45 +0200)

----------------------------------------------------------------
MediaTek ARM64 DTS updates for v6.16

This adds new MT8186-based Google Ponyta Chromebooks and improves
support for already supported SoCs and machines.

In particular, SoCs changes:
 - MT6893
   - Added pinmux header for this SoC
 - MT8183
   - Added port	node for dsi_out in mt8183.dtsi	to fix some DT
     validation	warnings.
 - MT8188
   - Adds an important fix for its Display Controller's Read DMA 0
     (RDMA0), as it was using the wrong IOMMU and failing;
   - Multimedia Data Path 3 (MDP3) devicetree nodes were added: now
     hardware assisted color format conversions are available;
   - Since SCP firmwares are available on linux-firmware, the
     necessary nodes for the dual-core SCP were added to devicetree
     along with the firmware-name property in mt8390-genio-common,
     enabling hardware video encoders and decoders on the MediaTek
     Genio 510 and Genio 700 EVKs.
 - MT8195
   - Power domains for video decoders and encoders were reparented
     as the secondary vdec/venc core needs the primary core to be
     also powered, as those are sharing the LAT hardware and SRAM;
   - Missing power domain was added to the primary DisplayPort
     Interface (dp_intf0) node.
 - MT8196
   - Added pinmux header for this SoC

... and machine-specific changes:
 - Radxa NIO-12L (MT8395)
   - Added support for Audio DSP and sound output through 3.5mm jack;
 - MediaTek Genio 1200 EVK (MT8395)
   - Support for this EVK's DSI display was added and enabled;
   - Secondary display backlight was disabled as it was unused
 - MediaTek Genio 510/700 (MT8370/MT8390)
   - Added support for the DSI display on these EVKs too;
   - Fixed an issue with integrated USB Bluetooth getting unplugged
     permanently due to wrong declaration of the ID GPIO polarity of
     the secondary USB port on the SSUSB2 controller;

Other than that, some other devicetree validation fixes were added
on the MT6357 and MT6359 PMIC DTs: for the former, all of the
compatible strings in all regulators were dropped as those were
wrong and causing DT kselftest failures - and for the latter, the
compatible string for the main `regulators` node was added as it
was missing.

----------------------------------------------------------------
AngeloGioacchino Del Regno (6):
      arm64: dts: mediatek: mt8195: Reparent vdec1/2 and venc1 power domains
      dt-bindings: display: mediatek: Add compatibles for MT8188 MDP3
      dt-bindings: media: mediatek: mdp3: Add compatibles for MT8188 MDP3
      arm64: dts: mediatek: mt8188: Add all Multimedia Data Path 3 nodes
      arm64: dts: mediatek: Add MT6893 pinmux macro header file
      arm64: dts: mediatek: mt8390-genio-common: Add Display on DSI0

Axe Yang (1):
      arm64: dts: mediatek: mt8186-corsola: make SDIO card removable

Cathy Xu (1):
      arm64: dts: mediatek: mt8196: Add pinmux macro header file

Chen-Yu Tsai (1):
      arm64: dts: mediatek: mt8188: Fix IOMMU device for rdma0

Jianeng Ceng (2):
      dt-bindings: arm: mediatek: Add MT8186 Ponyta Chromebook
      arm64: dts: mediatek: Add MT8186 Ponyta Chromebooks

Julien Massot (4):
      arm64: dts: mediatek: mt8395-nio-12l: Add scp firmware-name
      arm64: dts: mediatek: mt8395-genio-1200-evk: Add scp firmware-name
      arm64: dts: mediatek: mt8395-nio-12l: Enable Audio DSP and sound card
      arm64: dts: mt6359: Add missing 'compatible' property to regulators node

Louis-Alexis Eyraud (3):
      arm64: dts: mediatek: mt8390-genio-common: Fix pcie pinctrl dtbs_check error
      arm64: dts: mediatek: mt8395-genio-1200-evk: Add display on DSI0
      arm64: dts: mediatek: mt8390-genio-common: Set ssusb2 default dual role mode to host

Macpaul Lin (1):
      arm64: dts: mediatek: mt8195: Add power domain for dp_intf0

N?colas F. R. A. Prado (4):
      arm64: dts: mediatek: mt8188: Describe SCP as a cluster with two cores
      arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0
      arm64: dts: mediatek: mt6357: Drop regulator-fixed compatibles
      arm64: dts: mediatek: mt8395-genio-1200-evk: Disable unused backlight

Pin-yen Lin (1):
      arm64: dts: mt8183: Add port node to mt8183.dtsi

Rob Herring (Arm) (1):
      arm/arm64: dts: mediatek: Add missing "#sound-dai-cells" to linux,bt-sco

?ukasz Majczak (1):
      arm64: dts: mediatek: mt8186: starmie: Fix external display

 Documentation/devicetree/bindings/arm/mediatek.yaml                      |    7 +
 Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml     |    4 +
 Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml   |    4 +
 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml   |    4 +
 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml |   10 +-
 Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml            |    8 +-
 Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml           |    8 +-
 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml           |    1 +
 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml        |    8 +-
 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml           |    8 +-
 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml         |    8 +-
 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml          |    1 +
 arch/arm/boot/dts/mediatek/mt2701-evb.dts                                |    1 +
 arch/arm64/boot/dts/mediatek/Makefile                                    |    2 +
 arch/arm64/boot/dts/mediatek/mt6357.dtsi                                 |   10 -
 arch/arm64/boot/dts/mediatek/mt6359.dtsi                                 |    2 +
 arch/arm64/boot/dts/mediatek/mt6893-pinfunc.h                            | 1356 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi                           |   11 +-
 arch/arm64/boot/dts/mediatek/mt8183.dtsi                                 |    4 +
 arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku0.dts              |   18 +
 arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku1.dts              |   22 +
 arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta.dtsi                  |   49 ++
 arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie.dtsi                 |   45 --
 arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi                         |    1 -
 arch/arm64/boot/dts/mediatek/mt8188-evb.dts                              |    6 +-
 arch/arm64/boot/dts/mediatek/mt8188.dtsi                                 |  349 ++++++++++++++-
 arch/arm64/boot/dts/mediatek/mt8195.dtsi                                 |   51 ++-
 arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h                            | 1574 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi                    |  170 ++++++-
 arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts                   |  127 +++++-
 arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts                    |   59 ++-
 31 files changed, 3797 insertions(+), 131 deletions(-)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt6893-pinfunc.h
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku0.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku1.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta.dtsi
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h



From angelogioacchino.delregno at collabora.com  Tue May  6 02:17:33 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue,  6 May 2025 11:17:33 +0200
Subject: [GIT,PULL,2/2] MediaTek driver updates for v6.16
In-Reply-To: <20250506091736.125733-1-angelogioacchino.delregno@collabora.com>
References: <20250506091736.125733-1-angelogioacchino.delregno@collabora.com>
Message-ID: <20250506091736.125733-2-angelogioacchino.delregno@collabora.com>

The following changes since commit 0af2f6be1b4281385b618cb86ad946eded089ac8:

  Linux 6.15-rc1 (2025-04-06 13:11:33 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux.git tags/mtk-soc-for-v6.16

for you to fetch changes up to 69d63d19eda7792052f5f694f154898fc00d60ae:

  soc: mediatek: mtk-dvfsrc: remove an unused variable (2025-04-24 09:15:01 +0200)

----------------------------------------------------------------
MediaTek driver updates for v6.16

This brings some cleanups to the MediaTek DVFSRC driver, commonizing
the bandwidth constraints platform data, and also adds support for
the DVFSRC hardware found in the MediaTek Dimensity 1200 MT6893 SoC.

----------------------------------------------------------------
AngeloGioacchino Del Regno (3):
      dt-bindings: soc: mediatek: dvfsrc: Add support for MT6893
      soc: mediatek: mtk-dvfsrc: Rename and move bw constraints data
      soc: mediatek: mtk-dvfsrc: Add support for Dimensity 1200 MT6893

Arnd Bergmann (1):
      soc: mediatek: mtk-dvfsrc: remove an unused variable

 Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml |  1 +
 drivers/soc/mediatek/mtk-dvfsrc.c                                          | 53 +++++++++++++++++++++++++++++++++++++++++++----------
 2 files changed, 44 insertions(+), 10 deletions(-)



From amergnat at baylibre.com  Tue May  6 02:30:08 2025
From: amergnat at baylibre.com (Alexandre Mergnat)
Date: Tue, 6 May 2025 11:30:08 +0200
Subject: [PATCH] arm64: dts: mediatek: mt6357: Drop regulator-fixed
 compatibles
In-Reply-To: <174652097090.119919.16240846809714782858.b4-ty@collabora.com>
References: <20250502-mt6357-regulator-fixed-compatibles-removal-v1-1-a582c16743fe@collabora.com>
 <174652097090.119919.16240846809714782858.b4-ty@collabora.com>
Message-ID: <99febf26-2ada-4fed-b4b3-596ac4abf581@baylibre.com>

Hello N?colas and Angelo,

On 06/05/2025 10:42, AngeloGioacchino Del Regno wrote:
> On Fri, 02 May 2025 11:32:10 -0400, N?colas F. R. A. Prado wrote:
>> Some of the regulators in the MT6357 PMIC dtsi have compatible set to
>> regulator-fixed, even though they don't serve any purpose: all those
>> regulators are handled as a whole by the mt6357-regulator driver. In
>> fact this is the only dtsi in this family of chips where this is the
>> case: mt6359 and mt6358 don't have any such compatibles.
>>
>> A side-effect caused by this is that the DT kselftest, which is supposed
>> to identify nodes with compatibles that can be probed, but haven't,
>> shows these nodes as failures.
>>
>> [...]
> 
> Applied to v6.15-next/dts64, thanks!
> 
> [1/1] arm64: dts: mediatek: mt6357: Drop regulator-fixed compatibles
>        commit: d77e89b7b03fb945b4353f2dcc4a70b34baa7bcb

I'm surprised that patch is applied after the Rob's bot reply.
Also, I've some concern:

On 02/05/2025 17:32, N?colas F. R. A. Prado wrote:
 > Some of the regulators in the MT6357 PMIC dtsi have compatible set to
 > regulator-fixed, even though they don't serve any purpose: all those
 > regulators are handled as a whole by the mt6357-regulator driver. In
 > fact this is the only dtsi in this family of chips where this is the
 > case: mt6359 and mt6358 don't have any such compatibles.
This is the only dtsi in this family to do this, yes. But according to
all other vendor DTSI, which use regulator-fixed when a regulator can't
support a range of voltage, IMHO, it make sense to use it, isn't it ?
If other DTSI from the family of chips doesn't, why don't fix them to be
aligned with the other families?

 >
 > A side-effect caused by this is that the DT kselftest, which is supposed
 > to identify nodes with compatibles that can be probed, but haven't,
 > shows these nodes as failures.
 >
I lack of data about kselftest, but according to what is reported here, it
appear to me this is something which could be fixed in the test itself. It make
sense for a DTS, but not for a DTSI because it expose HW capability of a
device, not the board, so it isn't mandatory to probe all DTSI node.
Again, I'm not an expert, the test shouldn't show the DTSI node as failure,
but maybe more a warning.

 > Remove the useless compatibles to move the dtsi in line with the others
 > in its family and fix the DT kselftest failures.
If you remove compatible from these regulators, I think mediatek,mt6357-regulator.yaml
documentation file should be modified to be consistent and avoid dt-check error.

> 
> Cheers,
> Angelo
> 
> 

-- 
Regards,
Alexandre


From julien.massot at collabora.com  Tue May  6 03:03:47 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Tue, 06 May 2025 12:03:47 +0200
Subject: [PATCH 2/4] dt-bindings: iommu: mediatek: mt8195 Accept up to 5
 interrupts
In-Reply-To: <cb715936-3a44-4002-8d64-565f8d31820c@collabora.com>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
	 <20250505-mt8395-dtb-errors-v1-2-9c4714dcdcdb@collabora.com>
	 <cb715936-3a44-4002-8d64-565f8d31820c@collabora.com>
Message-ID: <2d3a8e55105526c999b490a2e92dd448c099faab.camel@collabora.com>

Hi Angelo,

On Tue, 2025-05-06 at 10:34 +0200, AngeloGioacchino Del Regno wrote:
> Il 05/05/25 15:23, Julien Massot ha scritto:
> > Some Mediatek IOMMU can have up to five interrupts so increase
> > the 'maxItems' to 5.
> > 
> > Fix the following dtb-check error:
> > 
> > mediatek/mt8395-radxa-nio-12l.dtb: infra-iommu at 10315000: interrupts:
> > [[0, 795, 4, 0], [0, 796, 4, 0], [0, 797, 4, 0], [0, 798, 4, 0], [0, 799, 4, 0]] is too long
> > 
> > Fixes: 3b5838d1d82e3 ("arm64: dts: mt8195: Add iommu and smi nodes")
> > Signed-off-by: Julien Massot <julien.massot at collabora.com>
> > ---
> > ? Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 3 ++-
> > ? 1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > index 75750c64157c868725c087500ac81be4e282c829..035941c2db32170e9a69a5363d8c05ef767bb251 100644
> > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > @@ -97,7 +97,8 @@ properties:
> > ????? maxItems: 1
> > ? 
> > ??? interrupts:
> > -??? maxItems: 1
> > +??? minItems: 1
> 
> Isn't minItems already implicitly 1? :-)
> 
> Looks not, from my understanding if 'minItems' is omitted then
dt-schema is setting it to 'maxItems'.
https://github.com/devicetree-org/dt-schema/blob/v2025.02/dtschema/fixups.py#L129

And you will have an error for a one item interrupts:
Documentation/devicetree/bindings/iommu/mediatek,iommu.example.dtb: iommu at 10205000: interrupts: [[0,
139, 8]] is too short

Regards,
Julien


From angelogioacchino.delregno at collabora.com  Tue May  6 03:20:46 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 6 May 2025 12:20:46 +0200
Subject: [PATCH 2/4] dt-bindings: iommu: mediatek: mt8195 Accept up to 5
 interrupts
In-Reply-To: <2d3a8e55105526c999b490a2e92dd448c099faab.camel@collabora.com>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
 <20250505-mt8395-dtb-errors-v1-2-9c4714dcdcdb@collabora.com>
 <cb715936-3a44-4002-8d64-565f8d31820c@collabora.com>
 <2d3a8e55105526c999b490a2e92dd448c099faab.camel@collabora.com>
Message-ID: <c8bb938d-5a43-47a2-b7de-695f95b077ad@collabora.com>

Il 06/05/25 12:03, Julien Massot ha scritto:
> Hi Angelo,
> 
> On Tue, 2025-05-06 at 10:34 +0200, AngeloGioacchino Del Regno wrote:
>> Il 05/05/25 15:23, Julien Massot ha scritto:
>>> Some Mediatek IOMMU can have up to five interrupts so increase
>>> the 'maxItems' to 5.
>>>
>>> Fix the following dtb-check error:
>>>
>>> mediatek/mt8395-radxa-nio-12l.dtb: infra-iommu at 10315000: interrupts:
>>> [[0, 795, 4, 0], [0, 796, 4, 0], [0, 797, 4, 0], [0, 798, 4, 0], [0, 799, 4, 0]] is too long
>>>
>>> Fixes: 3b5838d1d82e3 ("arm64: dts: mt8195: Add iommu and smi nodes")
>>> Signed-off-by: Julien Massot <julien.massot at collabora.com>
>>> ---
>>>  ? Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 3 ++-
>>>  ? 1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
>>> b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
>>> index 75750c64157c868725c087500ac81be4e282c829..035941c2db32170e9a69a5363d8c05ef767bb251 100644
>>> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
>>> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
>>> @@ -97,7 +97,8 @@ properties:
>>>  ????? maxItems: 1
>>>    
>>>  ??? interrupts:
>>> -??? maxItems: 1
>>> +??? minItems: 1
>>
>> Isn't minItems already implicitly 1? :-)
>>
>> Looks not, from my understanding if 'minItems' is omitted then
> dt-schema is setting it to 'maxItems'.
> https://github.com/devicetree-org/dt-schema/blob/v2025.02/dtschema/fixups.py#L129
> 
> And you will have an error for a one item interrupts:
> Documentation/devicetree/bindings/iommu/mediatek,iommu.example.dtb: iommu at 10205000: interrupts: [[0,
> 139, 8]] is too short
> 

Whoops, you're right.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>




From pchelkin at ispras.ru  Tue May  6 04:55:39 2025
From: pchelkin at ispras.ru (Fedor Pchelkin)
Date: Tue,  6 May 2025 14:55:39 +0300
Subject: [PATCH] wifi: mt76: disable napi on driver removal
Message-ID: <20250506115540.19045-1-pchelkin@ispras.ru>

A warning on driver removal started occurring after commit 9dd05df8403b
("net: warn if NAPI instance wasn't shut down"). Disable tx napi before
deleting it in mt76_dma_cleanup().

 WARNING: CPU: 4 PID: 18828 at net/core/dev.c:7288 __netif_napi_del_locked+0xf0/0x100
 CPU: 4 UID: 0 PID: 18828 Comm: modprobe Not tainted 6.15.0-rc4 #4 PREEMPT(lazy)
 Hardware name: ASUS System Product Name/PRIME X670E-PRO WIFI, BIOS 3035 09/05/2024
 RIP: 0010:__netif_napi_del_locked+0xf0/0x100
 Call Trace:
 <TASK>
 mt76_dma_cleanup+0x54/0x2f0 [mt76]
 mt7921_pci_remove+0xd5/0x190 [mt7921e]
 pci_device_remove+0x47/0xc0
 device_release_driver_internal+0x19e/0x200
 driver_detach+0x48/0x90
 bus_remove_driver+0x6d/0xf0
 pci_unregister_driver+0x2e/0xb0
 __do_sys_delete_module.isra.0+0x197/0x2e0
 do_syscall_64+0x7b/0x160
 entry_SYSCALL_64_after_hwframe+0x76/0x7e

Tested with mt7921e but the same pattern can be actually applied to other
mt76 drivers calling mt76_dma_cleanup() during removal. Tx napi is enabled
in their *_dma_init() functions and only toggled off and on again inside
their suspend/resume/reset paths. So it should be okay to disable tx
napi in such a generic way.

Found by Linux Verification Center (linuxtesting.org).

Fixes: 2ac515a5d74f ("mt76: mt76x02: use napi polling for tx cleanup")
Cc: stable at vger.kernel.org
Signed-off-by: Fedor Pchelkin <pchelkin at ispras.ru>
---
 drivers/net/wireless/mediatek/mt76/dma.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/wireless/mediatek/mt76/dma.c b/drivers/net/wireless/mediatek/mt76/dma.c
index 844af16ee551..35b4ec91979e 100644
--- a/drivers/net/wireless/mediatek/mt76/dma.c
+++ b/drivers/net/wireless/mediatek/mt76/dma.c
@@ -1011,6 +1011,7 @@ void mt76_dma_cleanup(struct mt76_dev *dev)
 	int i;
 
 	mt76_worker_disable(&dev->tx_worker);
+	napi_disable(&dev->tx_napi);
 	netif_napi_del(&dev->tx_napi);
 
 	for (i = 0; i < ARRAY_SIZE(dev->phys); i++) {
-- 
2.49.0



From patchwork-bot+netdevbpf at kernel.org  Tue May  6 05:00:34 2025
From: patchwork-bot+netdevbpf at kernel.org (patchwork-bot+netdevbpf at kernel.org)
Date: Tue, 06 May 2025 12:00:34 +0000
Subject: [PATCH net v2 1/2] net: ethernet: mtk_eth_soc: reset all TX queues
 on DMA free
In-Reply-To: <c9ff9adceac4f152239a0f65c397f13547639175.1746406763.git.daniel@makrotopia.org>
References: <c9ff9adceac4f152239a0f65c397f13547639175.1746406763.git.daniel@makrotopia.org>
Message-ID: <174653283451.1493761.12837257504091062082.git-patchwork-notify@kernel.org>

Hello:

This series was applied to netdev/net.git (main)
by Paolo Abeni <pabeni at redhat.com>:

On Mon, 5 May 2025 02:07:32 +0100 you wrote:
> The purpose of resetting the TX queue is to reset the byte and packet
> count as well as to clear the software flow control XOFF bit.
> 
> MediaTek developers pointed out that netdev_reset_queue would only
> resets queue 0 of the network device.
> 
> Queues that are not reset may cause unexpected issues.
> 
> [...]

Here is the summary with links:
  - [net,v2,1/2] net: ethernet: mtk_eth_soc: reset all TX queues on DMA free
    https://git.kernel.org/netdev/net/c/4db6c75124d8
  - [net,v2,2/2] net: ethernet: mtk_eth_soc: do not reset PSE when setting FE
    https://git.kernel.org/netdev/net/c/e8716b5b0dff

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html




From peter.wang at mediatek.com  Tue May  6 05:39:34 2025
From: peter.wang at mediatek.com (peter.wang at mediatek.com)
Date: Tue, 6 May 2025 20:39:34 +0800
Subject: [PATCH v1] ufs: core: fix hwq_id type and value
Message-ID: <20250506124038.4071609-1-peter.wang@mediatek.com>

From: Peter Wang <peter.wang at mediatek.com>

Because the member id of struct ufs_hw_queue is u32 (hwq->id) and
the trace entry hwq_id is also u32, the type should be changed to u32.
If mcq is not supported, SDB mode only supports one hardware queue,
for which setting the hwq_id to 0 is more suitable.

Fixes: 4a52338bf288 ("scsi: ufs: core: Add trace event for MCQ")
Cc: <stable at vger.kernel.org>
Signed-off-by: Peter Wang <peter.wang at mediatek.com>
---
 drivers/ufs/core/ufshcd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 7735421e3991..14e4cfbcb9eb 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -432,7 +432,7 @@ static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
 	u8 opcode = 0, group_id = 0;
 	u32 doorbell = 0;
 	u32 intr;
-	int hwq_id = -1;
+	u32 hwq_id = 0;
 	struct ufshcd_lrb *lrbp = &hba->lrb[tag];
 	struct scsi_cmnd *cmd = lrbp->cmd;
 	struct request *rq = scsi_cmd_to_rq(cmd);
-- 
2.45.2



From cjd at cjdns.fr  Tue May  6 07:25:41 2025
From: cjd at cjdns.fr (Caleb James DeLisle)
Date: Tue, 6 May 2025 16:25:41 +0200
Subject: [PATCH v4 2/7] clocksource/drivers: Add EcoNet Timer HPT driver
In-Reply-To: <7c08cc9e-f39f-490c-85fe-5738656380e5@linaro.org>
References: <20250430133433.22222-1-cjd@cjdns.fr>
 <20250430133433.22222-3-cjd@cjdns.fr> <aBjpBpJAIP89oiit@mai.linaro.org>
 <92cd3689-3409-4d43-8db1-8633d35f779a@cjdns.fr>
 <7c08cc9e-f39f-490c-85fe-5738656380e5@linaro.org>
Message-ID: <ea17e686-68c7-463c-bb9e-bcc9e59a929d@cjdns.fr>


On 06/05/2025 10:54, Daniel Lezcano wrote:
> On 05/05/2025 20:09, Caleb James DeLisle wrote:
>>
>> On 05/05/2025 18:36, Daniel Lezcano wrote:
>>> On Wed, Apr 30, 2025 at 01:34:28PM +0000, Caleb James DeLisle wrote:
>>>> Introduce a clocksource driver for the so-called high-precision 
>>>> timer (HPT)
>>>> in the EcoNet EN751221 MIPS SoC.
>>> As a new driver, please document the timer (up - down ?, SPI/PPI, etc
>>> ...) that will help to understand the code more easily, especially the
>>> reg_* functions (purposes?).
>>
>>
>> Sure thing, I can elaborate the comment in the header of
>> timer-econet-en751221.c. Let me know if you'd like it described
>> somewhere else as well, such as the help of config 
>> ECONET_EN751221_TIMER.
>
> It is ok in the changelog, so it is possible to get the description 
> when looking for the patch introducing the new timer.


Sounds good.


>
> [ ... ]
>
>>>> +
>>>> +??? cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING,
>>>> +????????????? "clockevents/en75/timer:starting",
>>>> +????????????? cevt_init_cpu, NULL);
>>> cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, ... ) ?
>>
>> I see that Ingenic does this. This is the only timer so until it's up,
>> sleeping causes a hang. If sleeping is prior to CPUHP_AP_ONLINE_DYN is
>> considered a bug then this should be okay, but I'm not informed enough
>> to say whether that is the case so I'll follow your guidance here.
>
> Hmm, hard to say without the platform. May be just give a try with 
> CPUHP_AP_ONLINE_DYN to check if it works otherwise stick on 
> CPUHP_AP_MIPS_GIC_TIMER_STARTING as it is already defined ?


I need a little time for this because I only got SMP on this processor

some time ago in a PoC so I'll need to put that back together in order

to validate the change.


Thanks,

Caleb


>
> [ ... ]
>
>


From bvanassche at acm.org  Tue May  6 09:15:02 2025
From: bvanassche at acm.org (Bart Van Assche)
Date: Tue, 6 May 2025 09:15:02 -0700
Subject: [PATCH v1] ufs: core: fix hwq_id type and value
In-Reply-To: <20250506124038.4071609-1-peter.wang@mediatek.com>
References: <20250506124038.4071609-1-peter.wang@mediatek.com>
Message-ID: <04fc1549-0fa6-4956-b522-df5fbc26100c@acm.org>

On 5/6/25 5:39 AM, peter.wang at mediatek.com wrote:
> From: Peter Wang <peter.wang at mediatek.com>
> 
> Because the member id of struct ufs_hw_queue is u32 (hwq->id) and
> the trace entry hwq_id is also u32, the type should be changed to u32.
> If mcq is not supported, SDB mode only supports one hardware queue,
> for which setting the hwq_id to 0 is more suitable.
> 
> Fixes: 4a52338bf288 ("scsi: ufs: core: Add trace event for MCQ")
> Cc: <stable at vger.kernel.org>
> Signed-off-by: Peter Wang <peter.wang at mediatek.com>
> ---
>   drivers/ufs/core/ufshcd.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
> index 7735421e3991..14e4cfbcb9eb 100644
> --- a/drivers/ufs/core/ufshcd.c
> +++ b/drivers/ufs/core/ufshcd.c
> @@ -432,7 +432,7 @@ static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
>   	u8 opcode = 0, group_id = 0;
>   	u32 doorbell = 0;
>   	u32 intr;
> -	int hwq_id = -1;
> +	u32 hwq_id = 0;
>   	struct ufshcd_lrb *lrbp = &hba->lrb[tag];
>   	struct scsi_cmnd *cmd = lrbp->cmd;
>   	struct request *rq = scsi_cmd_to_rq(cmd);

Is this change really necessary? I like the current behavior because it
makes it easy to figure out whether or not MCQ has been enabled. Even if
others would agree with this change, I think that the "Fixes:" and "Cc:
stable" tags are overkill because I don't see this as a bug fix but
rather as a behavior change that is not a bug fix.

Thanks,

Bart.


From conor at kernel.org  Tue May  6 09:30:22 2025
From: conor at kernel.org (Conor Dooley)
Date: Tue, 6 May 2025 17:30:22 +0100
Subject: [PATCH 1/2] dt-bindings: mfd: syscon: Add
 mediatek,mt8365-infracfg-nao
In-Reply-To: <20250502-mt8365-infracfg-nao-compatible-v1-1-e40394573f98@collabora.com>
References: <20250502-mt8365-infracfg-nao-compatible-v1-0-e40394573f98@collabora.com>
 <20250502-mt8365-infracfg-nao-compatible-v1-1-e40394573f98@collabora.com>
Message-ID: <20250506-safeguard-brisket-96da510a99d3@spud>

On Fri, May 02, 2025 at 12:43:21PM -0400, N?colas F. R. A. Prado wrote:
> The register space described by DT node of compatible
> mediatek,mt8365-infracfg-nao exposes a variety of unrelated registers,
> including registers for controlling bus protection on the MT8365 SoC,
> which is used by the power domain controller through a syscon.
> 
> Add this compatible to the syscon binding.
> 
> Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>

Acked-by: Conor Dooley <conor.dooley at microchip.com>
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From lorenzo at kernel.org  Tue May  6 09:56:47 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Tue, 06 May 2025 18:56:47 +0200
Subject: [PATCH net v5] net: airoha: Add missing field to ppe_mbox_data
 struct
Message-ID: <20250506-airoha-en7581-fix-ppe_mbox_data-v5-1-29cabed6864d@kernel.org>

The official Airoha EN7581 firmware requires adding max_packet field in
ppe_mbox_data struct while the unofficial one used to develop the Airoha
EN7581 flowtable support does not require this field.
This patch does not introduce any real backwards compatible issue since
EN7581 fw is not publicly available in linux-firmware or other
repositories (e.g. OpenWrt) yet and the official fw version will use this
new layout. For this reason this change needs to be backported.
Moreover, make explicit the padding added by the compiler introducing
the rsv array in init_info struct.
At the same time use u32 instead of int for init_info and set_info
struct definitions in ppe_mbox_data struct.

Fixes: 23290c7bc190d ("net: airoha: Introduce Airoha NPU support")
Reviewed-by: Simon Horman <horms at kernel.org>
Reviewed-by: Jacob Keller <jacob.e.keller at intel.com>
Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
Changes in v5:
- get rid of __packed attribute
- fix typo in the commit subject
- Link to v4: https://lore.kernel.org/r/20250429-airoha-en7581-fix-ppe_mbox_data-v4-1-d2a8b901dad0 at kernel.org

Changes in v4:
- use u32 instead of int in ppe_mbox_data struct
- add __packed attribute to struct definitions and make the fw layout
  padding explicit in init_info struct
- Link to v3: https://lore.kernel.org/r/20250422-airoha-en7581-fix-ppe_mbox_data-v3-1-87dd50d2956e at kernel.org

Changes in v3:
- resend targeting net tree
- Link to v2: https://lore.kernel.org/r/20250417-airoha-en7581-fix-ppe_mbox_data-v2-1-43433cfbe874 at kernel.org

Changes in v2:
- Add more details to commit log
- Link to v1: https://lore.kernel.org/r/20250415-airoha-en7581-fix-ppe_mbox_data-v1-1-4408c60ba964 at kernel.org
---
 drivers/net/ethernet/airoha/airoha_npu.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_npu.c b/drivers/net/ethernet/airoha/airoha_npu.c
index 7a5710f9ccf6a4a4f555ab63d67cb6b318de9b52..ead0625e781f57cd7c5883b6dd3d441db62292d3 100644
--- a/drivers/net/ethernet/airoha/airoha_npu.c
+++ b/drivers/net/ethernet/airoha/airoha_npu.c
@@ -104,12 +104,14 @@ struct ppe_mbox_data {
 			u8 xpon_hal_api;
 			u8 wan_xsi;
 			u8 ct_joyme4;
-			int ppe_type;
-			int wan_mode;
-			int wan_sel;
+			u8 max_packet;
+			u8 rsv[3];
+			u32 ppe_type;
+			u32 wan_mode;
+			u32 wan_sel;
 		} init_info;
 		struct {
-			int func_id;
+			u32 func_id;
 			u32 size;
 			u32 data;
 		} set_info;

---
base-commit: e8716b5b0dff1b3d523b4a83fd5e94d57b887c5c
change-id: 20250422-airoha-en7581-fix-ppe_mbox_data-56df12d4df72

Best regards,
-- 
Lorenzo Bianconi <lorenzo at kernel.org>



From luca.ceresoli at bootlin.com  Tue May  6 13:47:20 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Tue, 6 May 2025 22:47:20 +0200
Subject: [PATCH v2 30/34] drm/bridge: imx8qxp-pixel-combiner: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <f71d18d2-4271-4bb9-b54f-0e5a585778f3@nxp.com>
References: <20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b@bootlin.com>
	<20250424-drm-bridge-convert-to-alloc-api-v2-30-8f91a404d86b@bootlin.com>
	<553d62ed-976a-4e17-9678-cdc3d40ce4a7@nxp.com>
	<20250430112944.1b39caab@booty>
	<f71d18d2-4271-4bb9-b54f-0e5a585778f3@nxp.com>
Message-ID: <20250506224720.5cbcf3e1@booty>

Hello Liu,

thanks for your further feedback.

On Tue, 6 May 2025 10:24:18 +0800
Liu Ying <victor.liu at nxp.com> wrote:

> On 04/30/2025, Luca Ceresoli wrote:
> > Hello Liu,  
> 
> Hi Luca,
> 
> > 
> > On Tue, 29 Apr 2025 10:10:55 +0800
> > Liu Ying <victor.liu at nxp.com> wrote:
> >   
> >> Hi,
> >>
> >> On 04/25/2025, Luca Ceresoli wrote:  
> >>> This is the new API for allocating DRM bridges.
> >>>
> >>> This driver embeds an array of channels in the main struct, and each
> >>> channel embeds a drm_bridge. This prevents dynamic, refcount-based
> >>> deallocation of the bridges.
> >>>
> >>> To make the new, dynamic bridge allocation possible:
> >>>
> >>>  * change the array of channels into an array of channel pointers
> >>>  * allocate each channel using devm_drm_bridge_alloc()
> >>>  * adapt the code wherever using the channels
> >>>
> >>> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>  
> > 
> > [...]
> >   
> >>> @@ -345,8 +351,8 @@ static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
> >>>  free_child:
> >>>  	of_node_put(child);
> >>>  
> >>> -	if (i == 1 && pc->ch[0].next_bridge)
> >>> -		drm_bridge_remove(&pc->ch[0].bridge);
> >>> +	if (i == 1 && pc->ch[0]->next_bridge)    
> >>
> >> Since this patch makes pc->ch[0] and pc->ch[1] be allocated separately,
> >> pc->ch[0] could be NULL if channel0 is not available, hence a NULL pointer
> >> dereference here...  
> > 
> > See below for this.
> >   
> >>> +		drm_bridge_remove(&pc->ch[0]->bridge);
> >>>  
> >>>  	pm_runtime_disable(dev);
> >>>  	return ret;
> >>> @@ -359,7 +365,7 @@ static void imx8qxp_pc_bridge_remove(struct platform_device *pdev)
> >>>  	int i;
> >>>  
> >>>  	for (i = 0; i < 2; i++) {
> >>> -		ch = &pc->ch[i];
> >>> +		ch = pc->ch[i];
> >>>  
> >>>  		if (!ch->is_available)    
> >>
> >> ...and here too.  
> > 
> > This is indeed a bug, I should have checked the pointer for being
> > non-NULL.
> > 
> > Looking at that more closely, I think the is_available flag can be
> > entirely removed now. The allocation itself (ch != NULL) now is
> > equivalent. Do you think my reasoning is correct?
> > 
> > Ouch! After writing the previous paragraph I realized you proposed this
> > a few lines below! OK, removing is_available. :)
> > 
> > [...]
> >   
> >> On top of this patch series, this issue doesn't happen if I apply the below
> >> change:  
> > 
> > [...]
> >   
> >> @@ -351,7 +349,7 @@ static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
> >>  free_child:
> >>         of_node_put(child);
> >>  
> >> -       if (i == 1 && pc->ch[0]->next_bridge)
> >> +       if (i == 1 && pc->ch[0])
> >>                 drm_bridge_remove(&pc->ch[0]->bridge);  
> > 
> > Unrelated to this patch, but as I looked at it more in depth now, I'm
> > not sure this whole logic is robust, even in the original code.
> > 
> > The 'i == 1' check here seems to mean "if some error happened when
> > handling channel at 1, that means channel at 0 was successfully initialized,
> > so let's clean up channel 0".
> > 
> > However my understanding of the bindings is that device tree is allowed
> > to have the channel at 1 node before the channel at 0 node (or even channel at 1
> > without channel at 0, but that's less problematic here).
> > 
> > In such case (channel at 1 before channel at 0), this would happen:
> > 
> >  1. alloc and init ch[1], all OK
> >  2. alloc and init ch[0], an error happens
> >     (e.g. of_graph_get_remote_node() fails)
> > 
> > So we'd reach the free_child: label, and we should call
> > drm_bridge_remove() for ch[1]->bridge, but there's no code to do that.
> > 
> > To be robust in such a case, I think both channels need to be checked
> > independently, as the status of one does not imply the status of the
> > other. E.g.:
> > 
> >   for (i = 0; i < 2; i++)
> >       if (pc->ch[i] && pc->ch[i]->next_bridge)
> >           drm_bridge_remove(&pc->ch[i]->bridge);
> > 
> > (which is similar to what .remove() does after the changes discussed in
> > this thread, and which I have queued for v3)
> > 
> > What's your opinion? Do you think I missed anything?  
> 
> The pixel combiner DT node would be added in imx8-ss-dc{0,1}.dtsi, please
> see the case for imx8-ss-dc0.dtsi introduced by an in-flight patch[1].  As
> channel@{0,1} child nodes always exist(DT overlay cannot effectively delete
> any of them) and channel at 0 always comes first, there is no problematic case.

I'm not questioning what existing and future dts files (will) contain,
and surely I don't see a good reason someone would write channel at 1
before channel at 0.

My point is:

 - the bindings _allow_ channel1 before channel at 0
 - the error management code after the free_child label won't work
   correctly if channel1 is before channel at 0 in the device tree

IOW the driver is not robust against all legal device tree descriptions,
and it could be easily made robust using the example code in my
previous e-mail (quoted a few lines above).

If you agree about this I'll be happy to send a patch doing that change.
If you think I'm wrong, I won't fight a battle. This topic is
orthogonal to the change I'm introducing in this patch, and I can
continue the conversion independently from this discussion.

> > Thanks for taking the time to dig into this!  
> 
> After looking into this patch and patch 31(though I've already provided my A-b)
> more closely, I think the imx8qxp_pc and imx8{qm,qxp}_ldb main structures
> should have the same life time with the embedded DRM bridges, because for
> example the clk_apb clock in struct imx8qxp_pc would be accessed by the
> imx8qxp_pc_bridge_mode_set DRM bridge callback.  But, IIUC, your patches extend
> the life time for the embedded channel/bridge structures only, but not for the
> main structures.  What do you think ?

I see you concern, but I'm sure the change I'm introducing is not
creating the problem you are concerned about.

The key aspect is that my patch is merely changing the lifetime of the
_allocation_ of the drm_bridge, not its usage. On drm_bridge_remove()
the bridge is removed from its encoder chain and it is completely not
reachable, both before and after my patch. With my patch it is not
freed immediately, but it's just a piece of "wasted" memory that is
still allocated until elsewhere in the kernel there are pointers to it,
to avoid use-after-free.

With this explanation, do you think my patch is correct (after fixing
the bug we already discussed of course)?

Best regards,
Luca

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


From nfraprado at collabora.com  Tue May  6 14:20:58 2025
From: nfraprado at collabora.com (=?utf-8?B?TsOtY29sYXMgRi4gUi4gQS4=?= Prado)
Date: Tue, 6 May 2025 17:20:58 -0400
Subject: [PATCH] arm64: dts: mediatek: mt6357: Drop regulator-fixed
 compatibles
In-Reply-To: <99febf26-2ada-4fed-b4b3-596ac4abf581@baylibre.com>
References: <20250502-mt6357-regulator-fixed-compatibles-removal-v1-1-a582c16743fe@collabora.com>
 <174652097090.119919.16240846809714782858.b4-ty@collabora.com>
 <99febf26-2ada-4fed-b4b3-596ac4abf581@baylibre.com>
Message-ID: <1e8b80c9-d491-4b71-b424-e2322c711fd3@notapiano>

On Tue, May 06, 2025 at 11:30:08AM +0200, Alexandre Mergnat wrote:
> Hello N?colas and Angelo,
> 
> On 06/05/2025 10:42, AngeloGioacchino Del Regno wrote:
> > On Fri, 02 May 2025 11:32:10 -0400, N?colas F. R. A. Prado wrote:
> > > Some of the regulators in the MT6357 PMIC dtsi have compatible set to
> > > regulator-fixed, even though they don't serve any purpose: all those
> > > regulators are handled as a whole by the mt6357-regulator driver. In
> > > fact this is the only dtsi in this family of chips where this is the
> > > case: mt6359 and mt6358 don't have any such compatibles.
> > > 
> > > A side-effect caused by this is that the DT kselftest, which is supposed
> > > to identify nodes with compatibles that can be probed, but haven't,
> > > shows these nodes as failures.
> > > 
> > > [...]
> > 
> > Applied to v6.15-next/dts64, thanks!
> > 
> > [1/1] arm64: dts: mediatek: mt6357: Drop regulator-fixed compatibles
> >        commit: d77e89b7b03fb945b4353f2dcc4a70b34baa7bcb
> 
> I'm surprised that patch is applied after the Rob's bot reply.
> Also, I've some concern:
> 
> On 02/05/2025 17:32, N?colas F. R. A. Prado wrote:
> > Some of the regulators in the MT6357 PMIC dtsi have compatible set to
> > regulator-fixed, even though they don't serve any purpose: all those
> > regulators are handled as a whole by the mt6357-regulator driver. In
> > fact this is the only dtsi in this family of chips where this is the
> > case: mt6359 and mt6358 don't have any such compatibles.
> This is the only dtsi in this family to do this, yes. But according to
> all other vendor DTSI, which use regulator-fixed when a regulator can't
> support a range of voltage, IMHO, it make sense to use it, isn't it ?
> If other DTSI from the family of chips doesn't, why don't fix them to be
> aligned with the other families?

Well, but this isn't just like any other regulator-fixed in a DTSI. In this case
it is part of a multi-function device (MFD) and so it gets probed by a parent
node. That's the source of the issue, because then no driver gets assigned to
the node itself.

> 
> >
> > A side-effect caused by this is that the DT kselftest, which is supposed
> > to identify nodes with compatibles that can be probed, but haven't,
> > shows these nodes as failures.
> >
> I lack of data about kselftest, but according to what is reported here, it
> appear to me this is something which could be fixed in the test itself. It make
> sense for a DTS, but not for a DTSI because it expose HW capability of a
> device, not the board, so it isn't mandatory to probe all DTSI node.
> Again, I'm not an expert, the test shouldn't show the DTSI node as failure,
> but maybe more a warning.

The DT kselftest is a run-time test, so it wouldn't be able to distinguish
between DTSI and DTS. But in any case, we do want to check that devices from
DTSIs have probed, a lot of the devices come from them. When a particular board
doesn't actually have a node from a DTSI present then the node should be
disabled, and in that case the kselftest ignores the node.

It would be possible to ignore this particular compatible, "regulator-fixed", in
the kselftest, if it is a compatible that can't be expected to be probed. Of
course that would mean that all the other regulator nodes that aren't MFD
children and do get probed by that driver would no longer be checked by the
test.

> 
> > Remove the useless compatibles to move the dtsi in line with the others
> > in its family and fix the DT kselftest failures.
> If you remove compatible from these regulators, I think mediatek,mt6357-regulator.yaml
> documentation file should be modified to be consistent and avoid dt-check error.

Ah, yes, totally agreed, I seem to have missed running dtbs_check on this patch,
sorry. Indeed now either the binding needs to be fixed or the patch reverted.

I believe the most reasonable option would be to update those regulators in the
binding to reference the generic regulator binding, ie:

diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml
index 6327bb2f6ee0..9308008f420e 100644
--- a/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml
@@ -33,7 +33,7 @@ patternProperties:

   "^ldo-v(camio18|aud28|aux18|io18|io28|rf12|rf18|cn18|cn28|fe28)$":
     type: object
-    $ref: fixed-regulator.yaml#
+    $ref: regulator.yaml#
     unevaluatedProperties: false
     description:
       Properties for single fixed LDO regulator.

as well as updating the examples in the YAML. The fixed-regulator.yaml binding
doesn't seem to provide any additional checks compared to regulator.yaml,
besides enforcing the regulator-fixed compatible, which in this case doesn't
serve any purpose.

Thoughts?

Thanks,
N?colas


From broonie at kernel.org  Tue May  6 17:49:02 2025
From: broonie at kernel.org (Mark Brown)
Date: Wed, 07 May 2025 09:49:02 +0900
Subject: [PATCH] ASoC: mediatek: mt8188-mt6359: select
 CONFIG_SND_SOC_MT6359_ACCDET
In-Reply-To: <20250505052106.1811802-1-arnd@kernel.org>
References: <20250505052106.1811802-1-arnd@kernel.org>
Message-ID: <174657894243.4155013.16755704226665079789.b4-ty@kernel.org>

On Mon, 05 May 2025 07:20:52 +0200, Arnd Bergmann wrote:
> The driver support was added without selecting the codec, which leads to
> a link failure:
> 
> aarch64-linux-ld: sound/soc/mediatek/mt8188/mt8188-mt6359.o: in function `mt8188_mt6359_init':
> mt8188-mt6359.c:(.text+0x19f0): undefined reference to `mt6359_accdet_enable_jack_detect'
> 
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[1/1] ASoC: mediatek: mt8188-mt6359: select CONFIG_SND_SOC_MT6359_ACCDET
      commit: b19fa45715ce9cfcc597ed140df31115e969b39d

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark



From harry.yoo at oracle.com  Tue May  6 18:12:16 2025
From: harry.yoo at oracle.com (Harry Yoo)
Date: Wed, 7 May 2025 10:12:16 +0900
Subject: [PATCH] mm: Add Kcompressd for accelerated memory compression
In-Reply-To: <20250430082651.3152444-1-qun-wei.lin@mediatek.com>
References: <20250430082651.3152444-1-qun-wei.lin@mediatek.com>
Message-ID: <aBqzcIteOzC9mRjY@harry>

On Wed, Apr 30, 2025 at 04:26:41PM +0800, Qun-Wei Lin wrote:
> This patch series introduces a new mechanism called kcompressd to
> improve the efficiency of memory reclaiming in the operating system.
> 
> Problem:
>   In the current system, the kswapd thread is responsible for both scanning
>   the LRU pages and handling memory compression tasks (such as those
>   involving ZSWAP/ZRAM, if enabled). This combined responsibility can lead
>   to significant performance bottlenecks, especially under high memory
>   pressure. The kswapd thread becomes a single point of contention, causing
>   delays in memory reclaiming and overall system performance degradation.
> 
> Solution:
>   Introduced kcompressd to handle asynchronous compression during memory
>   reclaim, improving efficiency by offloading compression tasks from
>   kswapd. This allows kswapd to focus on its primary task of page reclaim
>   without being burdened by the additional overhead of compression.
> 
> In our handheld devices, we found that applying this mechanism under high
> memory pressure scenarios can increase the rate of pgsteal_anon per second
> by over 260% compared to the situation with only kswapd. Additionally, we
> observed a reduction of over 50% in page allocation stall occurrences,
> further demonstrating the effectiveness of kcompressd in alleviating memory
> pressure and improving system responsiveness.
> 
> Co-developed-by: Barry Song <21cnbao at gmail.com>
> Signed-off-by: Barry Song <21cnbao at gmail.com>
> Signed-off-by: Qun-Wei Lin <qun-wei.lin at mediatek.com>
> Reference: Re: [PATCH 0/2] Improve Zram by separating compression context from kswapd - Barry Song
>            https://lore.kernel.org/lkml/20250313093005.13998-1-21cnbao at gmail.com/
> ---

+Cc Zi Yan, who might be interested in writing a framework (or improving
the existing one, padata) for parallelizing jobs (e.g. migration/compression)

>  include/linux/mmzone.h |  6 ++++
>  mm/mm_init.c           |  1 +
>  mm/page_io.c           | 71 ++++++++++++++++++++++++++++++++++++++++++
>  mm/swap.h              |  6 ++++
>  mm/vmscan.c            | 25 +++++++++++++++
>  5 files changed, 109 insertions(+)
> 
> diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
> index 6ccec1bf2896..93c9195a54ae 100644
> --- a/include/linux/mmzone.h
> +++ b/include/linux/mmzone.h
> @@ -23,6 +23,7 @@
>  #include <linux/page-flags.h>
>  #include <linux/local_lock.h>
>  #include <linux/zswap.h>
> +#include <linux/kfifo.h>
>  #include <asm/page.h>
>  
>  /* Free memory management - zoned buddy allocator.  */
> @@ -1398,6 +1399,11 @@ typedef struct pglist_data {
>  
>  	int kswapd_failures;		/* Number of 'reclaimed == 0' runs */
>  
> +#define KCOMPRESS_FIFO_SIZE 256
> +	wait_queue_head_t kcompressd_wait;
> +	struct task_struct *kcompressd;
> +	struct kfifo kcompress_fifo;
> +
>  #ifdef CONFIG_COMPACTION
>  	int kcompactd_max_order;
>  	enum zone_type kcompactd_highest_zoneidx;
> diff --git a/mm/mm_init.c b/mm/mm_init.c
> index 9659689b8ace..49bae1dd4584 100644
> --- a/mm/mm_init.c
> +++ b/mm/mm_init.c
> @@ -1410,6 +1410,7 @@ static void __meminit pgdat_init_internals(struct pglist_data *pgdat)
>  	pgdat_init_kcompactd(pgdat);
>  
>  	init_waitqueue_head(&pgdat->kswapd_wait);
> +	init_waitqueue_head(&pgdat->kcompressd_wait);
>  	init_waitqueue_head(&pgdat->pfmemalloc_wait);
>  
>  	for (i = 0; i < NR_VMSCAN_THROTTLE; i++)
> diff --git a/mm/page_io.c b/mm/page_io.c
> index 4bce19df557b..d85deb494a6a 100644
> --- a/mm/page_io.c
> +++ b/mm/page_io.c
> @@ -233,6 +233,38 @@ static void swap_zeromap_folio_clear(struct folio *folio)
>  	}
>  }
>  
> +static bool swap_sched_async_compress(struct folio *folio)
> +{
> +	struct swap_info_struct *sis = swp_swap_info(folio->swap);
> +	int nid = numa_node_id();
> +	pg_data_t *pgdat = NODE_DATA(nid);
> +
> +	if (unlikely(!pgdat->kcompressd))
> +		return false;
> +
> +	if (!current_is_kswapd())
> +		return false;
> +
> +	if (!folio_test_anon(folio))
> +		return false;
> +	/*
> +	 * This case needs to synchronously return AOP_WRITEPAGE_ACTIVATE
> +	 */
> +	if (!mem_cgroup_zswap_writeback_enabled(folio_memcg(folio)))
> +		return false;
> +
> +	sis = swp_swap_info(folio->swap);
> +	if (zswap_is_enabled() || data_race(sis->flags & SWP_SYNCHRONOUS_IO)) {
> +		if (kfifo_avail(&pgdat->kcompress_fifo) >= sizeof(folio) &&
> +			kfifo_in(&pgdat->kcompress_fifo, &folio, sizeof(folio))) {
> +			wake_up_interruptible(&pgdat->kcompressd_wait);
> +			return true;
> +		}
> +	}
> +
> +	return false;
> +}
> +
>  /*
>   * We may have stale swap cache pages in memory: notice
>   * them here and get rid of the unnecessary final write.
> @@ -275,6 +307,15 @@ int swap_writepage(struct page *page, struct writeback_control *wbc)
>  		 */
>  		swap_zeromap_folio_clear(folio);
>  	}
> +
> +	/*
> +	 * Compression within zswap and zram might block rmap, unmap
> +	 * of both file and anon pages, try to do compression async
> +	 * if possible
> +	 */
> +	if (swap_sched_async_compress(folio))
> +		return 0;
> +
>  	if (zswap_store(folio)) {
>  		count_mthp_stat(folio_order(folio), MTHP_STAT_ZSWPOUT);
>  		folio_unlock(folio);
> @@ -289,6 +330,36 @@ int swap_writepage(struct page *page, struct writeback_control *wbc)
>  	return 0;
>  }
>  
> +int kcompressd(void *p)
> +{
> +	pg_data_t *pgdat = (pg_data_t *)p;
> +	struct folio *folio;
> +	struct writeback_control wbc = {
> +		.sync_mode = WB_SYNC_NONE,
> +		.nr_to_write = SWAP_CLUSTER_MAX,
> +		.range_start = 0,
> +		.range_end = LLONG_MAX,
> +		.for_reclaim = 1,
> +	};
> +
> +	while (!kthread_should_stop()) {
> +		wait_event_interruptible(pgdat->kcompressd_wait,
> +				!kfifo_is_empty(&pgdat->kcompress_fifo));
> +
> +		while (!kfifo_is_empty(&pgdat->kcompress_fifo)) {
> +			if (kfifo_out(&pgdat->kcompress_fifo, &folio, sizeof(folio))) {
> +				if (zswap_store(folio)) {
> +					count_mthp_stat(folio_order(folio), MTHP_STAT_ZSWPOUT);
> +					folio_unlock(folio);
> +					continue;
> +				}
> +				__swap_writepage(folio, &wbc);
> +			}
> +		}
> +	}
> +	return 0;
> +}
> +
>  static inline void count_swpout_vm_event(struct folio *folio)
>  {
>  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> diff --git a/mm/swap.h b/mm/swap.h
> index 6f4a3f927edb..3579da413dc2 100644
> --- a/mm/swap.h
> +++ b/mm/swap.h
> @@ -22,6 +22,7 @@ static inline void swap_read_unplug(struct swap_iocb *plug)
>  void swap_write_unplug(struct swap_iocb *sio);
>  int swap_writepage(struct page *page, struct writeback_control *wbc);
>  void __swap_writepage(struct folio *folio, struct writeback_control *wbc);
> +int kcompressd(void *p);
>  
>  /* linux/mm/swap_state.c */
>  /* One swap address space for each 64M swap space */
> @@ -199,6 +200,11 @@ static inline int swap_zeromap_batch(swp_entry_t entry, int max_nr,
>  	return 0;
>  }
>  
> +static inline int kcompressd(void *p)
> +{
> +	return 0;
> +}
> +
>  #endif /* CONFIG_SWAP */
>  
>  #endif /* _MM_SWAP_H */
> diff --git a/mm/vmscan.c b/mm/vmscan.c
> index 3783e45bfc92..2d7b9167bfd6 100644
> --- a/mm/vmscan.c
> +++ b/mm/vmscan.c
> @@ -7420,6 +7420,7 @@ unsigned long shrink_all_memory(unsigned long nr_to_reclaim)
>  void __meminit kswapd_run(int nid)
>  {
>  	pg_data_t *pgdat = NODE_DATA(nid);
> +	int ret;
>  
>  	pgdat_kswapd_lock(pgdat);
>  	if (!pgdat->kswapd) {
> @@ -7433,7 +7434,26 @@ void __meminit kswapd_run(int nid)
>  		} else {
>  			wake_up_process(pgdat->kswapd);
>  		}
> +		ret = kfifo_alloc(&pgdat->kcompress_fifo,
> +				KCOMPRESS_FIFO_SIZE * sizeof(struct folio *),
> +				GFP_KERNEL);
> +		if (ret) {
> +			pr_err("%s: fail to kfifo_alloc\n", __func__);
> +			goto out;
> +		}
> +
> +		pgdat->kcompressd = kthread_create_on_node(kcompressd, pgdat, nid,
> +				"kcompressd%d", nid);
> +		if (IS_ERR(pgdat->kcompressd)) {
> +			pr_err("Failed to start kcompressd on node %d?ret=%ld\n",
> +					nid, PTR_ERR(pgdat->kcompressd));
> +			pgdat->kcompressd = NULL;
> +			kfifo_free(&pgdat->kcompress_fifo);
> +		} else {
> +			wake_up_process(pgdat->kcompressd);
> +		}
>  	}
> +out:
>  	pgdat_kswapd_unlock(pgdat);
>  }
>  
> @@ -7452,6 +7472,11 @@ void __meminit kswapd_stop(int nid)
>  		kthread_stop(kswapd);
>  		pgdat->kswapd = NULL;
>  	}
> +	if (pgdat->kcompressd) {
> +		kthread_stop(pgdat->kcompressd);
> +		pgdat->kcompressd = NULL;
> +		kfifo_free(&pgdat->kcompress_fifo);
> +	}
>  	pgdat_kswapd_unlock(pgdat);
>  }
>  
> -- 
> 2.45.2
> 
> 

-- 
Cheers,
Harry / Hyeonggon


From Mingyen.Hsieh at mediatek.com  Tue May  6 18:27:05 2025
From: Mingyen.Hsieh at mediatek.com (=?utf-8?B?TWluZ3llbiBIc2llaCAo6Kyd5piO6Ku6KQ==?=)
Date: Wed, 7 May 2025 01:27:05 +0000
Subject: [REGRESSION][BISECTED][STABLE] MT7925: mDNS and IPv6 broken in
 kernel 6.14.3 and above
In-Reply-To: <0736898d8d53e6249d5be637c9b7e7c81398218a.camel@kernel.org>
References: <EmWnO5b-acRH1TXbGnkx41eJw654vmCR-8_xMBaPMwexCnfkvKCdlU5u19CGbaapJ3KRu-l3B-tSUhf8CCQwL0odjo6Cd5YG5lvNeB-vfdg=@pm.me>
	 <f73dec60b60dd7bb3be40c1feefbe223c7afe19b.camel@mediatek.com>
	 <5ae1ef34c9844d6d0f5fb167dd596a4c43321367.camel@kernel.org>
	 <28ef2cc608d071d1530902d7b5df045555ab5651.camel@mediatek.com>
	 <0736898d8d53e6249d5be637c9b7e7c81398218a.camel@kernel.org>
Message-ID: <d077736aff75bb534e3d6981fd579d8df84fa99d.camel@mediatek.com>

On Mon, 2025-05-05 at 19:18 +0200, Niklas Schnelle wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On Mon, 2025-05-05 at 05:48 +0000, Mingyen Hsieh (???) wrote:
> > On Sun, 2025-05-04 at 00:39 +0200, Niklas Schnelle wrote:
> > > 
> > > External email : Please do not click links or open attachments
> > > until
> > > you have verified the sender or the content.
> > > 
> > > 
> > > On Wed, 2025-04-30 at 06:47 +0000, Mingyen Hsieh (???) wrote:
> > > > On Wed, 2025-04-30 at 01:14 +0000, fossben at pm.me?wrote:
> > > > > 
> > > > > External email : Please do not click links or open
> > > > > attachments
> > > > > until
> > > > > you have verified the sender or the content.
> > > > > 
> > > > > 
> > > > > Hello all,
> > > > > 
> > > > > After upgrading to 6.14.3 on my PC with a MT7925 chip, I
> > > > > noticed
> > > > > that
> > > > > I could no longer ping *.local addresses provided by Avahi.
> > > > > In
> > > > > addition, I also noticed that I was not able to get a DHCP
> > > > > IPv6
> > > > > address from my router, no matter how many times I rebooted
> > > > > the
> > > > > router or reconnected with NetworkManager.
> > > > > 
> > > > > Reverting to 6.14.2 fixes both mDNS and IPv6 addresses
> > > > > immediately.
> > > > > Going back to 6.14.3 immediately breaks mDNS again, but the
> > > > > IPv6
> > > > > address will stay there for a while before disappearing
> > > > > later,
> > > > > possibly because the DHCP lease expired? I am not sure
> > > > > exactly
> > > > > when
> > > > > it stops working.
> > > > > 
> > > > > I've done a kernel bisect between 6.14.2 and 6.14.3 and found
> > > > > the
> > > > > offending commit that causes mDNS to fail:
> > > > > 
> > > > > commit 80007d3f92fd018d0a052a706400e976b36e3c87
> > > > > Author: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
> > > > > Date:?? Tue Mar 4 16:08:50 2025 -0800
> > > > > 
> > > > > ??? wifi: mt76: mt7925: integrate *mlo_sta_cmd and *sta_cmd
> > > > > 
> > > > > ??? commit cb1353ef34735ec1e5d9efa1fe966f05ff1dc1e1 upstream.
> > > > > 
> > > > > ??? Integrate *mlo_sta_cmd and *sta_cmd for the MLO firmware.
> > > > > 
> > > > > ??? Fixes: 86c051f2c418 ("wifi: mt76: mt7925: enabling MLO
> > > > > when
> > > > > the
> > > > > firmware supports it")
> > > > > 
> > > > > ?drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 59 ++++---
> > > > > ----
> > > > > ----
> > > > > --------------------------------------------
> > > > > ?1 file changed, 4 insertions(+), 55 deletions(-)
> > > > > 
> > > > > I do not know if this same commit is also causing the IPv6
> > > > > issues
> > > > > as
> > > > > testing that requires quite a bit of time to reproduce. What
> > > > > I do
> > > > > know with certainty as of this moment is that it definitely
> > > > > breaks in
> > > > > kernel 6.14.3.
> > > > > 
> > > > > I've attached my hardware info as well as dmesg logs from the
> > > > > last
> > > > > working kernel from the bisect and 6.14.4 which exhibits the
> > > > > issue.
> > > > > Please let me know if there's any other info you need.
> > > > > 
> > > > > Thanks!
> > > > > Benjamin Xiao
> > > > 
> > > > Hi,
> > > > 
> > > > Thanks for reporting this issue, we will aim into this.
> > > > 
> > > > Can you provide me with your testing steps?
> > > > 
> > > > Best Regards,
> > > > Yen.
> > > > 
> > > 
> > > Hi Yan,
> > > 
> > > I see the same IPv6 issue on my Framework 13 (Ryzen 5 AI 340)
> > > with an
> > > mt7925e WiFI module. My setup is just a home router with native
> > > IPv6
> > > both for my uplink and in the LAN. The problems with IPv6 can
> > > already
> > > be seen just in the LAN for example by checking which IP was used
> > > for
> > > SSH, in my setup it should always be IPv6 but falls back to IPv4
> > > in
> > > the
> > > broken state.
> > > 
> > > As another data point, I tried reverting cb1353ef3473 ("wifi:
> > > mt76:
> > > mt7925: integrate *mlo_sta_cmd and *sta_cmd") on top of 6.15.-
> > > rc4.
> > > This
> > > fully restores IPv6 for me. Also note I'm running this with the
> > > mt7925
> > > firmware version 20250425073330 from linux-firmware's master
> > > branch
> > > as
> > > I had some dropped connections with earlier firmware.
> > > 
> > > So it definitely looks like that commit also broke IPv6 and not
> > > just
> > > mDNS. Note that if if I use DHCPv6 instead of router
> > > advertisements,
> > > on
> > > the latest firmware, but without the revert, I get a global IPv6
> > > address added to the interface but then native IPv6 addresses are
> > > still
> > > uncreachable. With the offending patch reverted my SSH session to
> > > an
> > > IPv6 only host works fine and is stable. Also I'd be willing to
> > > test
> > > a
> > > proper fix as I rely on IPv6 heavily due to having to use CGNAT
> > > for
> > > IPv4 but not for IPv6.
> > > 
> > > 
> > > Thanks,
> > > Niklas
> > 
> > Hi Benjamin & Niklas,
> > 
> > Can you help to try this patch? I can get IPv6 address through this
> > patch.
> > 
> > If it can work at your environment as well, i will upstream it and
> > add
> > test tag with you.
> > 
> > diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > index a42b584634ab..fd756f0d18f8 100644
> > --- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > +++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > @@ -2183,14 +2183,14 @@ mt7925_mcu_sta_cmd(struct mt76_phy *phy,
> > ??????????????????????? mt7925_mcu_sta_mld_tlv(skb, info->vif,
> > info-
> > > link_sta->sta);
> > ??????????????????????? mt7925_mcu_sta_eht_mld_tlv(skb, info->vif,
> > info->link_sta->sta);
> > ??????????????? }
> > -
> > -?????????????? mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info-
> > > link_sta);
> > ??????? }
> > 
> > ??????? if (!info->enable) {
> > ??????????????? mt7925_mcu_sta_remove_tlv(skb);
> > ??????????????? mt76_connac_mcu_add_tlv(skb, STA_REC_MLD_OFF,
> > ??????????????????????????????????????? sizeof(struct tlv));
> > +?????? } else {
> > +?????????????? mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info-
> > > link_sta);
> > ??????? }
> > 
> > ??????? return mt76_mcu_skb_send_msg(dev, skb, info->cmd, true);
> > 
> > 
> > Thanks~
> > Yen.
> > 
> 
> Hi Yen,
> 
> As the patch didn't apply, I edited mt7925_mcu_sta_cmd() manually on
> top of v6.15-rc5 according to the diff. With that IPv6 works fine for
> me.
> 

Hi Niklas,

Thanks for testing.

> If it were me, I'd probably structure the if different. I'd leave
> the mt7925_mcu_sta_hdr_trans_tlv() where it is but have an inner if
> (info->link_sta) inside just if (!info->enable), then the !info-
> >enable
> case becomes just an else. I'd maybe even put the if (info->link_sta)
> body in its own static function if that makes sense semantically, but
> I
> don't know enough (anything) about the driver to know. Anyway, that's
> all a matter of taste and actually makes the patch quite a bit
> larger.
> 

I will consider about this approach and try to release the patch within
the next few days.

> So whichever way you decide on feel free to add:
> 
> Tested-by: Niklas Schnelle <niks at kernel.org>
> 
> Thanks,
> Niklas





From Mingyen.Hsieh at mediatek.com  Tue May  6 18:28:33 2025
From: Mingyen.Hsieh at mediatek.com (=?utf-8?B?TWluZ3llbiBIc2llaCAo6Kyd5piO6Ku6KQ==?=)
Date: Wed, 7 May 2025 01:28:33 +0000
Subject: [REGRESSION][BISECTED][STABLE] MT7925: mDNS and IPv6 broken in
 kernel 6.14.3 and above
In-Reply-To: <vCzHyPICbb61hk8jzrTcmvU7H9PJGenEtIAZaKQH9ofNUZPD4aOeD1i-oDl2G2CtieHoTnUWBWYy-uQhNwRo7sT5gj_uyFQs-zIkbCY-qZU=@pm.me>
References: <EmWnO5b-acRH1TXbGnkx41eJw654vmCR-8_xMBaPMwexCnfkvKCdlU5u19CGbaapJ3KRu-l3B-tSUhf8CCQwL0odjo6Cd5YG5lvNeB-vfdg=@pm.me>
	 <f73dec60b60dd7bb3be40c1feefbe223c7afe19b.camel@mediatek.com>
	 <5ae1ef34c9844d6d0f5fb167dd596a4c43321367.camel@kernel.org>
	 <28ef2cc608d071d1530902d7b5df045555ab5651.camel@mediatek.com>
	 <Q8fBN4506NOX9rrFspv9q0xuQRlE1YcHDbwfRUlXy7if-Lv-kGyIXPrNN2kOMoWENMYCfTmOhAhnSCs4gtUvpzEf0O_JZ_BV__V3B_A7iU8=@pm.me>
	 <vCzHyPICbb61hk8jzrTcmvU7H9PJGenEtIAZaKQH9ofNUZPD4aOeD1i-oDl2G2CtieHoTnUWBWYy-uQhNwRo7sT5gj_uyFQs-zIkbCY-qZU=@pm.me>
Message-ID: <13d1421c6ec96b19b22dc379222600a905334f87.camel@mediatek.com>

On Mon, 2025-05-05 at 23:15 +0000, fossben at pm.me wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On Monday, May 5th, 2025 at 3:20 AM, fossben at pm.me?<fossben at pm.me>
> wrote:
> 
> > 
> > 
> > On Monday, May 5th, 2025 at 12:48 AM, Mingyen Hsieh
> > Mingyen.Hsieh at mediatek.com?wrote:
> > 
> > > On Sun, 2025-05-04 at 00:39 +0200, Niklas Schnelle wrote:
> > > 
> > > > External email : Please do not click links or open attachments
> > > > until
> > > > you have verified the sender or the content.
> > > > 
> > > > On Wed, 2025-04-30 at 06:47 +0000, Mingyen Hsieh (???) wrote:
> > > > 
> > > > > On Wed, 2025-04-30 at 01:14 +0000, fossben at pm.me?wrote:
> > > > > 
> > > > > > External email : Please do not click links or open
> > > > > > attachments
> > > > > > until
> > > > > > you have verified the sender or the content.
> > > > > > 
> > > > > > Hello all,
> > > > > > 
> > > > > > After upgrading to 6.14.3 on my PC with a MT7925 chip, I
> > > > > > noticed
> > > > > > that
> > > > > > I could no longer ping *.local addresses provided by Avahi.
> > > > > > In
> > > > > > addition, I also noticed that I was not able to get a DHCP
> > > > > > IPv6
> > > > > > address from my router, no matter how many times I rebooted
> > > > > > the
> > > > > > router or reconnected with NetworkManager.
> > > > > > 
> > > > > > Reverting to 6.14.2 fixes both mDNS and IPv6 addresses
> > > > > > immediately.
> > > > > > Going back to 6.14.3 immediately breaks mDNS again, but the
> > > > > > IPv6
> > > > > > address will stay there for a while before disappearing
> > > > > > later,
> > > > > > possibly because the DHCP lease expired? I am not sure
> > > > > > exactly
> > > > > > when
> > > > > > it stops working.
> > > > > > 
> > > > > > I've done a kernel bisect between 6.14.2 and 6.14.3 and
> > > > > > found the
> > > > > > offending commit that causes mDNS to fail:
> > > > > > 
> > > > > > commit 80007d3f92fd018d0a052a706400e976b36e3c87
> > > > > > Author: Ming Yen Hsieh mingyen.hsieh at mediatek.com
> > > > > > Date: Tue Mar 4 16:08:50 2025 -0800
> > > > > > 
> > > > > > wifi: mt76: mt7925: integrate *mlo_sta_cmd and *sta_cmd
> > > > > > 
> > > > > > commit cb1353ef34735ec1e5d9efa1fe966f05ff1dc1e1 upstream.
> > > > > > 
> > > > > > Integrate *mlo_sta_cmd and *sta_cmd for the MLO firmware.
> > > > > > 
> > > > > > Fixes: 86c051f2c418 ("wifi: mt76: mt7925: enabling MLO when
> > > > > > the
> > > > > > firmware supports it")
> > > > > > 
> > > > > > drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 59 ++++--
> > > > > > -----
> > > > > > ----
> > > > > > --------------------------------------------
> > > > > > 1 file changed, 4 insertions(+), 55 deletions(-)
> > > > > > 
> > > > > > I do not know if this same commit is also causing the IPv6
> > > > > > issues
> > > > > > as
> > > > > > testing that requires quite a bit of time to reproduce.
> > > > > > What I do
> > > > > > know with certainty as of this moment is that it definitely
> > > > > > breaks in
> > > > > > kernel 6.14.3.
> > > > > > 
> > > > > > I've attached my hardware info as well as dmesg logs from
> > > > > > the
> > > > > > last
> > > > > > working kernel from the bisect and 6.14.4 which exhibits
> > > > > > the
> > > > > > issue.
> > > > > > Please let me know if there's any other info you need.
> > > > > > 
> > > > > > Thanks!
> > > > > > Benjamin Xiao
> > > > > 
> > > > > Hi,
> > > > > 
> > > > > Thanks for reporting this issue, we will aim into this.
> > > > > 
> > > > > Can you provide me with your testing steps?
> > > > > 
> > > > > Best Regards,
> > > > > Yen.
> > > > 
> > > > Hi Yan,
> > > > 
> > > > I see the same IPv6 issue on my Framework 13 (Ryzen 5 AI 340)
> > > > with an
> > > > mt7925e WiFI module. My setup is just a home router with native
> > > > IPv6
> > > > both for my uplink and in the LAN. The problems with IPv6 can
> > > > already
> > > > be seen just in the LAN for example by checking which IP was
> > > > used for
> > > > SSH, in my setup it should always be IPv6 but falls back to
> > > > IPv4 in
> > > > the
> > > > broken state.
> > > > 
> > > > As another data point, I tried reverting cb1353ef3473 ("wifi:
> > > > mt76:
> > > > mt7925: integrate *mlo_sta_cmd and *sta_cmd") on top of 6.15.-
> > > > rc4.
> > > > This
> > > > fully restores IPv6 for me. Also note I'm running this with the
> > > > mt7925
> > > > firmware version 20250425073330 from linux-firmware's master
> > > > branch
> > > > as
> > > > I had some dropped connections with earlier firmware.
> > > > 
> > > > So it definitely looks like that commit also broke IPv6 and not
> > > > just
> > > > mDNS. Note that if if I use DHCPv6 instead of router
> > > > advertisements,
> > > > on
> > > > the latest firmware, but without the revert, I get a global
> > > > IPv6
> > > > address added to the interface but then native IPv6 addresses
> > > > are
> > > > still
> > > > uncreachable. With the offending patch reverted my SSH session
> > > > to an
> > > > IPv6 only host works fine and is stable. Also I'd be willing to
> > > > test
> > > > a
> > > > proper fix as I rely on IPv6 heavily due to having to use CGNAT
> > > > for
> > > > IPv4 but not for IPv6.
> > > > 
> > > > Thanks,
> > > > Niklas
> > > 
> > > Hi Benjamin & Niklas,
> > > 
> > > Can you help to try this patch? I can get IPv6 address through
> > > this
> > > patch.
> > > 
> > > If it can work at your environment as well, i will upstream it
> > > and add
> > > test tag with you.
> > > 
> > > diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > > b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > > index a42b584634ab..fd756f0d18f8 100644
> > > --- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > > +++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > > @@ -2183,14 +2183,14 @@ mt7925_mcu_sta_cmd(struct mt76_phy *phy,
> > > mt7925_mcu_sta_mld_tlv(skb, info->vif, info-
> > > 
> > > > link_sta->sta);
> > > > mt7925_mcu_sta_eht_mld_tlv(skb, info->vif,
> > > > info->link_sta->sta);
> > > > }
> > > > -
> > > > - mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info-
> > > > link_sta);
> > > > }
> > > 
> > > if (!info->enable) {
> > > mt7925_mcu_sta_remove_tlv(skb);
> > > mt76_connac_mcu_add_tlv(skb, STA_REC_MLD_OFF,
> > > sizeof(struct tlv));
> > > + } else {
> > > + mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info-
> > > 
> > > > link_sta);
> > > > }
> > > 
> > > return mt76_mcu_skb_send_msg(dev, skb, info->cmd, true);
> > > 
> > > Thanks~
> > > Yen.
> > 
> > 
> > Hi Yen,
> > 
> > I manually applied the changes on top of 6.14.5 and mDNS seems to
> > work along with IPv6! I will do more testing for the rest of the
> > day to see if the issue is completely fixed but so far looks good
> > at least for the 5 minutes I've been testing it.
> > 
> > Thanks for the fix,
> > Ben
> 
> I've now used 6.14.5 with the patch applied for most of the day and
> it's been working great! mDNS has been rock solid and so has IPv6.
> 
> Would appreciate it if this fix got backported to the 6.14 series!
> 
> Ben

Hi Ben,

Thanks for testing it. And it will be backporting to 6.14 series after
the mainline merged it.

Yen.





From ziy at nvidia.com  Tue May  6 18:50:44 2025
From: ziy at nvidia.com (Zi Yan)
Date: Tue, 06 May 2025 21:50:44 -0400
Subject: [PATCH] mm: Add Kcompressd for accelerated memory compression
In-Reply-To: <aBqzcIteOzC9mRjY@harry>
References: <20250430082651.3152444-1-qun-wei.lin@mediatek.com>
 <aBqzcIteOzC9mRjY@harry>
Message-ID: <A3307E1B-B741-4C23-8053-72A1CA04D923@nvidia.com>

On 6 May 2025, at 21:12, Harry Yoo wrote:

> On Wed, Apr 30, 2025 at 04:26:41PM +0800, Qun-Wei Lin wrote:
>> This patch series introduces a new mechanism called kcompressd to
>> improve the efficiency of memory reclaiming in the operating system.
>>
>> Problem:
>>   In the current system, the kswapd thread is responsible for both scanning
>>   the LRU pages and handling memory compression tasks (such as those
>>   involving ZSWAP/ZRAM, if enabled). This combined responsibility can lead
>>   to significant performance bottlenecks, especially under high memory
>>   pressure. The kswapd thread becomes a single point of contention, causing
>>   delays in memory reclaiming and overall system performance degradation.
>>
>> Solution:
>>   Introduced kcompressd to handle asynchronous compression during memory
>>   reclaim, improving efficiency by offloading compression tasks from
>>   kswapd. This allows kswapd to focus on its primary task of page reclaim
>>   without being burdened by the additional overhead of compression.
>>
>> In our handheld devices, we found that applying this mechanism under high
>> memory pressure scenarios can increase the rate of pgsteal_anon per second
>> by over 260% compared to the situation with only kswapd. Additionally, we
>> observed a reduction of over 50% in page allocation stall occurrences,
>> further demonstrating the effectiveness of kcompressd in alleviating memory
>> pressure and improving system responsiveness.
>>
>> Co-developed-by: Barry Song <21cnbao at gmail.com>
>> Signed-off-by: Barry Song <21cnbao at gmail.com>
>> Signed-off-by: Qun-Wei Lin <qun-wei.lin at mediatek.com>
>> Reference: Re: [PATCH 0/2] Improve Zram by separating compression context from kswapd - Barry Song
>>           https://lore.kernel.org/lkml/20250313093005.13998-1-21cnbao at gmail.com/
>> ---
>
> +Cc Zi Yan, who might be interested in writing a framework (or improving
> the existing one, padata) for parallelizing jobs (e.g. migration/compression)

Thanks.

I am currently looking into padata [1] to perform multithreaded page migration
copy job. But based on this patch, it seems that kcompressed is just an additional
kernel thread of executing zswap_store(). Is there any need for performing
compression with multiple threads?

BTW, I also notice that zswap IAA compress batching patchset[2] is using
hardware accelerator (Intel Analytics Accelerator) to speed up zswap.
I wonder if the handheld devices have similar hardware to get a similar benefit.


[1] https://docs.kernel.org/core-api/padata.html
[2] https://lore.kernel.org/linux-crypto/20250303084724.6490-1-kanchana.p.sridhar at intel.com/
>
>>  include/linux/mmzone.h |  6 ++++
>>  mm/mm_init.c           |  1 +
>>  mm/page_io.c           | 71 ++++++++++++++++++++++++++++++++++++++++++
>>  mm/swap.h              |  6 ++++
>>  mm/vmscan.c            | 25 +++++++++++++++
>>  5 files changed, 109 insertions(+)
>>
>> diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
>> index 6ccec1bf2896..93c9195a54ae 100644
>> --- a/include/linux/mmzone.h
>> +++ b/include/linux/mmzone.h
>> @@ -23,6 +23,7 @@
>>  #include <linux/page-flags.h>
>>  #include <linux/local_lock.h>
>>  #include <linux/zswap.h>
>> +#include <linux/kfifo.h>
>>  #include <asm/page.h>
>>
>>  /* Free memory management - zoned buddy allocator.  */
>> @@ -1398,6 +1399,11 @@ typedef struct pglist_data {
>>
>>  	int kswapd_failures;		/* Number of 'reclaimed == 0' runs */
>>
>> +#define KCOMPRESS_FIFO_SIZE 256
>> +	wait_queue_head_t kcompressd_wait;
>> +	struct task_struct *kcompressd;
>> +	struct kfifo kcompress_fifo;
>> +
>>  #ifdef CONFIG_COMPACTION
>>  	int kcompactd_max_order;
>>  	enum zone_type kcompactd_highest_zoneidx;
>> diff --git a/mm/mm_init.c b/mm/mm_init.c
>> index 9659689b8ace..49bae1dd4584 100644
>> --- a/mm/mm_init.c
>> +++ b/mm/mm_init.c
>> @@ -1410,6 +1410,7 @@ static void __meminit pgdat_init_internals(struct pglist_data *pgdat)
>>  	pgdat_init_kcompactd(pgdat);
>>
>>  	init_waitqueue_head(&pgdat->kswapd_wait);
>> +	init_waitqueue_head(&pgdat->kcompressd_wait);
>>  	init_waitqueue_head(&pgdat->pfmemalloc_wait);
>>
>>  	for (i = 0; i < NR_VMSCAN_THROTTLE; i++)
>> diff --git a/mm/page_io.c b/mm/page_io.c
>> index 4bce19df557b..d85deb494a6a 100644
>> --- a/mm/page_io.c
>> +++ b/mm/page_io.c
>> @@ -233,6 +233,38 @@ static void swap_zeromap_folio_clear(struct folio *folio)
>>  	}
>>  }
>>
>> +static bool swap_sched_async_compress(struct folio *folio)
>> +{
>> +	struct swap_info_struct *sis = swp_swap_info(folio->swap);
>> +	int nid = numa_node_id();
>> +	pg_data_t *pgdat = NODE_DATA(nid);
>> +
>> +	if (unlikely(!pgdat->kcompressd))
>> +		return false;
>> +
>> +	if (!current_is_kswapd())
>> +		return false;
>> +
>> +	if (!folio_test_anon(folio))
>> +		return false;
>> +	/*
>> +	 * This case needs to synchronously return AOP_WRITEPAGE_ACTIVATE
>> +	 */
>> +	if (!mem_cgroup_zswap_writeback_enabled(folio_memcg(folio)))
>> +		return false;
>> +
>> +	sis = swp_swap_info(folio->swap);
>> +	if (zswap_is_enabled() || data_race(sis->flags & SWP_SYNCHRONOUS_IO)) {
>> +		if (kfifo_avail(&pgdat->kcompress_fifo) >= sizeof(folio) &&
>> +			kfifo_in(&pgdat->kcompress_fifo, &folio, sizeof(folio))) {
>> +			wake_up_interruptible(&pgdat->kcompressd_wait);
>> +			return true;
>> +		}
>> +	}
>> +
>> +	return false;
>> +}
>> +
>>  /*
>>   * We may have stale swap cache pages in memory: notice
>>   * them here and get rid of the unnecessary final write.
>> @@ -275,6 +307,15 @@ int swap_writepage(struct page *page, struct writeback_control *wbc)
>>  		 */
>>  		swap_zeromap_folio_clear(folio);
>>  	}
>> +
>> +	/*
>> +	 * Compression within zswap and zram might block rmap, unmap
>> +	 * of both file and anon pages, try to do compression async
>> +	 * if possible
>> +	 */
>> +	if (swap_sched_async_compress(folio))
>> +		return 0;
>> +
>>  	if (zswap_store(folio)) {
>>  		count_mthp_stat(folio_order(folio), MTHP_STAT_ZSWPOUT);
>>  		folio_unlock(folio);
>> @@ -289,6 +330,36 @@ int swap_writepage(struct page *page, struct writeback_control *wbc)
>>  	return 0;
>>  }
>>
>> +int kcompressd(void *p)
>> +{
>> +	pg_data_t *pgdat = (pg_data_t *)p;
>> +	struct folio *folio;
>> +	struct writeback_control wbc = {
>> +		.sync_mode = WB_SYNC_NONE,
>> +		.nr_to_write = SWAP_CLUSTER_MAX,
>> +		.range_start = 0,
>> +		.range_end = LLONG_MAX,
>> +		.for_reclaim = 1,
>> +	};
>> +
>> +	while (!kthread_should_stop()) {
>> +		wait_event_interruptible(pgdat->kcompressd_wait,
>> +				!kfifo_is_empty(&pgdat->kcompress_fifo));
>> +
>> +		while (!kfifo_is_empty(&pgdat->kcompress_fifo)) {
>> +			if (kfifo_out(&pgdat->kcompress_fifo, &folio, sizeof(folio))) {
>> +				if (zswap_store(folio)) {
>> +					count_mthp_stat(folio_order(folio), MTHP_STAT_ZSWPOUT);
>> +					folio_unlock(folio);
>> +					continue;
>> +				}
>> +				__swap_writepage(folio, &wbc);
>> +			}
>> +		}
>> +	}
>> +	return 0;
>> +}
>> +
>>  static inline void count_swpout_vm_event(struct folio *folio)
>>  {
>>  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
>> diff --git a/mm/swap.h b/mm/swap.h
>> index 6f4a3f927edb..3579da413dc2 100644
>> --- a/mm/swap.h
>> +++ b/mm/swap.h
>> @@ -22,6 +22,7 @@ static inline void swap_read_unplug(struct swap_iocb *plug)
>>  void swap_write_unplug(struct swap_iocb *sio);
>>  int swap_writepage(struct page *page, struct writeback_control *wbc);
>>  void __swap_writepage(struct folio *folio, struct writeback_control *wbc);
>> +int kcompressd(void *p);
>>
>>  /* linux/mm/swap_state.c */
>>  /* One swap address space for each 64M swap space */
>> @@ -199,6 +200,11 @@ static inline int swap_zeromap_batch(swp_entry_t entry, int max_nr,
>>  	return 0;
>>  }
>>
>> +static inline int kcompressd(void *p)
>> +{
>> +	return 0;
>> +}
>> +
>>  #endif /* CONFIG_SWAP */
>>
>>  #endif /* _MM_SWAP_H */
>> diff --git a/mm/vmscan.c b/mm/vmscan.c
>> index 3783e45bfc92..2d7b9167bfd6 100644
>> --- a/mm/vmscan.c
>> +++ b/mm/vmscan.c
>> @@ -7420,6 +7420,7 @@ unsigned long shrink_all_memory(unsigned long nr_to_reclaim)
>>  void __meminit kswapd_run(int nid)
>>  {
>>  	pg_data_t *pgdat = NODE_DATA(nid);
>> +	int ret;
>>
>>  	pgdat_kswapd_lock(pgdat);
>>  	if (!pgdat->kswapd) {
>> @@ -7433,7 +7434,26 @@ void __meminit kswapd_run(int nid)
>>  		} else {
>>  			wake_up_process(pgdat->kswapd);
>>  		}
>> +		ret = kfifo_alloc(&pgdat->kcompress_fifo,
>> +				KCOMPRESS_FIFO_SIZE * sizeof(struct folio *),
>> +				GFP_KERNEL);
>> +		if (ret) {
>> +			pr_err("%s: fail to kfifo_alloc\n", __func__);
>> +			goto out;
>> +		}
>> +
>> +		pgdat->kcompressd = kthread_create_on_node(kcompressd, pgdat, nid,
>> +				"kcompressd%d", nid);
>> +		if (IS_ERR(pgdat->kcompressd)) {
>> +			pr_err("Failed to start kcompressd on node %d?ret=%ld\n",
>> +					nid, PTR_ERR(pgdat->kcompressd));
>> +			pgdat->kcompressd = NULL;
>> +			kfifo_free(&pgdat->kcompress_fifo);
>> +		} else {
>> +			wake_up_process(pgdat->kcompressd);
>> +		}
>>  	}
>> +out:
>>  	pgdat_kswapd_unlock(pgdat);
>>  }
>>
>> @@ -7452,6 +7472,11 @@ void __meminit kswapd_stop(int nid)
>>  		kthread_stop(kswapd);
>>  		pgdat->kswapd = NULL;
>>  	}
>> +	if (pgdat->kcompressd) {
>> +		kthread_stop(pgdat->kcompressd);
>> +		pgdat->kcompressd = NULL;
>> +		kfifo_free(&pgdat->kcompress_fifo);
>> +	}
>>  	pgdat_kswapd_unlock(pgdat);
>>  }
>>
>> -- 
>> 2.45.2
>>
>>
>
> -- 
> Cheers,
> Harry / Hyeonggon


--
Best Regards,
Yan, Zi


From 21cnbao at gmail.com  Tue May  6 19:04:26 2025
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 7 May 2025 14:04:26 +1200
Subject: [PATCH] mm: Add Kcompressd for accelerated memory compression
In-Reply-To: <A3307E1B-B741-4C23-8053-72A1CA04D923@nvidia.com>
References: <20250430082651.3152444-1-qun-wei.lin@mediatek.com>
 <aBqzcIteOzC9mRjY@harry> <A3307E1B-B741-4C23-8053-72A1CA04D923@nvidia.com>
Message-ID: <CAGsJ_4yBn7j3WpCttPB0PVuRCYTYBcDbW2221AaPNLOHSmKADA@mail.gmail.com>

On Wed, May 7, 2025 at 1:50?PM Zi Yan <ziy at nvidia.com> wrote:
>
> On 6 May 2025, at 21:12, Harry Yoo wrote:
>
> > On Wed, Apr 30, 2025 at 04:26:41PM +0800, Qun-Wei Lin wrote:
> >> This patch series introduces a new mechanism called kcompressd to
> >> improve the efficiency of memory reclaiming in the operating system.
> >>
> >> Problem:
> >>   In the current system, the kswapd thread is responsible for both scanning
> >>   the LRU pages and handling memory compression tasks (such as those
> >>   involving ZSWAP/ZRAM, if enabled). This combined responsibility can lead
> >>   to significant performance bottlenecks, especially under high memory
> >>   pressure. The kswapd thread becomes a single point of contention, causing
> >>   delays in memory reclaiming and overall system performance degradation.
> >>
> >> Solution:
> >>   Introduced kcompressd to handle asynchronous compression during memory
> >>   reclaim, improving efficiency by offloading compression tasks from
> >>   kswapd. This allows kswapd to focus on its primary task of page reclaim
> >>   without being burdened by the additional overhead of compression.
> >>
> >> In our handheld devices, we found that applying this mechanism under high
> >> memory pressure scenarios can increase the rate of pgsteal_anon per second
> >> by over 260% compared to the situation with only kswapd. Additionally, we
> >> observed a reduction of over 50% in page allocation stall occurrences,
> >> further demonstrating the effectiveness of kcompressd in alleviating memory
> >> pressure and improving system responsiveness.
> >>
> >> Co-developed-by: Barry Song <21cnbao at gmail.com>
> >> Signed-off-by: Barry Song <21cnbao at gmail.com>
> >> Signed-off-by: Qun-Wei Lin <qun-wei.lin at mediatek.com>
> >> Reference: Re: [PATCH 0/2] Improve Zram by separating compression context from kswapd - Barry Song
> >>           https://lore.kernel.org/lkml/20250313093005.13998-1-21cnbao at gmail.com/
> >> ---
> >
> > +Cc Zi Yan, who might be interested in writing a framework (or improving
> > the existing one, padata) for parallelizing jobs (e.g. migration/compression)
>
> Thanks.
>
> I am currently looking into padata [1] to perform multithreaded page migration
> copy job. But based on this patch, it seems that kcompressed is just an additional
> kernel thread of executing zswap_store(). Is there any need for performing
> compression with multiple threads?

The current focus is on enabling kswapd to perform asynchronous compression,
which can significantly reduce direct reclaim and allocstall events.
Therefore, the work begins with supporting a single thread. Supporting
multiple threads might be possible in the future, but it could be difficult
to control?especially on busy phones?since it consumes more power and may
interfere with other threads impacting user experience.

>
> BTW, I also notice that zswap IAA compress batching patchset[2] is using
> hardware accelerator (Intel Analytics Accelerator) to speed up zswap.
> I wonder if the handheld devices have similar hardware to get a similar benefit.

Usually, the answer is no. We use zRAM and CPU, but this patch aims to provide
a common capability that can be shared by both zRAM and zswap.

>
>
> [1] https://docs.kernel.org/core-api/padata.html
> [2] https://lore.kernel.org/linux-crypto/20250303084724.6490-1-kanchana.p.sridhar at intel.com/
> >
> >>  include/linux/mmzone.h |  6 ++++
> >>  mm/mm_init.c           |  1 +
> >>  mm/page_io.c           | 71 ++++++++++++++++++++++++++++++++++++++++++
> >>  mm/swap.h              |  6 ++++
> >>  mm/vmscan.c            | 25 +++++++++++++++
> >>  5 files changed, 109 insertions(+)
> >>
> >> diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
> >> index 6ccec1bf2896..93c9195a54ae 100644
> >> --- a/include/linux/mmzone.h
> >> +++ b/include/linux/mmzone.h
> >> @@ -23,6 +23,7 @@
> >>  #include <linux/page-flags.h>
> >>  #include <linux/local_lock.h>
> >>  #include <linux/zswap.h>
> >> +#include <linux/kfifo.h>
> >>  #include <asm/page.h>
> >>
> >>  /* Free memory management - zoned buddy allocator.  */
> >> @@ -1398,6 +1399,11 @@ typedef struct pglist_data {
> >>
> >>      int kswapd_failures;            /* Number of 'reclaimed == 0' runs */
> >>
> >> +#define KCOMPRESS_FIFO_SIZE 256
> >> +    wait_queue_head_t kcompressd_wait;
> >> +    struct task_struct *kcompressd;
> >> +    struct kfifo kcompress_fifo;
> >> +
> >>  #ifdef CONFIG_COMPACTION
> >>      int kcompactd_max_order;
> >>      enum zone_type kcompactd_highest_zoneidx;
> >> diff --git a/mm/mm_init.c b/mm/mm_init.c
> >> index 9659689b8ace..49bae1dd4584 100644
> >> --- a/mm/mm_init.c
> >> +++ b/mm/mm_init.c
> >> @@ -1410,6 +1410,7 @@ static void __meminit pgdat_init_internals(struct pglist_data *pgdat)
> >>      pgdat_init_kcompactd(pgdat);
> >>
> >>      init_waitqueue_head(&pgdat->kswapd_wait);
> >> +    init_waitqueue_head(&pgdat->kcompressd_wait);
> >>      init_waitqueue_head(&pgdat->pfmemalloc_wait);
> >>
> >>      for (i = 0; i < NR_VMSCAN_THROTTLE; i++)
> >> diff --git a/mm/page_io.c b/mm/page_io.c
> >> index 4bce19df557b..d85deb494a6a 100644
> >> --- a/mm/page_io.c
> >> +++ b/mm/page_io.c
> >> @@ -233,6 +233,38 @@ static void swap_zeromap_folio_clear(struct folio *folio)
> >>      }
> >>  }
> >>
> >> +static bool swap_sched_async_compress(struct folio *folio)
> >> +{
> >> +    struct swap_info_struct *sis = swp_swap_info(folio->swap);
> >> +    int nid = numa_node_id();
> >> +    pg_data_t *pgdat = NODE_DATA(nid);
> >> +
> >> +    if (unlikely(!pgdat->kcompressd))
> >> +            return false;
> >> +
> >> +    if (!current_is_kswapd())
> >> +            return false;
> >> +
> >> +    if (!folio_test_anon(folio))
> >> +            return false;
> >> +    /*
> >> +     * This case needs to synchronously return AOP_WRITEPAGE_ACTIVATE
> >> +     */
> >> +    if (!mem_cgroup_zswap_writeback_enabled(folio_memcg(folio)))
> >> +            return false;
> >> +
> >> +    sis = swp_swap_info(folio->swap);
> >> +    if (zswap_is_enabled() || data_race(sis->flags & SWP_SYNCHRONOUS_IO)) {
> >> +            if (kfifo_avail(&pgdat->kcompress_fifo) >= sizeof(folio) &&
> >> +                    kfifo_in(&pgdat->kcompress_fifo, &folio, sizeof(folio))) {
> >> +                    wake_up_interruptible(&pgdat->kcompressd_wait);
> >> +                    return true;
> >> +            }
> >> +    }
> >> +
> >> +    return false;
> >> +}
> >> +
> >>  /*
> >>   * We may have stale swap cache pages in memory: notice
> >>   * them here and get rid of the unnecessary final write.
> >> @@ -275,6 +307,15 @@ int swap_writepage(struct page *page, struct writeback_control *wbc)
> >>               */
> >>              swap_zeromap_folio_clear(folio);
> >>      }
> >> +
> >> +    /*
> >> +     * Compression within zswap and zram might block rmap, unmap
> >> +     * of both file and anon pages, try to do compression async
> >> +     * if possible
> >> +     */
> >> +    if (swap_sched_async_compress(folio))
> >> +            return 0;
> >> +
> >>      if (zswap_store(folio)) {
> >>              count_mthp_stat(folio_order(folio), MTHP_STAT_ZSWPOUT);
> >>              folio_unlock(folio);
> >> @@ -289,6 +330,36 @@ int swap_writepage(struct page *page, struct writeback_control *wbc)
> >>      return 0;
> >>  }
> >>
> >> +int kcompressd(void *p)
> >> +{
> >> +    pg_data_t *pgdat = (pg_data_t *)p;
> >> +    struct folio *folio;
> >> +    struct writeback_control wbc = {
> >> +            .sync_mode = WB_SYNC_NONE,
> >> +            .nr_to_write = SWAP_CLUSTER_MAX,
> >> +            .range_start = 0,
> >> +            .range_end = LLONG_MAX,
> >> +            .for_reclaim = 1,
> >> +    };
> >> +
> >> +    while (!kthread_should_stop()) {
> >> +            wait_event_interruptible(pgdat->kcompressd_wait,
> >> +                            !kfifo_is_empty(&pgdat->kcompress_fifo));
> >> +
> >> +            while (!kfifo_is_empty(&pgdat->kcompress_fifo)) {
> >> +                    if (kfifo_out(&pgdat->kcompress_fifo, &folio, sizeof(folio))) {
> >> +                            if (zswap_store(folio)) {
> >> +                                    count_mthp_stat(folio_order(folio), MTHP_STAT_ZSWPOUT);
> >> +                                    folio_unlock(folio);
> >> +                                    continue;
> >> +                            }
> >> +                            __swap_writepage(folio, &wbc);
> >> +                    }
> >> +            }
> >> +    }
> >> +    return 0;
> >> +}
> >> +
> >>  static inline void count_swpout_vm_event(struct folio *folio)
> >>  {
> >>  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> >> diff --git a/mm/swap.h b/mm/swap.h
> >> index 6f4a3f927edb..3579da413dc2 100644
> >> --- a/mm/swap.h
> >> +++ b/mm/swap.h
> >> @@ -22,6 +22,7 @@ static inline void swap_read_unplug(struct swap_iocb *plug)
> >>  void swap_write_unplug(struct swap_iocb *sio);
> >>  int swap_writepage(struct page *page, struct writeback_control *wbc);
> >>  void __swap_writepage(struct folio *folio, struct writeback_control *wbc);
> >> +int kcompressd(void *p);
> >>
> >>  /* linux/mm/swap_state.c */
> >>  /* One swap address space for each 64M swap space */
> >> @@ -199,6 +200,11 @@ static inline int swap_zeromap_batch(swp_entry_t entry, int max_nr,
> >>      return 0;
> >>  }
> >>
> >> +static inline int kcompressd(void *p)
> >> +{
> >> +    return 0;
> >> +}
> >> +
> >>  #endif /* CONFIG_SWAP */
> >>
> >>  #endif /* _MM_SWAP_H */
> >> diff --git a/mm/vmscan.c b/mm/vmscan.c
> >> index 3783e45bfc92..2d7b9167bfd6 100644
> >> --- a/mm/vmscan.c
> >> +++ b/mm/vmscan.c
> >> @@ -7420,6 +7420,7 @@ unsigned long shrink_all_memory(unsigned long nr_to_reclaim)
> >>  void __meminit kswapd_run(int nid)
> >>  {
> >>      pg_data_t *pgdat = NODE_DATA(nid);
> >> +    int ret;
> >>
> >>      pgdat_kswapd_lock(pgdat);
> >>      if (!pgdat->kswapd) {
> >> @@ -7433,7 +7434,26 @@ void __meminit kswapd_run(int nid)
> >>              } else {
> >>                      wake_up_process(pgdat->kswapd);
> >>              }
> >> +            ret = kfifo_alloc(&pgdat->kcompress_fifo,
> >> +                            KCOMPRESS_FIFO_SIZE * sizeof(struct folio *),
> >> +                            GFP_KERNEL);
> >> +            if (ret) {
> >> +                    pr_err("%s: fail to kfifo_alloc\n", __func__);
> >> +                    goto out;
> >> +            }
> >> +
> >> +            pgdat->kcompressd = kthread_create_on_node(kcompressd, pgdat, nid,
> >> +                            "kcompressd%d", nid);
> >> +            if (IS_ERR(pgdat->kcompressd)) {
> >> +                    pr_err("Failed to start kcompressd on node %d?ret=%ld\n",
> >> +                                    nid, PTR_ERR(pgdat->kcompressd));
> >> +                    pgdat->kcompressd = NULL;
> >> +                    kfifo_free(&pgdat->kcompress_fifo);
> >> +            } else {
> >> +                    wake_up_process(pgdat->kcompressd);
> >> +            }
> >>      }
> >> +out:
> >>      pgdat_kswapd_unlock(pgdat);
> >>  }
> >>
> >> @@ -7452,6 +7472,11 @@ void __meminit kswapd_stop(int nid)
> >>              kthread_stop(kswapd);
> >>              pgdat->kswapd = NULL;
> >>      }
> >> +    if (pgdat->kcompressd) {
> >> +            kthread_stop(pgdat->kcompressd);
> >> +            pgdat->kcompressd = NULL;
> >> +            kfifo_free(&pgdat->kcompress_fifo);
> >> +    }
> >>      pgdat_kswapd_unlock(pgdat);
> >>  }
> >>
> >> --
> >> 2.45.2
> >>
> >>
> >
> > --
> > Cheers,
> > Harry / Hyeonggon
>
>
> --
> Best Regards,
> Yan, Zi

Thanks
Barry


From victor.liu at nxp.com  Tue May  6 19:10:53 2025
From: victor.liu at nxp.com (Liu Ying)
Date: Wed, 7 May 2025 10:10:53 +0800
Subject: [PATCH v2 30/34] drm/bridge: imx8qxp-pixel-combiner: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250506224720.5cbcf3e1@booty>
References: <20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b@bootlin.com>
 <20250424-drm-bridge-convert-to-alloc-api-v2-30-8f91a404d86b@bootlin.com>
 <553d62ed-976a-4e17-9678-cdc3d40ce4a7@nxp.com>
 <20250430112944.1b39caab@booty>
 <f71d18d2-4271-4bb9-b54f-0e5a585778f3@nxp.com>
 <20250506224720.5cbcf3e1@booty>
Message-ID: <a1abf31a-7a4a-4f8d-bf48-6b826aa01197@nxp.com>

On 05/07/2025, Luca Ceresoli wrote:
> Hello Liu,

Hi Luca,

> 
> thanks for your further feedback.
> 
> On Tue, 6 May 2025 10:24:18 +0800
> Liu Ying <victor.liu at nxp.com> wrote:
> 
>> On 04/30/2025, Luca Ceresoli wrote:
>>> Hello Liu,  
>>
>> Hi Luca,
>>
>>>
>>> On Tue, 29 Apr 2025 10:10:55 +0800
>>> Liu Ying <victor.liu at nxp.com> wrote:
>>>   
>>>> Hi,
>>>>
>>>> On 04/25/2025, Luca Ceresoli wrote:  
>>>>> This is the new API for allocating DRM bridges.
>>>>>
>>>>> This driver embeds an array of channels in the main struct, and each
>>>>> channel embeds a drm_bridge. This prevents dynamic, refcount-based
>>>>> deallocation of the bridges.
>>>>>
>>>>> To make the new, dynamic bridge allocation possible:
>>>>>
>>>>>  * change the array of channels into an array of channel pointers
>>>>>  * allocate each channel using devm_drm_bridge_alloc()
>>>>>  * adapt the code wherever using the channels
>>>>>
>>>>> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>  
>>>
>>> [...]
>>>   
>>>>> @@ -345,8 +351,8 @@ static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
>>>>>  free_child:
>>>>>  	of_node_put(child);
>>>>>  
>>>>> -	if (i == 1 && pc->ch[0].next_bridge)
>>>>> -		drm_bridge_remove(&pc->ch[0].bridge);
>>>>> +	if (i == 1 && pc->ch[0]->next_bridge)    
>>>>
>>>> Since this patch makes pc->ch[0] and pc->ch[1] be allocated separately,
>>>> pc->ch[0] could be NULL if channel0 is not available, hence a NULL pointer
>>>> dereference here...  
>>>
>>> See below for this.
>>>   
>>>>> +		drm_bridge_remove(&pc->ch[0]->bridge);
>>>>>  
>>>>>  	pm_runtime_disable(dev);
>>>>>  	return ret;
>>>>> @@ -359,7 +365,7 @@ static void imx8qxp_pc_bridge_remove(struct platform_device *pdev)
>>>>>  	int i;
>>>>>  
>>>>>  	for (i = 0; i < 2; i++) {
>>>>> -		ch = &pc->ch[i];
>>>>> +		ch = pc->ch[i];
>>>>>  
>>>>>  		if (!ch->is_available)    
>>>>
>>>> ...and here too.  
>>>
>>> This is indeed a bug, I should have checked the pointer for being
>>> non-NULL.
>>>
>>> Looking at that more closely, I think the is_available flag can be
>>> entirely removed now. The allocation itself (ch != NULL) now is
>>> equivalent. Do you think my reasoning is correct?
>>>
>>> Ouch! After writing the previous paragraph I realized you proposed this
>>> a few lines below! OK, removing is_available. :)
>>>
>>> [...]
>>>   
>>>> On top of this patch series, this issue doesn't happen if I apply the below
>>>> change:  
>>>
>>> [...]
>>>   
>>>> @@ -351,7 +349,7 @@ static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
>>>>  free_child:
>>>>         of_node_put(child);
>>>>  
>>>> -       if (i == 1 && pc->ch[0]->next_bridge)
>>>> +       if (i == 1 && pc->ch[0])
>>>>                 drm_bridge_remove(&pc->ch[0]->bridge);  
>>>
>>> Unrelated to this patch, but as I looked at it more in depth now, I'm
>>> not sure this whole logic is robust, even in the original code.
>>>
>>> The 'i == 1' check here seems to mean "if some error happened when
>>> handling channel at 1, that means channel at 0 was successfully initialized,
>>> so let's clean up channel 0".
>>>
>>> However my understanding of the bindings is that device tree is allowed
>>> to have the channel at 1 node before the channel at 0 node (or even channel at 1
>>> without channel at 0, but that's less problematic here).
>>>
>>> In such case (channel at 1 before channel at 0), this would happen:
>>>
>>>  1. alloc and init ch[1], all OK
>>>  2. alloc and init ch[0], an error happens
>>>     (e.g. of_graph_get_remote_node() fails)
>>>
>>> So we'd reach the free_child: label, and we should call
>>> drm_bridge_remove() for ch[1]->bridge, but there's no code to do that.
>>>
>>> To be robust in such a case, I think both channels need to be checked
>>> independently, as the status of one does not imply the status of the
>>> other. E.g.:
>>>
>>>   for (i = 0; i < 2; i++)
>>>       if (pc->ch[i] && pc->ch[i]->next_bridge)
>>>           drm_bridge_remove(&pc->ch[i]->bridge);
>>>
>>> (which is similar to what .remove() does after the changes discussed in
>>> this thread, and which I have queued for v3)
>>>
>>> What's your opinion? Do you think I missed anything?  
>>
>> The pixel combiner DT node would be added in imx8-ss-dc{0,1}.dtsi, please
>> see the case for imx8-ss-dc0.dtsi introduced by an in-flight patch[1].  As
>> channel@{0,1} child nodes always exist(DT overlay cannot effectively delete
>> any of them) and channel at 0 always comes first, there is no problematic case.
> 
> I'm not questioning what existing and future dts files (will) contain,
> and surely I don't see a good reason someone would write channel at 1
> before channel at 0.
> 
> My point is:
> 
>  - the bindings _allow_ channel1 before channel at 0
>  - the error management code after the free_child label won't work
>    correctly if channel1 is before channel at 0 in the device tree
> 
> IOW the driver is not robust against all legal device tree descriptions,
> and it could be easily made robust using the example code in my
> previous e-mail (quoted a few lines above).
> 
> If you agree about this I'll be happy to send a patch doing that change.
> If you think I'm wrong, I won't fight a battle. This topic is
> orthogonal to the change I'm introducing in this patch, and I can
> continue the conversion independently from this discussion.

I don't think it is necessary to do that change for now.  When someone
really comes across this issue, we may make the error management code
robust.

> 
>>> Thanks for taking the time to dig into this!  
>>
>> After looking into this patch and patch 31(though I've already provided my A-b)
>> more closely, I think the imx8qxp_pc and imx8{qm,qxp}_ldb main structures
>> should have the same life time with the embedded DRM bridges, because for
>> example the clk_apb clock in struct imx8qxp_pc would be accessed by the
>> imx8qxp_pc_bridge_mode_set DRM bridge callback.  But, IIUC, your patches extend
>> the life time for the embedded channel/bridge structures only, but not for the
>> main structures.  What do you think ?
> 
> I see you concern, but I'm sure the change I'm introducing is not
> creating the problem you are concerned about.
> 
> The key aspect is that my patch is merely changing the lifetime of the
> _allocation_ of the drm_bridge, not its usage. On drm_bridge_remove()
> the bridge is removed from its encoder chain and it is completely not
> reachable, both before and after my patch. With my patch it is not
> freed immediately, but it's just a piece of "wasted" memory that is
> still allocated until elsewhere in the kernel there are pointers to it,
> to avoid use-after-free.
> 
> With this explanation, do you think my patch is correct (after fixing
> the bug we already discussed of course)?

I tend to say your patch is not correct because we'll eventually make sure
that removing a bridge module is safe when doing atomic commit, which means
the main structures should have the same life time with the DRM bridges.

> 
> Best regards,
> Luca
> 

-- 
Regards,
Liu Ying


From peter.wang at mediatek.com  Tue May  6 21:03:24 2025
From: peter.wang at mediatek.com (=?utf-8?B?UGV0ZXIgV2FuZyAo546L5L+h5Y+LKQ==?=)
Date: Wed, 7 May 2025 04:03:24 +0000
Subject: [PATCH v1] ufs: core: fix hwq_id type and value
In-Reply-To: <04fc1549-0fa6-4956-b522-df5fbc26100c@acm.org>
References: <20250506124038.4071609-1-peter.wang@mediatek.com>
	 <04fc1549-0fa6-4956-b522-df5fbc26100c@acm.org>
Message-ID: <6c9e983154ff8d9b4a1e63eb503e8b147303eb68.camel@mediatek.com>

On Tue, 2025-05-06 at 09:15 -0700, Bart Van Assche wrote:
> 
> Is this change really necessary? I like the current behavior because
> it
> makes it easy to figure out whether or not MCQ has been enabled. Even
> if
> others would agree with this change, I think that the "Fixes:" and
> "Cc:
> stable" tags are overkill because I don't see this as a bug fix but
> rather as a behavior change that is not a bug fix.
> 
> Thanks,
> 
> Bart.


Hi Bart,

Whether it is necessary or not depends on how we define 'necessary.' 
If the criterion is simply to avoid errors, then indeed, this patch 
is not necessary. However, if we are addressing the warning caused 
by incorrect behavior (assigning int to u32), then it is necessary 
to fix it. After all, we shouldn't just be satisfied with avoiding 
errors, we should strive to make the Linux kernel as perfect as 
possible, shouldn't we?

Additionally, there are many ways to determine whether MCQ is enabled,
including reading the host capability or checking hba->mcq_enabled,
etc. 
Moreover, MCQ is not a feature that trun on and off at runtime.
It is at the end of the UFS initialization that the status of MCQ 
is determined, so it shouldn't be necessary to rely on this to 
determine whether MCQ is enabled, right?

Thanks
Peter



From allan.wang at mediatek.com  Tue May  6 22:31:31 2025
From: allan.wang at mediatek.com (Allan Wang)
Date: Wed, 7 May 2025 13:31:31 +0800
Subject: [PATCH v2] wifi: mt76: mt7925: add rfkill_poll for hardware rfkill
Message-ID: <20250507053131.4173691-1-allan.wang@mediatek.com>

Add mac80211 rfkill_poll ops to monitor hardware rfkill state
and state change will be updated.

Signed-off-by: Allan Wang <allan.wang at mediatek.com>

---
v2: Refine coding style
---
 .../wireless/mediatek/mt76/mt76_connac_mcu.h  |  1 +
 .../net/wireless/mediatek/mt76/mt7925/main.c  | 16 ++++++++
 .../net/wireless/mediatek/mt76/mt7925/mcu.c   | 37 +++++++++++++++++++
 .../wireless/mediatek/mt76/mt7925/mt7925.h    |  1 +
 .../net/wireless/mediatek/mt76/mt7925/pci.c   |  4 ++
 5 files changed, 59 insertions(+)

diff --git a/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h b/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h
index 478cd1886736..e195d69f61f6 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h
@@ -1298,6 +1298,7 @@ enum {
 	MCU_UNI_CMD_PER_STA_INFO = 0x6d,
 	MCU_UNI_CMD_ALL_STA_INFO = 0x6e,
 	MCU_UNI_CMD_ASSERT_DUMP = 0x6f,
+	MCU_UNI_CMD_RADIO_STATUS = 0x80,
 	MCU_UNI_CMD_SDO = 0x88,
 };
 
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/main.c b/drivers/net/wireless/mediatek/mt76/mt7925/main.c
index 83f93f9e002c..e1ea7136751a 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/main.c
@@ -334,6 +334,9 @@ int __mt7925_start(struct mt792x_phy *phy)
 	ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work,
 				     MT792x_WATCHDOG_TIME);
 
+	if (phy->chip_cap & MT792x_CHIP_CAP_WF_RF_PIN_CTRL_EVT_EN)
+		wiphy_rfkill_start_polling(mphy->hw->wiphy);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(__mt7925_start);
@@ -2205,6 +2208,18 @@ static void mt7925_unassign_vif_chanctx(struct ieee80211_hw *hw,
 	mutex_unlock(&dev->mt76.mutex);
 }
 
+static void mt7925_rfkill_poll(struct ieee80211_hw *hw)
+{
+	struct mt792x_phy *phy = mt792x_hw_phy(hw);
+	int ret;
+
+	mt792x_mutex_acquire(phy->dev);
+	ret = mt7925_mcu_wf_rf_pin_ctrl(phy);
+	mt792x_mutex_release(phy->dev);
+
+	wiphy_rfkill_set_hw_state(hw->wiphy, ret == 0);
+}
+
 const struct ieee80211_ops mt7925_ops = {
 	.tx = mt792x_tx,
 	.start = mt7925_start,
@@ -2265,6 +2280,7 @@ const struct ieee80211_ops mt7925_ops = {
 	.link_info_changed = mt7925_link_info_changed,
 	.change_vif_links = mt7925_change_vif_links,
 	.change_sta_links = mt7925_change_sta_links,
+	.rfkill_poll = mt7925_rfkill_poll,
 };
 EXPORT_SYMBOL_GPL(mt7925_ops);
 
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
index 286f602623c0..ec4c4a027922 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
@@ -3633,6 +3633,43 @@ int mt7925_mcu_set_rate_txpower(struct mt76_phy *phy)
 	return 0;
 }
 
+int mt7925_mcu_wf_rf_pin_ctrl(struct mt792x_phy *phy)
+{
+#define UNI_CMD_RADIO_STATUS_GET	0
+	struct mt792x_dev *dev = phy->dev;
+	struct sk_buff *skb;
+	int ret;
+	struct {
+		__le16 tag;
+		__le16 len;
+		u8 rsv[4];
+	} __packed req = {
+		.tag = UNI_CMD_RADIO_STATUS_GET,
+		.len = cpu_to_le16(sizeof(req)),
+	};
+	struct mt7925_radio_status_event {
+		__le16 tag;
+		__le16 len;
+
+		u8 data;
+		u8 rsv[3];
+	} __packed *status;
+
+	ret = mt76_mcu_send_and_get_msg(&dev->mt76,
+					MCU_UNI_CMD(RADIO_STATUS),
+					&req, sizeof(req), true, &skb);
+	if (ret)
+		return ret;
+
+	skb_pull(skb, sizeof(struct tlv));
+	status = (struct mt7925_radio_status_event *)skb->data;
+	ret = status->data;
+
+	dev_kfree_skb(skb);
+
+	return ret;
+}
+
 int mt7925_mcu_set_rxfilter(struct mt792x_dev *dev, u32 fif,
 			    u8 bit_op, u32 bit_map)
 {
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h b/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
index 4e50f2597ccd..283a40badd28 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
@@ -365,5 +365,6 @@ int mt7925_mcu_wtbl_update_hdr_trans(struct mt792x_dev *dev,
 				     struct ieee80211_vif *vif,
 				     struct ieee80211_sta *sta,
 				     int link_id);
+int mt7925_mcu_wf_rf_pin_ctrl(struct mt792x_phy *phy);
 
 #endif
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/pci.c b/drivers/net/wireless/mediatek/mt76/mt7925/pci.c
index c7b5dc1dbb34..b997cd8bf8d0 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/pci.c
@@ -31,6 +31,10 @@ static void mt7925e_unregister_device(struct mt792x_dev *dev)
 {
 	int i;
 	struct mt76_connac_pm *pm = &dev->pm;
+	struct ieee80211_hw *hw = mt76_hw(dev);
+
+	if (dev->phy.chip_cap & MT792x_CHIP_CAP_WF_RF_PIN_CTRL_EVT_EN)
+		wiphy_rfkill_stop_polling(hw->wiphy);
 
 	cancel_work_sync(&dev->init_work);
 	mt76_unregister_device(&dev->mt76);
-- 
2.45.2



From chenqiuji666 at gmail.com  Tue May  6 22:37:36 2025
From: chenqiuji666 at gmail.com (Qiu-ji Chen)
Date: Wed,  7 May 2025 13:37:36 +0800
Subject: [PATCH] dmaengine: mediatek: Fix a possible deadlock error in mtk_cqdma_tx_status()
Message-ID: <20250507053736.47220-1-chenqiuji666@gmail.com>

This patch fixes a potential deadlock bug. We observed that in the
mtk-cqdma.c file, most functions like mtk_cqdma_issue_pending() and
mtk_cqdma_free_active_desc() follow the correct locking sequence by
acquiring the pc lock first before taking the vc lock when handling the vc
and pc fields. However, in mtk_cqdma_tx_status(), the function incorrectly
acquires the vc lock first before calling mtk_cqdma_find_active_desc(),
which subsequently acquires the pc lock. This reversed lock acquisition
order (vc ? pc) violates the established sequence (pc ? vc) and could
potentially trigger deadlock scenarios.

To resolve this issue, we have moved the vc lock acquisition code from
mtk_cqdma_tx_status() into the mtk_cqdma_find_active_desc() function.
This adjustment ensures proper lock ordering while maintaining
functionality. Since mtk_cqdma_find_active_desc() is a static function
with only one call site in mtk_cqdma_tx_status(), this fix effectively
addresses the deadlock risk without introducing unintended side effects
to other components.

This possible bug is found by an experimental static analysis tool
developed by our team. This tool analyzes the locking APIs to extract
function pairs that can be concurrently executed, and then analyzes the
instructions in the paired functions to identify possible concurrency bugs
including data races and atomicity violations.

Fixes: b1f01e48df5a ("dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC")
Cc: stable at vger.kernel.org
Signed-off-by: Qiu-ji Chen <chenqiuji666 at gmail.com>
---
 drivers/dma/mediatek/mtk-cqdma.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index d5ddb4e30e71..656354bccb44 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -423,11 +423,14 @@ static struct virt_dma_desc *mtk_cqdma_find_active_desc(struct dma_chan *c,
 	unsigned long flags;
 
 	spin_lock_irqsave(&cvc->pc->lock, flags);
+	spin_lock_irqsave(&cvc->vc.lock, flags);
 	list_for_each_entry(vd, &cvc->pc->queue, node)
 		if (vd->tx.cookie == cookie) {
+			spin_unlock_irqrestore(&cvc->vc.lock, flags);
 			spin_unlock_irqrestore(&cvc->pc->lock, flags);
 			return vd;
 		}
+	spin_unlock_irqrestore(&cvc->vc.lock, flags);
 	spin_unlock_irqrestore(&cvc->pc->lock, flags);
 
 	list_for_each_entry(vd, &cvc->vc.desc_issued, node)
@@ -452,9 +455,7 @@ static enum dma_status mtk_cqdma_tx_status(struct dma_chan *c,
 	if (ret == DMA_COMPLETE || !txstate)
 		return ret;
 
-	spin_lock_irqsave(&cvc->vc.lock, flags);
 	vd = mtk_cqdma_find_active_desc(c, cookie);
-	spin_unlock_irqrestore(&cvc->vc.lock, flags);
 
 	if (vd) {
 		cvd = to_cqdma_vdesc(vd);
-- 
2.34.1



From andyshrk at 163.com  Tue May  6 23:09:13 2025
From: andyshrk at 163.com (Andy Yan)
Date: Wed, 7 May 2025 14:09:13 +0800 (CST)
Subject: [PATCH 1/1] drm/bridge: Pass down connector to drm bridge
 detect hook
In-Reply-To: <1bb549f4.746e.1965c8256e4.Coremail.andyshrk@163.com>
References: <20250321085345.136380-1-andyshrk@163.com>
 <20250321085345.136380-2-andyshrk@163.com>
 <20250321-optimistic-prompt-civet-bdcdba@houat>
 <1bb549f4.746e.1965c8256e4.Coremail.andyshrk@163.com>
Message-ID: <20cd09da.5462.196a95cce13.Coremail.andyshrk@163.com>



Ping......

At 2025-04-22 15:59:27, "Andy Yan" <andyshrk at 163.com> wrote:
>
>Hi all,
>
>At 2025-03-21 17:48:04, "Maxime Ripard" <mripard at kernel.org> wrote:
>>On Fri, Mar 21, 2025 at 04:53:38PM +0800, Andy Yan wrote:
>>> From: Andy Yan <andy.yan at rock-chips.com>
>>> 
>>> In some application scenarios, we hope to get the corresponding
>>> connector when the bridge's detect hook is invoked.
>>> 
>>> In most cases, we can get the connector by drm_atomic_get_connector_for_encoder
>>> if the encoder attached to the bridge is enabled, however there will
>>> still be some scenarios where the detect hook of the bridge is called
>>> but the corresponding encoder has not been enabled yet. For instance,
>>> this occurs when the device is hot plug in for the first time.
>>> 
>>> Since the call to bridge's detect is initiated by the connector, passing
>>> down the corresponding connector directly will make things simpler.
>>> 
>>> Signed-off-by: Andy Yan <andy.yan at rock-chips.com>
>>
>>FTR, I'm against it and would have appreciated that you wait for a
>>meaningful closure to the discussion we've had on this.
>
>Can we start to review this patch? Since it's been almost a month now and
>no one has raised any objection to Dmitry's suggestion[1].
>
>
>[1]https://lore.kernel.org/dri-devel/vw2ncdomx3rwltb2xlo6nf3rapgcdtcjcodofgmecrzzabf7ji at pybsfv27jkq2/
>
>
>>
>>Maxime

From peng.fan at oss.nxp.com  Wed May  7 00:33:18 2025
From: peng.fan at oss.nxp.com (Peng Fan)
Date: Wed, 7 May 2025 15:33:18 +0800
Subject: [PATCH v2 08/17] arm/arm64: dts: imx: Drop redundant CPU
 "clock-latency"
In-Reply-To: <20250410-dt-cpu-schema-v2-8-63d7dc9ddd0a@kernel.org>
References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org>
 <20250410-dt-cpu-schema-v2-8-63d7dc9ddd0a@kernel.org>
Message-ID: <20250507073318.GB2351@nxa18884-linux>

On Thu, Apr 10, 2025 at 10:47:29AM -0500, Rob Herring (Arm) wrote:
>The "clock-latency" property is part of the deprecated opp-v1 binding
>and is redundant if the opp-v2 table has equal or larger values in any
>"clock-latency-ns". The OPP tables have values of 150000, so it can be
>removed.
>
>Signed-off-by: Rob Herring (Arm) <robh at kernel.org>
>---
> arch/arm/boot/dts/nxp/imx/imx7s.dtsi      | 1 -
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 4 ----
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 4 ----
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ----
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 4 ----
> 5 files changed, 17 deletions(-)
>

Acked-by: Peng Fan <peng.fan at nxp.com>


From luca.ceresoli at bootlin.com  Wed May  7 00:12:44 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Wed, 7 May 2025 09:12:44 +0200
Subject: [PATCH v2 30/34] drm/bridge: imx8qxp-pixel-combiner: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <a1abf31a-7a4a-4f8d-bf48-6b826aa01197@nxp.com>
References: <20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b@bootlin.com>
	<20250424-drm-bridge-convert-to-alloc-api-v2-30-8f91a404d86b@bootlin.com>
	<553d62ed-976a-4e17-9678-cdc3d40ce4a7@nxp.com>
	<20250430112944.1b39caab@booty>
	<f71d18d2-4271-4bb9-b54f-0e5a585778f3@nxp.com>
	<20250506224720.5cbcf3e1@booty>
	<a1abf31a-7a4a-4f8d-bf48-6b826aa01197@nxp.com>
Message-ID: <20250507091244.32865a71@booty>

Hello Liu,

On Wed, 7 May 2025 10:10:53 +0800
Liu Ying <victor.liu at nxp.com> wrote:

> On 05/07/2025, Luca Ceresoli wrote:
> > Hello Liu,  
> 
> Hi Luca,
> 
> > 
> > thanks for your further feedback.
> > 
> > On Tue, 6 May 2025 10:24:18 +0800
> > Liu Ying <victor.liu at nxp.com> wrote:
> >   
> >> On 04/30/2025, Luca Ceresoli wrote:  
> >>> Hello Liu,    
> >>
> >> Hi Luca,
> >>  
> >>>
> >>> On Tue, 29 Apr 2025 10:10:55 +0800
> >>> Liu Ying <victor.liu at nxp.com> wrote:
> >>>     
> >>>> Hi,
> >>>>
> >>>> On 04/25/2025, Luca Ceresoli wrote:    
> >>>>> This is the new API for allocating DRM bridges.
> >>>>>
> >>>>> This driver embeds an array of channels in the main struct, and each
> >>>>> channel embeds a drm_bridge. This prevents dynamic, refcount-based
> >>>>> deallocation of the bridges.
> >>>>>
> >>>>> To make the new, dynamic bridge allocation possible:
> >>>>>
> >>>>>  * change the array of channels into an array of channel pointers
> >>>>>  * allocate each channel using devm_drm_bridge_alloc()
> >>>>>  * adapt the code wherever using the channels
> >>>>>
> >>>>> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>    
> >>>
> >>> [...]
> >>>     
> >>>>> @@ -345,8 +351,8 @@ static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
> >>>>>  free_child:
> >>>>>  	of_node_put(child);
> >>>>>  
> >>>>> -	if (i == 1 && pc->ch[0].next_bridge)
> >>>>> -		drm_bridge_remove(&pc->ch[0].bridge);
> >>>>> +	if (i == 1 && pc->ch[0]->next_bridge)      
> >>>>
> >>>> Since this patch makes pc->ch[0] and pc->ch[1] be allocated separately,
> >>>> pc->ch[0] could be NULL if channel0 is not available, hence a NULL pointer
> >>>> dereference here...    
> >>>
> >>> See below for this.
> >>>     
> >>>>> +		drm_bridge_remove(&pc->ch[0]->bridge);
> >>>>>  
> >>>>>  	pm_runtime_disable(dev);
> >>>>>  	return ret;
> >>>>> @@ -359,7 +365,7 @@ static void imx8qxp_pc_bridge_remove(struct platform_device *pdev)
> >>>>>  	int i;
> >>>>>  
> >>>>>  	for (i = 0; i < 2; i++) {
> >>>>> -		ch = &pc->ch[i];
> >>>>> +		ch = pc->ch[i];
> >>>>>  
> >>>>>  		if (!ch->is_available)      
> >>>>
> >>>> ...and here too.    
> >>>
> >>> This is indeed a bug, I should have checked the pointer for being
> >>> non-NULL.
> >>>
> >>> Looking at that more closely, I think the is_available flag can be
> >>> entirely removed now. The allocation itself (ch != NULL) now is
> >>> equivalent. Do you think my reasoning is correct?
> >>>
> >>> Ouch! After writing the previous paragraph I realized you proposed this
> >>> a few lines below! OK, removing is_available. :)
> >>>
> >>> [...]
> >>>     
> >>>> On top of this patch series, this issue doesn't happen if I apply the below
> >>>> change:    
> >>>
> >>> [...]
> >>>     
> >>>> @@ -351,7 +349,7 @@ static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
> >>>>  free_child:
> >>>>         of_node_put(child);
> >>>>  
> >>>> -       if (i == 1 && pc->ch[0]->next_bridge)
> >>>> +       if (i == 1 && pc->ch[0])
> >>>>                 drm_bridge_remove(&pc->ch[0]->bridge);    
> >>>
> >>> Unrelated to this patch, but as I looked at it more in depth now, I'm
> >>> not sure this whole logic is robust, even in the original code.
> >>>
> >>> The 'i == 1' check here seems to mean "if some error happened when
> >>> handling channel at 1, that means channel at 0 was successfully initialized,
> >>> so let's clean up channel 0".
> >>>
> >>> However my understanding of the bindings is that device tree is allowed
> >>> to have the channel at 1 node before the channel at 0 node (or even channel at 1
> >>> without channel at 0, but that's less problematic here).
> >>>
> >>> In such case (channel at 1 before channel at 0), this would happen:
> >>>
> >>>  1. alloc and init ch[1], all OK
> >>>  2. alloc and init ch[0], an error happens
> >>>     (e.g. of_graph_get_remote_node() fails)
> >>>
> >>> So we'd reach the free_child: label, and we should call
> >>> drm_bridge_remove() for ch[1]->bridge, but there's no code to do that.
> >>>
> >>> To be robust in such a case, I think both channels need to be checked
> >>> independently, as the status of one does not imply the status of the
> >>> other. E.g.:
> >>>
> >>>   for (i = 0; i < 2; i++)
> >>>       if (pc->ch[i] && pc->ch[i]->next_bridge)
> >>>           drm_bridge_remove(&pc->ch[i]->bridge);
> >>>
> >>> (which is similar to what .remove() does after the changes discussed in
> >>> this thread, and which I have queued for v3)
> >>>
> >>> What's your opinion? Do you think I missed anything?    
> >>
> >> The pixel combiner DT node would be added in imx8-ss-dc{0,1}.dtsi, please
> >> see the case for imx8-ss-dc0.dtsi introduced by an in-flight patch[1].  As
> >> channel@{0,1} child nodes always exist(DT overlay cannot effectively delete
> >> any of them) and channel at 0 always comes first, there is no problematic case.  
> > 
> > I'm not questioning what existing and future dts files (will) contain,
> > and surely I don't see a good reason someone would write channel at 1
> > before channel at 0.
> > 
> > My point is:
> > 
> >  - the bindings _allow_ channel1 before channel at 0
> >  - the error management code after the free_child label won't work
> >    correctly if channel1 is before channel at 0 in the device tree
> > 
> > IOW the driver is not robust against all legal device tree descriptions,
> > and it could be easily made robust using the example code in my
> > previous e-mail (quoted a few lines above).
> > 
> > If you agree about this I'll be happy to send a patch doing that change.
> > If you think I'm wrong, I won't fight a battle. This topic is
> > orthogonal to the change I'm introducing in this patch, and I can
> > continue the conversion independently from this discussion.  
> 
> I don't think it is necessary to do that change for now.  When someone
> really comes across this issue, we may make the error management code
> robust.
> 
> >   
> >>> Thanks for taking the time to dig into this!    
> >>
> >> After looking into this patch and patch 31(though I've already provided my A-b)
> >> more closely, I think the imx8qxp_pc and imx8{qm,qxp}_ldb main structures
> >> should have the same life time with the embedded DRM bridges, because for
> >> example the clk_apb clock in struct imx8qxp_pc would be accessed by the
> >> imx8qxp_pc_bridge_mode_set DRM bridge callback.  But, IIUC, your patches extend
> >> the life time for the embedded channel/bridge structures only, but not for the
> >> main structures.  What do you think ?  
> > 
> > I see you concern, but I'm sure the change I'm introducing is not
> > creating the problem you are concerned about.
> > 
> > The key aspect is that my patch is merely changing the lifetime of the
> > _allocation_ of the drm_bridge, not its usage. On drm_bridge_remove()
> > the bridge is removed from its encoder chain and it is completely not
> > reachable, both before and after my patch. With my patch it is not
> > freed immediately, but it's just a piece of "wasted" memory that is
> > still allocated until elsewhere in the kernel there are pointers to it,
> > to avoid use-after-free.
> > 
> > With this explanation, do you think my patch is correct (after fixing
> > the bug we already discussed of course)?  
> 
> I tend to say your patch is not correct because we'll eventually make sure
> that removing a bridge module is safe when doing atomic commit,

I think your sentence can be rephrased as "your patch is correct with
the current code base where bridges are not (yet) removable, but there
will be a problem when they start to actually be removable".

Is my understanding correct? If it is, I agree on that sentence.

The work to have removable bridges is massive and non-trivial, so it
will need to be tackled in steps. The grand plan [0] is:

 1. add refcounting to DRM bridges (struct drm_bridge)
 2. handle gracefully atomic updates during bridge removal
 3. avoid DSI host drivers to have dangling pointers to DSI devices 
 4. finish the hotplug bridge work, removing the "always-disconnected"
    connector, moving code to the core and potentially removing the
    hotplug-bridge itself (this needs to be clarified as points 1-3 are
    developed)

I am at step 1 right now. Removal during atomic updates is step 2,
ideas about how to implement that are already being discussed [1],
there's a practical plan proposed by Maxime with the goal of reaching
removable bridges without breaking things along the path.

[0] https://lore.kernel.org/lkml/20250206-hotplug-drm-bridge-v6-0-9d6f2c9c3058 at bootlin.com/
[1] https://lore.kernel.org/all/20250106-vigorous-talented-viper-fa49d9 at houat/

> which means
> the main structures should have the same life time with the DRM bridges.

The word "lifetime" mean two things for bridges:

 * the time span during which memory is allocated for a struct
   drm_bridge (along with the embedding struct)
 * the time span during which a DRM bridge is active/used/usable as
   part of a card
   - i.e. when it is part of an encoder chain
   - i.e. when drm_bridge_funcs callbacks can be called
   - i.e. from drm_bridge_add() to drm_bridge_remove()

These two lifetimes used to be nearly the same. Now the "memory
allocation lifetime" is extended, but the "bridge existence" is
unchanged: drm_bridge_add() to drm_bridge_remove() are called in the
same place and do the same things, so the bridge will stop being in any
encoder chain at the exact same time. now we are just keeping a piece of
memory allocated for a longer time.

Seen in another way, the events used to be:

 * probe:
   - allocate bridge
   - drm_bridge_add()

 * remove
   - drm_bridge_remove()
   - now the bridge is not used, it's just some dead memory [*]
   - kfree bridge (either in .remove() or just after by devm)

Now it becomes:

 * probe:
   - allocate bridge
   - drm_bridge_add()

 * remove
   - drm_bridge_remove()
   - now the bridge is not used, it's just some dead memory [*]
   - maybe some more time, possibly long, until the last put [*]
   - kfree bridge (by devm)

The duration of the [*] steps changes, but it's harmless because the
bridge is not used at all. No change except for memory allocation.

Luca

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


From amergnat at baylibre.com  Wed May  7 00:48:55 2025
From: amergnat at baylibre.com (Alexandre Mergnat)
Date: Wed, 7 May 2025 09:48:55 +0200
Subject: [PATCH] arm64: dts: mediatek: mt6357: Drop regulator-fixed
 compatibles
In-Reply-To: <1e8b80c9-d491-4b71-b424-e2322c711fd3@notapiano>
References: <20250502-mt6357-regulator-fixed-compatibles-removal-v1-1-a582c16743fe@collabora.com>
 <174652097090.119919.16240846809714782858.b4-ty@collabora.com>
 <99febf26-2ada-4fed-b4b3-596ac4abf581@baylibre.com>
 <1e8b80c9-d491-4b71-b424-e2322c711fd3@notapiano>
Message-ID: <50ef47ca-1054-4b5a-a7d7-56e6cfcb863e@baylibre.com>



On 06/05/2025 23:20, N?colas F. R. A. Prado wrote:
> On Tue, May 06, 2025 at 11:30:08AM +0200, Alexandre Mergnat wrote:
>> Hello N?colas and Angelo,
>>
>> On 06/05/2025 10:42, AngeloGioacchino Del Regno wrote:
>>> On Fri, 02 May 2025 11:32:10 -0400, N?colas F. R. A. Prado wrote:
>>>> Some of the regulators in the MT6357 PMIC dtsi have compatible set to
>>>> regulator-fixed, even though they don't serve any purpose: all those
>>>> regulators are handled as a whole by the mt6357-regulator driver. In
>>>> fact this is the only dtsi in this family of chips where this is the
>>>> case: mt6359 and mt6358 don't have any such compatibles.
>>>>
>>>> A side-effect caused by this is that the DT kselftest, which is supposed
>>>> to identify nodes with compatibles that can be probed, but haven't,
>>>> shows these nodes as failures.
>>>>
>>>> [...]
>>>
>>> Applied to v6.15-next/dts64, thanks!
>>>
>>> [1/1] arm64: dts: mediatek: mt6357: Drop regulator-fixed compatibles
>>>         commit: d77e89b7b03fb945b4353f2dcc4a70b34baa7bcb
>>
>> I'm surprised that patch is applied after the Rob's bot reply.
>> Also, I've some concern:
>>
>> On 02/05/2025 17:32, N?colas F. R. A. Prado wrote:
>>> Some of the regulators in the MT6357 PMIC dtsi have compatible set to
>>> regulator-fixed, even though they don't serve any purpose: all those
>>> regulators are handled as a whole by the mt6357-regulator driver. In
>>> fact this is the only dtsi in this family of chips where this is the
>>> case: mt6359 and mt6358 don't have any such compatibles.
>> This is the only dtsi in this family to do this, yes. But according to
>> all other vendor DTSI, which use regulator-fixed when a regulator can't
>> support a range of voltage, IMHO, it make sense to use it, isn't it ?
>> If other DTSI from the family of chips doesn't, why don't fix them to be
>> aligned with the other families?
> 
> Well, but this isn't just like any other regulator-fixed in a DTSI. In this case
> it is part of a multi-function device (MFD) and so it gets probed by a parent
> node. That's the source of the issue, because then no driver gets assigned to
> the node itself.
> 

Ok, thanks for the details. After Quick check, Maxim does't use "regulator-fixed"
in the MFD too.

>>
>>>
>>> A side-effect caused by this is that the DT kselftest, which is supposed
>>> to identify nodes with compatibles that can be probed, but haven't,
>>> shows these nodes as failures.
>>>
>> I lack of data about kselftest, but according to what is reported here, it
>> appear to me this is something which could be fixed in the test itself. It make
>> sense for a DTS, but not for a DTSI because it expose HW capability of a
>> device, not the board, so it isn't mandatory to probe all DTSI node.
>> Again, I'm not an expert, the test shouldn't show the DTSI node as failure,
>> but maybe more a warning.
> 
> The DT kselftest is a run-time test, so it wouldn't be able to distinguish
> between DTSI and DTS. But in any case, we do want to check that devices from
> DTSIs have probed, a lot of the devices come from them. When a particular board
> doesn't actually have a node from a DTSI present then the node should be
> disabled, and in that case the kselftest ignores the node.
> 
> It would be possible to ignore this particular compatible, "regulator-fixed", in
> the kselftest, if it is a compatible that can't be expected to be probed. Of
> course that would mean that all the other regulator nodes that aren't MFD
> children and do get probed by that driver would no longer be checked by the
> test.
> 

Yeah this isn't the wanted behavior.

>>
>>> Remove the useless compatibles to move the dtsi in line with the others
>>> in its family and fix the DT kselftest failures.
>> If you remove compatible from these regulators, I think mediatek,mt6357-regulator.yaml
>> documentation file should be modified to be consistent and avoid dt-check error.
> 
> Ah, yes, totally agreed, I seem to have missed running dtbs_check on this patch,
> sorry. Indeed now either the binding needs to be fixed or the patch reverted.
> 
> I believe the most reasonable option would be to update those regulators in the
> binding to reference the generic regulator binding, ie:
> 
> diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml
> index 6327bb2f6ee0..9308008f420e 100644
> --- a/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml
> +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml
> @@ -33,7 +33,7 @@ patternProperties:
> 
>     "^ldo-v(camio18|aud28|aux18|io18|io28|rf12|rf18|cn18|cn28|fe28)$":
>       type: object
> -    $ref: fixed-regulator.yaml#
> +    $ref: regulator.yaml#
>       unevaluatedProperties: false
>       description:
>         Properties for single fixed LDO regulator.
> 
> as well as updating the examples in the YAML. The fixed-regulator.yaml binding
> doesn't seem to provide any additional checks compared to regulator.yaml,
> besides enforcing the regulator-fixed compatible, which in this case doesn't
> serve any purpose.
> 
> Thoughts?
> 

Yes, IMHO, this yaml change should be enough.

-- 
Thanks,
Alexandre


From victor.liu at nxp.com  Wed May  7 03:16:28 2025
From: victor.liu at nxp.com (Liu Ying)
Date: Wed, 7 May 2025 18:16:28 +0800
Subject: [PATCH v2 30/34] drm/bridge: imx8qxp-pixel-combiner: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250507091244.32865a71@booty>
References: <20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b@bootlin.com>
 <20250424-drm-bridge-convert-to-alloc-api-v2-30-8f91a404d86b@bootlin.com>
 <553d62ed-976a-4e17-9678-cdc3d40ce4a7@nxp.com>
 <20250430112944.1b39caab@booty>
 <f71d18d2-4271-4bb9-b54f-0e5a585778f3@nxp.com>
 <20250506224720.5cbcf3e1@booty>
 <a1abf31a-7a4a-4f8d-bf48-6b826aa01197@nxp.com>
 <20250507091244.32865a71@booty>
Message-ID: <430d497d-45a1-436d-91fd-635854f80c9f@nxp.com>

On 05/07/2025, Luca Ceresoli wrote:
> Hello Liu,
> 
> On Wed, 7 May 2025 10:10:53 +0800
> Liu Ying <victor.liu at nxp.com> wrote:
> 
>> On 05/07/2025, Luca Ceresoli wrote:
>>> Hello Liu,  
>>
>> Hi Luca,
>>
>>>
>>> thanks for your further feedback.
>>>
>>> On Tue, 6 May 2025 10:24:18 +0800
>>> Liu Ying <victor.liu at nxp.com> wrote:
>>>   
>>>> On 04/30/2025, Luca Ceresoli wrote:  
>>>>> Hello Liu,    
>>>>
>>>> Hi Luca,
>>>>  
>>>>>
>>>>> On Tue, 29 Apr 2025 10:10:55 +0800
>>>>> Liu Ying <victor.liu at nxp.com> wrote:
>>>>>     
>>>>>> Hi,
>>>>>>
>>>>>> On 04/25/2025, Luca Ceresoli wrote:    
>>>>>>> This is the new API for allocating DRM bridges.
>>>>>>>
>>>>>>> This driver embeds an array of channels in the main struct, and each
>>>>>>> channel embeds a drm_bridge. This prevents dynamic, refcount-based
>>>>>>> deallocation of the bridges.
>>>>>>>
>>>>>>> To make the new, dynamic bridge allocation possible:
>>>>>>>
>>>>>>>  * change the array of channels into an array of channel pointers
>>>>>>>  * allocate each channel using devm_drm_bridge_alloc()
>>>>>>>  * adapt the code wherever using the channels
>>>>>>>
>>>>>>> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>    
>>>>>
>>>>> [...]
>>>>>     
>>>>>>> @@ -345,8 +351,8 @@ static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
>>>>>>>  free_child:
>>>>>>>  	of_node_put(child);
>>>>>>>  
>>>>>>> -	if (i == 1 && pc->ch[0].next_bridge)
>>>>>>> -		drm_bridge_remove(&pc->ch[0].bridge);
>>>>>>> +	if (i == 1 && pc->ch[0]->next_bridge)      
>>>>>>
>>>>>> Since this patch makes pc->ch[0] and pc->ch[1] be allocated separately,
>>>>>> pc->ch[0] could be NULL if channel0 is not available, hence a NULL pointer
>>>>>> dereference here...    
>>>>>
>>>>> See below for this.
>>>>>     
>>>>>>> +		drm_bridge_remove(&pc->ch[0]->bridge);
>>>>>>>  
>>>>>>>  	pm_runtime_disable(dev);
>>>>>>>  	return ret;
>>>>>>> @@ -359,7 +365,7 @@ static void imx8qxp_pc_bridge_remove(struct platform_device *pdev)
>>>>>>>  	int i;
>>>>>>>  
>>>>>>>  	for (i = 0; i < 2; i++) {
>>>>>>> -		ch = &pc->ch[i];
>>>>>>> +		ch = pc->ch[i];
>>>>>>>  
>>>>>>>  		if (!ch->is_available)      
>>>>>>
>>>>>> ...and here too.    
>>>>>
>>>>> This is indeed a bug, I should have checked the pointer for being
>>>>> non-NULL.
>>>>>
>>>>> Looking at that more closely, I think the is_available flag can be
>>>>> entirely removed now. The allocation itself (ch != NULL) now is
>>>>> equivalent. Do you think my reasoning is correct?
>>>>>
>>>>> Ouch! After writing the previous paragraph I realized you proposed this
>>>>> a few lines below! OK, removing is_available. :)
>>>>>
>>>>> [...]
>>>>>     
>>>>>> On top of this patch series, this issue doesn't happen if I apply the below
>>>>>> change:    
>>>>>
>>>>> [...]
>>>>>     
>>>>>> @@ -351,7 +349,7 @@ static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
>>>>>>  free_child:
>>>>>>         of_node_put(child);
>>>>>>  
>>>>>> -       if (i == 1 && pc->ch[0]->next_bridge)
>>>>>> +       if (i == 1 && pc->ch[0])
>>>>>>                 drm_bridge_remove(&pc->ch[0]->bridge);    
>>>>>
>>>>> Unrelated to this patch, but as I looked at it more in depth now, I'm
>>>>> not sure this whole logic is robust, even in the original code.
>>>>>
>>>>> The 'i == 1' check here seems to mean "if some error happened when
>>>>> handling channel at 1, that means channel at 0 was successfully initialized,
>>>>> so let's clean up channel 0".
>>>>>
>>>>> However my understanding of the bindings is that device tree is allowed
>>>>> to have the channel at 1 node before the channel at 0 node (or even channel at 1
>>>>> without channel at 0, but that's less problematic here).
>>>>>
>>>>> In such case (channel at 1 before channel at 0), this would happen:
>>>>>
>>>>>  1. alloc and init ch[1], all OK
>>>>>  2. alloc and init ch[0], an error happens
>>>>>     (e.g. of_graph_get_remote_node() fails)
>>>>>
>>>>> So we'd reach the free_child: label, and we should call
>>>>> drm_bridge_remove() for ch[1]->bridge, but there's no code to do that.
>>>>>
>>>>> To be robust in such a case, I think both channels need to be checked
>>>>> independently, as the status of one does not imply the status of the
>>>>> other. E.g.:
>>>>>
>>>>>   for (i = 0; i < 2; i++)
>>>>>       if (pc->ch[i] && pc->ch[i]->next_bridge)
>>>>>           drm_bridge_remove(&pc->ch[i]->bridge);
>>>>>
>>>>> (which is similar to what .remove() does after the changes discussed in
>>>>> this thread, and which I have queued for v3)
>>>>>
>>>>> What's your opinion? Do you think I missed anything?    
>>>>
>>>> The pixel combiner DT node would be added in imx8-ss-dc{0,1}.dtsi, please
>>>> see the case for imx8-ss-dc0.dtsi introduced by an in-flight patch[1].  As
>>>> channel@{0,1} child nodes always exist(DT overlay cannot effectively delete
>>>> any of them) and channel at 0 always comes first, there is no problematic case.  
>>>
>>> I'm not questioning what existing and future dts files (will) contain,
>>> and surely I don't see a good reason someone would write channel at 1
>>> before channel at 0.
>>>
>>> My point is:
>>>
>>>  - the bindings _allow_ channel1 before channel at 0
>>>  - the error management code after the free_child label won't work
>>>    correctly if channel1 is before channel at 0 in the device tree
>>>
>>> IOW the driver is not robust against all legal device tree descriptions,
>>> and it could be easily made robust using the example code in my
>>> previous e-mail (quoted a few lines above).
>>>
>>> If you agree about this I'll be happy to send a patch doing that change.
>>> If you think I'm wrong, I won't fight a battle. This topic is
>>> orthogonal to the change I'm introducing in this patch, and I can
>>> continue the conversion independently from this discussion.  
>>
>> I don't think it is necessary to do that change for now.  When someone
>> really comes across this issue, we may make the error management code
>> robust.
>>
>>>   
>>>>> Thanks for taking the time to dig into this!    
>>>>
>>>> After looking into this patch and patch 31(though I've already provided my A-b)
>>>> more closely, I think the imx8qxp_pc and imx8{qm,qxp}_ldb main structures
>>>> should have the same life time with the embedded DRM bridges, because for
>>>> example the clk_apb clock in struct imx8qxp_pc would be accessed by the
>>>> imx8qxp_pc_bridge_mode_set DRM bridge callback.  But, IIUC, your patches extend
>>>> the life time for the embedded channel/bridge structures only, but not for the
>>>> main structures.  What do you think ?  
>>>
>>> I see you concern, but I'm sure the change I'm introducing is not
>>> creating the problem you are concerned about.
>>>
>>> The key aspect is that my patch is merely changing the lifetime of the
>>> _allocation_ of the drm_bridge, not its usage. On drm_bridge_remove()
>>> the bridge is removed from its encoder chain and it is completely not
>>> reachable, both before and after my patch. With my patch it is not
>>> freed immediately, but it's just a piece of "wasted" memory that is
>>> still allocated until elsewhere in the kernel there are pointers to it,
>>> to avoid use-after-free.
>>>
>>> With this explanation, do you think my patch is correct (after fixing
>>> the bug we already discussed of course)?  
>>
>> I tend to say your patch is not correct because we'll eventually make sure
>> that removing a bridge module is safe when doing atomic commit,
> 
> I think your sentence can be rephrased as "your patch is correct with
> the current code base where bridges are not (yet) removable, but there
> will be a problem when they start to actually be removable".
> 
> Is my understanding correct? If it is, I agree on that sentence.

Nope, I meant your patch should align the life times of the main structures
and the DRM bridges, for the sake of the kinda long term goal - remove bridge
driver module safely when doing atomic commit.

> 
> The work to have removable bridges is massive and non-trivial, so it
> will need to be tackled in steps. The grand plan [0] is:
> 
>  1. add refcounting to DRM bridges (struct drm_bridge)
>  2. handle gracefully atomic updates during bridge removal
>  3. avoid DSI host drivers to have dangling pointers to DSI devices 
>  4. finish the hotplug bridge work, removing the "always-disconnected"
>     connector, moving code to the core and potentially removing the
>     hotplug-bridge itself (this needs to be clarified as points 1-3 are
>     developed)

I'm busy with internal things these days and cannot look into the grand
plan and steps closely, sorry about that.

> 
> I am at step 1 right now. Removal during atomic updates is step 2,
> ideas about how to implement that are already being discussed [1],
> there's a practical plan proposed by Maxime with the goal of reaching
> removable bridges without breaking things along the path.
> 
> [0] https://lore.kernel.org/lkml/20250206-hotplug-drm-bridge-v6-0-9d6f2c9c3058 at bootlin.com/
> [1] https://lore.kernel.org/all/20250106-vigorous-talented-viper-fa49d9 at houat/
> 
>> which means
>> the main structures should have the same life time with the DRM bridges.
> 
> The word "lifetime" mean two things for bridges:
> 
>  * the time span during which memory is allocated for a struct
>    drm_bridge (along with the embedding struct)

Note that with your patch set the imx8*-ldb drivers and this bridge driver
won't allocate the DRM bridge along with the embedding struct. This makes
me worry, because maybe these drivers are the only "special" ones in this
patch set and I don't want them to be "special" after your patch set is
applied.

>  * the time span during which a DRM bridge is active/used/usable as
>    part of a card
>    - i.e. when it is part of an encoder chain
>    - i.e. when drm_bridge_funcs callbacks can be called
>    - i.e. from drm_bridge_add() to drm_bridge_remove()
> 
> These two lifetimes used to be nearly the same. Now the "memory
> allocation lifetime" is extended, but the "bridge existence" is
> unchanged: drm_bridge_add() to drm_bridge_remove() are called in the
> same place and do the same things, so the bridge will stop being in any
> encoder chain at the exact same time. now we are just keeping a piece of
> memory allocated for a longer time.
> 
> Seen in another way, the events used to be:
> 
>  * probe:
>    - allocate bridge
>    - drm_bridge_add()
> 
>  * remove
>    - drm_bridge_remove()
>    - now the bridge is not used, it's just some dead memory [*]
>    - kfree bridge (either in .remove() or just after by devm)
> 
> Now it becomes:
> 
>  * probe:
>    - allocate bridge
>    - drm_bridge_add()
> 
>  * remove
>    - drm_bridge_remove()
>    - now the bridge is not used, it's just some dead memory [*]
>    - maybe some more time, possibly long, until the last put [*]
>    - kfree bridge (by devm)
> 
> The duration of the [*] steps changes, but it's harmless because the
> bridge is not used at all. No change except for memory allocation.
> 
> Luca
> 

-- 
Regards,
Liu Ying


From cjd at cjdns.fr  Wed May  7 06:44:53 2025
From: cjd at cjdns.fr (Caleb James DeLisle)
Date: Wed,  7 May 2025 13:44:53 +0000
Subject: [PATCH v5 0/7] Add EcoNet EN751221 MIPS platform support
Message-ID: <20250507134500.390547-1-cjd@cjdns.fr>

EcoNet MIPS SoCs are big endian machines based on 34Kc and 1004Kc
processors. They are found in xDSL and xPON modems, and contain PCM
(VoIP), Ethernet, USB, GPIO, I2C, SPI (Flash), UART, and PCIe.

The EcoNet MIPS SoCs are divided broadly into two families, the
EN751221 family based on the 34Kc, and the EN751627 family based on
the 1004Kc. Individual SoCs within a family are very similar, only
with different peripherals.

This patchset adds basic "boots to a console" support for the EN751221
family and adds SmartFiber XP8421-B, a low cost commercially available
board that is useful for testing and development.

Note that Airoha (AN7523, AN7581) is similar to EcoNet in terms of
peripherals, and for historical reasons Airoha chips are sometimes
referred to with the EN75xx prefix. However this is a different
platform because Airoha chips are ARM based.

This patchset is against mips-next.

v4 -> v5
* 2/7 clocksource/drivers: Add EcoNet Timer HPT driver:
  * Improve explanation of HPT timer in changelog
  * Move pr_info to pr_debug per recommendation
  * Remove pointless debug on spurious interrupt
  * Small code-style change

v3 -> v4
* Rebase to 3b3704261e851e25983860e4c352f1f73786f4ab
* Omit already accepted patches (thanks guys!):
  - https://patchwork.kernel.org/project/linux-mips/patch/20250330170306.2584136-2-cjd at cjdns.fr/
  - https://patchwork.kernel.org/project/linux-mips/patch/20250330170306.2584136-3-cjd at cjdns.fr/
  - https://patchwork.kernel.org/project/linux-mips/patch/20250330170306.2584136-4-cjd at cjdns.fr/

v2 -> v3
* econet,en751221-timer.yaml -> Improve code style
* vendor-prefixes.yaml -> Correct alphabetic order
* en751221.dtsi
  - interrupt-controller code style
  - serial: Explain reason for clock-frequency = <1843200>
* v3->v3 diff provided for reference
  - https://gist.github.com/cjdelisle/21c9f0cd225f499bdff3c574c7f185f2
* CC: linux-mediatek at lists.infradead.org who may be interested.

v1 -> v2
* Codestyle
  - Apply codestyle from "The tip tree handbook" and recommendations
  - Remove "_rai" and "_m" symbol suffixes which are not standard
* irq-econet-en751221.c
  - Use cleanup.h _guard() and _free()
  - Separate irq_domain_ops from irq_chip, eliminating econet_intc struct
  - Remove irqsave in econet_wreg, irqs are already disabled in mask/unmask
  - Add explainatory comments
  - Refactor shadow logic for clarity, e.g. INTC_NO_SHADOW -> NOT_PERCPU
  - Improve error handling in case of invalid DTS
* econet,timer-hpt.yaml
  - Rename to econet,timer-en751221.yaml
  - Impose rule: "reg" must have 1 item on EN751221 and 2 on EN751627
* timer-econet-hpt.c
  - Rename to timer-econet-en751221.c to follow naming scheme from DT
* econet,en751221-intc.yaml
  - Fix validation error from required: interrupt-parent
  - shadow-interrupts -> switch to uint32-matrix for list of pairs
* MAINTAINERS -> Fixed accidental F: MAINTAINERS
* Replace "test image" with device SmartFiber-XP8421-B
* Restructure arch/mips/econet/Kconfig per arch/mips/ralink example
* v1->v2 diff is offered for reference:
  - https://gist.github.com/cjdelisle/bb3acab78b5f70dcdfe5dd6338293efe


Caleb James DeLisle (7):
  dt-bindings: timer: Add EcoNet EN751221 "HPT" CPU Timer
  clocksource/drivers: Add EcoNet Timer HPT driver
  dt-bindings: mips: Add EcoNet platform binding
  mips: Add EcoNet MIPS platform support
  dt-bindings: vendor-prefixes: Add SmartFiber
  mips: dts: Add EcoNet DTS with EN751221 and SmartFiber XP8421-B board
  MAINTAINERS: Add entry for newly added EcoNet platform.

 .../devicetree/bindings/mips/econet.yaml      |  26 +++
 .../bindings/timer/econet,en751221-timer.yaml |  80 +++++++
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 MAINTAINERS                                   |  12 +
 arch/mips/Kbuild.platforms                    |   1 +
 arch/mips/Kconfig                             |  25 ++
 arch/mips/boot/compressed/uart-16550.c        |   5 +
 arch/mips/boot/dts/Makefile                   |   1 +
 arch/mips/boot/dts/econet/Makefile            |   2 +
 arch/mips/boot/dts/econet/en751221.dtsi       |  67 ++++++
 .../econet/en751221_smartfiber_xp8421-b.dts   |  19 ++
 arch/mips/econet/Kconfig                      |  48 ++++
 arch/mips/econet/Makefile                     |   2 +
 arch/mips/econet/Platform                     |   5 +
 arch/mips/econet/init.c                       |  78 +++++++
 drivers/clocksource/Kconfig                   |   8 +
 drivers/clocksource/Makefile                  |   1 +
 drivers/clocksource/timer-econet-en751221.c   | 216 ++++++++++++++++++
 18 files changed, 598 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mips/econet.yaml
 create mode 100644 Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
 create mode 100644 arch/mips/boot/dts/econet/Makefile
 create mode 100644 arch/mips/boot/dts/econet/en751221.dtsi
 create mode 100644 arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts
 create mode 100644 arch/mips/econet/Kconfig
 create mode 100644 arch/mips/econet/Makefile
 create mode 100644 arch/mips/econet/Platform
 create mode 100644 arch/mips/econet/init.c
 create mode 100644 drivers/clocksource/timer-econet-en751221.c

-- 
2.39.5



From cjd at cjdns.fr  Wed May  7 06:44:54 2025
From: cjd at cjdns.fr (Caleb James DeLisle)
Date: Wed,  7 May 2025 13:44:54 +0000
Subject: [PATCH v5 1/7] dt-bindings: timer: Add EcoNet EN751221 "HPT" CPU Timer
In-Reply-To: <20250507134500.390547-1-cjd@cjdns.fr>
References: <20250507134500.390547-1-cjd@cjdns.fr>
Message-ID: <20250507134500.390547-2-cjd@cjdns.fr>

Add device tree bindings for the so-called high-precision timer (HPT)
in the EcoNet EN751221 SoC.

Signed-off-by: Caleb James DeLisle <cjd at cjdns.fr>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 .../bindings/timer/econet,en751221-timer.yaml | 80 +++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml

diff --git a/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
new file mode 100644
index 000000000000..c1e7c2b6afde
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/econet,en751221-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: EcoNet EN751221 High Precision Timer (HPT)
+
+maintainers:
+  - Caleb James DeLisle <cjd at cjdns.fr>
+
+description:
+  The EcoNet High Precision Timer (HPT) is a timer peripheral found in various
+  EcoNet SoCs, including the EN751221 and EN751627 families. It provides per-VPE
+  count/compare registers and a per-CPU control register, with a single interrupt
+  line using a percpu-devid interrupt mechanism.
+
+properties:
+  compatible:
+    oneOf:
+      - const: econet,en751221-timer
+      - items:
+          - const: econet,en751627-timer
+          - const: econet,en751221-timer
+
+  reg:
+    minItems: 1
+    maxItems: 2
+
+  interrupts:
+    maxItems: 1
+    description: A percpu-devid timer interrupt shared across CPUs.
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: econet,en751627-timer
+    then:
+      properties:
+        reg:
+          items:
+            - description: VPE timers 0 and 1
+            - description: VPE timers 2 and 3
+    else:
+      properties:
+        reg:
+          items:
+            - description: VPE timers 0 and 1
+
+additionalProperties: false
+
+examples:
+  - |
+    timer at 1fbf0400 {
+        compatible = "econet,en751627-timer", "econet,en751221-timer";
+        reg = <0x1fbf0400 0x100>, <0x1fbe0000 0x100>;
+        interrupt-parent = <&intc>;
+        interrupts = <30>;
+        clocks = <&hpt_clock>;
+    };
+  - |
+    timer at 1fbf0400 {
+        compatible = "econet,en751221-timer";
+        reg = <0x1fbe0400 0x100>;
+        interrupt-parent = <&intc>;
+        interrupts = <30>;
+        clocks = <&hpt_clock>;
+    };
+...
-- 
2.39.5



From cjd at cjdns.fr  Wed May  7 06:44:56 2025
From: cjd at cjdns.fr (Caleb James DeLisle)
Date: Wed,  7 May 2025 13:44:56 +0000
Subject: [PATCH v5 3/7] dt-bindings: mips: Add EcoNet platform binding
In-Reply-To: <20250507134500.390547-1-cjd@cjdns.fr>
References: <20250507134500.390547-1-cjd@cjdns.fr>
Message-ID: <20250507134500.390547-4-cjd@cjdns.fr>

Document the top-level device tree binding for EcoNet MIPS-based SoCs.

Signed-off-by: Caleb James DeLisle <cjd at cjdns.fr>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 .../devicetree/bindings/mips/econet.yaml      | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mips/econet.yaml

diff --git a/Documentation/devicetree/bindings/mips/econet.yaml b/Documentation/devicetree/bindings/mips/econet.yaml
new file mode 100644
index 000000000000..d8181b58c781
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/econet.yaml
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/econet.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: EcoNet MIPS SoCs
+
+maintainers:
+  - Caleb James DeLisle <cjd at cjdns.fr>
+
+properties:
+  $nodename:
+    const: '/'
+
+  compatible:
+    oneOf:
+      - description: Boards with EcoNet EN751221 family SoC
+        items:
+          - enum:
+              - smartfiber,xp8421-b
+          - const: econet,en751221
+
+additionalProperties: true
+
+...
-- 
2.39.5



From cjd at cjdns.fr  Wed May  7 06:44:55 2025
From: cjd at cjdns.fr (Caleb James DeLisle)
Date: Wed,  7 May 2025 13:44:55 +0000
Subject: [PATCH v5 2/7] clocksource/drivers: Add EcoNet Timer HPT driver
In-Reply-To: <20250507134500.390547-1-cjd@cjdns.fr>
References: <20250507134500.390547-1-cjd@cjdns.fr>
Message-ID: <20250507134500.390547-3-cjd@cjdns.fr>

Introduce a clocksource driver for the so-called high-precision timer (HPT)
in the EcoNet EN751221 and EN751627 MIPS SoCs.

It's a 32 bit upward-counting one-shot timer which relies on the crystal so it
is unaffected by CPU power mode. On MIPS 34K devices (single core) there is
one timer, and on 1004K devices (dual core) there are two.

Each timer has two sets of count/compare registers so that there is one for
each of the VPEs on the core. Because each core has 2 VPEs, register selection
takes the CPU number / 2 for the timer corrisponding to the core, then CPU
number % 2 for the register corrisponding to the VPE.

These timers use a percpu-devid IRQ to route interrupts to the VPE which set
the event.

Signed-off-by: Caleb James DeLisle <cjd at cjdns.fr>
---
Re: https://patchwork.kernel.org/project/linux-mips/patch/20250430133433.22222-3-cjd at cjdns.fr/#26372668
I tested CPUHP_AP_ONLINE_DYN on my patched SMP kernel and confirmed it to
be working.
---
 drivers/clocksource/Kconfig                 |   8 +
 drivers/clocksource/Makefile                |   1 +
 drivers/clocksource/timer-econet-en751221.c | 216 ++++++++++++++++++++
 3 files changed, 225 insertions(+)
 create mode 100644 drivers/clocksource/timer-econet-en751221.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 487c85259967..976afb0b2312 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -73,6 +73,14 @@ config DW_APB_TIMER_OF
 	select DW_APB_TIMER
 	select TIMER_OF
 
+config ECONET_EN751221_TIMER
+	bool "EcoNet EN751221 High Precision Timer" if COMPILE_TEST
+	depends on HAS_IOMEM
+	select CLKSRC_MMIO
+	select TIMER_OF
+	help
+	  Support for CPU timer found on EcoNet MIPS based SoCs.
+
 config FTTMR010_TIMER
 	bool "Faraday Technology timer driver" if COMPILE_TEST
 	depends on HAS_IOMEM
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 43ef16a4efa6..d2998601eda5 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_CLKBLD_I8253)	+= i8253.o
 obj-$(CONFIG_CLKSRC_MMIO)	+= mmio.o
 obj-$(CONFIG_DAVINCI_TIMER)	+= timer-davinci.o
 obj-$(CONFIG_DIGICOLOR_TIMER)	+= timer-digicolor.o
+obj-$(CONFIG_ECONET_EN751221_TIMER)	+= timer-econet-en751221.o
 obj-$(CONFIG_OMAP_DM_TIMER)	+= timer-ti-dm.o
 obj-$(CONFIG_OMAP_DM_SYSTIMER)	+= timer-ti-dm-systimer.o
 obj-$(CONFIG_DW_APB_TIMER)	+= dw_apb_timer.o
diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksource/timer-econet-en751221.c
new file mode 100644
index 000000000000..3b449fdaafee
--- /dev/null
+++ b/drivers/clocksource/timer-econet-en751221.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Timer present on EcoNet EN75xx MIPS based SoCs.
+ *
+ * Copyright (C) 2025 by Caleb James DeLisle <cjd at cjdns.fr>
+ */
+
+#include <linux/io.h>
+#include <linux/cpumask.h>
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/sched_clock.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/cpuhotplug.h>
+#include <linux/clk.h>
+
+#define ECONET_BITS			32
+#define ECONET_MIN_DELTA		0x00001000
+#define ECONET_MAX_DELTA		GENMASK(ECONET_BITS - 2, 0)
+/* 34Kc hardware has 1 block and 1004Kc has 2. */
+#define ECONET_NUM_BLOCKS		DIV_ROUND_UP(NR_CPUS, 2)
+
+static struct {
+	void __iomem	*membase[ECONET_NUM_BLOCKS];
+	u32		freq_hz;
+} econet_timer __ro_after_init;
+
+static DEFINE_PER_CPU(struct clock_event_device, econet_timer_pcpu);
+
+/* Each memory block has 2 timers, the order of registers is:
+ * CTL, CMR0, CNT0, CMR1, CNT1
+ */
+static inline void __iomem *reg_ctl(u32 timer_n)
+{
+	return econet_timer.membase[timer_n >> 1];
+}
+
+static inline void __iomem *reg_compare(u32 timer_n)
+{
+	return econet_timer.membase[timer_n >> 1] + (timer_n & 1) * 0x08 + 0x04;
+}
+
+static inline void __iomem *reg_count(u32 timer_n)
+{
+	return econet_timer.membase[timer_n >> 1] + (timer_n & 1) * 0x08 + 0x08;
+}
+
+static inline u32 ctl_bit_enabled(u32 timer_n)
+{
+	return 1U << (timer_n & 1);
+}
+
+static inline u32 ctl_bit_pending(u32 timer_n)
+{
+	return 1U << ((timer_n & 1) + 16);
+}
+
+static bool cevt_is_pending(int cpu_id)
+{
+	return ioread32(reg_ctl(cpu_id)) & ctl_bit_pending(cpu_id);
+}
+
+static irqreturn_t cevt_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *dev = this_cpu_ptr(&econet_timer_pcpu);
+	int cpu = cpumask_first(dev->cpumask);
+
+	/* Each VPE has its own events,
+	 * so this will only happen on spurious interrupt.
+	 */
+	if (!cevt_is_pending(cpu))
+		return IRQ_NONE;
+
+	iowrite32(ioread32(reg_count(cpu)), reg_compare(cpu));
+	dev->event_handler(dev);
+	return IRQ_HANDLED;
+}
+
+static int cevt_set_next_event(ulong delta, struct clock_event_device *dev)
+{
+	u32 next;
+	int cpu;
+
+	cpu = cpumask_first(dev->cpumask);
+	next = ioread32(reg_count(cpu)) + delta;
+	iowrite32(next, reg_compare(cpu));
+
+	if ((s32)(next - ioread32(reg_count(cpu))) < ECONET_MIN_DELTA / 2)
+		return -ETIME;
+
+	return 0;
+}
+
+static int cevt_init_cpu(uint cpu)
+{
+	struct clock_event_device *cd = &per_cpu(econet_timer_pcpu, cpu);
+	u32 reg;
+
+	pr_debug("%s: Setting up clockevent for CPU %d\n", cd->name, cpu);
+
+	reg = ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu);
+	iowrite32(reg, reg_ctl(cpu));
+
+	enable_percpu_irq(cd->irq, IRQ_TYPE_NONE);
+
+	/* Do this last because it synchronously configures the timer */
+	clockevents_config_and_register(cd, econet_timer.freq_hz,
+					ECONET_MIN_DELTA, ECONET_MAX_DELTA);
+
+	return 0;
+}
+
+static u64 notrace sched_clock_read(void)
+{
+	/* Always read from clock zero no matter the CPU */
+	return (u64)ioread32(reg_count(0));
+}
+
+/* Init */
+
+static void __init cevt_dev_init(uint cpu)
+{
+	iowrite32(0, reg_count(cpu));
+	iowrite32(U32_MAX, reg_compare(cpu));
+}
+
+static int __init cevt_init(struct device_node *np)
+{
+	int i, irq, ret;
+
+	irq = irq_of_parse_and_map(np, 0);
+	if (irq <= 0) {
+		pr_err("%pOFn: irq_of_parse_and_map failed", np);
+		return -EINVAL;
+	}
+
+	ret = request_percpu_irq(irq, cevt_interrupt, np->name, &econet_timer_pcpu);
+
+	if (ret < 0) {
+		pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, irq, ret);
+		goto err_unmap_irq;
+	}
+
+	for_each_possible_cpu(i) {
+		struct clock_event_device *cd = &per_cpu(econet_timer_pcpu, i);
+
+		cd->rating		= 310,
+		cd->features		= CLOCK_EVT_FEAT_ONESHOT |
+					  CLOCK_EVT_FEAT_C3STOP |
+					  CLOCK_EVT_FEAT_PERCPU;
+		cd->set_next_event	= cevt_set_next_event;
+		cd->irq			= irq;
+		cd->cpumask		= cpumask_of(i);
+		cd->name		= np->name;
+
+		cevt_dev_init(i);
+	}
+
+	cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
+			  "clockevents/econet/timer:starting",
+			  cevt_init_cpu, NULL);
+	return 0;
+
+err_unmap_irq:
+	irq_dispose_mapping(irq);
+	return ret;
+}
+
+static int __init timer_init(struct device_node *np)
+{
+	int num_blocks = DIV_ROUND_UP(num_possible_cpus(), 2);
+	struct clk *clk;
+	int ret;
+
+	clk = of_clk_get(np, 0);
+	if (IS_ERR(clk)) {
+		pr_err("%pOFn: Failed to get CPU clock from DT %ld\n", np, PTR_ERR(clk));
+		return PTR_ERR(clk);
+	}
+
+	econet_timer.freq_hz = clk_get_rate(clk);
+
+	for (int i = 0; i < num_blocks; i++) {
+		econet_timer.membase[i] = of_iomap(np, i);
+		if (!econet_timer.membase[i]) {
+			pr_err("%pOFn: failed to map register [%d]\n", np, i);
+			return -ENXIO;
+		}
+	}
+
+	/* For clocksource purposes always read clock zero, whatever the CPU */
+	ret = clocksource_mmio_init(reg_count(0), np->name,
+				    econet_timer.freq_hz, 301, ECONET_BITS,
+				    clocksource_mmio_readl_up);
+	if (ret) {
+		pr_err("%pOFn: clocksource_mmio_init failed: %d", np, ret);
+		return ret;
+	}
+
+	ret = cevt_init(np);
+	if (ret < 0)
+		return ret;
+
+	sched_clock_register(sched_clock_read, ECONET_BITS,
+			     econet_timer.freq_hz);
+
+	pr_info("%pOFn: using %u.%03u MHz high precision timer\n", np,
+		econet_timer.freq_hz / 1000000,
+		(econet_timer.freq_hz / 1000) % 1000);
+
+	return 0;
+}
+
+TIMER_OF_DECLARE(econet_timer_hpt, "econet,en751221-timer", timer_init);
-- 
2.39.5



From cjd at cjdns.fr  Wed May  7 06:44:57 2025
From: cjd at cjdns.fr (Caleb James DeLisle)
Date: Wed,  7 May 2025 13:44:57 +0000
Subject: [PATCH v5 4/7] mips: Add EcoNet MIPS platform support
In-Reply-To: <20250507134500.390547-1-cjd@cjdns.fr>
References: <20250507134500.390547-1-cjd@cjdns.fr>
Message-ID: <20250507134500.390547-5-cjd@cjdns.fr>

Add platform support for EcoNet MIPS SoCs.

Signed-off-by: Caleb James DeLisle <cjd at cjdns.fr>
---
 arch/mips/Kbuild.platforms             |  1 +
 arch/mips/Kconfig                      | 25 +++++++++
 arch/mips/boot/compressed/uart-16550.c |  5 ++
 arch/mips/econet/Kconfig               | 37 ++++++++++++
 arch/mips/econet/Makefile              |  2 +
 arch/mips/econet/Platform              |  5 ++
 arch/mips/econet/init.c                | 78 ++++++++++++++++++++++++++
 7 files changed, 153 insertions(+)
 create mode 100644 arch/mips/econet/Kconfig
 create mode 100644 arch/mips/econet/Makefile
 create mode 100644 arch/mips/econet/Platform
 create mode 100644 arch/mips/econet/init.c

diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index bca37ddf974b..41a00fa860c1 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -11,6 +11,7 @@ platform-$(CONFIG_CAVIUM_OCTEON_SOC)	+= cavium-octeon/
 platform-$(CONFIG_EYEQ)			+= mobileye/
 platform-$(CONFIG_MIPS_COBALT)		+= cobalt/
 platform-$(CONFIG_MACH_DECSTATION)	+= dec/
+platform-$(CONFIG_ECONET)		+= econet/
 platform-$(CONFIG_MIPS_GENERIC)		+= generic/
 platform-$(CONFIG_MACH_JAZZ)		+= jazz/
 platform-$(CONFIG_LANTIQ)		+= lantiq/
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e0e6ce2592b4..c3dbdc808664 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -391,6 +391,30 @@ config MACH_DECSTATION
 
 	  otherwise choose R3000.
 
+config ECONET
+	bool "EcoNet MIPS family"
+	select BOOT_RAW
+	select CPU_BIG_ENDIAN
+	select DEBUG_ZBOOT
+	select EARLY_PRINTK_8250
+	select ECONET_EN751221_TIMER
+	select SERIAL_OF_PLATFORM
+	select SYS_SUPPORTS_BIG_ENDIAN
+	select SYS_HAS_CPU_MIPS32_R1
+	select SYS_HAS_CPU_MIPS32_R2
+	select SYS_HAS_EARLY_PRINTK
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_MIPS16
+	select SYS_SUPPORTS_ZBOOT_UART16550
+	select USE_GENERIC_EARLY_PRINTK_8250
+	select USE_OF
+	help
+	  EcoNet EN75xx MIPS devices are big endian MIPS machines used
+	  in XPON (fiber) and DSL applications. They have SPI, PCI, USB,
+	  GPIO, and Ethernet, with optional XPON, DSL, and VoIP DSP cores.
+	  Don't confuse these with the Airoha ARM devices sometimes referred
+	  to as "EcoNet", this family is for MIPS based devices only.
+
 config MACH_JAZZ
 	bool "Jazz family of machines"
 	select ARC_MEMORY
@@ -1021,6 +1045,7 @@ source "arch/mips/ath79/Kconfig"
 source "arch/mips/bcm47xx/Kconfig"
 source "arch/mips/bcm63xx/Kconfig"
 source "arch/mips/bmips/Kconfig"
+source "arch/mips/econet/Kconfig"
 source "arch/mips/generic/Kconfig"
 source "arch/mips/ingenic/Kconfig"
 source "arch/mips/jazz/Kconfig"
diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c
index db618e72a0c4..529e77a6487c 100644
--- a/arch/mips/boot/compressed/uart-16550.c
+++ b/arch/mips/boot/compressed/uart-16550.c
@@ -20,6 +20,11 @@
 #define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset))
 #endif
 
+#ifdef CONFIG_ECONET
+#define EN75_UART_BASE	0x1fbf0003
+#define PORT(offset)	(CKSEG1ADDR(EN75_UART_BASE) + (4 * (offset)))
+#endif
+
 #ifndef IOTYPE
 #define IOTYPE char
 #endif
diff --git a/arch/mips/econet/Kconfig b/arch/mips/econet/Kconfig
new file mode 100644
index 000000000000..d03f90f3daa4
--- /dev/null
+++ b/arch/mips/econet/Kconfig
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0
+if ECONET
+
+choice
+	prompt "EcoNet SoC selection"
+	default SOC_ECONET_EN751221
+	help
+	  Select EcoNet MIPS SoC type. Individual SoCs within a family are
+	  very similar, so is it enough to select the right family, and
+	  then customize to the specific SoC using the device tree only.
+
+	config SOC_ECONET_EN751221
+		bool "EN751221 family"
+		select COMMON_CLK
+		select ECONET_EN751221_INTC
+		select IRQ_MIPS_CPU
+		select SMP
+		select SMP_UP
+		select SYS_SUPPORTS_SMP
+		help
+		  The EN751221 family includes EN7512, RN7513, EN7521, EN7526.
+		  They are based on single core MIPS 34Kc processors. To boot
+		  this kernel, you will need a device tree such as
+		  MIPS_RAW_APPENDED_DTB=y, and a root filesystem.
+endchoice
+
+choice
+	prompt "Devicetree selection"
+	default DTB_ECONET_NONE
+	help
+	  Select the devicetree.
+
+	config DTB_ECONET_NONE
+		bool "None"
+endchoice
+
+endif
diff --git a/arch/mips/econet/Makefile b/arch/mips/econet/Makefile
new file mode 100644
index 000000000000..7e4529e7d3d7
--- /dev/null
+++ b/arch/mips/econet/Makefile
@@ -0,0 +1,2 @@
+
+obj-y := init.o
diff --git a/arch/mips/econet/Platform b/arch/mips/econet/Platform
new file mode 100644
index 000000000000..ea5616447bcd
--- /dev/null
+++ b/arch/mips/econet/Platform
@@ -0,0 +1,5 @@
+# To address a 7.2MB kernel size limit in the EcoNet SDK bootloader,
+# we put the load address well above where the bootloader loads and then use
+# zboot. So please set CONFIG_ZBOOT_LOAD_ADDRESS to the address where your
+# bootloader actually places the kernel.
+load-$(CONFIG_ECONET)	+= 0xffffffff81000000
diff --git a/arch/mips/econet/init.c b/arch/mips/econet/init.c
new file mode 100644
index 000000000000..6f43ffb209cb
--- /dev/null
+++ b/arch/mips/econet/init.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * EcoNet setup code
+ *
+ * Copyright (C) 2025 Caleb James DeLisle <cjd at cjdns.fr>
+ */
+
+#include <linux/init.h>
+#include <linux/of_clk.h>
+#include <linux/irqchip.h>
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/bootinfo.h>
+#include <asm/time.h>
+#include <asm/prom.h>
+#include <asm/smp-ops.h>
+#include <asm/reboot.h>
+
+#define CR_AHB_RSTCR		((void __iomem *)CKSEG1ADDR(0x1fb00040))
+#define RESET			BIT(31)
+
+#define UART_BASE		CKSEG1ADDR(0x1fbf0003)
+#define UART_REG_SHIFT		2
+
+static void hw_reset(char *command)
+{
+	iowrite32(RESET, CR_AHB_RSTCR);
+}
+
+/* 1. Bring up early printk. */
+void __init prom_init(void)
+{
+	setup_8250_early_printk_port(UART_BASE, UART_REG_SHIFT, 0);
+	_machine_restart = hw_reset;
+}
+
+/* 2. Parse the DT and find memory */
+void __init plat_mem_setup(void)
+{
+	void *dtb;
+
+	set_io_port_base(KSEG1);
+
+	dtb = get_fdt();
+	if (!dtb)
+		panic("no dtb found");
+
+	__dt_setup_arch(dtb);
+
+	early_init_dt_scan_memory();
+}
+
+/* 3. Overload __weak device_tree_init(), add SMP_UP ops */
+void __init device_tree_init(void)
+{
+	unflatten_and_copy_device_tree();
+
+	register_up_smp_ops();
+}
+
+const char *get_system_type(void)
+{
+	return "EcoNet-EN75xx";
+}
+
+/* 4. Initialize the IRQ subsystem */
+void __init arch_init_irq(void)
+{
+	irqchip_init();
+}
+
+/* 5. Timers */
+void __init plat_time_init(void)
+{
+	of_clk_init(NULL);
+	timer_probe();
+}
-- 
2.39.5



From cjd at cjdns.fr  Wed May  7 06:44:58 2025
From: cjd at cjdns.fr (Caleb James DeLisle)
Date: Wed,  7 May 2025 13:44:58 +0000
Subject: [PATCH v5 5/7] dt-bindings: vendor-prefixes: Add SmartFiber
In-Reply-To: <20250507134500.390547-1-cjd@cjdns.fr>
References: <20250507134500.390547-1-cjd@cjdns.fr>
Message-ID: <20250507134500.390547-6-cjd@cjdns.fr>

Add "smartfiber" vendor prefix for manufactorer of EcoNet based boards.

Signed-off-by: Caleb James DeLisle <cjd at cjdns.fr>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
Reviewed-by: Philippe Mathieu-Daud? <philmd at linaro.org>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 86f6a19b28ae..421fd5c2e41c 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1396,6 +1396,8 @@ patternProperties:
     description: SKOV A/S
   "^skyworks,.*":
     description: Skyworks Solutions, Inc.
+  "^smartfiber,.*":
+    description: ShenZhen Smartfiber Technology Co, Ltd.
   "^smartlabs,.*":
     description: SmartLabs LLC
   "^smartrg,.*":
-- 
2.39.5



From cjd at cjdns.fr  Wed May  7 06:44:59 2025
From: cjd at cjdns.fr (Caleb James DeLisle)
Date: Wed,  7 May 2025 13:44:59 +0000
Subject: [PATCH v5 6/7] mips: dts: Add EcoNet DTS with EN751221 and SmartFiber XP8421-B board
In-Reply-To: <20250507134500.390547-1-cjd@cjdns.fr>
References: <20250507134500.390547-1-cjd@cjdns.fr>
Message-ID: <20250507134500.390547-7-cjd@cjdns.fr>

Add DTS files in support of EcoNet platform, including SmartFiber XP8421-B,
a low cost commercially available board based on EN751221.

Signed-off-by: Caleb James DeLisle <cjd at cjdns.fr>
---
 arch/mips/boot/dts/Makefile                   |  1 +
 arch/mips/boot/dts/econet/Makefile            |  2 +
 arch/mips/boot/dts/econet/en751221.dtsi       | 67 +++++++++++++++++++
 .../econet/en751221_smartfiber_xp8421-b.dts   | 19 ++++++
 arch/mips/econet/Kconfig                      | 11 +++
 5 files changed, 100 insertions(+)
 create mode 100644 arch/mips/boot/dts/econet/Makefile
 create mode 100644 arch/mips/boot/dts/econet/en751221.dtsi
 create mode 100644 arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts

diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index ff468439a8c4..7375c6ced82b 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 subdir-$(CONFIG_BMIPS_GENERIC)		+= brcm
 subdir-$(CONFIG_CAVIUM_OCTEON_SOC)	+= cavium-octeon
+subdir-$(CONFIG_ECONET)			+= econet
 subdir-$(CONFIG_EYEQ)			+= mobileye
 subdir-$(CONFIG_FIT_IMAGE_FDT_MARDUK)   += img
 subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON)	+= img
diff --git a/arch/mips/boot/dts/econet/Makefile b/arch/mips/boot/dts/econet/Makefile
new file mode 100644
index 000000000000..b467d5624e39
--- /dev/null
+++ b/arch/mips/boot/dts/econet/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_DTB_ECONET_SMARTFIBER_XP8421_B)	+= en751221_smartfiber_xp8421-b.dtb
diff --git a/arch/mips/boot/dts/econet/en751221.dtsi b/arch/mips/boot/dts/econet/en751221.dtsi
new file mode 100644
index 000000000000..66197e73d4f0
--- /dev/null
+++ b/arch/mips/boot/dts/econet/en751221.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/dts-v1/;
+
+/ {
+	compatible = "econet,en751221";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	hpt_clock: clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;  /* 200 MHz */
+	};
+
+	cpus: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "mips,mips24KEc";
+			reg = <0>;
+		};
+	};
+
+	cpuintc: interrupt-controller {
+		compatible = "mti,cpu-interrupt-controller";
+		interrupt-controller;
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+	};
+
+	intc: interrupt-controller at 1fb40000 {
+		compatible = "econet,en751221-intc";
+		reg = <0x1fb40000 0x100>;
+		interrupt-parent = <&cpuintc>;
+		interrupts = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
+	};
+
+	uart: serial at 1fbf0000 {
+		compatible = "ns16550";
+		reg = <0x1fbf0000 0x30>;
+		reg-io-width = <4>;
+		reg-shift = <2>;
+		interrupt-parent = <&intc>;
+		interrupts = <0>;
+		/*
+		 * Conversion of baud rate to clock frequency requires a
+		 * computation that is not in the ns16550 driver, so this
+		 * uart is fixed at 115200 baud.
+		 */
+		clock-frequency = <1843200>;
+	};
+
+	timer_hpt: timer at 1fbf0400 {
+		compatible = "econet,en751221-timer";
+		reg = <0x1fbf0400 0x100>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <30>;
+		clocks = <&hpt_clock>;
+	};
+};
diff --git a/arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts b/arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts
new file mode 100644
index 000000000000..8223c5bce67f
--- /dev/null
+++ b/arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/dts-v1/;
+
+#include "en751221.dtsi"
+
+/ {
+	model = "SmartFiber XP8421-B";
+	compatible = "smartfiber,xp8421-b", "econet,en751221";
+
+	memory at 0 {
+		device_type = "memory";
+		reg = <0x00000000 0x1c000000>;
+	};
+
+	chosen {
+		stdout-path = "/serial at 1fbf0000:115200";
+		linux,usable-memory-range = <0x00020000 0x1bfe0000>;
+	};
+};
diff --git a/arch/mips/econet/Kconfig b/arch/mips/econet/Kconfig
index d03f90f3daa4..fd69884cc9a8 100644
--- a/arch/mips/econet/Kconfig
+++ b/arch/mips/econet/Kconfig
@@ -32,6 +32,17 @@ choice
 
 	config DTB_ECONET_NONE
 		bool "None"
+
+	config DTB_ECONET_SMARTFIBER_XP8421_B
+		bool "EN751221 SmartFiber XP8421-B"
+		depends on SOC_ECONET_EN751221
+		select BUILTIN_DTB
+		help
+		  The SmartFiber XP8421-B is a device based on the EN751221 SoC.
+		  It has 512MB of memory and 256MB of NAND flash. This kernel
+		  needs only an appended initramfs to boot. It can be loaded
+		  through XMODEM and booted from memory in the bootloader, or
+		  it can be packed in tclinux.trx format and written to flash.
 endchoice
 
 endif
-- 
2.39.5



From cjd at cjdns.fr  Wed May  7 06:45:00 2025
From: cjd at cjdns.fr (Caleb James DeLisle)
Date: Wed,  7 May 2025 13:45:00 +0000
Subject: [PATCH v5 7/7] MAINTAINERS: Add entry for newly added EcoNet platform.
In-Reply-To: <20250507134500.390547-1-cjd@cjdns.fr>
References: <20250507134500.390547-1-cjd@cjdns.fr>
Message-ID: <20250507134500.390547-8-cjd@cjdns.fr>

Add a MAINTAINERS entry as part of integration of the EcoNet MIPS platform.

Signed-off-by: Caleb James DeLisle <cjd at cjdns.fr>
Reviewed-by: Philippe Mathieu-Daud? <philmd at linaro.org>
---
 MAINTAINERS | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 96b827049501..5b2536150996 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8352,6 +8352,18 @@ W:	https://linuxtv.org
 Q:	http://patchwork.linuxtv.org/project/linux-media/list/
 F:	drivers/media/dvb-frontends/ec100*
 
+ECONET MIPS PLATFORM
+M:	Caleb James DeLisle <cjd at cjdns.fr>
+L:	linux-mips at vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml
+F:	Documentation/devicetree/bindings/mips/econet.yaml
+F:	Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
+F:	arch/mips/boot/dts/econet/
+F:	arch/mips/econet/
+F:	drivers/clocksource/timer-econet-en751221.c
+F:	drivers/irqchip/irq-econet-en751221.c
+
 ECRYPT FILE SYSTEM
 M:	Tyler Hicks <code at tyhicks.com>
 L:	ecryptfs at vger.kernel.org
-- 
2.39.5



From steven.price at arm.com  Wed May  7 07:06:58 2025
From: steven.price at arm.com (Steven Price)
Date: Wed, 7 May 2025 15:06:58 +0100
Subject: [PATCH v5 2/3] drm/panfrost: Add support for Mali on the MT8370
 SoC
In-Reply-To: <20250502-mt8370-enable-gpu-v5-2-98e247b30151@collabora.com>
References: <20250502-mt8370-enable-gpu-v5-0-98e247b30151@collabora.com>
 <20250502-mt8370-enable-gpu-v5-2-98e247b30151@collabora.com>
Message-ID: <2b85071a-e3e7-4cfc-a471-e81e463b7c37@arm.com>

On 02/05/2025 13:17, Louis-Alexis Eyraud wrote:
> Add a compatible for the MediaTek MT8370 SoC, with an integrated ARM
> Mali G57 MC2 GPU (Valhall-JM, dual core), with new platform data for
> its support in the panfrost driver.
> It uses the same data as MT8186 for the power management features to
> describe power supplies, pm_domains and enablement (one regulator, two
> power domains) but also sets the FORCE_AARCH64_PGTABLE flag in the GPU
> configuration quirks bitfield to enable AARCH64 4K page table format
> mode.
> As MT8186 and MT8370 SoC have different GPU architecture (Mali G52 2EE
> MC2 for MT8186), making them not compatible, and this mode is only
> enabled for Mediatek SoC that are Mali G57 based (compatible with
> mediatek,mali-mt8188 or mediatek,mali-8192), having specific platform
> data allows to set this flag for MT8370 without modifying MT8186
> configuration and behaviour.
> 
> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>

With one minor comment fixed below:

Reviewed-by: Steven Price <steven.price at arm.com>

> ---
>  drivers/gpu/drm/panfrost/panfrost_drv.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
> index f1ec3b02f15a0029d20c7d81046ded59854e885c..8e0a1ae6940c73b7b60233950ae3abdfa843cc8e 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_drv.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
> @@ -846,6 +846,16 @@ static const struct panfrost_compatible mediatek_mt8192_data = {
>  	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
>  };
>  
> +/* MT8370 uses the same power domains and power supplies as MT8186 */

This comment is not correct - you've got the power domains of MT8186, 
but the supplies of MT8183. The comment doesn't actually add much so you 
could just drop it.

If you're feeling adventurous then one option here is to actually clean 
up the mediatek entries a little. Instead of referring to particular 
part numbers we could have:

static const char * const mediatek_2_pm_domains[] = { "core0", "core1" };
static const char * const mediatek_3_pm_domains[] = { "core0", "core1", "core2" };
static const char * const mediatek_5_pm_domains[] = { "core0", "core1", "core2",
                                                      "core3", "core4" };

Or even just have the mediatek_5_domains[] array (dropping the '5' in
the name) and not use ARRAY_SIZE().

Equally the supplies arrays could be renamed. We have the one with 
"sram" for legacy and everything else uses {"mali", NULL} but we have 
two definitions for it (mt8183_b and mt8192).

Thanks,
Steve

> +static const struct panfrost_compatible mediatek_mt8370_data = {
> +	.num_supplies = ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1,
> +	.supply_names = mediatek_mt8183_b_supplies,
> +	.num_pm_domains = ARRAY_SIZE(mediatek_mt8186_pm_domains),
> +	.pm_domain_names = mediatek_mt8186_pm_domains,
> +	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
> +	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
> +};
> +
>  static const struct of_device_id dt_match[] = {
>  	/* Set first to probe before the generic compatibles */
>  	{ .compatible = "amlogic,meson-gxm-mali",
> @@ -868,6 +878,7 @@ static const struct of_device_id dt_match[] = {
>  	{ .compatible = "mediatek,mt8186-mali", .data = &mediatek_mt8186_data },
>  	{ .compatible = "mediatek,mt8188-mali", .data = &mediatek_mt8188_data },
>  	{ .compatible = "mediatek,mt8192-mali", .data = &mediatek_mt8192_data },
> +	{ .compatible = "mediatek,mt8370-mali", .data = &mediatek_mt8370_data },
>  	{ .compatible = "allwinner,sun50i-h616-mali", .data = &allwinner_h616_data },
>  	{}
>  };
> 



From luca.ceresoli at bootlin.com  Wed May  7 07:13:11 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Wed, 7 May 2025 16:13:11 +0200
Subject: [PATCH v2 30/34] drm/bridge: imx8qxp-pixel-combiner: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <430d497d-45a1-436d-91fd-635854f80c9f@nxp.com>
References: <20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b@bootlin.com>
	<20250424-drm-bridge-convert-to-alloc-api-v2-30-8f91a404d86b@bootlin.com>
	<553d62ed-976a-4e17-9678-cdc3d40ce4a7@nxp.com>
	<20250430112944.1b39caab@booty>
	<f71d18d2-4271-4bb9-b54f-0e5a585778f3@nxp.com>
	<20250506224720.5cbcf3e1@booty>
	<a1abf31a-7a4a-4f8d-bf48-6b826aa01197@nxp.com>
	<20250507091244.32865a71@booty>
	<430d497d-45a1-436d-91fd-635854f80c9f@nxp.com>
Message-ID: <20250507161311.6e434f2f@booty>

Hello Liu,

On Wed, 7 May 2025 18:16:28 +0800
Liu Ying <victor.liu at nxp.com> wrote:

[...]

> >>>> After looking into this patch and patch 31(though I've already provided my A-b)
> >>>> more closely, I think the imx8qxp_pc and imx8{qm,qxp}_ldb main structures
> >>>> should have the same life time with the embedded DRM bridges, because for
> >>>> example the clk_apb clock in struct imx8qxp_pc would be accessed by the
> >>>> imx8qxp_pc_bridge_mode_set DRM bridge callback.  But, IIUC, your patches extend
> >>>> the life time for the embedded channel/bridge structures only, but not for the
> >>>> main structures.  What do you think ?    
> >>>
> >>> I see you concern, but I'm sure the change I'm introducing is not
> >>> creating the problem you are concerned about.
> >>>
> >>> The key aspect is that my patch is merely changing the lifetime of the
> >>> _allocation_ of the drm_bridge, not its usage. On drm_bridge_remove()
> >>> the bridge is removed from its encoder chain and it is completely not
> >>> reachable, both before and after my patch. With my patch it is not
> >>> freed immediately, but it's just a piece of "wasted" memory that is
> >>> still allocated until elsewhere in the kernel there are pointers to it,
> >>> to avoid use-after-free.
> >>>
> >>> With this explanation, do you think my patch is correct (after fixing
> >>> the bug we already discussed of course)?    
> >>
> >> I tend to say your patch is not correct because we'll eventually make sure
> >> that removing a bridge module is safe when doing atomic commit,  
> > 
> > I think your sentence can be rephrased as "your patch is correct with
> > the current code base where bridges are not (yet) removable, but there
> > will be a problem when they start to actually be removable".
> > 
> > Is my understanding correct? If it is, I agree on that sentence.  
> 
> Nope, I meant your patch should align the life times of the main structures
> and the DRM bridges, for the sake of the kinda long term goal - remove bridge
> driver module safely when doing atomic commit.

Again, I don't think there is any bug introduced by this patch (once
the NULL ptr deref bug we already discussed is fixed). No bridge can be
removed as of now, with or without this patch.

You concern that this patch would make things more complex in the
future, when bridges will actually become removable and they could be
during atomic updates. But about this...

> > The work to have removable bridges is massive and non-trivial, so it
> > will need to be tackled in steps. The grand plan [0] is:
> > 
> >  1. add refcounting to DRM bridges (struct drm_bridge)
> >  2. handle gracefully atomic updates during bridge removal
> >  3. avoid DSI host drivers to have dangling pointers to DSI devices 
> >  4. finish the hotplug bridge work, removing the "always-disconnected"
> >     connector, moving code to the core and potentially removing the
> >     hotplug-bridge itself (this needs to be clarified as points 1-3 are
> >     developed)  
> 
> I'm busy with internal things these days and cannot look into the grand
> plan and steps closely, sorry about that.

...I'll wait until you have time to look into that more closely. There
is just no way to understand this whole topic without some dedicated
attention, which takes time unavoidably.

In the meanwhile I am going to send v3 soon with the known bug fixed,
so the best version is available to continue this discussion.

> > I am at step 1 right now. Removal during atomic updates is step 2,
> > ideas about how to implement that are already being discussed [1],
> > there's a practical plan proposed by Maxime with the goal of reaching
> > removable bridges without breaking things along the path.
> > 
> > [0] https://lore.kernel.org/lkml/20250206-hotplug-drm-bridge-v6-0-9d6f2c9c3058 at bootlin.com/
> > [1] https://lore.kernel.org/all/20250106-vigorous-talented-viper-fa49d9 at houat/
> >   
> >> which means
> >> the main structures should have the same life time with the DRM bridges.  
> > 
> > The word "lifetime" mean two things for bridges:
> > 
> >  * the time span during which memory is allocated for a struct
> >    drm_bridge (along with the embedding struct)  
> 
> Note that with your patch set the imx8*-ldb drivers and this bridge driver
> won't allocate the DRM bridge along with the embedding struct.

By "embedding struct" I mean the struct imx8qxp_pc_channel that embeds
the struct drm_bridge. Sorry, I realize my wording was ambiguous.

> This makes
> me worry, because maybe these drivers are the only "special" ones in this
> patch set and I don't want them to be "special" after your patch set is
> applied.

Luca

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


From nphamcs at gmail.com  Wed May  7 08:00:59 2025
From: nphamcs at gmail.com (Nhat Pham)
Date: Wed, 7 May 2025 08:00:59 -0700
Subject: [PATCH] mm: Add Kcompressd for accelerated memory compression
In-Reply-To: <CAGsJ_4yBn7j3WpCttPB0PVuRCYTYBcDbW2221AaPNLOHSmKADA@mail.gmail.com>
References: <20250430082651.3152444-1-qun-wei.lin@mediatek.com>
 <aBqzcIteOzC9mRjY@harry> <A3307E1B-B741-4C23-8053-72A1CA04D923@nvidia.com> <CAGsJ_4yBn7j3WpCttPB0PVuRCYTYBcDbW2221AaPNLOHSmKADA@mail.gmail.com>
Message-ID: <CAKEwX=NyZnNmiERFzwMUGQ8CJ7Pqm_XqHWMQoPjJKnBQefZkiw@mail.gmail.com>

On Tue, May 6, 2025 at 7:04?PM Barry Song <21cnbao at gmail.com> wrote:
>
> On Wed, May 7, 2025 at 1:50?PM Zi Yan <ziy at nvidia.com> wrote:
> >
> > On 6 May 2025, at 21:12, Harry Yoo wrote:
> >
> > > On Wed, Apr 30, 2025 at 04:26:41PM +0800, Qun-Wei Lin wrote:
> > >> This patch series introduces a new mechanism called kcompressd to
> > >> improve the efficiency of memory reclaiming in the operating system.
> > >>
> > >> Problem:
> > >>   In the current system, the kswapd thread is responsible for both scanning
> > >>   the LRU pages and handling memory compression tasks (such as those
> > >>   involving ZSWAP/ZRAM, if enabled). This combined responsibility can lead
> > >>   to significant performance bottlenecks, especially under high memory
> > >>   pressure. The kswapd thread becomes a single point of contention, causing
> > >>   delays in memory reclaiming and overall system performance degradation.
> > >>
> > >> Solution:
> > >>   Introduced kcompressd to handle asynchronous compression during memory
> > >>   reclaim, improving efficiency by offloading compression tasks from
> > >>   kswapd. This allows kswapd to focus on its primary task of page reclaim
> > >>   without being burdened by the additional overhead of compression.
> > >>
> > >> In our handheld devices, we found that applying this mechanism under high
> > >> memory pressure scenarios can increase the rate of pgsteal_anon per second
> > >> by over 260% compared to the situation with only kswapd. Additionally, we
> > >> observed a reduction of over 50% in page allocation stall occurrences,
> > >> further demonstrating the effectiveness of kcompressd in alleviating memory
> > >> pressure and improving system responsiveness.
> > >>
> > >> Co-developed-by: Barry Song <21cnbao at gmail.com>
> > >> Signed-off-by: Barry Song <21cnbao at gmail.com>
> > >> Signed-off-by: Qun-Wei Lin <qun-wei.lin at mediatek.com>
> > >> Reference: Re: [PATCH 0/2] Improve Zram by separating compression context from kswapd - Barry Song
> > >>           https://lore.kernel.org/lkml/20250313093005.13998-1-21cnbao at gmail.com/
> > >> ---
> > >
> > > +Cc Zi Yan, who might be interested in writing a framework (or improving
> > > the existing one, padata) for parallelizing jobs (e.g. migration/compression)
> >
> > Thanks.
> >
> > I am currently looking into padata [1] to perform multithreaded page migration

TIL about padata :)

> > copy job. But based on this patch, it seems that kcompressed is just an additional
> > kernel thread of executing zswap_store(). Is there any need for performing
> > compression with multiple threads?
>
> The current focus is on enabling kswapd to perform asynchronous compression,
> which can significantly reduce direct reclaim and allocstall events.
> Therefore, the work begins with supporting a single thread. Supporting
> multiple threads might be possible in the future, but it could be difficult
> to control?especially on busy phones?since it consumes more power and may
> interfere with other threads impacting user experience.

Right, yeah.

>
> >
> > BTW, I also notice that zswap IAA compress batching patchset[2] is using
> > hardware accelerator (Intel Analytics Accelerator) to speed up zswap.
> > I wonder if the handheld devices have similar hardware to get a similar benefit.
>
> Usually, the answer is no. We use zRAM and CPU, but this patch aims to provide
> a common capability that can be shared by both zRAM and zswap.
>

Also, not everyone and every setup has access to hardware compression
accelerators :) This provides benefits for all users.


From nphamcs at gmail.com  Wed May  7 08:11:36 2025
From: nphamcs at gmail.com (Nhat Pham)
Date: Wed, 7 May 2025 08:11:36 -0700
Subject: [PATCH] mm: Add Kcompressd for accelerated memory compression
In-Reply-To: <CAGsJ_4wLuJNe9uPE3-fBNLdiCPBpKt4a1ytuf7-+oiS5rBrg_w@mail.gmail.com>
References: <20250430082651.3152444-1-qun-wei.lin@mediatek.com>
 <20250430145106.8ce79a05d35cec72aa02baa6@linux-foundation.org> <CAGsJ_4wLuJNe9uPE3-fBNLdiCPBpKt4a1ytuf7-+oiS5rBrg_w@mail.gmail.com>
Message-ID: <CAKEwX=PW4YdCx77ZycvqkeW9JXL2PnxyjpseSy3ddtg8QtAKWQ@mail.gmail.com>

On Wed, Apr 30, 2025 at 3:50?PM Barry Song <21cnbao at gmail.com> wrote:
>
> On Thu, May 1, 2025 at 9:51?AM Andrew Morton <akpm at linux-foundation.org> wrote:
> >
> > On Wed, 30 Apr 2025 16:26:41 +0800 Qun-Wei Lin <qun-wei.lin at mediatek.com> wrote:
> >
> > > This patch series introduces a new mechanism called kcompressd to
> > > improve the efficiency of memory reclaiming in the operating system.
> > >
> > > Problem:
> > >   In the current system, the kswapd thread is responsible for both scanning
> > >   the LRU pages and handling memory compression tasks (such as those
> > >   involving ZSWAP/ZRAM, if enabled). This combined responsibility can lead
> > >   to significant performance bottlenecks, especially under high memory
> > >   pressure. The kswapd thread becomes a single point of contention, causing
> > >   delays in memory reclaiming and overall system performance degradation.
> > >
> > > Solution:
> > >   Introduced kcompressd to handle asynchronous compression during memory
> > >   reclaim, improving efficiency by offloading compression tasks from
> > >   kswapd. This allows kswapd to focus on its primary task of page reclaim
> > >   without being burdened by the additional overhead of compression.
> > >
> > > In our handheld devices, we found that applying this mechanism under high
> > > memory pressure scenarios can increase the rate of pgsteal_anon per second
> > > by over 260% compared to the situation with only kswapd. Additionally, we
> > > observed a reduction of over 50% in page allocation stall occurrences,
> > > further demonstrating the effectiveness of kcompressd in alleviating memory
> > > pressure and improving system responsiveness.
> >
> > It's a significant change and I'm thinking that broader performance
> > testing across a broader range of machines is needed before we can
> > confidently upstream such a change.
>
> We ran the same test on our phones and saw the same results as Qun-Wei.
> The async compression significantly reduces allocation stalls and improves
> reclamation speed. However, I agree that broader testing is needed, and
> we?ll also need the zswap team?s help with testing zswap cases.

The warning aside (which I got around by setting and unsetting
PF_MEMALLOC in kcompressd()), I run kernel building tests with zswap.
There is not much performance difference with and without kcompressd.
That probably means kernel building is a mediocre benchmark more than
anything. Ideally, I want to experiment with some real workloads, but
that is a bit more involved to set up, unfortunately :(

I can try again once you have sent v2 that incorporates our review, at
least to make sure everything is stable and there is no obvious
regression. Hopefully I can set up a proper experiment at some point
too...

>
> >
> > Also, it's presumably a small net loss on single-CPU machines (do these
> > exist any more?).  Is it hard to disable this feature on such machines?
>
> A net loss is possible, but kswapd can sometimes enter sleep contexts,
> allowing the parallel kcompressd thread to continue compression.
> This could actually be a win. But I agree that additional testing on
> single-CPU machines may be necessary.
>
> It could be disabled by the following if we discover any regression on
> single-CPU machines?
>
> if (num_online_cpus() == 1)
>      return false;
>
> >
> > >
> > > +static bool swap_sched_async_compress(struct folio *folio)
> > > +{
> > > +     struct swap_info_struct *sis = swp_swap_info(folio->swap);
> > > +     int nid = numa_node_id();
> > > +     pg_data_t *pgdat = NODE_DATA(nid);
> > > +
> > > +     if (unlikely(!pgdat->kcompressd))
> > > +             return false;
> > > +
> > > +     if (!current_is_kswapd())
> > > +             return false;
> > > +
> > > +     if (!folio_test_anon(folio))
> > > +             return false;
> >
> > Are you sure the above three tests are really needed?
>
> Currently, it runs as a per-node thread mainly to accelerate asynchronous
> reclamation, which effectively reduces direct reclamation. Since direct
> reclamation already follows the slow path, asynchronous compression offers
> limited additional benefit in that context. Moreover, it's difficult
> to determine
> the optimal number of threads for direct reclamation, whereas the  compression
> in the current direct reclamation allows it to utilize all CPUs.
>
> The first condition checks whether kcompressd is present. The second
> ensures that we're in kswapd asynchronous reclamation, not direct
> reclamation. The third condition might be optimized or dropped, at least for
> swap-backed shmem, and similar cases.
>
> Thanks
> Barry


From ziy at nvidia.com  Wed May  7 08:12:27 2025
From: ziy at nvidia.com (Zi Yan)
Date: Wed, 07 May 2025 11:12:27 -0400
Subject: [PATCH] mm: Add Kcompressd for accelerated memory compression
In-Reply-To: <CAKEwX=NyZnNmiERFzwMUGQ8CJ7Pqm_XqHWMQoPjJKnBQefZkiw@mail.gmail.com>
References: <20250430082651.3152444-1-qun-wei.lin@mediatek.com>
 <aBqzcIteOzC9mRjY@harry> <A3307E1B-B741-4C23-8053-72A1CA04D923@nvidia.com>
 <CAGsJ_4yBn7j3WpCttPB0PVuRCYTYBcDbW2221AaPNLOHSmKADA@mail.gmail.com>
 <CAKEwX=NyZnNmiERFzwMUGQ8CJ7Pqm_XqHWMQoPjJKnBQefZkiw@mail.gmail.com>
Message-ID: <5D8BCC32-4932-4030-AE42-C0009D92A7CA@nvidia.com>

On 7 May 2025, at 11:00, Nhat Pham wrote:

> On Tue, May 6, 2025 at 7:04?PM Barry Song <21cnbao at gmail.com> wrote:
>>
>> On Wed, May 7, 2025 at 1:50?PM Zi Yan <ziy at nvidia.com> wrote:
>>>
>>> On 6 May 2025, at 21:12, Harry Yoo wrote:
>>>
>>>> On Wed, Apr 30, 2025 at 04:26:41PM +0800, Qun-Wei Lin wrote:
>>>>> This patch series introduces a new mechanism called kcompressd to
>>>>> improve the efficiency of memory reclaiming in the operating system.
>>>>>
>>>>> Problem:
>>>>>   In the current system, the kswapd thread is responsible for both scanning
>>>>>   the LRU pages and handling memory compression tasks (such as those
>>>>>   involving ZSWAP/ZRAM, if enabled). This combined responsibility can lead
>>>>>   to significant performance bottlenecks, especially under high memory
>>>>>   pressure. The kswapd thread becomes a single point of contention, causing
>>>>>   delays in memory reclaiming and overall system performance degradation.
>>>>>
>>>>> Solution:
>>>>>   Introduced kcompressd to handle asynchronous compression during memory
>>>>>   reclaim, improving efficiency by offloading compression tasks from
>>>>>   kswapd. This allows kswapd to focus on its primary task of page reclaim
>>>>>   without being burdened by the additional overhead of compression.
>>>>>
>>>>> In our handheld devices, we found that applying this mechanism under high
>>>>> memory pressure scenarios can increase the rate of pgsteal_anon per second
>>>>> by over 260% compared to the situation with only kswapd. Additionally, we
>>>>> observed a reduction of over 50% in page allocation stall occurrences,
>>>>> further demonstrating the effectiveness of kcompressd in alleviating memory
>>>>> pressure and improving system responsiveness.
>>>>>
>>>>> Co-developed-by: Barry Song <21cnbao at gmail.com>
>>>>> Signed-off-by: Barry Song <21cnbao at gmail.com>
>>>>> Signed-off-by: Qun-Wei Lin <qun-wei.lin at mediatek.com>
>>>>> Reference: Re: [PATCH 0/2] Improve Zram by separating compression context from kswapd - Barry Song
>>>>>          https://lore.kernel.org/lkml/20250313093005.13998-1-21cnbao at gmail.com/
>>>>> ---
>>>>
>>>> +Cc Zi Yan, who might be interested in writing a framework (or improving
>>>> the existing one, padata) for parallelizing jobs (e.g. migration/compression)
>>>
>>> Thanks.
>>>
>>> I am currently looking into padata [1] to perform multithreaded page migration
>
> TIL about padata :)
>
>>> copy job. But based on this patch, it seems that kcompressed is just an additional
>>> kernel thread of executing zswap_store(). Is there any need for performing
>>> compression with multiple threads?
>>
>> The current focus is on enabling kswapd to perform asynchronous compression,
>> which can significantly reduce direct reclaim and allocstall events.
>> Therefore, the work begins with supporting a single thread. Supporting
>> multiple threads might be possible in the future, but it could be difficult
>> to control?especially on busy phones?since it consumes more power and may
>> interfere with other threads impacting user experience.
>
> Right, yeah.
>
>>
>>>
>>> BTW, I also notice that zswap IAA compress batching patchset[2] is using
>>> hardware accelerator (Intel Analytics Accelerator) to speed up zswap.
>>> I wonder if the handheld devices have similar hardware to get a similar benefit.
>>
>> Usually, the answer is no. We use zRAM and CPU, but this patch aims to provide
>> a common capability that can be shared by both zRAM and zswap.
>>
>
> Also, not everyone and every setup has access to hardware compression
> accelerators :) This provides benefits for all users.

Got it. Thanks for the explanation.


--
Best Regards,
Yan, Zi


From louisalexis.eyraud at collabora.com  Wed May  7 08:16:31 2025
From: louisalexis.eyraud at collabora.com (Louis-Alexis Eyraud)
Date: Wed, 07 May 2025 17:16:31 +0200
Subject: [PATCH v5 2/3] drm/panfrost: Add support for Mali on the MT8370
 SoC
In-Reply-To: <2b85071a-e3e7-4cfc-a471-e81e463b7c37@arm.com>
References: <20250502-mt8370-enable-gpu-v5-0-98e247b30151@collabora.com>
	 <20250502-mt8370-enable-gpu-v5-2-98e247b30151@collabora.com>
	 <2b85071a-e3e7-4cfc-a471-e81e463b7c37@arm.com>
Message-ID: <381091848a72424a333bb28006d83235068a9e33.camel@collabora.com>

Hi,

On Wed, 2025-05-07 at 15:06 +0100, Steven Price wrote:
> On 02/05/2025 13:17, Louis-Alexis Eyraud wrote:
> > Add a compatible for the MediaTek MT8370 SoC, with an integrated
> > ARM
> > Mali G57 MC2 GPU (Valhall-JM, dual core), with new platform data
> > for
> > its support in the panfrost driver.
> > It uses the same data as MT8186 for the power management features
> > to
> > describe power supplies, pm_domains and enablement (one regulator,
> > two
> > power domains) but also sets the FORCE_AARCH64_PGTABLE flag in the
> > GPU
> > configuration quirks bitfield to enable AARCH64 4K page table
> > format
> > mode.
> > As MT8186 and MT8370 SoC have different GPU architecture (Mali G52
> > 2EE
> > MC2 for MT8186), making them not compatible, and this mode is only
> > enabled for Mediatek SoC that are Mali G57 based (compatible with
> > mediatek,mali-mt8188 or mediatek,mali-8192), having specific
> > platform
> > data allows to set this flag for MT8370 without modifying MT8186
> > configuration and behaviour.
> > 
> > Signed-off-by: Louis-Alexis Eyraud
> > <louisalexis.eyraud at collabora.com>
> 
> With one minor comment fixed below:
> 
> Reviewed-by: Steven Price <steven.price at arm.com>
> 
> > ---
> > ?drivers/gpu/drm/panfrost/panfrost_drv.c | 11 +++++++++++
> > ?1 file changed, 11 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c
> > b/drivers/gpu/drm/panfrost/panfrost_drv.c
> > index
> > f1ec3b02f15a0029d20c7d81046ded59854e885c..8e0a1ae6940c73b7b60233950
> > ae3abdfa843cc8e 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_drv.c
> > +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
> > @@ -846,6 +846,16 @@ static const struct panfrost_compatible
> > mediatek_mt8192_data = {
> > ?	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
> > ?};
> > ?
> > +/* MT8370 uses the same power domains and power supplies as MT8186
> > */
> 
> This comment is not correct - you've got the power domains of MT8186,
> but the supplies of MT8183. The comment doesn't actually add much so
> you 
> could just drop it.
> 
I'll remove it.

> If you're feeling adventurous then one option here is to actually
> clean 
> up the mediatek entries a little. Instead of referring to particular 
> part numbers we could have:
> 
> static const char * const mediatek_2_pm_domains[] = { "core0",
> "core1" };
> static const char * const mediatek_3_pm_domains[] = { "core0",
> "core1", "core2" };
> static const char * const mediatek_5_pm_domains[] = { "core0",
> "core1", "core2",
> ????????????????????????????????????????????????????? "core3",
> "core4" };
> 
> Or even just have the mediatek_5_domains[] array (dropping the '5' in
> the name) and not use ARRAY_SIZE().
> 
> Equally the supplies arrays could be renamed. We have the one with 
> "sram" for legacy and everything else uses {"mali", NULL} but we have
> two definitions for it (mt8183_b and mt8192).
> 
> Thanks,
> Steve
I'll do the array cleaning as well in a separate patch in the v6.

Regards,
Louis-Alexis
> 
> > +static const struct panfrost_compatible mediatek_mt8370_data = {
> > +	.num_supplies = ARRAY_SIZE(mediatek_mt8183_b_supplies) -
> > 1,
> > +	.supply_names = mediatek_mt8183_b_supplies,
> > +	.num_pm_domains = ARRAY_SIZE(mediatek_mt8186_pm_domains),
> > +	.pm_domain_names = mediatek_mt8186_pm_domains,
> > +	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
> > +	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
> > +};
> > +
> > ?static const struct of_device_id dt_match[] = {
> > ?	/* Set first to probe before the generic compatibles */
> > ?	{ .compatible = "amlogic,meson-gxm-mali",
> > @@ -868,6 +878,7 @@ static const struct of_device_id dt_match[] = {
> > ?	{ .compatible = "mediatek,mt8186-mali", .data =
> > &mediatek_mt8186_data },
> > ?	{ .compatible = "mediatek,mt8188-mali", .data =
> > &mediatek_mt8188_data },
> > ?	{ .compatible = "mediatek,mt8192-mali", .data =
> > &mediatek_mt8192_data },
> > +	{ .compatible = "mediatek,mt8370-mali", .data =
> > &mediatek_mt8370_data },
> > ?	{ .compatible = "allwinner,sun50i-h616-mali", .data =
> > &allwinner_h616_data },
> > ?	{}
> > ?};
> > 


From andersson at kernel.org  Wed May  7 09:38:33 2025
From: andersson at kernel.org (Bjorn Andersson)
Date: Wed,  7 May 2025 09:38:33 -0700
Subject: (subset) [PATCH v2 00/17] Arm cpu schema clean-ups
In-Reply-To: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org>
References: <20250410-dt-cpu-schema-v2-0-63d7dc9ddd0a@kernel.org>
Message-ID: <174663591275.3531.6906045623469489227.b4-ty@kernel.org>


On Thu, 10 Apr 2025 10:47:21 -0500, Rob Herring (Arm) wrote:
> The Arm cpu.yaml schema fails to restrict allowed properties in 'cpu'
> nodes. The result, not surprisely, is a number of additional properties
> and errors in .dts files. This series resolves those issues.
> 
> There's still more properties in arm32 DTS files which I have not
> documented. Mostly yet more supply names and "fsl,soc-operating-points".
> What's a few more warnings on the 10000s of warnings...
> 
> [...]

Applied, thanks!

[09/17] arm: dts: qcom: ipq4019: Drop redundant CPU "clock-latency"
        commit: 3ea267124573f24e67f0fe47c4a865f0f283f8fc

Best regards,
-- 
Bjorn Andersson <andersson at kernel.org>


From nfraprado at collabora.com  Wed May  7 09:41:27 2025
From: nfraprado at collabora.com (=?utf-8?B?TsOtY29sYXMgRi4gUi4gQS4=?= Prado)
Date: Wed, 7 May 2025 12:41:27 -0400
Subject: [PATCH] ASoC: mediatek: mt8188-mt6359: select
 CONFIG_SND_SOC_MT6359_ACCDET
In-Reply-To: <20250505052106.1811802-1-arnd@kernel.org>
References: <20250505052106.1811802-1-arnd@kernel.org>
Message-ID: <d9642581-3fed-47d8-9661-4335ec1e9c27@notapiano>

On Mon, May 05, 2025 at 07:20:52AM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> The driver support was added without selecting the codec, which leads to
> a link failure:
> 
> aarch64-linux-ld: sound/soc/mediatek/mt8188/mt8188-mt6359.o: in function `mt8188_mt6359_init':
> mt8188-mt6359.c:(.text+0x19f0): undefined reference to `mt6359_accdet_enable_jack_detect'

Hm, I cannot seem to reproduce this. I just tried to build on today's next with
CONFIG_SND_SOC_MT6359_ACCDET disabled and have tried
CONFIG_SND_SOC_MT8188_MT6359 both =m and =y, but in both cases it compiles fine.

I wonder if somehow your tree was missing "ASoC: mediatek: mt6359: Add stub for
mt6359_accdet_enable_jack_detect" [1], or if it's due to a difference in
compiler versions used...

(I'm using gcc-linaro-12.3.1-2023.06-x86_64_aarch64-linux-gnu)

Thanks,
N?colas

[1] https://lore.kernel.org/all/20250306-mt8188-accdet-v3-3-7828e835ff4b at collabora.com/

> 
> Fixes: f35d834d67ad ("ASoC: mediatek: mt8188-mt6359: Add accdet headset jack detect support")
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  sound/soc/mediatek/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig
> index 3033e2d3fe16..e148d4d94160 100644
> --- a/sound/soc/mediatek/Kconfig
> +++ b/sound/soc/mediatek/Kconfig
> @@ -229,6 +229,7 @@ config SND_SOC_MT8188_MT6359
>  	tristate "ASoC Audio driver for MT8188 with MT6359 and I2S codecs"
>  	depends on SND_SOC_MT8188 && MTK_PMIC_WRAP
>  	depends on I2C
> +	select SND_SOC_MT6359_ACCDET
>  	select SND_SOC_MT6359
>  	select SND_SOC_HDMI_CODEC
>  	select SND_SOC_DMIC
> -- 
> 2.39.5
> 


From arnd at arndb.de  Wed May  7 10:10:54 2025
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 07 May 2025 19:10:54 +0200
Subject: [PATCH] ASoC: mediatek: mt8188-mt6359: select CONFIG_SND_SOC_MT6359_ACCDET
In-Reply-To: <d9642581-3fed-47d8-9661-4335ec1e9c27@notapiano>
References: <20250505052106.1811802-1-arnd@kernel.org>
 <d9642581-3fed-47d8-9661-4335ec1e9c27@notapiano>
Message-ID: <86a3a0ab-be37-4b4d-a5a5-32d09c1a75ce@app.fastmail.com>

On Wed, May 7, 2025, at 18:41, N?colas F. R. A. Prado wrote:
> On Mon, May 05, 2025 at 07:20:52AM +0200, Arnd Bergmann wrote:
>> From: Arnd Bergmann <arnd at arndb.de>
>> 
>> The driver support was added without selecting the codec, which leads to
>> a link failure:
>> 
>> aarch64-linux-ld: sound/soc/mediatek/mt8188/mt8188-mt6359.o: in function `mt8188_mt6359_init':
>> mt8188-mt6359.c:(.text+0x19f0): undefined reference to `mt6359_accdet_enable_jack_detect'
>
> Hm, I cannot seem to reproduce this. I just tried to build on today's next with
> CONFIG_SND_SOC_MT6359_ACCDET disabled and have tried
> CONFIG_SND_SOC_MT8188_MT6359 both =m and =y, but in both cases it compiles fine.

The config that failed for me had CONFIG_SND_SOC_MT6359_ACCDET.

> I wonder if somehow your tree was missing "ASoC: mediatek: mt6359: Add stub for
> mt6359_accdet_enable_jack_detect" [1]

> https://lore.kernel.org/all/20250306-mt8188-accdet-v3-3-7828e835ff4b at collabora.com/

I had not seen that patch, but with that applied, my patch needs to
be revised as well. If the idea is that CONFIG_SND_SOC_MT8188_MT6359
can work correctly without CONFIG_SND_SOC_MT6359_ACCDET, it should be

      depends on SND_SOC_MT6359_ACCDET || !SND_SOC_MT6359_ACCDET

in order to force SND_SOC_MT8188_MT6359=m if the ACCDET portion
is in a loadable module.

If SND_SOC_MT8188_MT6359 requires SND_SOC_MT6359_ACCDET to work
correctly, then my original patch is still needed and yours
should be reverted.

     Arnd


From lorenzo at kernel.org  Wed May  7 10:48:44 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 07 May 2025 19:48:44 +0200
Subject: [PATCH net-next 0/2] Add the capability to allocate hw buffers in
 SRAM for EN7581 SoC
Message-ID: <20250507-airopha-desc-sram-v1-0-d42037431bfa@kernel.org>

In order to improve packet processing and packet forwarding
performances, EN7581 SoC supports allocating buffers for hw forwarding
queues in SRAM instead of DRAM if available on the system.
Rely on SRAM for buffers allocation if available on the system and use
DRAM as fallback.

---
Lorenzo Bianconi (2):
      dt-bindings: net: airoha: Add EN7581 memory-region property
      net: airoha: Add the capability to allocate hw buffers in SRAM

 .../devicetree/bindings/net/airoha,en7581-eth.yaml | 13 ++++++
 drivers/net/ethernet/airoha/airoha_eth.c           | 48 ++++++++++++++++++----
 2 files changed, 52 insertions(+), 9 deletions(-)
---
base-commit: 9daaf197860055aa26c06d273d317c18c6e3621a
change-id: 20250507-airopha-desc-sram-faeb3ea6cbc5

Best regards,
-- 
Lorenzo Bianconi <lorenzo at kernel.org>



From lorenzo at kernel.org  Wed May  7 10:48:45 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 07 May 2025 19:48:45 +0200
Subject: [PATCH net-next 1/2] dt-bindings: net: airoha: Add EN7581
 memory-region property
In-Reply-To: <20250507-airopha-desc-sram-v1-0-d42037431bfa@kernel.org>
References: <20250507-airopha-desc-sram-v1-0-d42037431bfa@kernel.org>
Message-ID: <20250507-airopha-desc-sram-v1-1-d42037431bfa@kernel.org>

Introduce the memory-region and memory-region-names properties for the
ethernet node available on EN7581 SoC. In order to improve performances,
EN7581 SoC supports allocating buffers for hw forwarding queues in SRAM
instead of DRAM if available on the system.

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 .../devicetree/bindings/net/airoha,en7581-eth.yaml          | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
index 0fdd1126541774acacc783d98e4c089b2d2b85e2..6d22131ac2f9e28390b9e785ce33e8d983eafd0f 100644
--- a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
+++ b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
@@ -57,6 +57,16 @@ properties:
       - const: hsi-mac
       - const: xfp-mac
 
+  memory-region:
+    items:
+      - description: QDMA0 buffer memory
+      - description: QDMA1 buffer memory
+
+  memory-region-names:
+    items:
+      - const: qdma0-buf
+      - const: qdma1-buf
+
   "#address-cells":
     const: 1
 
@@ -140,6 +150,9 @@ examples:
                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
                      <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 
+        memory-region = <&qdma0_buf>, <&qdma1_buf>;
+        memory-region-names = "qdma0-buf", "qdma1-buf";
+
         airoha,npu = <&npu>;
 
         #address-cells = <1>;

-- 
2.49.0



From lorenzo at kernel.org  Wed May  7 10:48:46 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 07 May 2025 19:48:46 +0200
Subject: [PATCH net-next 2/2] net: airoha: Add the capability to allocate
 hw buffers in SRAM
In-Reply-To: <20250507-airopha-desc-sram-v1-0-d42037431bfa@kernel.org>
References: <20250507-airopha-desc-sram-v1-0-d42037431bfa@kernel.org>
Message-ID: <20250507-airopha-desc-sram-v1-2-d42037431bfa@kernel.org>

In order to improve packet processing and packet forwarding
performances, EN7581 SoC supports allocating buffers for hw forwarding
queues in SRAM instead of DRAM if available on the system.
Rely on SRAM for buffers allocation if available on the system and use
DRAM as fallback.

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 drivers/net/ethernet/airoha/airoha_eth.c | 48 ++++++++++++++++++++++++++------
 1 file changed, 39 insertions(+), 9 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 16c7896f931fd9532aa3b8cc78f41afc676aa117..b1ca8322d4eb34f48a6ed6a3b4596c128324cd50 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -5,6 +5,7 @@
  */
 #include <linux/of.h>
 #include <linux/of_net.h>
+#include <linux/of_reserved_mem.h>
 #include <linux/platform_device.h>
 #include <linux/tcp.h>
 #include <linux/u64_stats_sync.h>
@@ -1076,9 +1077,11 @@ static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q)
 static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
 {
 	struct airoha_eth *eth = qdma->eth;
+	int id = qdma - &eth->qdma[0];
 	dma_addr_t dma_addr;
-	u32 status;
-	int size;
+	const char *name;
+	int size, index;
+	u32 status, val;
 
 	size = HW_DSCP_NUM * sizeof(struct airoha_qdma_fwd_desc);
 	qdma->hfwd.desc = dmam_alloc_coherent(eth->dev, size, &dma_addr,
@@ -1088,12 +1091,36 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
 
 	airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr);
 
-	size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM;
-	qdma->hfwd.q = dmam_alloc_coherent(eth->dev, size, &dma_addr,
-					   GFP_KERNEL);
-	if (!qdma->hfwd.q)
+	name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id);
+	if (!name)
 		return -ENOMEM;
 
+	index = of_property_match_string(eth->dev->of_node,
+					 "memory-region-names", name);
+	if (index >= 0) { /* buffers in sram */
+		struct reserved_mem *rmem;
+		struct device_node *np;
+
+		np = of_parse_phandle(eth->dev->of_node, "memory-region",
+				      index);
+		if (!np)
+			return -ENODEV;
+
+		rmem = of_reserved_mem_lookup(np);
+		of_node_put(np);
+
+		dma_addr = rmem->base;
+		qdma->hfwd.q = devm_ioremap(eth->dev, rmem->base, rmem->size);
+		if (!qdma->hfwd.q)
+			return -ENOMEM;
+	} else {
+		size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM;
+		qdma->hfwd.q = dmam_alloc_coherent(eth->dev, size, &dma_addr,
+						   GFP_KERNEL);
+		if (!qdma->hfwd.q)
+			return -ENOMEM;
+	}
+
 	airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr);
 
 	airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG,
@@ -1101,11 +1128,14 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
 			FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 0));
 	airoha_qdma_rmw(qdma, REG_FWD_DSCP_LOW_THR, FWD_DSCP_LOW_THR_MASK,
 			FIELD_PREP(FWD_DSCP_LOW_THR_MASK, 128));
+
+	val = FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) |
+	      LMGR_INIT_START;
+	if (index >= 0)
+		val |= LMGR_SRAM_MODE_MASK;
 	airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG,
 			LMGR_INIT_START | LMGR_SRAM_MODE_MASK |
-			HW_FWD_DESC_NUM_MASK,
-			FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) |
-			LMGR_INIT_START);
+			HW_FWD_DESC_NUM_MASK, val);
 
 	return read_poll_timeout(airoha_qdma_rr, status,
 				 !(status & LMGR_INIT_START), USEC_PER_MSEC,

-- 
2.49.0



From nfraprado at collabora.com  Wed May  7 12:22:40 2025
From: nfraprado at collabora.com (=?utf-8?B?TsOtY29sYXMgRi4gUi4gQS4=?= Prado)
Date: Wed, 7 May 2025 15:22:40 -0400
Subject: [PATCH 1/4] dt-bindings: mfd: mediatek: mt6397: Add
 #sound-dai-cells property
In-Reply-To: <20250505-mt8395-dtb-errors-v1-1-9c4714dcdcdb@collabora.com>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
 <20250505-mt8395-dtb-errors-v1-1-9c4714dcdcdb@collabora.com>
Message-ID: <34399fb1-f876-4c7e-b164-4331defd4426@notapiano>

On Mon, May 05, 2025 at 03:23:37PM +0200, Julien Massot wrote:
> The 'mt6359.dtsi' file already uses the '#sound-dai-cells' property.
> Add the corresponding property to the binding to fix the following
> dtb-check error:
> 
> mediatek/mt8395-radxa-nio-12l.dtb: pmic: '#sound-dai-cells', 'mt6359rtc' do not match any of the regexes: 'pinctrl-[0-9]+'
> from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6397.yaml#
> 
> Fixes: 9bc8353be720 ("arm64: dts: mt6359: Add #sound-dai-cells property")
> Signed-off-by: Julien Massot <julien.massot at collabora.com>

Reviewed-by: N?colas F. R. A. Prado <nfraprado at collabora.com>

Thanks,
N?colas


From bvanassche at acm.org  Wed May  7 12:26:54 2025
From: bvanassche at acm.org (Bart Van Assche)
Date: Wed, 7 May 2025 12:26:54 -0700
Subject: [PATCH v1] ufs: core: fix hwq_id type and value
In-Reply-To: <6c9e983154ff8d9b4a1e63eb503e8b147303eb68.camel@mediatek.com>
References: <20250506124038.4071609-1-peter.wang@mediatek.com>
 <04fc1549-0fa6-4956-b522-df5fbc26100c@acm.org>
 <6c9e983154ff8d9b4a1e63eb503e8b147303eb68.camel@mediatek.com>
Message-ID: <95235015-270d-451e-989c-9fddcbfcb97e@acm.org>

On 5/6/25 9:03 PM, Peter Wang (???) wrote:
> Whether it is necessary or not depends on how we define 'necessary.'
> If the criterion is simply to avoid errors, then indeed, this patch
> is not necessary. However, if we are addressing the warning caused
> by incorrect behavior (assigning int to u32), then it is necessary
> to fix it. After all, we shouldn't just be satisfied with avoiding
> errors, we should strive to make the Linux kernel as perfect as
> possible, shouldn't we?

Errors? Which errors? Using -1 instead of UINT_MAX is common in C code.
Assigning variables of signed integer type to unsigned variables is also
widespread. Using %d to format a negative number, although dubious, is
also common in C code. Several years ago gcc warned about using %d to
format unsigned integers. That warning was disabled again because there
is too much existing code that follows this practice.

> Additionally, there are many ways to determine whether MCQ is enabled,
> including reading the host capability or checking hba->mcq_enabled,
> etc.
> Moreover, MCQ is not a feature that trun on and off at runtime.
> It is at the end of the UFS initialization that the status of MCQ
> is determined, so it shouldn't be necessary to rely on this to
> determine whether MCQ is enabled, right?

If you want to proceed with this patch, please make it clear in the
patch description that this patch is a behavior change and not a bug
fix.

Thanks,

Bart.


From nfraprado at collabora.com  Wed May  7 12:31:32 2025
From: nfraprado at collabora.com (=?utf-8?B?TsOtY29sYXMgRi4gUi4gQS4=?= Prado)
Date: Wed, 7 May 2025 15:31:32 -0400
Subject: [PATCH] ASoC: mediatek: mt8188-mt6359: select
 CONFIG_SND_SOC_MT6359_ACCDET
In-Reply-To: <86a3a0ab-be37-4b4d-a5a5-32d09c1a75ce@app.fastmail.com>
References: <20250505052106.1811802-1-arnd@kernel.org>
 <d9642581-3fed-47d8-9661-4335ec1e9c27@notapiano>
 <86a3a0ab-be37-4b4d-a5a5-32d09c1a75ce@app.fastmail.com>
Message-ID: <5e45cf78-ea88-4a93-83e6-9022feed0421@notapiano>

On Wed, May 07, 2025 at 07:10:54PM +0200, Arnd Bergmann wrote:
> On Wed, May 7, 2025, at 18:41, N?colas F. R. A. Prado wrote:
> > On Mon, May 05, 2025 at 07:20:52AM +0200, Arnd Bergmann wrote:
> >> From: Arnd Bergmann <arnd at arndb.de>
> >> 
> >> The driver support was added without selecting the codec, which leads to
> >> a link failure:
> >> 
> >> aarch64-linux-ld: sound/soc/mediatek/mt8188/mt8188-mt6359.o: in function `mt8188_mt6359_init':
> >> mt8188-mt6359.c:(.text+0x19f0): undefined reference to `mt6359_accdet_enable_jack_detect'
> >
> > Hm, I cannot seem to reproduce this. I just tried to build on today's next with
> > CONFIG_SND_SOC_MT6359_ACCDET disabled and have tried
> > CONFIG_SND_SOC_MT8188_MT6359 both =m and =y, but in both cases it compiles fine.
> 
> The config that failed for me had CONFIG_SND_SOC_MT6359_ACCDET.
> 
> > I wonder if somehow your tree was missing "ASoC: mediatek: mt6359: Add stub for
> > mt6359_accdet_enable_jack_detect" [1]
> 
> > https://lore.kernel.org/all/20250306-mt8188-accdet-v3-3-7828e835ff4b at collabora.com/
> 
> I had not seen that patch, but with that applied, my patch needs to
> be revised as well. If the idea is that CONFIG_SND_SOC_MT8188_MT6359
> can work correctly without CONFIG_SND_SOC_MT6359_ACCDET, it should be
> 
>       depends on SND_SOC_MT6359_ACCDET || !SND_SOC_MT6359_ACCDET
> 
> in order to force SND_SOC_MT8188_MT6359=m if the ACCDET portion
> is in a loadable module.

Ah indeed, that's it. The stub was added to allow MT8188_MT6359 to work without 
ACCDET, but we still need to prevent the MT8188_MT6359=y and ACCDET=m case, like
you suggest. I can send that patch right away.

Thanks,
N?colas


From nfraprado at collabora.com  Wed May  7 13:14:14 2025
From: nfraprado at collabora.com (=?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?=)
Date: Wed, 07 May 2025 16:14:14 -0400
Subject: [PATCH] ASoC: mediatek: mt8188-mt6359: Depend on MT6359_ACCDET set
 or disabled
Message-ID: <20250507-mt8188-mt6359-accdet-depend-v1-1-aad70ce62964@collabora.com>

Commit 0116a7d84b32 ("ASoC: mediatek: mt6359: Add stub for
mt6359_accdet_enable_jack_detect") added a stub for
mt6359_accdet_enable_jack_detect() in order to allow the mt8188-mt6359
driver to be enabled without requiring the mt6359-accdet to also be
enabled, since it is not always needed.

However, in the case that CONFIG_SND_SOC_MT8188_MT6359=y and
CONFIG_SND_SOC_MT6359_ACCDET=m, a link error will happen, which commit
b19fa45715ce ("ASoC: mediatek: mt8188-mt6359: select
CONFIG_SND_SOC_MT6359_ACCDET") solved by selecting
CONFIG_SND_SOC_MT6359_ACCDET.

In order to not require CONFIG_SND_SOC_MT6359_ACCDET as originally
intended, but also prevent the link error, depend on ACCDET being
enabled or disabled (which will force MT8188_MT6359=m if
MT6359_ACCDET=m).

Fixes: f35d834d67ad ("ASoC: mediatek: mt8188-mt6359: Add accdet headset jack detect support")
Fixes: b19fa45715ce ("ASoC: mediatek: mt8188-mt6359: select CONFIG_SND_SOC_MT6359_ACCDET")
Suggested-by: Arnd Bergmann <arnd at kernel.org>
Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
---
 sound/soc/mediatek/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig
index e148d4d9416011252ddbc37111c3e7b9d59082f9..90e367586493d7a413efade6a8586c4770c459ab 100644
--- a/sound/soc/mediatek/Kconfig
+++ b/sound/soc/mediatek/Kconfig
@@ -228,8 +228,8 @@ config SND_SOC_MT8188
 config SND_SOC_MT8188_MT6359
 	tristate "ASoC Audio driver for MT8188 with MT6359 and I2S codecs"
 	depends on SND_SOC_MT8188 && MTK_PMIC_WRAP
+	depends on SND_SOC_MT6359_ACCDET || !SND_SOC_MT6359_ACCDET
 	depends on I2C
-	select SND_SOC_MT6359_ACCDET
 	select SND_SOC_MT6359
 	select SND_SOC_HDMI_CODEC
 	select SND_SOC_DMIC

---
base-commit: b19fa45715ce9cfcc597ed140df31115e969b39d
change-id: 20250507-mt8188-mt6359-accdet-depend-4ac02b5e4dea

Best regards,
-- 
N?colas F. R. A. Prado <nfraprado at collabora.com>



From patchwork-bot+netdevbpf at kernel.org  Wed May  7 18:20:30 2025
From: patchwork-bot+netdevbpf at kernel.org (patchwork-bot+netdevbpf at kernel.org)
Date: Thu, 08 May 2025 01:20:30 +0000
Subject: [PATCH net v5] net: airoha: Add missing field to ppe_mbox_data
 struct
In-Reply-To: <20250506-airoha-en7581-fix-ppe_mbox_data-v5-1-29cabed6864d@kernel.org>
References: <20250506-airoha-en7581-fix-ppe_mbox_data-v5-1-29cabed6864d@kernel.org>
Message-ID: <174666723099.2414619.1850276703791840272.git-patchwork-notify@kernel.org>

Hello:

This patch was applied to netdev/net.git (main)
by Jakub Kicinski <kuba at kernel.org>:

On Tue, 06 May 2025 18:56:47 +0200 you wrote:
> The official Airoha EN7581 firmware requires adding max_packet field in
> ppe_mbox_data struct while the unofficial one used to develop the Airoha
> EN7581 flowtable support does not require this field.
> This patch does not introduce any real backwards compatible issue since
> EN7581 fw is not publicly available in linux-firmware or other
> repositories (e.g. OpenWrt) yet and the official fw version will use this
> new layout. For this reason this change needs to be backported.
> Moreover, make explicit the padding added by the compiler introducing
> the rsv array in init_info struct.
> At the same time use u32 instead of int for init_info and set_info
> struct definitions in ppe_mbox_data struct.
> 
> [...]

Here is the summary with links:
  - [net,v5] net: airoha: Add missing field to ppe_mbox_data struct
    https://git.kernel.org/netdev/net/c/4a7843cc8a41

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html




From mingyen.hsieh at mediatek.com  Wed May  7 22:16:04 2025
From: mingyen.hsieh at mediatek.com (Mingyen Hsieh)
Date: Thu, 8 May 2025 13:16:04 +0800
Subject: [PATCH] wifi: mt76: mt7925: fix missing hdr_trans_tlv command for broadcast wtbl
Message-ID: <20250508051604.280661-1-mingyen.hsieh@mediatek.com>

From: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>

The hdr_trans_tlv function call has been moved inside the conditional block
to ensure it is executed when info->enable is true.

Cc: stable at vger.kernel.org
Fixes: cb1353ef3473 ("wifi: mt76: mt7925: integrate *mlo_sta_cmd and *sta_cmd")
Signed-off-by: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
---
 drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
index a42b584634ab..fd756f0d18f8 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
@@ -2183,14 +2183,14 @@ mt7925_mcu_sta_cmd(struct mt76_phy *phy,
 			mt7925_mcu_sta_mld_tlv(skb, info->vif, info->link_sta->sta);
 			mt7925_mcu_sta_eht_mld_tlv(skb, info->vif, info->link_sta->sta);
 		}
-
-		mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info->link_sta);
 	}
 
 	if (!info->enable) {
 		mt7925_mcu_sta_remove_tlv(skb);
 		mt76_connac_mcu_add_tlv(skb, STA_REC_MLD_OFF,
 					sizeof(struct tlv));
+	} else {
+		mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info->link_sta);
 	}
 
 	return mt76_mcu_skb_send_msg(dev, skb, info->cmd, true);
-- 
2.34.1



From krzk at kernel.org  Wed May  7 23:01:16 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Thu, 8 May 2025 08:01:16 +0200
Subject: [PATCH 1/4] dt-bindings: mfd: mediatek: mt6397: Add
 #sound-dai-cells property
In-Reply-To: <20250505-mt8395-dtb-errors-v1-1-9c4714dcdcdb@collabora.com>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
 <20250505-mt8395-dtb-errors-v1-1-9c4714dcdcdb@collabora.com>
Message-ID: <79148223-d87f-486e-9d51-979f9188a837@kernel.org>

On 05/05/2025 15:23, Julien Massot wrote:
> The 'mt6359.dtsi' file already uses the '#sound-dai-cells' property.
> Add the corresponding property to the binding to fix the following
> dtb-check error:
If this is a DAI, then you miss dai-common reference. If not, you need
to explain it in commit msg.

Best regards,
Krzysztof


From krzk at kernel.org  Wed May  7 23:03:08 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Thu, 8 May 2025 08:03:08 +0200
Subject: [PATCH 2/4] dt-bindings: iommu: mediatek: mt8195 Accept up to 5
 interrupts
In-Reply-To: <20250505-mt8395-dtb-errors-v1-2-9c4714dcdcdb@collabora.com>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
 <20250505-mt8395-dtb-errors-v1-2-9c4714dcdcdb@collabora.com>
Message-ID: <baeae909-4d12-4cbd-a063-7ad165304b96@kernel.org>

On 05/05/2025 15:23, Julien Massot wrote:
> 
> Fixes: 3b5838d1d82e3 ("arm64: dts: mt8195: Add iommu and smi nodes")
> Signed-off-by: Julien Massot <julien.massot at collabora.com>
> ---
>  Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> index 75750c64157c868725c087500ac81be4e282c829..035941c2db32170e9a69a5363d8c05ef767bb251 100644
> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> @@ -97,7 +97,8 @@ properties:
>      maxItems: 1
>  
>    interrupts:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 5
>  
Every iommu or just some (as described in commit msg) can have 5
interrupts? Looks you miss here proper constraints per variant.

Best regards,
Krzysztof


From sirius.wang at mediatek.com  Wed May  7 23:35:40 2025
From: sirius.wang at mediatek.com (Sirius Wang)
Date: Thu, 8 May 2025 14:35:40 +0800
Subject: [PATCH v2 1/3] dt-bindings: arm: Add compatible for MediaTek MT8189
In-Reply-To: <20250508063546.289115-1-sirius.wang@mediatek.com>
References: <20250508063546.289115-1-sirius.wang@mediatek.com>
Message-ID: <20250508063546.289115-2-sirius.wang@mediatek.com>

This commit adds dt-binding documentation for the MediaTek MT8189
reference board.

Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>
---
 Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index fa1646bc0bac..05e827076a7f 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -372,6 +372,10 @@ properties:
           - enum:
               - mediatek,mt8188-evb
           - const: mediatek,mt8188
+      - items:
+          - enum:
+              - mediatek,mt8189-evb
+          - const: mediatek,mt8189
       - description: Google Hayato
         items:
           - const: google,hayato-rev1
-- 
2.45.2



From sirius.wang at mediatek.com  Wed May  7 23:35:42 2025
From: sirius.wang at mediatek.com (Sirius Wang)
Date: Thu, 8 May 2025 14:35:42 +0800
Subject: [PATCH v2 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile
In-Reply-To: <20250508063546.289115-1-sirius.wang@mediatek.com>
References: <20250508063546.289115-1-sirius.wang@mediatek.com>
Message-ID: <20250508063546.289115-4-sirius.wang@mediatek.com>

Add mt8189 dts evaluation board and Mafefile

Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>
---
 arch/arm64/boot/dts/mediatek/Makefile       |   1 +
 arch/arm64/boot/dts/mediatek/mt8189-evb.dts |  20 +
 arch/arm64/boot/dts/mediatek/mt8189.dtsi    | 430 ++++++++++++++++++++
 3 files changed, 451 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 3aa06476c6c0..ad2ac9e1bb79 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8189-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
new file mode 100644
index 000000000000..e5d9ce1b8e61
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ * Author: Sirius Wang <sirius.wang at mediatek.com>
+ */
+/dts-v1/;
+#include "mt8189.dtsi"
+
+/ {
+	model = "MediaTek MT8189 evaluation board";
+	compatible = "mediatek,mt8189-evb", "mediatek,mt8189";
+
+	chosen: chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
new file mode 100644
index 000000000000..50c7a3811e0f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
@@ -0,0 +1,430 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "mediatek,mt8189";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	clk32k: oscillator-clk32k {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32000>;
+		clock-output-names = "clk32k";
+	};
+
+	clk13m: oscillator-clk13m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk26m>;
+		clock-mult = <1>;
+		clock-div = <2>;
+		clock-output-names = "clk13m";
+	};
+
+	clk26m: oscillator-clk26m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+		clock-output-names = "clk26m";
+	};
+
+	clk104m: oscillator-clk104m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk26m>;
+		clock-mult = <4>;
+		clock-div = <1>;
+		clock-output-names = "clk104m";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x000>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu1: cpu at 100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu2: cpu at 200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu3: cpu at 300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu4: cpu at 400 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x400>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu5: cpu at 500 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x500>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu6: cpu at 600 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78";
+			reg = <0x600>;
+			enable-method = "psci";
+			clock-frequency = <3000000000>;
+			capacity-dmips-mhz = <958>;
+			cpu-idle-states = <&cpu_off_m>, <&cpu_cluster_off_m>, <&cpu_mcusys_off_m>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <65536>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <65536>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_1>;
+			performance-domains = <&performance 1>;
+			#cooling-cells = <2>;
+		};
+
+		cpu7: cpu at 700 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78";
+			reg = <0x700>;
+			enable-method = "psci";
+			clock-frequency = <3000000000>;
+			capacity-dmips-mhz = <958>;
+			cpu-idle-states = <&cpu_off_m>, <&cpu_cluster_off_m>, <&cpu_mcusys_off_m>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <65536>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <65536>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_1>;
+			performance-domains = <&performance 1>;
+			#cooling-cells = <2>;
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+				core4 {
+					cpu = <&cpu4>;
+				};
+				core5 {
+					cpu = <&cpu5>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu6>;
+				};
+				core1 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			cpu_off_l: cpu-off-l {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x00010000>;
+				local-timer-stop;
+				entry-latency-us = <97>;
+				exit-latency-us = <252>;
+				min-residency-us = <6710>;
+			};
+
+			cpu_off_m: cpu-off-m {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x00010000>;
+				local-timer-stop;
+				entry-latency-us = <53>;
+				exit-latency-us = <143>;
+				min-residency-us = <2120>;
+			};
+
+			cpu_cluster_off_l: cpu-cluster-off-l {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x01010001>;
+				local-timer-stop;
+				entry-latency-us = <109>;
+				exit-latency-us = <325>;
+				min-residency-us = <6710>;
+			};
+
+			cpu_cluster_off_m: cpu-cluster-off-m {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x01010001>;
+				local-timer-stop;
+				entry-latency-us = <59>;
+				exit-latency-us = <188>;
+				min-residency-us = <2120>;
+			};
+
+			cpu_mcusys_off_l: cpu-mcusys-off-l {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x02010007>;
+				local-timer-stop;
+				entry-latency-us = <1357>;
+				exit-latency-us = <835>;
+				min-residency-us = <6710>;
+			};
+
+			cpu_mcusys_off_m: cpu-mcusys-off-m {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x02010007>;
+				local-timer-stop;
+				entry-latency-us = <1202>;
+				exit-latency-us = <679>;
+				min-residency-us = <2120>;
+			};
+
+			cpu_system_vcore: cpu-system-vcore {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x020100ff>;
+				local-timer-stop;
+				entry-latency-us = <940>;
+				exit-latency-us = <3500>;
+				min-residency-us = <35200>;
+			};
+
+			cpu_s2idle: cpu-s2idle {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x020180ff>;
+				local-timer-stop;
+				entry-latency-us = <10000>;
+				exit-latency-us = <10000>;
+				min-residency-us = <4294967295>;
+			};
+		};
+
+		l2_0: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <131072>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			next-level-cache = <&l3_0>;
+			cache-unified;
+		};
+
+		l2_1: l2-cache1 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <262144>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			next-level-cache = <&l3_0>;
+			cache-unified;
+		};
+
+		l3_0: l3-cache {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-size = <1048576>;
+			cache-line-size = <64>;
+			cache-sets = <2048>;
+			cache-unified;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	memory: memory at 40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0xC0000000>;
+	};
+
+	timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+
+		performance: performance-controller at 11bc10 {
+			compatible = "mediatek,cpufreq-hw";
+			reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+			#performance-domain-cells = <1>;
+		};
+
+		gic: interrupt-controller at c000000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <4>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			reg = <0 0xc000000 0 0x40000>, /* distributor */
+			      <0 0xc040000 0 0x200000>; /* redistributor */
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+			ppi-partitions {
+				ppi_cluster0: interrupt-partition-0 {
+					affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
+				};
+
+				ppi_cluster1: interrupt-partition-1 {
+					affinity = <&cpu6 &cpu7>;
+				};
+			};
+		};
+
+		uart0: serial at 11001000 {
+			compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart";
+			reg = <0 0x11001000 0 0x1000>;
+			interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&clk26m>, <&clk26m>;
+			clock-names = "baud", "bus";
+			status = "disabled";
+		};
+	};
+
+	ulposc: oscillator-ulposc {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <520000000>;
+		clock-output-names = "ulposc";
+	};
+
+	ulposc3: oscillator-ulposc3 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+		clock-output-names = "ulposc3";
+	};
+};
-- 
2.45.2



From sirius.wang at mediatek.com  Wed May  7 23:35:39 2025
From: sirius.wang at mediatek.com (Sirius Wang)
Date: Thu, 8 May 2025 14:35:39 +0800
Subject: [PATCH v2 0/3] Add mt8189 dts evalution board and Makefile
Message-ID: <20250508063546.289115-1-sirius.wang@mediatek.com>

We add basic chip support for Mediatek MT8189 on evalution board.

In this series, we also add dt-bindings document definition for MT8189.

This series is based on tag: next-20250507

Changs in v2:
 - Fix warning issues for make CHECK_DTBS=y
 - Add mediatek,uart.yaml document

Sirius Wang (3):
  dt-bindings: arm: Add compatible for MediaTek MT8189
  dt-bindings: serial: mediatek,uart: Add compatible for MT8189
  arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile

 .../devicetree/bindings/arm/mediatek.yaml     |   4 +
 .../bindings/serial/mediatek,uart.yaml        |   1 +
 arch/arm64/boot/dts/mediatek/Makefile         |   1 +
 arch/arm64/boot/dts/mediatek/mt8189-evb.dts   |  20 +
 arch/arm64/boot/dts/mediatek/mt8189.dtsi      | 430 ++++++++++++++++++
 5 files changed, 456 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi

-- 
2.45.2



From sirius.wang at mediatek.com  Wed May  7 23:35:41 2025
From: sirius.wang at mediatek.com (Sirius Wang)
Date: Thu, 8 May 2025 14:35:41 +0800
Subject: [PATCH v2 2/3] dt-bindings: serial: mediatek,uart: Add compatible for MT8189
In-Reply-To: <20250508063546.289115-1-sirius.wang@mediatek.com>
References: <20250508063546.289115-1-sirius.wang@mediatek.com>
Message-ID: <20250508063546.289115-3-sirius.wang@mediatek.com>

Add compatible string for serial on MT8189 SoC.

Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>
---
 Documentation/devicetree/bindings/serial/mediatek,uart.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
index c55d9a0efa19..fabc22d47cb3 100644
--- a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
+++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
@@ -46,6 +46,7 @@ properties:
               - mediatek,mt8183-uart
               - mediatek,mt8186-uart
               - mediatek,mt8188-uart
+              - mediatek,mt8189-uart
               - mediatek,mt8192-uart
               - mediatek,mt8195-uart
               - mediatek,mt8365-uart
-- 
2.45.2



From robh at kernel.org  Thu May  8 00:09:55 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Thu, 08 May 2025 02:09:55 -0500
Subject: [PATCH v2 1/3] dt-bindings: arm: Add compatible for MediaTek
 MT8189
In-Reply-To: <20250508063546.289115-2-sirius.wang@mediatek.com>
References: <20250508063546.289115-1-sirius.wang@mediatek.com>
 <20250508063546.289115-2-sirius.wang@mediatek.com>
Message-ID: <174668818902.3553912.2627807939857046416.robh@kernel.org>


On Thu, 08 May 2025 14:35:40 +0800, Sirius Wang wrote:
> This commit adds dt-binding documentation for the MediaTek MT8189
> reference board.
> 
> Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>
> ---
>  Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:


doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250508063546.289115-2-sirius.wang at mediatek.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.



From robh at kernel.org  Thu May  8 00:09:57 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Thu, 08 May 2025 02:09:57 -0500
Subject: [PATCH v2 2/3] dt-bindings: serial: mediatek,uart: Add
 compatible for MT8189
In-Reply-To: <20250508063546.289115-3-sirius.wang@mediatek.com>
References: <20250508063546.289115-1-sirius.wang@mediatek.com>
 <20250508063546.289115-3-sirius.wang@mediatek.com>
Message-ID: <174668818993.3553950.2026638570584322328.robh@kernel.org>


On Thu, 08 May 2025 14:35:41 +0800, Sirius Wang wrote:
> Add compatible string for serial on MT8189 SoC.
> 
> Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>
> ---
>  Documentation/devicetree/bindings/serial/mediatek,uart.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:


doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250508063546.289115-3-sirius.wang at mediatek.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.



From chenqiuji666 at gmail.com  Thu May  8 00:36:33 2025
From: chenqiuji666 at gmail.com (Qiu-ji Chen)
Date: Thu,  8 May 2025 15:36:33 +0800
Subject: [PATCH v2] dmaengine: mediatek: Fix a possible deadlock error in mtk_cqdma_tx_status()
Message-ID: <20250508073634.3719-1-chenqiuji666@gmail.com>

Fix a potential deadlock bug. Observe that in the mtk-cqdma.c
file, functions like mtk_cqdma_issue_pending() and
mtk_cqdma_free_active_desc() properly acquire the pc lock before the vc
lock when handling pc and vc fields. However, mtk_cqdma_tx_status()
violates this order by first acquiring the vc lock before invoking
mtk_cqdma_find_active_desc(), which subsequently takes the pc lock. This
reversed locking sequence (vc ? pc) contradicts the established
pc ? vc order and creates deadlock risks.

Fix the issue by moving the vc lock acquisition code from
mtk_cqdma_find_active_desc() to mtk_cqdma_tx_status(). Ensure the pc lock
is acquired before the vc lock in the calling function to maintain correct
locking hierarchy. Note that since mtk_cqdma_find_active_desc() is a
static function with only one caller (mtk_cqdma_tx_status()), this
modification safely eliminates the deadlock possibility without affecting
other components.

This possible bug is found by an experimental static analysis tool
developed by our team. This tool analyzes the locking APIs to extract
function pairs that can be concurrently executed, and then analyzes the
instructions in the paired functions to identify possible concurrency bugs
including deadlocks, data races and atomicity violations.

Fixes: b1f01e48df5a ("dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC")
Cc: stable at vger.kernel.org
Signed-off-by: Qiu-ji Chen <chenqiuji666 at gmail.com>
---
V2:
Revised the fix approach and updated the description to address the
reduced protection scope of the vc lock in the V1 solution.
---
 drivers/dma/mediatek/mtk-cqdma.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index d5ddb4e30e71..e35271ac1eed 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -422,13 +422,10 @@ static struct virt_dma_desc *mtk_cqdma_find_active_desc(struct dma_chan *c,
 	struct virt_dma_desc *vd;
 	unsigned long flags;
 
-	spin_lock_irqsave(&cvc->pc->lock, flags);
 	list_for_each_entry(vd, &cvc->pc->queue, node)
 		if (vd->tx.cookie == cookie) {
-			spin_unlock_irqrestore(&cvc->pc->lock, flags);
 			return vd;
 		}
-	spin_unlock_irqrestore(&cvc->pc->lock, flags);
 
 	list_for_each_entry(vd, &cvc->vc.desc_issued, node)
 		if (vd->tx.cookie == cookie)
@@ -452,9 +449,11 @@ static enum dma_status mtk_cqdma_tx_status(struct dma_chan *c,
 	if (ret == DMA_COMPLETE || !txstate)
 		return ret;
 
+	spin_lock_irqsave(&cvc->pc->lock, flags);
 	spin_lock_irqsave(&cvc->vc.lock, flags);
 	vd = mtk_cqdma_find_active_desc(c, cookie);
 	spin_unlock_irqrestore(&cvc->vc.lock, flags);
+	spin_unlock_irqrestore(&cvc->pc->lock, flags);
 
 	if (vd) {
 		cvd = to_cqdma_vdesc(vd);
-- 
2.34.1



From angelogioacchino.delregno at collabora.com  Thu May  8 01:06:13 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Thu, 8 May 2025 10:06:13 +0200
Subject: [PATCH v2] dmaengine: mediatek: Fix a possible deadlock error in
 mtk_cqdma_tx_status()
In-Reply-To: <20250508073634.3719-1-chenqiuji666@gmail.com>
References: <20250508073634.3719-1-chenqiuji666@gmail.com>
Message-ID: <fede9d2d-6225-4760-8920-c5963665ca1e@collabora.com>

Il 08/05/25 09:36, Qiu-ji Chen ha scritto:
> Fix a potential deadlock bug. Observe that in the mtk-cqdma.c
> file, functions like mtk_cqdma_issue_pending() and
> mtk_cqdma_free_active_desc() properly acquire the pc lock before the vc
> lock when handling pc and vc fields. However, mtk_cqdma_tx_status()
> violates this order by first acquiring the vc lock before invoking
> mtk_cqdma_find_active_desc(), which subsequently takes the pc lock. This
> reversed locking sequence (vc ? pc) contradicts the established
> pc ? vc order and creates deadlock risks.
> 
> Fix the issue by moving the vc lock acquisition code from
> mtk_cqdma_find_active_desc() to mtk_cqdma_tx_status(). Ensure the pc lock
> is acquired before the vc lock in the calling function to maintain correct
> locking hierarchy. Note that since mtk_cqdma_find_active_desc() is a
> static function with only one caller (mtk_cqdma_tx_status()), this
> modification safely eliminates the deadlock possibility without affecting
> other components.
> 
> This possible bug is found by an experimental static analysis tool
> developed by our team. This tool analyzes the locking APIs to extract
> function pairs that can be concurrently executed, and then analyzes the
> instructions in the paired functions to identify possible concurrency bugs
> including deadlocks, data races and atomicity violations.
> 
> Fixes: b1f01e48df5a ("dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC")
> Cc: stable at vger.kernel.org
> Signed-off-by: Qiu-ji Chen <chenqiuji666 at gmail.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>



From angelogioacchino.delregno at collabora.com  Thu May  8 01:15:36 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Thu, 8 May 2025 10:15:36 +0200
Subject: [PATCH v2 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation
 board and Mafefile
In-Reply-To: <20250508063546.289115-4-sirius.wang@mediatek.com>
References: <20250508063546.289115-1-sirius.wang@mediatek.com>
 <20250508063546.289115-4-sirius.wang@mediatek.com>
Message-ID: <7abf1685-0dee-4ef4-8e8c-bc01509ed3e3@collabora.com>

Il 08/05/25 08:35, Sirius Wang ha scritto:
> Add mt8189 dts evaluation board and Mafefile
> 
> Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/Makefile       |   1 +
>   arch/arm64/boot/dts/mediatek/mt8189-evb.dts |  20 +
>   arch/arm64/boot/dts/mediatek/mt8189.dtsi    | 430 ++++++++++++++++++++
>   3 files changed, 451 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi
> 
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 3aa06476c6c0..ad2ac9e1bb79 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb
>   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb
>   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb
>   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8189-evb.dtb
>   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
>   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
>   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
> new file mode 100644
> index 000000000000..e5d9ce1b8e61
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
> @@ -0,0 +1,20 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2025 MediaTek Inc.
> + * Author: Sirius Wang <sirius.wang at mediatek.com>
> + */
> +/dts-v1/;
> +#include "mt8189.dtsi"
> +
> +/ {
> +	model = "MediaTek MT8189 evaluation board";
> +	compatible = "mediatek,mt8189-evb", "mediatek,mt8189";
> +
> +	chosen: chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
> new file mode 100644
> index 000000000000..50c7a3811e0f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
> @@ -0,0 +1,430 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2025 MediaTek Inc.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	compatible = "mediatek,mt8189";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	clk32k: oscillator-clk32k {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <32000>;
> +		clock-output-names = "clk32k";
> +	};
> +
> +	clk13m: oscillator-clk13m {
> +		compatible = "fixed-factor-clock";
> +		#clock-cells = <0>;
> +		clocks = <&clk26m>;
> +		clock-mult = <1>;
> +		clock-div = <2>;
> +		clock-output-names = "clk13m";
> +	};
> +
> +	clk26m: oscillator-clk26m {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <26000000>;
> +		clock-output-names = "clk26m";
> +	};
> +
> +	clk104m: oscillator-clk104m {
> +		compatible = "fixed-factor-clock";
> +		#clock-cells = <0>;
> +		clocks = <&clk26m>;
> +		clock-mult = <4>;
> +		clock-div = <1>;
> +		clock-output-names = "clk104m";
> +	};

ulposc and ulposc3 go here.

> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a55";
> +			reg = <0x000>;
> +			enable-method = "psci";
> +			clock-frequency = <2000000000>;
> +			capacity-dmips-mhz = <742>;
> +			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
> +					  <&cpu_system_vcore>, <&cpu_s2idle>;
> +			i-cache-size = <32768>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <128>;
> +			d-cache-size = <32768>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2_0>;
> +			performance-domains = <&performance 0>;
> +			#cooling-cells = <2>;
> +		};
> +
> +		cpu1: cpu at 100 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a55";
> +			reg = <0x100>;
> +			enable-method = "psci";
> +			clock-frequency = <2000000000>;
> +			capacity-dmips-mhz = <742>;
> +			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
> +					  <&cpu_system_vcore>, <&cpu_s2idle>;
> +			i-cache-size = <32768>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <128>;
> +			d-cache-size = <32768>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2_0>;
> +			performance-domains = <&performance 0>;
> +			#cooling-cells = <2>;
> +		};
> +
> +		cpu2: cpu at 200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a55";
> +			reg = <0x200>;
> +			enable-method = "psci";
> +			clock-frequency = <2000000000>;
> +			capacity-dmips-mhz = <742>;
> +			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
> +					  <&cpu_system_vcore>, <&cpu_s2idle>;
> +			i-cache-size = <32768>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <128>;
> +			d-cache-size = <32768>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2_0>;
> +			performance-domains = <&performance 0>;
> +			#cooling-cells = <2>;
> +		};
> +
> +		cpu3: cpu at 300 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a55";
> +			reg = <0x300>;
> +			enable-method = "psci";
> +			clock-frequency = <2000000000>;
> +			capacity-dmips-mhz = <742>;
> +			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
> +					  <&cpu_system_vcore>, <&cpu_s2idle>;
> +			i-cache-size = <32768>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <128>;
> +			d-cache-size = <32768>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2_0>;
> +			performance-domains = <&performance 0>;
> +			#cooling-cells = <2>;
> +		};
> +
> +		cpu4: cpu at 400 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a55";
> +			reg = <0x400>;
> +			enable-method = "psci";
> +			clock-frequency = <2000000000>;
> +			capacity-dmips-mhz = <742>;
> +			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
> +					  <&cpu_system_vcore>, <&cpu_s2idle>;
> +			i-cache-size = <32768>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <128>;
> +			d-cache-size = <32768>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2_0>;
> +			performance-domains = <&performance 0>;
> +			#cooling-cells = <2>;
> +		};
> +
> +		cpu5: cpu at 500 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a55";
> +			reg = <0x500>;
> +			enable-method = "psci";
> +			clock-frequency = <2000000000>;
> +			capacity-dmips-mhz = <742>;
> +			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
> +					  <&cpu_system_vcore>, <&cpu_s2idle>;
> +			i-cache-size = <32768>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <128>;
> +			d-cache-size = <32768>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2_0>;
> +			performance-domains = <&performance 0>;
> +			#cooling-cells = <2>;
> +		};
> +
> +		cpu6: cpu at 600 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a78";
> +			reg = <0x600>;
> +			enable-method = "psci";
> +			clock-frequency = <3000000000>;
> +			capacity-dmips-mhz = <958>;
> +			cpu-idle-states = <&cpu_off_m>, <&cpu_cluster_off_m>, <&cpu_mcusys_off_m>,
> +					  <&cpu_system_vcore>, <&cpu_s2idle>;
> +			i-cache-size = <65536>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <65536>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <256>;
> +			next-level-cache = <&l2_1>;
> +			performance-domains = <&performance 1>;
> +			#cooling-cells = <2>;
> +		};
> +
> +		cpu7: cpu at 700 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a78";
> +			reg = <0x700>;
> +			enable-method = "psci";
> +			clock-frequency = <3000000000>;
> +			capacity-dmips-mhz = <958>;
> +			cpu-idle-states = <&cpu_off_m>, <&cpu_cluster_off_m>, <&cpu_mcusys_off_m>,
> +					  <&cpu_system_vcore>, <&cpu_s2idle>;
> +			i-cache-size = <65536>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <65536>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <256>;
> +			next-level-cache = <&l2_1>;
> +			performance-domains = <&performance 1>;
> +			#cooling-cells = <2>;
> +		};
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +				core2 {
> +					cpu = <&cpu2>;
> +				};
> +				core3 {
> +					cpu = <&cpu3>;
> +				};
> +				core4 {
> +					cpu = <&cpu4>;
> +				};
> +				core5 {
> +					cpu = <&cpu5>;
> +				};
> +			};
> +
> +			cluster1 {

Is this really an old-style dual cluster SoC, or is this ARM DynamIQ?

If this is the latter (and I believe it is), this SoC features a "single, fully
integrated cluster".


> +				core0 {
> +					cpu = <&cpu6>;
> +				};
> +				core1 {
> +					cpu = <&cpu7>;
> +				};
> +			};
> +		};
> +
> +		idle-states {
> +			entry-method = "psci";
> +
> +			cpu_off_l: cpu-off-l {
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x00010000>;
> +				local-timer-stop;
> +				entry-latency-us = <97>;
> +				exit-latency-us = <252>;
> +				min-residency-us = <6710>;
> +			};
> +
> +			cpu_off_m: cpu-off-m {

what does "m" stand for?

should this be cpu-off-b (where b==big and l==little) instead?

> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x00010000>;
> +				local-timer-stop;
> +				entry-latency-us = <53>;
> +				exit-latency-us = <143>;
> +				min-residency-us = <2120>;
> +			};
> +
> +			cpu_cluster_off_l: cpu-cluster-off-l {
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x01010001>;
> +				local-timer-stop;
> +				entry-latency-us = <109>;
> +				exit-latency-us = <325>;
> +				min-residency-us = <6710>;
> +			};
> +
> +			cpu_cluster_off_m: cpu-cluster-off-m {
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x01010001>;
> +				local-timer-stop;
> +				entry-latency-us = <59>;
> +				exit-latency-us = <188>;
> +				min-residency-us = <2120>;
> +			};
> +
> +			cpu_mcusys_off_l: cpu-mcusys-off-l {
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x02010007>;
> +				local-timer-stop;
> +				entry-latency-us = <1357>;
> +				exit-latency-us = <835>;
> +				min-residency-us = <6710>;
> +			};
> +
> +			cpu_mcusys_off_m: cpu-mcusys-off-m {
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x02010007>;
> +				local-timer-stop;
> +				entry-latency-us = <1202>;
> +				exit-latency-us = <679>;
> +				min-residency-us = <2120>;
> +			};
> +
> +			cpu_system_vcore: cpu-system-vcore {
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x020100ff>;
> +				local-timer-stop;
> +				entry-latency-us = <940>;
> +				exit-latency-us = <3500>;
> +				min-residency-us = <35200>;
> +			};
> +
> +			cpu_s2idle: cpu-s2idle {
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x020180ff>;
> +				local-timer-stop;
> +				entry-latency-us = <10000>;
> +				exit-latency-us = <10000>;
> +				min-residency-us = <4294967295>;
> +			};
> +		};
> +
> +		l2_0: l2-cache0 {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-size = <131072>;
> +			cache-line-size = <64>;
> +			cache-sets = <512>;
> +			next-level-cache = <&l3_0>;
> +			cache-unified;
> +		};
> +
> +		l2_1: l2-cache1 {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-size = <262144>;
> +			cache-line-size = <64>;
> +			cache-sets = <512>;
> +			next-level-cache = <&l3_0>;
> +			cache-unified;
> +		};
> +
> +		l3_0: l3-cache {
> +			compatible = "cache";
> +			cache-level = <3>;
> +			cache-size = <1048576>;
> +			cache-line-size = <64>;
> +			cache-sets = <2048>;
> +			cache-unified;
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};
> +
> +	memory: memory at 40000000 {
> +		device_type = "memory";
> +		reg = <0 0x40000000 0 0xC0000000>;
> +	};
> +

psci goes here

Regards,
Angelo

> +	timer: timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
> +
> +		performance: performance-controller at 11bc10 {
> +			compatible = "mediatek,cpufreq-hw";
> +			reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
> +			#performance-domain-cells = <1>;
> +		};
> +
> +		gic: interrupt-controller at c000000 {
> +			compatible = "arm,gic-v3";
> +			#interrupt-cells = <4>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			interrupt-controller;
> +			reg = <0 0xc000000 0 0x40000>, /* distributor */
> +			      <0 0xc040000 0 0x200000>; /* redistributor */
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> +
> +			ppi-partitions {
> +				ppi_cluster0: interrupt-partition-0 {
> +					affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
> +				};
> +
> +				ppi_cluster1: interrupt-partition-1 {
> +					affinity = <&cpu6 &cpu7>;
> +				};
> +			};
> +		};
> +
> +		uart0: serial at 11001000 {
> +			compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart";
> +			reg = <0 0x11001000 0 0x1000>;
> +			interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&clk26m>, <&clk26m>;
> +			clock-names = "baud", "bus";
> +			status = "disabled";
> +		};
> +	};
> +
> +	ulposc: oscillator-ulposc {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <520000000>;
> +		clock-output-names = "ulposc";
> +	};
> +
> +	ulposc3: oscillator-ulposc3 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <26000000>;
> +		clock-output-names = "ulposc3";
> +	};
> +};




From angelogioacchino.delregno at collabora.com  Thu May  8 01:15:38 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Thu, 8 May 2025 10:15:38 +0200
Subject: [PATCH v2 2/3] dt-bindings: serial: mediatek,uart: Add compatible
 for MT8189
In-Reply-To: <20250508063546.289115-3-sirius.wang@mediatek.com>
References: <20250508063546.289115-1-sirius.wang@mediatek.com>
 <20250508063546.289115-3-sirius.wang@mediatek.com>
Message-ID: <fe72f05e-6a79-4240-8cf5-7a20e094aa46@collabora.com>

Il 08/05/25 08:35, Sirius Wang ha scritto:
> Add compatible string for serial on MT8189 SoC.
> 
> Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>



From angelogioacchino.delregno at collabora.com  Thu May  8 01:15:41 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Thu, 8 May 2025 10:15:41 +0200
Subject: [PATCH v2 1/3] dt-bindings: arm: Add compatible for MediaTek
 MT8189
In-Reply-To: <20250508063546.289115-2-sirius.wang@mediatek.com>
References: <20250508063546.289115-1-sirius.wang@mediatek.com>
 <20250508063546.289115-2-sirius.wang@mediatek.com>
Message-ID: <97ec1373-1662-49e5-aecd-407a2ab2c2aa@collabora.com>

Il 08/05/25 08:35, Sirius Wang ha scritto:
> This commit adds dt-binding documentation for the MediaTek MT8189
> reference board.
> 
> Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>




From angelogioacchino.delregno at collabora.com  Thu May  8 01:25:27 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Thu, 8 May 2025 10:25:27 +0200
Subject: [PATCH] ASoC: mediatek: mt8188-mt6359: Depend on MT6359_ACCDET
 set or disabled
In-Reply-To: <20250507-mt8188-mt6359-accdet-depend-v1-1-aad70ce62964@collabora.com>
References: <20250507-mt8188-mt6359-accdet-depend-v1-1-aad70ce62964@collabora.com>
Message-ID: <4b12cb42-a1fc-4687-a5d0-07c2c822d778@collabora.com>

Il 07/05/25 22:14, N?colas F. R. A. Prado ha scritto:
> Commit 0116a7d84b32 ("ASoC: mediatek: mt6359: Add stub for
> mt6359_accdet_enable_jack_detect") added a stub for
> mt6359_accdet_enable_jack_detect() in order to allow the mt8188-mt6359
> driver to be enabled without requiring the mt6359-accdet to also be
> enabled, since it is not always needed.
> 
> However, in the case that CONFIG_SND_SOC_MT8188_MT6359=y and
> CONFIG_SND_SOC_MT6359_ACCDET=m, a link error will happen, which commit
> b19fa45715ce ("ASoC: mediatek: mt8188-mt6359: select
> CONFIG_SND_SOC_MT6359_ACCDET") solved by selecting
> CONFIG_SND_SOC_MT6359_ACCDET.
> 
> In order to not require CONFIG_SND_SOC_MT6359_ACCDET as originally
> intended, but also prevent the link error, depend on ACCDET being
> enabled or disabled (which will force MT8188_MT6359=m if
> MT6359_ACCDET=m).
> 
> Fixes: f35d834d67ad ("ASoC: mediatek: mt8188-mt6359: Add accdet headset jack detect support")
> Fixes: b19fa45715ce ("ASoC: mediatek: mt8188-mt6359: select CONFIG_SND_SOC_MT6359_ACCDET")
> Suggested-by: Arnd Bergmann <arnd at kernel.org>
> Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>




From angelogioacchino.delregno at collabora.com  Thu May  8 01:34:45 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Thu, 8 May 2025 10:34:45 +0200
Subject: [PATCH 2/4] dt-bindings: iommu: mediatek: mt8195 Accept up to 5
 interrupts
In-Reply-To: <baeae909-4d12-4cbd-a063-7ad165304b96@kernel.org>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
 <20250505-mt8395-dtb-errors-v1-2-9c4714dcdcdb@collabora.com>
 <baeae909-4d12-4cbd-a063-7ad165304b96@kernel.org>
Message-ID: <ff8da58b-9e87-46d9-b4d2-4059ef05780d@collabora.com>

Il 08/05/25 08:03, Krzysztof Kozlowski ha scritto:
> On 05/05/2025 15:23, Julien Massot wrote:
>>
>> Fixes: 3b5838d1d82e3 ("arm64: dts: mt8195: Add iommu and smi nodes")
>> Signed-off-by: Julien Massot <julien.massot at collabora.com>
>> ---
>>   Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
>> index 75750c64157c868725c087500ac81be4e282c829..035941c2db32170e9a69a5363d8c05ef767bb251 100644
>> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
>> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
>> @@ -97,7 +97,8 @@ properties:
>>       maxItems: 1
>>   
>>     interrupts:
>> -    maxItems: 1
>> +    minItems: 1
>> +    maxItems: 5
>>   
> Every iommu or just some (as described in commit msg) can have 5
> interrupts? Looks you miss here proper constraints per variant.
> 
Technically, all of the IOMMUs can have more than one interrupt - but it's not
clear which one and why, as documentation is lacking.

Let's restrict this discussion to MT8195 anyway, as it's the only one declaring
those 5 interrupts...
...all of the IOMMUs declare just one, and mediatek,mt8195-iommu-infra declares 5.

P.S.: Nice catch!

Cheers,
Angelo


From mingyen.hsieh at mediatek.com  Thu May  8 01:55:34 2025
From: mingyen.hsieh at mediatek.com (Mingyen Hsieh)
Date: Thu, 8 May 2025 16:55:34 +0800
Subject: [PATCH v2] wifi: mt76: mt7925: fix missing hdr_trans_tlv command for broadcast wtbl
Message-ID: <20250508085534.305242-1-mingyen.hsieh@mediatek.com>

From: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>

The hdr_trans_tlv function call has been moved inside the conditional block
to ensure it is executed when info->enable is true.

Cc: stable at vger.kernel.org
Fixes: cb1353ef3473 ("wifi: mt76: mt7925: integrate *mlo_sta_cmd and *sta_cmd")
Signed-off-by: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
Tested-by: Niklas Schnelle <niks at kernel.org>
---
v2:
    add tested-by tag
---
 drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
index a42b584634ab..fd756f0d18f8 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
@@ -2183,14 +2183,14 @@ mt7925_mcu_sta_cmd(struct mt76_phy *phy,
 			mt7925_mcu_sta_mld_tlv(skb, info->vif, info->link_sta->sta);
 			mt7925_mcu_sta_eht_mld_tlv(skb, info->vif, info->link_sta->sta);
 		}
-
-		mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info->link_sta);
 	}
 
 	if (!info->enable) {
 		mt7925_mcu_sta_remove_tlv(skb);
 		mt76_connac_mcu_add_tlv(skb, STA_REC_MLD_OFF,
 					sizeof(struct tlv));
+	} else {
+		mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info->link_sta);
 	}
 
 	return mt76_mcu_skb_send_msg(dev, skb, info->cmd, true);
-- 
2.34.1



From Kyrie.Wu at mediatek.com  Thu May  8 02:01:33 2025
From: Kyrie.Wu at mediatek.com (=?utf-8?B?S3lyaWUgV3UgKOWQtOaZlyk=?=)
Date: Thu, 8 May 2025 09:01:33 +0000
Subject: [PATCH v3 01/12] dt-bindings: media: mediatek,jpeg: Add mediatek,
 mt8196-jpgdec compatible
In-Reply-To: <41e258daf6ffaf14c3330c95860d70c95f9b61a2.camel@mediatek.com>
References: <20250425085328.16929-1-kyrie.wu@mediatek.com>
	 <20250425085328.16929-2-kyrie.wu@mediatek.com>
	 <20250428-ambitious-deer-of-plenty-2a553a@kuoka>
	 <5b6e70181b417f1b25df6fc1838b0ad600e29e9c.camel@mediatek.com>
	 <2044b305-8786-49b9-82e2-aa294434c24e@kernel.org>
	 <41e258daf6ffaf14c3330c95860d70c95f9b61a2.camel@mediatek.com>
Message-ID: <874ba04ef5e06385667549c6e29c47450113bff5.camel@mediatek.com>

On Tue, 2025-04-29 at 16:25 +0800, Kyrie Wu wrote:
> On Tue, 2025-04-29 at 09:33 +0200, Krzysztof Kozlowski wrote:
> > External email : Please do not click links or open attachments
> > until
> > you have verified the sender or the content.
> > 
> > 
> > On 28/04/2025 10:19, Kyrie Wu (??) wrote:
> > > On Mon, 2025-04-28 at 09:04 +0200, Krzysztof Kozlowski wrote:
> > > > External email : Please do not click links or open attachments
> > > > until
> > > > you have verified the sender or the content.
> > > > 
> > > > 
> > > > On Fri, Apr 25, 2025 at 04:53:17PM GMT, Kyrie Wu wrote:
> > > > > Compared to the previous generation IC, the MT8196 uses SMMU
> > > > > instead of IOMMU and supports features such as dynamic
> > > > > voltage
> > > > > and frequency scaling. Therefore, add "mediatek,mt8196-
> > > > > jpgdec"
> > > > > compatible to the binding document.
> > > > > 
> > > > > Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
> > > > 
> > > > I gave you a link to the exact part of documentation about
> > > > prefixes
> > > > to
> > > > read. I do not see improvements, so I do not believe you read
> > > > it.
> > > > I
> > > > could
> > > > imagine people skip reading entire doc (who would listen to the
> > > > reviewer, right?), but if I give direct link to specific
> > > > chapter
> > > > and
> > > > still not following it, makes me feel quite dissapointed.
> > > > 
> > > > Best regards,
> > > > Krzysztof
> > > > 
> > > 
> > > Dear Krzysztof,
> > > 
> > > I would like to apologize to you again here. I am very sorry for
> > > wasting your precious time. I changed the subject from "dt-
> > > bindings:
> > > mediatek: XXX" to "dt-bindings: media: mediatek,jpeg: XXX" in V3.
> > > This
> > > change is based on your previous suggestion. Use this command,
> > > git
> > > log
> > > --oneline --
> > > Documentation/devicetree/bindings/media/, obtained. But this
> > > modification does not meet your requirements. Should I change the
> > > subject to "media: dt-bindings: mediatek,jpeg: XXX"?
> > > 
> > > Another question I need to ask you:
> > > MT8195 and MT8196 both have multi-core hardware architectures. Do
> > > we
> > > need to change the yaml file name from 'mediatek,mt8195-
> > > jpegenc.yaml'
> > > to 'mediatek,multi-core-jpegenc.yaml'? In my opinion, this is
> > > more
> > > appropriate. What is your suggestion?
> > 
> > I asked above about link to documentation. You ignored that part,
> > so
> > let's be specific:
> > 
> > Did you or did you not read the doc I linked last time?
> > 
> > Best regards,
> > Krzysztof
> 
> Dear Krzysztof,
> 
> I have read the following link you provided:
> 
> 
https://urldefense.com/v3/__https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html*i-for-patch-submitters__;Iw!!CTRNKA9wMg0ARbw!lYnGLcOBQIh9yQUyMcteKxvcKQv2_eSc4udxkDDWXikTyN8VcXyYDgGuK-8UZWxKE5Pmg3D5lvplcw$
> 
> How to add the prefix of the patch's subject, the link and command
> line
> you provided respectively introduce two different methods:
> 'media:dt-bindings:xxx' is the method provided in the link you
> provided;
> ?dt-bindings:media:xxx? is the information obtained from the command
> you provided;
> I have previously sent you an email asking how you would choose
> between
> the two (
> 
https://patchwork.kernel.org/project/linux-mediatek/patch/20250410063006.5313-3-kyrie.wu at mediatek.com/
> ). But you didn't reply. Therefore, I used the previously merged
> patch
> approach in V3:
> b15a5ce86383 dt-bindings: media: mediatek,jpeg: Relax IOMMU max item
> count
> My behavior has caused you inconvenience and I have misunderstood
> your
> instructions. I once again sincerely apologize to you. I hope you can
> understand and accept it.
> Finally, please give some correct guidance.
> 
> Thanks!
> 
> Regards,
> Kyrie.
> 
> 
Dear Krzysztof,

I'm terriably sorry to bother you again.
Could you please give more specific suggestions on this issue?
We apologize for any inconvenience caused to you.
Thank you!

Regards,
Kyrie.

From peter.wang at mediatek.com  Thu May  8 02:12:36 2025
From: peter.wang at mediatek.com (=?utf-8?B?UGV0ZXIgV2FuZyAo546L5L+h5Y+LKQ==?=)
Date: Thu, 8 May 2025 09:12:36 +0000
Subject: [PATCH v1] ufs: core: fix hwq_id type and value
In-Reply-To: <95235015-270d-451e-989c-9fddcbfcb97e@acm.org>
References: <20250506124038.4071609-1-peter.wang@mediatek.com>
	 <04fc1549-0fa6-4956-b522-df5fbc26100c@acm.org>
	 <6c9e983154ff8d9b4a1e63eb503e8b147303eb68.camel@mediatek.com>
	 <95235015-270d-451e-989c-9fddcbfcb97e@acm.org>
Message-ID: <5adddae8a46a5dd7e1feb6e0cc9bcd76e91d0611.camel@mediatek.com>

On Wed, 2025-05-07 at 12:26 -0700, Bart Van Assche wrote:
> 
> If you want to proceed with this patch, please make it clear in the
> patch description that this patch is a behavior change and not a bug
> fix.
> 
> Thanks,
> 
> Bart.

Hi Bart,

Okay, the commit message for the bug fix will be 
corrected in the next version.

Thanks
Peter



From peter.wang at mediatek.com  Thu May  8 02:18:15 2025
From: peter.wang at mediatek.com (peter.wang at mediatek.com)
Date: Thu, 8 May 2025 17:18:15 +0800
Subject: [PATCH v2] ufs: core: behavior change of hwq_id type and value
Message-ID: <20250508091914.307944-1-peter.wang@mediatek.com>

From: Peter Wang <peter.wang at mediatek.com>

Because the member id of struct ufs_hw_queue is u32 (hwq->id) and
the trace entry hwq_id is also u32, the type should be changed to u32.
If mcq is not supported, SDB mode only supports one hardware queue,
for which setting the hwq_id to 0 is more suitable.

Signed-off-by: Peter Wang <peter.wang at mediatek.com>
---
 drivers/ufs/core/ufshcd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 7735421e3991..14e4cfbcb9eb 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -432,7 +432,7 @@ static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
 	u8 opcode = 0, group_id = 0;
 	u32 doorbell = 0;
 	u32 intr;
-	int hwq_id = -1;
+	u32 hwq_id = 0;
 	struct ufshcd_lrb *lrbp = &hba->lrb[tag];
 	struct scsi_cmnd *cmd = lrbp->cmd;
 	struct request *rq = scsi_cmd_to_rq(cmd);
-- 
2.45.2



From arnd at arndb.de  Thu May  8 06:54:00 2025
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 08 May 2025 15:54:00 +0200
Subject: [PATCH] ASoC: mediatek: mt8188-mt6359: Depend on MT6359_ACCDET set or
 disabled
In-Reply-To: <20250507-mt8188-mt6359-accdet-depend-v1-1-aad70ce62964@collabora.com>
References: <20250507-mt8188-mt6359-accdet-depend-v1-1-aad70ce62964@collabora.com>
Message-ID: <518ffd4c-2ea1-4496-b0fd-399ea1db0f57@app.fastmail.com>

On Wed, May 7, 2025, at 22:14, N?colas F. R. A. Prado wrote:
> Commit 0116a7d84b32 ("ASoC: mediatek: mt6359: Add stub for
> mt6359_accdet_enable_jack_detect") added a stub for
> mt6359_accdet_enable_jack_detect() in order to allow the mt8188-mt6359
> driver to be enabled without requiring the mt6359-accdet to also be
> enabled, since it is not always needed.
>
> Fixes: f35d834d67ad ("ASoC: mediatek: mt8188-mt6359: Add accdet headset 
> jack detect support")
> Fixes: b19fa45715ce ("ASoC: mediatek: mt8188-mt6359: select 
> CONFIG_SND_SOC_MT6359_ACCDET")
> Suggested-by: Arnd Bergmann <arnd at kernel.org>
> Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From christophe.jaillet at wanadoo.fr  Thu May  8 07:30:06 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Thu, 8 May 2025 16:30:06 +0200
Subject: [PATCH] net: airoha: Fix an error handling path in airoha_probe()
In-Reply-To: <aAJFgqrOFL_xAqtW@lore-desk>
References: <f4a420f3a8b4a6fe72798f9774ec9aff2291522d.1744977434.git.christophe.jaillet@wanadoo.fr>
 <aAJFgqrOFL_xAqtW@lore-desk>
Message-ID: <f7386884-cf6f-451a-aa39-6ce26ca22832@wanadoo.fr>

Le 18/04/2025 ? 14:28, Lorenzo Bianconi a ?crit?:
>> If an error occurs after a successful airoha_hw_init() call,
>> airoha_ppe_deinit() needs to be called as already done in the remove
>> function.
>>
>> Fixes: 00a7678310fe ("net: airoha: Introduce flowtable offload support")
>> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
>> ---
>> Compile tested-only
>> ---
>>   drivers/net/ethernet/airoha/airoha_eth.c | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
>> index 69e523dd4186..252b32ceb064 100644
>> --- a/drivers/net/ethernet/airoha/airoha_eth.c
>> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
>> @@ -2631,6 +2631,8 @@ static int airoha_probe(struct platform_device *pdev)
>>   		}
>>   	}
>>   	free_netdev(eth->napi_dev);
>> +
>> +	airoha_ppe_deinit(eth);
>>   	platform_set_drvdata(pdev, NULL);
>>   
>>   	return err;
>> -- 
>> 2.49.0
>>
> 
> Hi Christophe,
> 
> I agree we are missing a airoha_ppe_deinit() call in the probe error path,
> but we should move it above after stopping the NAPI since if airoha_hw_init()
> fails we will undo the work done by airoha_ppe_init(). Something like:

Agreed.

I'll send a v2 with as a small series, because of another leak I found 
while looking at it.

And while at it, I'll propose a few clean-ups.

CJ


> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index 16c7896f931f..37d9678798d1 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -2959,6 +2959,7 @@ static int airoha_probe(struct platform_device *pdev)
>   error_napi_stop:
>   	for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
>   		airoha_qdma_stop_napi(&eth->qdma[i]);
> +	airoha_ppe_init(eth);
>   error_hw_cleanup:
>   	for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
>   		airoha_hw_cleanup(&eth->qdma[i]);
> 
> 
> Agree?
> 
> Regards,
> Lorenzo



From lee at kernel.org  Thu May  8 07:32:56 2025
From: lee at kernel.org (Lee Jones)
Date: Thu, 08 May 2025 15:32:56 +0100
Subject: (subset) [PATCH] leds: rgb: leds-mt6370-rgb: Improve
 definition of some struct linear_range
In-Reply-To: <1ce4245107e0a51dce502a007a69899bda018d5f.1746197460.git.christophe.jaillet@wanadoo.fr>
References: <1ce4245107e0a51dce502a007a69899bda018d5f.1746197460.git.christophe.jaillet@wanadoo.fr>
Message-ID: <174671477676.2472260.13790392166774211195.b4-ty@kernel.org>

On Fri, 02 May 2025 16:51:22 +0200, Christophe JAILLET wrote:
> Use LINEAR_RANGE() instead of hand-writing it. It is more robust, should
> the layout of the structure change one day.
> 
> 

Applied, thanks!

[1/1] leds: rgb: leds-mt6370-rgb: Improve definition of some struct linear_range
      commit: 4e055c846de470cb4a9bf4be0811c7d624785abc

--
Lee Jones [???]



From conor at kernel.org  Thu May  8 07:48:49 2025
From: conor at kernel.org (Conor Dooley)
Date: Thu, 8 May 2025 15:48:49 +0100
Subject: [PATCH v2 2/3] dt-bindings: serial: mediatek,uart: Add
 compatible for MT8189
In-Reply-To: <20250508063546.289115-3-sirius.wang@mediatek.com>
References: <20250508063546.289115-1-sirius.wang@mediatek.com>
 <20250508063546.289115-3-sirius.wang@mediatek.com>
Message-ID: <20250508-kisser-kiln-647bbdeb7e29@spud>

On Thu, May 08, 2025 at 02:35:41PM +0800, Sirius Wang wrote:
> Add compatible string for serial on MT8189 SoC.
> 
> Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>

Acked-by: Conor Dooley <conor.dooley at microchip.com>
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From christophe.jaillet at wanadoo.fr  Thu May  8 07:52:25 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Thu,  8 May 2025 16:52:25 +0200
Subject: [PATCH v2 1/4] net: airoha: Fix an error handling path in airoha_alloc_gdm_port()
Message-ID: <5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet@wanadoo.fr>

If register_netdev() fails, the error handling path of the probe will not
free the memory allocated by the previous airoha_metadata_dst_alloc() call
because port->dev->reg_state will not be NETREG_REGISTERED.

So, an explicit airoha_metadata_dst_free() call is needed in this case to
avoid a memory leak.

Fixes: af3cf757d5c9 ("net: airoha: Move DSA tag in DMA descriptor")
Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
---
Changes in v2:
  - New patch

Compile tested only.
---
 drivers/net/ethernet/airoha/airoha_eth.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 16c7896f931f..af8c4015938c 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2873,7 +2873,15 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
 	if (err)
 		return err;
 
-	return register_netdev(dev);
+	err = register_netdev(dev);
+	if (err)
+		goto free_metadata_dst;
+
+	return 0;
+
+free_metadata_dst:
+	airoha_metadata_dst_free(port);
+	return err;
 }
 
 static int airoha_probe(struct platform_device *pdev)
-- 
2.49.0



From christophe.jaillet at wanadoo.fr  Thu May  8 07:52:26 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Thu,  8 May 2025 16:52:26 +0200
Subject: [PATCH v2 2/4] net: airoha: Fix an error handling path in airoha_probe()
In-Reply-To: <5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <3791c95da3fa3c3bd2a942210e821d9301362128.1746715755.git.christophe.jaillet@wanadoo.fr>

If an error occurs after a successful airoha_hw_init() call,
airoha_ppe_deinit() needs to be called as already done in the remove
function.

Fixes: 00a7678310fe ("net: airoha: Introduce flowtable offload support")
Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
---
Changes in v2:
  - Call airoha_ppe_init() at the right place in the error handling path
    of the probe   [Lorenzo Bianconi]

Compile tested only.
---
 drivers/net/ethernet/airoha/airoha_eth.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index af8c4015938c..d435179875df 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2967,6 +2967,7 @@ static int airoha_probe(struct platform_device *pdev)
 error_napi_stop:
 	for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
 		airoha_qdma_stop_napi(&eth->qdma[i]);
+	airoha_ppe_init(eth);
 error_hw_cleanup:
 	for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
 		airoha_hw_cleanup(&eth->qdma[i]);
-- 
2.49.0



From christophe.jaillet at wanadoo.fr  Thu May  8 07:52:27 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Thu,  8 May 2025 16:52:27 +0200
Subject: [PATCH v2 3/4] net: airoha: Use for_each_child_of_node_scoped()
In-Reply-To: <5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <88143d6af26b32066c92b5ba81d8e08c55426ebe.1746715755.git.christophe.jaillet@wanadoo.fr>

Use for_each_child_of_node_scoped() to slightly simplify the code.

Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
---
Changes in v2:
  - New patch

Compile tested only.
---
 drivers/net/ethernet/airoha/airoha_eth.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index d435179875df..2335aa59b06f 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2886,7 +2886,6 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
 
 static int airoha_probe(struct platform_device *pdev)
 {
-	struct device_node *np;
 	struct airoha_eth *eth;
 	int i, err;
 
@@ -2948,7 +2947,7 @@ static int airoha_probe(struct platform_device *pdev)
 		airoha_qdma_start_napi(&eth->qdma[i]);
 
 	i = 0;
-	for_each_child_of_node(pdev->dev.of_node, np) {
+	for_each_child_of_node_scoped(pdev->dev.of_node, np) {
 		if (!of_device_is_compatible(np, "airoha,eth-mac"))
 			continue;
 
@@ -2956,10 +2955,8 @@ static int airoha_probe(struct platform_device *pdev)
 			continue;
 
 		err = airoha_alloc_gdm_port(eth, np, i++);
-		if (err) {
-			of_node_put(np);
+		if (err)
 			goto error_napi_stop;
-		}
 	}
 
 	return 0;
-- 
2.49.0



From christophe.jaillet at wanadoo.fr  Thu May  8 07:52:28 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Thu,  8 May 2025 16:52:28 +0200
Subject: [PATCH v2 4/4] net: airoha: Use dev_err_probe()
In-Reply-To: <5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <1b67aa9ea0245325c3779d32dde46cdf5c232db9.1746715755.git.christophe.jaillet@wanadoo.fr>

Use dev_err_probe() to slightly simplify the code.
It is less verbose, more informational and makes error logging more
consistent in the probe.

Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
---
Changes in v2:
  - New patch

Compile tested only.
---
 drivers/net/ethernet/airoha/airoha_eth.c | 21 +++++++++------------
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 2335aa59b06f..7404ee894467 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2896,10 +2896,9 @@ static int airoha_probe(struct platform_device *pdev)
 	eth->dev = &pdev->dev;
 
 	err = dma_set_mask_and_coherent(eth->dev, DMA_BIT_MASK(32));
-	if (err) {
-		dev_err(eth->dev, "failed configuring DMA mask\n");
-		return err;
-	}
+	if (err)
+		return dev_err_probe(eth->dev, err,
+				     "failed configuring DMA mask\n");
 
 	eth->fe_regs = devm_platform_ioremap_resource_byname(pdev, "fe");
 	if (IS_ERR(eth->fe_regs))
@@ -2912,10 +2911,9 @@ static int airoha_probe(struct platform_device *pdev)
 	err = devm_reset_control_bulk_get_exclusive(eth->dev,
 						    ARRAY_SIZE(eth->rsts),
 						    eth->rsts);
-	if (err) {
-		dev_err(eth->dev, "failed to get bulk reset lines\n");
-		return err;
-	}
+	if (err)
+		return dev_err_probe(eth->dev, err,
+				     "failed to get bulk reset lines\n");
 
 	eth->xsi_rsts[0].id = "xsi-mac";
 	eth->xsi_rsts[1].id = "hsi0-mac";
@@ -2925,10 +2923,9 @@ static int airoha_probe(struct platform_device *pdev)
 	err = devm_reset_control_bulk_get_exclusive(eth->dev,
 						    ARRAY_SIZE(eth->xsi_rsts),
 						    eth->xsi_rsts);
-	if (err) {
-		dev_err(eth->dev, "failed to get bulk xsi reset lines\n");
-		return err;
-	}
+	if (err)
+		return dev_err_probe(eth->dev, err,
+				     "failed to get bulk xsi reset lines\n");
 
 	eth->napi_dev = alloc_netdev_dummy(0);
 	if (!eth->napi_dev)
-- 
2.49.0



From lorenzo at kernel.org  Thu May  8 08:10:28 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Thu, 8 May 2025 17:10:28 +0200
Subject: [PATCH v2 2/4] net: airoha: Fix an error handling path in
 airoha_probe()
In-Reply-To: <3791c95da3fa3c3bd2a942210e821d9301362128.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet@wanadoo.fr>
 <3791c95da3fa3c3bd2a942210e821d9301362128.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <aBzJZCIvE9u_IAM-@lore-desk>

> If an error occurs after a successful airoha_hw_init() call,
> airoha_ppe_deinit() needs to be called as already done in the remove
> function.
> 
> Fixes: 00a7678310fe ("net: airoha: Introduce flowtable offload support")
> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
> ---
> Changes in v2:
>   - Call airoha_ppe_init() at the right place in the error handling path
>     of the probe   [Lorenzo Bianconi]
> 
> Compile tested only.
> ---
>  drivers/net/ethernet/airoha/airoha_eth.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index af8c4015938c..d435179875df 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -2967,6 +2967,7 @@ static int airoha_probe(struct platform_device *pdev)
>  error_napi_stop:
>  	for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
>  		airoha_qdma_stop_napi(&eth->qdma[i]);
> +	airoha_ppe_init(eth);

it was actually a typo in my previous email but this should be clearly
airoha_ppe_deinit().

Regards,
Lorenzo

>  error_hw_cleanup:
>  	for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
>  		airoha_hw_cleanup(&eth->qdma[i]);
> -- 
> 2.49.0
> 
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From bvanassche at acm.org  Thu May  8 08:20:41 2025
From: bvanassche at acm.org (Bart Van Assche)
Date: Thu, 8 May 2025 08:20:41 -0700
Subject: [PATCH v2] ufs: core: behavior change of hwq_id type and value
In-Reply-To: <20250508091914.307944-1-peter.wang@mediatek.com>
References: <20250508091914.307944-1-peter.wang@mediatek.com>
Message-ID: <b3fb4302-462d-4b92-a6cb-784000cd796c@acm.org>

On 5/8/25 2:18 AM, peter.wang at mediatek.com wrote:
> From: Peter Wang <peter.wang at mediatek.com>

Patch descriptions, including the subject, should use the imperative
mood. Anyway:

Reviewed-by: Bart Van Assche <bvanassche at acm.org>


From christophe.jaillet at wanadoo.fr  Thu May  8 08:21:08 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Thu, 8 May 2025 17:21:08 +0200
Subject: [PATCH v2 2/4] net: airoha: Fix an error handling path in
 airoha_probe()
In-Reply-To: <aBzJZCIvE9u_IAM-@lore-desk>
References: <5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet@wanadoo.fr>
 <3791c95da3fa3c3bd2a942210e821d9301362128.1746715755.git.christophe.jaillet@wanadoo.fr>
 <aBzJZCIvE9u_IAM-@lore-desk>
Message-ID: <23517507-bf1a-47fa-9a96-b27922e1e05f@wanadoo.fr>


Le 08/05/2025 ? 17:10, Lorenzo Bianconi a ?crit?:
>> If an error occurs after a successful airoha_hw_init() call,
>> airoha_ppe_deinit() needs to be called as already done in the remove
>> function.
>>
>> Fixes: 00a7678310fe ("net: airoha: Introduce flowtable offload support")
>> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
>> ---
>> Changes in v2:
>>    - Call airoha_ppe_init() at the right place in the error handling path
>>      of the probe   [Lorenzo Bianconi]
>>
>> Compile tested only.
>> ---
>>   drivers/net/ethernet/airoha/airoha_eth.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
>> index af8c4015938c..d435179875df 100644
>> --- a/drivers/net/ethernet/airoha/airoha_eth.c
>> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
>> @@ -2967,6 +2967,7 @@ static int airoha_probe(struct platform_device *pdev)
>>   error_napi_stop:
>>   	for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
>>   		airoha_qdma_stop_napi(&eth->qdma[i]);
>> +	airoha_ppe_init(eth);
> it was actually a typo in my previous email but this should be clearly
> airoha_ppe_deinit().

My bad!
Sorry for not spotting myself it.

We can really trust no one, nowadays ! :)

The good news is that my cocci script would have spotted it the next 
time I would have run it, because it would still find a 
airoha_ppe_deinit() in the remove function, but none in the probe.

I give you some time to review the other patches, and I'll a v3 later.

CJ

>
> Regards,
> Lorenzo
>
>>   error_hw_cleanup:
>>   	for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
>>   		airoha_hw_cleanup(&eth->qdma[i]);
>> -- 
>> 2.49.0
>>


From lorenzo at kernel.org  Thu May  8 08:31:54 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Thu, 8 May 2025 17:31:54 +0200
Subject: [PATCH v2 1/4] net: airoha: Fix an error handling path in
 airoha_alloc_gdm_port()
In-Reply-To: <5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <aBzOaiU6Ac3ZTU-4@lore-desk>

> If register_netdev() fails, the error handling path of the probe will not
> free the memory allocated by the previous airoha_metadata_dst_alloc() call
> because port->dev->reg_state will not be NETREG_REGISTERED.
> 
> So, an explicit airoha_metadata_dst_free() call is needed in this case to
> avoid a memory leak.
> 
> Fixes: af3cf757d5c9 ("net: airoha: Move DSA tag in DMA descriptor")
> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
> ---
> Changes in v2:
>   - New patch
> 
> Compile tested only.
> ---
>  drivers/net/ethernet/airoha/airoha_eth.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index 16c7896f931f..af8c4015938c 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -2873,7 +2873,15 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
>  	if (err)
>  		return err;
>  
> -	return register_netdev(dev);
> +	err = register_netdev(dev);
> +	if (err)
> +		goto free_metadata_dst;
> +
> +	return 0;
> +
> +free_metadata_dst:
> +	airoha_metadata_dst_free(port);
> +	return err;
>  }
>  
>  static int airoha_probe(struct platform_device *pdev)
> -- 
> 2.49.0
> 

I have not tested it but I think the right fix here would be something like:

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index b1ca8322d4eb..33f8926bba25 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2996,10 +2996,12 @@ static int airoha_probe(struct platform_device *pdev)
 	for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
 		struct airoha_gdm_port *port = eth->ports[i];
 
-		if (port && port->dev->reg_state == NETREG_REGISTERED) {
+		if (!port)
+			continue;
+
+		if (port->dev->reg_state == NETREG_REGISTERED)
 			unregister_netdev(port->dev);
-			airoha_metadata_dst_free(port);
-		}
+		airoha_metadata_dst_free(port);
 	}
 	free_netdev(eth->napi_dev);
 	platform_set_drvdata(pdev, NULL);

Regards,
Lorenzo
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From lorenzo at kernel.org  Thu May  8 08:43:53 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Thu, 8 May 2025 17:43:53 +0200
Subject: [PATCH v2 4/4] net: airoha: Use dev_err_probe()
In-Reply-To: <1b67aa9ea0245325c3779d32dde46cdf5c232db9.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet@wanadoo.fr>
 <1b67aa9ea0245325c3779d32dde46cdf5c232db9.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <aBzROQyQ_5oHmYr3@lore-desk>

On May 08, Christophe JAILLET wrote:
> Use dev_err_probe() to slightly simplify the code.
> It is less verbose, more informational and makes error logging more
> consistent in the probe.
> 
> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
> ---
> Changes in v2:
>   - New patch
> 
> Compile tested only.
> ---
>  drivers/net/ethernet/airoha/airoha_eth.c | 21 +++++++++------------
>  1 file changed, 9 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index 2335aa59b06f..7404ee894467 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -2896,10 +2896,9 @@ static int airoha_probe(struct platform_device *pdev)
>  	eth->dev = &pdev->dev;
>  
>  	err = dma_set_mask_and_coherent(eth->dev, DMA_BIT_MASK(32));
> -	if (err) {
> -		dev_err(eth->dev, "failed configuring DMA mask\n");
> -		return err;
> -	}
> +	if (err)
> +		return dev_err_probe(eth->dev, err,
> +				     "failed configuring DMA mask\n");

Can dma_set_mask_and_coherent() return -EPROBE_DEFER? The other parts are fine.

Regards,
Lorenzo

>  
>  	eth->fe_regs = devm_platform_ioremap_resource_byname(pdev, "fe");
>  	if (IS_ERR(eth->fe_regs))
> @@ -2912,10 +2911,9 @@ static int airoha_probe(struct platform_device *pdev)
>  	err = devm_reset_control_bulk_get_exclusive(eth->dev,
>  						    ARRAY_SIZE(eth->rsts),
>  						    eth->rsts);
> -	if (err) {
> -		dev_err(eth->dev, "failed to get bulk reset lines\n");
> -		return err;
> -	}
> +	if (err)
> +		return dev_err_probe(eth->dev, err,
> +				     "failed to get bulk reset lines\n");
>  
>  	eth->xsi_rsts[0].id = "xsi-mac";
>  	eth->xsi_rsts[1].id = "hsi0-mac";
> @@ -2925,10 +2923,9 @@ static int airoha_probe(struct platform_device *pdev)
>  	err = devm_reset_control_bulk_get_exclusive(eth->dev,
>  						    ARRAY_SIZE(eth->xsi_rsts),
>  						    eth->xsi_rsts);
> -	if (err) {
> -		dev_err(eth->dev, "failed to get bulk xsi reset lines\n");
> -		return err;
> -	}
> +	if (err)
> +		return dev_err_probe(eth->dev, err,
> +				     "failed to get bulk xsi reset lines\n");
>  
>  	eth->napi_dev = alloc_netdev_dummy(0);
>  	if (!eth->napi_dev)
> -- 
> 2.49.0
> 
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From christophe.jaillet at wanadoo.fr  Thu May  8 09:00:15 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Thu, 8 May 2025 18:00:15 +0200
Subject: [PATCH v2 4/4] net: airoha: Use dev_err_probe()
In-Reply-To: <aBzROQyQ_5oHmYr3@lore-desk>
References: <5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet@wanadoo.fr>
 <1b67aa9ea0245325c3779d32dde46cdf5c232db9.1746715755.git.christophe.jaillet@wanadoo.fr>
 <aBzROQyQ_5oHmYr3@lore-desk>
Message-ID: <aeab63d4-9740-4213-86c3-ca975762046e@wanadoo.fr>

Le 08/05/2025 ? 17:43, Lorenzo Bianconi a ?crit?:
> On May 08, Christophe JAILLET wrote:
>> Use dev_err_probe() to slightly simplify the code.
>> It is less verbose, more informational and makes error logging more
>> consistent in the probe.
>>
>> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
>> ---
>> Changes in v2:
>>    - New patch
>>
>> Compile tested only.
>> ---
>>   drivers/net/ethernet/airoha/airoha_eth.c | 21 +++++++++------------
>>   1 file changed, 9 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
>> index 2335aa59b06f..7404ee894467 100644
>> --- a/drivers/net/ethernet/airoha/airoha_eth.c
>> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
>> @@ -2896,10 +2896,9 @@ static int airoha_probe(struct platform_device *pdev)
>>   	eth->dev = &pdev->dev;
>>   
>>   	err = dma_set_mask_and_coherent(eth->dev, DMA_BIT_MASK(32));
>> -	if (err) {
>> -		dev_err(eth->dev, "failed configuring DMA mask\n");
>> -		return err;
>> -	}
>> +	if (err)
>> +		return dev_err_probe(eth->dev, err,
>> +				     "failed configuring DMA mask\n");
> 
> Can dma_set_mask_and_coherent() return -EPROBE_DEFER? The other parts are fine.
> 
> Regards,
> Lorenzo
> 

No, it can't, but using dev_err_probe() does not hurt.

Using dev_err_probe():
   - saves 1 LoC
   - is consistent in the function
   - log the error code in a human readable format
   - generate smaller binaries (can easily be checked with size)

So, even if "unneeded", I think it is still a improvement.

CJ


From christophe.jaillet at wanadoo.fr  Thu May  8 09:05:26 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Thu, 8 May 2025 18:05:26 +0200
Subject: [PATCH v2 1/4] net: airoha: Fix an error handling path in
 airoha_alloc_gdm_port()
In-Reply-To: <aBzOaiU6Ac3ZTU-4@lore-desk>
References: <5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet@wanadoo.fr>
 <aBzOaiU6Ac3ZTU-4@lore-desk>
Message-ID: <68149c51-ba75-4f0f-a86a-bd810d47d684@wanadoo.fr>

Le 08/05/2025 ? 17:31, Lorenzo Bianconi a ?crit?:
>> If register_netdev() fails, the error handling path of the probe will not
>> free the memory allocated by the previous airoha_metadata_dst_alloc() call
>> because port->dev->reg_state will not be NETREG_REGISTERED.
>>
>> So, an explicit airoha_metadata_dst_free() call is needed in this case to
>> avoid a memory leak.
>>
>> Fixes: af3cf757d5c9 ("net: airoha: Move DSA tag in DMA descriptor")
>> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
>> ---
>> Changes in v2:
>>    - New patch
>>
>> Compile tested only.
>> ---
>>   drivers/net/ethernet/airoha/airoha_eth.c | 10 +++++++++-
>>   1 file changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
>> index 16c7896f931f..af8c4015938c 100644
>> --- a/drivers/net/ethernet/airoha/airoha_eth.c
>> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
>> @@ -2873,7 +2873,15 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
>>   	if (err)
>>   		return err;
>>   
>> -	return register_netdev(dev);
>> +	err = register_netdev(dev);
>> +	if (err)
>> +		goto free_metadata_dst;
>> +
>> +	return 0;
>> +
>> +free_metadata_dst:
>> +	airoha_metadata_dst_free(port);
>> +	return err;
>>   }
>>   
>>   static int airoha_probe(struct platform_device *pdev)
>> -- 
>> 2.49.0
>>
> 
> I have not tested it but I think the right fix here would be something like:
> 
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index b1ca8322d4eb..33f8926bba25 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -2996,10 +2996,12 @@ static int airoha_probe(struct platform_device *pdev)
>   	for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
>   		struct airoha_gdm_port *port = eth->ports[i];
>   
> -		if (port && port->dev->reg_state == NETREG_REGISTERED) {
> +		if (!port)
> +			continue;

I think it works.

We can still have port non NULL and airoha_metadata_dst_alloc() which 
fails, but airoha_metadata_dst_free() seems to handle it correctly.

CJ


> +
> +		if (port->dev->reg_state == NETREG_REGISTERED)
>   			unregister_netdev(port->dev);
> -			airoha_metadata_dst_free(port);
> -		}
> +		airoha_metadata_dst_free(port);
>   	}
>   	free_netdev(eth->napi_dev);
>   	platform_set_drvdata(pdev, NULL);
> 
> Regards,
> Lorenzo



From niks at kernel.org  Thu May  8 15:05:57 2025
From: niks at kernel.org (Niklas Schnelle)
Date: Fri, 09 May 2025 00:05:57 +0200
Subject: [PATCH v2] wifi: mt76: mt7925: fix missing hdr_trans_tlv
 command for broadcast wtbl
In-Reply-To: <20250508085534.305242-1-mingyen.hsieh@mediatek.com>
References: <20250508085534.305242-1-mingyen.hsieh@mediatek.com>
Message-ID: <18a80b20916b2f7d73ea29cc67d1389662f9836b.camel@kernel.org>

On Thu, 2025-05-08 at 16:55 +0800, Mingyen Hsieh wrote:
> From: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
> 
> The hdr_trans_tlv function call has been moved inside the conditional block
> to ensure it is executed when info->enable is true.
> 
> Cc: stable at vger.kernel.org
> Fixes: cb1353ef3473 ("wifi: mt76: mt7925: integrate *mlo_sta_cmd and *sta_cmd")
> Signed-off-by: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
> Tested-by: Niklas Schnelle <niks at kernel.org>
> ---
> v2:
>     add tested-by tag
> 

Thanks for adding the tag, appreciate it. If I may add some stylistic
comments. I saw that this is one of your first independent upstream
patches so congratulations on that and even better it's an actual
proper fix. Well done!

One thing, I noticed though is that your commit message lacks context,
like this affecting IPv6 and multicast. Basically it just re-iterates
what I can already see in the code. It also doesn't use the recommended
imperative tone (see [0]). Moreover, I think this would be a good case
for using a Link: tag pointing to the thread[1] of Ben's bisect result.
Relatedly one could also add a Reported-by tag for Ben, I still fondly
remember getting a Reported-by mention long before I did my first
kernel contribution. This stuff is hard to balance with getting fixes
out there and I still screw up some detail with mails sometimes, but
we're all learning so wanted to give my 5 cents.

Thanks,
Niklas

[0]
https://www.kernel.org/doc/html/v4.12/process/submitting-patches.html#describe-your-changes
[1]
https://lore.kernel.org/lkml/EmWnO5b-acRH1TXbGnkx41eJw654vmCR-8_xMBaPMwexCnfkvKCdlU5u19CGbaapJ3KRu-l3B-tSUhf8CCQwL0odjo6Cd5YG5lvNeB-vfdg=@pm.me/

> ---
>  drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> index a42b584634ab..fd756f0d18f8 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> @@ -2183,14 +2183,14 @@ mt7925_mcu_sta_cmd(struct mt76_phy *phy,
>  			mt7925_mcu_sta_mld_tlv(skb, info->vif, info->link_sta->sta);
>  			mt7925_mcu_sta_eht_mld_tlv(skb, info->vif, info->link_sta->sta);
>  		}
> -
> -		mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info->link_sta);
>  	}
>  
>  	if (!info->enable) {
>  		mt7925_mcu_sta_remove_tlv(skb);
>  		mt76_connac_mcu_add_tlv(skb, STA_REC_MLD_OFF,
>  					sizeof(struct tlv));
> +	} else {
> +		mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info->link_sta);
>  	}
>  
>  	return mt76_mcu_skb_send_msg(dev, skb, info->cmd, true);


From mingyen.hsieh at mediatek.com  Thu May  8 18:04:20 2025
From: mingyen.hsieh at mediatek.com (Mingyen Hsieh)
Date: Fri, 9 May 2025 09:04:20 +0800
Subject: [PATCH v3] wifi: mt76: mt7925: fix missing hdr_trans_tlv command for broadcast wtbl
Message-ID: <20250509010421.403022-1-mingyen.hsieh@mediatek.com>

From: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>

Ensure that the hdr_trans_tlv command is included in the broadcast wtbl to
prevent the IPv6 and multicast packet from being dropped by the chip.

Cc: stable at vger.kernel.org
Fixes: cb1353ef3473 ("wifi: mt76: mt7925: integrate *mlo_sta_cmd and *sta_cmd")
Reported-by: Benjamin Xiao <fossben at pm.me>
Tested-by: Niklas Schnelle <niks at kernel.org>
Link: https://lore.kernel.org/lkml/EmWnO5b-acRH1TXbGnkx41eJw654vmCR-8_xMBaPMwexCnfkvKCdlU5u19CGbaapJ3KRu-l3B-tSUhf8CCQwL0odjo6Cd5YG5lvNeB-vfdg=@pm.me/
---
v2:
    add tested-by tag
v3:
    add more info in commit
---
 drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
index a42b584634ab..fd756f0d18f8 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
@@ -2183,14 +2183,14 @@ mt7925_mcu_sta_cmd(struct mt76_phy *phy,
 			mt7925_mcu_sta_mld_tlv(skb, info->vif, info->link_sta->sta);
 			mt7925_mcu_sta_eht_mld_tlv(skb, info->vif, info->link_sta->sta);
 		}
-
-		mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info->link_sta);
 	}
 
 	if (!info->enable) {
 		mt7925_mcu_sta_remove_tlv(skb);
 		mt76_connac_mcu_add_tlv(skb, STA_REC_MLD_OFF,
 					sizeof(struct tlv));
+	} else {
+		mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info->link_sta);
 	}
 
 	return mt76_mcu_skb_send_msg(dev, skb, info->cmd, true);
-- 
2.34.1



From peter.wang at mediatek.com  Thu May  8 19:15:37 2025
From: peter.wang at mediatek.com (=?utf-8?B?UGV0ZXIgV2FuZyAo546L5L+h5Y+LKQ==?=)
Date: Fri, 9 May 2025 02:15:37 +0000
Subject: [PATCH v2] ufs: core: behavior change of hwq_id type and value
In-Reply-To: <b3fb4302-462d-4b92-a6cb-784000cd796c@acm.org>
References: <20250508091914.307944-1-peter.wang@mediatek.com>
	 <b3fb4302-462d-4b92-a6cb-784000cd796c@acm.org>
Message-ID: <b5046a752b4deaa9f84c0b848eb2062d955d1d51.camel@mediatek.com>

On Thu, 2025-05-08 at 08:20 -0700, Bart Van Assche wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 5/8/25 2:18 AM, peter.wang at mediatek.com?wrote:
> > From: Peter Wang <peter.wang at mediatek.com>
> 
> Patch descriptions, including the subject, should use the imperative
> mood. Anyway:
> 
> Reviewed-by: Bart Van Assche <bvanassche at acm.org>


Hi Bart,

Okay, I will use the imperative mood for patch descriptions. 
Thanks for the review.

Peter

From peter.wang at mediatek.com  Thu May  8 19:16:12 2025
From: peter.wang at mediatek.com (peter.wang at mediatek.com)
Date: Fri, 9 May 2025 10:16:12 +0800
Subject: [PATCH v3] ufs: core: change hwq_id type and value
Message-ID: <20250509021648.412098-1-peter.wang@mediatek.com>

From: Peter Wang <peter.wang at mediatek.com>

Change the type of hwq_id to u32 because the member id of struct
ufs_hw_queue is u32 (hwq->id) and the trace entry hwq_id is also u32.
Set hwq_id to 0 if mcq is not supported, as SDB mode only supports
one hardware queue.

Signed-off-by: Peter Wang <peter.wang at mediatek.com>
Reviewed-by: Bart Van Assche <bvanassche at acm.org>
---
 drivers/ufs/core/ufshcd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 7735421e3991..14e4cfbcb9eb 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -432,7 +432,7 @@ static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
 	u8 opcode = 0, group_id = 0;
 	u32 doorbell = 0;
 	u32 intr;
-	int hwq_id = -1;
+	u32 hwq_id = 0;
 	struct ufshcd_lrb *lrbp = &hba->lrb[tag];
 	struct scsi_cmnd *cmd = lrbp->cmd;
 	struct request *rq = scsi_cmd_to_rq(cmd);
-- 
2.45.2



From kuba at kernel.org  Thu May  8 20:13:12 2025
From: kuba at kernel.org (Jakub Kicinski)
Date: Thu, 8 May 2025 20:13:12 -0700
Subject: [PATCH net-next 2/2] net: airoha: Add the capability to
 allocate hw buffers in SRAM
In-Reply-To: <20250507-airopha-desc-sram-v1-2-d42037431bfa@kernel.org>
References: <20250507-airopha-desc-sram-v1-0-d42037431bfa@kernel.org>
	<20250507-airopha-desc-sram-v1-2-d42037431bfa@kernel.org>
Message-ID: <20250508201312.078a0a37@kernel.org>

On Wed, 07 May 2025 19:48:46 +0200 Lorenzo Bianconi wrote:
> In order to improve packet processing and packet forwarding
> performances, EN7581 SoC supports allocating buffers for hw forwarding
> queues in SRAM instead of DRAM if available on the system.
> Rely on SRAM for buffers allocation if available on the system and use
> DRAM as fallback.

drivers/net/ethernet/airoha/airoha_eth.c:1113:30: warning: incorrect type in assignment (different address spaces)
drivers/net/ethernet/airoha/airoha_eth.c:1113:30:    expected void *q
drivers/net/ethernet/airoha/airoha_eth.c:1113:30:    got void [noderef] __iomem *
-- 
pw-bot: cr


From peter.wang at mediatek.com  Fri May  9 00:08:32 2025
From: peter.wang at mediatek.com (peter.wang at mediatek.com)
Date: Fri, 9 May 2025 15:08:32 +0800
Subject: [PATCH v1] ufs: core: support updating device command timeout
Message-ID: <20250509071029.446697-1-peter.wang@mediatek.com>

From: Peter Wang <peter.wang at mediatek.com>

The default device command timeout remains 1.5 seconds,
but platform drivers can override it if needed.

Some UFS device commands may timeout due to being blocked
by regular SCSI write commands. Therefore, the timeout
needs to be extended to 30 seconds, matching the SCSI write
command timeout.

Signed-off-by: Peter Wang <peter.wang at mediatek.com>
---
 drivers/ufs/core/ufshcd.c | 34 +++++++++++++++++++++++++++-------
 1 file changed, 27 insertions(+), 7 deletions(-)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 7735421e3991..09d9a16af339 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -63,7 +63,10 @@ enum {
 /* Query request retries */
 #define QUERY_REQ_RETRIES 3
 /* Query request timeout */
-#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
+enum {
+	QUERY_REQ_TIMEOUT_DEFAULT = 1500,
+	QUERY_REQ_TIMEOUT_MAX     = 30000
+};
 
 /* Advanced RPMB request timeout */
 #define ADVANCED_RPMB_REQ_TIMEOUT  3000 /* 3 seconds */
@@ -135,6 +138,23 @@ module_param_cb(uic_cmd_timeout, &uic_cmd_timeout_ops, &uic_cmd_timeout, 0644);
 MODULE_PARM_DESC(uic_cmd_timeout,
 		 "UFS UIC command timeout in milliseconds. Defaults to 500ms. Supported values range from 500ms to 2 seconds inclusively");
 
+static unsigned int dev_cmd_timeout = QUERY_REQ_TIMEOUT_DEFAULT;
+
+static int dev_cmd_timeout_set(const char *val, const struct kernel_param *kp)
+{
+	return param_set_uint_minmax(val, kp, QUERY_REQ_TIMEOUT_DEFAULT,
+				     QUERY_REQ_TIMEOUT_MAX);
+}
+
+static const struct kernel_param_ops dev_cmd_timeout_ops = {
+	.set = dev_cmd_timeout_set,
+	.get = param_get_uint,
+};
+
+module_param_cb(dev_cmd_timeout, &dev_cmd_timeout_ops, &dev_cmd_timeout, 0644);
+MODULE_PARM_DESC(dev_cmd_timeout,
+		 "UFS Device command timeout in milliseconds. Defaults to 1.5s. Supported values range from 1.5 to 30 seconds inclusively");
+
 #define ufshcd_toggle_vreg(_dev, _vreg, _on)				\
 	({                                                              \
 		int _ret;                                               \
@@ -3365,7 +3385,7 @@ int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
 	struct ufs_query_req *request = NULL;
 	struct ufs_query_res *response = NULL;
 	int err, selector = 0;
-	int timeout = QUERY_REQ_TIMEOUT;
+	int timeout = dev_cmd_timeout;
 
 	BUG_ON(!hba);
 
@@ -3462,7 +3482,7 @@ int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
 		goto out_unlock;
 	}
 
-	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
+	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, dev_cmd_timeout);
 
 	if (err) {
 		dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
@@ -3558,7 +3578,7 @@ static int __ufshcd_query_descriptor(struct ufs_hba *hba,
 		goto out_unlock;
 	}
 
-	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
+	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, dev_cmd_timeout);
 
 	if (err) {
 		dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
@@ -6020,7 +6040,7 @@ int ufshcd_read_device_lvl_exception_id(struct ufs_hba *hba, u64 *exception_id)
 
 	request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
 
-	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
+	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, dev_cmd_timeout);
 
 	if (err) {
 		dev_err(hba->dev, "%s: failed to read device level exception %d\n",
@@ -7245,7 +7265,7 @@ static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
 	 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
 	 * read the response directly ignoring all errors.
 	 */
-	ufshcd_issue_dev_cmd(hba, lrbp, tag, QUERY_REQ_TIMEOUT);
+	ufshcd_issue_dev_cmd(hba, lrbp, tag, dev_cmd_timeout);
 
 	/* just copy the upiu response as it is */
 	memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
@@ -8678,7 +8698,7 @@ static void ufshcd_set_timestamp_attr(struct ufs_hba *hba)
 
 	put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3);
 
-	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
+	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, dev_cmd_timeout);
 
 	if (err)
 		dev_err(hba->dev, "%s: failed to set timestamp %d\n",
-- 
2.45.2



From linus.walleij at linaro.org  Fri May  9 01:05:10 2025
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 9 May 2025 10:05:10 +0200
Subject: [PATCH 0/5] pinctrl: mediatek: convert GPIO chips to using new
 value setters
In-Reply-To: <20250425-gpiochip-set-rv-pinctrl-mediatek-v1-0-93e6a01855e7@linaro.org>
References: <20250425-gpiochip-set-rv-pinctrl-mediatek-v1-0-93e6a01855e7@linaro.org>
Message-ID: <CACRpkdat91GuhtkYw8mzzt2fgufktWCy4fnA5Dkos2=pWfWftw@mail.gmail.com>

On Fri, Apr 25, 2025 at 11:01?AM Bartosz Golaszewski <brgl at bgdev.pl> wrote:

> struct gpio_chip now has callbacks for setting line values that return
> an integer, allowing to indicate failures. We're in the process of
> converting all GPIO drivers to using the new API. This series converts
> all the mediatek pinctrl GPIO controllers.
>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski at linaro.org>

All 5 patches applied!

Yours,
Linus Walleij


From mingyen.hsieh at mediatek.com  Fri May  9 01:21:17 2025
From: mingyen.hsieh at mediatek.com (Mingyen Hsieh)
Date: Fri, 9 May 2025 16:21:17 +0800
Subject: [PATCH] wifi: mt76: mt7925: introduce thermal protection
Message-ID: <20250509082117.453819-1-mingyen.hsieh@mediatek.com>

From: Leon Yen <leon.yen at mediatek.com>

Add thermal protection to prevent the chip from possible overheating
due to prolonged high traffic and adverse operating conditions.

Signed-off-by: Leon Yen <leon.yen at mediatek.com>
Signed-off-by: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
---
 .../net/wireless/mediatek/mt76/mt7925/init.c  |  6 ++++++
 .../net/wireless/mediatek/mt76/mt7925/mcu.c   | 20 ++++++++++++++++++-
 .../net/wireless/mediatek/mt76/mt7925/mcu.h   |  1 +
 3 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/init.c b/drivers/net/wireless/mediatek/mt76/mt7925/init.c
index 79639be0d29a..2a83ff59a968 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/init.c
@@ -322,6 +322,12 @@ static void mt7925_init_work(struct work_struct *work)
 		return;
 	}
 
+	ret = mt7925_mcu_set_thermal_protect(dev);
+	if (ret) {
+		dev_err(dev->mt76.dev, "thermal protection enable failed\n");
+		return;
+	}
+
 	/* we support chip reset now */
 	dev->hw_init_done = true;
 
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
index d7116d8b020c..ca5d6b87c9da 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
@@ -1061,6 +1061,23 @@ int mt7925_mcu_set_deep_sleep(struct mt792x_dev *dev, bool enable)
 }
 EXPORT_SYMBOL_GPL(mt7925_mcu_set_deep_sleep);
 
+int mt7925_mcu_set_thermal_protect(struct mt792x_dev *dev)
+{
+	char cmd[64];
+	int ret = 0;
+
+	snprintf(cmd, sizeof(cmd), "ThermalProtGband %d %d %d %d %d %d %d %d %d %d",
+		 0, 100, 90, 80, 30, 1, 1, 115, 105, 5);
+	ret = mt7925_mcu_chip_config(dev, cmd);
+
+	snprintf(cmd, sizeof(cmd), "ThermalProtAband %d %d %d %d %d %d %d %d %d %d",
+		 1, 100, 90, 80, 30, 1, 1, 115, 105, 5);
+	ret |= mt7925_mcu_chip_config(dev, cmd);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(mt7925_mcu_set_thermal_protect);
+
 int mt7925_run_firmware(struct mt792x_dev *dev)
 {
 	int err;
@@ -3463,7 +3480,8 @@ int mt7925_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb,
 		else
 			uni_txd->option = MCU_CMD_UNI_EXT_ACK;
 
-		if (cmd == MCU_UNI_CMD(HIF_CTRL))
+		if (cmd == MCU_UNI_CMD(HIF_CTRL) ||
+		    cmd == MCU_UNI_CMD(CHIP_CONFIG))
 			uni_txd->option &= ~MCU_CMD_ACK;
 
 		goto exit;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.h b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.h
index a13b5ae42b00..22237c68cbf7 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.h
@@ -654,6 +654,7 @@ int mt7925_mcu_add_bss_info(struct mt792x_phy *phy,
 int mt7925_mcu_set_timing(struct mt792x_phy *phy,
 			  struct ieee80211_bss_conf *link_conf);
 int mt7925_mcu_set_deep_sleep(struct mt792x_dev *dev, bool enable);
+int mt7925_mcu_set_thermal_protect(struct mt792x_dev *dev);
 int mt7925_mcu_set_channel_domain(struct mt76_phy *phy);
 int mt7925_mcu_set_radio_en(struct mt792x_phy *phy, bool enable);
 int mt7925_mcu_set_chctx(struct mt76_phy *phy, struct mt76_vif_link *mvif,
-- 
2.34.1



From mingyen.hsieh at mediatek.com  Fri May  9 01:35:12 2025
From: mingyen.hsieh at mediatek.com (Mingyen Hsieh)
Date: Fri, 9 May 2025 16:35:12 +0800
Subject: [PATCH] wifi: mt76: mt7925: fix host interrupt register initialization
Message-ID: <20250509083512.455095-1-mingyen.hsieh@mediatek.com>

From: Michael Lo <michael.lo at mediatek.com>

ensure proper interrupt handling and aligns with the hardware spec by
updating the register offset for MT_WFDMA0_HOST_INT_ENA.

Cc: stable at vger.kernel.org
Fixes: c948b5da6bbe ("wifi: mt76: mt7925: add Mediatek Wi-Fi7 driver for mt7925 chips")
Signed-off-by: Michael Lo <michael.lo at mediatek.com>
Signed-off-by: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
---
 drivers/net/wireless/mediatek/mt76/mt7925/pci.c  | 3 ---
 drivers/net/wireless/mediatek/mt76/mt7925/regs.h | 2 +-
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/pci.c b/drivers/net/wireless/mediatek/mt76/mt7925/pci.c
index c7b5dc1dbb34..2e20ecc71207 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/pci.c
@@ -490,9 +490,6 @@ static int mt7925_pci_suspend(struct device *device)
 
 	/* disable interrupt */
 	mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
-	mt76_wr(dev, MT_WFDMA0_HOST_INT_DIS,
-		dev->irq_map->tx.all_complete_mask |
-		MT_INT_RX_DONE_ALL | MT_INT_MCU_CMD);
 
 	mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
 
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/regs.h b/drivers/net/wireless/mediatek/mt76/mt7925/regs.h
index 985794a40c1a..547489092c29 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/regs.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/regs.h
@@ -28,7 +28,7 @@
 #define MT_MDP_TO_HIF			0
 #define MT_MDP_TO_WM			1
 
-#define MT_WFDMA0_HOST_INT_ENA		MT_WFDMA0(0x228)
+#define MT_WFDMA0_HOST_INT_ENA		MT_WFDMA0(0x204)
 #define MT_WFDMA0_HOST_INT_DIS		MT_WFDMA0(0x22c)
 #define HOST_RX_DONE_INT_ENA4		BIT(12)
 #define HOST_RX_DONE_INT_ENA5		BIT(13)
-- 
2.34.1



From broonie at kernel.org  Fri May  9 01:58:44 2025
From: broonie at kernel.org (Mark Brown)
Date: Fri, 09 May 2025 17:58:44 +0900
Subject: [PATCH] ASoC: mediatek: mt8188-mt6359: Depend on MT6359_ACCDET
 set or disabled
In-Reply-To: <20250507-mt8188-mt6359-accdet-depend-v1-1-aad70ce62964@collabora.com>
References: <20250507-mt8188-mt6359-accdet-depend-v1-1-aad70ce62964@collabora.com>
Message-ID: <174678112414.29979.2917402833370390569.b4-ty@kernel.org>

On Wed, 07 May 2025 16:14:14 -0400, N?colas F. R. A. Prado wrote:
> Commit 0116a7d84b32 ("ASoC: mediatek: mt6359: Add stub for
> mt6359_accdet_enable_jack_detect") added a stub for
> mt6359_accdet_enable_jack_detect() in order to allow the mt8188-mt6359
> driver to be enabled without requiring the mt6359-accdet to also be
> enabled, since it is not always needed.
> 
> However, in the case that CONFIG_SND_SOC_MT8188_MT6359=y and
> CONFIG_SND_SOC_MT6359_ACCDET=m, a link error will happen, which commit
> b19fa45715ce ("ASoC: mediatek: mt8188-mt6359: select
> CONFIG_SND_SOC_MT6359_ACCDET") solved by selecting
> CONFIG_SND_SOC_MT6359_ACCDET.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[1/1] ASoC: mediatek: mt8188-mt6359: Depend on MT6359_ACCDET set or disabled
      commit: b7e3ec4e17e27420ebe976c7714881b64c28d63b

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark



From Sirius.Wang at mediatek.com  Fri May  9 02:03:49 2025
From: Sirius.Wang at mediatek.com (=?utf-8?B?U2lyaXVzIFdhbmcgKOeOi+eak+aYsSk=?=)
Date: Fri, 9 May 2025 09:03:49 +0000
Subject: [PATCH v2 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation
 board and Mafefile
In-Reply-To: <7abf1685-0dee-4ef4-8e8c-bc01509ed3e3@collabora.com>
References: <20250508063546.289115-1-sirius.wang@mediatek.com>
	 <20250508063546.289115-4-sirius.wang@mediatek.com>
	 <7abf1685-0dee-4ef4-8e8c-bc01509ed3e3@collabora.com>
Message-ID: <73c8b326d961ca6a00422b45454890a47e4c6d7b.camel@mediatek.com>

On Thu, 2025-05-08 at 10:15 +0200, AngeloGioacchino Del Regno wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Il 08/05/25 08:35, Sirius Wang ha scritto:
> > Add mt8189 dts evaluation board and Mafefile
> > 
> > Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>
> > ---
> > ? arch/arm64/boot/dts/mediatek/Makefile?????? |?? 1 +
> > ? arch/arm64/boot/dts/mediatek/mt8189-evb.dts |? 20 +
> > ? arch/arm64/boot/dts/mediatek/mt8189.dtsi??? | 430
> > ++++++++++++++++++++
> > ? 3 files changed, 451 insertions(+)
> > ? create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
> > ? create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 3aa06476c6c0..ad2ac9e1bb79 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-
> > ciri-sku4.dtb
> > ? dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb
> > ? dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb
> > ? dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8189-evb.dtb
> > ? dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
> > ? dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
> > ? dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
> > b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
> > new file mode 100644
> > index 000000000000..e5d9ce1b8e61
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
> > @@ -0,0 +1,20 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2025 MediaTek Inc.
> > + * Author: Sirius Wang <sirius.wang at mediatek.com>
> > + */
> > +/dts-v1/;
> > +#include "mt8189.dtsi"
> > +
> > +/ {
> > +???? model = "MediaTek MT8189 evaluation board";
> > +???? compatible = "mediatek,mt8189-evb", "mediatek,mt8189";
> > +
> > +???? chosen: chosen {
> > +???????????? stdout-path = "serial0:115200n8";
> > +???? };
> > +};
> > +
> > +&uart0 {
> > +???? status = "okay";
> > +};
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
> > new file mode 100644
> > index 000000000000..50c7a3811e0f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
> > @@ -0,0 +1,430 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (c) 2025 MediaTek Inc.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > +???? compatible = "mediatek,mt8189";
> > +???? interrupt-parent = <&gic>;
> > +???? #address-cells = <2>;
> > +???? #size-cells = <2>;
> > +
> > +???? aliases {
> > +???????????? serial0 = &uart0;
> > +???? };
> > +
> > +???? clk32k: oscillator-clk32k {
> > +???????????? compatible = "fixed-clock";
> > +???????????? #clock-cells = <0>;
> > +???????????? clock-frequency = <32000>;
> > +???????????? clock-output-names = "clk32k";
> > +???? };
> > +
> > +???? clk13m: oscillator-clk13m {
> > +???????????? compatible = "fixed-factor-clock";
> > +???????????? #clock-cells = <0>;
> > +???????????? clocks = <&clk26m>;
> > +???????????? clock-mult = <1>;
> > +???????????? clock-div = <2>;
> > +???????????? clock-output-names = "clk13m";
> > +???? };
> > +
> > +???? clk26m: oscillator-clk26m {
> > +???????????? compatible = "fixed-clock";
> > +???????????? #clock-cells = <0>;
> > +???????????? clock-frequency = <26000000>;
> > +???????????? clock-output-names = "clk26m";
> > +???? };
> > +
> > +???? clk104m: oscillator-clk104m {
> > +???????????? compatible = "fixed-factor-clock";
> > +???????????? #clock-cells = <0>;
> > +???????????? clocks = <&clk26m>;
> > +???????????? clock-mult = <4>;
> > +???????????? clock-div = <1>;
> > +???????????? clock-output-names = "clk104m";
> > +???? };
> 
> ulposc and ulposc3 go here.
It will be fixed on next version.
> 
> > +
> > +???? cpus {
> > +???????????? #address-cells = <1>;
> > +???????????? #size-cells = <0>;
> > +
> > +???????????? cpu0: cpu at 0 {
> > +???????????????????? device_type = "cpu";
> > +???????????????????? compatible = "arm,cortex-a55";
> > +???????????????????? reg = <0x000>;
> > +???????????????????? enable-method = "psci";
> > +???????????????????? clock-frequency = <2000000000>;
> > +???????????????????? capacity-dmips-mhz = <742>;
> > +???????????????????? cpu-idle-states = <&cpu_off_l>,
> > <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
> > +?????????????????????????????????????? <&cpu_system_vcore>,
> > <&cpu_s2idle>;
> > +???????????????????? i-cache-size = <32768>;
> > +???????????????????? i-cache-line-size = <64>;
> > +???????????????????? i-cache-sets = <128>;
> > +???????????????????? d-cache-size = <32768>;
> > +???????????????????? d-cache-line-size = <64>;
> > +???????????????????? d-cache-sets = <128>;
> > +???????????????????? next-level-cache = <&l2_0>;
> > +???????????????????? performance-domains = <&performance 0>;
> > +???????????????????? #cooling-cells = <2>;
> > +???????????? };
> > +
> > +???????????? cpu1: cpu at 100 {
> > +???????????????????? device_type = "cpu";
> > +???????????????????? compatible = "arm,cortex-a55";
> > +???????????????????? reg = <0x100>;
> > +???????????????????? enable-method = "psci";
> > +???????????????????? clock-frequency = <2000000000>;
> > +???????????????????? capacity-dmips-mhz = <742>;
> > +???????????????????? cpu-idle-states = <&cpu_off_l>,
> > <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
> > +?????????????????????????????????????? <&cpu_system_vcore>,
> > <&cpu_s2idle>;
> > +???????????????????? i-cache-size = <32768>;
> > +???????????????????? i-cache-line-size = <64>;
> > +???????????????????? i-cache-sets = <128>;
> > +???????????????????? d-cache-size = <32768>;
> > +???????????????????? d-cache-line-size = <64>;
> > +???????????????????? d-cache-sets = <128>;
> > +???????????????????? next-level-cache = <&l2_0>;
> > +???????????????????? performance-domains = <&performance 0>;
> > +???????????????????? #cooling-cells = <2>;
> > +???????????? };
> > +
> > +???????????? cpu2: cpu at 200 {
> > +???????????????????? device_type = "cpu";
> > +???????????????????? compatible = "arm,cortex-a55";
> > +???????????????????? reg = <0x200>;
> > +???????????????????? enable-method = "psci";
> > +???????????????????? clock-frequency = <2000000000>;
> > +???????????????????? capacity-dmips-mhz = <742>;
> > +???????????????????? cpu-idle-states = <&cpu_off_l>,
> > <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
> > +?????????????????????????????????????? <&cpu_system_vcore>,
> > <&cpu_s2idle>;
> > +???????????????????? i-cache-size = <32768>;
> > +???????????????????? i-cache-line-size = <64>;
> > +???????????????????? i-cache-sets = <128>;
> > +???????????????????? d-cache-size = <32768>;
> > +???????????????????? d-cache-line-size = <64>;
> > +???????????????????? d-cache-sets = <128>;
> > +???????????????????? next-level-cache = <&l2_0>;
> > +???????????????????? performance-domains = <&performance 0>;
> > +???????????????????? #cooling-cells = <2>;
> > +???????????? };
> > +
> > +???????????? cpu3: cpu at 300 {
> > +???????????????????? device_type = "cpu";
> > +???????????????????? compatible = "arm,cortex-a55";
> > +???????????????????? reg = <0x300>;
> > +???????????????????? enable-method = "psci";
> > +???????????????????? clock-frequency = <2000000000>;
> > +???????????????????? capacity-dmips-mhz = <742>;
> > +???????????????????? cpu-idle-states = <&cpu_off_l>,
> > <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
> > +?????????????????????????????????????? <&cpu_system_vcore>,
> > <&cpu_s2idle>;
> > +???????????????????? i-cache-size = <32768>;
> > +???????????????????? i-cache-line-size = <64>;
> > +???????????????????? i-cache-sets = <128>;
> > +???????????????????? d-cache-size = <32768>;
> > +???????????????????? d-cache-line-size = <64>;
> > +???????????????????? d-cache-sets = <128>;
> > +???????????????????? next-level-cache = <&l2_0>;
> > +???????????????????? performance-domains = <&performance 0>;
> > +???????????????????? #cooling-cells = <2>;
> > +???????????? };
> > +
> > +???????????? cpu4: cpu at 400 {
> > +???????????????????? device_type = "cpu";
> > +???????????????????? compatible = "arm,cortex-a55";
> > +???????????????????? reg = <0x400>;
> > +???????????????????? enable-method = "psci";
> > +???????????????????? clock-frequency = <2000000000>;
> > +???????????????????? capacity-dmips-mhz = <742>;
> > +???????????????????? cpu-idle-states = <&cpu_off_l>,
> > <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
> > +?????????????????????????????????????? <&cpu_system_vcore>,
> > <&cpu_s2idle>;
> > +???????????????????? i-cache-size = <32768>;
> > +???????????????????? i-cache-line-size = <64>;
> > +???????????????????? i-cache-sets = <128>;
> > +???????????????????? d-cache-size = <32768>;
> > +???????????????????? d-cache-line-size = <64>;
> > +???????????????????? d-cache-sets = <128>;
> > +???????????????????? next-level-cache = <&l2_0>;
> > +???????????????????? performance-domains = <&performance 0>;
> > +???????????????????? #cooling-cells = <2>;
> > +???????????? };
> > +
> > +???????????? cpu5: cpu at 500 {
> > +???????????????????? device_type = "cpu";
> > +???????????????????? compatible = "arm,cortex-a55";
> > +???????????????????? reg = <0x500>;
> > +???????????????????? enable-method = "psci";
> > +???????????????????? clock-frequency = <2000000000>;
> > +???????????????????? capacity-dmips-mhz = <742>;
> > +???????????????????? cpu-idle-states = <&cpu_off_l>,
> > <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
> > +?????????????????????????????????????? <&cpu_system_vcore>,
> > <&cpu_s2idle>;
> > +???????????????????? i-cache-size = <32768>;
> > +???????????????????? i-cache-line-size = <64>;
> > +???????????????????? i-cache-sets = <128>;
> > +???????????????????? d-cache-size = <32768>;
> > +???????????????????? d-cache-line-size = <64>;
> > +???????????????????? d-cache-sets = <128>;
> > +???????????????????? next-level-cache = <&l2_0>;
> > +???????????????????? performance-domains = <&performance 0>;
> > +???????????????????? #cooling-cells = <2>;
> > +???????????? };
> > +
> > +???????????? cpu6: cpu at 600 {
> > +???????????????????? device_type = "cpu";
> > +???????????????????? compatible = "arm,cortex-a78";
> > +???????????????????? reg = <0x600>;
> > +???????????????????? enable-method = "psci";
> > +???????????????????? clock-frequency = <3000000000>;
> > +???????????????????? capacity-dmips-mhz = <958>;
> > +???????????????????? cpu-idle-states = <&cpu_off_m>,
> > <&cpu_cluster_off_m>, <&cpu_mcusys_off_m>,
> > +?????????????????????????????????????? <&cpu_system_vcore>,
> > <&cpu_s2idle>;
> > +???????????????????? i-cache-size = <65536>;
> > +???????????????????? i-cache-line-size = <64>;
> > +???????????????????? i-cache-sets = <256>;
> > +???????????????????? d-cache-size = <65536>;
> > +???????????????????? d-cache-line-size = <64>;
> > +???????????????????? d-cache-sets = <256>;
> > +???????????????????? next-level-cache = <&l2_1>;
> > +???????????????????? performance-domains = <&performance 1>;
> > +???????????????????? #cooling-cells = <2>;
> > +???????????? };
> > +
> > +???????????? cpu7: cpu at 700 {
> > +???????????????????? device_type = "cpu";
> > +???????????????????? compatible = "arm,cortex-a78";
> > +???????????????????? reg = <0x700>;
> > +???????????????????? enable-method = "psci";
> > +???????????????????? clock-frequency = <3000000000>;
> > +???????????????????? capacity-dmips-mhz = <958>;
> > +???????????????????? cpu-idle-states = <&cpu_off_m>,
> > <&cpu_cluster_off_m>, <&cpu_mcusys_off_m>,
> > +?????????????????????????????????????? <&cpu_system_vcore>,
> > <&cpu_s2idle>;
> > +???????????????????? i-cache-size = <65536>;
> > +???????????????????? i-cache-line-size = <64>;
> > +???????????????????? i-cache-sets = <256>;
> > +???????????????????? d-cache-size = <65536>;
> > +???????????????????? d-cache-line-size = <64>;
> > +???????????????????? d-cache-sets = <256>;
> > +???????????????????? next-level-cache = <&l2_1>;
> > +???????????????????? performance-domains = <&performance 1>;
> > +???????????????????? #cooling-cells = <2>;
> > +???????????? };
> > +
> > +???????????? cpu-map {
> > +???????????????????? cluster0 {
> > +???????????????????????????? core0 {
> > +???????????????????????????????????? cpu = <&cpu0>;
> > +???????????????????????????? };
> > +???????????????????????????? core1 {
> > +???????????????????????????????????? cpu = <&cpu1>;
> > +???????????????????????????? };
> > +???????????????????????????? core2 {
> > +???????????????????????????????????? cpu = <&cpu2>;
> > +???????????????????????????? };
> > +???????????????????????????? core3 {
> > +???????????????????????????????????? cpu = <&cpu3>;
> > +???????????????????????????? };
> > +???????????????????????????? core4 {
> > +???????????????????????????????????? cpu = <&cpu4>;
> > +???????????????????????????? };
> > +???????????????????????????? core5 {
> > +???????????????????????????????????? cpu = <&cpu5>;
> > +???????????????????????????? };
> > +???????????????????? };
> > +
> > +???????????????????? cluster1 {
> 
> Is this really an old-style dual cluster SoC, or is this ARM DynamIQ?
> 
> If this is the latter (and I believe it is), this SoC features a
> "single, fully
> integrated cluster".
It will be fixed on next version.
> 
> 
> > +???????????????????????????? core0 {
> > +???????????????????????????????????? cpu = <&cpu6>;
> > +???????????????????????????? };
> > +???????????????????????????? core1 {
> > +???????????????????????????????????? cpu = <&cpu7>;
> > +???????????????????????????? };
> > +???????????????????? };
> > +???????????? };
> > +
> > +???????????? idle-states {
> > +???????????????????? entry-method = "psci";
> > +
> > +???????????????????? cpu_off_l: cpu-off-l {
> > +???????????????????????????? compatible = "arm,idle-state";
> > +???????????????????????????? arm,psci-suspend-param =
> > <0x00010000>;
> > +???????????????????????????? local-timer-stop;
> > +???????????????????????????? entry-latency-us = <97>;
> > +???????????????????????????? exit-latency-us = <252>;
> > +???????????????????????????? min-residency-us = <6710>;
> > +???????????????????? };
> > +
> > +???????????????????? cpu_off_m: cpu-off-m {
> 
> what does "m" stand for?
> 
> should this be cpu-off-b (where b==big and l==little) instead?
m for medium core.
It will be fixed to correct name b==big.
> 
> > +???????????????????????????? compatible = "arm,idle-state";
> > +???????????????????????????? arm,psci-suspend-param =
> > <0x00010000>;
> > +???????????????????????????? local-timer-stop;
> > +???????????????????????????? entry-latency-us = <53>;
> > +???????????????????????????? exit-latency-us = <143>;
> > +???????????????????????????? min-residency-us = <2120>;
> > +???????????????????? };
> > +
> > +???????????????????? cpu_cluster_off_l: cpu-cluster-off-l {
> > +???????????????????????????? compatible = "arm,idle-state";
> > +???????????????????????????? arm,psci-suspend-param =
> > <0x01010001>;
> > +???????????????????????????? local-timer-stop;
> > +???????????????????????????? entry-latency-us = <109>;
> > +???????????????????????????? exit-latency-us = <325>;
> > +???????????????????????????? min-residency-us = <6710>;
> > +???????????????????? };
> > +
> > +???????????????????? cpu_cluster_off_m: cpu-cluster-off-m {
> > +???????????????????????????? compatible = "arm,idle-state";
> > +???????????????????????????? arm,psci-suspend-param =
> > <0x01010001>;
> > +???????????????????????????? local-timer-stop;
> > +???????????????????????????? entry-latency-us = <59>;
> > +???????????????????????????? exit-latency-us = <188>;
> > +???????????????????????????? min-residency-us = <2120>;
> > +???????????????????? };
> > +
> > +???????????????????? cpu_mcusys_off_l: cpu-mcusys-off-l {
> > +???????????????????????????? compatible = "arm,idle-state";
> > +???????????????????????????? arm,psci-suspend-param =
> > <0x02010007>;
> > +???????????????????????????? local-timer-stop;
> > +???????????????????????????? entry-latency-us = <1357>;
> > +???????????????????????????? exit-latency-us = <835>;
> > +???????????????????????????? min-residency-us = <6710>;
> > +???????????????????? };
> > +
> > +???????????????????? cpu_mcusys_off_m: cpu-mcusys-off-m {
> > +???????????????????????????? compatible = "arm,idle-state";
> > +???????????????????????????? arm,psci-suspend-param =
> > <0x02010007>;
> > +???????????????????????????? local-timer-stop;
> > +???????????????????????????? entry-latency-us = <1202>;
> > +???????????????????????????? exit-latency-us = <679>;
> > +???????????????????????????? min-residency-us = <2120>;
> > +???????????????????? };
> > +
> > +???????????????????? cpu_system_vcore: cpu-system-vcore {
> > +???????????????????????????? compatible = "arm,idle-state";
> > +???????????????????????????? arm,psci-suspend-param =
> > <0x020100ff>;
> > +???????????????????????????? local-timer-stop;
> > +???????????????????????????? entry-latency-us = <940>;
> > +???????????????????????????? exit-latency-us = <3500>;
> > +???????????????????????????? min-residency-us = <35200>;
> > +???????????????????? };
> > +
> > +???????????????????? cpu_s2idle: cpu-s2idle {
> > +???????????????????????????? compatible = "arm,idle-state";
> > +???????????????????????????? arm,psci-suspend-param =
> > <0x020180ff>;
> > +???????????????????????????? local-timer-stop;
> > +???????????????????????????? entry-latency-us = <10000>;
> > +???????????????????????????? exit-latency-us = <10000>;
> > +???????????????????????????? min-residency-us = <4294967295>;
> > +???????????????????? };
> > +???????????? };
> > +
> > +???????????? l2_0: l2-cache0 {
> > +???????????????????? compatible = "cache";
> > +???????????????????? cache-level = <2>;
> > +???????????????????? cache-size = <131072>;
> > +???????????????????? cache-line-size = <64>;
> > +???????????????????? cache-sets = <512>;
> > +???????????????????? next-level-cache = <&l3_0>;
> > +???????????????????? cache-unified;
> > +???????????? };
> > +
> > +???????????? l2_1: l2-cache1 {
> > +???????????????????? compatible = "cache";
> > +???????????????????? cache-level = <2>;
> > +???????????????????? cache-size = <262144>;
> > +???????????????????? cache-line-size = <64>;
> > +???????????????????? cache-sets = <512>;
> > +???????????????????? next-level-cache = <&l3_0>;
> > +???????????????????? cache-unified;
> > +???????????? };
> > +
> > +???????????? l3_0: l3-cache {
> > +???????????????????? compatible = "cache";
> > +???????????????????? cache-level = <3>;
> > +???????????????????? cache-size = <1048576>;
> > +???????????????????? cache-line-size = <64>;
> > +???????????????????? cache-sets = <2048>;
> > +???????????????????? cache-unified;
> > +???????????? };
> > +???? };
> > +
> > +???? psci {
> > +???????????? compatible = "arm,psci-1.0";
> > +???????????? method = "smc";
> > +???? };
> > +
> > +???? memory: memory at 40000000 {
> > +???????????? device_type = "memory";
> > +???????????? reg = <0 0x40000000 0 0xC0000000>;
> > +???? };
> > +
> 
> psci goes here
It will be fixed on next version.
> 
> Regards,
> Angelo
> 
> > +???? timer: timer {
> > +???????????? compatible = "arm,armv8-timer";
> > +???????????? interrupt-parent = <&gic>;
> > +???????????? interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
> > +????????????????????????? <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
> > +????????????????????????? <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
> > +????????????????????????? <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
> > +???? };
> > +
> > +???? soc {
> > +???????????? compatible = "simple-bus";
> > +???????????? #address-cells = <2>;
> > +???????????? #size-cells = <2>;
> > +???????????? ranges;
> > +???????????? dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
> > +
> > +???????????? performance: performance-controller at 11bc10 {
> > +???????????????????? compatible = "mediatek,cpufreq-hw";
> > +???????????????????? reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0
> > 0x120>;
> > +???????????????????? #performance-domain-cells = <1>;
> > +???????????? };
> > +
> > +???????????? gic: interrupt-controller at c000000 {
> > +???????????????????? compatible = "arm,gic-v3";
> > +???????????????????? #interrupt-cells = <4>;
> > +???????????????????? #address-cells = <2>;
> > +???????????????????? #size-cells = <2>;
> > +???????????????????? interrupt-parent = <&gic>;
> > +???????????????????? interrupt-controller;
> > +???????????????????? reg = <0 0xc000000 0 0x40000>, /* distributor
> > */
> > +?????????????????????????? <0 0xc040000 0 0x200000>; /*
> > redistributor */
> > +???????????????????? interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +
> > +???????????????????? ppi-partitions {
> > +???????????????????????????? ppi_cluster0: interrupt-partition-0 {
> > +???????????????????????????????????? affinity = <&cpu0 &cpu1 &cpu2
> > &cpu3 &cpu4 &cpu5>;
> > +???????????????????????????? };
> > +
> > +???????????????????????????? ppi_cluster1: interrupt-partition-1 {
> > +???????????????????????????????????? affinity = <&cpu6 &cpu7>;
> > +???????????????????????????? };
> > +???????????????????? };
> > +???????????? };
> > +
> > +???????????? uart0: serial at 11001000 {
> > +???????????????????? compatible = "mediatek,mt8189-uart",
> > "mediatek,mt6577-uart";
> > +???????????????????? reg = <0 0x11001000 0 0x1000>;
> > +???????????????????? interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +???????????????????? clocks = <&clk26m>, <&clk26m>;
> > +???????????????????? clock-names = "baud", "bus";
> > +???????????????????? status = "disabled";
> > +???????????? };
> > +???? };
> > +
> > +???? ulposc: oscillator-ulposc {
> > +???????????? compatible = "fixed-clock";
> > +???????????? #clock-cells = <0>;
> > +???????????? clock-frequency = <520000000>;
> > +???????????? clock-output-names = "ulposc";
> > +???? };
> > +
> > +???? ulposc3: oscillator-ulposc3 {
> > +???????????? compatible = "fixed-clock";
> > +???????????? #clock-cells = <0>;
> > +???????????? clock-frequency = <26000000>;
> > +???????????? clock-output-names = "ulposc3";
> > +???? };
> > +};
> 
> 
Thanks for your review.

Regards,
Sirius

From jianqi.ren.cn at windriver.com  Fri May  9 02:26:03 2025
From: jianqi.ren.cn at windriver.com (jianqi.ren.cn at windriver.com)
Date: Fri, 9 May 2025 17:26:03 +0800
Subject: [PATCH 5.10.y] media: mtk-vcodec: potential null pointer deference in SCP
Message-ID: <20250509092603.3242559-1-jianqi.ren.cn@windriver.com>

From: Fullway Wang <fullwaywang at outlook.com>

[ Upstream commit 53dbe08504442dc7ba4865c09b3bbf5fe849681b ]

The return value of devm_kzalloc() needs to be checked to avoid
NULL pointer deference. This is similar to CVE-2022-3113.

Link: https://lore.kernel.org/linux-media/PH7PR20MB5925094DAE3FD750C7E39E01BF712 at PH7PR20MB5925.namprd20.prod.outlook.com
Signed-off-by: Fullway Wang <fullwaywang at outlook.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab at kernel.org>
[Minor conflict resolved due to code context change.]
Signed-off-by: Jianqi Ren <jianqi.ren.cn at windriver.com>
Signed-off-by: He Zhe <zhe.he at windriver.com>
---
Verified the build test
---
 drivers/media/platform/mtk-vcodec/mtk_vcodec_fw_scp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_fw_scp.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_fw_scp.c
index d8e66b645bd8..27f08b1d34d1 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_fw_scp.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_fw_scp.c
@@ -65,6 +65,8 @@ struct mtk_vcodec_fw *mtk_vcodec_fw_scp_init(struct mtk_vcodec_dev *dev)
 	}
 
 	fw = devm_kzalloc(&dev->plat_dev->dev, sizeof(*fw), GFP_KERNEL);
+	if (!fw)
+		return ERR_PTR(-ENOMEM);
 	fw->type = SCP;
 	fw->ops = &mtk_vcodec_rproc_msg;
 	fw->scp = scp;
-- 
2.34.1



From jianqi.ren.cn at windriver.com  Fri May  9 02:28:05 2025
From: jianqi.ren.cn at windriver.com (jianqi.ren.cn at windriver.com)
Date: Fri, 9 May 2025 17:28:05 +0800
Subject: [PATCH 5.15.y] media: mtk-vcodec: potential null pointer deference in SCP
Message-ID: <20250509092805.3242802-1-jianqi.ren.cn@windriver.com>

From: Fullway Wang <fullwaywang at outlook.com>

[ Upstream commit 53dbe08504442dc7ba4865c09b3bbf5fe849681b ]

The return value of devm_kzalloc() needs to be checked to avoid
NULL pointer deference. This is similar to CVE-2022-3113.

Link: https://lore.kernel.org/linux-media/PH7PR20MB5925094DAE3FD750C7E39E01BF712 at PH7PR20MB5925.namprd20.prod.outlook.com
Signed-off-by: Fullway Wang <fullwaywang at outlook.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab at kernel.org>
[Minor conflict resolved due to code context change.]
Signed-off-by: Jianqi Ren <jianqi.ren.cn at windriver.com>
Signed-off-by: He Zhe <zhe.he at windriver.com>
---
Verified the build test
---
 drivers/media/platform/mtk-vcodec/mtk_vcodec_fw_scp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_fw_scp.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_fw_scp.c
index d8e66b645bd8..27f08b1d34d1 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_fw_scp.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_fw_scp.c
@@ -65,6 +65,8 @@ struct mtk_vcodec_fw *mtk_vcodec_fw_scp_init(struct mtk_vcodec_dev *dev)
 	}
 
 	fw = devm_kzalloc(&dev->plat_dev->dev, sizeof(*fw), GFP_KERNEL);
+	if (!fw)
+		return ERR_PTR(-ENOMEM);
 	fw->type = SCP;
 	fw->ops = &mtk_vcodec_rproc_msg;
 	fw->scp = scp;
-- 
2.34.1



From niks at kernel.org  Fri May  9 02:40:36 2025
From: niks at kernel.org (Niklas Schnelle)
Date: Fri, 09 May 2025 11:40:36 +0200
Subject: [PATCH v3] wifi: mt76: mt7925: fix missing hdr_trans_tlv
 command for broadcast wtbl
In-Reply-To: <20250509010421.403022-1-mingyen.hsieh@mediatek.com>
References: <20250509010421.403022-1-mingyen.hsieh@mediatek.com>
Message-ID: <534b9a609564c8bb6d90805dca7fb1d3a45a3abf.camel@kernel.org>

On Fri, 2025-05-09 at 09:04 +0800, Mingyen Hsieh wrote:
> From: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
> 
> Ensure that the hdr_trans_tlv command is included in the broadcast wtbl to
> prevent the IPv6 and multicast packet from being dropped by the chip.
> 
> Cc: stable at vger.kernel.org
> Fixes: cb1353ef3473 ("wifi: mt76: mt7925: integrate *mlo_sta_cmd and *sta_cmd")
> Reported-by: Benjamin Xiao <fossben at pm.me>
> Tested-by: Niklas Schnelle <niks at kernel.org>
> Link: https://lore.kernel.org/lkml/EmWnO5b-acRH1TXbGnkx41eJw654vmCR-8_xMBaPMwexCnfkvKCdlU5u19CGbaapJ3KRu-l3B-tSUhf8CCQwL0odjo6Cd5YG5lvNeB-vfdg=@pm.me/
> ---
> v2:
>     add tested-by tag
> v3:
>     add more info in commit
> ---
>  drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> index a42b584634ab..fd756f0d18f8 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> @@ -2183,14 +2183,14 @@ mt7925_mcu_sta_cmd(struct mt76_phy *phy,
>  			mt7925_mcu_sta_mld_tlv(skb, info->vif, info->link_sta->sta);
>  			mt7925_mcu_sta_eht_mld_tlv(skb, info->vif, info->link_sta->sta);
>  		}
> -
> -		mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info->link_sta);
>  	}
>  
>  	if (!info->enable) {
>  		mt7925_mcu_sta_remove_tlv(skb);
>  		mt76_connac_mcu_add_tlv(skb, STA_REC_MLD_OFF,
>  					sizeof(struct tlv));
> +	} else {
> +		mt7925_mcu_sta_hdr_trans_tlv(skb, info->vif, info->link_sta);
>  	}
>  
>  	return mt76_mcu_skb_send_msg(dev, skb, info->cmd, true);

Thank you for picking up my suggestions so quickly! This looks much
better now.


From louisalexis.eyraud at collabora.com  Fri May  9 03:12:46 2025
From: louisalexis.eyraud at collabora.com (Louis-Alexis Eyraud)
Date: Fri, 09 May 2025 12:12:46 +0200
Subject: [PATCH v6 0/5] Add Mali GPU support for Mediatek MT8370 SoC
Message-ID: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com>

This patchset adds the support of the ARM Mali G57 MC2 GPU (Valhall-JM,
dual core), integrated in the Mediatek MT8370 SoC, to the panfrost
driver and to the mt8370.dtsi include file.

Since v4 patchset was sent, the [1] patchset adds in panfrost driver
the AARCH64_4K page table format support and enablement for Mediatek
SoC with integrated Arm Mali-G57, already supported in panfrost driver
(like MT8188, MT8192, MT8195, MT8390, MT8395...).
As MT8370 SoC is a less powerful variant of MT8390 (same GPU but with
one less core for MT8370), I've reworked the second patch
('drm/panfrost: Add support for Mali on the MT8370 SoC') to enable the
AARCH64_4K mode on this SoC as well by adding specific MT8370 platform
data to set the needed flag.
The previous patch revision uses MT8186 platform data because despite
having different GPU architecture (Mali G52 2EE MC2 for MT8186, making
them not compatible), using the same plaform data, for describing the
same power management features only, was okay.
But now, the platform data also contains the GPU configuration quirk
bitfield that needs to be modified to enable the AARCH64_4K page table
format, and in order not to change MT8186 behaviour, I add specific
MT8370 platform data.

I've tested this patchset on a Mediatek Genio 510 EVK board,
with a kernel based on linux-next (tag: next-20250502).

The panfrost driver probed with the following messages:
```
panfrost 13000000.gpu: clock rate = 390000000
panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x0 status 0x0
panfrost 13000000.gpu: features: 00000000,000019f7, issues: 00000003,
  80000400
panfrost 13000000.gpu: Features: L2:0x08130206 Shader:0x00000000
  Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
panfrost 13000000.gpu: shader_present=0x5 l2_present=0x1
[drm] Initialized panfrost 1.3.0 for 13000000.gpu on minor 0
```

Running glmark2-es2-drm is also OK:
```
=======================================================
    glmark2 2023.01
=======================================================
    OpenGL Information
    GL_VENDOR:      Mesa
    GL_RENDERER:    Mali-G57 (Panfrost)
    GL_VERSION:     OpenGL ES 3.1 Mesa 25.0.3-1
    Surface Config: buf=32 r=8 g=8 b=8 a=8 depth=24 stencil=0 samples=0
    Surface Size:   1200x1920 fullscreen
=======================================================
[build] use-vbo=false: FPS: 952 FrameTime: 1.051 ms
[build] use-vbo=true: FPS: 983 FrameTime: 1.018 ms
[texture] texture-filter=nearest: FPS: 906 FrameTime: 1.105 ms
[texture] texture-filter=linear: FPS: 908 FrameTime: 1.102 ms
[texture] texture-filter=mipmap: FPS: 883 FrameTime: 1.134 ms
[shading] shading=gouraud: FPS: 838 FrameTime: 1.194 ms
[shading] shading=blinn-phong-inf: FPS: 778 FrameTime: 1.287 ms
[shading] shading=phong: FPS: 583 FrameTime: 1.717 ms
[shading] shading=cel: FPS: 553 FrameTime: 1.809 ms
[bump] bump-render=high-poly: FPS: 573 FrameTime: 1.747 ms
[bump] bump-render=normals: FPS: 868 FrameTime: 1.153 ms
[bump] bump-render=height: FPS: 707 FrameTime: 1.415 ms
[effect2d] kernel=0,1,0;1,-4,1;0,1,0;: FPS: 454 FrameTime: 2.204 ms
[effect2d] kernel=1,1,1,1,1;1,1,1,1,1;1,1,1,1,1;: FPS: 172 FrameTime:
  5.843 ms
[pulsar] light=false:quads=5:texture=false: FPS: 770 FrameTime:
  1.300 ms
[desktop] blur-radius=5:effect=blur:passes=1:separable=true:windows=4:
  FPS: 161 FrameTime: 6.235 ms
[desktop] effect=shadow:windows=4: FPS: 484 FrameTime: 2.069 ms
[buffer] columns=200:interleave=false:update-dispersion=0.9:update-fraction
  =0.5:update-method=map: FPS: 512 FrameTime: 1.955 ms
[buffer] columns=200:interleave=false:update-dispersion=0.9:update-fraction
  =0.5:update-method=subdata: FPS: 513 FrameTime: 1.952 ms
[buffer] columns=200:interleave=true:update-dispersion=0.9:update-fraction
  =0.5:update-method=map: FPS: 577 FrameTime: 1.735 ms
[ideas] speed=duration: FPS: 448 FrameTime: 2.235 ms
[jellyfish] <default>: FPS: 226 FrameTime: 4.440 ms
[terrain] <default>: FPS: 38 FrameTime: 26.861 ms
[shadow] <default>: FPS: 328 FrameTime: 3.051 ms
[refract] <default>: FPS: 72 FrameTime: 13.937 ms
[conditionals] fragment-steps=0:vertex-steps=0: FPS: 844 FrameTime:
  1.186 ms
[conditionals] fragment-steps=5:vertex-steps=0: FPS: 685 FrameTime: 
  1.462 ms
[conditionals] fragment-steps=0:vertex-steps=5: FPS: 833 FrameTime:
  1.201 ms
[function] fragment-complexity=low:fragment-steps=5: FPS: 830 FrameTime:
  1.205 ms
[function] fragment-complexity=medium:fragment-steps=5: FPS: 525 FrameTime:
  1.905 ms
[loop] fragment-loop=false:fragment-steps=5:vertex-steps=5: FPS: 837
  FrameTime: 1.195 ms
[loop] fragment-steps=5:fragment-uniform=false:vertex-steps=5: FPS: 835 
  FrameTime: 1.199 ms
[loop] fragment-steps=5:fragment-uniform=true:vertex-steps=5: FPS: 550
  FrameTime: 1.820 ms
=======================================================
                                  glmark2 Score: 611 
=======================================================
```

[1] https://lore.kernel.org/dri-devel/20250324185801.168664-1-ariel.dalessandro at collabora.com/

Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>
---
Changes in v6:
- Add two new patches to commonize and drop duplicated data related to 
  the power domain and supplies definitions for Mediatek SoC
- Remove useless comment and rework MT8370 platform data to use
  mediatek_pm_domains and default_supplies arrays in 'drm/panfrost: Add
  support for Mali on the MT8370 SoC'
- Update code-review trailer
- Link to v5: https://lore.kernel.org/r/20250502-mt8370-enable-gpu-v5-0-98e247b30151 at collabora.com

Changes in v5:
- Rebase on linux-next (tqg: next-2020501)
- Rework 'drm/panfrost: Add support for Mali on the MT8370 SoC' patch
  to have MT8370 support with its AARCH64_4K page table format support enabled 
- Drop code-review trailers from 'drm/panfrost: Add support for Mali on
  the MT8370 SoC' patch due to major changes in content and commit message
- Add ack trailer for 'dt-bindings: gpu: mali-bifrost: Add compatible 
  for MT8370 SoC' patch
- Add glmark2-es2-drm benchmark results in cover letter
- Link to v4: https://lore.kernel.org/r/20250211-mt8370-enable-gpu-v4-0-77deb7a75c23 at collabora.com

Changes in v4:
- Add warning comment in mt8370.dtsi about GPU node override
- Reword "dt-bindings: gpu: mali-bifrost: Add compatible for MT8370
  SoC" commit message
- Add code-review trailers
- Link to v3: https://lore.kernel.org/r/20250207-mt8370-enable-gpu-v3-0-75e9b902f9c1 at collabora.com

Changes in v3:
- Rebased on linux-next (tag: next-20250207)
- Remove prerequisite change/patch ids
- Reword commit messages to better explicit compatible needs
- Link to v2: https://lore.kernel.org/r/20250130-mt8370-enable-gpu-v2-0-c154d0815db5 at collabora.com

Changes in v2:
- Rework "drm/panfrost: Add support for Mali on the MT8370 SoC" to avoid
  data structure duplication, as requested by Krzysztof Kozlowski
- Reword commit messages to use imperative mood and make new compatible
  need more explicit
- Link to v1: https://lore.kernel.org/r/20250116-mt8370-enable-gpu-v1-0-0a6b78e925c8 at collabora.com

---
Louis-Alexis Eyraud (5):
      dt-bindings: gpu: mali-bifrost: Add compatible for MT8370 SoC
      drm/panfrost: Drop duplicated Mediatek supplies arrays
      drm/panfrost: Commonize Mediatek power domain array definitions
      drm/panfrost: Add support for Mali on the MT8370 SoC
      arm64: dts: mediatek: mt8370: Enable gpu support

 .../devicetree/bindings/gpu/arm,mali-bifrost.yaml  |  5 +-
 arch/arm64/boot/dts/mediatek/mt8370.dtsi           | 16 ++++++
 drivers/gpu/drm/panfrost/panfrost_drv.c            | 61 ++++++++++++----------
 3 files changed, 53 insertions(+), 29 deletions(-)
---
base-commit: 1c51b1ba38c07e4f999802eb708bf798dd5f5d1b
change-id: 20250115-mt8370-enable-gpu-3b6f595fa63d

Best regards,
-- 
Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>



From louisalexis.eyraud at collabora.com  Fri May  9 03:12:47 2025
From: louisalexis.eyraud at collabora.com (Louis-Alexis Eyraud)
Date: Fri, 09 May 2025 12:12:47 +0200
Subject: [PATCH v6 1/5] dt-bindings: gpu: mali-bifrost: Add compatible for
 MT8370 SoC
In-Reply-To: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com>
References: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com>
Message-ID: <20250509-mt8370-enable-gpu-v6-1-2833888cb1d3@collabora.com>

Add a compatible for the MediaTek MT8370 SoC, with an
integrated ARM Mali G57 MC2 GPU (Valhall-JM, dual core).
None of the already existing SoC specific compatibles is usable as
fallback, as those either do not match the number of cores (and number
of power domains), or are for a different GPU architecture.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Acked-by: Conor Dooley <conor.dooley at microchip.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>
---
 Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
index 019bd28a29f19bb4f7a9c32434b208b6d04db221..5726b79fd0f9de8914f724929f462409e088ec31 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
@@ -40,6 +40,7 @@ properties:
           - enum:
               - mediatek,mt8188-mali
               - mediatek,mt8192-mali
+              - mediatek,mt8370-mali
           - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
 
   reg:
@@ -221,7 +222,9 @@ allOf:
       properties:
         compatible:
           contains:
-            const: mediatek,mt8186-mali
+            enum:
+              - mediatek,mt8186-mali
+              - mediatek,mt8370-mali
     then:
       properties:
         power-domains:

-- 
2.49.0



From louisalexis.eyraud at collabora.com  Fri May  9 03:12:48 2025
From: louisalexis.eyraud at collabora.com (Louis-Alexis Eyraud)
Date: Fri, 09 May 2025 12:12:48 +0200
Subject: [PATCH v6 2/5] drm/panfrost: Drop duplicated Mediatek supplies
 arrays
In-Reply-To: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com>
References: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com>
Message-ID: <20250509-mt8370-enable-gpu-v6-2-2833888cb1d3@collabora.com>

In the panfrost driver, the platform data of several Mediatek SoC
declares and uses custom supplies array definitions
(mediatek_mt8192_supplies, mediatek_mt8183_b_supplies), that are the
same as default_supplies (used by default platform data).

So drop these duplicated definitions and use default_supplies instead.
Also, rename mediatek_mt8183_supplies to a more generic name too
(legacy_supplies).

Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>
---
 drivers/gpu/drm/panfrost/panfrost_drv.c | 24 +++++++++++-------------
 1 file changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
index f1ec3b02f15a0029d20c7d81046ded59854e885c..7b899a9b2120c608e61dab9ca831ab8e907e8139 100644
--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
@@ -797,19 +797,18 @@ static const struct panfrost_compatible amlogic_data = {
  * On new devicetrees please use the _b variant with a single and
  * coupled regulators instead.
  */
-static const char * const mediatek_mt8183_supplies[] = { "mali", "sram", NULL };
+static const char * const legacy_supplies[] = { "mali", "sram", NULL };
 static const char * const mediatek_mt8183_pm_domains[] = { "core0", "core1", "core2" };
 static const struct panfrost_compatible mediatek_mt8183_data = {
-	.num_supplies = ARRAY_SIZE(mediatek_mt8183_supplies) - 1,
-	.supply_names = mediatek_mt8183_supplies,
+	.num_supplies = ARRAY_SIZE(legacy_supplies) - 1,
+	.supply_names = legacy_supplies,
 	.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),
 	.pm_domain_names = mediatek_mt8183_pm_domains,
 };
 
-static const char * const mediatek_mt8183_b_supplies[] = { "mali", NULL };
 static const struct panfrost_compatible mediatek_mt8183_b_data = {
-	.num_supplies = ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1,
-	.supply_names = mediatek_mt8183_b_supplies,
+	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
+	.supply_names = default_supplies,
 	.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),
 	.pm_domain_names = mediatek_mt8183_pm_domains,
 	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
@@ -817,8 +816,8 @@ static const struct panfrost_compatible mediatek_mt8183_b_data = {
 
 static const char * const mediatek_mt8186_pm_domains[] = { "core0", "core1" };
 static const struct panfrost_compatible mediatek_mt8186_data = {
-	.num_supplies = ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1,
-	.supply_names = mediatek_mt8183_b_supplies,
+	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
+	.supply_names = default_supplies,
 	.num_pm_domains = ARRAY_SIZE(mediatek_mt8186_pm_domains),
 	.pm_domain_names = mediatek_mt8186_pm_domains,
 	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
@@ -826,20 +825,19 @@ static const struct panfrost_compatible mediatek_mt8186_data = {
 
 /* MT8188 uses the same power domains and power supplies as MT8183 */
 static const struct panfrost_compatible mediatek_mt8188_data = {
-	.num_supplies = ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1,
-	.supply_names = mediatek_mt8183_b_supplies,
+	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
+	.supply_names = default_supplies,
 	.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),
 	.pm_domain_names = mediatek_mt8183_pm_domains,
 	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
 	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
 };
 
-static const char * const mediatek_mt8192_supplies[] = { "mali", NULL };
 static const char * const mediatek_mt8192_pm_domains[] = { "core0", "core1", "core2",
 							   "core3", "core4" };
 static const struct panfrost_compatible mediatek_mt8192_data = {
-	.num_supplies = ARRAY_SIZE(mediatek_mt8192_supplies) - 1,
-	.supply_names = mediatek_mt8192_supplies,
+	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
+	.supply_names = default_supplies,
 	.num_pm_domains = ARRAY_SIZE(mediatek_mt8192_pm_domains),
 	.pm_domain_names = mediatek_mt8192_pm_domains,
 	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),

-- 
2.49.0



From louisalexis.eyraud at collabora.com  Fri May  9 03:12:49 2025
From: louisalexis.eyraud at collabora.com (Louis-Alexis Eyraud)
Date: Fri, 09 May 2025 12:12:49 +0200
Subject: [PATCH v6 3/5] drm/panfrost: Commonize Mediatek power domain array
 definitions
In-Reply-To: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com>
References: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com>
Message-ID: <20250509-mt8370-enable-gpu-v6-3-2833888cb1d3@collabora.com>

In the panfrost driver, the platform data of several Mediatek SoC
declares and uses several different power domains arrays according to
GPU core number present in the SoC:
- mediatek_mt8186_pm_domains (2 cores)
- mediatek_mt8183_pm_domains (3 cores)
- mediatek_mt8192_pm_domains (5 cores)

As they all are fixed arrays, starting with the same entries and the
platform data also has a power domains array length field
(num_pm_domains), they can be replaced by a single array, containing
all entries, if the num_pm_domains field of the platform data is also
set to the matching core number.

So, create a generic power domain array (mediatek_pm_domains) and use
it in the mt8183(b), mt8186, mt8188 and mt8192 platform data instead.

Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>
---
 drivers/gpu/drm/panfrost/panfrost_drv.c | 27 ++++++++++++---------------
 1 file changed, 12 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
index 7b899a9b2120c608e61dab9ca831ab8e907e8139..21b28bef84015793d9dba6b1e585891dc0dfcb6d 100644
--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
@@ -789,6 +789,8 @@ static const struct panfrost_compatible amlogic_data = {
 	.vendor_quirk = panfrost_gpu_amlogic_quirk,
 };
 
+static const char * const mediatek_pm_domains[] = { "core0", "core1", "core2",
+						    "core3", "core4" };
 /*
  * The old data with two power supplies for MT8183 is here only to
  * keep retro-compatibility with older devicetrees, as DVFS will
@@ -798,48 +800,43 @@ static const struct panfrost_compatible amlogic_data = {
  * coupled regulators instead.
  */
 static const char * const legacy_supplies[] = { "mali", "sram", NULL };
-static const char * const mediatek_mt8183_pm_domains[] = { "core0", "core1", "core2" };
 static const struct panfrost_compatible mediatek_mt8183_data = {
 	.num_supplies = ARRAY_SIZE(legacy_supplies) - 1,
 	.supply_names = legacy_supplies,
-	.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),
-	.pm_domain_names = mediatek_mt8183_pm_domains,
+	.num_pm_domains = 3,
+	.pm_domain_names = mediatek_pm_domains,
 };
 
 static const struct panfrost_compatible mediatek_mt8183_b_data = {
 	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
 	.supply_names = default_supplies,
-	.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),
-	.pm_domain_names = mediatek_mt8183_pm_domains,
+	.num_pm_domains = 3,
+	.pm_domain_names = mediatek_pm_domains,
 	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
 };
 
-static const char * const mediatek_mt8186_pm_domains[] = { "core0", "core1" };
 static const struct panfrost_compatible mediatek_mt8186_data = {
 	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
 	.supply_names = default_supplies,
-	.num_pm_domains = ARRAY_SIZE(mediatek_mt8186_pm_domains),
-	.pm_domain_names = mediatek_mt8186_pm_domains,
+	.num_pm_domains = 2,
+	.pm_domain_names = mediatek_pm_domains,
 	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
 };
 
-/* MT8188 uses the same power domains and power supplies as MT8183 */
 static const struct panfrost_compatible mediatek_mt8188_data = {
 	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
 	.supply_names = default_supplies,
-	.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),
-	.pm_domain_names = mediatek_mt8183_pm_domains,
+	.num_pm_domains = 3,
+	.pm_domain_names = mediatek_pm_domains,
 	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
 	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
 };
 
-static const char * const mediatek_mt8192_pm_domains[] = { "core0", "core1", "core2",
-							   "core3", "core4" };
 static const struct panfrost_compatible mediatek_mt8192_data = {
 	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
 	.supply_names = default_supplies,
-	.num_pm_domains = ARRAY_SIZE(mediatek_mt8192_pm_domains),
-	.pm_domain_names = mediatek_mt8192_pm_domains,
+	.num_pm_domains = 5,
+	.pm_domain_names = mediatek_pm_domains,
 	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
 	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
 };

-- 
2.49.0



From louisalexis.eyraud at collabora.com  Fri May  9 03:12:50 2025
From: louisalexis.eyraud at collabora.com (Louis-Alexis Eyraud)
Date: Fri, 09 May 2025 12:12:50 +0200
Subject: [PATCH v6 4/5] drm/panfrost: Add support for Mali on the MT8370
 SoC
In-Reply-To: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com>
References: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com>
Message-ID: <20250509-mt8370-enable-gpu-v6-4-2833888cb1d3@collabora.com>

Add a compatible for the MediaTek MT8370 SoC, with an integrated ARM
Mali G57 MC2 GPU (Valhall-JM, dual core), with new platform data for
its support in the panfrost driver.
It uses the same data as MT8186 for the power management features to
describe power supplies, pm_domains and enablement (one regulator, two
power domains) but also sets the FORCE_AARCH64_PGTABLE flag in the GPU
configuration quirks bitfield to enable AARCH64 4K page table format
mode.
As MT8186 and MT8370 SoC have different GPU architecture (Mali G52 2EE
MC2 for MT8186), making them not compatible, and this mode is only
enabled for Mediatek SoC that are Mali G57 based (compatible with
mediatek,mali-mt8188 or mediatek,mali-8192), having specific platform
data allows to set this flag for MT8370 without modifying MT8186
configuration and behaviour.

Reviewed-by: Steven Price <steven.price at arm.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>
---
 drivers/gpu/drm/panfrost/panfrost_drv.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
index 21b28bef84015793d9dba6b1e585891dc0dfcb6d..07cd67baa81bfccabf3b1a29f7d78702038bb2cd 100644
--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
@@ -841,6 +841,15 @@ static const struct panfrost_compatible mediatek_mt8192_data = {
 	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
 };
 
+static const struct panfrost_compatible mediatek_mt8370_data = {
+	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
+	.supply_names = default_supplies,
+	.num_pm_domains = 2,
+	.pm_domain_names = mediatek_pm_domains,
+	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
+	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
+};
+
 static const struct of_device_id dt_match[] = {
 	/* Set first to probe before the generic compatibles */
 	{ .compatible = "amlogic,meson-gxm-mali",
@@ -863,6 +872,7 @@ static const struct of_device_id dt_match[] = {
 	{ .compatible = "mediatek,mt8186-mali", .data = &mediatek_mt8186_data },
 	{ .compatible = "mediatek,mt8188-mali", .data = &mediatek_mt8188_data },
 	{ .compatible = "mediatek,mt8192-mali", .data = &mediatek_mt8192_data },
+	{ .compatible = "mediatek,mt8370-mali", .data = &mediatek_mt8370_data },
 	{ .compatible = "allwinner,sun50i-h616-mali", .data = &allwinner_h616_data },
 	{}
 };

-- 
2.49.0



From louisalexis.eyraud at collabora.com  Fri May  9 03:12:51 2025
From: louisalexis.eyraud at collabora.com (Louis-Alexis Eyraud)
Date: Fri, 09 May 2025 12:12:51 +0200
Subject: [PATCH v6 5/5] arm64: dts: mediatek: mt8370: Enable gpu support
In-Reply-To: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com>
References: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com>
Message-ID: <20250509-mt8370-enable-gpu-v6-5-2833888cb1d3@collabora.com>

Add a new gpu node in mt8370.dtsi to enable support for the
ARM Mali G57 MC2 GPU (Valhall-JM) found on the MT8370 SoC, using the
Panfrost driver.

On a Mediatek Genio 510 EVK board, the panfrost driver probed with the
following message:
```
panfrost 13000000.gpu: clock rate = 390000000
panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x0 status 0x0
panfrost 13000000.gpu: features: 00000000,000019f7, issues: 00000003,
   80000400
panfrost 13000000.gpu: Features: L2:0x08130206 Shader:0x00000000
   Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
panfrost 13000000.gpu: shader_present=0x5 l2_present=0x1
[drm] Initialized panfrost 1.3.0 for 13000000.gpu on minor 0
```

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8370.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8370.dtsi b/arch/arm64/boot/dts/mediatek/mt8370.dtsi
index cf1a3759451ff899ce9e63e5a00f192fb483f6e5..7ac8b8d0349455922a73f35db607b2b27cad23d7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8370.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8370.dtsi
@@ -59,6 +59,22 @@ &cpu_little3_cooling_map0 {
 				<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 };
 
+/*
+ * Please note that overriding compatibles is a discouraged practice and is a
+ * clear indication of nodes not being, well, compatible!
+ *
+ * This is a special case, where the GPU is the same as MT8188, but with one
+ * of the cores fused out in this lower-binned SoC.
+ */
+&gpu {
+	compatible = "mediatek,mt8370-mali", "arm,mali-valhall-jm";
+
+	power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
+			<&spm MT8188_POWER_DOMAIN_MFG3>;
+
+	power-domain-names = "core0", "core1";
+};
+
 &ppi_cluster0 {
 	affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
 };

-- 
2.49.0



From steven.price at arm.com  Fri May  9 03:59:07 2025
From: steven.price at arm.com (Steven Price)
Date: Fri, 9 May 2025 11:59:07 +0100
Subject: [PATCH v6 2/5] drm/panfrost: Drop duplicated Mediatek supplies
 arrays
In-Reply-To: <20250509-mt8370-enable-gpu-v6-2-2833888cb1d3@collabora.com>
References: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com>
 <20250509-mt8370-enable-gpu-v6-2-2833888cb1d3@collabora.com>
Message-ID: <124b8718-1a8e-4cf2-99e2-604fe63ae132@arm.com>

On 09/05/2025 11:12, Louis-Alexis Eyraud wrote:
> In the panfrost driver, the platform data of several Mediatek SoC
> declares and uses custom supplies array definitions
> (mediatek_mt8192_supplies, mediatek_mt8183_b_supplies), that are the
> same as default_supplies (used by default platform data).
> 
> So drop these duplicated definitions and use default_supplies instead.
> Also, rename mediatek_mt8183_supplies to a more generic name too
> (legacy_supplies).
> 
> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>

Thanks for doing this.

Reviewed-by: Steven Price <steven.price at arm.com>

> ---
>  drivers/gpu/drm/panfrost/panfrost_drv.c | 24 +++++++++++-------------
>  1 file changed, 11 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
> index f1ec3b02f15a0029d20c7d81046ded59854e885c..7b899a9b2120c608e61dab9ca831ab8e907e8139 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_drv.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
> @@ -797,19 +797,18 @@ static const struct panfrost_compatible amlogic_data = {
>   * On new devicetrees please use the _b variant with a single and
>   * coupled regulators instead.
>   */
> -static const char * const mediatek_mt8183_supplies[] = { "mali", "sram", NULL };
> +static const char * const legacy_supplies[] = { "mali", "sram", NULL };
>  static const char * const mediatek_mt8183_pm_domains[] = { "core0", "core1", "core2" };
>  static const struct panfrost_compatible mediatek_mt8183_data = {
> -	.num_supplies = ARRAY_SIZE(mediatek_mt8183_supplies) - 1,
> -	.supply_names = mediatek_mt8183_supplies,
> +	.num_supplies = ARRAY_SIZE(legacy_supplies) - 1,
> +	.supply_names = legacy_supplies,
>  	.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),
>  	.pm_domain_names = mediatek_mt8183_pm_domains,
>  };
>  
> -static const char * const mediatek_mt8183_b_supplies[] = { "mali", NULL };
>  static const struct panfrost_compatible mediatek_mt8183_b_data = {
> -	.num_supplies = ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1,
> -	.supply_names = mediatek_mt8183_b_supplies,
> +	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
> +	.supply_names = default_supplies,
>  	.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),
>  	.pm_domain_names = mediatek_mt8183_pm_domains,
>  	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
> @@ -817,8 +816,8 @@ static const struct panfrost_compatible mediatek_mt8183_b_data = {
>  
>  static const char * const mediatek_mt8186_pm_domains[] = { "core0", "core1" };
>  static const struct panfrost_compatible mediatek_mt8186_data = {
> -	.num_supplies = ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1,
> -	.supply_names = mediatek_mt8183_b_supplies,
> +	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
> +	.supply_names = default_supplies,
>  	.num_pm_domains = ARRAY_SIZE(mediatek_mt8186_pm_domains),
>  	.pm_domain_names = mediatek_mt8186_pm_domains,
>  	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
> @@ -826,20 +825,19 @@ static const struct panfrost_compatible mediatek_mt8186_data = {
>  
>  /* MT8188 uses the same power domains and power supplies as MT8183 */
>  static const struct panfrost_compatible mediatek_mt8188_data = {
> -	.num_supplies = ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1,
> -	.supply_names = mediatek_mt8183_b_supplies,
> +	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
> +	.supply_names = default_supplies,
>  	.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),
>  	.pm_domain_names = mediatek_mt8183_pm_domains,
>  	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
>  	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
>  };
>  
> -static const char * const mediatek_mt8192_supplies[] = { "mali", NULL };
>  static const char * const mediatek_mt8192_pm_domains[] = { "core0", "core1", "core2",
>  							   "core3", "core4" };
>  static const struct panfrost_compatible mediatek_mt8192_data = {
> -	.num_supplies = ARRAY_SIZE(mediatek_mt8192_supplies) - 1,
> -	.supply_names = mediatek_mt8192_supplies,
> +	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
> +	.supply_names = default_supplies,
>  	.num_pm_domains = ARRAY_SIZE(mediatek_mt8192_pm_domains),
>  	.pm_domain_names = mediatek_mt8192_pm_domains,
>  	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
> 



From steven.price at arm.com  Fri May  9 03:59:15 2025
From: steven.price at arm.com (Steven Price)
Date: Fri, 9 May 2025 11:59:15 +0100
Subject: [PATCH v6 3/5] drm/panfrost: Commonize Mediatek power domain
 array definitions
In-Reply-To: <20250509-mt8370-enable-gpu-v6-3-2833888cb1d3@collabora.com>
References: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com>
 <20250509-mt8370-enable-gpu-v6-3-2833888cb1d3@collabora.com>
Message-ID: <32dd077c-52db-4bef-8d76-12b7aaff2408@arm.com>

On 09/05/2025 11:12, Louis-Alexis Eyraud wrote:
> In the panfrost driver, the platform data of several Mediatek SoC
> declares and uses several different power domains arrays according to
> GPU core number present in the SoC:
> - mediatek_mt8186_pm_domains (2 cores)
> - mediatek_mt8183_pm_domains (3 cores)
> - mediatek_mt8192_pm_domains (5 cores)
> 
> As they all are fixed arrays, starting with the same entries and the
> platform data also has a power domains array length field
> (num_pm_domains), they can be replaced by a single array, containing
> all entries, if the num_pm_domains field of the platform data is also
> set to the matching core number.
> 
> So, create a generic power domain array (mediatek_pm_domains) and use
> it in the mt8183(b), mt8186, mt8188 and mt8192 platform data instead.
> 
> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>

Reviewed-by: Steven Price <steven.price at arm.com>

> ---
>  drivers/gpu/drm/panfrost/panfrost_drv.c | 27 ++++++++++++---------------
>  1 file changed, 12 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
> index 7b899a9b2120c608e61dab9ca831ab8e907e8139..21b28bef84015793d9dba6b1e585891dc0dfcb6d 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_drv.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
> @@ -789,6 +789,8 @@ static const struct panfrost_compatible amlogic_data = {
>  	.vendor_quirk = panfrost_gpu_amlogic_quirk,
>  };
>  
> +static const char * const mediatek_pm_domains[] = { "core0", "core1", "core2",
> +						    "core3", "core4" };
>  /*
>   * The old data with two power supplies for MT8183 is here only to
>   * keep retro-compatibility with older devicetrees, as DVFS will
> @@ -798,48 +800,43 @@ static const struct panfrost_compatible amlogic_data = {
>   * coupled regulators instead.
>   */
>  static const char * const legacy_supplies[] = { "mali", "sram", NULL };
> -static const char * const mediatek_mt8183_pm_domains[] = { "core0", "core1", "core2" };
>  static const struct panfrost_compatible mediatek_mt8183_data = {
>  	.num_supplies = ARRAY_SIZE(legacy_supplies) - 1,
>  	.supply_names = legacy_supplies,
> -	.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),
> -	.pm_domain_names = mediatek_mt8183_pm_domains,
> +	.num_pm_domains = 3,
> +	.pm_domain_names = mediatek_pm_domains,
>  };
>  
>  static const struct panfrost_compatible mediatek_mt8183_b_data = {
>  	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
>  	.supply_names = default_supplies,
> -	.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),
> -	.pm_domain_names = mediatek_mt8183_pm_domains,
> +	.num_pm_domains = 3,
> +	.pm_domain_names = mediatek_pm_domains,
>  	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
>  };
>  
> -static const char * const mediatek_mt8186_pm_domains[] = { "core0", "core1" };
>  static const struct panfrost_compatible mediatek_mt8186_data = {
>  	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
>  	.supply_names = default_supplies,
> -	.num_pm_domains = ARRAY_SIZE(mediatek_mt8186_pm_domains),
> -	.pm_domain_names = mediatek_mt8186_pm_domains,
> +	.num_pm_domains = 2,
> +	.pm_domain_names = mediatek_pm_domains,
>  	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
>  };
>  
> -/* MT8188 uses the same power domains and power supplies as MT8183 */
>  static const struct panfrost_compatible mediatek_mt8188_data = {
>  	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
>  	.supply_names = default_supplies,
> -	.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),
> -	.pm_domain_names = mediatek_mt8183_pm_domains,
> +	.num_pm_domains = 3,
> +	.pm_domain_names = mediatek_pm_domains,
>  	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
>  	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
>  };
>  
> -static const char * const mediatek_mt8192_pm_domains[] = { "core0", "core1", "core2",
> -							   "core3", "core4" };
>  static const struct panfrost_compatible mediatek_mt8192_data = {
>  	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
>  	.supply_names = default_supplies,
> -	.num_pm_domains = ARRAY_SIZE(mediatek_mt8192_pm_domains),
> -	.pm_domain_names = mediatek_mt8192_pm_domains,
> +	.num_pm_domains = 5,
> +	.pm_domain_names = mediatek_pm_domains,
>  	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
>  	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
>  };
> 



From luca.ceresoli at bootlin.com  Fri May  9 06:53:27 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:27 +0200
Subject: [PATCH v3 01/22] Revert "drm/exynos: mic: convert to
 devm_drm_bridge_alloc() API"
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-1-b8bc1f16d7aa@bootlin.com>

This reverts commit 3be618fab0e31b086cd6456280293119bb20fd41.

This patch has been applied by mistake without needed review/ack by
maintainers.

---

Cc: Louis Chauvet <louis.chauvet at bootlin.com>
Cc: Alim Akhtar <alim.akhtar at samsung.com>
Cc: Inki Dae <inki.dae at samsung.com>
Cc: Kyungmin Park <kyungmin.park at samsung.com>
Cc: Seung-Woo Kim <sw0312.kim at samsung.com>
---
 drivers/gpu/drm/exynos/exynos_drm_mic.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_mic.c b/drivers/gpu/drm/exynos/exynos_drm_mic.c
index 29a8366513fa70655c6ceec9a09db0158e7bb169..b34ec67283370e3fa836c7df06e12e2fba524622 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_mic.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_mic.c
@@ -379,11 +379,11 @@ static int exynos_mic_probe(struct platform_device *pdev)
 	struct resource res;
 	int ret, i;
 
-	mic = devm_drm_bridge_alloc(dev, struct exynos_mic, bridge, &mic_bridge_funcs);
-	if (IS_ERR(mic)) {
+	mic = devm_kzalloc(dev, sizeof(*mic), GFP_KERNEL);
+	if (!mic) {
 		DRM_DEV_ERROR(dev,
 			      "mic: Failed to allocate memory for MIC object\n");
-		ret = PTR_ERR(mic);
+		ret = -ENOMEM;
 		goto err;
 	}
 
@@ -421,6 +421,7 @@ static int exynos_mic_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, mic);
 
+	mic->bridge.funcs = &mic_bridge_funcs;
 	mic->bridge.of_node = dev->of_node;
 
 	drm_bridge_add(&mic->bridge);

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:26 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:26 +0200
Subject: [PATCH v3 00/22] drm: convert all bridges to
 devm_drm_bridge_alloc()
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>

devm_drm_bridge_alloc() [0] is the new API to allocate and initialize a DRM
bridge, and the only one supported from now on. It is the first milestone
towards removal of bridges from a still existing DRM pipeline without
use-after-free.

The steps in the grand plan [1] are:

 1. ? add refcounting to DRM bridges (struct drm_bridge)
 2. handle gracefully atomic updates during bridge removal
 3. avoid DSI host drivers to have dangling pointers to DSI devices
 4. finish the hotplug bridge work, removing the "always-disconnected"
    connector, moving code to the core and potentially removing the
    hotplug-bridge itself (this needs to be clarified as points 1-3 are
    developed)

This series is part of step 1 of the grand plan.

Current tasks in step 1 of the grand plan:

 A. ? add new alloc API and refcounting -> (now in drm-misc-next)
 B. ? convert all bridge drivers to new API (this series)
 C. ? documentation, kunit tests (v1 under discussion)
 D. after (B), add get/put to drm_bridge_add/remove() + attach/detech()
 E. after (B), convert accessors; this is a large work and can be done
    in chunks
 F. debugfs improvements

More info about this series in the v2 cover [2].

Luca

[0] https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/0cc6aadd7fc1e629b715ea3d1ba537ef2da95eec
[1] https://lore.kernel.org/lkml/20250206-hotplug-drm-bridge-v6-0-9d6f2c9c3058 at bootlin.com/t/#u
[2] https://lore.kernel.org/lkml/20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b at bootlin.com/

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
---
Changes in v3:
- Fixed issues reported for some patches
- Added review tags
- Removed patches that have been applied
- Added revert for the exynos patch, applied by mistake
- Update cover with grand plan info and trim some of it
- Updated bouncing e-mail address in Cc list
- Link to v2: https://lore.kernel.org/lkml/20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b at bootlin.com/

Changes in v2:
- Improved cover letter with link to commit adding devm_drm_bridge_alloc()
- add review tags
- fix bugs in zynqmp, vc4 patches
- fix patch 1 error code checking
- Link to v1: https://lore.kernel.org/r/20250407-drm-bridge-convert-to-alloc-api-v1-0-42113ff8d9c0 at bootlin.com

---
Luca Ceresoli (22):
      Revert "drm/exynos: mic: convert to devm_drm_bridge_alloc() API"
      drm: convert many bridge drivers from devm_kzalloc() to devm_drm_bridge_alloc() API
      drm/bridge: anx7625: convert to devm_drm_bridge_alloc() API
      drm/bridge: cdns-dsi: convert to devm_drm_bridge_alloc() API
      drm/bridge: megachips-stdpxxxx-ge-b850v3-fw: convert to devm_drm_bridge_alloc() API
      drm/bridge: nxp-ptn3460: convert to devm_drm_bridge_alloc() API
      drm/bridge: sii902x: convert to devm_drm_bridge_alloc() API
      drm/omap: dss: dpi: convert to devm_drm_bridge_alloc() API
      drm/omap: dss: dsi: convert to devm_drm_bridge_alloc() API
      drm/omap: dss: hdmi4: convert to devm_drm_bridge_alloc() API
      drm/omap: dss: hdmi5: convert to devm_drm_bridge_alloc() API
      drm/omap: dss: sdi: convert to devm_drm_bridge_alloc() API
      drm/omap: dss: venc: convert to devm_drm_bridge_alloc() API
      drm/rcar-du: dsi: convert to devm_drm_bridge_alloc() API
      drm/bridge: stm_lvds: convert to devm_drm_bridge_alloc() API
      drm/sti: dvo: convert to devm_drm_bridge_alloc() API
      drm: zynqmp_dp: convert to devm_drm_bridge_alloc() API
      drm/bridge: imx8qxp-pixel-combiner: convert to devm_drm_bridge_alloc() API
      drm/bridge: tc358767: convert to devm_drm_bridge_alloc() API
      drm/bridge: add devm_drm_put_bridge()
      drm/bridge: panel: convert to devm_drm_bridge_alloc() API
      drm/todo: add entry to remove devm_drm_put_bridge()

 Documentation/gpu/todo.rst                         | 15 ++++++
 drivers/gpu/drm/adp/adp-mipi.c                     |  8 ++--
 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c       |  8 ++--
 drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c |  9 ++--
 drivers/gpu/drm/bridge/analogix/anx7625.c          |  7 ++-
 drivers/gpu/drm/bridge/aux-bridge.c                |  8 ++--
 drivers/gpu/drm/bridge/aux-hpd-bridge.c            |  9 ++--
 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c     |  8 ++--
 .../gpu/drm/bridge/cadence/cdns-mhdp8546-core.c    |  8 ++--
 drivers/gpu/drm/bridge/chipone-icn6211.c           |  8 ++--
 drivers/gpu/drm/bridge/chrontel-ch7033.c           |  8 ++--
 drivers/gpu/drm/bridge/cros-ec-anx7688.c           |  8 ++--
 drivers/gpu/drm/bridge/fsl-ldb.c                   |  7 ++-
 drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c     |  8 ++--
 drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c       |  8 ++--
 .../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c    | 27 ++++++-----
 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c    |  8 ++--
 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c       |  8 ++--
 drivers/gpu/drm/bridge/ite-it6263.c                |  8 ++--
 drivers/gpu/drm/bridge/ite-it6505.c                |  8 ++--
 drivers/gpu/drm/bridge/ite-it66121.c               |  8 ++--
 drivers/gpu/drm/bridge/lontium-lt8912b.c           |  8 ++--
 drivers/gpu/drm/bridge/lontium-lt9211.c            |  7 ++-
 drivers/gpu/drm/bridge/lontium-lt9611.c            |  8 ++--
 drivers/gpu/drm/bridge/lvds-codec.c                |  9 ++--
 .../drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c   | 11 ++---
 drivers/gpu/drm/bridge/microchip-lvds.c            |  8 ++--
 drivers/gpu/drm/bridge/nwl-dsi.c                   |  8 ++--
 drivers/gpu/drm/bridge/nxp-ptn3460.c               |  9 ++--
 drivers/gpu/drm/bridge/panel.c                     | 12 ++---
 drivers/gpu/drm/bridge/parade-ps8622.c             |  8 ++--
 drivers/gpu/drm/bridge/parade-ps8640.c             |  8 ++--
 drivers/gpu/drm/bridge/sii902x.c                   |  7 ++-
 drivers/gpu/drm/bridge/sii9234.c                   |  8 ++--
 drivers/gpu/drm/bridge/sil-sii8620.c               |  8 ++--
 drivers/gpu/drm/bridge/simple-bridge.c             |  8 ++--
 drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c       |  8 ++--
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c      |  8 ++--
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c     |  8 ++--
 drivers/gpu/drm/bridge/tc358762.c                  |  8 ++--
 drivers/gpu/drm/bridge/tc358764.c                  |  8 ++--
 drivers/gpu/drm/bridge/tc358767.c                  | 56 +++++++++++++++-------
 drivers/gpu/drm/bridge/tc358768.c                  |  8 ++--
 drivers/gpu/drm/bridge/tc358775.c                  |  8 ++--
 drivers/gpu/drm/bridge/thc63lvd1024.c              |  8 ++--
 drivers/gpu/drm/bridge/ti-dlpc3433.c               |  8 ++--
 drivers/gpu/drm/bridge/ti-tdp158.c                 |  8 ++--
 drivers/gpu/drm/bridge/ti-tfp410.c                 |  8 ++--
 drivers/gpu/drm/bridge/ti-tpd12s015.c              |  8 ++--
 drivers/gpu/drm/drm_bridge.c                       | 17 +++++++
 drivers/gpu/drm/exynos/exynos_drm_mic.c            |  7 +--
 drivers/gpu/drm/mediatek/mtk_dp.c                  |  8 ++--
 drivers/gpu/drm/mediatek/mtk_dpi.c                 |  8 ++--
 drivers/gpu/drm/mediatek/mtk_dsi.c                 |  8 ++--
 drivers/gpu/drm/mediatek/mtk_hdmi.c                |  8 ++--
 drivers/gpu/drm/meson/meson_encoder_cvbs.c         | 10 ++--
 drivers/gpu/drm/meson/meson_encoder_dsi.c          | 10 ++--
 drivers/gpu/drm/meson/meson_encoder_hdmi.c         | 10 ++--
 drivers/gpu/drm/omapdrm/dss/dpi.c                  |  7 ++-
 drivers/gpu/drm/omapdrm/dss/dsi.c                  |  7 ++-
 drivers/gpu/drm/omapdrm/dss/hdmi4.c                | 26 ++++------
 drivers/gpu/drm/omapdrm/dss/hdmi5.c                | 26 ++++------
 drivers/gpu/drm/omapdrm/dss/sdi.c                  | 25 ++++------
 drivers/gpu/drm/omapdrm/dss/venc.c                 | 23 ++++-----
 drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c        |  8 ++--
 drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c    |  8 ++--
 drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c     |  8 ++--
 drivers/gpu/drm/sti/sti_dvo.c                      | 29 +++++------
 drivers/gpu/drm/stm/lvds.c                         |  7 ++-
 drivers/gpu/drm/xlnx/zynqmp_dp.c                   | 31 +++++-------
 drivers/gpu/drm/xlnx/zynqmp_dpsub.c                |  1 -
 include/drm/drm_bridge.h                           |  4 ++
 72 files changed, 390 insertions(+), 379 deletions(-)
---
base-commit: 94c60d3c1079fc044e356a78ffc68ca7b0603039
change-id: 20250404-drm-bridge-convert-to-alloc-api-614becf62294

Best regards,
-- 
Luca Ceresoli <luca.ceresoli at bootlin.com>



From luca.ceresoli at bootlin.com  Fri May  9 06:53:28 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:28 +0200
Subject: [PATCH v3 02/22] drm: convert many bridge drivers from
 devm_kzalloc() to devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-2-b8bc1f16d7aa@bootlin.com>

devm_drm_bridge_alloc() is the new API to be used for allocating (and
partially initializing) a private driver struct embedding a struct
drm_bridge.

For many drivers having a simple code flow in the probe function, this
commit does a mass conversion automatically with the following semantic
patch. The changes have been reviewed manually for correctness as well as
to find any false positives.

The patch has been applied with the explicit exclusion of bridge/panel.c,
handled by a separate patch.

After applying the semantic patch, manually fixed these issues:

 - 4 drivers need ERR_CAST() instead of PTR_ERR() as the function calling
   devm_drm_bridge_alloc() returns a pointer
 - re-added empty lines and comments that the script had removed but that
   should stay

  @@
  type T;
  identifier C;
  identifier BR;
  expression DEV;
  expression FUNCS;
  @@
  -T *C;
  +T *C;
   ...
  (
  -C = devm_kzalloc(DEV, ...);
  -if (!C)
  -    return -ENOMEM;
  +C = devm_drm_bridge_alloc(DEV, T, BR, FUNCS);
  +if (IS_ERR(C))
  +     return PTR_ERR(C);
  |
  -C = devm_kzalloc(DEV, ...);
  -if (!C)
  -    return ERR_PTR(-ENOMEM);
  +C = devm_drm_bridge_alloc(DEV, T, BR, FUNCS);
  +if (IS_ERR(C))
  +     return PTR_ERR(C);
  )
   ...
  -C->BR.funcs = FUNCS;

Reviewed-by: Manikandan Muralidharan <manikandan.m at microchip.com> # microchip-lvds.c
Reviewed-by: Douglas Anderson <dianders at chromium.org> # parade-ps8640
Tested-by: Douglas Anderson <dianders at chromium.org> # parade-ps8640
Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
---

Cc: Adam Ford <aford173 at gmail.com>
Cc: Adrien Grassein <adrien.grassein at gmail.com>
Cc: Aleksandr Mishin <amishin at t-argos.ru>
Cc: Andy Yan <andy.yan at rock-chips.com>
Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Cc: Benson Leung <bleung at chromium.org>
Cc: Biju Das <biju.das.jz at bp.renesas.com>
Cc: Christoph Fritz <chf.fritz at googlemail.com>
Cc: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
Cc: Detlev Casanova <detlev.casanova at collabora.com>
Cc: Dharma Balasubiramani <dharma.b at microchip.com>
Cc: Guenter Roeck <groeck at chromium.org>
Cc: Heiko Stuebner <heiko at sntech.de>
Cc: Jani Nikula <jani.nikula at intel.com>
Cc: Janne Grunau <j at jannau.net>
Cc: Jerome Brunet <jbrunet at baylibre.com>
Cc: Jesse Van Gavere <jesseevg at gmail.com>
Cc: Kevin Hilman <khilman at baylibre.com>
Cc: Kieran Bingham <kieran.bingham+renesas at ideasonboard.com>
Cc: Liu Ying <victor.liu at nxp.com>
Cc: Manikandan Muralidharan <manikandan.m at microchip.com>
Cc: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
Cc: Matthias Brugger <matthias.bgg at gmail.com>
Cc: Philipp Zabel <p.zabel at pengutronix.de>
Cc: Phong LE <ple at baylibre.com>
Cc: Sasha Finkelstein <fnkl.kernel at gmail.com>
Cc: Sugar Zhang <sugar.zhang at rock-chips.com>
Cc: Sui Jingfeng <sui.jingfeng at linux.dev>
Cc: Tomi Valkeinen <tomi.valkeinen+renesas at ideasonboard.com>
Cc: Vitalii Mordan <mordan at ispras.ru>

Changed in v3:
- manually replaced PTR_ERR() with ERR_CAST() in the 4 cases where the
  return value is not int
- manually added empty lines and comments that the spatch had removed
  inappropriately
- improved commit message

Changed in v2:
- added missing PTR_ERR() in the second spatch alternative
---
 drivers/gpu/drm/adp/adp-mipi.c                      |  8 ++++----
 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c        |  8 ++++----
 drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c  |  9 ++++-----
 drivers/gpu/drm/bridge/aux-bridge.c                 |  8 ++++----
 drivers/gpu/drm/bridge/aux-hpd-bridge.c             |  9 +++++----
 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c |  8 ++++----
 drivers/gpu/drm/bridge/chipone-icn6211.c            |  8 ++++----
 drivers/gpu/drm/bridge/chrontel-ch7033.c            |  8 ++++----
 drivers/gpu/drm/bridge/cros-ec-anx7688.c            |  8 ++++----
 drivers/gpu/drm/bridge/fsl-ldb.c                    |  7 +++----
 drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c      |  8 ++++----
 drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c        |  8 ++++----
 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c     |  8 ++++----
 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c        |  8 ++++----
 drivers/gpu/drm/bridge/ite-it6263.c                 |  8 ++++----
 drivers/gpu/drm/bridge/ite-it6505.c                 |  8 ++++----
 drivers/gpu/drm/bridge/ite-it66121.c                |  8 ++++----
 drivers/gpu/drm/bridge/lontium-lt8912b.c            |  8 ++++----
 drivers/gpu/drm/bridge/lontium-lt9211.c             |  7 +++----
 drivers/gpu/drm/bridge/lontium-lt9611.c             |  8 ++++----
 drivers/gpu/drm/bridge/lvds-codec.c                 |  9 ++++-----
 drivers/gpu/drm/bridge/microchip-lvds.c             |  8 ++++----
 drivers/gpu/drm/bridge/nwl-dsi.c                    |  8 ++++----
 drivers/gpu/drm/bridge/parade-ps8622.c              |  8 ++++----
 drivers/gpu/drm/bridge/parade-ps8640.c              |  8 ++++----
 drivers/gpu/drm/bridge/sii9234.c                    |  8 ++++----
 drivers/gpu/drm/bridge/sil-sii8620.c                |  8 ++++----
 drivers/gpu/drm/bridge/simple-bridge.c              |  8 ++++----
 drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c        |  8 ++++----
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c       |  8 ++++----
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c      |  8 ++++----
 drivers/gpu/drm/bridge/tc358762.c                   |  8 ++++----
 drivers/gpu/drm/bridge/tc358764.c                   |  8 ++++----
 drivers/gpu/drm/bridge/tc358768.c                   |  8 ++++----
 drivers/gpu/drm/bridge/tc358775.c                   |  8 ++++----
 drivers/gpu/drm/bridge/thc63lvd1024.c               |  8 ++++----
 drivers/gpu/drm/bridge/ti-dlpc3433.c                |  8 ++++----
 drivers/gpu/drm/bridge/ti-tdp158.c                  |  8 ++++----
 drivers/gpu/drm/bridge/ti-tfp410.c                  |  8 ++++----
 drivers/gpu/drm/bridge/ti-tpd12s015.c               |  8 ++++----
 drivers/gpu/drm/mediatek/mtk_dp.c                   |  8 ++++----
 drivers/gpu/drm/mediatek/mtk_dpi.c                  |  8 ++++----
 drivers/gpu/drm/mediatek/mtk_dsi.c                  |  8 ++++----
 drivers/gpu/drm/mediatek/mtk_hdmi.c                 |  8 ++++----
 drivers/gpu/drm/meson/meson_encoder_cvbs.c          | 10 ++++++----
 drivers/gpu/drm/meson/meson_encoder_dsi.c           | 10 ++++++----
 drivers/gpu/drm/meson/meson_encoder_hdmi.c          | 10 ++++++----
 drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c         |  8 ++++----
 drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c      |  8 ++++----
 49 files changed, 201 insertions(+), 198 deletions(-)

diff --git a/drivers/gpu/drm/adp/adp-mipi.c b/drivers/gpu/drm/adp/adp-mipi.c
index 2b60128e2c693e9f85affff569cc57cdb6f47909..cba7d32150a98d78d07a25b1822dec6bf2f08f65 100644
--- a/drivers/gpu/drm/adp/adp-mipi.c
+++ b/drivers/gpu/drm/adp/adp-mipi.c
@@ -229,9 +229,10 @@ static int adp_mipi_probe(struct platform_device *pdev)
 {
 	struct adp_mipi_drv_private *adp;
 
-	adp = devm_kzalloc(&pdev->dev, sizeof(*adp), GFP_KERNEL);
-	if (!adp)
-		return -ENOMEM;
+	adp = devm_drm_bridge_alloc(&pdev->dev, struct adp_mipi_drv_private,
+				    bridge, &adp_dsi_bridge_funcs);
+	if (IS_ERR(adp))
+		return PTR_ERR(adp);
 
 	adp->mipi = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(adp->mipi)) {
@@ -241,7 +242,6 @@ static int adp_mipi_probe(struct platform_device *pdev)
 
 	adp->dsi.dev = &pdev->dev;
 	adp->dsi.ops = &adp_dsi_host_ops;
-	adp->bridge.funcs = &adp_dsi_bridge_funcs;
 	adp->bridge.of_node = pdev->dev.of_node;
 	adp->bridge.type = DRM_MODE_CONNECTOR_DSI;
 	dev_set_drvdata(&pdev->dev, adp);
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index 1257009e850c1b20184cfaea5b6a4440e75e10d7..8d7b007ea203d0d8be8f5b145f8531e23294dacc 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
@@ -1224,9 +1224,10 @@ static int adv7511_probe(struct i2c_client *i2c)
 	if (!dev->of_node)
 		return -EINVAL;
 
-	adv7511 = devm_kzalloc(dev, sizeof(*adv7511), GFP_KERNEL);
-	if (!adv7511)
-		return -ENOMEM;
+	adv7511 = devm_drm_bridge_alloc(dev, struct adv7511, bridge,
+					&adv7511_bridge_funcs);
+	if (IS_ERR(adv7511))
+		return PTR_ERR(adv7511);
 
 	adv7511->i2c_main = i2c;
 	adv7511->powered = false;
@@ -1327,7 +1328,6 @@ static int adv7511_probe(struct i2c_client *i2c)
 	if (ret)
 		goto err_unregister_cec;
 
-	adv7511->bridge.funcs = &adv7511_bridge_funcs;
 	adv7511->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID;
 	if (adv7511->i2c_main->irq)
 		adv7511->bridge.ops |= DRM_BRIDGE_OP_HPD;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
index a83020d6576f78372056069947783a626acf64b1..ba0fc149a9e722a53da6027a851bf62262ba64b2 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
@@ -1193,9 +1193,10 @@ static int anx78xx_i2c_probe(struct i2c_client *client)
 	bool found = false;
 	int err;
 
-	anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL);
-	if (!anx78xx)
-		return -ENOMEM;
+	anx78xx = devm_drm_bridge_alloc(&client->dev, struct anx78xx, bridge,
+					&anx78xx_bridge_funcs);
+	if (IS_ERR(anx78xx))
+		return PTR_ERR(anx78xx);
 
 	pdata = &anx78xx->pdata;
 
@@ -1306,8 +1307,6 @@ static int anx78xx_i2c_probe(struct i2c_client *client)
 		goto err_poweroff;
 	}
 
-	anx78xx->bridge.funcs = &anx78xx_bridge_funcs;
-
 	drm_bridge_add(&anx78xx->bridge);
 
 	/* If cable is pulled out, just poweroff and wait for HPD event */
diff --git a/drivers/gpu/drm/bridge/aux-bridge.c b/drivers/gpu/drm/bridge/aux-bridge.c
index c179b86d208f70d95b41e6f2157b78f97bac4d8d..5b219e3b87b1df9fc4aaf2c8a6e78bac8f894628 100644
--- a/drivers/gpu/drm/bridge/aux-bridge.c
+++ b/drivers/gpu/drm/bridge/aux-bridge.c
@@ -109,9 +109,10 @@ static int drm_aux_bridge_probe(struct auxiliary_device *auxdev,
 {
 	struct drm_aux_bridge_data *data;
 
-	data = devm_kzalloc(&auxdev->dev, sizeof(*data), GFP_KERNEL);
-	if (!data)
-		return -ENOMEM;
+	data = devm_drm_bridge_alloc(&auxdev->dev, struct drm_aux_bridge_data,
+				     bridge, &drm_aux_bridge_funcs);
+	if (IS_ERR(data))
+		return PTR_ERR(data);
 
 	data->dev = &auxdev->dev;
 	data->next_bridge = devm_drm_of_get_bridge(&auxdev->dev, auxdev->dev.of_node, 0, 0);
@@ -119,7 +120,6 @@ static int drm_aux_bridge_probe(struct auxiliary_device *auxdev,
 		return dev_err_probe(&auxdev->dev, PTR_ERR(data->next_bridge),
 				     "failed to acquire drm_bridge\n");
 
-	data->bridge.funcs = &drm_aux_bridge_funcs;
 	data->bridge.of_node = data->dev->of_node;
 
 	/* passthrough data, allow everything */
diff --git a/drivers/gpu/drm/bridge/aux-hpd-bridge.c b/drivers/gpu/drm/bridge/aux-hpd-bridge.c
index b3f588b71a7d7ad5c2ee7b07c39079bc5ba34cee..3eb411f874e41b322f732649bd2074c5d8422566 100644
--- a/drivers/gpu/drm/bridge/aux-hpd-bridge.c
+++ b/drivers/gpu/drm/bridge/aux-hpd-bridge.c
@@ -171,12 +171,13 @@ static int drm_aux_hpd_bridge_probe(struct auxiliary_device *auxdev,
 {
 	struct drm_aux_hpd_bridge_data *data;
 
-	data = devm_kzalloc(&auxdev->dev, sizeof(*data), GFP_KERNEL);
-	if (!data)
-		return -ENOMEM;
+	data = devm_drm_bridge_alloc(&auxdev->dev,
+				     struct drm_aux_hpd_bridge_data, bridge,
+				     &drm_aux_hpd_bridge_funcs);
+	if (IS_ERR(data))
+		return PTR_ERR(data);
 
 	data->dev = &auxdev->dev;
-	data->bridge.funcs = &drm_aux_hpd_bridge_funcs;
 	data->bridge.of_node = dev_get_platdata(data->dev);
 	data->bridge.ops = DRM_BRIDGE_OP_HPD;
 	data->bridge.type = id->driver_data;
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index b431e7efd1f0d749320ea15b6f1f5ca13fc72800..cb5f5a8c539a471290df8435d4c2e3ed696b38d4 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -2389,9 +2389,10 @@ static int cdns_mhdp_probe(struct platform_device *pdev)
 	int ret;
 	int irq;
 
-	mhdp = devm_kzalloc(dev, sizeof(*mhdp), GFP_KERNEL);
-	if (!mhdp)
-		return -ENOMEM;
+	mhdp = devm_drm_bridge_alloc(dev, struct cdns_mhdp_device, bridge,
+				     &cdns_mhdp_bridge_funcs);
+	if (IS_ERR(mhdp))
+		return PTR_ERR(mhdp);
 
 	clk = devm_clk_get_enabled(dev, NULL);
 	if (IS_ERR(clk)) {
@@ -2481,7 +2482,6 @@ static int cdns_mhdp_probe(struct platform_device *pdev)
 	mhdp->display_fmt.bpc = 8;
 
 	mhdp->bridge.of_node = pdev->dev.of_node;
-	mhdp->bridge.funcs = &cdns_mhdp_bridge_funcs;
 	mhdp->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
 			   DRM_BRIDGE_OP_HPD;
 	mhdp->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c b/drivers/gpu/drm/bridge/chipone-icn6211.c
index 634c5b0306679d2e68798c2b9013aae4491dd44c..814713c5bea97dcdc2b847d2f266a567ef40e981 100644
--- a/drivers/gpu/drm/bridge/chipone-icn6211.c
+++ b/drivers/gpu/drm/bridge/chipone-icn6211.c
@@ -691,9 +691,10 @@ static int chipone_common_probe(struct device *dev, struct chipone **icnr)
 	struct chipone *icn;
 	int ret;
 
-	icn = devm_kzalloc(dev, sizeof(struct chipone), GFP_KERNEL);
-	if (!icn)
-		return -ENOMEM;
+	icn = devm_drm_bridge_alloc(dev, struct chipone, bridge,
+				    &chipone_bridge_funcs);
+	if (IS_ERR(icn))
+		return PTR_ERR(icn);
 
 	icn->dev = dev;
 
@@ -701,7 +702,6 @@ static int chipone_common_probe(struct device *dev, struct chipone **icnr)
 	if (ret)
 		return ret;
 
-	icn->bridge.funcs = &chipone_bridge_funcs;
 	icn->bridge.type = DRM_MODE_CONNECTOR_DPI;
 	icn->bridge.of_node = dev->of_node;
 
diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c b/drivers/gpu/drm/bridge/chrontel-ch7033.c
index 210c45c1efd48f5b541bf73da66a169c27e110b2..ab92747933568bfba77da45219e019408029f297 100644
--- a/drivers/gpu/drm/bridge/chrontel-ch7033.c
+++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
@@ -536,9 +536,10 @@ static int ch7033_probe(struct i2c_client *client)
 	unsigned int val;
 	int ret;
 
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
+	priv = devm_drm_bridge_alloc(dev, struct ch7033_priv, bridge,
+				     &ch7033_bridge_funcs);
+	if (IS_ERR(priv))
+		return PTR_ERR(priv);
 
 	dev_set_drvdata(dev, priv);
 
@@ -575,7 +576,6 @@ static int ch7033_probe(struct i2c_client *client)
 	}
 
 	INIT_LIST_HEAD(&priv->bridge.list);
-	priv->bridge.funcs = &ch7033_bridge_funcs;
 	priv->bridge.of_node = dev->of_node;
 	drm_bridge_add(&priv->bridge);
 
diff --git a/drivers/gpu/drm/bridge/cros-ec-anx7688.c b/drivers/gpu/drm/bridge/cros-ec-anx7688.c
index c8abd9920fee956cf049bcb09827d658b7939333..a35dae9b56e247d43cac317d8bf1f904d5e7435e 100644
--- a/drivers/gpu/drm/bridge/cros-ec-anx7688.c
+++ b/drivers/gpu/drm/bridge/cros-ec-anx7688.c
@@ -103,9 +103,10 @@ static int cros_ec_anx7688_bridge_probe(struct i2c_client *client)
 	u8 buffer[4];
 	int ret;
 
-	anx7688 = devm_kzalloc(dev, sizeof(*anx7688), GFP_KERNEL);
-	if (!anx7688)
-		return -ENOMEM;
+	anx7688 = devm_drm_bridge_alloc(dev, struct cros_ec_anx7688, bridge,
+					&cros_ec_anx7688_bridge_funcs);
+	if (IS_ERR(anx7688))
+		return PTR_ERR(anx7688);
 
 	anx7688->client = client;
 	i2c_set_clientdata(client, anx7688);
@@ -153,7 +154,6 @@ static int cros_ec_anx7688_bridge_probe(struct i2c_client *client)
 		DRM_WARN("Old ANX7688 FW version (0x%04x), not filtering\n",
 			 fw_version);
 
-	anx7688->bridge.funcs = &cros_ec_anx7688_bridge_funcs;
 	drm_bridge_add(&anx7688->bridge);
 
 	return 0;
diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index 2cb6dfc7a6d3dbdd620a35345204f8fb9cae6651..5c3cf37200bcee1db285c97e2b463c9355ee6acb 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -298,16 +298,15 @@ static int fsl_ldb_probe(struct platform_device *pdev)
 	struct fsl_ldb *fsl_ldb;
 	int dual_link;
 
-	fsl_ldb = devm_kzalloc(dev, sizeof(*fsl_ldb), GFP_KERNEL);
-	if (!fsl_ldb)
-		return -ENOMEM;
+	fsl_ldb = devm_drm_bridge_alloc(dev, struct fsl_ldb, bridge, &funcs);
+	if (IS_ERR(fsl_ldb))
+		return PTR_ERR(fsl_ldb);
 
 	fsl_ldb->devdata = of_device_get_match_data(dev);
 	if (!fsl_ldb->devdata)
 		return -EINVAL;
 
 	fsl_ldb->dev = &pdev->dev;
-	fsl_ldb->bridge.funcs = &funcs;
 	fsl_ldb->bridge.of_node = dev->of_node;
 
 	fsl_ldb->clk = devm_clk_get(dev, "ldb");
diff --git a/drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c b/drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c
index f072c6ed39ef183b10518b43bd6d979bc89e36f9..989bc497b05071af2a92c750d907addcfe783858 100644
--- a/drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c
+++ b/drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c
@@ -59,9 +59,10 @@ struct drm_bridge *devm_imx_drm_legacy_bridge(struct device *dev,
 	struct imx_legacy_bridge *imx_bridge;
 	int ret;
 
-	imx_bridge = devm_kzalloc(dev, sizeof(*imx_bridge), GFP_KERNEL);
-	if (!imx_bridge)
-		return ERR_PTR(-ENOMEM);
+	imx_bridge = devm_drm_bridge_alloc(dev, struct imx_legacy_bridge,
+					   base, &imx_legacy_bridge_funcs);
+	if (IS_ERR(imx_bridge))
+		return ERR_CAST(imx_bridge);
 
 	ret = of_get_drm_display_mode(np,
 				      &imx_bridge->mode,
@@ -72,7 +73,6 @@ struct drm_bridge *devm_imx_drm_legacy_bridge(struct device *dev,
 
 	imx_bridge->mode.type |= DRM_MODE_TYPE_DRIVER;
 
-	imx_bridge->base.funcs = &imx_legacy_bridge_funcs;
 	imx_bridge->base.of_node = np;
 	imx_bridge->base.ops = DRM_BRIDGE_OP_MODES;
 	imx_bridge->base.type = type;
diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
index 8a4fd7d77a8d516b3b46f41cf07d2633d23bde12..3a6f8587a257c3ceacefbed1b37024289617b7c1 100644
--- a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
+++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
@@ -140,9 +140,10 @@ static int imx8mp_hdmi_pvi_probe(struct platform_device *pdev)
 	struct device_node *remote;
 	struct imx8mp_hdmi_pvi *pvi;
 
-	pvi = devm_kzalloc(&pdev->dev, sizeof(*pvi), GFP_KERNEL);
-	if (!pvi)
-		return -ENOMEM;
+	pvi = devm_drm_bridge_alloc(&pdev->dev, struct imx8mp_hdmi_pvi,
+				    bridge, &imx_hdmi_pvi_bridge_funcs);
+	if (IS_ERR(pvi))
+		return PTR_ERR(pvi);
 
 	platform_set_drvdata(pdev, pvi);
 	pvi->dev = &pdev->dev;
@@ -166,7 +167,6 @@ static int imx8mp_hdmi_pvi_probe(struct platform_device *pdev)
 	pm_runtime_enable(&pdev->dev);
 
 	/* Register the bridge. */
-	pvi->bridge.funcs = &imx_hdmi_pvi_bridge_funcs;
 	pvi->bridge.of_node = pdev->dev.of_node;
 	pvi->bridge.timings = pvi->next_bridge->timings;
 
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
index e092c9ea99b0224802919ff84b448acb53508951..e5943506981dfb8f113c94ad52ddbba52e00ec3f 100644
--- a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
@@ -327,9 +327,10 @@ static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev)
 	struct device_node *np = dev->of_node;
 	int ret;
 
-	pl = devm_kzalloc(dev, sizeof(*pl), GFP_KERNEL);
-	if (!pl)
-		return -ENOMEM;
+	pl = devm_drm_bridge_alloc(dev, struct imx8qxp_pixel_link, bridge,
+				   &imx8qxp_pixel_link_bridge_funcs);
+	if (IS_ERR(pl))
+		return PTR_ERR(pl);
 
 	ret = imx_scu_get_handle(&pl->ipc_handle);
 	if (ret) {
@@ -384,7 +385,6 @@ static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, pl);
 
 	pl->bridge.driver_private = pl;
-	pl->bridge.funcs = &imx8qxp_pixel_link_bridge_funcs;
 	pl->bridge.of_node = np;
 
 	drm_bridge_add(&pl->bridge);
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
index da138ab51b3bd2c6ebd3780c09818891d5320092..111310acab2ce403a62a47ecbe9d9dd372c75ecd 100644
--- a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
@@ -392,9 +392,10 @@ static int imx8qxp_pxl2dpi_bridge_probe(struct platform_device *pdev)
 	struct device_node *np = dev->of_node;
 	int ret;
 
-	p2d = devm_kzalloc(dev, sizeof(*p2d), GFP_KERNEL);
-	if (!p2d)
-		return -ENOMEM;
+	p2d = devm_drm_bridge_alloc(dev, struct imx8qxp_pxl2dpi, bridge,
+				    &imx8qxp_pxl2dpi_bridge_funcs);
+	if (IS_ERR(p2d))
+		return PTR_ERR(p2d);
 
 	p2d->regmap = syscon_node_to_regmap(np->parent);
 	if (IS_ERR(p2d->regmap)) {
@@ -441,7 +442,6 @@ static int imx8qxp_pxl2dpi_bridge_probe(struct platform_device *pdev)
 	pm_runtime_enable(dev);
 
 	p2d->bridge.driver_private = p2d;
-	p2d->bridge.funcs = &imx8qxp_pxl2dpi_bridge_funcs;
 	p2d->bridge.of_node = np;
 
 	drm_bridge_add(&p2d->bridge);
diff --git a/drivers/gpu/drm/bridge/ite-it6263.c b/drivers/gpu/drm/bridge/ite-it6263.c
index a3a63a977b0a8487ad38fc08e0eed08672f4d41a..c4eedf643f39e9b91efeb5a6214bf2fe6f2c040a 100644
--- a/drivers/gpu/drm/bridge/ite-it6263.c
+++ b/drivers/gpu/drm/bridge/ite-it6263.c
@@ -816,9 +816,10 @@ static int it6263_probe(struct i2c_client *client)
 	struct it6263 *it;
 	int ret;
 
-	it = devm_kzalloc(dev, sizeof(*it), GFP_KERNEL);
-	if (!it)
-		return -ENOMEM;
+	it = devm_drm_bridge_alloc(dev, struct it6263, bridge,
+				   &it6263_bridge_funcs);
+	if (IS_ERR(it))
+		return PTR_ERR(it);
 
 	it->dev = dev;
 	it->hdmi_i2c = client;
@@ -866,7 +867,6 @@ static int it6263_probe(struct i2c_client *client)
 
 	i2c_set_clientdata(client, it);
 
-	it->bridge.funcs = &it6263_bridge_funcs;
 	it->bridge.of_node = dev->of_node;
 	/* IT6263 chip doesn't support HPD interrupt. */
 	it->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c
index 1383d1e21afea1acb46b7bd28860908b58832dbc..b0dc9280d870c4864d43984999238e8a34bf47df 100644
--- a/drivers/gpu/drm/bridge/ite-it6505.c
+++ b/drivers/gpu/drm/bridge/ite-it6505.c
@@ -3583,9 +3583,10 @@ static int it6505_i2c_probe(struct i2c_client *client)
 	struct extcon_dev *extcon;
 	int err;
 
-	it6505 = devm_kzalloc(&client->dev, sizeof(*it6505), GFP_KERNEL);
-	if (!it6505)
-		return -ENOMEM;
+	it6505 = devm_drm_bridge_alloc(&client->dev, struct it6505, bridge,
+				       &it6505_bridge_funcs);
+	if (IS_ERR(it6505))
+		return PTR_ERR(it6505);
 
 	mutex_init(&it6505->extcon_lock);
 	mutex_init(&it6505->mode_lock);
@@ -3660,7 +3661,6 @@ static int it6505_i2c_probe(struct i2c_client *client)
 	it6505->aux.transfer = it6505_aux_transfer;
 	drm_dp_aux_init(&it6505->aux);
 
-	it6505->bridge.funcs = &it6505_bridge_funcs;
 	it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
 	it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
 			     DRM_BRIDGE_OP_HPD;
diff --git a/drivers/gpu/drm/bridge/ite-it66121.c b/drivers/gpu/drm/bridge/ite-it66121.c
index 7b110ae532918d2d6f91ebc5f747c38e7e77dc07..6494f0842793829b7658b330338767e5b38a1115 100644
--- a/drivers/gpu/drm/bridge/ite-it66121.c
+++ b/drivers/gpu/drm/bridge/ite-it66121.c
@@ -1516,9 +1516,10 @@ static int it66121_probe(struct i2c_client *client)
 		return -ENXIO;
 	}
 
-	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
-	if (!ctx)
-		return -ENOMEM;
+	ctx = devm_drm_bridge_alloc(dev, struct it66121_ctx, bridge,
+				    &it66121_bridge_funcs);
+	if (IS_ERR(ctx))
+		return PTR_ERR(ctx);
 
 	ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
 	if (!ep)
@@ -1577,7 +1578,6 @@ static int it66121_probe(struct i2c_client *client)
 		return -ENODEV;
 	}
 
-	ctx->bridge.funcs = &it66121_bridge_funcs;
 	ctx->bridge.of_node = dev->of_node;
 	ctx->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
 	ctx->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID;
diff --git a/drivers/gpu/drm/bridge/lontium-lt8912b.c b/drivers/gpu/drm/bridge/lontium-lt8912b.c
index 3e49d855b3648880cea9bce5f3f04fbb6f838a45..bd83228b0f0eb49062ee84f62f8ae50b78bbfb0e 100644
--- a/drivers/gpu/drm/bridge/lontium-lt8912b.c
+++ b/drivers/gpu/drm/bridge/lontium-lt8912b.c
@@ -761,9 +761,10 @@ static int lt8912_probe(struct i2c_client *client)
 	int ret = 0;
 	struct device *dev = &client->dev;
 
-	lt = devm_kzalloc(dev, sizeof(struct lt8912), GFP_KERNEL);
-	if (!lt)
-		return -ENOMEM;
+	lt = devm_drm_bridge_alloc(dev, struct lt8912, bridge,
+				   &lt8912_bridge_funcs);
+	if (IS_ERR(lt))
+		return PTR_ERR(lt);
 
 	lt->dev = dev;
 	lt->i2c_client[0] = client;
@@ -778,7 +779,6 @@ static int lt8912_probe(struct i2c_client *client)
 
 	i2c_set_clientdata(client, lt);
 
-	lt->bridge.funcs = &lt8912_bridge_funcs;
 	lt->bridge.of_node = dev->of_node;
 	lt->bridge.ops = (DRM_BRIDGE_OP_EDID |
 			  DRM_BRIDGE_OP_DETECT);
diff --git a/drivers/gpu/drm/bridge/lontium-lt9211.c b/drivers/gpu/drm/bridge/lontium-lt9211.c
index 9b2dac9bd63c5afd4ffbafafdbbb1230549bc36f..399fa7eebd49cc3fe9e812517fc3e8ed25004086 100644
--- a/drivers/gpu/drm/bridge/lontium-lt9211.c
+++ b/drivers/gpu/drm/bridge/lontium-lt9211.c
@@ -727,9 +727,9 @@ static int lt9211_probe(struct i2c_client *client)
 	struct lt9211 *ctx;
 	int ret;
 
-	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
-	if (!ctx)
-		return -ENOMEM;
+	ctx = devm_drm_bridge_alloc(dev, struct lt9211, bridge, &lt9211_funcs);
+	if (IS_ERR(ctx))
+		return PTR_ERR(ctx);
 
 	ctx->dev = dev;
 
@@ -755,7 +755,6 @@ static int lt9211_probe(struct i2c_client *client)
 	dev_set_drvdata(dev, ctx);
 	i2c_set_clientdata(client, ctx);
 
-	ctx->bridge.funcs = &lt9211_funcs;
 	ctx->bridge.of_node = dev->of_node;
 	drm_bridge_add(&ctx->bridge);
 
diff --git a/drivers/gpu/drm/bridge/lontium-lt9611.c b/drivers/gpu/drm/bridge/lontium-lt9611.c
index a35a8b8ca89c2cc138a7cb4de01c796c6211d655..d6ee79c1e42771174ee01f17448f1a8fff70b63f 100644
--- a/drivers/gpu/drm/bridge/lontium-lt9611.c
+++ b/drivers/gpu/drm/bridge/lontium-lt9611.c
@@ -1072,9 +1072,10 @@ static int lt9611_probe(struct i2c_client *client)
 		return -ENODEV;
 	}
 
-	lt9611 = devm_kzalloc(dev, sizeof(*lt9611), GFP_KERNEL);
-	if (!lt9611)
-		return -ENOMEM;
+	lt9611 = devm_drm_bridge_alloc(dev, struct lt9611, bridge,
+				       &lt9611_bridge_funcs);
+	if (IS_ERR(lt9611))
+		return PTR_ERR(lt9611);
 
 	lt9611->dev = dev;
 	lt9611->client = client;
@@ -1127,7 +1128,6 @@ static int lt9611_probe(struct i2c_client *client)
 	/* Disable Audio InfoFrame, enabled by default */
 	regmap_update_bits(lt9611->regmap, 0x843d, LT9611_INFOFRAME_AUDIO, 0);
 
-	lt9611->bridge.funcs = &lt9611_bridge_funcs;
 	lt9611->bridge.of_node = client->dev.of_node;
 	lt9611->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
 			     DRM_BRIDGE_OP_HPD | DRM_BRIDGE_OP_MODES |
diff --git a/drivers/gpu/drm/bridge/lvds-codec.c b/drivers/gpu/drm/bridge/lvds-codec.c
index 1646e454e0b0b558d00f9421f15bb7084e2aa45a..e6a7147e141b64fc77dfef03a737ee599a0ecd10 100644
--- a/drivers/gpu/drm/bridge/lvds-codec.c
+++ b/drivers/gpu/drm/bridge/lvds-codec.c
@@ -118,9 +118,10 @@ static int lvds_codec_probe(struct platform_device *pdev)
 	u32 val;
 	int ret;
 
-	lvds_codec = devm_kzalloc(dev, sizeof(*lvds_codec), GFP_KERNEL);
-	if (!lvds_codec)
-		return -ENOMEM;
+	lvds_codec = devm_drm_bridge_alloc(dev, struct lvds_codec, bridge,
+					   &funcs);
+	if (IS_ERR(lvds_codec))
+		return PTR_ERR(lvds_codec);
 
 	lvds_codec->dev = &pdev->dev;
 	lvds_codec->connector_type = (uintptr_t)of_device_get_match_data(dev);
@@ -156,8 +157,6 @@ static int lvds_codec_probe(struct platform_device *pdev)
 	if (IS_ERR(lvds_codec->panel_bridge))
 		return PTR_ERR(lvds_codec->panel_bridge);
 
-	lvds_codec->bridge.funcs = &funcs;
-
 	/*
 	 * Decoder input LVDS format is a property of the decoder chip or even
 	 * its strapping. Handle data-mapping the same way lvds-panel does. In
diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/bridge/microchip-lvds.c
index 1d4ae0097df847d9f93c79eecff0c4587ae331ba..9f4ff82bc6b49010f8727da3b367f5a744a28edc 100644
--- a/drivers/gpu/drm/bridge/microchip-lvds.c
+++ b/drivers/gpu/drm/bridge/microchip-lvds.c
@@ -157,9 +157,10 @@ static int mchp_lvds_probe(struct platform_device *pdev)
 	if (!dev->of_node)
 		return -ENODEV;
 
-	lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
-	if (!lvds)
-		return -ENOMEM;
+	lvds = devm_drm_bridge_alloc(&pdev->dev, struct mchp_lvds, bridge,
+				     &mchp_lvds_bridge_funcs);
+	if (IS_ERR(lvds))
+		return PTR_ERR(lvds);
 
 	lvds->dev = dev;
 
@@ -192,7 +193,6 @@ static int mchp_lvds_probe(struct platform_device *pdev)
 
 	lvds->bridge.of_node = dev->of_node;
 	lvds->bridge.type = DRM_MODE_CONNECTOR_LVDS;
-	lvds->bridge.funcs = &mchp_lvds_bridge_funcs;
 
 	dev_set_drvdata(dev, lvds);
 	ret = devm_pm_runtime_enable(dev);
diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
index 55912ae11f46a1d551e11f93a306a8a00ef3f7d8..2f7429b24fc20db104dec17182f1119c6c75e600 100644
--- a/drivers/gpu/drm/bridge/nwl-dsi.c
+++ b/drivers/gpu/drm/bridge/nwl-dsi.c
@@ -1149,9 +1149,10 @@ static int nwl_dsi_probe(struct platform_device *pdev)
 	struct nwl_dsi *dsi;
 	int ret;
 
-	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
-	if (!dsi)
-		return -ENOMEM;
+	dsi = devm_drm_bridge_alloc(dev, struct nwl_dsi, bridge,
+				    &nwl_dsi_bridge_funcs);
+	if (IS_ERR(dsi))
+		return PTR_ERR(dsi);
 
 	dsi->dev = dev;
 
@@ -1180,7 +1181,6 @@ static int nwl_dsi_probe(struct platform_device *pdev)
 		dsi->quirks = (uintptr_t)attr->data;
 
 	dsi->bridge.driver_private = dsi;
-	dsi->bridge.funcs = &nwl_dsi_bridge_funcs;
 	dsi->bridge.of_node = dev->of_node;
 	dsi->bridge.timings = &nwl_dsi_timings;
 	dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
diff --git a/drivers/gpu/drm/bridge/parade-ps8622.c b/drivers/gpu/drm/bridge/parade-ps8622.c
index 8726fefc5c654e49bce029d943d241789ca4f802..f879a1df077d25d0c5121e51aa067f511a41a9bd 100644
--- a/drivers/gpu/drm/bridge/parade-ps8622.c
+++ b/drivers/gpu/drm/bridge/parade-ps8622.c
@@ -449,9 +449,10 @@ static int ps8622_probe(struct i2c_client *client)
 	struct drm_bridge *panel_bridge;
 	int ret;
 
-	ps8622 = devm_kzalloc(dev, sizeof(*ps8622), GFP_KERNEL);
-	if (!ps8622)
-		return -ENOMEM;
+	ps8622 = devm_drm_bridge_alloc(dev, struct ps8622_bridge, bridge,
+				       &ps8622_bridge_funcs);
+	if (IS_ERR(ps8622))
+		return PTR_ERR(ps8622);
 
 	panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0);
 	if (IS_ERR(panel_bridge))
@@ -509,7 +510,6 @@ static int ps8622_probe(struct i2c_client *client)
 		ps8622->bl->props.brightness = PS8622_MAX_BRIGHTNESS;
 	}
 
-	ps8622->bridge.funcs = &ps8622_bridge_funcs;
 	ps8622->bridge.type = DRM_MODE_CONNECTOR_LVDS;
 	ps8622->bridge.of_node = dev->of_node;
 	drm_bridge_add(&ps8622->bridge);
diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c
index 2422ff68c1042bd8eaa6821ff387d4faad47c550..825777a5758f67b5bdaa5f9de2e0e4f597f0f7a4 100644
--- a/drivers/gpu/drm/bridge/parade-ps8640.c
+++ b/drivers/gpu/drm/bridge/parade-ps8640.c
@@ -636,9 +636,10 @@ static int ps8640_probe(struct i2c_client *client)
 	int ret;
 	u32 i;
 
-	ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
-	if (!ps_bridge)
-		return -ENOMEM;
+	ps_bridge = devm_drm_bridge_alloc(dev, struct ps8640, bridge,
+					  &ps8640_bridge_funcs);
+	if (IS_ERR(ps_bridge))
+		return PTR_ERR(ps_bridge);
 
 	mutex_init(&ps_bridge->aux_lock);
 
@@ -662,7 +663,6 @@ static int ps8640_probe(struct i2c_client *client)
 	if (IS_ERR(ps_bridge->gpio_reset))
 		return PTR_ERR(ps_bridge->gpio_reset);
 
-	ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
 	ps_bridge->bridge.of_node = dev->of_node;
 	ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP;
 
diff --git a/drivers/gpu/drm/bridge/sii9234.c b/drivers/gpu/drm/bridge/sii9234.c
index cd7837c9a6e00b572a3fb65e5e0c9fa884555a73..bb1bed03eb5b7ae67f752c0d593dc54131e9e370 100644
--- a/drivers/gpu/drm/bridge/sii9234.c
+++ b/drivers/gpu/drm/bridge/sii9234.c
@@ -888,9 +888,10 @@ static int sii9234_probe(struct i2c_client *client)
 	struct device *dev = &client->dev;
 	int ret;
 
-	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
-	if (!ctx)
-		return -ENOMEM;
+	ctx = devm_drm_bridge_alloc(dev, struct sii9234, bridge,
+				    &sii9234_bridge_funcs);
+	if (IS_ERR(ctx))
+		return PTR_ERR(ctx);
 
 	ctx->dev = dev;
 	mutex_init(&ctx->lock);
@@ -921,7 +922,6 @@ static int sii9234_probe(struct i2c_client *client)
 
 	i2c_set_clientdata(client, ctx);
 
-	ctx->bridge.funcs = &sii9234_bridge_funcs;
 	ctx->bridge.of_node = dev->of_node;
 	drm_bridge_add(&ctx->bridge);
 
diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c
index 3af650dc92a1612ca88fe378319519546b79901f..9e48ad39e1cc995768d767c27b8116d7baa2f47e 100644
--- a/drivers/gpu/drm/bridge/sil-sii8620.c
+++ b/drivers/gpu/drm/bridge/sil-sii8620.c
@@ -2291,9 +2291,10 @@ static int sii8620_probe(struct i2c_client *client)
 	struct sii8620 *ctx;
 	int ret;
 
-	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
-	if (!ctx)
-		return -ENOMEM;
+	ctx = devm_drm_bridge_alloc(dev, struct sii8620, bridge,
+				    &sii8620_bridge_funcs);
+	if (IS_ERR(ctx))
+		return PTR_ERR(ctx);
 
 	ctx->dev = dev;
 	mutex_init(&ctx->lock);
@@ -2336,7 +2337,6 @@ static int sii8620_probe(struct i2c_client *client)
 
 	i2c_set_clientdata(client, ctx);
 
-	ctx->bridge.funcs = &sii8620_bridge_funcs;
 	ctx->bridge.of_node = dev->of_node;
 	drm_bridge_add(&ctx->bridge);
 
diff --git a/drivers/gpu/drm/bridge/simple-bridge.c b/drivers/gpu/drm/bridge/simple-bridge.c
index 70db5b99e5bb84f099ec54cf62abbda53475311d..c66bd913e33ae311a980251348199889ef5b99af 100644
--- a/drivers/gpu/drm/bridge/simple-bridge.c
+++ b/drivers/gpu/drm/bridge/simple-bridge.c
@@ -168,9 +168,10 @@ static int simple_bridge_probe(struct platform_device *pdev)
 	struct simple_bridge *sbridge;
 	struct device_node *remote;
 
-	sbridge = devm_kzalloc(&pdev->dev, sizeof(*sbridge), GFP_KERNEL);
-	if (!sbridge)
-		return -ENOMEM;
+	sbridge = devm_drm_bridge_alloc(&pdev->dev, struct simple_bridge,
+					bridge, &simple_bridge_bridge_funcs);
+	if (IS_ERR(sbridge))
+		return PTR_ERR(sbridge);
 
 	sbridge->info = of_device_get_match_data(&pdev->dev);
 
@@ -204,7 +205,6 @@ static int simple_bridge_probe(struct platform_device *pdev)
 				     "Unable to retrieve enable GPIO\n");
 
 	/* Register the bridge. */
-	sbridge->bridge.funcs = &simple_bridge_bridge_funcs;
 	sbridge->bridge.of_node = pdev->dev.of_node;
 	sbridge->bridge.timings = sbridge->info->timings;
 
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
index 5e5f8c2f95be1f5c4633f1093b17a00f9425bb37..94dddaf49b3c1fa115f376e5cf1c2f515f2594ea 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
@@ -1045,9 +1045,10 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
 		return ERR_PTR(-ENODEV);
 	}
 
-	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
-	if (!hdmi)
-		return ERR_PTR(-ENOMEM);
+	hdmi = devm_drm_bridge_alloc(dev, struct dw_hdmi_qp, bridge,
+				     &dw_hdmi_qp_bridge_funcs);
+	if (IS_ERR(hdmi))
+		return ERR_CAST(hdmi);
 
 	hdmi->dev = dev;
 
@@ -1073,7 +1074,6 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
 		return ERR_PTR(ret);
 
 	hdmi->bridge.driver_private = hdmi;
-	hdmi->bridge.funcs = &dw_hdmi_qp_bridge_funcs;
 	hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT |
 			   DRM_BRIDGE_OP_EDID |
 			   DRM_BRIDGE_OP_HDMI |
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index b08ada920a501d6a62f39581944a87019f5e5c15..c0dc0f2976b92f5a4eb2416de8f510ec7214e562 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -1194,9 +1194,10 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
 	struct dw_mipi_dsi *dsi;
 	int ret;
 
-	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
-	if (!dsi)
-		return ERR_PTR(-ENOMEM);
+	dsi = devm_drm_bridge_alloc(dev, struct dw_mipi_dsi, bridge,
+				    &dw_mipi_dsi_bridge_funcs);
+	if (IS_ERR(dsi))
+		return ERR_CAST(dsi);
 
 	dsi->dev = dev;
 	dsi->plat_data = plat_data;
@@ -1265,7 +1266,6 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
 	}
 
 	dsi->bridge.driver_private = dsi;
-	dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
 	dsi->bridge.of_node = pdev->dev.of_node;
 
 	return dsi;
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
index c76f5f2e74d14bd372f969c6c7832aa57f80772b..fc91aca95d126ae37726ccd939fdc8657151ca81 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
@@ -914,9 +914,10 @@ __dw_mipi_dsi2_probe(struct platform_device *pdev,
 	struct dw_mipi_dsi2 *dsi2;
 	int ret;
 
-	dsi2 = devm_kzalloc(dev, sizeof(*dsi2), GFP_KERNEL);
-	if (!dsi2)
-		return ERR_PTR(-ENOMEM);
+	dsi2 = devm_drm_bridge_alloc(dev, struct dw_mipi_dsi2, bridge,
+				     &dw_mipi_dsi2_bridge_funcs);
+	if (IS_ERR(dsi2))
+		return ERR_CAST(dsi2);
 
 	dsi2->dev = dev;
 	dsi2->plat_data = plat_data;
@@ -981,7 +982,6 @@ __dw_mipi_dsi2_probe(struct platform_device *pdev,
 	}
 
 	dsi2->bridge.driver_private = dsi2;
-	dsi2->bridge.funcs = &dw_mipi_dsi2_bridge_funcs;
 	dsi2->bridge.of_node = pdev->dev.of_node;
 
 	return dsi2;
diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc358762.c
index edf01476f2ef6e05ef2c144ff4467e7f6babc4c6..98df3e667d4aac48c19c82c8bc9e116b36a4cec8 100644
--- a/drivers/gpu/drm/bridge/tc358762.c
+++ b/drivers/gpu/drm/bridge/tc358762.c
@@ -265,9 +265,10 @@ static int tc358762_probe(struct mipi_dsi_device *dsi)
 	struct tc358762 *ctx;
 	int ret;
 
-	ctx = devm_kzalloc(dev, sizeof(struct tc358762), GFP_KERNEL);
-	if (!ctx)
-		return -ENOMEM;
+	ctx = devm_drm_bridge_alloc(dev, struct tc358762, bridge,
+				    &tc358762_bridge_funcs);
+	if (IS_ERR(ctx))
+		return PTR_ERR(ctx);
 
 	mipi_dsi_set_drvdata(dsi, ctx);
 
@@ -288,7 +289,6 @@ static int tc358762_probe(struct mipi_dsi_device *dsi)
 	if (ret < 0)
 		return ret;
 
-	ctx->bridge.funcs = &tc358762_bridge_funcs;
 	ctx->bridge.type = DRM_MODE_CONNECTOR_DPI;
 	ctx->bridge.of_node = dev->of_node;
 	ctx->bridge.pre_enable_prev_first = true;
diff --git a/drivers/gpu/drm/bridge/tc358764.c b/drivers/gpu/drm/bridge/tc358764.c
index 3f76c890fad9ffa50dc02f289a37378332830516..084e9d898e226ecfa618a3c91c0786d2f83fa51b 100644
--- a/drivers/gpu/drm/bridge/tc358764.c
+++ b/drivers/gpu/drm/bridge/tc358764.c
@@ -347,9 +347,10 @@ static int tc358764_probe(struct mipi_dsi_device *dsi)
 	struct tc358764 *ctx;
 	int ret;
 
-	ctx = devm_kzalloc(dev, sizeof(struct tc358764), GFP_KERNEL);
-	if (!ctx)
-		return -ENOMEM;
+	ctx = devm_drm_bridge_alloc(dev, struct tc358764, bridge,
+				    &tc358764_bridge_funcs);
+	if (IS_ERR(ctx))
+		return PTR_ERR(ctx);
 
 	mipi_dsi_set_drvdata(dsi, ctx);
 
@@ -368,7 +369,6 @@ static int tc358764_probe(struct mipi_dsi_device *dsi)
 	if (ret < 0)
 		return ret;
 
-	ctx->bridge.funcs = &tc358764_bridge_funcs;
 	ctx->bridge.of_node = dev->of_node;
 	ctx->bridge.pre_enable_prev_first = true;
 
diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c
index 063f217a17b6cf32e9793b8a96a5ac6128584098..fbdc44e162293f2f9b090bc956604184a2a406b2 100644
--- a/drivers/gpu/drm/bridge/tc358768.c
+++ b/drivers/gpu/drm/bridge/tc358768.c
@@ -1287,9 +1287,10 @@ static int tc358768_i2c_probe(struct i2c_client *client)
 	if (!np)
 		return -ENODEV;
 
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
+	priv = devm_drm_bridge_alloc(dev, struct tc358768_priv, bridge,
+				     &tc358768_bridge_funcs);
+	if (IS_ERR(priv))
+		return PTR_ERR(priv);
 
 	dev_set_drvdata(dev, priv);
 	priv->dev = dev;
@@ -1321,7 +1322,6 @@ static int tc358768_i2c_probe(struct i2c_client *client)
 	priv->dsi_host.dev = dev;
 	priv->dsi_host.ops = &tc358768_dsi_host_ops;
 
-	priv->bridge.funcs = &tc358768_bridge_funcs;
 	priv->bridge.timings = &default_tc358768_timings;
 	priv->bridge.of_node = np;
 
diff --git a/drivers/gpu/drm/bridge/tc358775.c b/drivers/gpu/drm/bridge/tc358775.c
index 1b10e6ee1724ffb4bb8946f86d2f18e53428381a..366b12db0e7cbfb45b3dfc2a83a7af580cfde41f 100644
--- a/drivers/gpu/drm/bridge/tc358775.c
+++ b/drivers/gpu/drm/bridge/tc358775.c
@@ -659,9 +659,10 @@ static int tc_probe(struct i2c_client *client)
 	struct tc_data *tc;
 	int ret;
 
-	tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
-	if (!tc)
-		return -ENOMEM;
+	tc = devm_drm_bridge_alloc(dev, struct tc_data, bridge,
+				   &tc_bridge_funcs);
+	if (IS_ERR(tc))
+		return PTR_ERR(tc);
 
 	tc->dev = dev;
 	tc->i2c = client;
@@ -701,7 +702,6 @@ static int tc_probe(struct i2c_client *client)
 		return ret;
 	}
 
-	tc->bridge.funcs = &tc_bridge_funcs;
 	tc->bridge.of_node = dev->of_node;
 	tc->bridge.pre_enable_prev_first = true;
 	drm_bridge_add(&tc->bridge);
diff --git a/drivers/gpu/drm/bridge/thc63lvd1024.c b/drivers/gpu/drm/bridge/thc63lvd1024.c
index e2fc78adebcf22f0d8cdb484078e37b748b776c6..2cb7cd0c060824256bbfa511f833cc00437d318b 100644
--- a/drivers/gpu/drm/bridge/thc63lvd1024.c
+++ b/drivers/gpu/drm/bridge/thc63lvd1024.c
@@ -181,9 +181,10 @@ static int thc63_probe(struct platform_device *pdev)
 	struct thc63_dev *thc63;
 	int ret;
 
-	thc63 = devm_kzalloc(&pdev->dev, sizeof(*thc63), GFP_KERNEL);
-	if (!thc63)
-		return -ENOMEM;
+	thc63 = devm_drm_bridge_alloc(&pdev->dev, struct thc63_dev, bridge,
+				      &thc63_bridge_func);
+	if (IS_ERR(thc63))
+		return PTR_ERR(thc63);
 
 	thc63->dev = &pdev->dev;
 	platform_set_drvdata(pdev, thc63);
@@ -208,7 +209,6 @@ static int thc63_probe(struct platform_device *pdev)
 
 	thc63->bridge.driver_private = thc63;
 	thc63->bridge.of_node = pdev->dev.of_node;
-	thc63->bridge.funcs = &thc63_bridge_func;
 	thc63->bridge.timings = &thc63->timings;
 
 	drm_bridge_add(&thc63->bridge);
diff --git a/drivers/gpu/drm/bridge/ti-dlpc3433.c b/drivers/gpu/drm/bridge/ti-dlpc3433.c
index 47638d1c96ec5ad999604c8c7e8839ff85936d98..b07f7c9d5890967a6db7bb01a9695abc809babbd 100644
--- a/drivers/gpu/drm/bridge/ti-dlpc3433.c
+++ b/drivers/gpu/drm/bridge/ti-dlpc3433.c
@@ -348,9 +348,10 @@ static int dlpc3433_probe(struct i2c_client *client)
 	struct dlpc *dlpc;
 	int ret;
 
-	dlpc = devm_kzalloc(dev, sizeof(*dlpc), GFP_KERNEL);
-	if (!dlpc)
-		return -ENOMEM;
+	dlpc = devm_drm_bridge_alloc(dev, struct dlpc, bridge,
+				     &dlpc_bridge_funcs);
+	if (IS_ERR(dlpc))
+		return PTR_ERR(dlpc);
 
 	dlpc->dev = dev;
 
@@ -365,7 +366,6 @@ static int dlpc3433_probe(struct i2c_client *client)
 	dev_set_drvdata(dev, dlpc);
 	i2c_set_clientdata(client, dlpc);
 
-	dlpc->bridge.funcs = &dlpc_bridge_funcs;
 	dlpc->bridge.of_node = dev->of_node;
 	drm_bridge_add(&dlpc->bridge);
 
diff --git a/drivers/gpu/drm/bridge/ti-tdp158.c b/drivers/gpu/drm/bridge/ti-tdp158.c
index cca75443f0121e39527a6cecf711eff2c0d507b5..27053d020df7c6fabbd5ce631b46c3f2358f12b2 100644
--- a/drivers/gpu/drm/bridge/ti-tdp158.c
+++ b/drivers/gpu/drm/bridge/ti-tdp158.c
@@ -68,9 +68,10 @@ static int tdp158_probe(struct i2c_client *client)
 	struct tdp158 *tdp158;
 	struct device *dev = &client->dev;
 
-	tdp158 = devm_kzalloc(dev, sizeof(*tdp158), GFP_KERNEL);
-	if (!tdp158)
-		return -ENOMEM;
+	tdp158 = devm_drm_bridge_alloc(dev, struct tdp158, bridge,
+				       &tdp158_bridge_funcs);
+	if (IS_ERR(tdp158))
+		return PTR_ERR(tdp158);
 
 	tdp158->next = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
 	if (IS_ERR(tdp158->next))
@@ -89,7 +90,6 @@ static int tdp158_probe(struct i2c_client *client)
 		return dev_err_probe(dev, PTR_ERR(tdp158->enable), "enable");
 
 	tdp158->bridge.of_node = dev->of_node;
-	tdp158->bridge.funcs = &tdp158_bridge_funcs;
 	tdp158->bridge.driver_private = tdp158;
 	tdp158->dev = dev;
 
diff --git a/drivers/gpu/drm/bridge/ti-tfp410.c b/drivers/gpu/drm/bridge/ti-tfp410.c
index e15d232ddbac55c6f5f966471a6c63f9c29a06c1..549e8e8edeb4f2f27d86a86fa0312e727380ecd9 100644
--- a/drivers/gpu/drm/bridge/ti-tfp410.c
+++ b/drivers/gpu/drm/bridge/ti-tfp410.c
@@ -341,14 +341,14 @@ static int tfp410_init(struct device *dev, bool i2c)
 		return -ENXIO;
 	}
 
-	dvi = devm_kzalloc(dev, sizeof(*dvi), GFP_KERNEL);
-	if (!dvi)
-		return -ENOMEM;
+	dvi = devm_drm_bridge_alloc(dev, struct tfp410, bridge,
+				    &tfp410_bridge_funcs);
+	if (IS_ERR(dvi))
+		return PTR_ERR(dvi);
 
 	dvi->dev = dev;
 	dev_set_drvdata(dev, dvi);
 
-	dvi->bridge.funcs = &tfp410_bridge_funcs;
 	dvi->bridge.of_node = dev->of_node;
 	dvi->bridge.timings = &dvi->timings;
 	dvi->bridge.type = DRM_MODE_CONNECTOR_DVID;
diff --git a/drivers/gpu/drm/bridge/ti-tpd12s015.c b/drivers/gpu/drm/bridge/ti-tpd12s015.c
index 1c289051a5987e0aec4c286ef4c01ee1a2f9421f..0919364e80d1f69b95a99e76daa915bee0b43d45 100644
--- a/drivers/gpu/drm/bridge/ti-tpd12s015.c
+++ b/drivers/gpu/drm/bridge/ti-tpd12s015.c
@@ -116,13 +116,13 @@ static int tpd12s015_probe(struct platform_device *pdev)
 	struct gpio_desc *gpio;
 	int ret;
 
-	tpd = devm_kzalloc(&pdev->dev, sizeof(*tpd), GFP_KERNEL);
-	if (!tpd)
-		return -ENOMEM;
+	tpd = devm_drm_bridge_alloc(&pdev->dev, struct tpd12s015_device,
+				    bridge, &tpd12s015_bridge_funcs);
+	if (IS_ERR(tpd))
+		return PTR_ERR(tpd);
 
 	platform_set_drvdata(pdev, tpd);
 
-	tpd->bridge.funcs = &tpd12s015_bridge_funcs;
 	tpd->bridge.of_node = pdev->dev.of_node;
 	tpd->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
 	tpd->bridge.ops = DRM_BRIDGE_OP_DETECT;
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
index b2408abb9d491bf25773d4dcc1be73c89cf208ce..bb80686a70e17dc79daa724b44e781a81ce4de85 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -2725,9 +2725,10 @@ static int mtk_dp_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	int ret;
 
-	mtk_dp = devm_kzalloc(dev, sizeof(*mtk_dp), GFP_KERNEL);
-	if (!mtk_dp)
-		return -ENOMEM;
+	mtk_dp = devm_drm_bridge_alloc(dev, struct mtk_dp, bridge,
+				       &mtk_dp_bridge_funcs);
+	if (IS_ERR(mtk_dp))
+		return PTR_ERR(mtk_dp);
 
 	mtk_dp->dev = dev;
 	mtk_dp->data = (struct mtk_dp_data *)of_device_get_match_data(dev);
@@ -2785,7 +2786,6 @@ static int mtk_dp_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	mtk_dp->bridge.funcs = &mtk_dp_bridge_funcs;
 	mtk_dp->bridge.of_node = dev->of_node;
 	mtk_dp->bridge.type = mtk_dp->data->bridge_type;
 
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 0f3b1ef8e497354edaf0a56e24660bf356fe01ac..9669bf4b80a14086159ae245ed51dd587b514bfb 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -1179,9 +1179,10 @@ static int mtk_dpi_probe(struct platform_device *pdev)
 	struct mtk_dpi *dpi;
 	int ret;
 
-	dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
-	if (!dpi)
-		return -ENOMEM;
+	dpi = devm_drm_bridge_alloc(dev, struct mtk_dpi, bridge,
+				    &mtk_dpi_bridge_funcs);
+	if (IS_ERR(dpi))
+		return PTR_ERR(dpi);
 
 	dpi->dev = dev;
 	dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev);
@@ -1233,7 +1234,6 @@ static int mtk_dpi_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, dpi);
 
-	dpi->bridge.funcs = &mtk_dpi_bridge_funcs;
 	dpi->bridge.of_node = dev->of_node;
 	dpi->bridge.type = DRM_MODE_CONNECTOR_DPI;
 
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 4fe1f38a3c4b7fcbbdbf7f6a82f66c9e2b546c02..d7726091819c4762698b41060b3d4d8d27940238 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1196,9 +1196,10 @@ static int mtk_dsi_probe(struct platform_device *pdev)
 	int irq_num;
 	int ret;
 
-	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
-	if (!dsi)
-		return -ENOMEM;
+	dsi = devm_drm_bridge_alloc(dev, struct mtk_dsi, bridge,
+				    &mtk_dsi_bridge_funcs);
+	if (IS_ERR(dsi))
+		return PTR_ERR(dsi);
 
 	dsi->driver_data = of_device_get_match_data(dev);
 
@@ -1246,7 +1247,6 @@ static int mtk_dsi_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, dsi);
 
-	dsi->bridge.funcs = &mtk_dsi_bridge_funcs;
 	dsi->bridge.of_node = dev->of_node;
 	dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
 
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index c9d0c335c519d405d480ffdc2feaa5b847c0e1bb..76aecad116bad23384db438ee2649f5f0b31ae50 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1690,9 +1690,10 @@ static int mtk_hdmi_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	int ret;
 
-	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
-	if (!hdmi)
-		return -ENOMEM;
+	hdmi = devm_drm_bridge_alloc(dev, struct mtk_hdmi, bridge,
+				     &mtk_hdmi_bridge_funcs);
+	if (IS_ERR(hdmi))
+		return PTR_ERR(hdmi);
 
 	hdmi->dev = dev;
 	hdmi->conf = of_device_get_match_data(dev);
@@ -1719,7 +1720,6 @@ static int mtk_hdmi_probe(struct platform_device *pdev)
 		return dev_err_probe(dev, ret,
 				     "Failed to register audio driver\n");
 
-	hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
 	hdmi->bridge.of_node = pdev->dev.of_node;
 	hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
 			 | DRM_BRIDGE_OP_HPD;
diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
index c9678dc68fa142882e2beb24fe81185fbdef733b..dc374bfc5951c0f13fc28f44325aa845ab590056 100644
--- a/drivers/gpu/drm/meson/meson_encoder_cvbs.c
+++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
@@ -227,9 +227,12 @@ int meson_encoder_cvbs_probe(struct meson_drm *priv)
 	struct device_node *remote;
 	int ret;
 
-	meson_encoder_cvbs = devm_kzalloc(priv->dev, sizeof(*meson_encoder_cvbs), GFP_KERNEL);
-	if (!meson_encoder_cvbs)
-		return -ENOMEM;
+	meson_encoder_cvbs = devm_drm_bridge_alloc(priv->dev,
+						   struct meson_encoder_cvbs,
+						   bridge,
+						   &meson_encoder_cvbs_bridge_funcs);
+	if (IS_ERR(meson_encoder_cvbs))
+		return PTR_ERR(meson_encoder_cvbs);
 
 	/* CVBS Connector Bridge */
 	remote = of_graph_get_remote_node(priv->dev->of_node, 0, 0);
@@ -245,7 +248,6 @@ int meson_encoder_cvbs_probe(struct meson_drm *priv)
 				     "Failed to find CVBS Connector bridge\n");
 
 	/* CVBS Encoder Bridge */
-	meson_encoder_cvbs->bridge.funcs = &meson_encoder_cvbs_bridge_funcs;
 	meson_encoder_cvbs->bridge.of_node = priv->dev->of_node;
 	meson_encoder_cvbs->bridge.type = DRM_MODE_CONNECTOR_Composite;
 	meson_encoder_cvbs->bridge.ops = DRM_BRIDGE_OP_MODES;
diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.c b/drivers/gpu/drm/meson/meson_encoder_dsi.c
index 3db518e5f95d324c218b730e0948c3dc845382bd..6c6624f9ba24a182900215d65b3ad7ab8aab6cf8 100644
--- a/drivers/gpu/drm/meson/meson_encoder_dsi.c
+++ b/drivers/gpu/drm/meson/meson_encoder_dsi.c
@@ -106,9 +106,12 @@ int meson_encoder_dsi_probe(struct meson_drm *priv)
 	struct device_node *remote;
 	int ret;
 
-	meson_encoder_dsi = devm_kzalloc(priv->dev, sizeof(*meson_encoder_dsi), GFP_KERNEL);
-	if (!meson_encoder_dsi)
-		return -ENOMEM;
+	meson_encoder_dsi = devm_drm_bridge_alloc(priv->dev,
+						  struct meson_encoder_dsi,
+						  bridge,
+						  &meson_encoder_dsi_bridge_funcs);
+	if (IS_ERR(meson_encoder_dsi))
+		return PTR_ERR(meson_encoder_dsi);
 
 	/* DSI Transceiver Bridge */
 	remote = of_graph_get_remote_node(priv->dev->of_node, 2, 0);
@@ -123,7 +126,6 @@ int meson_encoder_dsi_probe(struct meson_drm *priv)
 				     "Failed to find DSI transceiver bridge\n");
 
 	/* DSI Encoder Bridge */
-	meson_encoder_dsi->bridge.funcs = &meson_encoder_dsi_bridge_funcs;
 	meson_encoder_dsi->bridge.of_node = priv->dev->of_node;
 	meson_encoder_dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
 
diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
index 040c04b5dff9f0d4e2875e344c076bb8ab635c76..5a0d37a257f53c22165fad1a32e3c7522b8dd7f1 100644
--- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c
+++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
@@ -376,9 +376,12 @@ int meson_encoder_hdmi_probe(struct meson_drm *priv)
 	struct device_node *remote;
 	int ret;
 
-	meson_encoder_hdmi = devm_kzalloc(priv->dev, sizeof(*meson_encoder_hdmi), GFP_KERNEL);
-	if (!meson_encoder_hdmi)
-		return -ENOMEM;
+	meson_encoder_hdmi = devm_drm_bridge_alloc(priv->dev,
+						   struct meson_encoder_hdmi,
+						   bridge,
+						   &meson_encoder_hdmi_bridge_funcs);
+	if (IS_ERR(meson_encoder_hdmi))
+		return PTR_ERR(meson_encoder_hdmi);
 
 	/* HDMI Transceiver Bridge */
 	remote = of_graph_get_remote_node(priv->dev->of_node, 1, 0);
@@ -395,7 +398,6 @@ int meson_encoder_hdmi_probe(struct meson_drm *priv)
 	}
 
 	/* HDMI Encoder Bridge */
-	meson_encoder_hdmi->bridge.funcs = &meson_encoder_hdmi_bridge_funcs;
 	meson_encoder_hdmi->bridge.of_node = priv->dev->of_node;
 	meson_encoder_hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
 	meson_encoder_hdmi->bridge.interlace_allowed = true;
diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c b/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
index a9145253294fcaef6bae4e1406a781f6d710d357..af58b814e5887f2e231338c1d87feedf4db5e754 100644
--- a/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
+++ b/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
@@ -878,9 +878,10 @@ static int rcar_lvds_probe(struct platform_device *pdev)
 	struct rcar_lvds *lvds;
 	int ret;
 
-	lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
-	if (lvds == NULL)
-		return -ENOMEM;
+	lvds = devm_drm_bridge_alloc(&pdev->dev, struct rcar_lvds, bridge,
+				     &rcar_lvds_bridge_ops);
+	if (IS_ERR(lvds))
+		return PTR_ERR(lvds);
 
 	platform_set_drvdata(pdev, lvds);
 
@@ -895,7 +896,6 @@ static int rcar_lvds_probe(struct platform_device *pdev)
 	if (ret < 0)
 		return ret;
 
-	lvds->bridge.funcs = &rcar_lvds_bridge_ops;
 	lvds->bridge.of_node = pdev->dev.of_node;
 
 	lvds->mmio = devm_platform_ioremap_resource(pdev, 0);
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
index dc6ab012cdb69f92a33da69638aef3fc6fdfa46c..8ba0dde8d48227944263159313e184e581d9cb58 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
@@ -701,9 +701,10 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
 	u32 txsetr;
 	int ret;
 
-	dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
-	if (!dsi)
-		return -ENOMEM;
+	dsi = devm_drm_bridge_alloc(&pdev->dev, struct rzg2l_mipi_dsi, bridge,
+				    &rzg2l_mipi_dsi_bridge_ops);
+	if (IS_ERR(dsi))
+		return PTR_ERR(dsi);
 
 	platform_set_drvdata(pdev, dsi);
 	dsi->dev = &pdev->dev;
@@ -761,7 +762,6 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
 	pm_runtime_put(dsi->dev);
 
 	/* Initialize the DRM bridge. */
-	dsi->bridge.funcs = &rzg2l_mipi_dsi_bridge_ops;
 	dsi->bridge.of_node = dsi->dev->of_node;
 
 	/* Init host device */

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:29 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:29 +0200
Subject: [PATCH v3 03/22] drm/bridge: anx7625: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-3-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Cc: "Rob Herring (Arm)" <robh at kernel.org>
Cc: Hsin-Te Yuan <yuanhsinte at chromium.org>
Cc: Jani Nikula <jani.nikula at intel.com>
Cc: Pin-yen Lin <treapking at chromium.org>
Cc: Sui Jingfeng <sui.jingfeng at linux.dev>
Cc: Xin Ji <xji at analogixsemi.com>
---
 drivers/gpu/drm/bridge/analogix/anx7625.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
index 8a9079c2ed5c22565d0733ef899119e347947d21..0ac4a82c5a6e5e665d913674b664905a96c0d8e6 100644
--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
@@ -2596,7 +2596,6 @@ static int anx7625_link_bridge(struct drm_dp_aux *aux)
 		return ret;
 	}
 
-	platform->bridge.funcs = &anx7625_bridge_funcs;
 	platform->bridge.of_node = dev->of_node;
 	if (!anx7625_of_panel_on_aux_bus(dev))
 		platform->bridge.ops |= DRM_BRIDGE_OP_EDID;
@@ -2630,10 +2629,10 @@ static int anx7625_i2c_probe(struct i2c_client *client)
 		return -ENODEV;
 	}
 
-	platform = devm_kzalloc(dev, sizeof(*platform), GFP_KERNEL);
-	if (!platform) {
+	platform = devm_drm_bridge_alloc(dev, struct anx7625_data, bridge, &anx7625_bridge_funcs);
+	if (IS_ERR(platform)) {
 		DRM_DEV_ERROR(dev, "fail to allocate driver data\n");
-		return -ENOMEM;
+		return PTR_ERR(platform);
 	}
 
 	pdata = &platform->pdata;

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:30 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:30 +0200
Subject: [PATCH v3 04/22] drm/bridge: cdns-dsi: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-4-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Cc: Aradhya Bhatia <a-bhatia1 at ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen at ideasonboard.com>
---
 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
index b022dd6e6b6e9e43bf11583806e1a8d1e7431ae8..7604574da66606c103cc035dd94b0e211b64ebdc 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
@@ -1289,9 +1289,10 @@ static int cdns_dsi_drm_probe(struct platform_device *pdev)
 	int ret, irq;
 	u32 val;
 
-	dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
-	if (!dsi)
-		return -ENOMEM;
+	dsi = devm_drm_bridge_alloc(&pdev->dev, struct cdns_dsi, input.bridge,
+				    &cdns_dsi_bridge_funcs);
+	if (IS_ERR(dsi))
+		return PTR_ERR(dsi);
 
 	platform_set_drvdata(pdev, dsi);
 
@@ -1349,7 +1350,6 @@ static int cdns_dsi_drm_probe(struct platform_device *pdev)
 	 * CDNS_DPI_INPUT.
 	 */
 	input->id = CDNS_DPI_INPUT;
-	input->bridge.funcs = &cdns_dsi_bridge_funcs;
 	input->bridge.of_node = pdev->dev.of_node;
 
 	/* Mask all interrupts before registering the IRQ handler. */

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:31 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:31 +0200
Subject: [PATCH v3 05/22] drm/bridge: megachips-stdpxxxx-ge-b850v3-fw:
 convert to devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-5-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Cc: Ian Ray <ian.ray at gehealthcare.com>
Cc: Martyn Welch <martyn.welch at collabora.co.uk>
Cc: Peter Senna Tschudin <peter.senna at gmail.com>

Changed in v3:
- updated Ian Ray's e-mail (old one is bouncing

Changed in v2: none
---
 drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c b/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c
index 15a5a1f644fc10182c55bc9e489ccb81d4f924f9..81dde9ed7bcf7cacae000d9da31a3a5c347ce037 100644
--- a/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c
+++ b/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c
@@ -225,13 +225,11 @@ static int ge_b850v3_lvds_init(struct device *dev)
 	if (ge_b850v3_lvds_ptr)
 		goto success;
 
-	ge_b850v3_lvds_ptr = devm_kzalloc(dev,
-					  sizeof(*ge_b850v3_lvds_ptr),
-					  GFP_KERNEL);
-
-	if (!ge_b850v3_lvds_ptr) {
+	ge_b850v3_lvds_ptr = devm_drm_bridge_alloc(dev, struct ge_b850v3_lvds, bridge,
+						   &ge_b850v3_lvds_funcs);
+	if (IS_ERR(ge_b850v3_lvds_ptr)) {
 		mutex_unlock(&ge_b850v3_lvds_dev_mutex);
-		return -ENOMEM;
+		return PTR_ERR(ge_b850v3_lvds_ptr);
 	}
 
 success:
@@ -264,7 +262,6 @@ static int ge_b850v3_register(void)
 	struct device *dev = &stdp4028_i2c->dev;
 
 	/* drm bridge initialization */
-	ge_b850v3_lvds_ptr->bridge.funcs = &ge_b850v3_lvds_funcs;
 	ge_b850v3_lvds_ptr->bridge.ops = DRM_BRIDGE_OP_DETECT |
 					 DRM_BRIDGE_OP_EDID;
 	ge_b850v3_lvds_ptr->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:32 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:32 +0200
Subject: [PATCH v3 06/22] drm/bridge: nxp-ptn3460: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-6-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
---
 drivers/gpu/drm/bridge/nxp-ptn3460.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/bridge/nxp-ptn3460.c b/drivers/gpu/drm/bridge/nxp-ptn3460.c
index 25d7c415478b14ef634bff4185a8dd8e866be0c6..7acb11f16dc19e87a84cc765b1cebef158662c00 100644
--- a/drivers/gpu/drm/bridge/nxp-ptn3460.c
+++ b/drivers/gpu/drm/bridge/nxp-ptn3460.c
@@ -261,10 +261,10 @@ static int ptn3460_probe(struct i2c_client *client)
 	struct drm_bridge *panel_bridge;
 	int ret;
 
-	ptn_bridge = devm_kzalloc(dev, sizeof(*ptn_bridge), GFP_KERNEL);
-	if (!ptn_bridge) {
-		return -ENOMEM;
-	}
+	ptn_bridge = devm_drm_bridge_alloc(dev, struct ptn3460_bridge, bridge,
+					   &ptn3460_bridge_funcs);
+	if (IS_ERR(ptn_bridge))
+		return PTR_ERR(ptn_bridge);
 
 	panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0);
 	if (IS_ERR(panel_bridge))
@@ -300,7 +300,6 @@ static int ptn3460_probe(struct i2c_client *client)
 		return ret;
 	}
 
-	ptn_bridge->bridge.funcs = &ptn3460_bridge_funcs;
 	ptn_bridge->bridge.ops = DRM_BRIDGE_OP_EDID;
 	ptn_bridge->bridge.type = DRM_MODE_CONNECTOR_LVDS;
 	ptn_bridge->bridge.of_node = dev->of_node;

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:33 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:33 +0200
Subject: [PATCH v3 07/22] drm/bridge: sii902x: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-7-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
---
 drivers/gpu/drm/bridge/sii902x.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/bridge/sii902x.c b/drivers/gpu/drm/bridge/sii902x.c
index 6de61d9fe06487856e8b3c32db3c8d8c25633fd8..882973e900628c0d972d32cd4ff3588432daa8e9 100644
--- a/drivers/gpu/drm/bridge/sii902x.c
+++ b/drivers/gpu/drm/bridge/sii902x.c
@@ -1135,7 +1135,6 @@ static int sii902x_init(struct sii902x *sii902x)
 	if (ret)
 		goto err_unreg_audio;
 
-	sii902x->bridge.funcs = &sii902x_bridge_funcs;
 	sii902x->bridge.of_node = dev->of_node;
 	sii902x->bridge.timings = &default_sii902x_timings;
 	sii902x->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID;
@@ -1170,9 +1169,9 @@ static int sii902x_probe(struct i2c_client *client)
 		return -EIO;
 	}
 
-	sii902x = devm_kzalloc(dev, sizeof(*sii902x), GFP_KERNEL);
-	if (!sii902x)
-		return -ENOMEM;
+	sii902x = devm_drm_bridge_alloc(dev, struct sii902x, bridge, &sii902x_bridge_funcs);
+	if (IS_ERR(sii902x))
+		return PTR_ERR(sii902x);
 
 	sii902x->i2c = client;
 	sii902x->regmap = devm_regmap_init_i2c(client, &sii902x_regmap_config);

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:34 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:34 +0200
Subject: [PATCH v3 08/22] drm/omap: dss: dpi: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-8-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Cc: "Rob Herring (Arm)" <robh at kernel.org>
Cc: Helge Deller <deller at gmx.de>
Cc: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Cc: Tomi Valkeinen <tomi.valkeinen at ideasonboard.com>
---
 drivers/gpu/drm/omapdrm/dss/dpi.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/dpi.c b/drivers/gpu/drm/omapdrm/dss/dpi.c
index 6eff97a091602f6d137095b3b7bf54fce17e8d3e..9f86db774c395db7e3396cbf2694748fc23c309d 100644
--- a/drivers/gpu/drm/omapdrm/dss/dpi.c
+++ b/drivers/gpu/drm/omapdrm/dss/dpi.c
@@ -562,7 +562,6 @@ static const struct drm_bridge_funcs dpi_bridge_funcs = {
 
 static void dpi_bridge_init(struct dpi_data *dpi)
 {
-	dpi->bridge.funcs = &dpi_bridge_funcs;
 	dpi->bridge.of_node = dpi->pdev->dev.of_node;
 	dpi->bridge.type = DRM_MODE_CONNECTOR_DPI;
 
@@ -707,9 +706,9 @@ int dpi_init_port(struct dss_device *dss, struct platform_device *pdev,
 	u32 datalines;
 	int r;
 
-	dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL);
-	if (!dpi)
-		return -ENOMEM;
+	dpi = devm_drm_bridge_alloc(&pdev->dev, struct dpi_data, bridge, &dpi_bridge_funcs);
+	if (IS_ERR(dpi))
+		return PTR_ERR(dpi);
 
 	ep = of_graph_get_next_port_endpoint(port, NULL);
 	if (!ep)

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:35 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:35 +0200
Subject: [PATCH v3 09/22] drm/omap: dss: dsi: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-9-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Cc: Tomi Valkeinen <tomi.valkeinen at ideasonboard.com>
---
 drivers/gpu/drm/omapdrm/dss/dsi.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c
index 91ee63bfe0bc73e28877d0383812225867e167a4..b129e5a8d791507098c7b8d1bc54f54c4b453954 100644
--- a/drivers/gpu/drm/omapdrm/dss/dsi.c
+++ b/drivers/gpu/drm/omapdrm/dss/dsi.c
@@ -4701,7 +4701,6 @@ static const struct drm_bridge_funcs dsi_bridge_funcs = {
 
 static void dsi_bridge_init(struct dsi_data *dsi)
 {
-	dsi->bridge.funcs = &dsi_bridge_funcs;
 	dsi->bridge.of_node = dsi->host.dev->of_node;
 	dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
 
@@ -4894,9 +4893,9 @@ static int dsi_probe(struct platform_device *pdev)
 	unsigned int i;
 	int r;
 
-	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
-	if (!dsi)
-		return -ENOMEM;
+	dsi = devm_drm_bridge_alloc(dev, struct dsi_data, bridge, &dsi_bridge_funcs);
+	if (IS_ERR(dsi))
+		return PTR_ERR(dsi);
 
 	dsi->dev = dev;
 	dev_set_drvdata(dev, dsi);

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:36 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:36 +0200
Subject: [PATCH v3 10/22] drm/omap: dss: hdmi4: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-10-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

Switching from a non-devm to a devm allocation allows removing the kfree()
in the remove function and in the probe error management code, and as a
consequence to simplify the code flow by removing now unnecessary gotos.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Cc: Tomi Valkeinen <tomi.valkeinen at ideasonboard.com>
---
 drivers/gpu/drm/omapdrm/dss/hdmi4.c | 26 ++++++++++----------------
 1 file changed, 10 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4.c b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
index a3b22952fdc32b5899dae82d413108c5c0a1c3c8..3cd612af24498b057c33eaecb3d43c8df76cd23e 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
@@ -505,7 +505,6 @@ static const struct drm_bridge_funcs hdmi4_bridge_funcs = {
 
 static void hdmi4_bridge_init(struct omap_hdmi *hdmi)
 {
-	hdmi->bridge.funcs = &hdmi4_bridge_funcs;
 	hdmi->bridge.of_node = hdmi->pdev->dev.of_node;
 	hdmi->bridge.ops = DRM_BRIDGE_OP_EDID;
 	hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
@@ -761,9 +760,9 @@ static int hdmi4_probe(struct platform_device *pdev)
 	int irq;
 	int r;
 
-	hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
-	if (!hdmi)
-		return -ENOMEM;
+	hdmi = devm_drm_bridge_alloc(&pdev->dev, struct omap_hdmi, bridge, &hdmi4_bridge_funcs);
+	if (IS_ERR(hdmi))
+		return PTR_ERR(hdmi);
 
 	hdmi->pdev = pdev;
 
@@ -774,25 +773,24 @@ static int hdmi4_probe(struct platform_device *pdev)
 
 	r = hdmi4_probe_of(hdmi);
 	if (r)
-		goto err_free;
+		return r;
 
 	r = hdmi_wp_init(pdev, &hdmi->wp, 4);
 	if (r)
-		goto err_free;
+		return r;
 
 	r = hdmi_phy_init(pdev, &hdmi->phy, 4);
 	if (r)
-		goto err_free;
+		return r;
 
 	r = hdmi4_core_init(pdev, &hdmi->core);
 	if (r)
-		goto err_free;
+		return r;
 
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0) {
 		DSSERR("platform_get_irq failed\n");
-		r = -ENODEV;
-		goto err_free;
+		return -ENODEV;
 	}
 
 	r = devm_request_threaded_irq(&pdev->dev, irq,
@@ -800,7 +798,7 @@ static int hdmi4_probe(struct platform_device *pdev)
 			IRQF_ONESHOT, "OMAP HDMI", hdmi);
 	if (r) {
 		DSSERR("HDMI IRQ request failed\n");
-		goto err_free;
+		return r;
 	}
 
 	hdmi->vdda_reg = devm_regulator_get(&pdev->dev, "vdda");
@@ -808,7 +806,7 @@ static int hdmi4_probe(struct platform_device *pdev)
 		r = PTR_ERR(hdmi->vdda_reg);
 		if (r != -EPROBE_DEFER)
 			DSSERR("can't get VDDA regulator\n");
-		goto err_free;
+		return r;
 	}
 
 	pm_runtime_enable(&pdev->dev);
@@ -827,8 +825,6 @@ static int hdmi4_probe(struct platform_device *pdev)
 	hdmi4_uninit_output(hdmi);
 err_pm_disable:
 	pm_runtime_disable(&pdev->dev);
-err_free:
-	kfree(hdmi);
 	return r;
 }
 
@@ -841,8 +837,6 @@ static void hdmi4_remove(struct platform_device *pdev)
 	hdmi4_uninit_output(hdmi);
 
 	pm_runtime_disable(&pdev->dev);
-
-	kfree(hdmi);
 }
 
 static const struct of_device_id hdmi_of_match[] = {

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:37 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:37 +0200
Subject: [PATCH v3 11/22] drm/omap: dss: hdmi5: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-11-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

Switching from a non-devm to a devm allocation allows removing the kfree()
in the remove function and in the probe error management code, and as a
consequence to simplify the code flow by removing now unnecessary gotos.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Cc: Tomi Valkeinen <tomi.valkeinen at ideasonboard.com>
---
 drivers/gpu/drm/omapdrm/dss/hdmi5.c | 26 ++++++++++----------------
 1 file changed, 10 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5.c b/drivers/gpu/drm/omapdrm/dss/hdmi5.c
index 0c98444d39a93d8336b4d8dbd45aa4521181c3b4..5636b3dfec1c9581118b20adecd268c03e882efb 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi5.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi5.c
@@ -480,7 +480,6 @@ static const struct drm_bridge_funcs hdmi5_bridge_funcs = {
 
 static void hdmi5_bridge_init(struct omap_hdmi *hdmi)
 {
-	hdmi->bridge.funcs = &hdmi5_bridge_funcs;
 	hdmi->bridge.of_node = hdmi->pdev->dev.of_node;
 	hdmi->bridge.ops = DRM_BRIDGE_OP_EDID;
 	hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
@@ -727,9 +726,9 @@ static int hdmi5_probe(struct platform_device *pdev)
 	int irq;
 	int r;
 
-	hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
-	if (!hdmi)
-		return -ENOMEM;
+	hdmi = devm_drm_bridge_alloc(&pdev->dev, struct omap_hdmi, bridge, &hdmi5_bridge_funcs);
+	if (IS_ERR(hdmi))
+		return PTR_ERR(hdmi);
 
 	hdmi->pdev = pdev;
 
@@ -740,25 +739,24 @@ static int hdmi5_probe(struct platform_device *pdev)
 
 	r = hdmi5_probe_of(hdmi);
 	if (r)
-		goto err_free;
+		return r;
 
 	r = hdmi_wp_init(pdev, &hdmi->wp, 5);
 	if (r)
-		goto err_free;
+		return r;
 
 	r = hdmi_phy_init(pdev, &hdmi->phy, 5);
 	if (r)
-		goto err_free;
+		return r;
 
 	r = hdmi5_core_init(pdev, &hdmi->core);
 	if (r)
-		goto err_free;
+		return r;
 
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0) {
 		DSSERR("platform_get_irq failed\n");
-		r = -ENODEV;
-		goto err_free;
+		return -ENODEV;
 	}
 
 	r = devm_request_threaded_irq(&pdev->dev, irq,
@@ -766,7 +764,7 @@ static int hdmi5_probe(struct platform_device *pdev)
 			IRQF_ONESHOT, "OMAP HDMI", hdmi);
 	if (r) {
 		DSSERR("HDMI IRQ request failed\n");
-		goto err_free;
+		return r;
 	}
 
 	hdmi->vdda_reg = devm_regulator_get(&pdev->dev, "vdda");
@@ -774,7 +772,7 @@ static int hdmi5_probe(struct platform_device *pdev)
 		r = PTR_ERR(hdmi->vdda_reg);
 		if (r != -EPROBE_DEFER)
 			DSSERR("can't get VDDA regulator\n");
-		goto err_free;
+		return r;
 	}
 
 	pm_runtime_enable(&pdev->dev);
@@ -793,8 +791,6 @@ static int hdmi5_probe(struct platform_device *pdev)
 	hdmi5_uninit_output(hdmi);
 err_pm_disable:
 	pm_runtime_disable(&pdev->dev);
-err_free:
-	kfree(hdmi);
 	return r;
 }
 
@@ -807,8 +803,6 @@ static void hdmi5_remove(struct platform_device *pdev)
 	hdmi5_uninit_output(hdmi);
 
 	pm_runtime_disable(&pdev->dev);
-
-	kfree(hdmi);
 }
 
 static const struct of_device_id hdmi_of_match[] = {

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:38 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:38 +0200
Subject: [PATCH v3 12/22] drm/omap: dss: sdi: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-12-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

Switching from a non-devm to a devm allocation allows removing the kfree()
in the remove function and in the probe error management code, and as a
consequence to simplify the code flow by removing now unnecessary gotos.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Cc: "Rob Herring (Arm)" <robh at kernel.org>
Cc: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Cc: Tomi Valkeinen <tomi.valkeinen at ideasonboard.com>
---
 drivers/gpu/drm/omapdrm/dss/sdi.c | 25 ++++++++-----------------
 1 file changed, 8 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/sdi.c b/drivers/gpu/drm/omapdrm/dss/sdi.c
index e78826e4b560a2b9af2d8a5a38e181bd3e44d250..df4cbc683e2ca27ef5fc45f79b77dcdcd9ca529a 100644
--- a/drivers/gpu/drm/omapdrm/dss/sdi.c
+++ b/drivers/gpu/drm/omapdrm/dss/sdi.c
@@ -284,7 +284,6 @@ static const struct drm_bridge_funcs sdi_bridge_funcs = {
 
 static void sdi_bridge_init(struct sdi_device *sdi)
 {
-	sdi->bridge.funcs = &sdi_bridge_funcs;
 	sdi->bridge.of_node = sdi->pdev->dev.of_node;
 	sdi->bridge.type = DRM_MODE_CONNECTOR_LVDS;
 
@@ -344,21 +343,19 @@ int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
 	u32 datapairs;
 	int r;
 
-	sdi = kzalloc(sizeof(*sdi), GFP_KERNEL);
-	if (!sdi)
-		return -ENOMEM;
+	sdi = devm_drm_bridge_alloc(&pdev->dev, struct sdi_device, bridge, &sdi_bridge_funcs);
+	if (IS_ERR(sdi))
+		return PTR_ERR(sdi);
 
 	ep = of_graph_get_next_port_endpoint(port, NULL);
-	if (!ep) {
-		r = 0;
-		goto err_free;
-	}
+	if (!ep)
+		return 0;
 
 	r = of_property_read_u32(ep, "datapairs", &datapairs);
 	of_node_put(ep);
 	if (r) {
 		DSSERR("failed to parse datapairs\n");
-		goto err_free;
+		return r;
 	}
 
 	sdi->datapairs = datapairs;
@@ -372,19 +369,14 @@ int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
 		r = PTR_ERR(sdi->vdds_sdi_reg);
 		if (r != -EPROBE_DEFER)
 			DSSERR("can't get VDDS_SDI regulator\n");
-		goto err_free;
+		return r;
 	}
 
 	r = sdi_init_output(sdi);
 	if (r)
-		goto err_free;
+		return r;
 
 	return 0;
-
-err_free:
-	kfree(sdi);
-
-	return r;
 }
 
 void sdi_uninit_port(struct device_node *port)
@@ -395,5 +387,4 @@ void sdi_uninit_port(struct device_node *port)
 		return;
 
 	sdi_uninit_output(sdi);
-	kfree(sdi);
 }

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:39 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:39 +0200
Subject: [PATCH v3 13/22] drm/omap: dss: venc: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-13-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

Switching from a non-devm to a devm allocation allows removing the kfree()
in the remove function and in the probe error management code, and as a
consequence to simplify the code flow by removing now unnecessary gotos.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Cc: Tomi Valkeinen <tomi.valkeinen at ideasonboard.com>
---
 drivers/gpu/drm/omapdrm/dss/venc.c | 23 ++++++++---------------
 1 file changed, 8 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/venc.c b/drivers/gpu/drm/omapdrm/dss/venc.c
index 50349518eda1630400529caf27ca4469bb09fc82..9b5d53dc361e654a2e4009c3c81b726f9ef76ced 100644
--- a/drivers/gpu/drm/omapdrm/dss/venc.c
+++ b/drivers/gpu/drm/omapdrm/dss/venc.c
@@ -664,7 +664,6 @@ static const struct drm_bridge_funcs venc_bridge_funcs = {
 
 static void venc_bridge_init(struct venc_device *venc)
 {
-	venc->bridge.funcs = &venc_bridge_funcs;
 	venc->bridge.of_node = venc->pdev->dev.of_node;
 	venc->bridge.ops = DRM_BRIDGE_OP_MODES;
 	venc->bridge.type = DRM_MODE_CONNECTOR_SVIDEO;
@@ -809,9 +808,9 @@ static int venc_probe(struct platform_device *pdev)
 	struct venc_device *venc;
 	int r;
 
-	venc = kzalloc(sizeof(*venc), GFP_KERNEL);
-	if (!venc)
-		return -ENOMEM;
+	venc = devm_drm_bridge_alloc(&pdev->dev, struct venc_device, bridge, &venc_bridge_funcs);
+	if (IS_ERR(venc))
+		return PTR_ERR(venc);
 
 	venc->pdev = pdev;
 
@@ -824,26 +823,24 @@ static int venc_probe(struct platform_device *pdev)
 	venc->config = &venc_config_pal_trm;
 
 	venc->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(venc->base)) {
-		r = PTR_ERR(venc->base);
-		goto err_free;
-	}
+	if (IS_ERR(venc->base))
+		return PTR_ERR(venc->base);
 
 	venc->vdda_dac_reg = devm_regulator_get(&pdev->dev, "vdda");
 	if (IS_ERR(venc->vdda_dac_reg)) {
 		r = PTR_ERR(venc->vdda_dac_reg);
 		if (r != -EPROBE_DEFER)
 			DSSERR("can't get VDDA_DAC regulator\n");
-		goto err_free;
+		return r;
 	}
 
 	r = venc_get_clocks(venc);
 	if (r)
-		goto err_free;
+		return r;
 
 	r = venc_probe_of(venc);
 	if (r)
-		goto err_free;
+		return r;
 
 	pm_runtime_enable(&pdev->dev);
 
@@ -861,8 +858,6 @@ static int venc_probe(struct platform_device *pdev)
 	venc_uninit_output(venc);
 err_pm_disable:
 	pm_runtime_disable(&pdev->dev);
-err_free:
-	kfree(venc);
 	return r;
 }
 
@@ -875,8 +870,6 @@ static void venc_remove(struct platform_device *pdev)
 	venc_uninit_output(venc);
 
 	pm_runtime_disable(&pdev->dev);
-
-	kfree(venc);
 }
 
 static __maybe_unused int venc_runtime_suspend(struct device *dev)

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:40 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:40 +0200
Subject: [PATCH v3 14/22] drm/rcar-du: dsi: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-14-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Cc: Kieran Bingham <kieran.bingham+renesas at ideasonboard.com>
Cc: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
Cc: Tomi Valkeinen <tomi.valkeinen+renesas at ideasonboard.com>
---
 drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
index 7ab8be46c7f6547f29b4d45af7ac704283da9dcd..1af4c73f7a887712aef8c8176b0d0338d9ca9727 100644
--- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
@@ -918,7 +918,6 @@ static int rcar_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 	}
 
 	/* Initialize the DRM bridge. */
-	dsi->bridge.funcs = &rcar_mipi_dsi_bridge_ops;
 	dsi->bridge.of_node = dsi->dev->of_node;
 	drm_bridge_add(&dsi->bridge);
 
@@ -1004,9 +1003,10 @@ static int rcar_mipi_dsi_probe(struct platform_device *pdev)
 	struct rcar_mipi_dsi *dsi;
 	int ret;
 
-	dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
-	if (dsi == NULL)
-		return -ENOMEM;
+	dsi = devm_drm_bridge_alloc(&pdev->dev, struct rcar_mipi_dsi, bridge,
+				    &rcar_mipi_dsi_bridge_ops);
+	if (IS_ERR(dsi))
+		return PTR_ERR(dsi);
 
 	platform_set_drvdata(pdev, dsi);
 

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:41 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:41 +0200
Subject: [PATCH v3 15/22] drm/bridge: stm_lvds: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-15-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Cc: Alexandre Torgue <alexandre.torgue at foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32 at gmail.com>
Cc: Philippe Cornu <philippe.cornu at foss.st.com>
Cc: Raphael Gallais-Pou <raphael.gallais-pou at foss.st.com>
Cc: Yannick Fertre <yannick.fertre at foss.st.com>
---
 drivers/gpu/drm/stm/lvds.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/stm/lvds.c b/drivers/gpu/drm/stm/lvds.c
index a3ae9a93ce6670eb2c4dd36b3e572fcbca791a1c..07788e8d3d8302a3951e97d64736b721033998d3 100644
--- a/drivers/gpu/drm/stm/lvds.c
+++ b/drivers/gpu/drm/stm/lvds.c
@@ -1049,9 +1049,9 @@ static int lvds_probe(struct platform_device *pdev)
 
 	dev_dbg(dev, "Probing LVDS driver...\n");
 
-	lvds = devm_kzalloc(dev, sizeof(*lvds), GFP_KERNEL);
-	if (!lvds)
-		return -ENOMEM;
+	lvds = devm_drm_bridge_alloc(dev, struct stm_lvds, lvds_bridge, &lvds_bridge_funcs);
+	if (IS_ERR(lvds))
+		return PTR_ERR(lvds);
 
 	lvds->dev = dev;
 
@@ -1164,7 +1164,6 @@ static int lvds_probe(struct platform_device *pdev)
 		goto err_lvds_probe;
 	}
 
-	lvds->lvds_bridge.funcs = &lvds_bridge_funcs;
 	lvds->lvds_bridge.of_node = dev->of_node;
 	lvds->hw_version = lvds_read(lvds, LVDS_VERR);
 

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:42 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:42 +0200
Subject: [PATCH v3 16/22] drm/sti: dvo: convert to devm_drm_bridge_alloc()
 API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-16-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

This driver allocates the DRM bridge separately from the main driver
private struct, which prevents using the new devm_drm_bridge_alloc()
API. Simplify the code by replacing the struct drm_bridge pointer with an
embedded struct drm_bridge inside the private struct, to make use of the
new API with the same code flow.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Cc: Alain Volmat <alain.volmat at foss.st.com>
Cc: Raphael Gallais-Pou <rgallaispou at gmail.com>

Changed in v2:
- fix typos in commit message
---
 drivers/gpu/drm/sti/sti_dvo.c | 29 +++++++++++------------------
 1 file changed, 11 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/sti/sti_dvo.c b/drivers/gpu/drm/sti/sti_dvo.c
index 74a1eef4674eeabc445b53b380e325f785242024..7484d3c3f4ed5fac7eab408e30cbe2f6b87f27e5 100644
--- a/drivers/gpu/drm/sti/sti_dvo.c
+++ b/drivers/gpu/drm/sti/sti_dvo.c
@@ -97,7 +97,7 @@ struct sti_dvo {
 	struct dvo_config *config;
 	bool enabled;
 	struct drm_encoder *encoder;
-	struct drm_bridge *bridge;
+	struct drm_bridge bridge;
 };
 
 struct sti_dvo_connector {
@@ -439,7 +439,6 @@ static int sti_dvo_bind(struct device *dev, struct device *master, void *data)
 	struct drm_encoder *encoder;
 	struct sti_dvo_connector *connector;
 	struct drm_connector *drm_connector;
-	struct drm_bridge *bridge;
 	int err;
 
 	/* Set the drm device handle */
@@ -455,20 +454,14 @@ static int sti_dvo_bind(struct device *dev, struct device *master, void *data)
 
 	connector->dvo = dvo;
 
-	bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
-	if (!bridge)
-		return -ENOMEM;
-
-	bridge->driver_private = dvo;
-	bridge->funcs = &sti_dvo_bridge_funcs;
-	bridge->of_node = dvo->dev.of_node;
-	drm_bridge_add(bridge);
+	dvo->bridge.driver_private = dvo;
+	dvo->bridge.of_node = dvo->dev.of_node;
+	drm_bridge_add(&dvo->bridge);
 
-	err = drm_bridge_attach(encoder, bridge, NULL, 0);
+	err = drm_bridge_attach(encoder, &dvo->bridge, NULL, 0);
 	if (err)
 		return err;
 
-	dvo->bridge = bridge;
 	connector->encoder = encoder;
 	dvo->encoder = encoder;
 
@@ -490,7 +483,7 @@ static int sti_dvo_bind(struct device *dev, struct device *master, void *data)
 	return 0;
 
 err_sysfs:
-	drm_bridge_remove(bridge);
+	drm_bridge_remove(&dvo->bridge);
 	return -EINVAL;
 }
 
@@ -499,7 +492,7 @@ static void sti_dvo_unbind(struct device *dev,
 {
 	struct sti_dvo *dvo = dev_get_drvdata(dev);
 
-	drm_bridge_remove(dvo->bridge);
+	drm_bridge_remove(&dvo->bridge);
 }
 
 static const struct component_ops sti_dvo_ops = {
@@ -515,10 +508,10 @@ static int sti_dvo_probe(struct platform_device *pdev)
 
 	DRM_INFO("%s\n", __func__);
 
-	dvo = devm_kzalloc(dev, sizeof(*dvo), GFP_KERNEL);
-	if (!dvo) {
-		DRM_ERROR("Failed to allocate memory for DVO\n");
-		return -ENOMEM;
+	dvo = devm_drm_bridge_alloc(dev, struct sti_dvo, bridge, &sti_dvo_bridge_funcs);
+	if (IS_ERR(dvo)) {
+		DRM_ERROR("Failed to allocate DVO\n");
+		return PTR_ERR(dvo);
 	}
 
 	dvo->dev = pdev->dev;

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:43 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:43 +0200
Subject: [PATCH v3 17/22] drm: zynqmp_dp: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-17-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

This driver has a peculiar structure. zynqmp_dpsub.c is the actual driver,
which delegates to a submodule (zynqmp_dp.c) the allocation of a
sub-structure embedding the drm_bridge and its initialization, however it
does not delegate the drm_bridge_add(). Hence, following carefully the code
flow, it is correct to change the allocation function and .funcs assignment
in the submodule, while the drm_bridge_add() is not in that submodule.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Cc: Michal Simek <michal.simek at amd.com>
Cc: Tomi Valkeinen <tomi.valkeinen at ideasonboard.com>

Changes in v2:
- rebased on current drm-misc-next
- remove the kfree() calls too, as we are converting from kzalloc+kfree,
  not from devm_kzalloc
---
 drivers/gpu/drm/xlnx/zynqmp_dp.c    | 31 +++++++++++--------------------
 drivers/gpu/drm/xlnx/zynqmp_dpsub.c |  1 -
 2 files changed, 11 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c
index 238cbb49963efa6e8cc737d8a6e76250f6531276..02e1feaa611596a24217136ee8ce7f5d2f1900a2 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_dp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c
@@ -2439,9 +2439,9 @@ int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub)
 	struct zynqmp_dp *dp;
 	int ret;
 
-	dp = kzalloc(sizeof(*dp), GFP_KERNEL);
-	if (!dp)
-		return -ENOMEM;
+	dp = devm_drm_bridge_alloc(&pdev->dev, struct zynqmp_dp, bridge, &zynqmp_dp_bridge_funcs);
+	if (IS_ERR(dp))
+		return PTR_ERR(dp);
 
 	dp->dev = &pdev->dev;
 	dp->dpsub = dpsub;
@@ -2454,31 +2454,25 @@ int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub)
 
 	/* Acquire all resources (IOMEM, IRQ and PHYs). */
 	dp->iomem = devm_platform_ioremap_resource_byname(pdev, "dp");
-	if (IS_ERR(dp->iomem)) {
-		ret = PTR_ERR(dp->iomem);
-		goto err_free;
-	}
+	if (IS_ERR(dp->iomem))
+		return PTR_ERR(dp->iomem);
 
 	dp->irq = platform_get_irq(pdev, 0);
-	if (dp->irq < 0) {
-		ret = dp->irq;
-		goto err_free;
-	}
+	if (dp->irq < 0)
+		return dp->irq;
 
 	dp->reset = devm_reset_control_get(dp->dev, NULL);
-	if (IS_ERR(dp->reset)) {
-		ret = dev_err_probe(dp->dev, PTR_ERR(dp->reset),
+	if (IS_ERR(dp->reset))
+		return dev_err_probe(dp->dev, PTR_ERR(dp->reset),
 				    "failed to get reset\n");
-		goto err_free;
-	}
 
 	ret = zynqmp_dp_reset(dp, true);
 	if (ret < 0)
-		goto err_free;
+		return ret;
 
 	ret = zynqmp_dp_reset(dp, false);
 	if (ret < 0)
-		goto err_free;
+		return ret;
 
 	ret = zynqmp_dp_phy_probe(dp);
 	if (ret)
@@ -2486,7 +2480,6 @@ int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub)
 
 	/* Initialize the bridge. */
 	bridge = &dp->bridge;
-	bridge->funcs = &zynqmp_dp_bridge_funcs;
 	bridge->ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
 		    | DRM_BRIDGE_OP_HPD;
 	bridge->type = DRM_MODE_CONNECTOR_DisplayPort;
@@ -2539,8 +2532,6 @@ int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub)
 	zynqmp_dp_phy_exit(dp);
 err_reset:
 	zynqmp_dp_reset(dp, true);
-err_free:
-	kfree(dp);
 	return ret;
 }
 
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
index 3a9544b97bc5311f9adeb57c08c837a04b6922fa..2764c4b17c5e49611db8adf41dd09e3134c2d524 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
@@ -180,7 +180,6 @@ static int zynqmp_dpsub_parse_dt(struct zynqmp_dpsub *dpsub)
 void zynqmp_dpsub_release(struct zynqmp_dpsub *dpsub)
 {
 	kfree(dpsub->disp);
-	kfree(dpsub->dp);
 	kfree(dpsub);
 }
 

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:44 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:44 +0200
Subject: [PATCH v3 18/22] drm/bridge: imx8qxp-pixel-combiner: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-18-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

This driver embeds an array of channels in the main struct, and each
channel embeds a drm_bridge. This prevents dynamic, refcount-based
deallocation of the bridges.

To make the new, dynamic bridge allocation possible:

 * change the array of channels into an array of channel pointers
 * allocate each channel using devm_drm_bridge_alloc()
 * adapt the code wherever using the channels
 * remove the is_available flag, now "ch != NULL" is equivalent

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Cc: Liu Ying <victor.liu at nxp.com>

Changes in v3:
- fix NULL pointer deref in .remove and remove is_available bool

Changes in v2: none
---
 .../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c    | 27 +++++++++++-----------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
index 1f6fd488e7039e943351006d3373009f0c15cb08..8517b1c953d4e0fb9f5b6dbe25fbaaa63eef2b33 100644
--- a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
@@ -63,12 +63,11 @@ struct imx8qxp_pc_channel {
 	struct drm_bridge *next_bridge;
 	struct imx8qxp_pc *pc;
 	unsigned int stream_id;
-	bool is_available;
 };
 
 struct imx8qxp_pc {
 	struct device *dev;
-	struct imx8qxp_pc_channel ch[2];
+	struct imx8qxp_pc_channel *ch[2];
 	struct clk *clk_apb;
 	void __iomem *base;
 };
@@ -307,7 +306,14 @@ static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
 			goto free_child;
 		}
 
-		ch = &pc->ch[i];
+		ch = devm_drm_bridge_alloc(dev, struct imx8qxp_pc_channel, bridge,
+					   &imx8qxp_pc_bridge_funcs);
+		if (IS_ERR(ch)) {
+			ret = PTR_ERR(ch);
+			goto free_child;
+		}
+
+		pc->ch[i] = ch;
 		ch->pc = pc;
 		ch->stream_id = i;
 
@@ -333,9 +339,7 @@ static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
 		of_node_put(remote);
 
 		ch->bridge.driver_private = ch;
-		ch->bridge.funcs = &imx8qxp_pc_bridge_funcs;
 		ch->bridge.of_node = child;
-		ch->is_available = true;
 
 		drm_bridge_add(&ch->bridge);
 	}
@@ -345,8 +349,8 @@ static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
 free_child:
 	of_node_put(child);
 
-	if (i == 1 && pc->ch[0].next_bridge)
-		drm_bridge_remove(&pc->ch[0].bridge);
+	if (i == 1 && pc->ch[0]->next_bridge)
+		drm_bridge_remove(&pc->ch[0]->bridge);
 
 	pm_runtime_disable(dev);
 	return ret;
@@ -359,13 +363,10 @@ static void imx8qxp_pc_bridge_remove(struct platform_device *pdev)
 	int i;
 
 	for (i = 0; i < 2; i++) {
-		ch = &pc->ch[i];
-
-		if (!ch->is_available)
-			continue;
+		ch = pc->ch[i];
 
-		drm_bridge_remove(&ch->bridge);
-		ch->is_available = false;
+		if (ch)
+			drm_bridge_remove(&ch->bridge);
 	}
 
 	pm_runtime_disable(&pdev->dev);

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:45 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:45 +0200
Subject: [PATCH v3 19/22] drm/bridge: tc358767: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-19-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

Converting this driver is a bit convoluted because the drm_bridge funcs
pointer differs based on the bridge mode. So the current code does:

 * tc_probe()
   * devm_kzalloc() private struct embedding drm_bridge
   * call tc_probe_bridge_endpoint() which
     * parses DT description into struct fields
     * computes the mode
     * calls different bridge init functions based on the mode
       * each sets a different bridge.funcs pointer

The new API expects the funcs pointer to be known at alloc time, which does
not fit in the current code structure.

Solve this by moving the part of tc_probe_bridge_endpoint() computing the
mode into a separate function, tc_probe_get_mode(), which does not need the
private driver structure. So now the mode is known before allocation and so
is the funcs pointer, while all other operations are still happening after
allocation, directly into the private struct data, as they used to.

This solution is chosen to minimize the changes in the driver logical code
flow. The drawback is we now iterate twice over the endpoints.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
---
 drivers/gpu/drm/bridge/tc358767.c | 56 ++++++++++++++++++++++++++++-----------
 1 file changed, 40 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 7e5449fb86a3fcdae8255bc490d12c543ef3f8ae..61559467e2d22b4b1b4223c97766ca3bf58908fd 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -344,6 +344,14 @@
 #define COLOR_BAR_MODE_BARS	2
 #define PLL_DBG			0x0a04
 
+enum tc_mode {
+	mode_dpi_to_edp = BIT(1) | BIT(2),
+	mode_dpi_to_dp  = BIT(1),
+	mode_dsi_to_edp = BIT(0) | BIT(2),
+	mode_dsi_to_dp  = BIT(0),
+	mode_dsi_to_dpi = BIT(0) | BIT(1),
+};
+
 static bool tc_test_pattern;
 module_param_named(test, tc_test_pattern, bool, 0644);
 
@@ -2327,7 +2335,6 @@ static int tc_probe_dpi_bridge_endpoint(struct tc_data *tc)
 	if (bridge) {
 		tc->panel_bridge = bridge;
 		tc->bridge.type = DRM_MODE_CONNECTOR_DPI;
-		tc->bridge.funcs = &tc_dpi_bridge_funcs;
 
 		return 0;
 	}
@@ -2360,7 +2367,6 @@ static int tc_probe_edp_bridge_endpoint(struct tc_data *tc)
 		tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
 	}
 
-	tc->bridge.funcs = &tc_edp_bridge_funcs;
 	if (tc->hpd_pin >= 0)
 		tc->bridge.ops |= DRM_BRIDGE_OP_DETECT;
 	tc->bridge.ops |= DRM_BRIDGE_OP_EDID;
@@ -2368,17 +2374,11 @@ static int tc_probe_edp_bridge_endpoint(struct tc_data *tc)
 	return 0;
 }
 
-static int tc_probe_bridge_endpoint(struct tc_data *tc)
+static enum tc_mode tc_probe_get_mode(struct device *dev)
 {
-	struct device *dev = tc->dev;
 	struct of_endpoint endpoint;
 	struct device_node *node = NULL;
-	const u8 mode_dpi_to_edp = BIT(1) | BIT(2);
-	const u8 mode_dpi_to_dp = BIT(1);
-	const u8 mode_dsi_to_edp = BIT(0) | BIT(2);
-	const u8 mode_dsi_to_dp = BIT(0);
-	const u8 mode_dsi_to_dpi = BIT(0) | BIT(1);
-	u8 mode = 0;
+	enum tc_mode mode = 0;
 
 	/*
 	 * Determine bridge configuration.
@@ -2401,7 +2401,27 @@ static int tc_probe_bridge_endpoint(struct tc_data *tc)
 			return -EINVAL;
 		}
 		mode |= BIT(endpoint.port);
+	}
+
+	if (mode != mode_dpi_to_edp &&
+	    mode != mode_dpi_to_dp  &&
+	    mode != mode_dsi_to_dpi &&
+	    mode != mode_dsi_to_edp &&
+	    mode != mode_dsi_to_dp) {
+		dev_warn(dev, "Invalid mode (0x%x) is not supported!\n", mode);
+		return -EINVAL;
+	}
+
+	return mode;
+}
 
+static int tc_probe_bridge_endpoint(struct tc_data *tc, enum tc_mode mode)
+{
+	struct device *dev = tc->dev;
+	struct of_endpoint endpoint;
+	struct device_node *node = NULL;
+
+	for_each_endpoint_of_node(dev->of_node, node) {
 		if (endpoint.port == 2) {
 			of_property_read_u8_array(node, "toshiba,pre-emphasis",
 						  tc->pre_emphasis,
@@ -2427,24 +2447,28 @@ static int tc_probe_bridge_endpoint(struct tc_data *tc)
 		return tc_probe_edp_bridge_endpoint(tc);
 	}
 
-	dev_warn(dev, "Invalid mode (0x%x) is not supported!\n", mode);
-
+	/* Should never happen, mode was validated by tc_probe_get_mode() */
 	return -EINVAL;
 }
 
 static int tc_probe(struct i2c_client *client)
 {
 	struct device *dev = &client->dev;
+	const struct drm_bridge_funcs *funcs;
 	struct tc_data *tc;
+	int mode;
 	int ret;
 
-	tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
-	if (!tc)
-		return -ENOMEM;
+	mode = tc_probe_get_mode(dev);
+	funcs = (mode == mode_dsi_to_dpi) ? &tc_dpi_bridge_funcs : &tc_edp_bridge_funcs;
+
+	tc = devm_drm_bridge_alloc(dev, struct tc_data, bridge, funcs);
+	if (IS_ERR(tc))
+		return PTR_ERR(tc);
 
 	tc->dev = dev;
 
-	ret = tc_probe_bridge_endpoint(tc);
+	ret = tc_probe_bridge_endpoint(tc, mode);
 	if (ret)
 		return ret;
 

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:46 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:46 +0200
Subject: [PATCH v3 20/22] drm/bridge: add devm_drm_put_bridge()
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-20-b8bc1f16d7aa@bootlin.com>

Bridges obtained via devm_drm_bridge_alloc(dev, ...) will be put when the
requesting device (@dev) is removed.

However drivers which obtained them may need to put the obtained reference
explicitly. One such case is if they bind the devm removal action to a
different device than the one implemented by the driver itself and which
might be removed at a different time, such as bridge/panel.c.

Add devm_drm_put_bridge() to manually release a devm-obtained bridge in
such cases.

This function is considered only a temporary workaround until the panel
bridge is reworked and should be removed afterwards.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Changes in v3:
- document this function is a temporary workaround, not to be used
  (in kerneldoc and commit message)

Changes in v2: none
---
 drivers/gpu/drm/drm_bridge.c | 17 +++++++++++++++++
 include/drm/drm_bridge.h     |  4 ++++
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c
index b4c89ec01998b849018ce031c7cd84614e65e710..d0e81639927a73422671b7b43f3e8a946f1d4300 100644
--- a/drivers/gpu/drm/drm_bridge.c
+++ b/drivers/gpu/drm/drm_bridge.c
@@ -1392,6 +1392,23 @@ struct drm_bridge *of_drm_find_bridge(struct device_node *np)
 EXPORT_SYMBOL(of_drm_find_bridge);
 #endif
 
+/**
+ * devm_drm_put_bridge - Release a bridge reference obtained via devm
+ * @dev: device that got the bridge via devm
+ * @bridge: pointer to a struct drm_bridge obtained via devm
+ *
+ * Same as drm_bridge_put() for bridge pointers obtained via devm functions
+ * such as devm_drm_bridge_alloc().
+ *
+ * This function is a temporary workaround and MUST NOT be used. Manual
+ * handling of bridge lifetime is inherently unsafe.
+ */
+void devm_drm_put_bridge(struct device *dev, struct drm_bridge *bridge)
+{
+	devm_release_action(dev, drm_bridge_put_void, bridge);
+}
+EXPORT_SYMBOL(devm_drm_put_bridge);
+
 static void drm_bridge_debugfs_show_bridge(struct drm_printer *p,
 					   struct drm_bridge *bridge,
 					   unsigned int idx)
diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h
index 4e418a29a9ff9d014d6ac0910a5d9bcf7118195e..6f00a3998ed6d026332b0f1e3bb5bee3cb5158e0 100644
--- a/include/drm/drm_bridge.h
+++ b/include/drm/drm_bridge.h
@@ -1265,6 +1265,8 @@ static inline struct drm_bridge *devm_drm_of_get_bridge(struct device *dev,
 	return ERR_PTR(-ENODEV);
 }
 
+static inline void devm_drm_put_bridge(struct device *dev, struct drm_bridge *bridge) {}
+
 static inline struct drm_bridge *drmm_of_get_bridge(struct drm_device *drm,
 						     struct device_node *node,
 						     u32 port,
@@ -1274,6 +1276,8 @@ static inline struct drm_bridge *drmm_of_get_bridge(struct drm_device *drm,
 }
 #endif
 
+void devm_drm_put_bridge(struct device *dev, struct drm_bridge *bridge);
+
 void drm_bridge_debugfs_params(struct dentry *root);
 void drm_bridge_debugfs_encoder_params(struct dentry *root, struct drm_encoder *encoder);
 

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:47 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:47 +0200
Subject: [PATCH v3 21/22] drm/bridge: panel: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-21-b8bc1f16d7aa@bootlin.com>

This is the new API for allocating DRM bridges.

The devm lifetime management of this driver is peculiar. The underlying
device for the panel_bridge is the panel, and the devm lifetime is tied the
panel device (panel->dev). However the panel_bridge allocation is not
performed by the panel driver, but rather by a separate entity (typically
the previous bridge in the encoder chain).

Thus when that separate entity is destroyed, the panel_bridge is not
removed automatically by devm, so it is rather done explicitly by calling
drm_panel_bridge_remove(). This is the function that does devm_kfree() the
panel_bridge in current code, so update it as well to put the bridge
reference instead.

This is a temporary solution until the panel lifetime is reworked, which
should make this workaround unnecessary, so add a comment to clarify that.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

Changes in v3:
- add TODO to remove devm_drm_put_bridge(), update commit message
- fix typo in commit message

Changes in v2: none
---
 drivers/gpu/drm/bridge/panel.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c
index 79b009ab9396048eac57ad47631a902e949d77c6..6cbbfb1381a4a75fbc3acf6e6c5361202627e740 100644
--- a/drivers/gpu/drm/bridge/panel.c
+++ b/drivers/gpu/drm/bridge/panel.c
@@ -287,15 +287,14 @@ struct drm_bridge *drm_panel_bridge_add_typed(struct drm_panel *panel,
 	if (!panel)
 		return ERR_PTR(-EINVAL);
 
-	panel_bridge = devm_kzalloc(panel->dev, sizeof(*panel_bridge),
-				    GFP_KERNEL);
-	if (!panel_bridge)
-		return ERR_PTR(-ENOMEM);
+	panel_bridge = devm_drm_bridge_alloc(panel->dev, struct panel_bridge, bridge,
+					     &panel_bridge_bridge_funcs);
+	if (IS_ERR(panel_bridge))
+		return (void *)panel_bridge;
 
 	panel_bridge->connector_type = connector_type;
 	panel_bridge->panel = panel;
 
-	panel_bridge->bridge.funcs = &panel_bridge_bridge_funcs;
 	panel_bridge->bridge.of_node = panel->dev->of_node;
 	panel_bridge->bridge.ops = DRM_BRIDGE_OP_MODES;
 	panel_bridge->bridge.type = connector_type;
@@ -327,7 +326,8 @@ void drm_panel_bridge_remove(struct drm_bridge *bridge)
 	panel_bridge = drm_bridge_to_panel_bridge(bridge);
 
 	drm_bridge_remove(bridge);
-	devm_kfree(panel_bridge->panel->dev, bridge);
+	/* TODO remove this after reworking panel_bridge lifetime */
+	devm_drm_put_bridge(panel_bridge->panel->dev, bridge);
 }
 EXPORT_SYMBOL(drm_panel_bridge_remove);
 

-- 
2.49.0



From luca.ceresoli at bootlin.com  Fri May  9 06:53:48 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 09 May 2025 15:53:48 +0200
Subject: [PATCH v3 22/22] drm/todo: add entry to remove
 devm_drm_put_bridge()
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250509-drm-bridge-convert-to-alloc-api-v3-22-b8bc1f16d7aa@bootlin.com>

devm_drm_put_bridge() is a temporary workaround waiting for the panel
bridge lifetime rework. Add a TODO entry to not forget it must be removed
after such rework.

Suggested-by: Maxime Ripard <mripard at kernel.org>
Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

---

To: Jonathan Corbet <corbet at lwn.net>
Cc: linux-doc at vger.kernel.org

This patch was added in v3
---
 Documentation/gpu/todo.rst | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index c57777a24e03d91b1ffe04365f7356f2d938befd..be8637da3fe950ddcb65cdcf626bc4b4e6b0fa26 100644
--- a/Documentation/gpu/todo.rst
+++ b/Documentation/gpu/todo.rst
@@ -515,6 +515,21 @@ Contact: Douglas Anderson <dianders at chromium.org>
 
 Level: Starter
 
+Remove devm_drm_put_bridge()
+----------------------------
+
+Due to how the panel bridge handles the drm_bridge object lifetime, special
+care must be taken to dispose of the drm_bridge object when the
+panel_bridge is removed. This is currently managed using
+devm_drm_put_bridge(), but that is an unsafe, temporary workaround. To fix
+that, the DRM panel lifetime needs to be reworked. After the rework is
+done, remove devm_drm_put_bridge() and the TODO in
+drm_panel_bridge_remove().
+
+Contact: Maxime Ripard <mripard at kernel.org>,
+         Luca Ceresoli <luca.ceresoli at bootlin.com>
+
+Level: Intermediate
 
 Core refactorings
 =================

-- 
2.49.0



From lorenzo at kernel.org  Fri May  9 07:51:32 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Fri, 09 May 2025 16:51:32 +0200
Subject: [PATCH net-next v2 0/2] Add the capability to allocate hw buffers
 in SRAM for EN7581 SoC
Message-ID: <20250509-airopha-desc-sram-v2-0-9dc3d8076dfb@kernel.org>

In order to improve packet processing and packet forwarding
performances, EN7581 SoC supports allocating buffers for hw forwarding
queues in SRAM instead of DRAM if available on the system.
Rely on SRAM for buffers allocation if available on the system and use
DRAM as fallback.

---
Changes in v2:
- fix sparse warnings
- Link to v1: https://lore.kernel.org/r/20250507-airopha-desc-sram-v1-0-d42037431bfa at kernel.org

---
Lorenzo Bianconi (2):
      dt-bindings: net: airoha: Add EN7581 memory-region property
      net: airoha: Add the capability to allocate hw buffers in SRAM

 .../devicetree/bindings/net/airoha,en7581-eth.yaml | 13 +++++
 drivers/net/ethernet/airoha/airoha_eth.c           | 57 ++++++++++++++++++----
 2 files changed, 61 insertions(+), 9 deletions(-)
---
base-commit: a9ce2ce1800e04267e6d99016ed0fe132d6049a9
change-id: 20250507-airopha-desc-sram-faeb3ea6cbc5

Best regards,
-- 
Lorenzo Bianconi <lorenzo at kernel.org>



From lorenzo at kernel.org  Fri May  9 07:51:33 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Fri, 09 May 2025 16:51:33 +0200
Subject: [PATCH net-next v2 1/2] dt-bindings: net: airoha: Add EN7581
 memory-region property
In-Reply-To: <20250509-airopha-desc-sram-v2-0-9dc3d8076dfb@kernel.org>
References: <20250509-airopha-desc-sram-v2-0-9dc3d8076dfb@kernel.org>
Message-ID: <20250509-airopha-desc-sram-v2-1-9dc3d8076dfb@kernel.org>

Introduce the memory-region and memory-region-names properties for the
ethernet node available on EN7581 SoC. In order to improve performances,
EN7581 SoC supports allocating buffers for hw forwarding queues in SRAM
instead of DRAM if available on the system.

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 .../devicetree/bindings/net/airoha,en7581-eth.yaml          | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
index 0fdd1126541774acacc783d98e4c089b2d2b85e2..6d22131ac2f9e28390b9e785ce33e8d983eafd0f 100644
--- a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
+++ b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
@@ -57,6 +57,16 @@ properties:
       - const: hsi-mac
       - const: xfp-mac
 
+  memory-region:
+    items:
+      - description: QDMA0 buffer memory
+      - description: QDMA1 buffer memory
+
+  memory-region-names:
+    items:
+      - const: qdma0-buf
+      - const: qdma1-buf
+
   "#address-cells":
     const: 1
 
@@ -140,6 +150,9 @@ examples:
                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
                      <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 
+        memory-region = <&qdma0_buf>, <&qdma1_buf>;
+        memory-region-names = "qdma0-buf", "qdma1-buf";
+
         airoha,npu = <&npu>;
 
         #address-cells = <1>;

-- 
2.49.0



From lorenzo at kernel.org  Fri May  9 07:51:34 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Fri, 09 May 2025 16:51:34 +0200
Subject: [PATCH net-next v2 2/2] net: airoha: Add the capability to
 allocate hw buffers in SRAM
In-Reply-To: <20250509-airopha-desc-sram-v2-0-9dc3d8076dfb@kernel.org>
References: <20250509-airopha-desc-sram-v2-0-9dc3d8076dfb@kernel.org>
Message-ID: <20250509-airopha-desc-sram-v2-2-9dc3d8076dfb@kernel.org>

In order to improve packet processing and packet forwarding
performances, EN7581 SoC supports allocating buffers for hw forwarding
queues in SRAM instead of DRAM if available on the system.
Rely on SRAM for buffers allocation if available on the system and use
DRAM as fallback.

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 drivers/net/ethernet/airoha/airoha_eth.c | 57 +++++++++++++++++++++++++++-----
 1 file changed, 48 insertions(+), 9 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 16c7896f931fd9532aa3b8cc78f41afc676aa117..b11c25442eb8c8c2b5aa45ded7a9d61e24aa2e4a 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -5,6 +5,7 @@
  */
 #include <linux/of.h>
 #include <linux/of_net.h>
+#include <linux/of_reserved_mem.h>
 #include <linux/platform_device.h>
 #include <linux/tcp.h>
 #include <linux/u64_stats_sync.h>
@@ -1076,9 +1077,11 @@ static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q)
 static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
 {
 	struct airoha_eth *eth = qdma->eth;
+	int id = qdma - &eth->qdma[0];
 	dma_addr_t dma_addr;
-	u32 status;
-	int size;
+	const char *name;
+	int size, index;
+	u32 status, val;
 
 	size = HW_DSCP_NUM * sizeof(struct airoha_qdma_fwd_desc);
 	qdma->hfwd.desc = dmam_alloc_coherent(eth->dev, size, &dma_addr,
@@ -1088,12 +1091,45 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
 
 	airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr);
 
-	size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM;
-	qdma->hfwd.q = dmam_alloc_coherent(eth->dev, size, &dma_addr,
-					   GFP_KERNEL);
-	if (!qdma->hfwd.q)
+	name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id);
+	if (!name)
 		return -ENOMEM;
 
+	index = of_property_match_string(eth->dev->of_node,
+					 "memory-region-names", name);
+	if (index >= 0) { /* buffers in sram */
+		struct reserved_mem *rmem;
+		struct device_node *np;
+		void *q;
+
+		np = of_parse_phandle(eth->dev->of_node, "memory-region",
+				      index);
+		if (!np)
+			return -ENODEV;
+
+		rmem = of_reserved_mem_lookup(np);
+		of_node_put(np);
+
+		/* SRAM is actual memory and supports transparent access just
+		 * like DRAM. Hence we don't require __iomem being set and
+		 * we don't need to use accessor routines to read from or write
+		 * to SRAM.
+		 */
+		q = (void __force *)devm_ioremap(eth->dev, rmem->base,
+						 rmem->size);
+		if (!q)
+			return -ENOMEM;
+
+		qdma->hfwd.q = q;
+		dma_addr = rmem->base;
+	} else {
+		size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM;
+		qdma->hfwd.q = dmam_alloc_coherent(eth->dev, size, &dma_addr,
+						   GFP_KERNEL);
+		if (!qdma->hfwd.q)
+			return -ENOMEM;
+	}
+
 	airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr);
 
 	airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG,
@@ -1101,11 +1137,14 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
 			FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 0));
 	airoha_qdma_rmw(qdma, REG_FWD_DSCP_LOW_THR, FWD_DSCP_LOW_THR_MASK,
 			FIELD_PREP(FWD_DSCP_LOW_THR_MASK, 128));
+
+	val = FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) |
+	      LMGR_INIT_START;
+	if (index >= 0)
+		val |= LMGR_SRAM_MODE_MASK;
 	airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG,
 			LMGR_INIT_START | LMGR_SRAM_MODE_MASK |
-			HW_FWD_DESC_NUM_MASK,
-			FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) |
-			LMGR_INIT_START);
+			HW_FWD_DESC_NUM_MASK, val);
 
 	return read_poll_timeout(airoha_qdma_rr, status,
 				 !(status & LMGR_INIT_START), USEC_PER_MSEC,

-- 
2.49.0



From bvanassche at acm.org  Fri May  9 08:07:55 2025
From: bvanassche at acm.org (Bart Van Assche)
Date: Fri, 9 May 2025 08:07:55 -0700
Subject: [PATCH v1] ufs: core: support updating device command timeout
In-Reply-To: <20250509071029.446697-1-peter.wang@mediatek.com>
References: <20250509071029.446697-1-peter.wang@mediatek.com>
Message-ID: <946d62cd-b1a1-4ddb-8411-2060362f7d33@acm.org>

On 5/9/25 12:08 AM, peter.wang at mediatek.com wrote:
> Some UFS device commands may timeout due to being blocked
> by regular SCSI write commands. Therefore, the timeout
> needs to be extended to 30 seconds, matching the SCSI write
> command timeout.

Does this happen with all UFS devices or only with some UFS devices? Is
this behavior perhaps a firmware bug? Processing of device commands
shouldn't be postponed until SCSI command processing has finished.

> +enum {
> +	QUERY_REQ_TIMEOUT_DEFAULT = 1500,
> +	QUERY_REQ_TIMEOUT_MAX     = 30000
> +};

[ ... ]

> +static int dev_cmd_timeout_set(const char *val, const struct kernel_param *kp)
> +{
> +	return param_set_uint_minmax(val, kp, QUERY_REQ_TIMEOUT_DEFAULT,
> +				     QUERY_REQ_TIMEOUT_MAX);
> +}

This change makes it impossible to reduce the device command timeout
below 1.5 seconds. I think that setting lower values can be useful for
error injection purposes.

Thanks,

Bart.


From peter.wang at mediatek.com  Fri May  9 09:11:49 2025
From: peter.wang at mediatek.com (=?utf-8?B?UGV0ZXIgV2FuZyAo546L5L+h5Y+LKQ==?=)
Date: Fri, 9 May 2025 16:11:49 +0000
Subject: [PATCH v1] ufs: core: support updating device command timeout
In-Reply-To: <946d62cd-b1a1-4ddb-8411-2060362f7d33@acm.org>
References: <20250509071029.446697-1-peter.wang@mediatek.com>
	 <946d62cd-b1a1-4ddb-8411-2060362f7d33@acm.org>
Message-ID: <8b56be3dee19dd210ceaac46a30f29f34b31a83c.camel@mediatek.com>

On Fri, 2025-05-09 at 08:07 -0700, Bart Van Assche wrote:
> Does this happen with all UFS devices or only with some UFS devices?
> Is
> this behavior perhaps a firmware bug? Processing of device commands
> shouldn't be postponed until SCSI command processing has finished.

Hi Bart,

We inquired with three UFS device vendors. Samsung and SKHynix
will need 30 seconds, while Micron does not have a specific number.


> This change makes it impossible to reduce the device command timeout
> below 1.5 seconds. I think that setting lower values can be useful
> for
> error injection purposes.
> 
> Thanks,
> 
> Bart.

Do you have a recommended number? Would min value 1 ms be acceptable?

Thanks.
Peter

From bvanassche at acm.org  Fri May  9 10:11:45 2025
From: bvanassche at acm.org (Bart Van Assche)
Date: Fri, 9 May 2025 10:11:45 -0700
Subject: [PATCH v1] ufs: core: support updating device command timeout
In-Reply-To: <8b56be3dee19dd210ceaac46a30f29f34b31a83c.camel@mediatek.com>
References: <20250509071029.446697-1-peter.wang@mediatek.com>
 <946d62cd-b1a1-4ddb-8411-2060362f7d33@acm.org>
 <8b56be3dee19dd210ceaac46a30f29f34b31a83c.camel@mediatek.com>
Message-ID: <bcf87e8b-a994-4168-821e-9c1c4d4771b0@acm.org>

On 5/9/25 9:11 AM, Peter Wang (???) wrote:
> Do you have a recommended number? Would min value 1 ms be acceptable?

That sounds good to me.

Thanks,

Bart.


From robh at kernel.org  Fri May  9 11:08:39 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Fri, 9 May 2025 13:08:39 -0500
Subject: [PATCH v2 02/13] ASoC: dt-bindings: mt8173-afe-pcm: Add power
 domain
In-Reply-To: <20250424102509.1083185-3-wenst@chromium.org>
References: <20250424102509.1083185-1-wenst@chromium.org>
 <20250424102509.1083185-3-wenst@chromium.org>
Message-ID: <174681411907.3875523.1397658621992836226.robh@kernel.org>


On Thu, 24 Apr 2025 18:24:56 +0800, Chen-Yu Tsai wrote:
> The audio subsystem sits under a controllable power domain.
> 
> Add it to the binding.
> 
> Signed-off-by: Chen-Yu Tsai <wenst at chromium.org>
> ---
>  .../devicetree/bindings/sound/mediatek,mt8173-afe-pcm.yaml  | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh at kernel.org>



From robh at kernel.org  Fri May  9 11:08:49 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Fri, 9 May 2025 13:08:49 -0500
Subject: [PATCH v2 03/13] ASoC: dt-bindings: mt8173-afe-pcm: Allow
 specifying reserved memory region
In-Reply-To: <20250424102509.1083185-4-wenst@chromium.org>
References: <20250424102509.1083185-1-wenst@chromium.org>
 <20250424102509.1083185-4-wenst@chromium.org>
Message-ID: <174681412863.3875813.695297684123812813.robh@kernel.org>


On Thu, 24 Apr 2025 18:24:57 +0800, Chen-Yu Tsai wrote:
> It is desirable to reserve memory for the audio frontend.
> 
> Allow the "memory-region" property, to be used to point to a reserved
> memory region.
> 
> Signed-off-by: Chen-Yu Tsai <wenst at chromium.org>
> ---
>  .../devicetree/bindings/sound/mediatek,mt8173-afe-pcm.yaml   | 5 +++++
>  1 file changed, 5 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh at kernel.org>



From robh at kernel.org  Fri May  9 11:08:57 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Fri, 9 May 2025 13:08:57 -0500
Subject: [PATCH v2 04/13] ASoC: dt-bindings: mt8186-afe-pcm: Allow
 specifying reserved memory region
In-Reply-To: <20250424102509.1083185-5-wenst@chromium.org>
References: <20250424102509.1083185-1-wenst@chromium.org>
 <20250424102509.1083185-5-wenst@chromium.org>
Message-ID: <174681413699.3876088.12249965431481195226.robh@kernel.org>


On Thu, 24 Apr 2025 18:24:58 +0800, Chen-Yu Tsai wrote:
> It is desirable to reserve memory for the audio frontend.
> 
> Allow the "memory-region" property, to be used to point to a reserved
> memory region.
> 
> Signed-off-by: Chen-Yu Tsai <wenst at chromium.org>
> ---
>  Documentation/devicetree/bindings/sound/mt8186-afe-pcm.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh at kernel.org>



From robh at kernel.org  Fri May  9 11:09:15 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Fri, 9 May 2025 13:09:15 -0500
Subject: [PATCH v2 05/13] ASoC: dt-bindings: mt8192-afe-pcm: Allow
 specifying reserved memory region
In-Reply-To: <20250424102509.1083185-6-wenst@chromium.org>
References: <20250424102509.1083185-1-wenst@chromium.org>
 <20250424102509.1083185-6-wenst@chromium.org>
Message-ID: <174681415530.3876555.5160678199255318947.robh@kernel.org>


On Thu, 24 Apr 2025 18:24:59 +0800, Chen-Yu Tsai wrote:
> It is desirable to reserve memory for the audio frontend.
> 
> Allow the "memory-region" property, to be used to point to a reserved
> memory region.
> 
> Signed-off-by: Chen-Yu Tsai <wenst at chromium.org>
> ---
>  Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh at kernel.org>



From arnd at arndb.de  Fri May  9 13:54:53 2025
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 09 May 2025 22:54:53 +0200
Subject: [GIT,PULL,1/2] MediaTek ARM64 DTS updates for v6.16
In-Reply-To: <20250506091736.125733-1-angelogioacchino.delregno@collabora.com>
References: <20250506091736.125733-1-angelogioacchino.delregno@collabora.com>
Message-ID: <7e8718b0-df78-44a6-a102-89529d6abcce@app.fastmail.com>

On Tue, May 6, 2025, at 11:17, AngeloGioacchino Del Regno wrote:

>    - Since SCP firmwares are available on linux-firmware, the
>      necessary nodes for the dual-core SCP were added to devicetree
>      along with the firmware-name property in mt8390-genio-common,
>      enabling hardware video encoders and decoders on the MediaTek
>      Genio 510 and Genio 700 EVKs.

This looks wrong to me: the devicetree should never care about
particular file names in a Linux repository.

Usually what happens is that the device driver must work with
a particular firmware version, so the driver is the one that
constructs a name based on what firmware is knows and what
hardware it is running on, so a newer version of the driver
can attempt to load a newer firmware that may be incompatible
with the old driver.

The other patches in the branch all look fine to me.

Can you resend the pull request without these patches and
try to come up with a different approach?

     Arnd


From yunfei.dong at mediatek.com  Sat May 10 00:53:31 2025
From: yunfei.dong at mediatek.com (Yunfei Dong)
Date: Sat, 10 May 2025 15:53:31 +0800
Subject: [PATCH 01/14] dt-bindings: media: mediatek: vcodec: add decoder dt-bindings for mt8196
In-Reply-To: <20250510075357.11761-1-yunfei.dong@mediatek.com>
References: <20250510075357.11761-1-yunfei.dong@mediatek.com>
Message-ID: <20250510075357.11761-2-yunfei.dong@mediatek.com>

Add compatible for video decoder on MT8196 platform, which is a
lat + single core architecture.

Signed-off-by: Yunfei Dong <yunfei.dong at mediatek.com>
---
 .../bindings/media/mediatek,vcodec-subdev-decoder.yaml           | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
index bf8082d87ac0..74e1d88d3056 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
@@ -76,6 +76,7 @@ properties:
       - mediatek,mt8186-vcodec-dec
       - mediatek,mt8188-vcodec-dec
       - mediatek,mt8195-vcodec-dec
+      - mediatek,mt8196-vcodec-dec
 
   reg:
     minItems: 1
-- 
2.46.0



From yunfei.dong at mediatek.com  Sat May 10 00:53:34 2025
From: yunfei.dong at mediatek.com (Yunfei Dong)
Date: Sat, 10 May 2025 15:53:34 +0800
Subject: [PATCH 04/14] media: mediatek: vcodec: add driver to support vcp encoder
In-Reply-To: <20250510075357.11761-1-yunfei.dong@mediatek.com>
References: <20250510075357.11761-1-yunfei.dong@mediatek.com>
Message-ID: <20250510075357.11761-5-yunfei.dong@mediatek.com>

Encoder also need to call vcp interface to communicate with vcp,
add driver to support encoder.

Signed-off-by: Yunfei Dong <yunfei.dong at mediatek.com>
---
 .../vcodec/common/mtk_vcodec_fw_vcp.c         | 40 +++++++++++++++----
 .../vcodec/common/mtk_vcodec_fw_vcp.h         |  1 +
 .../mediatek/vcodec/encoder/mtk_vcodec_enc.c  |  1 -
 .../mediatek/vcodec/encoder/mtk_vcodec_enc.h  |  2 +
 4 files changed, 36 insertions(+), 8 deletions(-)

diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
index 227310c116c6..c9e5cde40aef 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
@@ -13,6 +13,8 @@
 
 #include "../decoder/mtk_vcodec_dec_drv.h"
 #include "../decoder/vdec_ipi_msg.h"
+#include "../encoder/mtk_vcodec_enc.h"
+#include "../encoder/mtk_vcodec_enc_drv.h"
 #include "mtk_vcodec_fw_priv.h"
 
 #define IPI_SEND_TIMEOUT_MS  100U
@@ -189,8 +191,8 @@ static int mtk_vcodec_vcp_msg_ipi_send(struct mtk_vcodec_fw *fw, int id, void *b
 	}
 
 	mutex_lock(msg_mutex);
-	feature_id = VDEC_FEATURE_ID;
-	mailbox_id = IPI_OUT_VDEC_1;
+	feature_id = (fw->fw_use == ENCODER) ? VENC_FEATURE_ID : VDEC_FEATURE_ID;
+	mailbox_id = (fw->fw_use == ENCODER) ? IPI_OUT_VENC_0 : IPI_OUT_VDEC_1;
 
 	timeout_jiffies = jiffies + msecs_to_jiffies(VCP_SYNC_TIMEOUT_MS);
 	while (!vcp_device->ops->vcp_is_ready(feature_id)) {
@@ -300,10 +302,10 @@ static int mtk_vcodec_vcp_load_firmware(struct mtk_vcodec_fw *fw)
 
 	vcp_device = fw->vcp->vcp_device;
 
-	feature_id = VDEC_FEATURE_ID;
-	mem_id = VDEC_MEM_ID;
-	mailbox_id = IPI_IN_VDEC_1;
-	ipi_id = VCP_IPI_LAT_DECODER;
+	feature_id = fw->fw_use == ENCODER ? VENC_FEATURE_ID : VDEC_FEATURE_ID;
+	mem_id = fw->fw_use == ENCODER ? VENC_MEM_ID : VDEC_MEM_ID;
+	mailbox_id = fw->fw_use == ENCODER ? IPI_IN_VENC_0 : IPI_IN_VDEC_1;
+	ipi_id = fw->fw_use == ENCODER ? VCP_IPI_ENCODER : VCP_IPI_LAT_DECODER;
 
 	ret = mtk_vcp_mbox_ipc_register(vcp_get_ipidev(vcp_device), mailbox_id,
 					mtk_vcodec_vcp_msg_ack_isr, fw, &fw->vcp->share_data);
@@ -322,6 +324,20 @@ static int mtk_vcodec_vcp_load_firmware(struct mtk_vcodec_fw *fw)
 	mutex_init(&fw->vcp->ipi_desc[ipi_id].lock);
 	mutex_init(&fw->vcp->ipi_mutex);
 
+	if (fw->fw_use == ENCODER) {
+		kthread_run(mtk_vcodec_vcp_msg_process_thread, fw, "vcp_enc_msq_thread");
+
+		fw->vcp->vsi_addr = vcp_device->ops->vcp_get_mem_virt(mem_id);
+		fw->vcp->vsi_size = vcp_device->ops->vcp_get_mem_size(mem_id);
+		fw->vcp->iova_addr = vcp_device->ops->vcp_get_mem_iova(mem_id);
+
+		dev_dbg(&fw->pdev->dev, "enc vcp init done => va: %p size:0x%x iova:%pad.\n",
+			fw->vcp->vsi_addr, fw->vcp->vsi_size, &fw->vcp->iova_addr);
+
+		init_waitqueue_head(&fw->vcp->msg_wq[VCP_IPI_ENCODER]);
+		return 0;
+	}
+
 	kthread_run(mtk_vcodec_vcp_msg_process_thread, fw, "vcp_vdec_msq_thread");
 
 	fw->vcp->vsi_addr = vcp_device->ops->vcp_get_mem_virt(mem_id);
@@ -345,6 +361,11 @@ static unsigned int mtk_vcodec_vcp_get_vdec_capa(struct mtk_vcodec_fw *fw)
 	       MTK_VDEC_IS_SUPPORT_10BIT | MTK_VDEC_IS_SUPPORT_EXT;
 }
 
+static unsigned int mtk_vcodec_vcp_get_venc_capa(struct mtk_vcodec_fw *fw)
+{
+	return MTK_VENC_4K_CAPABILITY_ENABLE;
+}
+
 static void *mtk_vcodec_vcp_dm_addr(struct mtk_vcodec_fw *fw, u32 dtcm_dmem_addr)
 {
 	return NULL;
@@ -396,6 +417,7 @@ static void mtk_vcodec_vcp_release(struct mtk_vcodec_fw *fw)
 static const struct mtk_vcodec_fw_ops mtk_vcodec_vcp_msg = {
 	.load_firmware = mtk_vcodec_vcp_load_firmware,
 	.get_vdec_capa = mtk_vcodec_vcp_get_vdec_capa,
+	.get_venc_capa = mtk_vcodec_vcp_get_venc_capa,
 	.map_dm_addr = mtk_vcodec_vcp_dm_addr,
 	.ipi_register = mtk_vcodec_vcp_set_ipi_register,
 	.ipi_send = mtk_vcodec_vcp_ipi_send,
@@ -409,7 +431,11 @@ struct mtk_vcodec_fw *mtk_vcodec_fw_vcp_init(void *priv, enum mtk_vcodec_fw_use
 	struct mtk_vcodec_fw *fw;
 	int i;
 
-	if (fw_use == DECODER) {
+	if (fw_use == ENCODER) {
+		struct mtk_vcodec_enc_dev *enc_dev = priv;
+
+		plat_dev = enc_dev->plat_dev;
+	} else if (fw_use == DECODER) {
 		struct mtk_vcodec_dec_dev *dec_dev = priv;
 
 		plat_dev = dec_dev->plat_dev;
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.h b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.h
index 40f5481d1889..53080ed12c69 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.h
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.h
@@ -16,6 +16,7 @@ typedef void (*vcp_ipi_handler_t) (void *data, unsigned int len, void *priv);
 
 /* enum mtk_vcp_ipi_index - index used to separate different hardware */
 enum mtk_vcp_ipi_index {
+	VCP_IPI_ENCODER,
 	VCP_IPI_LAT_DECODER,
 	VCP_IPI_CORE_DECODER,
 	VCP_IPI_MAX,
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
index a01dc25a7699..dcafb1303c29 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
@@ -26,7 +26,6 @@
 
 #define MTK_DEFAULT_FRAMERATE_NUM 1001
 #define MTK_DEFAULT_FRAMERATE_DENOM 30000
-#define MTK_VENC_4K_CAPABILITY_ENABLE BIT(0)
 
 static void mtk_venc_worker(struct work_struct *work);
 
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.h b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.h
index 908d8179b2d2..84156c102d8d 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.h
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.h
@@ -23,6 +23,8 @@
 #define MTK_VENC_IRQ_STATUS_OFFSET	0x05C
 #define MTK_VENC_IRQ_ACK_OFFSET	0x060
 
+#define MTK_VENC_4K_CAPABILITY_ENABLE BIT(0)
+
 /**
  * struct mtk_video_enc_buf - Private data related to each VB2 buffer.
  * @m2m_buf:	M2M buffer
-- 
2.46.0



From yunfei.dong at mediatek.com  Sat May 10 00:53:32 2025
From: yunfei.dong at mediatek.com (Yunfei Dong)
Date: Sat, 10 May 2025 15:53:32 +0800
Subject: [PATCH 02/14] media: mediatek: vcodec: add decoder compatible to support mt8196
In-Reply-To: <20250510075357.11761-1-yunfei.dong@mediatek.com>
References: <20250510075357.11761-1-yunfei.dong@mediatek.com>
Message-ID: <20250510075357.11761-3-yunfei.dong@mediatek.com>

MT8196 is lat single core architecture. Support its compatible and
use `mtk_lat_sig_core_pdata` to initialize platform data.

Signed-off-by: Yunfei Dong <yunfei.dong at mediatek.com>
---
 .../platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c   | 6 ++++++
 .../platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h   | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
index 9247d92d431d..fa609343c168 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
@@ -346,6 +346,8 @@ static void mtk_vcodec_dec_get_chip_name(struct mtk_vcodec_dec_dev *vdec_dev)
 		vdec_dev->chip_name = MTK_VDEC_MT8186;
 	else if (of_device_is_compatible(dev->of_node, "mediatek,mt8188-vcodec-dec"))
 		vdec_dev->chip_name = MTK_VDEC_MT8188;
+	else if (of_device_is_compatible(dev->of_node, "mediatek,mt8196-vcodec-dec"))
+		vdec_dev->chip_name = MTK_VDEC_MT8196;
 	else
 		vdec_dev->chip_name = MTK_VDEC_INVAL;
 }
@@ -559,6 +561,10 @@ static const struct of_device_id mtk_vcodec_match[] = {
 		.compatible = "mediatek,mt8188-vcodec-dec",
 		.data = &mtk_lat_sig_core_pdata,
 	},
+	{
+		.compatible = "mediatek,mt8196-vcodec-dec",
+		.data = &mtk_lat_sig_core_pdata,
+	},
 	{},
 };
 
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h
index aececca7ecf8..6bdde600a167 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h
@@ -27,6 +27,7 @@ enum mtk_vcodec_dec_chip_name {
 	MTK_VDEC_MT8188 = 8188,
 	MTK_VDEC_MT8192 = 8192,
 	MTK_VDEC_MT8195 = 8195,
+	MTK_VDEC_MT8196 = 8196,
 };
 
 /*
-- 
2.46.0



From yunfei.dong at mediatek.com  Sat May 10 00:53:33 2025
From: yunfei.dong at mediatek.com (Yunfei Dong)
Date: Sat, 10 May 2025 15:53:33 +0800
Subject: [PATCH 03/14] media: mediatek: vcodec: add driver to support vcp
In-Reply-To: <20250510075357.11761-1-yunfei.dong@mediatek.com>
References: <20250510075357.11761-1-yunfei.dong@mediatek.com>
Message-ID: <20250510075357.11761-4-yunfei.dong@mediatek.com>

The processor is changed from scp to vcp in mt8196 platform.
Adding new firmware interface to communicate kernel with vcp
for the communication method is changed.

Signed-off-by: Yunfei Dong <yunfei.dong at mediatek.com>
---
 .../media/platform/mediatek/vcodec/Kconfig    |   4 +
 .../platform/mediatek/vcodec/common/Makefile  |   4 +
 .../mediatek/vcodec/common/mtk_vcodec_fw.c    |   3 +
 .../mediatek/vcodec/common/mtk_vcodec_fw.h    |   1 +
 .../vcodec/common/mtk_vcodec_fw_priv.h        |  12 +
 .../vcodec/common/mtk_vcodec_fw_vcp.c         | 449 ++++++++++++++++++
 .../vcodec/common/mtk_vcodec_fw_vcp.h         | 137 ++++++
 include/linux/remoteproc/mtk_vcp_public.h     |   2 +-
 8 files changed, 611 insertions(+), 1 deletion(-)
 create mode 100644 drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
 create mode 100644 drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.h

diff --git a/drivers/media/platform/mediatek/vcodec/Kconfig b/drivers/media/platform/mediatek/vcodec/Kconfig
index bc8292232530..d23dad5c78ce 100644
--- a/drivers/media/platform/mediatek/vcodec/Kconfig
+++ b/drivers/media/platform/mediatek/vcodec/Kconfig
@@ -1,4 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
+config VIDEO_MEDIATEK_VCODEC_VCP
+	bool
+
 config VIDEO_MEDIATEK_VCODEC_SCP
 	bool
 
@@ -21,6 +24,7 @@ config VIDEO_MEDIATEK_VCODEC
 	select V4L2_MEM2MEM_DEV
 	select VIDEO_MEDIATEK_VCODEC_VPU if VIDEO_MEDIATEK_VPU
 	select VIDEO_MEDIATEK_VCODEC_SCP if MTK_SCP
+	select VIDEO_MEDIATEK_VCODEC_VCP if MTK_VCP_RPROC
 	select V4L2_H264
 	select V4L2_VP9
 	select MEDIA_CONTROLLER
diff --git a/drivers/media/platform/mediatek/vcodec/common/Makefile b/drivers/media/platform/mediatek/vcodec/common/Makefile
index d0479914dfb3..2f68692e8c98 100644
--- a/drivers/media/platform/mediatek/vcodec/common/Makefile
+++ b/drivers/media/platform/mediatek/vcodec/common/Makefile
@@ -14,6 +14,10 @@ ifneq ($(CONFIG_VIDEO_MEDIATEK_VCODEC_SCP),)
 mtk-vcodec-common-y += mtk_vcodec_fw_scp.o
 endif
 
+ifneq ($(CONFIG_VIDEO_MEDIATEK_VCODEC_VCP),)
+mtk-vcodec-common-y += mtk_vcodec_fw_vcp.o
+endif
+
 ifneq ($(CONFIG_DEBUG_FS),)
 obj-$(CONFIG_VIDEO_MEDIATEK_VCODEC) += mtk-vcodec-dbgfs.o
 
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
index 08949b08fbc6..fc547afa4ebf 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
@@ -3,6 +3,7 @@
 #include "../decoder/mtk_vcodec_dec_drv.h"
 #include "../encoder/mtk_vcodec_enc_drv.h"
 #include "mtk_vcodec_fw_priv.h"
+#include "mtk_vcodec_fw_vcp.h"
 
 struct mtk_vcodec_fw *mtk_vcodec_fw_select(void *priv, enum mtk_vcodec_fw_type type,
 					   enum mtk_vcodec_fw_use fw_use)
@@ -19,6 +20,8 @@ struct mtk_vcodec_fw *mtk_vcodec_fw_select(void *priv, enum mtk_vcodec_fw_type t
 		return mtk_vcodec_fw_vpu_init(priv, fw_use);
 	case SCP:
 		return mtk_vcodec_fw_scp_init(priv, fw_use);
+	case VCP:
+		return mtk_vcodec_fw_vcp_init(priv, fw_use);
 	default:
 		dev_err(&plat_dev->dev, "Invalid vcodec fw type");
 		return ERR_PTR(-EINVAL);
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h
index 300363a40158..c1642fb09b42 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h
@@ -14,6 +14,7 @@ struct mtk_vcodec_enc_dev;
 enum mtk_vcodec_fw_type {
 	VPU,
 	SCP,
+	VCP,
 };
 
 enum mtk_vcodec_fw_use {
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_priv.h b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_priv.h
index 99603accd82e..0a2a9b010244 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_priv.h
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_priv.h
@@ -4,6 +4,7 @@
 #define _MTK_VCODEC_FW_PRIV_H_
 
 #include "mtk_vcodec_fw.h"
+#include "mtk_vcodec_fw_vcp.h"
 
 struct mtk_vcodec_dec_dev;
 struct mtk_vcodec_enc_dev;
@@ -13,6 +14,7 @@ struct mtk_vcodec_fw {
 	const struct mtk_vcodec_fw_ops *ops;
 	struct platform_device *pdev;
 	struct mtk_scp *scp;
+	struct mtk_vcp *vcp;
 	enum mtk_vcodec_fw_use fw_use;
 };
 
@@ -49,4 +51,14 @@ mtk_vcodec_fw_scp_init(void *priv, enum mtk_vcodec_fw_use fw_use)
 }
 #endif /* CONFIG_VIDEO_MEDIATEK_VCODEC_SCP */
 
+#if IS_ENABLED(CONFIG_VIDEO_MEDIATEK_VCODEC_VCP)
+struct mtk_vcodec_fw *mtk_vcodec_fw_vcp_init(void *priv, enum mtk_vcodec_fw_use fw_use);
+#else
+static inline struct mtk_vcodec_fw *
+mtk_vcodec_fw_vcp_init(void *priv, enum mtk_vcodec_fw_use fw_use)
+{
+	return ERR_PTR(-ENODEV);
+}
+#endif /* CONFIG_VIDEO_MEDIATEK_VCODEC_VCP */
+
 #endif /* _MTK_VCODEC_FW_PRIV_H_ */
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
new file mode 100644
index 000000000000..227310c116c6
--- /dev/null
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
@@ -0,0 +1,449 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Yunfei Dong <yunfei.dong at mediatek.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-direction.h>
+#include <linux/dma-mapping.h>
+#include <linux/iommu.h>
+#include <linux/remoteproc/mtk_vcp_public.h>
+#include <linux/firmware/mediatek/mtk-vcp-ipc.h>
+
+#include "../decoder/mtk_vcodec_dec_drv.h"
+#include "../decoder/vdec_ipi_msg.h"
+#include "mtk_vcodec_fw_priv.h"
+
+#define IPI_SEND_TIMEOUT_MS  100U
+#define IPI_TIMEOUT_MS       100U
+
+static void mtk_vcodec_vcp_ipi_lock(struct mtk_vcp *vcp, u32 ipi_id)
+{
+	if (WARN_ON(ipi_id >= VCP_IPI_MAX))
+		return;
+
+	mutex_lock(&vcp->ipi_desc[ipi_id].lock);
+}
+
+static void mtk_vcodec_vcp_ipi_unlock(struct mtk_vcp *vcp, u32 ipi_id)
+{
+	if (WARN_ON(ipi_id >= VCP_IPI_MAX))
+		return;
+
+	mutex_unlock(&vcp->ipi_desc[ipi_id].lock);
+}
+
+static int mtk_vcodec_vcp_notifier(struct notifier_block *nb, unsigned long event, void *ptr)
+{
+	struct mtk_vcp *vcp = container_of(nb, struct mtk_vcp, vcp_notify);
+
+	switch (event) {
+	case VCP_EVENT_SUSPEND:
+	case VCP_EVENT_STOP:
+		dev_dbg(&vcp->pdev->dev, "vcp notifier suspend");
+		break;
+	case VCP_EVENT_READY:
+	case VCP_EVENT_RESUME:
+		dev_dbg(&vcp->pdev->dev, "vcp notifier ready");
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+static void mtk_vcodec_vcp_free_msg_node(struct mtk_vcodec_fw *fw,
+					 struct mtk_vcp_msg_node *msg_node)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&fw->vcp->msg_queue.lock, flags);
+	list_add(&msg_node->list, &fw->vcp->msg_queue.node_list);
+	spin_unlock_irqrestore(&fw->vcp->msg_queue.lock, flags);
+}
+
+static int mtk_vcodec_vcp_ipi_register(struct mtk_vcp *vcp, u32 ipi_id, vcp_ipi_handler_t handler,
+				       void *priv)
+{
+	if (!vcp)
+		return -EPROBE_DEFER;
+
+	if (WARN_ON(ipi_id >= VCP_IPI_MAX) || WARN_ON(!handler))
+		return -EINVAL;
+
+	mtk_vcodec_vcp_ipi_lock(vcp, ipi_id);
+	vcp->ipi_desc[ipi_id].handler = handler;
+	vcp->ipi_desc[ipi_id].priv = priv;
+	mtk_vcodec_vcp_ipi_unlock(vcp, ipi_id);
+
+	return 0;
+}
+
+static int mtk_vcodec_vcp_msg_process_thread(void *arg)
+{
+	struct mtk_vcodec_fw *fw = arg;
+	struct vdec_vpu_ipi_ack *msg = NULL;
+	struct mtk_vcp_share_obj *obj;
+	struct mtk_vcp_msg_node *msg_node;
+	unsigned long flags;
+	vcp_ipi_handler_t handler;
+	int ret = 0;
+
+	do {
+		ret = wait_event_interruptible(fw->vcp->msg_queue.wq,
+					       atomic_read(&fw->vcp->msg_queue.cnt) > 0);
+		if (ret < 0) {
+			dev_err(&fw->pdev->dev, "wait msg queue ack timeout %d %d\n",
+				ret, atomic_read(&fw->vcp->msg_queue.cnt));
+			continue;
+		}
+
+		spin_lock_irqsave(&fw->vcp->msg_queue.lock, flags);
+		msg_node = list_entry(fw->vcp->msg_queue.msg_list.next,
+				      struct mtk_vcp_msg_node, list);
+		list_del(&msg_node->list);
+		atomic_dec(&fw->vcp->msg_queue.cnt);
+		spin_unlock_irqrestore(&fw->vcp->msg_queue.lock, flags);
+
+		obj = &msg_node->ipi_data;
+		msg = (struct vdec_vpu_ipi_ack *)obj->share_buf;
+
+		if (!msg->ap_inst_addr) {
+			dev_err(&fw->pdev->dev, "invalid message address\n");
+			mtk_vcodec_vcp_free_msg_node(fw, msg_node);
+			continue;
+		}
+
+		dev_dbg(&fw->pdev->dev, "msg ack id %d len %d msg_id 0x%x\n", obj->id, obj->len,
+			msg->msg_id);
+
+		mtk_vcodec_vcp_ipi_lock(fw->vcp, obj->id);
+		handler = fw->vcp->ipi_desc[obj->id].handler;
+		if (!handler) {
+			dev_err(&fw->pdev->dev, "invalid ack ipi handler id = %d\n", obj->id);
+			mtk_vcodec_vcp_ipi_unlock(fw->vcp, obj->id);
+			mtk_vcodec_vcp_free_msg_node(fw, msg_node);
+			return -EINVAL;
+		}
+
+		handler(msg, obj->len, fw->vcp->ipi_desc[obj->id].priv);
+		mtk_vcodec_vcp_ipi_unlock(fw->vcp, obj->id);
+
+		fw->vcp->msg_signaled[obj->id] = true;
+		wake_up(&fw->vcp->msg_wq[obj->id]);
+
+		mtk_vcodec_vcp_free_msg_node(fw, msg_node);
+	} while (!kthread_should_stop());
+
+	return ret;
+}
+
+static int mtk_vcodec_vcp_msg_ack_isr(unsigned int id, void *prdata, void *data, unsigned int len)
+{
+	struct mtk_vcodec_fw *fw = prdata;
+	struct mtk_vcp_msg_queue *msg_queue = &fw->vcp->msg_queue;
+	struct mtk_vcp_msg_node *msg_node;
+	struct vdec_vpu_ipi_ack *msg = NULL;
+	struct mtk_vcp_share_obj *obj = data;
+	unsigned long flags;
+
+	msg = (struct vdec_vpu_ipi_ack *)obj->share_buf;
+
+	spin_lock_irqsave(&msg_queue->lock, flags);
+	if (!list_empty(&msg_queue->node_list)) {
+		msg_node = list_entry(msg_queue->node_list.next, struct mtk_vcp_msg_node, list);
+
+		memcpy(&msg_node->ipi_data, obj, sizeof(*obj));
+		list_move_tail(&msg_node->list, &msg_queue->msg_list);
+		atomic_inc(&msg_queue->cnt);
+		spin_unlock_irqrestore(&msg_queue->lock, flags);
+
+		dev_dbg(&fw->pdev->dev, "push ipi_id %x msg_id %x, msg cnt %d\n",
+			obj->id, msg->msg_id, atomic_read(&msg_queue->cnt));
+
+		wake_up(&msg_queue->wq);
+	} else {
+		spin_unlock_irqrestore(&msg_queue->lock, flags);
+		dev_err(&fw->pdev->dev, "no free nodes in msg queue\n");
+	}
+
+	return 0;
+}
+
+static int mtk_vcodec_vcp_msg_ipi_send(struct mtk_vcodec_fw *fw, int id, void *buf,
+				       unsigned int len, unsigned int wait)
+{
+	struct mtk_vcp *vcp = fw->vcp;
+	struct mtk_vcp_device *vcp_device = vcp->vcp_device;
+	struct mutex *msg_mutex = &vcp->ipi_mutex;
+	bool *msg_signaled = &vcp->msg_signaled[id];
+	wait_queue_head_t *msg_wq = &vcp->msg_wq[id];
+	int ret, ipi_size, feature_id, mailbox_id, retry_cnt = 0;
+	unsigned long timeout_jiffies = 0;
+	struct mtk_vcp_share_obj obj = {0};
+	unsigned int *data;
+
+	if (!vcp_device) {
+		dev_dbg(&fw->pdev->dev, "vcp device is null\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(msg_mutex);
+	feature_id = VDEC_FEATURE_ID;
+	mailbox_id = IPI_OUT_VDEC_1;
+
+	timeout_jiffies = jiffies + msecs_to_jiffies(VCP_SYNC_TIMEOUT_MS);
+	while (!vcp_device->ops->vcp_is_ready(feature_id)) {
+		if (time_after(jiffies, timeout_jiffies)) {
+			vcp->ipi_id_ack[id] = -EINVAL;
+			ret = -EINVAL;
+			goto error;
+		}
+		mdelay(1);
+	}
+
+	if (len > VCP_SHARE_BUF_SIZE) {
+		vcp->ipi_id_ack[id] = -EINVAL;
+		ret = -EINVAL;
+		goto error;
+	}
+
+	obj.id = id;
+	obj.len = len;
+	memcpy(obj.share_buf, buf, len);
+
+	ipi_size = ((sizeof(u32) * 2) + len + 3) / 4;
+	data = (unsigned int *)obj.share_buf;
+	dev_dbg(&fw->pdev->dev, "vcp send message: id %d len %d data 0x%x\n",
+		obj.id, obj.len, data[0]);
+
+	ret = mtk_vcp_ipc_send(vcp_get_ipidev(vcp_device), mailbox_id, &obj, ipi_size);
+	if (ret != IPI_ACTION_DONE) {
+		vcp->ipi_id_ack[id] = -EIO;
+		ret = -EIO;
+		goto error;
+	}
+
+wait_ack:
+	/* wait for VCP's ACK */
+	ret = wait_event_timeout(*msg_wq, *msg_signaled, msecs_to_jiffies(IPI_TIMEOUT_MS));
+	if (!ret || retry_cnt > 5) {
+		vcp->ipi_id_ack[id] = VCODEC_IPI_MSG_STATUS_FAIL;
+		dev_err(&fw->pdev->dev, "wait ipi ack timeout! %d %d\n", ret, vcp->ipi_id_ack[id]);
+	} else if (ret == -ERESTARTSYS) {
+		dev_err(&fw->pdev->dev, "wait ipi ack err (%d)\n", vcp->ipi_id_ack[id]);
+		retry_cnt++;
+		goto wait_ack;
+	} else if (ret < 0) {
+		dev_err(&fw->pdev->dev, "wait ipi ack fail ret %d %d\n", ret, vcp->ipi_id_ack[id]);
+		vcp->ipi_id_ack[id] = VCODEC_IPI_MSG_STATUS_FAIL;
+	}
+
+	dev_dbg(&fw->pdev->dev, "receive message: id %d len %d data 0x%x\n",
+		obj.id, obj.len, data[0]);
+
+	*msg_signaled = false;
+	mutex_unlock(msg_mutex);
+
+	return vcp->ipi_id_ack[id];
+
+error:
+	mutex_unlock(msg_mutex);
+	dev_err(&fw->pdev->dev, "send msg error type:%d msg:%d > %d ret:%d\n", fw->type, len,
+		VCP_SHARE_BUF_SIZE, ret);
+
+	return ret;
+}
+
+static int mtk_vcodec_vcp_get_vcp_device(struct mtk_vcodec_fw *fw)
+{
+	struct device *dev = &fw->pdev->dev;
+	int retry = 0, retry_cnt = 10000;
+	phandle vcp_phandle;
+
+	while (request_module("mtk-vcp")) {
+		if (++retry > retry_cnt) {
+			dev_err(dev, "failed to load mtk-vcp module");
+			return -ENODEV;
+		}
+		msleep(1);
+	}
+
+	if (of_property_read_u32(dev->of_node, "mediatek,vcp", &vcp_phandle)) {
+		dev_err(dev, "can't get vcp handle.\n");
+		return -ENODEV;
+	}
+
+	fw->vcp->vcp_device = mtk_vcp_get_by_phandle(vcp_phandle);
+	if (!fw->vcp->vcp_device) {
+		dev_err(dev, "get vcp device failed\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int mtk_vcodec_vcp_load_firmware(struct mtk_vcodec_fw *fw)
+{
+	struct mtk_vcp_device *vcp_device;
+	int ret, feature_id, mem_id, mailbox_id, ipi_id;
+
+	if (fw->vcp->is_init_done) {
+		dev_dbg(&fw->pdev->dev, "vcp has already been initialized done.\n");
+		return 0;
+	}
+
+	if (mtk_vcodec_vcp_get_vcp_device(fw) < 0) {
+		dev_err(&fw->pdev->dev, "vcp device is null.\n");
+		return -EINVAL;
+	}
+
+	vcp_device = fw->vcp->vcp_device;
+
+	feature_id = VDEC_FEATURE_ID;
+	mem_id = VDEC_MEM_ID;
+	mailbox_id = IPI_IN_VDEC_1;
+	ipi_id = VCP_IPI_LAT_DECODER;
+
+	ret = mtk_vcp_mbox_ipc_register(vcp_get_ipidev(vcp_device), mailbox_id,
+					mtk_vcodec_vcp_msg_ack_isr, fw, &fw->vcp->share_data);
+	if (ret) {
+		dev_dbg(&fw->pdev->dev, "ipi register fail %d %d %d %d\n", ret, feature_id,
+			mem_id, mailbox_id);
+		return -EINVAL;
+	}
+
+	fw->vcp->vcp_notify.notifier_call = mtk_vcodec_vcp_notifier;
+	fw->vcp->vcp_notify.priority = 1;
+	vcp_device->ops->vcp_register_notify(feature_id, &fw->vcp->vcp_notify);
+
+	fw->vcp->is_init_done = true;
+
+	mutex_init(&fw->vcp->ipi_desc[ipi_id].lock);
+	mutex_init(&fw->vcp->ipi_mutex);
+
+	kthread_run(mtk_vcodec_vcp_msg_process_thread, fw, "vcp_vdec_msq_thread");
+
+	fw->vcp->vsi_addr = vcp_device->ops->vcp_get_mem_virt(mem_id);
+	fw->vcp->vsi_core_addr = fw->vcp->vsi_addr + VCODEC_VSI_LEN;
+	fw->vcp->vsi_size = vcp_device->ops->vcp_get_mem_size(mem_id);
+	fw->vcp->iova_addr = vcp_device->ops->vcp_get_mem_iova(mem_id);
+
+	init_waitqueue_head(&fw->vcp->msg_wq[VCP_IPI_LAT_DECODER]);
+	init_waitqueue_head(&fw->vcp->msg_wq[VCP_IPI_CORE_DECODER]);
+
+	dev_dbg(&fw->pdev->dev, "vdec vcp init done => va: %p size:0x%x iova:%p.\n",
+		fw->vcp->vsi_addr, fw->vcp->vsi_size, &fw->vcp->iova_addr);
+
+	return 0;
+}
+
+static unsigned int mtk_vcodec_vcp_get_vdec_capa(struct mtk_vcodec_fw *fw)
+{
+	return MTK_VDEC_FORMAT_MM21 | MTK_VDEC_FORMAT_H264_SLICE | MTK_VDEC_FORMAT_VP9_FRAME |
+	       MTK_VDEC_FORMAT_AV1_FRAME | MTK_VDEC_FORMAT_HEVC_FRAME |
+	       MTK_VDEC_IS_SUPPORT_10BIT | MTK_VDEC_IS_SUPPORT_EXT;
+}
+
+static void *mtk_vcodec_vcp_dm_addr(struct mtk_vcodec_fw *fw, u32 dtcm_dmem_addr)
+{
+	return NULL;
+}
+
+static int mtk_vcodec_vcp_set_ipi_register(struct mtk_vcodec_fw *fw, int id,
+					   mtk_vcodec_ipi_handler handler,
+					   const char *name, void *priv)
+{
+	return mtk_vcodec_vcp_ipi_register(fw->vcp, id, handler, priv);
+}
+
+static int mtk_vcodec_vcp_ipi_send(struct mtk_vcodec_fw *fw, int id, void *buf,
+				   unsigned int len, unsigned int wait)
+{
+	struct mtk_vcp_device *vcp_device = fw->vcp->vcp_device;
+	struct device *dev = &fw->pdev->dev;
+	int ret;
+
+	if (!fw->vcp->vcp_device) {
+		dev_err(dev, "vcp device is null\n");
+		return -ENODEV;
+	}
+
+	ret = vcp_device->ops->vcp_register_feature(vcp_device, VDEC_FEATURE_ID);
+	if (ret < 0)
+		goto error;
+
+	ret = mtk_vcodec_vcp_msg_ipi_send(fw, id, buf, len, wait);
+	if (ret < 0)
+		goto error;
+
+	ret = vcp_device->ops->vcp_deregister_feature(vcp_device, VDEC_FEATURE_ID);
+	if (ret < 0)
+		goto error;
+
+	return ret;
+
+error:
+	dev_err(dev, "vcp ipi send fail ret:%d\n", ret);
+
+	return ret;
+}
+
+static void mtk_vcodec_vcp_release(struct mtk_vcodec_fw *fw)
+{
+}
+
+static const struct mtk_vcodec_fw_ops mtk_vcodec_vcp_msg = {
+	.load_firmware = mtk_vcodec_vcp_load_firmware,
+	.get_vdec_capa = mtk_vcodec_vcp_get_vdec_capa,
+	.map_dm_addr = mtk_vcodec_vcp_dm_addr,
+	.ipi_register = mtk_vcodec_vcp_set_ipi_register,
+	.ipi_send = mtk_vcodec_vcp_ipi_send,
+	.release = mtk_vcodec_vcp_release,
+};
+
+struct mtk_vcodec_fw *mtk_vcodec_fw_vcp_init(void *priv, enum mtk_vcodec_fw_use fw_use)
+{
+	struct mtk_vcp_msg_node *msg_node;
+	struct platform_device *plat_dev;
+	struct mtk_vcodec_fw *fw;
+	int i;
+
+	if (fw_use == DECODER) {
+		struct mtk_vcodec_dec_dev *dec_dev = priv;
+
+		plat_dev = dec_dev->plat_dev;
+	} else {
+		pr_err("Invalid fw_use %d (use a reasonable fw id here)\n", fw_use);
+		return ERR_PTR(-EINVAL);
+	}
+
+	fw = devm_kzalloc(&plat_dev->dev, sizeof(*fw), GFP_KERNEL);
+	if (!fw)
+		return ERR_PTR(-ENOMEM);
+
+	fw->type = VCP;
+	fw->pdev = plat_dev;
+	fw->fw_use = fw_use;
+	fw->ops = &mtk_vcodec_vcp_msg;
+	fw->vcp = devm_kzalloc(&plat_dev->dev, sizeof(*fw->vcp), GFP_KERNEL);
+	if (!fw->vcp)
+		return ERR_PTR(-ENOMEM);
+
+	INIT_LIST_HEAD(&fw->vcp->msg_queue.msg_list);
+	INIT_LIST_HEAD(&fw->vcp->msg_queue.node_list);
+	spin_lock_init(&fw->vcp->msg_queue.lock);
+	init_waitqueue_head(&fw->vcp->msg_queue.wq);
+	atomic_set(&fw->vcp->msg_queue.cnt, 0);
+	fw->vcp->pdev = plat_dev;
+
+	for (i = 0; i < VCP_MAX_MQ_NODE_CNT; i++) {
+		msg_node = devm_kzalloc(&plat_dev->dev, sizeof(*msg_node), GFP_KERNEL);
+		if (!msg_node)
+			return ERR_PTR(-ENOMEM);
+
+		list_add(&msg_node->list, &fw->vcp->msg_queue.node_list);
+	}
+
+	return fw;
+}
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.h b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.h
new file mode 100644
index 000000000000..40f5481d1889
--- /dev/null
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Yunfei Dong <yunfei.dong at mediatek.com>
+ */
+
+#ifndef _MTK_VCODEC_FW_VCP_H_
+#define _MTK_VCODEC_FW_VCP_H_
+
+typedef void (*vcp_ipi_handler_t) (void *data, unsigned int len, void *priv);
+
+#define VCP_MAX_MQ_NODE_CNT  6
+#define VCP_SHARE_BUF_SIZE 64
+
+#define VCODEC_VSI_LEN (0x2000)
+
+/* enum mtk_vcp_ipi_index - index used to separate different hardware */
+enum mtk_vcp_ipi_index {
+	VCP_IPI_LAT_DECODER,
+	VCP_IPI_CORE_DECODER,
+	VCP_IPI_MAX,
+};
+
+/**
+ * struct mtk_vcp_msg_queue - process the vcp message between kernel with vcp
+ *
+ * @msg_list:  store share buffer list which from vcp to kernel
+ * @wq:        waitqueue that can be used to wait for vcp message
+ * @lock:      protect msg list
+ * @cnt:       the count of share obj in msg list
+ * @node_list: share obj list
+ */
+struct mtk_vcp_msg_queue {
+	struct list_head msg_list;
+	wait_queue_head_t wq;
+	spinlock_t lock;
+	atomic_t cnt;
+	struct list_head node_list;
+};
+
+/**
+ * struct mtk_vcp_ipi_desc - store the ack handler
+ *
+ * @lock:    protect ack handler data
+ * @handler: calling this handler when kernel receive ack
+ * @priv:    private data when calling handler to process
+ */
+struct mtk_vcp_ipi_desc {
+	struct mutex lock;
+	vcp_ipi_handler_t handler;
+	void *priv;
+};
+
+/**
+ * struct mtk_vcp_share_obj - share buffer used to send data to vcp
+ *
+ * @id:        message index
+ * @len:       message size
+ * @share_buf: message data
+ */
+struct mtk_vcp_share_obj {
+	unsigned int id;
+	unsigned int len;
+	unsigned char share_buf[VCP_SHARE_BUF_SIZE];
+};
+
+/* enum mtk_vcp_ipi_msg_status - the status when send message to vcp */
+enum mtk_vcp_ipi_msg_status {
+	VCODEC_IPI_MSG_STATUS_OK         = 0,
+	VCODEC_IPI_MSG_STATUS_FAIL       = -1,
+	VCODEC_IPI_MSG_STATUS_MAX_INST   = -2,
+	VCODEC_IPI_MSG_STATUS_ILSEQ      = -3,
+	VCODEC_IPI_MSG_STATUS_INVALID_ID = -4,
+	VCODEC_IPI_MSG_STATUS_DMA_FAIL   = -5,
+};
+
+/**
+ * struct mtk_vcp_msg_node - share buffer used to send data to vcp
+ *
+ * @ipi_data: share obj data
+ * @list:     list to store msg node
+ */
+struct mtk_vcp_msg_node {
+	struct mtk_vcp_share_obj ipi_data;
+	struct list_head list;
+};
+
+/**
+ * struct mtk_vcp - vcp firmware private data
+ *
+ * @is_init_done:  vcp is ready to use
+ *
+ * @ipi_mutex:     used to protect ipi data
+ * @msg_signaled:  whether receive ack from vcp
+ * @msg_wq:        wake message queue
+ *
+ * @ipi_desc:      store ack handler
+ * @ipi_id_ack:    the ack handler status
+ *
+ * @msg_queue:     process vcp message
+ * @share_data:    temp share obj data
+ *
+ * @vcp_notify:    register notifier to vcp
+ *
+ * @vsi_addr:      vsi virtual data address
+ * @vsi_core_addr: vsi core virtual data address
+ * @iova_addr:     vsi iova address
+ * @vsi_size:      vsi size
+ *
+ * @pdev:          platform device
+ * @vcp_device:    vcp private data
+ */
+struct mtk_vcp {
+	bool is_init_done;
+
+	struct mutex ipi_mutex;
+	bool msg_signaled[VCP_IPI_MAX];
+	wait_queue_head_t msg_wq[VCP_IPI_MAX];
+
+	struct mtk_vcp_ipi_desc ipi_desc[VCP_IPI_MAX];
+	bool ipi_id_ack[VCP_IPI_MAX];
+
+	struct mtk_vcp_msg_queue msg_queue;
+	struct mtk_vcp_share_obj share_data;
+
+	struct notifier_block vcp_notify;
+
+	void *vsi_addr;
+	void *vsi_core_addr;
+	dma_addr_t iova_addr;
+	int vsi_size;
+
+	struct platform_device *pdev;
+	struct mtk_vcp_device *vcp_device;
+};
+
+#endif
diff --git a/include/linux/remoteproc/mtk_vcp_public.h b/include/linux/remoteproc/mtk_vcp_public.h
index 07b0b30ea964..0b7d1c3c28ca 100644
--- a/include/linux/remoteproc/mtk_vcp_public.h
+++ b/include/linux/remoteproc/mtk_vcp_public.h
@@ -10,7 +10,7 @@
 #include <linux/firmware/mediatek/mtk-vcp-ipc.h>
 #include <linux/remoteproc.h>
 
-#define VCP_SYNC_TIMEOUT_MS             (999)
+#define VCP_SYNC_TIMEOUT_MS             (50)
 
 /* vcp notify event */
 enum VCP_NOTIFY_EVENT {
-- 
2.46.0



From yunfei.dong at mediatek.com  Sat May 10 00:53:30 2025
From: yunfei.dong at mediatek.com (Yunfei Dong)
Date: Sat, 10 May 2025 15:53:30 +0800
Subject: [PATCH 00/14] media: mediatek: vcodec: support video decoder in mt8196
Message-ID: <20250510075357.11761-1-yunfei.dong@mediatek.com>

Using vcp micro processor to support video decoder in mt8196 platform,
need to add new firmware interface to communicate with vcp in kernel
side. Then add mt8196 compatible, codec levels/profiles and private data.
Re-write av1 driver to support extend vsi struct, then change irq table
and cdf table size.

This patch set depends on "Add VCP support for mt8196"[1]

[1] https://patchwork.kernel.org/project/linux-remoteproc/patch/20250402092134.12293-2-xiangzhi.tang at mediatek.com/
---
Yunfei Dong (14):
  dt-bindings: media: mediatek: vcodec: add decoder dt-bindings for
    mt8196
  media: mediatek: vcodec: add decoder compatible to support mt8196
  media: mediatek: vcodec: add driver to support vcp
  media: mediatek: vcodec: add driver to support vcp encoder
  media: mediatek: vcodec: get different firmware ipi id
  media: mediatek: vcodec: get share memory address
  media: mediatek: vcodec: define MT8196 vcodec levels.
  media: mediatek: vcodec: support vcp architecture
  media: mediatek: vcodec: support 36bit iova address
  media: mediatek: vcodec: clean xpc status
  media: mediatek: vcodec: add debug information
  media: mediatek: vcodec: send share memory address to vcp
  media: mediatek: decoder: fill av1 buffer size with picinfo
  media: mediatek: decoder: support av1 extend vsi

 .../media/mediatek,vcodec-subdev-decoder.yaml |   1 +
 .../media/platform/mediatek/vcodec/Kconfig    |   4 +
 .../platform/mediatek/vcodec/common/Makefile  |   4 +
 .../mediatek/vcodec/common/mtk_vcodec_dbgfs.c |  21 +-
 .../mediatek/vcodec/common/mtk_vcodec_fw.c    |  16 +
 .../mediatek/vcodec/common/mtk_vcodec_fw.h    |   2 +
 .../vcodec/common/mtk_vcodec_fw_priv.h        |  12 +
 .../vcodec/common/mtk_vcodec_fw_vcp.c         | 493 ++++++++++++++++++
 .../vcodec/common/mtk_vcodec_fw_vcp.h         | 151 ++++++
 .../vcodec/decoder/mtk_vcodec_dec_drv.c       |  16 +
 .../vcodec/decoder/mtk_vcodec_dec_drv.h       |   1 +
 .../vcodec/decoder/mtk_vcodec_dec_hw.c        |  28 +
 .../vcodec/decoder/mtk_vcodec_dec_hw.h        |  13 +-
 .../vcodec/decoder/mtk_vcodec_dec_stateless.c |   6 +
 .../vcodec/decoder/vdec/vdec_av1_req_lat_if.c |  85 ++-
 .../decoder/vdec/vdec_h264_req_multi_if.c     |  10 +-
 .../decoder/vdec/vdec_hevc_req_multi_if.c     |  11 +-
 .../vcodec/decoder/vdec/vdec_vp8_req_if.c     |   4 +-
 .../vcodec/decoder/vdec/vdec_vp9_req_lat_if.c |  20 +-
 .../mediatek/vcodec/decoder/vdec_ipi_msg.h    |   2 +
 .../mediatek/vcodec/decoder/vdec_vpu_if.c     |   9 +-
 .../mediatek/vcodec/encoder/mtk_vcodec_enc.c  |   1 -
 .../mediatek/vcodec/encoder/mtk_vcodec_enc.h  |   2 +
 include/linux/remoteproc/mtk_vcp_public.h     |   2 +-
 24 files changed, 871 insertions(+), 43 deletions(-)
 create mode 100644 drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
 create mode 100644 drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.h

-- 
2.46.0



From yunfei.dong at mediatek.com  Sat May 10 00:53:35 2025
From: yunfei.dong at mediatek.com (Yunfei Dong)
Date: Sat, 10 May 2025 15:53:35 +0800
Subject: [PATCH 05/14] media: mediatek: vcodec: get different firmware ipi id
In-Reply-To: <20250510075357.11761-1-yunfei.dong@mediatek.com>
References: <20250510075357.11761-1-yunfei.dong@mediatek.com>
Message-ID: <20250510075357.11761-6-yunfei.dong@mediatek.com>

Getting ipi(inter-processor interrupt) id according to firmware
type and hardware index for different architecture.

Signed-off-by: Yunfei Dong <yunfei.dong at mediatek.com>
---
 .../platform/mediatek/vcodec/common/mtk_vcodec_fw.c | 13 +++++++++++++
 .../platform/mediatek/vcodec/common/mtk_vcodec_fw.h |  1 +
 .../vcodec/decoder/vdec/vdec_av1_req_lat_if.c       |  4 ++--
 .../vcodec/decoder/vdec/vdec_h264_req_multi_if.c    |  4 ++--
 .../vcodec/decoder/vdec/vdec_hevc_req_multi_if.c    |  4 ++--
 .../mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c  |  4 ++--
 .../vcodec/decoder/vdec/vdec_vp9_req_lat_if.c       |  4 ++--
 7 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
index fc547afa4ebf..4ed7639dfa30 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
@@ -5,6 +5,19 @@
 #include "mtk_vcodec_fw_priv.h"
 #include "mtk_vcodec_fw_vcp.h"
 
+int mtk_vcodec_fw_get_ipi(enum mtk_vcodec_fw_type type, int hw_id)
+{
+	switch (type) {
+	case SCP:
+		return hw_id == MTK_VDEC_LAT0 ? SCP_IPI_VDEC_LAT : SCP_IPI_VDEC_CORE;
+	case VCP:
+		return hw_id == MTK_VDEC_LAT0 ? VCP_IPI_LAT_DECODER : VCP_IPI_CORE_DECODER;
+	default:
+		return -EINVAL;
+	}
+}
+EXPORT_SYMBOL_GPL(mtk_vcodec_fw_get_ipi);
+
 struct mtk_vcodec_fw *mtk_vcodec_fw_select(void *priv, enum mtk_vcodec_fw_type type,
 					   enum mtk_vcodec_fw_use fw_use)
 {
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h
index c1642fb09b42..142e2e87905c 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h
@@ -41,5 +41,6 @@ int mtk_vcodec_fw_ipi_register(struct mtk_vcodec_fw *fw, int id,
 int mtk_vcodec_fw_ipi_send(struct mtk_vcodec_fw *fw, int id,
 			   void *buf, unsigned int len, unsigned int wait);
 int mtk_vcodec_fw_get_type(struct mtk_vcodec_fw *fw);
+int mtk_vcodec_fw_get_ipi(enum mtk_vcodec_fw_type type, int hw_id);
 
 #endif /* _MTK_VCODEC_FW_H_ */
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c
index bf21f2467a0f..618064001883 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c
@@ -1886,8 +1886,8 @@ static int vdec_av1_slice_init(struct mtk_vcodec_dec_ctx *ctx)
 		return -ENOMEM;
 
 	instance->ctx = ctx;
-	instance->vpu.id = SCP_IPI_VDEC_LAT;
-	instance->vpu.core_id = SCP_IPI_VDEC_CORE;
+	instance->vpu.id = mtk_vcodec_fw_get_ipi(ctx->dev->fw_handler->type, MTK_VDEC_LAT0);
+	instance->vpu.core_id = mtk_vcodec_fw_get_ipi(ctx->dev->fw_handler->type, MTK_VDEC_CORE);
 	instance->vpu.ctx = ctx;
 	instance->vpu.codec_type = ctx->current_codec;
 
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
index 5b25e1679b51..50f81f1cb616 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
@@ -1212,8 +1212,8 @@ static int vdec_h264_slice_init(struct mtk_vcodec_dec_ctx *ctx)
 
 	inst->ctx = ctx;
 
-	inst->vpu.id = SCP_IPI_VDEC_LAT;
-	inst->vpu.core_id = SCP_IPI_VDEC_CORE;
+	inst->vpu.id = mtk_vcodec_fw_get_ipi(ctx->dev->fw_handler->type, MTK_VDEC_LAT0);
+	inst->vpu.core_id = mtk_vcodec_fw_get_ipi(ctx->dev->fw_handler->type, MTK_VDEC_CORE);
 	inst->vpu.ctx = ctx;
 	inst->vpu.codec_type = ctx->current_codec;
 	inst->vpu.capture_type = ctx->capture_fourcc;
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
index 2725db882e5b..80fbd0309b9e 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
@@ -863,8 +863,8 @@ static int vdec_hevc_slice_init(struct mtk_vcodec_dec_ctx *ctx)
 
 	inst->ctx = ctx;
 
-	inst->vpu.id = SCP_IPI_VDEC_LAT;
-	inst->vpu.core_id = SCP_IPI_VDEC_CORE;
+	inst->vpu.id = mtk_vcodec_fw_get_ipi(ctx->dev->fw_handler->type, MTK_VDEC_LAT0);
+	inst->vpu.core_id = mtk_vcodec_fw_get_ipi(ctx->dev->fw_handler->type, MTK_VDEC_CORE);
 	inst->vpu.ctx = ctx;
 	inst->vpu.codec_type = ctx->current_codec;
 	inst->vpu.capture_type = ctx->capture_fourcc;
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
index 232ef3bd246a..764f4d4054c0 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
@@ -281,8 +281,8 @@ static int vdec_vp8_slice_init(struct mtk_vcodec_dec_ctx *ctx)
 
 	inst->ctx = ctx;
 
-	inst->vpu.id = SCP_IPI_VDEC_LAT;
-	inst->vpu.core_id = SCP_IPI_VDEC_CORE;
+	inst->vpu.id = mtk_vcodec_fw_get_ipi(ctx->dev->fw_handler->type, MTK_VDEC_LAT0);
+	inst->vpu.core_id = mtk_vcodec_fw_get_ipi(ctx->dev->fw_handler->type, MTK_VDEC_CORE);
 	inst->vpu.ctx = ctx;
 	inst->vpu.codec_type = ctx->current_codec;
 	inst->vpu.capture_type = ctx->capture_fourcc;
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
index 47c302745c1d..0279f66efdf9 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
@@ -1855,8 +1855,8 @@ static int vdec_vp9_slice_init(struct mtk_vcodec_dec_ctx *ctx)
 		return -ENOMEM;
 
 	instance->ctx = ctx;
-	instance->vpu.id = SCP_IPI_VDEC_LAT;
-	instance->vpu.core_id = SCP_IPI_VDEC_CORE;
+	instance->vpu.id = mtk_vcodec_fw_get_ipi(ctx->dev->fw_handler->type, MTK_VDEC_LAT0);
+	instance->vpu.core_id = mtk_vcodec_fw_get_ipi(ctx->dev->fw_handler->type, MTK_VDEC_CORE);
 	instance->vpu.ctx = ctx;
 	instance->vpu.codec_type = ctx->current_codec;
 
-- 
2.46.0



From yunfei.dong at mediatek.com  Sat May 10 00:53:37 2025
From: yunfei.dong at mediatek.com (Yunfei Dong)
Date: Sat, 10 May 2025 15:53:37 +0800
Subject: [PATCH 07/14] media: mediatek: vcodec: define MT8196 vcodec levels.
In-Reply-To: <20250510075357.11761-1-yunfei.dong@mediatek.com>
References: <20250510075357.11761-1-yunfei.dong@mediatek.com>
Message-ID: <20250510075357.11761-8-yunfei.dong@mediatek.com>

The supported level and profile are not the same for different
codecs and architecture. Select the correct one.

Signed-off-by: Yunfei Dong <yunfei.dong at mediatek.com>
---
 .../mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c      | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
index d873159b9b30..c1cef78471a9 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
@@ -555,6 +555,7 @@ static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg,
 		cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_5_2;
 		break;
 	case MTK_VDEC_MT8195:
+	case MTK_VDEC_MT8196:
 		cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_6_0;
 		break;
 	case MTK_VDEC_MT8183:
@@ -573,6 +574,7 @@ static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg,
 	switch (ctx->dev->chip_name) {
 	case MTK_VDEC_MT8188:
 	case MTK_VDEC_MT8195:
+	case MTK_VDEC_MT8196:
 		cfg->max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10;
 		break;
 	default:
@@ -589,6 +591,7 @@ static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg,
 		cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1;
 		break;
 	case MTK_VDEC_MT8195:
+	case MTK_VDEC_MT8196:
 		cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2;
 		break;
 	default:
@@ -603,6 +606,7 @@ static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg,
 	switch (ctx->dev->chip_name) {
 	case MTK_VDEC_MT8188:
 	case MTK_VDEC_MT8195:
+	case MTK_VDEC_MT8196:
 		cfg->max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10;
 		break;
 	default:
@@ -620,6 +624,7 @@ static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg,
 		cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1;
 		break;
 	case MTK_VDEC_MT8195:
+	case MTK_VDEC_MT8196:
 		cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_2;
 		break;
 	case MTK_VDEC_MT8186:
@@ -637,6 +642,7 @@ static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg,
 	switch (ctx->dev->chip_name) {
 	case MTK_VDEC_MT8188:
 	case MTK_VDEC_MT8195:
+	case MTK_VDEC_MT8196:
 		cfg->max = V4L2_MPEG_VIDEO_VP9_PROFILE_2;
 		break;
 	default:
-- 
2.46.0



From yunfei.dong at mediatek.com  Sat May 10 00:53:36 2025
From: yunfei.dong at mediatek.com (Yunfei Dong)
Date: Sat, 10 May 2025 15:53:36 +0800
Subject: [PATCH 06/14] media: mediatek: vcodec: get share memory address
In-Reply-To: <20250510075357.11761-1-yunfei.dong@mediatek.com>
References: <20250510075357.11761-1-yunfei.dong@mediatek.com>
Message-ID: <20250510075357.11761-7-yunfei.dong@mediatek.com>

There is only one share memory for vcp architecture, need to
divide it into many different functions.

Signed-off-by: Yunfei Dong <yunfei.dong at mediatek.com>
---
 .../vcodec/common/mtk_vcodec_fw_vcp.c         | 20 +++++++++++++++++-
 .../vcodec/common/mtk_vcodec_fw_vcp.h         | 13 ++++++++++++
 .../vcodec/decoder/vdec/vdec_av1_req_lat_if.c | 21 ++++++++++++++-----
 .../decoder/vdec/vdec_h264_req_multi_if.c     |  6 +++++-
 .../decoder/vdec/vdec_hevc_req_multi_if.c     |  7 +++++--
 .../vcodec/decoder/vdec/vdec_vp9_req_lat_if.c | 16 ++++++++++----
 .../mediatek/vcodec/decoder/vdec_vpu_if.c     |  7 +++++--
 7 files changed, 75 insertions(+), 15 deletions(-)

diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
index c9e5cde40aef..f6b93e1bcbf3 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
@@ -366,8 +366,26 @@ static unsigned int mtk_vcodec_vcp_get_venc_capa(struct mtk_vcodec_fw *fw)
 	return MTK_VENC_4K_CAPABILITY_ENABLE;
 }
 
-static void *mtk_vcodec_vcp_dm_addr(struct mtk_vcodec_fw *fw, u32 dtcm_dmem_addr)
+static void *mtk_vcodec_vcp_dm_addr(struct mtk_vcodec_fw *fw, u32 mem_type)
 {
+	unsigned char *vsi_core = fw->vcp->vsi_core_addr;
+
+	switch (mem_type) {
+	case ENCODER_MEM:
+	case VCODEC_LAT_MEM:
+		return fw->vcp->vsi_addr;
+	case VCODEC_CORE_MEM:
+		return vsi_core;
+	case VP9_FRAME_MEM:
+		return vsi_core + VCODEC_VSI_LEN;
+	case AV1_CDF_MEM:
+		return vsi_core + VCODEC_VSI_LEN + VP9_FRAME_SIZE;
+	case AV1_IQ_MEM:
+		return vsi_core + VCODEC_VSI_LEN + VP9_FRAME_SIZE + AV1_CDF_SIZE;
+	default:
+		break;
+	}
+
 	return NULL;
 }
 
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.h b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.h
index 53080ed12c69..54df468f301b 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.h
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.h
@@ -13,6 +13,19 @@ typedef void (*vcp_ipi_handler_t) (void *data, unsigned int len, void *priv);
 #define VCP_SHARE_BUF_SIZE 64
 
 #define VCODEC_VSI_LEN (0x2000)
+#define VP9_FRAME_SIZE (0x1000)
+#define AV1_CDF_SIZE (0xFE80)
+#define AV1_IQ_TABLE_SIZE (0x12200)
+
+/* enum mtk_vcp_mem_type - memory type for different hardware */
+enum mtk_vcp_mem_type {
+	ENCODER_MEM,
+	VCODEC_LAT_MEM,
+	VCODEC_CORE_MEM,
+	VP9_FRAME_MEM,
+	AV1_CDF_MEM,
+	AV1_IQ_MEM,
+};
 
 /* enum mtk_vcp_ipi_index - index used to separate different hardware */
 enum mtk_vcp_ipi_index {
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c
index 618064001883..2b2173062cb0 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c
@@ -774,8 +774,11 @@ static int vdec_av1_slice_init_cdf_table(struct vdec_av1_slice_instance *instanc
 
 	ctx = instance->ctx;
 	vsi = instance->vpu.vsi;
-	remote_cdf_table = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler,
-						     (u32)vsi->cdf_table_addr);
+	if (mtk_vcodec_fw_get_type(ctx->dev->fw_handler) == VCP)
+		remote_cdf_table = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, AV1_CDF_MEM);
+	else
+		remote_cdf_table = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler,
+							     (u32)vsi->cdf_table_addr);
 	if (IS_ERR(remote_cdf_table)) {
 		mtk_vdec_err(ctx, "failed to map cdf table\n");
 		return PTR_ERR(remote_cdf_table);
@@ -805,8 +808,11 @@ static int vdec_av1_slice_init_iq_table(struct vdec_av1_slice_instance *instance
 
 	ctx = instance->ctx;
 	vsi = instance->vpu.vsi;
-	remote_iq_table = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler,
-						    (u32)vsi->iq_table_addr);
+	if (mtk_vcodec_fw_get_type(ctx->dev->fw_handler) == VCP)
+		remote_iq_table = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, AV1_IQ_MEM);
+	else
+		remote_iq_table = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler,
+							    (u32)vsi->iq_table_addr);
 	if (IS_ERR(remote_iq_table)) {
 		mtk_vdec_err(ctx, "failed to map iq table\n");
 		return PTR_ERR(remote_iq_table);
@@ -1905,7 +1911,12 @@ static int vdec_av1_slice_init(struct mtk_vcodec_dec_ctx *ctx)
 		goto error_vsi;
 	}
 	instance->init_vsi = vsi;
-	instance->core_vsi = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, (u32)vsi->core_vsi);
+	if (mtk_vcodec_fw_get_type(ctx->dev->fw_handler) == VCP)
+		instance->core_vsi =
+			mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, VCODEC_CORE_MEM);
+	else
+		instance->core_vsi =
+			mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, (u32)vsi->core_vsi);
 
 	if (!instance->core_vsi) {
 		mtk_vdec_err(ctx, "failed to get AV1 core vsi\n");
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
index 50f81f1cb616..6b354d30910c 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
@@ -1230,7 +1230,11 @@ static int vdec_h264_slice_init(struct mtk_vcodec_dec_ctx *ctx)
 		vsi_size = round_up(vsi_size, VCODEC_DEC_ALIGNED_64);
 		inst->vsi_ext = inst->vpu.vsi;
 		temp = (unsigned char *)inst->vsi_ext;
-		inst->vsi_core_ext = (struct vdec_h264_slice_vsi_ext *)(temp + vsi_size);
+		if (mtk_vcodec_fw_get_type(ctx->dev->fw_handler) == VCP)
+			inst->vsi_core_ext =
+				mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, VCODEC_CORE_MEM);
+		else
+			inst->vsi_core_ext = (struct vdec_h264_slice_vsi_ext *)(temp + vsi_size);
 
 		if (inst->ctx->dev->vdec_pdata->hw_arch == MTK_VDEC_PURE_SINGLE_CORE)
 			inst->decode = vdec_h264_slice_single_decode_ext;
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
index 80fbd0309b9e..ac0deea0df4c 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
@@ -877,8 +877,11 @@ static int vdec_hevc_slice_init(struct mtk_vcodec_dec_ctx *ctx)
 
 	vsi_size = round_up(sizeof(struct vdec_hevc_slice_vsi), VCODEC_DEC_ALIGNED_64);
 	inst->vsi = inst->vpu.vsi;
-	inst->vsi_core =
-		(struct vdec_hevc_slice_vsi *)(((char *)inst->vpu.vsi) + vsi_size);
+	if (mtk_vcodec_fw_get_type(ctx->dev->fw_handler) == VCP)
+		inst->vsi_core = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, VCODEC_CORE_MEM);
+	else
+		inst->vsi_core =
+			(struct vdec_hevc_slice_vsi *)(((char *)inst->vpu.vsi) + vsi_size);
 
 	inst->resolution_changed = true;
 	inst->realloc_mv_buf = true;
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
index 0279f66efdf9..fa0f406f7726 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
@@ -513,8 +513,12 @@ static int vdec_vp9_slice_init_default_frame_ctx(struct vdec_vp9_slice_instance
 	if (!ctx || !vsi)
 		return -EINVAL;
 
-	remote_frame_ctx = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler,
-						     (u32)vsi->default_frame_ctx);
+	if (mtk_vcodec_fw_get_type(ctx->dev->fw_handler) == VCP)
+		remote_frame_ctx =
+			mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, VP9_FRAME_MEM);
+	else
+		remote_frame_ctx = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler,
+							     (u32)vsi->default_frame_ctx);
 	if (!remote_frame_ctx) {
 		mtk_vdec_err(ctx, "failed to map default frame ctx\n");
 		return -EINVAL;
@@ -1875,8 +1879,12 @@ static int vdec_vp9_slice_init(struct mtk_vcodec_dec_ctx *ctx)
 		goto error_vsi;
 	}
 	instance->init_vsi = vsi;
-	instance->core_vsi = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler,
-						       (u32)vsi->core_vsi);
+	if (mtk_vcodec_fw_get_type(ctx->dev->fw_handler) == VCP)
+		instance->core_vsi =
+			mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, VCODEC_CORE_MEM);
+	else
+		instance->core_vsi = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler,
+							       (u32)vsi->core_vsi);
 	if (!instance->core_vsi) {
 		mtk_vdec_err(ctx, "failed to get VP9 core vsi\n");
 		ret = -EINVAL;
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c
index 145958206e38..ac10e0dfefb2 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c
@@ -18,8 +18,11 @@ static void handle_init_ack_msg(const struct vdec_vpu_ipi_init_ack *msg)
 
 	/* mapping VPU address to kernel virtual address */
 	/* the content in vsi is initialized to 0 in VPU */
-	vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler,
-					     msg->vpu_inst_addr);
+	if (mtk_vcodec_fw_get_type(vpu->ctx->dev->fw_handler) == VCP)
+		vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, VCODEC_LAT_MEM);
+	else
+		vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler,
+						     msg->vpu_inst_addr);
 	vpu->inst_addr = msg->vpu_inst_addr;
 
 	mtk_vdec_debug(vpu->ctx, "- vpu_inst_addr = 0x%x", vpu->inst_addr);
-- 
2.46.0



From yunfei.dong at mediatek.com  Sat May 10 00:53:40 2025
From: yunfei.dong at mediatek.com (Yunfei Dong)
Date: Sat, 10 May 2025 15:53:40 +0800
Subject: [PATCH 10/14] media: mediatek: vcodec: clean xpc status
In-Reply-To: <20250510075357.11761-1-yunfei.dong@mediatek.com>
References: <20250510075357.11761-1-yunfei.dong@mediatek.com>
Message-ID: <20250510075357.11761-11-yunfei.dong@mediatek.com>

The driver need to clean xpc status when receive decoder hardware
interrupt for mt8196 platform.

Signed-off-by: Yunfei Dong <yunfei.dong at mediatek.com>
---
 .../vcodec/decoder/mtk_vcodec_dec_hw.c        | 28 +++++++++++++++++++
 .../vcodec/decoder/mtk_vcodec_dec_hw.h        | 13 +++++++--
 2 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c
index 881d5de41e05..e4e527fe54dc 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c
@@ -61,6 +61,31 @@ static int mtk_vdec_hw_prob_done(struct mtk_vcodec_dec_dev *vdec_dev)
 	return 0;
 }
 
+static void mtk_vdec_hw_write_reg_mask(void __iomem *reg_base, u32 reg_offset, u32 val, u32 mask)
+{
+	void __iomem *reg_addr = reg_base + reg_offset;
+	u32 reg_val;
+
+	reg_val =  readl(reg_addr);
+	reg_val &= ~mask;
+	reg_val |= (val & mask);
+	writel(reg_val, reg_addr);
+}
+
+static void mtk_vdec_hw_clean_xpc(struct mtk_vdec_hw_dev *dev)
+{
+	u32 val, mask, addr = VDEC_XPC_CLEAN_ADDR;
+
+	if (dev->main_dev->chip_name != MTK_VDEC_MT8196)
+		return;
+
+	val = dev->hw_idx == MTK_VDEC_LAT0 ? VDEC_XPC_LAT_VAL : VDEC_XPC_CORE_VAL;
+	mask = dev->hw_idx == MTK_VDEC_LAT0 ? VDEC_XPC_LAT_MASK : VDEC_XPC_CORE_MASK;
+
+	mtk_vdec_hw_write_reg_mask(dev->reg_base[VDEC_HW_XPC], addr, val, mask);
+	mtk_vdec_hw_write_reg_mask(dev->reg_base[VDEC_HW_XPC], addr, 0, mask);
+}
+
 static irqreturn_t mtk_vdec_hw_irq_handler(int irq, void *priv)
 {
 	struct mtk_vdec_hw_dev *dev = priv;
@@ -88,6 +113,8 @@ static irqreturn_t mtk_vdec_hw_irq_handler(int irq, void *priv)
 	writel(dec_done_status | VDEC_IRQ_CFG, vdec_misc_addr);
 	writel(dec_done_status & ~VDEC_IRQ_CLR, vdec_misc_addr);
 
+	mtk_vdec_hw_clean_xpc(dev);
+
 	wake_up_dec_ctx(ctx, MTK_INST_IRQ_RECEIVED, dev->hw_idx);
 
 	mtk_v4l2_vdec_dbg(3, ctx, "wake up ctx %d, dec_done_status=%x",
@@ -166,6 +193,7 @@ static int mtk_vdec_hw_probe(struct platform_device *pdev)
 	subdev_dev->hw_idx = hw_idx;
 	subdev_dev->main_dev = main_dev;
 	subdev_dev->reg_base[VDEC_HW_SYS] = main_dev->reg_base[VDEC_HW_SYS];
+	subdev_dev->reg_base[VDEC_HW_XPC] = main_dev->reg_base[VDEC_HW_MISC];
 	set_bit(subdev_dev->hw_idx, main_dev->subdev_bitmap);
 
 	if (IS_SUPPORT_VDEC_HW_IRQ(hw_idx)) {
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.h
index 83fe8b9428e6..50ce6c1d25a2 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.h
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.h
@@ -18,17 +18,26 @@
 #define VDEC_IRQ_CLR 0x10
 #define VDEC_IRQ_CFG_REG 0xa4
 
+#define VDEC_XPC_CLEAN_ADDR 0xC
+#define VDEC_XPC_LAT_VAL BIT(0)
+#define VDEC_XPC_LAT_MASK BIT(0)
+
+#define VDEC_XPC_CORE_VAL BIT(4)
+#define VDEC_XPC_CORE_MASK BIT(4)
+
 #define IS_SUPPORT_VDEC_HW_IRQ(hw_idx) ((hw_idx) != MTK_VDEC_LAT_SOC)
 
 /**
  * enum mtk_vdec_hw_reg_idx - subdev hardware register base index
- * @VDEC_HW_SYS : vdec soc register index
+ * @VDEC_HW_SYS:  vdec soc register index
  * @VDEC_HW_MISC: vdec misc register index
- * @VDEC_HW_MAX : vdec supported max register index
+ * @VDEC_HW_XPC:  vdec xpc register index
+ * @VDEC_HW_MAX:  vdec supported max register index
  */
 enum mtk_vdec_hw_reg_idx {
 	VDEC_HW_SYS,
 	VDEC_HW_MISC,
+	VDEC_HW_XPC,
 	VDEC_HW_MAX
 };
 
-- 
2.46.0



From yunfei.dong at mediatek.com  Sat May 10 00:53:38 2025
From: yunfei.dong at mediatek.com (Yunfei Dong)
Date: Sat, 10 May 2025 15:53:38 +0800
Subject: [PATCH 08/14] media: mediatek: vcodec: support vcp architecture
In-Reply-To: <20250510075357.11761-1-yunfei.dong@mediatek.com>
References: <20250510075357.11761-1-yunfei.dong@mediatek.com>
Message-ID: <20250510075357.11761-9-yunfei.dong@mediatek.com>

Some platforms expose the video codec through the VCP coprocessor.
Use the VCP architecture when the VCP coprocessor is found.

Signed-off-by: Yunfei Dong <yunfei.dong at mediatek.com>
---
 .../platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c      | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
index fa609343c168..5e312f86e652 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
@@ -380,6 +380,9 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
 	} else if (!of_property_read_u32(pdev->dev.of_node, "mediatek,scp",
 					 &rproc_phandle)) {
 		fw_type = SCP;
+	} else if (!of_property_read_u32(pdev->dev.of_node, "mediatek,vcp",
+					 &rproc_phandle)) {
+		fw_type = VCP;
 	} else {
 		dev_dbg(&pdev->dev, "Could not get vdec IPI device");
 		return -ENODEV;
-- 
2.46.0



From yunfei.dong at mediatek.com  Sat May 10 00:53:39 2025
From: yunfei.dong at mediatek.com (Yunfei Dong)
Date: Sat, 10 May 2025 15:53:39 +0800
Subject: [PATCH 09/14] media: mediatek: vcodec: support 36bit iova address
In-Reply-To: <20250510075357.11761-1-yunfei.dong@mediatek.com>
References: <20250510075357.11761-1-yunfei.dong@mediatek.com>
Message-ID: <20250510075357.11761-10-yunfei.dong@mediatek.com>

Need to set dma mask to support 36bit iova address for decoder
hardware can use 36bit address to decode for mt8196.

Signed-off-by: Yunfei Dong <yunfei.dong at mediatek.com>
---
 .../platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c  | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
index 5e312f86e652..fabf969bc8a9 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
@@ -388,6 +388,13 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 	dma_set_max_seg_size(&pdev->dev, UINT_MAX);
+	if (dev->chip_name == MTK_VDEC_MT8196) {
+		ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
+		if (ret) {
+			dev_err(&pdev->dev, "Failed to enable 36-bit DMA: %d\n", ret);
+			return ret;
+		}
+	}
 
 	dev->fw_handler = mtk_vcodec_fw_select(dev, fw_type, DECODER);
 	if (IS_ERR(dev->fw_handler))
-- 
2.46.0



From yunfei.dong at mediatek.com  Sat May 10 00:53:42 2025
From: yunfei.dong at mediatek.com (Yunfei Dong)
Date: Sat, 10 May 2025 15:53:42 +0800
Subject: [PATCH 12/14] media: mediatek: vcodec: send share memory address to vcp
In-Reply-To: <20250510075357.11761-1-yunfei.dong@mediatek.com>
References: <20250510075357.11761-1-yunfei.dong@mediatek.com>
Message-ID: <20250510075357.11761-13-yunfei.dong@mediatek.com>

Send share memory address to vcp for it is reserved in kernel
side.

Signed-off-by: Yunfei Dong <yunfei.dong at mediatek.com>
---
 drivers/media/platform/mediatek/vcodec/decoder/vdec_ipi_msg.h | 2 ++
 drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c  | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec_ipi_msg.h b/drivers/media/platform/mediatek/vcodec/decoder/vdec_ipi_msg.h
index 47070be2a991..097561a1efdc 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec_ipi_msg.h
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec_ipi_msg.h
@@ -67,11 +67,13 @@ struct vdec_vpu_ipi_ack {
  * @msg_id	: AP_IPIMSG_DEC_INIT
  * @codec_type	: codec fourcc
  * @ap_inst_addr	: AP video decoder instance address
+ * @shared_iova	: reserved share memory address
  */
 struct vdec_ap_ipi_init {
 	uint32_t msg_id;
 	u32 codec_type;
 	uint64_t ap_inst_addr;
+	u64 shared_iova;
 };
 
 /**
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c
index ac10e0dfefb2..428ed9e5f2c3 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c
@@ -232,6 +232,8 @@ int vpu_dec_init(struct vdec_vpu_inst *vpu)
 	msg.msg_id = AP_IPIMSG_DEC_INIT;
 	msg.ap_inst_addr = (unsigned long)vpu;
 	msg.codec_type = vpu->codec_type;
+	if (mtk_vcodec_fw_get_type(vpu->ctx->dev->fw_handler) == VCP)
+		msg.shared_iova = vpu->ctx->dev->fw_handler->vcp->iova_addr;
 
 	mtk_vdec_debug(vpu->ctx, "vdec_inst=%p", vpu);
 
-- 
2.46.0



From yunfei.dong at mediatek.com  Sat May 10 00:53:41 2025
From: yunfei.dong at mediatek.com (Yunfei Dong)
Date: Sat, 10 May 2025 15:53:41 +0800
Subject: [PATCH 11/14] media: mediatek: vcodec: add debug information
In-Reply-To: <20250510075357.11761-1-yunfei.dong@mediatek.com>
References: <20250510075357.11761-1-yunfei.dong@mediatek.com>
Message-ID: <20250510075357.11761-12-yunfei.dong@mediatek.com>

Print hevc/av1 output format and 10bit capture format
information to debug.

Signed-off-by: Yunfei Dong <yunfei.dong at mediatek.com>
---
 .../mediatek/vcodec/common/mtk_vcodec_dbgfs.c | 21 +++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_dbgfs.c b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_dbgfs.c
index 5ad3797836db..79ccbe13735a 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_dbgfs.c
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_dbgfs.c
@@ -29,6 +29,14 @@ static void mtk_vdec_dbgfs_get_format_type(struct mtk_vcodec_dec_ctx *ctx, char
 		curr_len = snprintf(buf + *used, total - *used,
 				    "\toutput format: vp9 slice\n");
 		break;
+	case V4L2_PIX_FMT_HEVC_SLICE:
+		curr_len = snprintf(buf + *used, total - *used,
+				    "\toutput format: hevc slice\n");
+		break;
+	case V4L2_PIX_FMT_AV1_FRAME:
+		curr_len = snprintf(buf + *used, total - *used,
+				    "\toutput format: av1 slice\n");
+		break;
 	default:
 		curr_len = snprintf(buf + *used, total - *used,
 				    "\tunsupported output format: 0x%x\n",
@@ -45,6 +53,14 @@ static void mtk_vdec_dbgfs_get_format_type(struct mtk_vcodec_dec_ctx *ctx, char
 		curr_len = snprintf(buf + *used, total - *used,
 				    "\tcapture format: MT21C\n");
 		break;
+	case V4L2_PIX_FMT_MT2110T:
+		curr_len = snprintf(buf + *used, total - *used,
+				    "\tcapture format: MT2110T (10bit tile mode)\n");
+		break;
+	case V4L2_PIX_FMT_MT2110R:
+		curr_len = snprintf(buf + *used, total - *used,
+				    "\tcapture format: MT2110T (10bit raster mode)\n");
+		break;
 	default:
 		curr_len = snprintf(buf + *used, total - *used,
 				    "\tunsupported capture format: 0x%x\n",
@@ -122,9 +138,10 @@ static ssize_t mtk_vdec_dbgfs_read(struct file *filp, char __user *ubuf,
 
 		if (dbgfs_index[MTK_VDEC_DBGFS_PICINFO]) {
 			curr_len = snprintf(buf + used_len, total_len - used_len,
-					    "\treal(%dx%d)=>align(%dx%d)\n",
+					    "\treal(%dx%d)=>align(%dx%d) 10bit(%d)\n",
 					    ctx->picinfo.pic_w, ctx->picinfo.pic_h,
-					    ctx->picinfo.buf_w, ctx->picinfo.buf_h);
+					    ctx->picinfo.buf_w, ctx->picinfo.buf_h,
+					    ctx->is_10bit_bitstream);
 			used_len += curr_len;
 		}
 
-- 
2.46.0



From yunfei.dong at mediatek.com  Sat May 10 00:53:43 2025
From: yunfei.dong at mediatek.com (Yunfei Dong)
Date: Sat, 10 May 2025 15:53:43 +0800
Subject: [PATCH 13/14] media: mediatek: decoder: fill av1 buffer size with picinfo
In-Reply-To: <20250510075357.11761-1-yunfei.dong@mediatek.com>
References: <20250510075357.11761-1-yunfei.dong@mediatek.com>
Message-ID: <20250510075357.11761-14-yunfei.dong@mediatek.com>

The buffer size of y and c plane has been calculated in vcp/scp,
can fill each frame buffer size with picinfo directly.

Signed-off-by: Yunfei Dong <yunfei.dong at mediatek.com>
---
 .../vcodec/decoder/vdec/vdec_av1_req_lat_if.c      | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c
index 2b2173062cb0..6070485e26c4 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c
@@ -1799,18 +1799,19 @@ static int vdec_av1_slice_setup_core_buffer(struct vdec_av1_slice_instance *inst
 {
 	struct vb2_buffer *vb;
 	struct vb2_queue *vq;
-	int w, h, plane, size;
+	int plane;
 	int i;
 
 	plane = instance->ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes;
-	w = vsi->frame.uh.upscaled_width;
-	h = vsi->frame.uh.frame_height;
-	size = ALIGN(w, VCODEC_DEC_ALIGNED_64) * ALIGN(h, VCODEC_DEC_ALIGNED_64);
 
 	/* frame buffer */
 	vsi->fb.y.dma_addr = fb->base_y.dma_addr;
+
+	vsi->fb.y.size = instance->ctx->picinfo.fb_sz[0];
+	vsi->fb.c.size = instance->ctx->picinfo.fb_sz[1];
+
 	if (plane == 1)
-		vsi->fb.c.dma_addr = fb->base_y.dma_addr + size;
+		vsi->fb.c.dma_addr = fb->base_y.dma_addr + vsi->fb.y.size;
 	else
 		vsi->fb.c.dma_addr = fb->base_c.dma_addr;
 
@@ -1835,8 +1836,9 @@ static int vdec_av1_slice_setup_core_buffer(struct vdec_av1_slice_instance *inst
 		}
 
 		vref->y.dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
+		vref->y.size = vsi->fb.y.size;
 		if (plane == 1)
-			vref->c.dma_addr = vref->y.dma_addr + size;
+			vref->c.dma_addr = vref->y.dma_addr + vsi->fb.y.size;
 		else
 			vref->c.dma_addr = vb2_dma_contig_plane_dma_addr(vb, 1);
 	}
-- 
2.46.0



From yunfei.dong at mediatek.com  Sat May 10 00:53:44 2025
From: yunfei.dong at mediatek.com (Yunfei Dong)
Date: Sat, 10 May 2025 15:53:44 +0800
Subject: [PATCH 14/14] media: mediatek: decoder: support av1 extend vsi
In-Reply-To: <20250510075357.11761-1-yunfei.dong@mediatek.com>
References: <20250510075357.11761-1-yunfei.dong@mediatek.com>
Message-ID: <20250510075357.11761-15-yunfei.dong@mediatek.com>

The driver can't access tile buffer address for extend architecture,
set tile group information in vcp and share it with kernel.

Signed-off-by: Yunfei Dong <yunfei.dong at mediatek.com>
---
 .../vcodec/decoder/vdec/vdec_av1_req_lat_if.c | 46 ++++++++++++++++---
 1 file changed, 39 insertions(+), 7 deletions(-)

diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c
index 6070485e26c4..43541faeea87 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_av1_req_lat_if.c
@@ -25,6 +25,8 @@
 
 #define AV1_INVALID_IDX			-1
 
+#define AV1_NON_EXT_VSI_SIZE		0xD50
+
 #define AV1_DIV_ROUND_UP_POW2(value, n)			\
 ({							\
 	typeof(n) _n  = n;				\
@@ -641,6 +643,8 @@ struct vdec_av1_slice_fb {
  * @frame:		current frame info
  * @state:		status after decode done
  * @cur_lst_tile_id:	tile id for large scale
+ * @tile_group:	tile group info
+ * @reserved:		reserved
  */
 struct vdec_av1_slice_vsi {
 	/* lat */
@@ -665,6 +669,8 @@ struct vdec_av1_slice_vsi {
 	struct vdec_av1_slice_frame frame;
 	struct vdec_av1_slice_state state;
 	u32 cur_lst_tile_id;
+	struct vdec_av1_slice_tile_group tile_group;
+	unsigned int reserved[4];
 };
 
 /**
@@ -1394,13 +1400,18 @@ static int vdec_av1_slice_setup_tile_group(struct vdec_av1_slice_instance *insta
 					   struct vdec_av1_slice_vsi *vsi)
 {
 	struct v4l2_ctrl_av1_tile_group_entry *ctrl_tge;
-	struct vdec_av1_slice_tile_group *tile_group = &instance->tile_group;
+	struct vdec_av1_slice_tile_group *tile_group;
 	struct vdec_av1_slice_uncompressed_header *uh = &vsi->frame.uh;
 	struct vdec_av1_slice_tile *tile = &uh->tile;
 	struct v4l2_ctrl *ctrl;
 	u32 tge_size;
 	int i;
 
+	if (IS_VDEC_SUPPORT_EXT(instance->ctx->dev->dec_capability))
+		tile_group = &vsi->tile_group;
+	else
+		tile_group = &instance->tile_group;
+
 	ctrl = v4l2_ctrl_find(&instance->ctx->ctrl_hdl, V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY);
 	if (!ctrl)
 		return -EINVAL;
@@ -1601,6 +1612,7 @@ static void vdec_av1_slice_setup_lat_buffer(struct vdec_av1_slice_instance *inst
 					    struct vdec_lat_buf *lat_buf)
 {
 	struct vdec_av1_slice_work_buffer *work_buffer;
+	u32 num_tiles;
 	int i;
 
 	vsi->bs.dma_addr = bs->dma_addr;
@@ -1635,12 +1647,18 @@ static void vdec_av1_slice_setup_lat_buffer(struct vdec_av1_slice_instance *inst
 
 	vsi->tile.buf = instance->tile.dma_addr;
 	vsi->tile.size = instance->tile.size;
-	memcpy(lat_buf->tile_addr.va, instance->tile.va, 64 * instance->tile_group.num_tiles);
 
 	vsi->cdf_table.buf = instance->cdf_table.dma_addr;
 	vsi->cdf_table.size = instance->cdf_table.size;
 	vsi->iq_table.buf = instance->iq_table.dma_addr;
 	vsi->iq_table.size = instance->iq_table.size;
+
+	if (IS_VDEC_SUPPORT_EXT(instance->ctx->dev->dec_capability))
+		num_tiles = vsi->tile_group.num_tiles;
+	else
+		num_tiles = instance->tile_group.num_tiles;
+
+	memcpy(lat_buf->tile_addr.va, instance->tile.va, 64 * num_tiles);
 }
 
 static void vdec_av1_slice_setup_seg_buffer(struct vdec_av1_slice_instance *instance,
@@ -1663,7 +1681,7 @@ static void vdec_av1_slice_setup_tile_buffer(struct vdec_av1_slice_instance *ins
 					     struct vdec_av1_slice_vsi *vsi,
 					     struct mtk_vcodec_mem *bs)
 {
-	struct vdec_av1_slice_tile_group *tile_group = &instance->tile_group;
+	struct vdec_av1_slice_tile_group *tile_group;
 	struct vdec_av1_slice_uncompressed_header *uh = &vsi->frame.uh;
 	struct vdec_av1_slice_tile *tile = &uh->tile;
 	u32 tile_num, tile_row, tile_col;
@@ -1674,6 +1692,11 @@ static void vdec_av1_slice_setup_tile_buffer(struct vdec_av1_slice_instance *ins
 	u32 *tile_info_buf = instance->tile.va;
 	u64 pa = (u64)bs->dma_addr;
 
+	if (IS_VDEC_SUPPORT_EXT(instance->ctx->dev->dec_capability))
+		tile_group = &vsi->tile_group;
+	else
+		tile_group = &instance->tile_group;
+
 	if (uh->disable_cdf_update == 0)
 		allow_update_cdf = 1;
 
@@ -1887,7 +1910,7 @@ static int vdec_av1_slice_init(struct mtk_vcodec_dec_ctx *ctx)
 {
 	struct vdec_av1_slice_instance *instance;
 	struct vdec_av1_slice_init_vsi *vsi;
-	int ret;
+	int ret, vsi_size = AV1_NON_EXT_VSI_SIZE;
 
 	instance = kzalloc(sizeof(*instance), GFP_KERNEL);
 	if (!instance)
@@ -1926,9 +1949,18 @@ static int vdec_av1_slice_init(struct mtk_vcodec_dec_ctx *ctx)
 		goto error_vsi;
 	}
 
-	if (vsi->vsi_size != sizeof(struct vdec_av1_slice_vsi))
-		mtk_vdec_err(ctx, "remote vsi size 0x%x mismatch! expected: 0x%zx\n",
-			     vsi->vsi_size, sizeof(struct vdec_av1_slice_vsi));
+	if (IS_VDEC_SUPPORT_EXT(ctx->dev->dec_capability)) {
+		vsi_size = sizeof(struct vdec_av1_slice_vsi);
+		vsi->iq_table_size = AV1_IQ_TABLE_SIZE;
+		vsi->cdf_table_size = AV1_CDF_SIZE;
+	}
+
+	if (vsi->vsi_size != vsi_size) {
+		mtk_vdec_err(ctx, "remote vsi size 0x%x mismatch! expected: 0x%x\n",
+			     vsi->vsi_size, vsi_size);
+		ret = -EINVAL;
+		goto error_vsi;
+	}
 
 	instance->irq_enabled = 1;
 	instance->inneracing_mode = IS_VDEC_INNER_RACING(instance->ctx->dev->dec_capability);
-- 
2.46.0



From peter.wang at mediatek.com  Sat May 10 01:01:01 2025
From: peter.wang at mediatek.com (peter.wang at mediatek.com)
Date: Sat, 10 May 2025 16:01:01 +0800
Subject: [PATCH v2] ufs: core: support updating device command timeout
Message-ID: <20250510080345.595798-1-peter.wang@mediatek.com>

From: Peter Wang <peter.wang at mediatek.com>

The default device command timeout remains 1.5 seconds,
but platform drivers can override it if needed.

Some UFS device commands may timeout due to being blocked
by regular SCSI write commands. Therefore, the maximun timeout
needs to be extended to 30 seconds, matching the SCSI write
command timeout. And for error injection purposes, set the
minimum value to 1 ms.

V2:
- Change minimun value to 1ms

Signed-off-by: Peter Wang <peter.wang at mediatek.com>
Suggested-by: Bart Van Assche <bvanassche at acm.org>
---
 drivers/ufs/core/ufshcd.c | 35 ++++++++++++++++++++++++++++-------
 1 file changed, 28 insertions(+), 7 deletions(-)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 7735421e3991..0fcc403f0a9e 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -63,7 +63,11 @@ enum {
 /* Query request retries */
 #define QUERY_REQ_RETRIES 3
 /* Query request timeout */
-#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
+enum {
+	QUERY_REQ_TIMEOUT_MIN     = 1,
+	QUERY_REQ_TIMEOUT_DEFAULT = 1500,
+	QUERY_REQ_TIMEOUT_MAX     = 30000
+};
 
 /* Advanced RPMB request timeout */
 #define ADVANCED_RPMB_REQ_TIMEOUT  3000 /* 3 seconds */
@@ -135,6 +139,23 @@ module_param_cb(uic_cmd_timeout, &uic_cmd_timeout_ops, &uic_cmd_timeout, 0644);
 MODULE_PARM_DESC(uic_cmd_timeout,
 		 "UFS UIC command timeout in milliseconds. Defaults to 500ms. Supported values range from 500ms to 2 seconds inclusively");
 
+static unsigned int dev_cmd_timeout = QUERY_REQ_TIMEOUT_DEFAULT;
+
+static int dev_cmd_timeout_set(const char *val, const struct kernel_param *kp)
+{
+	return param_set_uint_minmax(val, kp, QUERY_REQ_TIMEOUT_MIN,
+				     QUERY_REQ_TIMEOUT_MAX);
+}
+
+static const struct kernel_param_ops dev_cmd_timeout_ops = {
+	.set = dev_cmd_timeout_set,
+	.get = param_get_uint,
+};
+
+module_param_cb(dev_cmd_timeout, &dev_cmd_timeout_ops, &dev_cmd_timeout, 0644);
+MODULE_PARM_DESC(dev_cmd_timeout,
+		 "UFS Device command timeout in milliseconds. Defaults to 1.5s. Supported values range from 1ms to 30 seconds inclusively");
+
 #define ufshcd_toggle_vreg(_dev, _vreg, _on)				\
 	({                                                              \
 		int _ret;                                               \
@@ -3365,7 +3386,7 @@ int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
 	struct ufs_query_req *request = NULL;
 	struct ufs_query_res *response = NULL;
 	int err, selector = 0;
-	int timeout = QUERY_REQ_TIMEOUT;
+	int timeout = dev_cmd_timeout;
 
 	BUG_ON(!hba);
 
@@ -3462,7 +3483,7 @@ int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
 		goto out_unlock;
 	}
 
-	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
+	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, dev_cmd_timeout);
 
 	if (err) {
 		dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
@@ -3558,7 +3579,7 @@ static int __ufshcd_query_descriptor(struct ufs_hba *hba,
 		goto out_unlock;
 	}
 
-	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
+	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, dev_cmd_timeout);
 
 	if (err) {
 		dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
@@ -6020,7 +6041,7 @@ int ufshcd_read_device_lvl_exception_id(struct ufs_hba *hba, u64 *exception_id)
 
 	request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
 
-	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
+	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, dev_cmd_timeout);
 
 	if (err) {
 		dev_err(hba->dev, "%s: failed to read device level exception %d\n",
@@ -7245,7 +7266,7 @@ static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
 	 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
 	 * read the response directly ignoring all errors.
 	 */
-	ufshcd_issue_dev_cmd(hba, lrbp, tag, QUERY_REQ_TIMEOUT);
+	ufshcd_issue_dev_cmd(hba, lrbp, tag, dev_cmd_timeout);
 
 	/* just copy the upiu response as it is */
 	memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
@@ -8678,7 +8699,7 @@ static void ufshcd_set_timestamp_attr(struct ufs_hba *hba)
 
 	put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3);
 
-	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
+	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, dev_cmd_timeout);
 
 	if (err)
 		dev_err(hba->dev, "%s: failed to set timestamp %d\n",
-- 
2.45.2



From lorenzo at kernel.org  Sat May 10 01:20:14 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Sat, 10 May 2025 10:20:14 +0200
Subject: [PATCH v2 1/4] net: airoha: Fix an error handling path in
 airoha_alloc_gdm_port()
In-Reply-To: <68149c51-ba75-4f0f-a86a-bd810d47d684@wanadoo.fr>
References: <5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet@wanadoo.fr>
 <aBzOaiU6Ac3ZTU-4@lore-desk>
 <68149c51-ba75-4f0f-a86a-bd810d47d684@wanadoo.fr>
Message-ID: <aB8MPkMYXWvoaA03@lore-desk>

> Le 08/05/2025 ? 17:31, Lorenzo Bianconi a ?crit?:
> > > If register_netdev() fails, the error handling path of the probe will not
> > > free the memory allocated by the previous airoha_metadata_dst_alloc() call
> > > because port->dev->reg_state will not be NETREG_REGISTERED.
> > > 
> > > So, an explicit airoha_metadata_dst_free() call is needed in this case to
> > > avoid a memory leak.
> > > 
> > > Fixes: af3cf757d5c9 ("net: airoha: Move DSA tag in DMA descriptor")
> > > Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
> > > ---
> > > Changes in v2:
> > >    - New patch
> > > 
> > > Compile tested only.
> > > ---
> > >   drivers/net/ethernet/airoha/airoha_eth.c | 10 +++++++++-
> > >   1 file changed, 9 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> > > index 16c7896f931f..af8c4015938c 100644
> > > --- a/drivers/net/ethernet/airoha/airoha_eth.c
> > > +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> > > @@ -2873,7 +2873,15 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
> > >   	if (err)
> > >   		return err;
> > > -	return register_netdev(dev);
> > > +	err = register_netdev(dev);
> > > +	if (err)
> > > +		goto free_metadata_dst;
> > > +
> > > +	return 0;
> > > +
> > > +free_metadata_dst:
> > > +	airoha_metadata_dst_free(port);
> > > +	return err;
> > >   }
> > >   static int airoha_probe(struct platform_device *pdev)
> > > -- 
> > > 2.49.0
> > > 
> > 
> > I have not tested it but I think the right fix here would be something like:
> > 
> > diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> > index b1ca8322d4eb..33f8926bba25 100644
> > --- a/drivers/net/ethernet/airoha/airoha_eth.c
> > +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> > @@ -2996,10 +2996,12 @@ static int airoha_probe(struct platform_device *pdev)
> >   	for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
> >   		struct airoha_gdm_port *port = eth->ports[i];
> > -		if (port && port->dev->reg_state == NETREG_REGISTERED) {
> > +		if (!port)
> > +			continue;
> 
> I think it works.
> 
> We can still have port non NULL and airoha_metadata_dst_alloc() which fails,
> but airoha_metadata_dst_free() seems to handle it correctly.
> 
> CJ

Actually, in order to be consistent with the rest of the code where a
routine undoes changes in case of an internal failure, I would prefer your
approach. Can you please post your solution in the next iteration? Thanks.

Regards,
Lorenzo

> 
> 
> > +
> > +		if (port->dev->reg_state == NETREG_REGISTERED)
> >   			unregister_netdev(port->dev);
> > -			airoha_metadata_dst_free(port);
> > -		}
> > +		airoha_metadata_dst_free(port);
> >   	}
> >   	free_netdev(eth->napi_dev);
> >   	platform_set_drvdata(pdev, NULL);
> > 
> > Regards,
> > Lorenzo
> 
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From mripard at kernel.org  Sat May 10 01:43:04 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 10:43:04 +0200
Subject: [PATCH v3 02/22] drm: convert many bridge drivers from
 devm_kzalloc() to devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-2-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
 <20250509-drm-bridge-convert-to-alloc-api-v3-2-b8bc1f16d7aa@bootlin.com>
Message-ID: <4yeqvg3wnlr2bhb54zutgqpkehrodat5w5x4rr5qjlrc2ts3pz@gr2iosycclpl>

On Fri, May 09, 2025 at 03:53:28PM +0200, Luca Ceresoli wrote:
> devm_drm_bridge_alloc() is the new API to be used for allocating (and
> partially initializing) a private driver struct embedding a struct
> drm_bridge.
> 
> For many drivers having a simple code flow in the probe function, this
> commit does a mass conversion automatically with the following semantic
> patch. The changes have been reviewed manually for correctness as well as
> to find any false positives.
> 
> The patch has been applied with the explicit exclusion of bridge/panel.c,
> handled by a separate patch.
> 
> After applying the semantic patch, manually fixed these issues:
> 
>  - 4 drivers need ERR_CAST() instead of PTR_ERR() as the function calling
>    devm_drm_bridge_alloc() returns a pointer
>  - re-added empty lines and comments that the script had removed but that
>    should stay
> 
>   @@
>   type T;
>   identifier C;
>   identifier BR;
>   expression DEV;
>   expression FUNCS;
>   @@
>   -T *C;
>   +T *C;
>    ...
>   (
>   -C = devm_kzalloc(DEV, ...);
>   -if (!C)
>   -    return -ENOMEM;
>   +C = devm_drm_bridge_alloc(DEV, T, BR, FUNCS);
>   +if (IS_ERR(C))
>   +     return PTR_ERR(C);
>   |
>   -C = devm_kzalloc(DEV, ...);
>   -if (!C)
>   -    return ERR_PTR(-ENOMEM);
>   +C = devm_drm_bridge_alloc(DEV, T, BR, FUNCS);
>   +if (IS_ERR(C))
>   +     return PTR_ERR(C);
>   )
>    ...
>   -C->BR.funcs = FUNCS;
> 
> Reviewed-by: Manikandan Muralidharan <manikandan.m at microchip.com> # microchip-lvds.c
> Reviewed-by: Douglas Anderson <dianders at chromium.org> # parade-ps8640
> Tested-by: Douglas Anderson <dianders at chromium.org> # parade-ps8640
> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

Acked-by: Maxime Ripard <mripard at kernel.org>

Maxime
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From mripard at kernel.org  Sat May 10 01:43:56 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 10:43:56 +0200
Subject: [PATCH v3 03/22] drm/bridge: anx7625: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-3-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
 <20250509-drm-bridge-convert-to-alloc-api-v3-3-b8bc1f16d7aa@bootlin.com>
Message-ID: <3cccwtayrisa4x6gn4wvmd3unabionun7va3qlh7cmfxf4ukqd@vgwai2ralai7>

On Fri, May 09, 2025 at 03:53:29PM +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

Acked-by: Maxime Ripard <mripard at kernel.org>
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From mripard at kernel.org  Sat May 10 01:44:28 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 10:44:28 +0200
Subject: [PATCH v3 04/22] drm/bridge: cdns-dsi: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-4-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
 <20250509-drm-bridge-convert-to-alloc-api-v3-4-b8bc1f16d7aa@bootlin.com>
Message-ID: <xf44dsvdlzwxuzxgsmysf62azyv7tvq7dqgy2ixpcw4sb3jifq@gvgpl5qjozld>

On Fri, May 09, 2025 at 03:53:30PM +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

Acked-by: Maxime Ripard <mripard at kernel.org>

Maxime
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From mripard at kernel.org  Sat May 10 01:52:13 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 08:52:13 +0000
Subject: [PATCH v3 05/22] drm/bridge: megachips-stdpxxxx-ge-b850v3-fw:
 convert to devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-5-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-5-b8bc1f16d7aa@bootlin.com>
Message-ID: <79d5e811481345b20d53c0159f8e0aab@kernel.org>

On Fri, 9 May 2025 15:53:31 +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
> 

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From mripard at kernel.org  Sat May 10 01:52:30 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 08:52:30 +0000
Subject: [PATCH v3 06/22] drm/bridge: nxp-ptn3460: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-6-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-6-b8bc1f16d7aa@bootlin.com>
Message-ID: <9c4cd5dbff541b2af45a7c093e619666@kernel.org>

On Fri, 9 May 2025 15:53:32 +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From mripard at kernel.org  Sat May 10 01:52:53 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 08:52:53 +0000
Subject: [PATCH v3 07/22] drm/bridge: sii902x: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-7-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-7-b8bc1f16d7aa@bootlin.com>
Message-ID: <0306d6e01554bd7f41d962848306ef9e@kernel.org>

On Fri, 9 May 2025 15:53:33 +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From mripard at kernel.org  Sat May 10 01:54:10 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 08:54:10 +0000
Subject: [PATCH v3 08/22] drm/omap: dss: dpi: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-8-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-8-b8bc1f16d7aa@bootlin.com>
Message-ID: <e6c1eb762fc643793a3ba02cc0f79e9e@kernel.org>

On Fri, 9 May 2025 15:53:34 +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
> 

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From mripard at kernel.org  Sat May 10 01:54:19 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 08:54:19 +0000
Subject: [PATCH v3 09/22] drm/omap: dss: dsi: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-9-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-9-b8bc1f16d7aa@bootlin.com>
Message-ID: <ef3b22915764e919b2750c2a7b389cbe@kernel.org>

On Fri, 9 May 2025 15:53:35 +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
> 

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From mripard at kernel.org  Sat May 10 01:54:40 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 08:54:40 +0000
Subject: [PATCH v3 10/22] drm/omap: dss: hdmi4: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-10-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-10-b8bc1f16d7aa@bootlin.com>
Message-ID: <d6c002809f9c851bd5e891be23c08d4f@kernel.org>

On Fri, 9 May 2025 15:53:36 +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> Switching from a non-devm to a devm allocation allows removing the kfree()
> in the remove function and in the probe error management code, and as a
> consequence to simplify the code flow by removing now unnecessary gotos.
> 
> [ ... ]

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From mripard at kernel.org  Sat May 10 01:54:55 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 08:54:55 +0000
Subject: [PATCH v3 11/22] drm/omap: dss: hdmi5: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-11-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-11-b8bc1f16d7aa@bootlin.com>
Message-ID: <eee8c1382b8fa3034621a4d3bc251c48@kernel.org>

On Fri, 9 May 2025 15:53:37 +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> Switching from a non-devm to a devm allocation allows removing the kfree()
> in the remove function and in the probe error management code, and as a
> consequence to simplify the code flow by removing now unnecessary gotos.
> 
> [ ... ]

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From mripard at kernel.org  Sat May 10 01:55:57 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 08:55:57 +0000
Subject: [PATCH v3 13/22] drm/omap: dss: venc: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-13-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-13-b8bc1f16d7aa@bootlin.com>
Message-ID: <923990fc00f1d421c7db3ccd74aa516b@kernel.org>

On Fri, 9 May 2025 15:53:39 +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> Switching from a non-devm to a devm allocation allows removing the kfree()
> in the remove function and in the probe error management code, and as a
> consequence to simplify the code flow by removing now unnecessary gotos.
> 
> [ ... ]

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From mripard at kernel.org  Sat May 10 01:56:11 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 08:56:11 +0000
Subject: [PATCH v3 14/22] drm/rcar-du: dsi: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-14-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-14-b8bc1f16d7aa@bootlin.com>
Message-ID: <3b2d3e047a8c0f1735c154f46f420216@kernel.org>

On Fri, 9 May 2025 15:53:40 +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
> 

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From mripard at kernel.org  Sat May 10 01:56:37 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 08:56:37 +0000
Subject: [PATCH v3 15/22] drm/bridge: stm_lvds: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-15-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-15-b8bc1f16d7aa@bootlin.com>
Message-ID: <46bdd0658ee475b1378a831dd0918748@kernel.org>

On Fri, 9 May 2025 15:53:41 +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
> 

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From mripard at kernel.org  Sat May 10 01:57:11 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 08:57:11 +0000
Subject: [PATCH v3 16/22] drm/sti: dvo: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-16-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-16-b8bc1f16d7aa@bootlin.com>
Message-ID: <b9d480ecdb95f59b7e9f0af7694800ef@kernel.org>

On Fri, 9 May 2025 15:53:42 +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> This driver allocates the DRM bridge separately from the main driver
> private struct, which prevents using the new devm_drm_bridge_alloc()
> API. Simplify the code by replacing the struct drm_bridge pointer with an
> 
> [ ... ]

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From mripard at kernel.org  Sat May 10 01:57:30 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 08:57:30 +0000
Subject: [PATCH v3 17/22] drm: zynqmp_dp: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-17-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-17-b8bc1f16d7aa@bootlin.com>
Message-ID: <c264afd17fb81a5c39e4de6eb903d05b@kernel.org>

On Fri, 9 May 2025 15:53:43 +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> This driver has a peculiar structure. zynqmp_dpsub.c is the actual driver,
> which delegates to a submodule (zynqmp_dp.c) the allocation of a
> sub-structure embedding the drm_bridge and its initialization, however it
> 
> [ ... ]

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From mripard at kernel.org  Sat May 10 01:58:22 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 08:58:22 +0000
Subject: [PATCH v3 12/22] drm/omap: dss: sdi: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-12-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-12-b8bc1f16d7aa@bootlin.com>
Message-ID: <5573173c96551b51def2ec8806f297be@kernel.org>

On Fri, 9 May 2025 15:53:38 +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> Switching from a non-devm to a devm allocation allows removing the kfree()
> in the remove function and in the probe error management code, and as a
> consequence to simplify the code flow by removing now unnecessary gotos.
> 
> [ ... ]

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From mripard at kernel.org  Sat May 10 02:15:59 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 09:15:59 +0000
Subject: [PATCH v3 20/22] drm/bridge: add devm_drm_put_bridge()
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-20-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-20-b8bc1f16d7aa@bootlin.com>
Message-ID: <13d5e1fbe12e289da1d1e5184eb5277c@kernel.org>

On Fri, 9 May 2025 15:53:46 +0200, Luca Ceresoli wrote:
> Bridges obtained via devm_drm_bridge_alloc(dev, ...) will be put when the
> requesting device (@dev) is removed.
> 
> However drivers which obtained them may need to put the obtained reference
> explicitly. One such case is if they bind the devm removal action to a
> 
> [ ... ]

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From mripard at kernel.org  Sat May 10 02:42:16 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 09:42:16 +0000
Subject: [PATCH v3 21/22] drm/bridge: panel: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-21-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-21-b8bc1f16d7aa@bootlin.com>
Message-ID: <217864a52bc7770419e5da062d43aaa7@kernel.org>

On Fri, 9 May 2025 15:53:47 +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> The devm lifetime management of this driver is peculiar. The underlying
> device for the panel_bridge is the panel, and the devm lifetime is tied the
> panel device (panel->dev). However the panel_bridge allocation is not
> 
> [ ... ]

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From mripard at kernel.org  Sat May 10 02:42:32 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Sat, 10 May 2025 09:42:32 +0000
Subject: [PATCH v3 22/22] drm/todo: add entry to remove
 devm_drm_put_bridge()
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-22-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-22-b8bc1f16d7aa@bootlin.com>
Message-ID: <0bc432f67dc0cdb5fa307565df72af34@kernel.org>

On Fri, 9 May 2025 15:53:48 +0200, Luca Ceresoli wrote:
> devm_drm_put_bridge() is a temporary workaround waiting for the panel
> bridge lifetime rework. Add a TODO entry to not forget it must be removed
> after such rework.
> 
> Suggested-by: Maxime Ripard <mripard at kernel.org>
> 
> [ ... ]

Acked-by: Maxime Ripard <mripard at kernel.org>

Thanks!
Maxime


From ansuelsmth at gmail.com  Sat May 10 03:23:20 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sat, 10 May 2025 12:23:20 +0200
Subject: [net-next PATCH v3 00/11] net: pcs: Introduce support for fwnode PCS
Message-ID: <20250510102348.14134-1-ansuelsmth@gmail.com>

This series introduce a most awaited feature that is correctly
provide PCS with fwnode without having to use specific export symbol
and additional handling of PCS in phylink.

There is currently an equivalent series for this feature where
a wrapper implementation is proposed. I honestly don't really like
introducing layer of layer of wrapping to workaround stuff, so
this is my attempt at giving a more direct approach to this.

---
First the PCS fwnode:

The concept is to implement a producer-consumer API similar to other
subsystem like clock or PHY.

That seems to be the best solution to the problem as PCS driver needs
to be detached from phylink and implement a simple way to provide a
PCS while maintaining support for probe defer or driver removal.

To keep the implementation simple, the PCS driver devs needs some
collaboration to correctly implement this. This is O.K. as helper
to correctly implement this are provided hence it's really a matter
of following a pattern to correct follow removal of a PCS driver.

A PCS provider have to implement and call fwnode_pcs_add_provider() in
probe function and define an xlate function to define how the PCS
should be provided based on the requested interface and phandle spec
defined in fwnode (based on the #pcs-cells)

fwnode_pcs_get() is provided to provide a specific PCS declared in
fwnode at index.

A simple xlate function is provided for simple single PCS
implementation, fwnode_pcs_simple_get.

A PCS provider on driver removal should first call
fwnode_pcs_del_provider() to delete itself as a provider and then
release the PCS from phylink with phylink_release_pcs() under rtnl
lock.

---
Second PCS handling in phylink:

We have the PCS problem for the only reason that in initial
implementation, we permitted way too much flexibility to MAC driver
and things started to deviate. At times we couldn't think SoC
would start to put PCS outside the MAC hence it was OK to assume
they would live in the same driver. With the introduction of
10g in more consumer devices, we are observing a rapid growth
of this pattern with multiple PCS external to MAC.

To put a stop on this, the only solution is to give back to phylink
control on PCS handling and enforce more robust supported interface
definition from both MAC and PCS side.

It's suggested to read patch 0003 of this series for more info, here
a brief explaination of the idea:

This series introduce handling of PCS in phylink and try to deprecate
.mac_select_pcs.

Phylink now might contain a linked list of available PCS and
those will be used for PCS selection on phylink_major_config.

MAC driver needs to define pcs_interfaces mask in phylink_config
for every interface that needs a dedicated PCS.

These PCS needs to be provided to phylink at phylink_create time
by setting the available_pcs and num_available_pcs in phylink_config.
A helper to parse PCS from fwnode is provided
fwnode_phylink_pcs_parse() that will fill a preallocated array of
PCS. (the same function can be used to get the number of PCS
defined in DT, more info in patch 0005)

phylink_create() will fill the internal PCS list with the passed
array of PCS. phylink_major_config and other user of .mac_select_pcs
are adapted to make use of this new PCS list.

The supported interface value is also moved internally to phylink
struct. This is to handle late removal and addition of PCS.
(the bonus effect to this is giving phylink a clear idea of what
is actually supported by the MAC and his constraint with PCS)

The supported interface mask in phylink is done by OR the
supported_interfaces in phylink_config with every PCS in PCS list.

PCS removal is supported by forcing a mac_config, refresh the
supported interfaces and run a phy_resolve().

PCS late addition is supported by introducing a global notifier
for PCS provider. If a phylink have the pcs_interfaces mask not
zero, it's registered to this notifier.

PCS provider will emit a global PCS add event to signal any
interface that a new PCS might be avialable.

The function will then check if the PCS is related to the MAC
fwnode and add it accordingly.

A user for this new implementation is provided as an Airoha PCS
driver. This was also tested downstream with the IPQ95xx QCOM SoC
and with the help of Daniel also on the various Mediatek MT7988
SoC with both SFP cage implementation and DSA attached.

Lots of tests were done with driver unbind/bind and with interface
up/down also by adding print to make sure major_config_fail gets
correctly triggered and reset once the PCS comes back.

The dedicated commits have longer description on the implementation
so it's suggested to also check there for additional info.

---

Changes v3:
- Out of RFC
- Fix various spelling mistake
- Drop circular dependency patch
- Complete Airoha Ethernet phylink integration
- Introduce .pcs_link_down PCS OP
Changes v2:
- Switch to fwnode
- Implement PCS provider notifier
- Better split changes
- Move supported_interfaces to phylink
- Add circular dependency patch
- Rework handling with indirect addition/removal and
  trigger of phylink_resolve()

Christian Marangi (11):
  net: phylink: keep and use MAC supported_interfaces in phylink struct
  net: phy: introduce phy_interface_copy helper
  net: phylink: introduce internal phylink PCS handling
  net: phylink: add phylink_release_pcs() to externally release a PCS
  net: pcs: implement Firmware node support for PCS driver
  net: phylink: support late PCS provider attach
  dt-bindings: net: ethernet-controller: permit to define multiple PCS
  net: phylink: add .pcs_link_down PCS OP
  net: pcs: airoha: add PCS driver for Airoha SoC
  dt-bindings: net: pcs: Document support for Airoha Ethernet PCS
  net: airoha: add phylink support for GDM2/3/4

 .../bindings/net/ethernet-controller.yaml     |    2 -
 .../bindings/net/pcs/airoha,pcs.yaml          |  112 +
 drivers/net/ethernet/airoha/airoha_eth.c      |  138 +
 drivers/net/ethernet/airoha/airoha_eth.h      |    3 +
 drivers/net/ethernet/airoha/airoha_regs.h     |   12 +
 drivers/net/pcs/Kconfig                       |   14 +
 drivers/net/pcs/Makefile                      |    2 +
 drivers/net/pcs/core.c                        |  241 ++
 drivers/net/pcs/pcs-airoha.c                  | 2920 +++++++++++++++++
 drivers/net/phy/phylink.c                     |  287 +-
 include/linux/pcs/pcs-provider.h              |   41 +
 include/linux/pcs/pcs.h                       |  104 +
 include/linux/phy.h                           |    5 +
 include/linux/phylink.h                       |   14 +
 14 files changed, 3867 insertions(+), 28 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
 create mode 100644 drivers/net/pcs/core.c
 create mode 100644 drivers/net/pcs/pcs-airoha.c
 create mode 100644 include/linux/pcs/pcs-provider.h
 create mode 100644 include/linux/pcs/pcs.h

-- 
2.48.1



From ansuelsmth at gmail.com  Sat May 10 03:23:21 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sat, 10 May 2025 12:23:21 +0200
Subject: [net-next PATCH v3 01/11] net: phylink: keep and use MAC supported_interfaces in phylink struct
In-Reply-To: <20250510102348.14134-1-ansuelsmth@gmail.com>
References: <20250510102348.14134-1-ansuelsmth@gmail.com>
Message-ID: <20250510102348.14134-2-ansuelsmth@gmail.com>

Add in phylink struct a copy of supported_interfaces from phylink_config
and make use of that instead of relying on phylink_config value.

This in preparation for support of PCS handling internally to phylink
where a PCS can be removed or added after the phylink is created and we
need both a reference of the supported_interfaces value from
phylink_config and an internal value that can be updated with the new
PCS info.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/phy/phylink.c | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 0faa3d97e06b..ec42fd278604 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -59,6 +59,11 @@ struct phylink {
 	/* The link configuration settings */
 	struct phylink_link_state link_config;
 
+	/* What interface are supported by the current link.
+	 * Can change on removal or addition of new PCS.
+	 */
+	DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+
 	/* The current settings */
 	phy_interface_t cur_interface;
 
@@ -610,7 +615,7 @@ static int phylink_validate_mask(struct phylink *pl, struct phy_device *phy,
 static int phylink_validate(struct phylink *pl, unsigned long *supported,
 			    struct phylink_link_state *state)
 {
-	const unsigned long *interfaces = pl->config->supported_interfaces;
+	const unsigned long *interfaces = pl->supported_interfaces;
 
 	if (state->interface == PHY_INTERFACE_MODE_NA)
 		return phylink_validate_mask(pl, NULL, supported, state,
@@ -1809,6 +1814,9 @@ struct phylink *phylink_create(struct phylink_config *config,
 	mutex_init(&pl->state_mutex);
 	INIT_WORK(&pl->resolve, phylink_resolve);
 
+	phy_interface_copy(pl->supported_interfaces,
+			   config->supported_interfaces);
+
 	pl->config = config;
 	if (config->type == PHYLINK_NETDEV) {
 		pl->netdev = to_net_dev(config->dev);
@@ -1967,7 +1975,7 @@ static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy,
 		 * those which the host supports.
 		 */
 		phy_interface_and(interfaces, phy->possible_interfaces,
-				  pl->config->supported_interfaces);
+				  pl->supported_interfaces);
 
 		if (phy_interface_empty(interfaces)) {
 			phylink_err(pl, "PHY has no common interfaces\n");
@@ -2684,12 +2692,12 @@ static phy_interface_t phylink_sfp_select_interface(struct phylink *pl,
 		return interface;
 	}
 
-	if (!test_bit(interface, pl->config->supported_interfaces)) {
+	if (!test_bit(interface, pl->supported_interfaces)) {
 		phylink_err(pl,
 			    "selection of interface failed, SFP selected %s (%u) but MAC supports %*pbl\n",
 			    phy_modes(interface), interface,
 			    (int)PHY_INTERFACE_MODE_MAX,
-			    pl->config->supported_interfaces);
+			    pl->supported_interfaces);
 		return PHY_INTERFACE_MODE_NA;
 	}
 
@@ -3576,14 +3584,14 @@ static int phylink_sfp_config_optical(struct phylink *pl)
 
 	phylink_dbg(pl, "optical SFP: interfaces=[mac=%*pbl, sfp=%*pbl]\n",
 		    (int)PHY_INTERFACE_MODE_MAX,
-		    pl->config->supported_interfaces,
+		    pl->supported_interfaces,
 		    (int)PHY_INTERFACE_MODE_MAX,
 		    pl->sfp_interfaces);
 
 	/* Find the union of the supported interfaces by the PCS/MAC and
 	 * the SFP module.
 	 */
-	phy_interface_and(interfaces, pl->config->supported_interfaces,
+	phy_interface_and(interfaces, pl->supported_interfaces,
 			  pl->sfp_interfaces);
 	if (phy_interface_empty(interfaces)) {
 		phylink_err(pl, "unsupported SFP module: no common interface modes\n");
@@ -3729,7 +3737,7 @@ static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)
 
 	/* Set the PHY's host supported interfaces */
 	phy_interface_and(phy->host_interfaces, phylink_sfp_interfaces,
-			  pl->config->supported_interfaces);
+			  pl->supported_interfaces);
 
 	/* Do the initial configuration */
 	return phylink_sfp_config_phy(pl, phy);
-- 
2.48.1



From ansuelsmth at gmail.com  Sat May 10 03:23:22 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sat, 10 May 2025 12:23:22 +0200
Subject: [net-next PATCH v3 02/11] net: phy: introduce phy_interface_copy helper
In-Reply-To: <20250510102348.14134-1-ansuelsmth@gmail.com>
References: <20250510102348.14134-1-ansuelsmth@gmail.com>
Message-ID: <20250510102348.14134-3-ansuelsmth@gmail.com>

Introduce phy_interface_copy helper as a shorthand to copy the PHY
interface bitmap to a different location.

This is useful if a PHY interface bitmap needs to be stored in a
different variable and needs to be reset to an original value saved in a
different bitmap.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 include/linux/phy.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/linux/phy.h b/include/linux/phy.h
index d62d292024bc..9f0e5fb30d63 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -173,6 +173,11 @@ static inline void phy_interface_or(unsigned long *dst, const unsigned long *a,
 	bitmap_or(dst, a, b, PHY_INTERFACE_MODE_MAX);
 }
 
+static inline void phy_interface_copy(unsigned long *dst, const unsigned long *src)
+{
+	bitmap_copy(dst, src, PHY_INTERFACE_MODE_MAX);
+}
+
 static inline void phy_interface_set_rgmii(unsigned long *intf)
 {
 	__set_bit(PHY_INTERFACE_MODE_RGMII, intf);
-- 
2.48.1



From ansuelsmth at gmail.com  Sat May 10 03:23:23 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sat, 10 May 2025 12:23:23 +0200
Subject: [net-next PATCH v3 03/11] net: phylink: introduce internal phylink PCS handling
In-Reply-To: <20250510102348.14134-1-ansuelsmth@gmail.com>
References: <20250510102348.14134-1-ansuelsmth@gmail.com>
Message-ID: <20250510102348.14134-4-ansuelsmth@gmail.com>

Introduce internal handling of PCS for phylink. This is an alternative
to .mac_select_pcs that moves the selection logic of the PCS entirely to
phylink with the usage of the supported_interface value in the PCS
struct.

MAC should now provide an array of available PCS in phylink_config in
.available_pcs and fill the .num_available_pcs with the number of
elements in the array. MAC should also define a new bitmap,
pcs_interfaces, in phylink_config to define for what interface mode a
dedicated PCS is required.

On phylink_create() this array is parsed and a linked list of PCS is
created based on the PCS passed in phylink_config.
Also the supported_interface value in phylink struct is updated with the
new supported_interface from the provided PCS.

On phylink_start() every PCS in phylink PCS list gets attached to the
phylink instance. This is done by setting the phylink value in
phylink_pcs struct to the phylink instance.

On phylink_stop(), every PCS in phylink PCS list is detached from the
phylink instance. This is done by setting the phylink value in
phylink_pcs struct to NULL.

phylink_validate_mac_and_pcs(), phylink_major_config() and
phylink_inband_caps() are updated to support this new implementation
with the PCS list stored in phylink.

They will make use of phylink_validate_pcs_interface() that will loop
for every PCS in the phylink PCS available list and find one that supports
the passed interface.

phylink_validate_pcs_interface() applies the same logic of .mac_select_pcs
where if a supported_interface value is not set for the PCS struct, then
it's assumed every interface is supported.

A MAC is required to implement either a .mac_select_pcs or make use of
the PCS list implementation. Implementing both will result in a fail
on MAC/PCS validation.

phylink value in phylink_pcs struct with this implementation is used to
track from PCS side when it's attached to a phylink instance. PCS driver
will make use of this information to correctly detach from a phylink
instance if needed.

The .mac_select_pcs implementation is not changed but it's expected that
every MAC driver migrates to the new implementation to later deprecate
and remove .mac_select_pcs.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/phy/phylink.c | 147 +++++++++++++++++++++++++++++++++-----
 include/linux/phylink.h   |  10 +++
 2 files changed, 139 insertions(+), 18 deletions(-)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index ec42fd278604..95d7e06dee56 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -59,6 +59,9 @@ struct phylink {
 	/* The link configuration settings */
 	struct phylink_link_state link_config;
 
+	/* List of available PCS */
+	struct list_head pcs_list;
+
 	/* What interface are supported by the current link.
 	 * Can change on removal or addition of new PCS.
 	 */
@@ -144,6 +147,8 @@ static const phy_interface_t phylink_sfp_interface_preference[] = {
 
 static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);
 
+static void phylink_run_resolve(struct phylink *pl);
+
 /**
  * phylink_set_port_modes() - set the port type modes in the ethtool mask
  * @mask: ethtool link mode mask
@@ -499,22 +504,59 @@ static void phylink_validate_mask_caps(unsigned long *supported,
 	linkmode_and(state->advertising, state->advertising, mask);
 }
 
+static int phylink_validate_pcs_interface(struct phylink_pcs *pcs,
+					  phy_interface_t interface)
+{
+	/* If PCS define an empty supported_interfaces value, assume
+	 * all interface are supported.
+	 */
+	if (phy_interface_empty(pcs->supported_interfaces))
+		return 0;
+
+	/* Ensure that this PCS supports the interface mode */
+	if (!test_bit(interface, pcs->supported_interfaces))
+		return -EINVAL;
+
+	return 0;
+}
+
 static int phylink_validate_mac_and_pcs(struct phylink *pl,
 					unsigned long *supported,
 					struct phylink_link_state *state)
 {
-	struct phylink_pcs *pcs = NULL;
 	unsigned long capabilities;
+	struct phylink_pcs *pcs;
+	bool pcs_found = false;
 	int ret;
 
 	/* Get the PCS for this interface mode */
 	if (pl->mac_ops->mac_select_pcs) {
+		/* Make sure either PCS internal validation or .mac_select_pcs
+		 * is used. Return error if both are defined.
+		 */
+		if (!list_empty(&pl->pcs_list)) {
+			phylink_err(pl, "either phylink_pcs_add() or .mac_select_pcs must be used\n");
+			return -EINVAL;
+		}
+
 		pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
 		if (IS_ERR(pcs))
 			return PTR_ERR(pcs);
+
+		pcs_found = !!pcs;
+	} else {
+		/* Check every assigned PCS and search for one that supports
+		 * the interface.
+		 */
+		list_for_each_entry(pcs, &pl->pcs_list, list) {
+			if (!phylink_validate_pcs_interface(pcs, state->interface)) {
+				pcs_found = true;
+				break;
+			}
+		}
 	}
 
-	if (pcs) {
+	if (pcs_found) {
 		/* The PCS, if present, must be setup before phylink_create()
 		 * has been called. If the ops is not initialised, print an
 		 * error and backtrace rather than oopsing the kernel.
@@ -526,13 +568,10 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
 			return -EINVAL;
 		}
 
-		/* Ensure that this PCS supports the interface which the MAC
-		 * returned it for. It is an error for the MAC to return a PCS
-		 * that does not support the interface mode.
-		 */
-		if (!phy_interface_empty(pcs->supported_interfaces) &&
-		    !test_bit(state->interface, pcs->supported_interfaces)) {
-			phylink_err(pl, "MAC returned PCS which does not support %s\n",
+		/* Recheck PCS to handle legacy way for .mac_select_pcs */
+		ret = phylink_validate_pcs_interface(pcs, state->interface);
+		if (ret) {
+			phylink_err(pl, "selected PCS does not support %s\n",
 				    phy_modes(state->interface));
 			return -EINVAL;
 		}
@@ -937,12 +976,22 @@ static unsigned int phylink_inband_caps(struct phylink *pl,
 					 phy_interface_t interface)
 {
 	struct phylink_pcs *pcs;
+	bool pcs_found = false;
 
-	if (!pl->mac_ops->mac_select_pcs)
-		return 0;
+	if (pl->mac_ops->mac_select_pcs) {
+		pcs = pl->mac_ops->mac_select_pcs(pl->config,
+						  interface);
+		pcs_found = !!pcs;
+	} else {
+		list_for_each_entry(pcs, &pl->pcs_list, list) {
+			if (!phylink_validate_pcs_interface(pcs, interface)) {
+				pcs_found = true;
+				break;
+			}
+		}
+	}
 
-	pcs = pl->mac_ops->mac_select_pcs(pl->config, interface);
-	if (!pcs)
+	if (!pcs_found)
 		return 0;
 
 	return phylink_pcs_inband_caps(pcs, interface);
@@ -1228,10 +1277,36 @@ static void phylink_major_config(struct phylink *pl, bool restart,
 			pl->major_config_failed = true;
 			return;
 		}
+	/* Find a PCS in available PCS list for the requested interface.
+	 * This doesn't overwrite the previous .mac_select_pcs as either
+	 * .mac_select_pcs or PCS list implementation are permitted.
+	 *
+	 * Skip searching if the MAC doesn't require a dedicaed PCS for
+	 * the requested interface.
+	 */
+	} else if (test_bit(state->interface, pl->config->pcs_interfaces)) {
+		bool pcs_found = false;
+
+		list_for_each_entry(pcs, &pl->pcs_list, list) {
+			if (!phylink_validate_pcs_interface(pcs,
+							    state->interface)) {
+				pcs_found = true;
+				break;
+			}
+		}
+
+		if (!pcs_found) {
+			phylink_err(pl,
+				    "couldn't find a PCS for %s\n",
+				    phy_modes(state->interface));
 
-		pcs_changed = pl->pcs != pcs;
+			pl->major_config_failed = true;
+			return;
+		}
 	}
 
+	pcs_changed = pl->pcs != pcs;
+
 	phylink_pcs_neg_mode(pl, pcs, state->interface, state->advertising);
 
 	phylink_dbg(pl, "major config, active %s/%s/%s\n",
@@ -1258,10 +1333,12 @@ static void phylink_major_config(struct phylink *pl, bool restart,
 	if (pcs_changed) {
 		phylink_pcs_disable(pl->pcs);
 
-		if (pl->pcs)
-			pl->pcs->phylink = NULL;
+		if (pl->mac_ops->mac_select_pcs) {
+			if (pl->pcs)
+				pl->pcs->phylink = NULL;
 
-		pcs->phylink = pl;
+			pcs->phylink = pl;
+		}
 
 		pl->pcs = pcs;
 	}
@@ -1797,8 +1874,9 @@ struct phylink *phylink_create(struct phylink_config *config,
 			       phy_interface_t iface,
 			       const struct phylink_mac_ops *mac_ops)
 {
+	struct phylink_pcs *pcs;
 	struct phylink *pl;
-	int ret;
+	int i, ret;
 
 	/* Validate the supplied configuration */
 	if (phy_interface_empty(config->supported_interfaces)) {
@@ -1813,9 +1891,21 @@ struct phylink *phylink_create(struct phylink_config *config,
 
 	mutex_init(&pl->state_mutex);
 	INIT_WORK(&pl->resolve, phylink_resolve);
+	INIT_LIST_HEAD(&pl->pcs_list);
+
+	/* Fill the PCS list with available PCS from phylink config */
+	for (i = 0; i < config->num_available_pcs; i++) {
+		pcs = config->available_pcs[i];
+
+		list_add(&pcs->list, &pl->pcs_list);
+	}
 
 	phy_interface_copy(pl->supported_interfaces,
 			   config->supported_interfaces);
+	list_for_each_entry(pcs, &pl->pcs_list, list)
+		phy_interface_or(pl->supported_interfaces,
+				 pl->supported_interfaces,
+				 pcs->supported_interfaces);
 
 	pl->config = config;
 	if (config->type == PHYLINK_NETDEV) {
@@ -1894,10 +1984,16 @@ EXPORT_SYMBOL_GPL(phylink_create);
  */
 void phylink_destroy(struct phylink *pl)
 {
+	struct phylink_pcs *pcs, *tmp;
+
 	sfp_bus_del_upstream(pl->sfp_bus);
 	if (pl->link_gpio)
 		gpiod_put(pl->link_gpio);
 
+	/* Remove every PCS from phylink PCS list */
+	list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list)
+		list_del(&pcs->list);
+
 	cancel_work_sync(&pl->resolve);
 	kfree(pl);
 }
@@ -2374,6 +2470,7 @@ static irqreturn_t phylink_link_handler(int irq, void *data)
  */
 void phylink_start(struct phylink *pl)
 {
+	struct phylink_pcs *pcs;
 	bool poll = false;
 
 	ASSERT_RTNL();
@@ -2400,6 +2497,10 @@ void phylink_start(struct phylink *pl)
 
 	pl->pcs_state = PCS_STATE_STARTED;
 
+	/* link available PCS to phylink struct */
+	list_for_each_entry(pcs, &pl->pcs_list, list)
+		pcs->phylink = pl;
+
 	phylink_enable_and_run_resolve(pl, PHYLINK_DISABLE_STOPPED);
 
 	if (pl->cfg_link_an_mode == MLO_AN_FIXED && pl->link_gpio) {
@@ -2444,6 +2545,8 @@ EXPORT_SYMBOL_GPL(phylink_start);
  */
 void phylink_stop(struct phylink *pl)
 {
+	struct phylink_pcs *pcs;
+
 	ASSERT_RTNL();
 
 	if (pl->sfp_bus)
@@ -2461,6 +2564,14 @@ void phylink_stop(struct phylink *pl)
 	pl->pcs_state = PCS_STATE_DOWN;
 
 	phylink_pcs_disable(pl->pcs);
+
+	/* Drop link between phylink and PCS */
+	list_for_each_entry(pcs, &pl->pcs_list, list)
+		pcs->phylink = NULL;
+
+	/* Restore original supported interfaces */
+	phy_interface_copy(pl->supported_interfaces,
+			   pl->config->supported_interfaces);
 }
 EXPORT_SYMBOL_GPL(phylink_stop);
 
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index 30659b615fca..ef0b5a0729c8 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -150,12 +150,16 @@ enum phylink_op_type {
  *		     if MAC link is at %MLO_AN_FIXED mode.
  * @supported_interfaces: bitmap describing which PHY_INTERFACE_MODE_xxx
  *                        are supported by the MAC/PCS.
+ * @pcs_interfaces: bitmap describing for which PHY_INTERFACE_MODE_xxx a
+ *		    dedicated PCS is required.
  * @lpi_interfaces: bitmap describing which PHY interface modes can support
  *		    LPI signalling.
  * @mac_capabilities: MAC pause/speed/duplex capabilities.
  * @lpi_capabilities: MAC speeds which can support LPI signalling
  * @lpi_timer_default: Default EEE LPI timer setting.
  * @eee_enabled_default: If set, EEE will be enabled by phylink at creation time
+ * @available_pcs: array of available phylink_pcs PCS
+ * @num_available_pcs: num of available phylink_pcs PCS
  */
 struct phylink_config {
 	struct device *dev;
@@ -168,11 +172,14 @@ struct phylink_config {
 	void (*get_fixed_state)(struct phylink_config *config,
 				struct phylink_link_state *state);
 	DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+	DECLARE_PHY_INTERFACE_MASK(pcs_interfaces);
 	DECLARE_PHY_INTERFACE_MASK(lpi_interfaces);
 	unsigned long mac_capabilities;
 	unsigned long lpi_capabilities;
 	u32 lpi_timer_default;
 	bool eee_enabled_default;
+	struct phylink_pcs **available_pcs;
+	unsigned int num_available_pcs;
 };
 
 void phylink_limit_mac_speed(struct phylink_config *config, u32 max_speed);
@@ -469,6 +476,9 @@ struct phylink_pcs {
 	struct phylink *phylink;
 	bool poll;
 	bool rxc_always_on;
+
+	/* private: */
+	struct list_head list;
 };
 
 /**
-- 
2.48.1



From ansuelsmth at gmail.com  Sat May 10 03:23:24 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sat, 10 May 2025 12:23:24 +0200
Subject: [net-next PATCH v3 04/11] net: phylink: add phylink_release_pcs() to externally release a PCS
In-Reply-To: <20250510102348.14134-1-ansuelsmth@gmail.com>
References: <20250510102348.14134-1-ansuelsmth@gmail.com>
Message-ID: <20250510102348.14134-5-ansuelsmth@gmail.com>

Add phylink_release_pcs() to externally release a PCS from a phylink
instance. This can be used to handle case when a single PCS needs to be
removed and the phylink instance needs to be refreshed.

On calling phylink_release_pcs(), the PCS will be removed from the
phylink internal PCS list and the phylink supported_interfaces value is
reparsed with the remaining PCS interfaces.

Also a phylink resolve is triggered to handle the PCS removal.

A flag to make phylink resolve reconfigure the interface (even if it
didn't change) is also added. This is needed to handle the special
case when the current PCS used by phylink is removed and a major_config
is needed to propagae the configuration change. With this option
enabled we also force mac_config even if the PHY link is not up for
the in-band case.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/phy/phylink.c | 58 ++++++++++++++++++++++++++++++++++++++-
 include/linux/phylink.h   |  2 ++
 2 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 95d7e06dee56..2f28c4c83062 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -84,6 +84,7 @@ struct phylink {
 	bool link_failed;
 	bool suspend_link_up;
 	bool major_config_failed;
+	bool reconfig_interface;
 	bool mac_supports_eee_ops;
 	bool mac_supports_eee;
 	bool phy_enable_tx_lpi;
@@ -895,6 +896,55 @@ static void phylink_resolve_an_pause(struct phylink_link_state *state)
 	}
 }
 
+/**
+ * phylink_release_pcs - Removes a PCS from the phylink PCS available list
+ * @pcs: a pointer to the phylink_pcs struct to be released
+ *
+ * This function release a PCS from the phylink PCS available list if
+ * actually in use. It also refreshes the supported interfaces of the
+ * phylink instance by copying the supported interfaces from the phylink
+ * conf and merging the supported interfaces of the remaining available PCS
+ * in the list and trigger a resolve.
+ */
+void phylink_release_pcs(struct phylink_pcs *pcs)
+{
+	struct phylink *pl;
+
+	ASSERT_RTNL();
+
+	pl = pcs->phylink;
+	if (!pl)
+		return;
+
+	list_del(&pcs->list);
+	pcs->phylink = NULL;
+
+	/* Check if we are removing the PCS currently
+	 * in use by phylink. If this is the case,
+	 * force phylink resolve to reconfigure the interface
+	 * mode and set the phylink PCS to NULL.
+	 */
+	if (pl->pcs == pcs) {
+		mutex_lock(&pl->state_mutex);
+
+		pl->reconfig_interface = true;
+		pl->pcs = NULL;
+
+		mutex_unlock(&pl->state_mutex);
+	}
+
+	/* Refresh supported interfaces */
+	phy_interface_copy(pl->supported_interfaces,
+			   pl->config->supported_interfaces);
+	list_for_each_entry(pcs, &pl->pcs_list, list)
+		phy_interface_or(pl->supported_interfaces,
+				 pl->supported_interfaces,
+				 pcs->supported_interfaces);
+
+	phylink_run_resolve(pl);
+}
+EXPORT_SYMBOL_GPL(phylink_release_pcs);
+
 static unsigned int phylink_pcs_inband_caps(struct phylink_pcs *pcs,
 				    phy_interface_t interface)
 {
@@ -1688,6 +1738,10 @@ static void phylink_resolve(struct work_struct *w)
 		if (pl->phydev)
 			link_state.link &= pl->phy_state.link;
 
+		/* Force mac_config if we need to reconfig the interface */
+		if (pl->reconfig_interface)
+			mac_config = true;
+
 		/* Only update if the PHY link is up */
 		if (pl->phydev && pl->phy_state.link) {
 			/* If the interface has changed, force a link down
@@ -1722,7 +1776,8 @@ static void phylink_resolve(struct work_struct *w)
 		phylink_apply_manual_flow(pl, &link_state);
 
 	if (mac_config) {
-		if (link_state.interface != pl->link_config.interface) {
+		if (link_state.interface != pl->link_config.interface ||
+		    pl->reconfig_interface) {
 			/* The interface has changed, force the link down and
 			 * then reconfigure.
 			 */
@@ -1732,6 +1787,7 @@ static void phylink_resolve(struct work_struct *w)
 			}
 			phylink_major_config(pl, false, &link_state);
 			pl->link_config.interface = link_state.interface;
+			pl->reconfig_interface = false;
 		}
 	}
 
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index ef0b5a0729c8..c5496c063b6a 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -717,6 +717,8 @@ void phylink_disconnect_phy(struct phylink *);
 int phylink_set_fixed_link(struct phylink *,
 			   const struct phylink_link_state *);
 
+void phylink_release_pcs(struct phylink_pcs *pcs);
+
 void phylink_mac_change(struct phylink *, bool up);
 void phylink_pcs_change(struct phylink_pcs *, bool up);
 
-- 
2.48.1



From ansuelsmth at gmail.com  Sat May 10 03:23:25 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sat, 10 May 2025 12:23:25 +0200
Subject: [net-next PATCH v3 05/11] net: pcs: implement Firmware node support for PCS driver
In-Reply-To: <20250510102348.14134-1-ansuelsmth@gmail.com>
References: <20250510102348.14134-1-ansuelsmth@gmail.com>
Message-ID: <20250510102348.14134-6-ansuelsmth@gmail.com>

Implement the foundation of Firmware node support for PCS driver.

To support this, implement a simple Provider API where a PCS driver can
expose multiple PCS with an xlate .get function.

PCS driver will have to call fwnode_pcs_add_provider() and pass the
firmware node pointer and a xlate function to return the correct PCS for
the passed #pcs-cells.

This will register the PCS in a global list of providers so that
consumer can access it.

The consumer will then use fwnode_pcs_get() to get the actual PCS by
passing the firmware node pointer and the index for #pcs-cells.

For a simple implementation where #pcs-cells is 0 and the PCS driver
expose a single PCS, the xlate function fwnode_pcs_simple_get() is
provided.

For an advanced implementation a custom xlate function is required.

One removal the PCS driver should first delete itself from the provider
list using fwnode_pcs_del_provider() and then call phylink_release_pcs()
on every PCS the driver provides.

A generic function fwnode_phylink_pcs_parse() is provided for MAC driver
that will declare PCS in DT (or ACPI).
This function will parse "pcs-handle" property and fill the passed array
with the parsed PCS in availabel_pcs up to the passed num_pcs value.
It's also possible to pass NULL as array to only parse the PCS and
update the num_pcs value with the count of scanned PCS.

Co-developed-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/pcs/Kconfig          |   7 ++
 drivers/net/pcs/Makefile         |   1 +
 drivers/net/pcs/core.c           | 201 +++++++++++++++++++++++++++++++
 include/linux/pcs/pcs-provider.h |  41 +++++++
 include/linux/pcs/pcs.h          |  56 +++++++++
 5 files changed, 306 insertions(+)
 create mode 100644 drivers/net/pcs/core.c
 create mode 100644 include/linux/pcs/pcs-provider.h
 create mode 100644 include/linux/pcs/pcs.h

diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index f6aa437473de..2951aa2f4cda 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -5,6 +5,13 @@
 
 menu "PCS device drivers"
 
+config FWNODE_PCS
+	tristate
+	depends on (ACPI || OF)
+	depends on PHYLINK
+	help
+		Firmware node PCS accessors
+
 config PCS_XPCS
 	tristate "Synopsys DesignWare Ethernet XPCS"
 	select PHYLINK
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index 4f7920618b90..e29e57025728 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 # Makefile for Linux PCS drivers
 
+obj-$(CONFIG_FWNODE_PCS)	+= core.o
 pcs_xpcs-$(CONFIG_PCS_XPCS)	:= pcs-xpcs.o pcs-xpcs-plat.o \
 				   pcs-xpcs-nxp.o pcs-xpcs-wx.o
 
diff --git a/drivers/net/pcs/core.c b/drivers/net/pcs/core.c
new file mode 100644
index 000000000000..26d07a2edfce
--- /dev/null
+++ b/drivers/net/pcs/core.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <linux/mutex.h>
+#include <linux/property.h>
+#include <linux/phylink.h>
+#include <linux/pcs/pcs.h>
+#include <linux/pcs/pcs-provider.h>
+
+MODULE_DESCRIPTION("PCS library");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth at gmail.com>");
+MODULE_LICENSE("GPL");
+
+struct fwnode_pcs_provider {
+	struct list_head link;
+
+	struct fwnode_handle *fwnode;
+	struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+				   void *data);
+
+	void *data;
+};
+
+static LIST_HEAD(fwnode_pcs_providers);
+static DEFINE_MUTEX(fwnode_pcs_mutex);
+
+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
+					  void *data)
+{
+	return data;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_simple_get);
+
+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+			    struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+						       void *data),
+			    void *data)
+{
+	struct fwnode_pcs_provider *pp;
+
+	if (!fwnode)
+		return 0;
+
+	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
+	if (!pp)
+		return -ENOMEM;
+
+	pp->fwnode = fwnode_handle_get(fwnode);
+	pp->data = data;
+	pp->get = get;
+
+	mutex_lock(&fwnode_pcs_mutex);
+	list_add(&pp->link, &fwnode_pcs_providers);
+	mutex_unlock(&fwnode_pcs_mutex);
+	pr_debug("Added pcs provider from %pfwf\n", fwnode);
+
+	fwnode_dev_initialized(fwnode, true);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
+
+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode)
+{
+	struct fwnode_pcs_provider *pp;
+
+	if (!fwnode)
+		return;
+
+	mutex_lock(&fwnode_pcs_mutex);
+	list_for_each_entry(pp, &fwnode_pcs_providers, link) {
+		if (pp->fwnode == fwnode) {
+			list_del(&pp->link);
+			fwnode_dev_initialized(pp->fwnode, false);
+			fwnode_handle_put(pp->fwnode);
+			kfree(pp);
+			break;
+		}
+	}
+	mutex_unlock(&fwnode_pcs_mutex);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_del_provider);
+
+static int fwnode_parse_pcsspec(const struct fwnode_handle *fwnode, int index,
+				const char *name,
+				struct fwnode_reference_args *out_args)
+{
+	int ret;
+
+	if (!fwnode)
+		return -ENOENT;
+
+	if (name)
+		index = fwnode_property_match_string(fwnode, "pcs-names",
+						     name);
+
+	ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+						 "#pcs-cells",
+						 -1, index, out_args);
+	if (ret || (name && index < 0))
+		return ret;
+
+	return 0;
+}
+
+static struct phylink_pcs *
+fwnode_pcs_get_from_pcsspec(struct fwnode_reference_args *pcsspec)
+{
+	struct fwnode_pcs_provider *provider;
+	struct phylink_pcs *pcs = ERR_PTR(-EPROBE_DEFER);
+
+	if (!pcsspec)
+		return ERR_PTR(-EINVAL);
+
+	mutex_lock(&fwnode_pcs_mutex);
+	list_for_each_entry(provider, &fwnode_pcs_providers, link) {
+		if (provider->fwnode == pcsspec->fwnode) {
+			pcs = provider->get(pcsspec, provider->data);
+			if (!IS_ERR(pcs))
+				break;
+		}
+	}
+	mutex_unlock(&fwnode_pcs_mutex);
+
+	return pcs;
+}
+
+static struct phylink_pcs *__fwnode_pcs_get(struct fwnode_handle *fwnode,
+					    int index, const char *con_id)
+{
+	struct fwnode_reference_args pcsspec;
+	struct phylink_pcs *pcs;
+	int ret;
+
+	ret = fwnode_parse_pcsspec(fwnode, index, con_id, &pcsspec);
+	if (ret)
+		return ERR_PTR(ret);
+
+	pcs = fwnode_pcs_get_from_pcsspec(&pcsspec);
+	fwnode_handle_put(pcsspec.fwnode);
+
+	return pcs;
+}
+
+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, int index)
+{
+	return __fwnode_pcs_get(fwnode, index, NULL);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_get);
+
+static int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode,
+				    unsigned int *num_pcs)
+{
+	struct fwnode_reference_args out_args;
+	int index = 0;
+	int ret;
+
+	while (true) {
+		ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+							 "#pcs-cells",
+							 -1, index, &out_args);
+		/* We expect to reach an -ENOENT error while counting */
+		if (ret)
+			break;
+
+		fwnode_handle_put(out_args.fwnode);
+		index++;
+	}
+
+	/* Update num_pcs with parsed PCS */
+	*num_pcs = index;
+
+	/* Return error if we didn't found any PCS */
+	return index > 0 ? 0 : -ENOENT;
+}
+
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+			     struct phylink_pcs **available_pcs,
+			     unsigned int *num_pcs)
+{
+	int i;
+
+	if (!fwnode_property_present(fwnode, "pcs-handle"))
+		return -ENODEV;
+
+	/* With available_pcs NULL, only count the PCS */
+	if (!available_pcs)
+		return fwnode_phylink_pcs_count(fwnode, num_pcs);
+
+	for (i = 0; i < *num_pcs; i++) {
+		struct phylink_pcs *pcs;
+
+		pcs = fwnode_pcs_get(fwnode, i);
+		if (IS_ERR(pcs))
+			return PTR_ERR(pcs);
+
+		available_pcs[i] = pcs;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_parse);
diff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h
new file mode 100644
index 000000000000..2fcc1d696c97
--- /dev/null
+++ b/include/linux/pcs/pcs-provider.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_PROVIDER_H
+#define __LINUX_PCS_PROVIDER_H
+
+/**
+ * fwnode_pcs_simple_get - Simple xlate function to retrieve PCS
+ * @pcsspec: reference arguments
+ * @data: Context data (assumed assigned to the single PCS)
+ *
+ * Returns the PCS. (pointed by data)
+ */
+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
+					  void *data);
+
+/**
+ * fwnode_pcs_add_provider - Registers a new PCS provider
+ * @np: Firmware node
+ * @get: xlate function to retrieve the PCS
+ * @data: Context data
+ *
+ * Register and add a new PCS to the global providers list
+ * for the firmware node. A function to get the PCS from
+ * firmware node with the use fwnode reference arguments.
+ * To the get function is also passed the interface type
+ * requested for the PHY. PCS driver will use the passed
+ * interface to understand if the PCS can support it or not.
+ *
+ * Returns 0 on success or -ENOMEM on allocation failure.
+ */
+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+			    struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+						       void *data),
+			    void *data);
+
+/**
+ * fwnode_pcs_del_provider - Removes a PCS provider
+ * @fwnode: Firmware node
+ */
+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode);
+
+#endif /* __LINUX_PCS_PROVIDER_H */
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
new file mode 100644
index 000000000000..c7a4d63bcd6d
--- /dev/null
+++ b/include/linux/pcs/pcs.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_H
+#define __LINUX_PCS_H
+
+#include <linux/phylink.h>
+
+#if IS_ENABLED(CONFIG_FWNODE_PCS)
+/**
+ * fwnode_pcs_get - Retrieves a PCS from a firmware node
+ * @fwnode: firmware node
+ * @index: index fwnode PCS handle in firmware node
+ *
+ * Get a PCS from the firmware node at index.
+ *
+ * Returns a pointer to the phylink_pcs or a negative
+ * error pointer. Can return -EPROBE_DEFER if the PCS is not
+ * present in global providers list (either due to driver
+ * still needs to be probed or it failed to probe/removed)
+ */
+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
+				   int index);
+
+/**
+ * fwnode_phylink_pcs_parse - generic PCS parse for fwnode PCS provider
+ * @fwnode: firmware node
+ * @available_pcs: pointer to preallocated array of PCS
+ * @num_pcs: where to store count of parsed PCS
+ *
+ * Generic helper function to fill available_pcs array with PCS parsed
+ * from a "pcs-handle" fwnode property defined in firmware node up to
+ * passed num_pcs.
+ *
+ * If available_pcs is NULL, num_pcs is updated with the count of the
+ * parsed PCS.
+ *
+ * Returns 0 or a negative error.
+ */
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+			     struct phylink_pcs **available_pcs,
+			     unsigned int *num_pcs);
+#else
+static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
+						 int index)
+{
+	return ERR_PTR(-ENOENT);
+}
+
+static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+					   struct phylink_pcs **available_pcs,
+					   unsigned int *num_pcs)
+{
+	return -EOPNOTSUPP;
+}
+#endif
+
+#endif /* __LINUX_PCS_H */
-- 
2.48.1



From ansuelsmth at gmail.com  Sat May 10 03:23:26 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sat, 10 May 2025 12:23:26 +0200
Subject: [net-next PATCH v3 06/11] net: phylink: support late PCS provider attach
In-Reply-To: <20250510102348.14134-1-ansuelsmth@gmail.com>
References: <20250510102348.14134-1-ansuelsmth@gmail.com>
Message-ID: <20250510102348.14134-7-ansuelsmth@gmail.com>

Add support for late PCS provider attachment to a phylink instance.
This works by creating a global notifier for the PCS provider and
making each phylink instance that makes use of fwnode subscribe to
this notifier.

The PCS notifier will emit the event FWNODE_PCS_PROVIDER_ADD every time
a new PCS provider is added.

phylink will then react to this event and will call the new function
fwnode_phylink_pcs_get_from_fwnode() that will check if the PCS fwnode
provided by the event is present in the phy-handle property of the
phylink instance.

If a related PCS is found, then such PCS is added to the phylink
instance PCS list.

Then we link the PCS to the phylink instance if it's not disable and we
refresh the supported interfaces of the phylink instance.

Finally we check if we are in a major_config_failed scenario and trigger
an interface reconfiguration in the next phylink resolve.

In the example scenario where the link was previously torn down due to
removal of PCS, the link will be established again as the PCS came back
and is now available to phylink.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/pcs/core.c    | 40 ++++++++++++++++++++++++++++++
 drivers/net/phy/phylink.c | 52 +++++++++++++++++++++++++++++++++++++++
 include/linux/pcs/pcs.h   | 48 ++++++++++++++++++++++++++++++++++++
 3 files changed, 140 insertions(+)

diff --git a/drivers/net/pcs/core.c b/drivers/net/pcs/core.c
index 26d07a2edfce..409d06658167 100644
--- a/drivers/net/pcs/core.c
+++ b/drivers/net/pcs/core.c
@@ -22,6 +22,13 @@ struct fwnode_pcs_provider {
 
 static LIST_HEAD(fwnode_pcs_providers);
 static DEFINE_MUTEX(fwnode_pcs_mutex);
+static BLOCKING_NOTIFIER_HEAD(fwnode_pcs_notify_list);
+
+int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_register(&fwnode_pcs_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(register_fwnode_pcs_notifier);
 
 struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
 					  void *data)
@@ -55,6 +62,10 @@ int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
 
 	fwnode_dev_initialized(fwnode, true);
 
+	blocking_notifier_call_chain(&fwnode_pcs_notify_list,
+				     FWNODE_PCS_PROVIDER_ADD,
+				     fwnode);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
@@ -147,6 +158,35 @@ struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, int index)
 }
 EXPORT_SYMBOL_GPL(fwnode_pcs_get);
 
+struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+				   struct fwnode_handle *pcs_fwnode)
+{
+	struct fwnode_reference_args pcsspec;
+	int index = 0;
+	int ret;
+
+	/* Loop until we find a matching PCS node or
+	 * fwnode_parse_pcsspec() returns error
+	 * if we don't have any other PCS reference to check.
+	 */
+	while (true) {
+		ret = fwnode_parse_pcsspec(fwnode, index, NULL, &pcsspec);
+		if (ret)
+			return ERR_PTR(ret);
+
+		/* Exit loop if we found the matching PCS node */
+		if (pcsspec.fwnode == pcs_fwnode)
+			break;
+
+		/* Check the next PCS reference */
+		index++;
+	}
+
+	return fwnode_pcs_get(fwnode, index);
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_get_from_fwnode);
+
 static int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode,
 				    unsigned int *num_pcs)
 {
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 2f28c4c83062..1a4df0d24aa2 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -12,6 +12,7 @@
 #include <linux/netdevice.h>
 #include <linux/of.h>
 #include <linux/of_mdio.h>
+#include <linux/pcs/pcs.h>
 #include <linux/phy.h>
 #include <linux/phy_fixed.h>
 #include <linux/phylink.h>
@@ -61,6 +62,7 @@ struct phylink {
 
 	/* List of available PCS */
 	struct list_head pcs_list;
+	struct notifier_block fwnode_pcs_nb;
 
 	/* What interface are supported by the current link.
 	 * Can change on removal or addition of new PCS.
@@ -1909,6 +1911,51 @@ int phylink_set_fixed_link(struct phylink *pl,
 }
 EXPORT_SYMBOL_GPL(phylink_set_fixed_link);
 
+static int pcs_provider_notify(struct notifier_block *self,
+			       unsigned long val, void *data)
+{
+	struct phylink *pl = container_of(self, struct phylink, fwnode_pcs_nb);
+	struct fwnode_handle *pcs_fwnode = data;
+	struct phylink_pcs *pcs;
+
+	/* Check if the just added PCS provider is
+	 * in the phylink instance phy-handle property
+	 */
+	pcs = fwnode_phylink_pcs_get_from_fwnode(dev_fwnode(pl->config->dev),
+						 pcs_fwnode);
+	if (IS_ERR(pcs))
+		return NOTIFY_DONE;
+
+	/* Add the PCS */
+	rtnl_lock();
+
+	list_add(&pcs->list, &pl->pcs_list);
+
+	/* Link phylink if we are started */
+	if (!pl->phylink_disable_state)
+		pcs->phylink = pl;
+
+	/* Refresh supported interfaces */
+	phy_interface_copy(pl->supported_interfaces,
+			   pl->config->supported_interfaces);
+	list_for_each_entry(pcs, &pl->pcs_list, list)
+		phy_interface_or(pl->supported_interfaces,
+				 pl->supported_interfaces,
+				 pcs->supported_interfaces);
+
+	mutex_lock(&pl->state_mutex);
+	/* Force an interface reconfig if major config fail */
+	if (pl->major_config_failed)
+		pl->reconfig_interface = true;
+	mutex_unlock(&pl->state_mutex);
+
+	rtnl_unlock();
+
+	phylink_run_resolve(pl);
+
+	return NOTIFY_OK;
+}
+
 /**
  * phylink_create() - create a phylink instance
  * @config: a pointer to the target &struct phylink_config
@@ -1963,6 +2010,11 @@ struct phylink *phylink_create(struct phylink_config *config,
 				 pl->supported_interfaces,
 				 pcs->supported_interfaces);
 
+	if (!phy_interface_empty(config->pcs_interfaces)) {
+		pl->fwnode_pcs_nb.notifier_call = pcs_provider_notify;
+		register_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
+	}
+
 	pl->config = config;
 	if (config->type == PHYLINK_NETDEV) {
 		pl->netdev = to_net_dev(config->dev);
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
index c7a4d63bcd6d..480c155a3f03 100644
--- a/include/linux/pcs/pcs.h
+++ b/include/linux/pcs/pcs.h
@@ -4,7 +4,24 @@
 
 #include <linux/phylink.h>
 
+enum fwnode_pcs_notify_event {
+	FWNODE_PCS_PROVIDER_ADD,
+};
+
 #if IS_ENABLED(CONFIG_FWNODE_PCS)
+/**
+ * register_fwnode_pcs_notifier - Register a notifier block for fwnode
+ *				  PCS events
+ * @nb: pointer to the notifier block
+ *
+ * Registers a notifier block to the fwnode_pcs_notify_list blocking
+ * notifier chain. This allows phylink instance to subscribe for
+ * PCS provider events.
+ *
+ * Returns 0 or a negative error.
+ */
+int register_fwnode_pcs_notifier(struct notifier_block *nb);
+
 /**
  * fwnode_pcs_get - Retrieves a PCS from a firmware node
  * @fwnode: firmware node
@@ -20,6 +37,25 @@
 struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
 				   int index);
 
+/**
+ * fwnode_phylink_pcs_get_from_fwnode - Retrieves the PCS provided
+ *					by the firmware node from a
+ *					firmware node
+ * @fwnode: firmware node
+ * @pcs_fwnode: PCS firmware node
+ *
+ * Parse 'pcs-handle' in 'fwnode' and get the PCS that match
+ * 'pcs_fwnode' firmware node.
+ *
+ * Returns a pointer to the phylink_pcs or a negative
+ * error pointer. Can return -EPROBE_DEFER if the PCS is not
+ * present in global providers list (either due to driver
+ * still needs to be probed or it failed to probe/removed)
+ */
+struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+				   struct fwnode_handle *pcs_fwnode);
+
 /**
  * fwnode_phylink_pcs_parse - generic PCS parse for fwnode PCS provider
  * @fwnode: firmware node
@@ -39,12 +75,24 @@ int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
 			     struct phylink_pcs **available_pcs,
 			     unsigned int *num_pcs);
 #else
+static int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+	return -EOPNOTSUPP;
+}
+
 static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
 						 int index)
 {
 	return ERR_PTR(-ENOENT);
 }
 
+static struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+				   struct fwnode_handle *pcs_fwnode)
+{
+	return ERR_PTR(-ENOENT);
+}
+
 static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
 					   struct phylink_pcs **available_pcs,
 					   unsigned int *num_pcs)
-- 
2.48.1



From ansuelsmth at gmail.com  Sat May 10 03:23:27 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sat, 10 May 2025 12:23:27 +0200
Subject: [net-next PATCH v3 07/11] dt-bindings: net: ethernet-controller: permit to define multiple PCS
In-Reply-To: <20250510102348.14134-1-ansuelsmth@gmail.com>
References: <20250510102348.14134-1-ansuelsmth@gmail.com>
Message-ID: <20250510102348.14134-8-ansuelsmth@gmail.com>

Drop the limitation of a single PCS in pcs-handle property. Multiple PCS
can be defined for an ethrnet-controller node to support various PHY
interface mode type.

It's very common for SoCs to have a 2 or more dedicated PCS for Base-X
(for example SGMII, 1000base-x, 2500base-x, ...) and Base-R (for example
USXGMII,10base-r, ...) with the MAC selecting one of the other based on
the attached PHY.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 Documentation/devicetree/bindings/net/ethernet-controller.yaml | 2 --
 1 file changed, 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
index 7cbf11bbe99c..60605b34d242 100644
--- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
@@ -84,8 +84,6 @@ properties:
 
   pcs-handle:
     $ref: /schemas/types.yaml#/definitions/phandle-array
-    items:
-      maxItems: 1
     description:
       Specifies a reference to a node representing a PCS PHY device on a MDIO
       bus to link with an external PHY (phy-handle) if exists.
-- 
2.48.1



From ansuelsmth at gmail.com  Sat May 10 03:23:28 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sat, 10 May 2025 12:23:28 +0200
Subject: [net-next PATCH v3 08/11] net: phylink: add .pcs_link_down PCS OP
In-Reply-To: <20250510102348.14134-1-ansuelsmth@gmail.com>
References: <20250510102348.14134-1-ansuelsmth@gmail.com>
Message-ID: <20250510102348.14134-9-ansuelsmth@gmail.com>

Permit for PCS driver to define specific operation to torn down the link
between the MAC and the PCS.

This might be needed for some PCS that reset counter or require special
reset to correctly work if the link needs to be restored later.

On phylink_link_down() call, the additional phylink_pcs_link_down() will
be called before .mac_link_down to torn down the link.

PCS driver will need to define .pcs_link_down to make use of this.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/phy/phylink.c | 8 ++++++++
 include/linux/phylink.h   | 2 ++
 2 files changed, 10 insertions(+)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 1a4df0d24aa2..39cd15e30598 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -1009,6 +1009,12 @@ static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
 		pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex);
 }
 
+static void phylink_pcs_link_down(struct phylink_pcs *pcs)
+{
+	if (pcs && pcs->ops->pcs_link_down)
+		pcs->ops->pcs_link_down(pcs);
+}
+
 static void phylink_pcs_disable_eee(struct phylink_pcs *pcs)
 {
 	if (pcs && pcs->ops->pcs_disable_eee)
@@ -1686,6 +1692,8 @@ static void phylink_link_down(struct phylink *pl)
 
 	phylink_deactivate_lpi(pl);
 
+	phylink_pcs_link_down(pl->pcs);
+
 	pl->mac_ops->mac_link_down(pl->config, pl->act_link_an_mode,
 				   pl->cur_interface);
 	phylink_info(pl, "Link is Down\n");
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index c5496c063b6a..8b3d1dfb83a1 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -494,6 +494,7 @@ struct phylink_pcs {
  * @pcs_an_restart: restart 802.3z BaseX autonegotiation.
  * @pcs_link_up: program the PCS for the resolved link configuration
  *               (where necessary).
+ * @pcs_link_down: torn down link between MAC and PCS.
  * @pcs_disable_eee: optional notification to PCS that EEE has been disabled
  *		     at the MAC.
  * @pcs_enable_eee: optional notification to PCS that EEE will be enabled at
@@ -521,6 +522,7 @@ struct phylink_pcs_ops {
 	void (*pcs_an_restart)(struct phylink_pcs *pcs);
 	void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode,
 			    phy_interface_t interface, int speed, int duplex);
+	void (*pcs_link_down)(struct phylink_pcs *pcs);
 	void (*pcs_disable_eee)(struct phylink_pcs *pcs);
 	void (*pcs_enable_eee)(struct phylink_pcs *pcs);
 	int (*pcs_pre_init)(struct phylink_pcs *pcs);
-- 
2.48.1



From ansuelsmth at gmail.com  Sat May 10 03:23:29 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sat, 10 May 2025 12:23:29 +0200
Subject: [net-next PATCH v3 09/11] net: pcs: airoha: add PCS driver for Airoha SoC
In-Reply-To: <20250510102348.14134-1-ansuelsmth@gmail.com>
References: <20250510102348.14134-1-ansuelsmth@gmail.com>
Message-ID: <20250510102348.14134-10-ansuelsmth@gmail.com>

Add PCS driver for Airoha SoC for Ethernet Serdes and PCS and permit
usage of external PHY or connected SFP cage. Supported modes are
USXGMII, 10-BASER, 2500BASE-X, 1000BASE-X and SGMII.

The driver register as a PCS provider and supports poll mode to detect
PCS port state. While interrupt is supported by the HW, there are some
defect with the interrupt not fired on cable detach.

The PCS require complex calibration to correctly work and might require
multiple try until the signal detection module "lock" on the signal
level to correct work with the attached PHY.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/pcs/Kconfig      |    7 +
 drivers/net/pcs/Makefile     |    1 +
 drivers/net/pcs/pcs-airoha.c | 2920 ++++++++++++++++++++++++++++++++++
 3 files changed, 2928 insertions(+)
 create mode 100644 drivers/net/pcs/pcs-airoha.c

diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index 2951aa2f4cda..69d28cd1e624 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -12,6 +12,13 @@ config FWNODE_PCS
 	help
 		Firmware node PCS accessors
 
+config PCS_AIROHA
+	select FWNODE_PCS
+	tristate "Airoha PCS driver"
+	help
+	  This module provides helper to phylink for managing the Airoha
+	  PCS for SoC Ethernet Serdes and PCS.
+
 config PCS_XPCS
 	tristate "Synopsys DesignWare Ethernet XPCS"
 	select PHYLINK
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index e29e57025728..ae679c8aa571 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -2,6 +2,7 @@
 # Makefile for Linux PCS drivers
 
 obj-$(CONFIG_FWNODE_PCS)	+= core.o
+obj-$(CONFIG_PCS_AIROHA)	+= pcs-airoha.o
 pcs_xpcs-$(CONFIG_PCS_XPCS)	:= pcs-xpcs.o pcs-xpcs-plat.o \
 				   pcs-xpcs-nxp.o pcs-xpcs-wx.o
 
diff --git a/drivers/net/pcs/pcs-airoha.c b/drivers/net/pcs/pcs-airoha.c
new file mode 100644
index 000000000000..43c5c637be37
--- /dev/null
+++ b/drivers/net/pcs/pcs-airoha.c
@@ -0,0 +1,2920 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth at gmail.com>
+ */
+
+#include <linux/device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pcs/pcs-provider.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/rtnetlink.h>
+
+/* SCU*/
+#define AIROHA_SCU_WAN_CONF			0x70
+#define   AIROHA_SCU_WAN_SEL			GENMASK(7, 0)
+#define   AIROHA_SCU_WAN_SEL_SGMII		FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10)
+#define   AIROHA_SCU_WAN_SEL_HSGMII		FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11)
+#define   AIROHA_SCU_WAN_SEL_USXGMII		FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x12)
+#define AIROHA_SCU_SSR3				0x94
+#define   AIROHA_SCU_ETH_XSI_SEL		GENMASK(14, 13)
+#define   AIROHA_SCU_ETH_XSI_USXGMII		FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x1)
+#define   AIROHA_SCU_ETH_XSI_HSGMII		FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x2)
+#define AIROHA_SCU_SSTR				0x9c
+#define   AIROHA_SCU_PON_XSI_SEL		GENMASK(10, 9)
+#define   AIROHA_SCU_PON_XSI_USXGMII		FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x1)
+#define   AIROHA_SCU_PON_XSI_HSGMII		FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x2)
+
+/* XFI_MAC */
+#define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG		0x0
+#define   AIROHA_PCS_XFI_RX_FRAG_LEN		GENMASK(26, 22)
+#define   AIROHA_PCS_XFI_TX_FRAG_LEN		GENMASK(21, 17)
+#define   AIROHA_PCS_XFI_IPG_NUM		GENMASK(15, 10)
+#define   AIROHA_PCS_XFI_TX_FC_EN		BIT(5)
+#define   AIROHA_PCS_XFI_RX_FC_EN		BIT(4)
+#define   AIROHA_PCS_XFI_RXMPI_STOP		BIT(3)
+#define   AIROHA_PCS_XFI_RXMBI_STOP		BIT(2)
+#define   AIROHA_PCS_XFI_TXMPI_STOP		BIT(1)
+#define   AIROHA_PCS_XFI_TXMBI_STOP		BIT(0)
+#define AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST	0x10
+#define   AIROHA_PCS_XFI_MAC_LOGIC_RST		BIT(0)
+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRH		0x60
+#define   AIROHA_PCS_XFI_MAC_MACADDRH		GENMASK(15, 0)
+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRL		0x64
+#define   AIROHA_PCS_XFI_MAC_MACADDRL		GENMASK(31, 0)
+#define AIROHA_PCS_XFI_MAC_XFI_CNT_CLR		0x100
+#define   AIROHA_PCS_XFI_GLB_CNT_CLR		BIT(0)
+
+/* HSGMII_AN */
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0	0x0
+#define   AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE	BIT(12)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART	BIT(9)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1	0x4 /* BMSR */
+#define   AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4	0x10
+#define   AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5	0x14 /* LPA */
+#define   AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11	0x2c
+#define   AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER	GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13	0x34
+#define   AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0)
+#define     AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5)
+#define     AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4)
+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2)
+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2)
+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1)
+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0)
+#define     AIROHA_PCS_HSGMII_AN_SIDEBAND_EN	BIT(1)
+#define     AIROHA_PCS_HSGMII_AN_SGMII_EN	BIT(0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60
+#define   AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE	BIT(0)
+
+/* HSGMII_PCS */
+#define AIROHA_PCS_HSGMII_PCS_CTROL_1		0x0
+#define   AIROHA_PCS_TBI_10B_MODE		BIT(30)
+#define   AIROHA_PCS_SGMII_SEND_AN_ERR_EN	BIT(24)
+#define   AIROHA_PCS_REMOTE_FAULT_DIS		BIT(12)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_3		0x8
+#define   AIROHA_PCS_HSGMII_PCS_LINK_STSTIME	GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_6		0x14
+#define   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14)
+#define   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13)
+#define   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12)
+#define   AIROHA_PCS_HSGMII_PCS_MAC_MODE	BIT(8)
+#define   AIROHA_PCS_HSGMII_PCS_TX_ENABLE	BIT(4)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT	BIT(1)
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_EN	BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20
+#define   AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11)
+#define   AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT	BIT(4)
+#define   AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2)
+#define   AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT	BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0)
+#define ARIOHA_PCS_HSGMII_PCS_STATE_2		0x104
+#define   AIROHA_PCS_HSGMII_PCS_RX_SYNC		BIT(5)
+#define   AIROHA_PCS_HSGMII_PCS_AN_DONE		BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_INT_STATE		0x15c
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4)
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS	BIT(3)
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2)
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC	BIT(1)
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE	BIT(0)
+
+/* MULTI_SGMII */
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0	0x14
+#define   AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0	BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18
+#define   AIROHA_PCS_LINK_MODE_P0		GENMASK(5, 4)
+#define   AIROHA_PCS_LINK_MODE_P0_2_5G		FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x3)
+#define   AIROHA_PCS_LINK_MODE_P0_1G		FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x2)
+#define   AIROHA_PCS_LINK_MODE_P0_100M		FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x1)
+#define   AIROHA_PCS_LINK_MODE_P0_10M		FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x0)
+#define   AIROHA_PCS_FORCE_SPD_MODE_P0		BIT(2)
+#define   AIROHA_PCS_FORCE_LINKDOWN_P0		BIT(1)
+#define   AIROHA_PCS_FORCE_LINKUP_P0		BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0	0x100
+#define   AIROHA_PCS_HSGMII_XFI_SEL		BIT(28)
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL	0x14c
+#define   AIROHA_PCS_HSGMII_PCS_INT		BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15	0x43c
+#define   AIROHA_PCS_LINK_STS_P0		BIT(3)
+#define   AIROHA_PCS_SPEED_STS_P0		GENMASK(2, 0)
+#define   AIROHA_PCS_SPEED_STS_P0_1G		FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x2)
+#define   AIROHA_PCS_SPEED_STS_P0_100M		FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x1)
+#define   AIROHA_PCS_SPEED_STS_P0_10M		FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18	0x448
+#define   AIROHA_PCS_P0_SGMII_IS_10		BIT(2)
+#define   AIROHA_PCS_P0_SGMII_IS_100		BIT(1)
+#define   AIROHA_PCS_P0_SGMII_IS_1000		BIT(0)
+
+/* HSGMII_RATE_ADP */
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0	0x0
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27)
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26)
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN	BIT(4)
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN	BIT(0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1	0x4
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16)
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6	0x18
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8	0x20
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11	0x2c
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \
+	FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \
+	FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \
+	FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \
+	FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \
+	FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6)
+#define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0	0x100
+#define   AIROHA_PCS_HSGMII_P0_DIS_MII_MODE	BIT(31)
+
+/* USXGMII */
+#define AIROHA_PCS_USXGMII_PCS_CTROL_1		0x0
+#define   AIROHA_PCS_USXGMII_SPEED_SEL_H	BIT(13)
+#define AIROHA_PCS_USXGMII_PCS_STUS_1		0x30
+#define   AIROHA_PCS_USXGMII_RX_LINK_STUS	BIT(12)
+#define   AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3)
+#define   AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2)
+#define   AIROHA_PCS_USXGMII_PCS_BLK_LK		BIT(0)
+#define AIROHA_PCS_USGMII_VENDOR_DEFINE_116	0x22c
+#define AIROHA_PCS_USXGMII_PCS_CTRL_0		0x2c0
+#define   AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN	BIT(24)
+#define   AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN	BIT(16)
+#define   AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN	BIT(8)
+#define   AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_1		0x2c4
+#define   AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN	BIT(24)
+#define   AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN	BIT(16)
+#define   AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8)
+#define   AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_2		0x2c8
+#define   AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24)
+#define   AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN	BIT(16)
+#define   AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN	BIT(8)
+#define   AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_3		0x2cc
+#define   AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24)
+#define   AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16)
+#define   AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN	BIT(8)
+#define   AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_2	0x2d8
+#define   AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24)
+#define   AIROHA_PCS_USXGMII_R_TYPE_E_INT	BIT(16)
+#define   AIROHA_PCS_USXGMII_R_TYPE_T_INT	BIT(8)
+#define   AIROHA_PCS_USXGMII_R_TYPE_D_INT	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_3	0x2dc
+#define   AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24)
+#define   AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16)
+#define   AIROHA_PCS_USXGMII_LINK_UP_ST_INT	BIT(8)
+#define   AIROHA_PCS_USXGMII_HI_BER_ST_INT	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_4		0x2e0
+#define   AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_4	0x2e4
+#define   AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0	0x2f8
+#define   AIROHA_PCS_USXGMII_AN_RESTART		BIT(8)
+#define   AIROHA_PCS_USXGMII_AN_ENABLE		BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_0	0x310
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE	GENMASK(30, 28)
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x0)
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x1)
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x2)
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x3)
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x4)
+#define   AIROHA_PCS_USXGMII_PARTNER_ABILITY	GENMASK(15, 0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_2	0x318
+#define   AIROHA_PCS_USXGMII_PCS_AN_COMPLETE	BIT(24)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6	0x31c
+#define   AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7	0x320
+#define   AIROHA_PCS_USXGMII_RATE_UPDATE_MODE	BIT(12)
+#define   AIROHA_PCS_USXGMII_MODE		GENMASK(10, 8)
+#define   AIROHA_PCS_USXGMII_MODE_10000		FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x0)
+#define   AIROHA_PCS_USXGMII_MODE_5000		FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x1)
+#define   AIROHA_PCS_USXGMII_MODE_2500		FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x2)
+#define   AIROHA_PCS_USXGMII_MODE_1000		FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x3)
+#define   AIROHA_PCS_USXGMII_MODE_100		FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x4)
+
+/* PMA_PHYA */
+#define AIROHA_PCS_ANA_PXP_CMN_EN		0x0
+#define   AIROHA_PCS_ANA_CMN_EN			BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN	0x4
+#define   AIROHA_PCS_ANA_JCPLL_CHP_IOFST	GENMASK(29, 24)
+#define   AIROHA_PCS_ANA_JCPLL_CHP_IBIAS	GENMASK(21, 16)
+#define   AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN	BIT(8)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR		0x8
+#define   AIROHA_PCS_ANA_JCPLL_LPF_BWR		GENMASK(28, 24)
+#define   AIROHA_PCS_ANA_JCPLL_LPF_BP		GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_JCPLL_LPF_BC		GENMASK(12, 8)
+#define   AIROHA_PCS_ANA_JCPLL_LPF_BR		GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC	0xc
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_DIV	GENMASK(26, 24)
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_CODE	GENMASK(23, 16)
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_OPTION	BIT(8)
+#define   AIROHA_PCS_ANA_JCPLL_LPF_BWC		GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC	0x10
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_KS		GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_KF		GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_KFC	GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14
+#define   AIROHA_PCS_ANA_JCPLL_POSTDIV_D5	BIT(24)
+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE	GENMASK(1, 0)
+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x3)
+#define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY	0x1c
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS	GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x3)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_EN	BIT(16)
+#define   AIROHA_PCS_ANA_JCPLL_PLL_RSTB		BIT(8)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY		GENMASK(2, 0)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x3)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x4)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x5)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x6)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM	0x20
+#define   AIROHA_PCS_ANA_JCPLL_SDM_OUT		BIT(24)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD		GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x3)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_MODE		GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_IFM		BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN	0x24
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF	GENMASK(28, 24)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN	GENMASK(18, 16)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x3)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x4)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN	BIT(8)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_HREN		BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN	0x28
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW	GENMASK(26, 24)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x3)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x4)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x6)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN	BIT(16)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW	GENMASK(26, 24)
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV		0x2c
+#define   AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR	GENMASK(26, 24)
+#define   AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN	BIT(16)
+#define   AIROHA_PCS_ANA_JCPLL_VCO_CFIX		GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_JCPLL_VCODIV		GENMASK(1, 0)
+#define   AIROHA_PCS_ANA_JCPLL_VCODIV_1		FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_VCODIV_2		FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x1)
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR	0x30
+#define   AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI	BIT(17)
+#define   AIROHA_PCS_ANA_JCPLL_SSC_EN		BIT(16)
+#define   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8)
+#define   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3)
+#define   AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR	GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN	0x34
+#define   AIROHA_PCS_ANA_JCPLL_SSC_DELTA1	GENMASK(23, 8)
+#define   AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN	BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA	0x38
+#define   AIROHA_PCS_ANA_JCPLL_SSC_PERIOD	GENMASK(31, 16)
+#define   AIROHA_PCS_ANA_JCPLL_SSC_DELTA	GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H	0x48
+#define   AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF	GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_JCPLL_SPARE_L		GENMASK(15, 8)
+#define     AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5))
+#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS	0x50
+#define   AIROHA_PCS_ANA_TXPLL_LPF_BC		GENMASK(28, 24)
+#define   AIROHA_PCS_ANA_TXPLL_LPF_BR		GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_TXPLL_CHP_IOFST	GENMASK(13, 8)
+#define   AIROHA_PCS_ANA_TXPLL_CHP_IBIAS	GENMASK(5, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP		0x54
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_OPTION	BIT(24)
+#define   AIROHA_PCS_ANA_TXPLL_LPF_BWC		GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_TXPLL_LPF_BWR		GENMASK(12, 8)
+#define   AIROHA_PCS_ANA_TXPLL_LPF_BP		GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE	0x58
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_KF		GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_KFC	GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_DIV	GENMASK(10, 8)
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_CODE	GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS	0x5c
+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE	GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x3)
+#define   AIROHA_PCS_ANA_TXPLL_POSTDIV_EN	BIT(8)
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_KS		GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL	0x64
+#define   AIROHA_PCS_ANA_TXPLL_PLL_RSTB		BIT(24)
+#define   AIROHA_PCS_ANA_TXPLL_RST_DLY		GENMASK(18, 16)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV	GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x3)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL	BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN	0x68
+#define   AIROHA_PCS_ANA_TXPLL_SDM_MODE		GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_IFM		BIT(16)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS	GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x3)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_EN	BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD	0x6c
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN	BIT(24)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_HREN		BIT(16)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_OUT		BIT(8)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD		GENMASK(1, 0)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x3)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN	0x70
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF	GENMASK(12, 8)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN	GENMASK(2, 0)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x3)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x4)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN	0x74
+#define   AIROHA_PCS_ANA_TXPLL_VCO_CFIX		GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_TXPLL_VCODIV		GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_TXPLL_VCODIV_1		FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_VCODIV_2		FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_VCODIV_2		FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW	GENMASK(10, 8)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x3)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x4)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x6)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN	BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN	0x78
+#define   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27)
+#define   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24)
+#define   AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR	GENMASK(18, 16)
+#define   AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR	GENMASK(10, 8)
+#define   AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN	BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN		0x7c
+#define   AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN	BIT(16)
+#define   AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI	BIT(8)
+#define   AIROHA_PCS_ANA_TXPLL_SSC_EN		BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1	0x80
+#define   AIROHA_PCS_ANA_TXPLL_SSC_DELTA	GENMASK(31, 16)
+#define   AIROHA_PCS_ANA_TXPLL_SSC_DELTA1	GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD	0x84
+#define   AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT	GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_TXPLL_LDO_OUT		GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_TXPLL_SSC_PERIOD	GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF	0x94
+#define   AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF	GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN		0xc4
+#define   AIROHA_PCS_ANA_TX_DMEDGEGEN_EN	BIT(24)
+#define   AIROHA_PCS_ANA_TX_CKLDO_EN		BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL	0xcc
+#define    AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE	BIT(24)
+#define    AIROHA_PCS_ANA_RX_PHY_CK_SEL		BIT(16) /* 0: from PR 1: from DES */
+#define AIROHA_PCS_ANA_PXP_RX_REV_0		0xd4
+#define   AIROHA_PCS_ANA_RX_REV_1		GENMASK(31, 16)
+#define     AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define     AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define     AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define     AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK	GENMASK(19, 18)
+#define     AIROHA_PCS_ANA_REV_1_FECUR_PWDB	BIT(16)
+#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV		0xd8
+#define   AIROHA_PCS_ANA_RX_TDC_CK_SEL		BIT(24)
+#define   AIROHA_PCS_ANA_RX_PHYCK_RSTB		BIT(16)
+#define   AIROHA_PCS_ANA_RX_PHYCK_SEL		GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_RX_PHYCK_DIV		GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc
+#define   AIROHA_PCS_ANA_CDR_PD_EDGE_DIS	BIT(8)
+#define   AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV	BIT(0)
+#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO	0xe8
+#define   AIROHA_PCS_ANA_CDR_LPF_TOP_LIM	GENMASK(26, 8)
+#define   AIROHA_PCS_ANA_CDR_LPF_RATIO		GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE	0xf4
+#define   AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF	BIT(24)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC	0xf8
+#define   AIROHA_PCS_ANA_CDR_PR_KBAND_DIV	GENMASK(26, 24)
+#define   AIROHA_PCS_ANA_CDR_PR_BETA_SEL	GENMASK(19, 16)
+#define   AIROHA_PCS_ANA_CDR_PR_VCOADC_OS	GENMASK(11, 8)
+#define   AIROHA_PCS_ANA_CDR_PR_BETA_DAC	GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc
+#define   AIROHA_PCS_ANA_CDR_PR_FBKSEL		GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_CDR_PR_VREG_DAC_BAND	GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL	GENMASK(10, 8)
+#define   AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL	GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN	0x10c
+#define   AIROHA_PCS_ANA_RX_DAC_MON		GENMASK(28, 24)
+#define   AIROHA_PCS_ANA_CDR_PR_CAP_EN		BIT(19)
+#define   AIROHA_PCS_ANA_CDR_BUF_IN_SR		GENMASK(18, 16)
+#define   AIROHA_PCS_ANA_CDR_PR_XFICK_EN	BIT(2)
+#define   AIROHA_PCS_ANA_CDR_PR_MONDPI_EN	BIT(1)
+#define   AIROHA_PCS_ANA_CDR_PR_MONDPR_EN	BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE		0x110
+#define   AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL	GENMASK(25, 24)
+#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH	0x114
+#define   AIROHA_PCS_ANA_RX_FE_50OHMS_SEL	GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL	GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_RX_SIGDET_PEAK		GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN	0x118
+#define   AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN	BIT(24)
+#define   AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN	BIT(16)
+#define   AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN	BIT(8)
+#define   AIROHA_PCS_ANA_RX_FE_EQ_HZEN		BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB	0x11c
+#define   AIROHA_PCS_ANA_FE_VCM_GEN_PWDB	BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW	0x120
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE		GENMASK(17, 8)
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(0))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(1))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(2))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(3))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(4))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(5))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(6))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(7))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(8))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(9))
+#define AIROHA_PCS_ANA_PXP_AEQ_CFORCE		0x13c
+#define   AIROHA_PCS_ANA_AEQ_OFORCE		GENMASK(19, 8)
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_SAOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(0))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(1))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(2))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(3))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(4))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(5))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(6))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(7))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_VGA		FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(8))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_CTLE	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(9))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_ATT		FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(10))
+#define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144
+#define   AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ	BIT(24)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ	0x148
+#define   AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ	BIT(24)
+#define   AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ	BIT(16)
+#define   AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ	BIT(8)
+#define   AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ	BIT(0)
+
+/* PMA_PHYD */
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0	0x0
+#define   AIROHA_PCS_PMA_SW_LCPLL_EN		BIT(24)
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1	0x4
+#define   AIROHA_PCS_PMA_LCPLL_MAN_PWDB		BIT(0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2	0x88
+#define   AIROHA_PCS_PMA_DATA_SHIFT		BIT(8)
+#define   AIROHA_PCS_PMA_EYECNT_FAST		BIT(0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0	0x8c
+#define   AIROHA_PCS_PMA_RX_OS_START		GENMASK(23, 8)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT		GENMASK(2, 0)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x0)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x1)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x2)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x3)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x4)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x5)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x6)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x7)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1	0x90
+#define   AIROHA_PCS_PMA_RX_PICAL_END		GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_RX_PICAL_START		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2	0x94
+#define   AIROHA_PCS_PMA_RX_PDOS_END		GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_RX_PDOS_START		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3	0x98
+#define   AIROHA_PCS_PMA_RX_FEOS_END		GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_RX_FEOS_START		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4	0x9c
+#define   AIROHA_PCS_PMA_RX_SDCAL_END		GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_RX_SDCAL_START		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5	0x100
+#define   AIROHA_PCS_PMA_RX_RDY			GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_RX_BLWC_RDY_EN		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6	0x104
+#define   AIROHA_PCS_PMA_RX_OS_END		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c
+#define   AIROHA_PCS_PMA_DISB_RX_RDY		BIT(24)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114
+#define   AIROHA_PCS_PMA_FORCE_RX_RDY		BIT(24)
+#define AIROHA_PCS_PMA_PHY_EQ_CTRL_3		0x120
+#define   AIROHA_PCS_PMA_EQ_DEBUG_SEL		GENMASK(17, 16)
+#define   AIROHA_PCS_PMA_FOM_NUM_ORDER		GENMASK(12, 8)
+#define   AIROHA_PCS_PMA_A_SEL			GENMASK(1, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1		0x14c
+#define   AIROHA_PCS_PMA_UNLOCK_CYCLECNT	GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_LOCK_CYCLECNT		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2		0x150
+#define   AIROHA_PCS_PMA_LOCK_TARGET_END	GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_LOCK_TARGET_BEG	GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3		0x154
+#define   AIROHA_PCS_PMA_UNLOCK_TARGET_END	GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_UNLOCK_TARGET_BEG	GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4		0x158
+#define   AIROHA_PCS_PMA_LOCK_UNLOCKTH		GENMASK(15, 12)
+#define   AIROHA_PCS_PMA_LOCK_LOCKTH		GENMASK(11, 8)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN	GENMASK(2, 0)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x0)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x1)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT	FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL	FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7)
+#define AIROHA_PCS_PMA_SS_RX_SIGDET_1		0x16c
+#define   AIROHA_PCS_PMA_SIGDET_EN		BIT(0)
+#define AIROHA_PCS_PMA_RX_FLL_1			0x174
+#define   AIROHA_PCS_PMA_LPATH_IDAC		GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_2			0x178
+#define   AIROHA_PCS_PMA_CK_RATE		GENMASK(18, 16)
+#define   AIROHA_PCS_PMA_CK_RATE_20		FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0)
+#define   AIROHA_PCS_PMA_CK_RATE_10		FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1)
+#define   AIROHA_PCS_PMA_CK_RATE_5		FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2)
+#define AIROHA_PCS_PMA_RX_FLL_5			0x184
+#define   AIROHA_PCS_PMA_FLL_IDAC_MIN		GENMASK(26, 16)
+#define   AIROHA_PCS_PMA_FLL_IDAC_MAX		GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_B		        0x19c
+#define   AIROHA_PCS_PMA_LOAD_EN		BIT(0)
+#define AIROHA_PCS_PMA_RX_RESET_1		0x208
+#define   AIROHA_PCS_PMA_SIGDET_RST_B		BIT(8)
+#define AIROHA_PCS_PMA_TX_RST_B			0x260
+#define   AIROHA_PCS_PMA_TXCALIB_RST_B		BIT(8)
+#define   AIROHA_PCS_PMA_TX_TOP_RST_B		BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_4		0x320
+#define   AIROHA_PCS_PMA_DISB_BLWC_OFFSET	BIT(24)
+#define AIROHA_PCS_PMA_RX_FORCE_MODE_9		0x330
+#define   AIROHA_PCS_PMA_FORCE_FBCK_LOCK	BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_8		0x33c
+#define   AIROHA_PCS_PMA_DISB_FBCK_LOCK		BIT(0)
+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0		0x38c
+#define   AIROHA_PCS_PMA_RX_SYS_EN_SEL		GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0	0x390
+#define   AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT	GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1	0x394
+#define   AIROHA_PCS_PMA_PLL_LOCK_TARGET_END	GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG	GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3	0x39c
+#define   AIROHA_PCS_PMA_PLL_LOCK_LOCKTH	GENMASK(11, 8)
+#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL		0x48c
+#define   AIROHA_PCS_PMA_DISB_LEQ		BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0	0x34c
+#define   AIROHA_PCS_PMA_XPON_CDR_PR_PD_PWDB	BIT(24)
+#define   AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB	BIT(16)
+#define   AIROHA_PCS_PMA_XPON_CDR_PW_PWDB	BIT(8)
+#define   AIROHA_PCS_PMA_XPON_RX_FE_PWDB	BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1	0x350
+#define   AIROHA_PCS_PMA_RX_SIDGET_PWDB		BIT(0)
+#define AIROHA_PCS_PMA_DIG_RESERVE_0		0x360
+#define AIROHA_PCS_PMA_DIG_RO_RESERVE_2		0x380
+#define AIROHA_PCS_PMA_XPON_RX_RESERVED_1	0x374
+#define   AIROHA_PCS_PMA_XPON_RX_RATE_CTRL	GENMASK(1, 0)
+#define AIROHA_PCS_PMA_SW_RST_SET		0x460
+#define   AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N	BIT(11)
+#define   AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N	BIT(10)
+#define   AIROHA_PCS_PMA_SW_HSG_RXPCS_BIST_RST_N BIT(9)
+#define   AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N	BIT(8)
+#define   AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N	BIT(7)
+#define   AIROHA_PCS_PMA_SW_TX_FIFO_RST_N	BIT(6)
+#define   AIROHA_PCS_PMA_SW_REF_RST_N		BIT(5)
+#define   AIROHA_PCS_PMA_SW_ALLPCS_RST_N	BIT(4)
+#define   AIROHA_PCS_PMA_SW_PMA_RST_N		BIT(3)
+#define   AIROHA_PCS_PMA_SW_TX_RST_N		BIT(2)
+#define   AIROHA_PCS_PMA_SW_RX_RST_N		BIT(1)
+#define   AIROHA_PCS_PMA_SW_RX_FIFO_RST_N	BIT(0)
+#define AIROHA_PCS_PMA_XPON_INT_EN_3		0x474
+#define   AIROHA_PCS_PMA_RX_SIGDET_INT_EN	BIT(16)
+#define AIROHA_PCS_PMA_XPON_INT_STA_3		0x47c
+#define   AIROHA_PCS_PMA_RX_SIGDET_INT		BIT(16)
+#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL		0x48c
+#define   AIROHA_PCS_PMA_DISB_LEQ		BIT(0)
+#define AIROHA_PCS_PMA_RX_FREQDET		0x530
+#define   AIROHA_PCS_PMA_FL_OUT			GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_FBCK_LOCK		BIT(0)
+#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL	0x580
+#define   AIROHA_PCS_PMA_PON_TX_RATE_CTRL	GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN	0x768
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PEAKING_CTRL BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_PEAKING_CTRL GENMASK(19, 16)
+#define AIROHA_PCS_PMA_PXP_AEQ_SPEED		0x76c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL	BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_OSR_SEL	GENMASK(17, 16)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C0B		0x778
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1	GENMASK(20, 16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B	GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_TERM_SEL		0x77c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL	GENMASK(2, 0)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C1		0x780
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2	GENMASK(20, 16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1	GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL		0x784
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC		0x794
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC	GENMASK(10, 0)
+#define     AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8)
+#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW	0x798
+#define   AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW	GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_VOS		0x79c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS	BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_FE_VOS	GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW	0x800
+#define   AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW	GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_AEQ_BYPASS		0x80c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON	BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON	BIT(16)
+#define AIROHA_PCS_PMA_PXP_AEQ_RSTB		0x814
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL	BIT(16)
+#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA	0x818
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB	BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB		0x81c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN	0x820
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB	0x824
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB	BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN	0x828
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN	BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN	BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B	0x84c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B	 BIT(0)
+#define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN	0x854
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN	BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN	BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN		0x874
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL	BIT(16)
+#define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL		0x88c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_PWDB		0x894
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN	BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB	 BIT(0)
+
+#define AIROHA_PCS_MAX_CALIBRATION_TRY		50
+#define AIROHA_PCS_MAX_NUM_RSTS			2
+
+enum xfi_port_type {
+	AIROHA_PCS_ETH,
+	AIROHA_PCS_PON,
+};
+
+struct airoha_pcs_match_data {
+	enum xfi_port_type port_type;
+};
+
+struct airoha_pcs_priv {
+	struct device *dev;
+	const struct airoha_pcs_match_data *data;
+	phy_interface_t interface;
+
+	struct regmap *scu;
+
+	struct regmap *xfi_mac;
+	struct regmap *hsgmii_an;
+	struct regmap *hsgmii_pcs;
+	struct regmap *hsgmii_rate_adp;
+	struct regmap *multi_sgmii;
+	struct regmap *usxgmii_pcs;
+
+	struct regmap *xfi_pma;
+	struct regmap *xfi_ana;
+
+	struct reset_control_bulk_data rsts[AIROHA_PCS_MAX_NUM_RSTS];
+
+	struct phylink_pcs pcs;
+};
+
+static struct airoha_pcs_priv *phylink_pcs_to_airoha_pcs_port(struct phylink_pcs *pcs)
+{
+	return container_of(pcs, struct airoha_pcs_priv, pcs);
+}
+
+static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv,
+				     phy_interface_t interface)
+{
+	u32 xsi_sel;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		xsi_sel = AIROHA_SCU_ETH_XSI_HSGMII;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+	default:
+		xsi_sel = AIROHA_SCU_ETH_XSI_USXGMII;
+	}
+
+	regmap_update_bits(priv->scu, AIROHA_SCU_SSR3,
+			   AIROHA_SCU_ETH_XSI_SEL,
+			   xsi_sel);
+}
+
+static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv,
+				     phy_interface_t interface)
+{
+	u32 xsi_sel, wan_sel;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+		wan_sel = AIROHA_SCU_WAN_SEL_SGMII;
+		xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX:
+		wan_sel = AIROHA_SCU_WAN_SEL_HSGMII;
+		xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+	default:
+		wan_sel = AIROHA_SCU_WAN_SEL_USXGMII;
+		xsi_sel = AIROHA_SCU_PON_XSI_USXGMII;
+	}
+
+	regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+			   AIROHA_SCU_PON_XSI_SEL,
+			   xsi_sel);
+
+	regmap_update_bits(priv->scu, AIROHA_SCU_WAN_CONF,
+			   AIROHA_SCU_WAN_SEL,
+			   wan_sel);
+}
+
+static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv,
+				phy_interface_t interface)
+{
+	int ret;
+
+	switch (priv->data->port_type) {
+	case AIROHA_PCS_ETH:
+		airoha_pcs_setup_scu_eth(priv, interface);
+		break;
+	case AIROHA_PCS_PON:
+		airoha_pcs_setup_scu_pon(priv, interface);
+		break;
+	}
+
+	ret = reset_control_bulk_assert(ARRAY_SIZE(priv->rsts),
+					priv->rsts);
+	if (ret)
+		return ret;
+
+	ret = reset_control_bulk_deassert(ARRAY_SIZE(priv->rsts),
+					  priv->rsts);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv)
+{
+	regmap_set_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+			AIROHA_PCS_HSGMII_XFI_SEL);
+
+	/* Disable Hibernation */
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1,
+			  AIROHA_PCS_USXGMII_SPEED_SEL_H);
+
+	/* FIXME: wait Airoha */
+	/* Avoid PCS sending garbage to MAC in some HW revision (E0) */
+	regmap_write(priv->usxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0);
+}
+
+static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv)
+{
+	regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+			  AIROHA_PCS_HSGMII_XFI_SEL);
+
+	regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+			AIROHA_PCS_TBI_10B_MODE);
+}
+
+static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv)
+{
+	regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+			  AIROHA_PCS_HSGMII_XFI_SEL);
+
+	regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+			AIROHA_PCS_TBI_10B_MODE);
+
+	regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6,
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L,
+			   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, 0x07070707));
+
+	regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8,
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C,
+			   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, 0xff));
+}
+
+static void airoha_pcs_init(struct airoha_pcs_priv *priv,
+			    phy_interface_t interface)
+{
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+		airoha_pcs_init_sgmii(priv);
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX:
+		airoha_pcs_init_hsgmii(priv);
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		airoha_pcs_init_usxgmii(priv);
+		break;
+	default:
+		return;
+	}
+}
+
+static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv)
+{
+	/* Disable every interrupt */
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+			  AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT |
+			  AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT |
+			  AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT |
+			  AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT |
+			  AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT);
+
+	/* Clear interrupt */
+	regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+			AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+			AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+			AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+			AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+			AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+			  AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+			  AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+			  AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+			  AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+			  AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+}
+
+static void airoha_pcs_interrupt_init_usxgmii(struct airoha_pcs_priv *priv)
+{
+	/* Disable every Interrupt */
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_0,
+			  AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN |
+			  AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN |
+			  AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN |
+			  AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN);
+
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_1,
+			  AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN |
+			  AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN |
+			  AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN |
+			  AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN);
+
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_2,
+			  AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN |
+			  AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN |
+			  AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN |
+			  AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN);
+
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_3,
+			  AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN |
+			  AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN |
+			  AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN |
+			  AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN);
+
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_4,
+			  AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN);
+
+	/* Clear any pending interrupt */
+	regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_2,
+			AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT |
+			AIROHA_PCS_USXGMII_R_TYPE_E_INT |
+			AIROHA_PCS_USXGMII_R_TYPE_T_INT |
+			AIROHA_PCS_USXGMII_R_TYPE_D_INT);
+
+	regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_3,
+			AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT |
+			AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT |
+			AIROHA_PCS_USXGMII_LINK_UP_ST_INT |
+			AIROHA_PCS_USXGMII_HI_BER_ST_INT);
+
+	regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_4,
+			AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT);
+
+	/* Interrupt saddly seems to be not weel supported for Link Down.
+	 * PCS Poll is a must to correctly read and react on Cable Deatch
+	 * as only cable attach interrupt are fired and Link Down interrupt
+	 * are fired only in special case like AN restart.
+	 */
+}
+
+static void airoha_pcs_interrupt_init(struct airoha_pcs_priv *priv,
+				      phy_interface_t interface)
+{
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		return airoha_pcs_interrupt_init_sgmii(priv);
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		return airoha_pcs_interrupt_init_usxgmii(priv);
+	default:
+		return;
+	}
+}
+
+static void airoha_pcs_jcpll_bringup(struct airoha_pcs_priv *priv,
+				     phy_interface_t interface)
+{
+	u32 kband_vref;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		kband_vref = 0x10;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		kband_vref = 0xf;
+		break;
+	default:
+		return;
+	}
+
+	/* Setup LDO */
+	usleep_range(200, 300);
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H,
+			AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO);
+
+	/* Setup RSTB */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,
+			   AIROHA_PCS_ANA_JCPLL_RST_DLY,
+			   AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200);
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,
+			AIROHA_PCS_ANA_JCPLL_PLL_RSTB);
+
+	/* Enable PLL force selection and Force Disable */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN);
+
+	/* Setup SDM */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,
+			   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS |
+			   AIROHA_PCS_ANA_JCPLL_SDM_DI_EN,
+			   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM,
+			   AIROHA_PCS_ANA_JCPLL_SDM_OUT |
+			   AIROHA_PCS_ANA_JCPLL_SDM_ORD |
+			   AIROHA_PCS_ANA_JCPLL_SDM_MODE |
+			   AIROHA_PCS_ANA_JCPLL_SDM_IFM,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0) |
+			   AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_MODE, 0x0));
+
+	regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN,
+			  AIROHA_PCS_ANA_JCPLL_SDM_HREN);
+
+	/* Setup SSC */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA,
+			   AIROHA_PCS_ANA_JCPLL_SSC_PERIOD |
+			   AIROHA_PCS_ANA_JCPLL_SSC_DELTA,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_PERIOD, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA, 0x0));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN,
+			   AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 |
+			   AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA1, 0x0));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR,
+			   AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI |
+			   AIROHA_PCS_ANA_JCPLL_SSC_EN |
+			   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L |
+			   AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x0));
+
+	/* Setup LPF */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN,
+			   AIROHA_PCS_ANA_JCPLL_CHP_IOFST |
+			   AIROHA_PCS_ANA_JCPLL_CHP_IBIAS |
+			   AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IOFST, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IBIAS, 0x18));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR,
+			   AIROHA_PCS_ANA_JCPLL_LPF_BWR |
+			   AIROHA_PCS_ANA_JCPLL_LPF_BP |
+			   AIROHA_PCS_ANA_JCPLL_LPF_BC |
+			   AIROHA_PCS_ANA_JCPLL_LPF_BR,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWR, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BP, 0x10) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BC, 0x1f) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BR, BIT(3) | BIT(1)));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC,
+			   AIROHA_PCS_ANA_JCPLL_LPF_BWC,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWC, 0x0));
+
+	/* Setup VCO */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV,
+			   AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR |
+			   AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN |
+			   AIROHA_PCS_ANA_JCPLL_VCO_CFIX,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR, 0x4) |
+			   AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_CFIX, 0x1));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR,
+			   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L |
+			   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H |
+			   AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H, 0x3) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x3));
+
+	/* Setup PCW */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW,
+			   AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW,
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, 0x25800000));
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW);
+
+	/* Setup DIV */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE,
+			   AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 |
+			   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE,
+			   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV,
+			   AIROHA_PCS_ANA_JCPLL_VCODIV,
+			   AIROHA_PCS_ANA_JCPLL_VCODIV_1);
+
+	/* Setup KBand */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC,
+			   AIROHA_PCS_ANA_JCPLL_KBAND_KS |
+			   AIROHA_PCS_ANA_JCPLL_KBAND_KF |
+			   AIROHA_PCS_ANA_JCPLL_KBAND_KFC,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KS, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KF, 0x3) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KFC, 0x0));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC,
+			   AIROHA_PCS_ANA_JCPLL_KBAND_DIV |
+			   AIROHA_PCS_ANA_JCPLL_KBAND_CODE |
+			   AIROHA_PCS_ANA_JCPLL_KBAND_OPTION,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_DIV, 0x2) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_CODE, 0xe4));
+
+	/* Setup TCL */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H,
+			   AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF, kband_vref));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN,
+			   AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF |
+			   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN |
+			   AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF, 0x5) |
+			   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 |
+			   AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN,
+			   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW |
+			   AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN,
+			   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 |
+			   AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN);
+
+	/* Enable PLL */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+			AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN);
+
+	/* Enale PLL Output */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN |
+			AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN);
+}
+
+static void airoha_pcs_txpll_bringup(struct airoha_pcs_priv *priv,
+				     phy_interface_t interface)
+{
+	u32 lpf_chp_ibias, lpf_bp, lpf_bwr, lpf_bwc;
+	u32 vco_cfix;
+	u32 pcw;
+	u32 tcl_amp_vref;
+	bool sdm_hren;
+	bool vcodiv;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+		lpf_chp_ibias = 0xf;
+		lpf_bp = BIT(1);
+		lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+		lpf_bwc = BIT(4) | BIT(3);
+		vco_cfix = BIT(1) | BIT(0);
+		pcw = BIT(27);
+		tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+		vcodiv = false;
+		sdm_hren = false;
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX:
+		lpf_chp_ibias = 0xa;
+		lpf_bp = BIT(2) | BIT(0);
+		lpf_bwr = 0;
+		lpf_bwc = 0;
+		vco_cfix = 0;
+		pcw = BIT(27) | BIT(25);
+		tcl_amp_vref = BIT(3) | BIT(2) | BIT(0);
+		vcodiv = true;
+		sdm_hren = false;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		lpf_chp_ibias = 0xf;
+		lpf_bp = BIT(1);
+		lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+		lpf_bwc = BIT(4) | BIT(3);
+		vco_cfix = BIT(0);
+		pcw = BIT(27) | BIT(22);
+		tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+		vcodiv = false;
+		sdm_hren = true;
+		break;
+	default:
+		return;
+	}
+
+	/* Setup VCO LDO Output */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD,
+			   AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT |
+			   AIROHA_PCS_ANA_TXPLL_LDO_OUT,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT, 0x1) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_OUT, 0x1));
+
+	/* Setup RSTB */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL,
+			   AIROHA_PCS_ANA_TXPLL_PLL_RSTB |
+			   AIROHA_PCS_ANA_TXPLL_RST_DLY |
+			   AIROHA_PCS_ANA_TXPLL_REFIN_DIV |
+			   AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL,
+			   AIROHA_PCS_ANA_TXPLL_PLL_RSTB |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_RST_DLY, 0x4) |
+			   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 |
+			   AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL);
+
+	/* Enable PLL force selection and Force Disable */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN);
+
+	/* Setup SDM */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN,
+			   AIROHA_PCS_ANA_TXPLL_SDM_MODE |
+			   AIROHA_PCS_ANA_TXPLL_SDM_IFM |
+			   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS |
+			   AIROHA_PCS_ANA_TXPLL_SDM_DI_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SDM_MODE, 0) |
+			   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD,
+			   AIROHA_PCS_ANA_TXPLL_SDM_HREN |
+			   AIROHA_PCS_ANA_TXPLL_SDM_OUT |
+			   AIROHA_PCS_ANA_TXPLL_SDM_ORD,
+			   (sdm_hren ? AIROHA_PCS_ANA_TXPLL_SDM_HREN : 0) |
+			   AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM);
+
+	/* Setup SSC */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1,
+			   AIROHA_PCS_ANA_TXPLL_SSC_DELTA |
+			   AIROHA_PCS_ANA_TXPLL_SSC_DELTA1,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA1, 0x0));
+
+	regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN,
+			  AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN |
+			  AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI |
+			  AIROHA_PCS_ANA_TXPLL_SSC_EN);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD,
+			   AIROHA_PCS_ANA_TXPLL_SSC_PERIOD,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_PERIOD, 0x0));
+
+	/* Setup LPF */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS,
+			   AIROHA_PCS_ANA_TXPLL_LPF_BC |
+			   AIROHA_PCS_ANA_TXPLL_LPF_BR |
+			   AIROHA_PCS_ANA_TXPLL_CHP_IOFST |
+			   AIROHA_PCS_ANA_TXPLL_CHP_IBIAS,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BC, 0x1f) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BR, 0x5) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IOFST, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IBIAS, lpf_chp_ibias));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,
+			   AIROHA_PCS_ANA_TXPLL_LPF_BWC |
+			   AIROHA_PCS_ANA_TXPLL_LPF_BWR |
+			   AIROHA_PCS_ANA_TXPLL_LPF_BP,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWC, lpf_bwc) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWR, lpf_bwr) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BP, lpf_bp));
+
+	/* Setup VCO */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
+			   AIROHA_PCS_ANA_TXPLL_VCO_CFIX,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_CFIX, vco_cfix));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN,
+			   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L |
+			   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H |
+			   AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR |
+			   AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR |
+			   AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H, 0x4) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR, 0x4) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR, 0x7) |
+			   AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN);
+
+	/* Setup PCW */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW,
+			   AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW);
+
+	/* Setup KBand */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE,
+			   AIROHA_PCS_ANA_TXPLL_KBAND_KF |
+			   AIROHA_PCS_ANA_TXPLL_KBAND_KFC |
+			   AIROHA_PCS_ANA_TXPLL_KBAND_DIV |
+			   AIROHA_PCS_ANA_TXPLL_KBAND_CODE,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KF, 0x3) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KFC, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_DIV, 0x4) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_CODE, 0xe4));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS,
+			   AIROHA_PCS_ANA_TXPLL_KBAND_KS,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KS, 0x1));
+
+	regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,
+			  AIROHA_PCS_ANA_TXPLL_KBAND_OPTION);
+
+	/* Setup DIV */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS,
+			   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE |
+			   AIROHA_PCS_ANA_TXPLL_POSTDIV_EN,
+			   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
+			   AIROHA_PCS_ANA_TXPLL_VCODIV,
+			   vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 :
+				    AIROHA_PCS_ANA_TXPLL_VCODIV_1);
+
+	/* Setup TCL */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF,
+			   AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF, 0xf));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN,
+			   AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF |
+			   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF, tcl_amp_vref) |
+			   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
+			   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW |
+			   AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN,
+			   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 |
+			   AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN);
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD,
+			AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN);
+
+	/* Enable PLL */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+			AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN);
+
+	/* Enale PLL Output */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN |
+			AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN);
+}
+
+static void airoha_pcs_pll_bringup(struct airoha_pcs_priv *priv,
+				   phy_interface_t interface)
+{
+	airoha_pcs_jcpll_bringup(priv, interface);
+
+	usleep_range(200, 300);
+
+	airoha_pcs_txpll_bringup(priv, interface);
+
+	usleep_range(200, 300);
+}
+
+static void airoha_pcs_tx_bringup(struct airoha_pcs_priv *priv,
+				  phy_interface_t interface)
+{
+	u32 tx_rate_ctrl;
+	u32 ckin_divisor;
+	u32 fir_cn1, fir_c0b, fir_c1;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+		ckin_divisor = BIT(1);
+		tx_rate_ctrl = BIT(0);
+		fir_cn1 = 0;
+		fir_c0b = 12;
+		fir_c1 = 0;
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX:
+		ckin_divisor = BIT(2);
+		tx_rate_ctrl = BIT(0);
+		fir_cn1 = 0;
+		fir_c0b = 11;
+		fir_c1 = 1;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		ckin_divisor = BIT(2) | BIT(0);
+		tx_rate_ctrl = BIT(1);
+		fir_cn1 = 1;
+		fir_c0b = 1;
+		fir_c1 = 11;
+		break;
+	default:
+		return;
+	}
+
+	/* Set TX rate ctrl */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL,
+			   AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+			   FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+				      tx_rate_ctrl));
+
+	/* Setup TX Config */
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TX_CKLDO_EN,
+			AIROHA_PCS_ANA_TX_DMEDGEGEN_EN |
+			AIROHA_PCS_ANA_TX_CKLDO_EN);
+
+	udelay(1);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL |
+			AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL);
+
+	/* FIXME: Ask Airoha TX term is OK to reset? */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR,
+				      ckin_divisor) |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL, 0x0));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+				      tx_rate_ctrl));
+
+	/* Setup TX FIR Load Parameters (Reference 660mV) */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1));
+
+	/* Reset TX Bar */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_TX_RST_B,
+			AIROHA_PCS_PMA_TXCALIB_RST_B | AIROHA_PCS_PMA_TX_TOP_RST_B);
+}
+
+static void airoha_pcs_rx_bringup(struct airoha_pcs_priv *priv,
+				  phy_interface_t interface)
+{
+	u32 rx_rate_ctrl;
+	u32 osr;
+	u32 pr_cdr_beta_dac;
+	u32 cdr_pr_buf_in_sr;
+	bool cdr_pr_cap_en;
+	u32 sigdet_vth_sel;
+	u32 phyck_div, phyck_sel;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+		osr = BIT(1) | BIT(0); /* 1.25G */
+		pr_cdr_beta_dac = BIT(3);
+		rx_rate_ctrl = 0;
+		cdr_pr_cap_en = false;
+		cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+		sigdet_vth_sel = BIT(2) | BIT(1);
+		phyck_div = BIT(5) | BIT(3) | BIT(0);
+		phyck_sel = BIT(0);
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX:
+		osr = BIT(0); /* 2.5G */
+		pr_cdr_beta_dac = BIT(2) | BIT(1);
+		rx_rate_ctrl = 0;
+		cdr_pr_cap_en = true;
+		cdr_pr_buf_in_sr = BIT(2) | BIT(1);
+		sigdet_vth_sel = BIT(2) | BIT(1);
+		phyck_div = BIT(3) | BIT(1) | BIT(0);
+		phyck_sel = BIT(0);
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		osr = 0; /* 10G */
+		cdr_pr_cap_en = false;
+		pr_cdr_beta_dac = BIT(3);
+		rx_rate_ctrl = BIT(1);
+		cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+		sigdet_vth_sel = BIT(1);
+		phyck_div = BIT(6) | BIT(1);
+		phyck_sel = BIT(1);
+		break;
+	default:
+		return;
+	}
+
+	/* Set RX rate ctrl */
+	if (interface == PHY_INTERFACE_MODE_2500BASEX)
+		regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_2,
+				   AIROHA_PCS_PMA_CK_RATE,
+				   AIROHA_PCS_PMA_CK_RATE_10);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1,
+			   AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,
+			   FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL, rx_rate_ctrl));
+
+	/* Setup RX Path */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_5,
+			   AIROHA_PCS_PMA_FLL_IDAC_MIN |
+			   AIROHA_PCS_PMA_FLL_IDAC_MAX,
+			   FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) |
+			   FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x3ff));
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ,
+			AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ |
+			AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ |
+			AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ |
+			AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ);
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB,
+			AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ);
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB,
+			AIROHA_PCS_ANA_FE_VCM_GEN_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1,
+			AIROHA_PCS_PMA_LCPLL_MAN_PWDB);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_AEQ_CFORCE,
+			   AIROHA_PCS_ANA_AEQ_OFORCE,
+			   AIROHA_PCS_ANA_AEQ_OFORCE_CTLE);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW,
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE,
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4,
+			  AIROHA_PCS_PMA_DISB_BLWC_OFFSET);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL,
+			  AIROHA_PCS_PMA_DISB_LEQ);
+
+	regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV,
+			  AIROHA_PCS_ANA_CDR_PD_EDGE_DIS |
+			  AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_BYPASS,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON |
+			   AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL |
+			AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN,
+			   AIROHA_PCS_ANA_RX_DAC_MON |
+			   AIROHA_PCS_ANA_CDR_PR_XFICK_EN |
+			   AIROHA_PCS_ANA_CDR_PR_MONDPI_EN |
+			   AIROHA_PCS_ANA_CDR_PR_MONDPR_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_DAC_MON, 0x0) |
+			   AIROHA_PCS_ANA_CDR_PR_XFICK_EN);
+
+	/* Setup FE Gain and FE Peacking */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, 0x0));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PEAKING_CTRL |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_PEAKING_CTRL,
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_PEAKING_CTRL, 0x0));
+
+	/* Setup FE VOS */
+	if (interface != PHY_INTERFACE_MODE_USXGMII &&
+	    interface != PHY_INTERFACE_MODE_10GBASER)
+		regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+				   AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+				   AIROHA_PCS_PMA_FORCE_DA_FE_VOS,
+				   AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+				   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_FE_VOS, 0x0));
+
+	/* Setup FLL PR FMeter (no bypass mode)*/
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_0,
+			   AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT,
+			   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, 0x1));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_1,
+			   AIROHA_PCS_PMA_PLL_LOCK_TARGET_END |
+			   AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG,
+			   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_END, 0xffff) |
+			   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, 0x0));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_3,
+			   AIROHA_PCS_PMA_PLL_LOCK_LOCKTH,
+			   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, 0x1));
+
+	/* FIXME: Warn and Ask Airoha about typo in air_eth_xsgmii.c line 1391 */
+	/* AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL is set 0x0 in SDK but seems a typo */
+	/* Setup REV */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_REV_0,
+			   AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL |
+			   AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL |
+			   AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK,
+			   FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL, BIT(2)) |
+			   FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL, BIT(2)) |
+			   FIELD_PREP(AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK, 0x0));
+
+	/* Setup Rdy Timeout */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5,
+			   AIROHA_PCS_PMA_RX_RDY |
+			   AIROHA_PCS_PMA_RX_BLWC_RDY_EN,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) |
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5));
+
+	/* Setup CaBoundry Init */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0,
+			   AIROHA_PCS_PMA_RX_OS_START |
+			   AIROHA_PCS_PMA_OSC_SPEED_OPT,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1) |
+			   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6,
+			   AIROHA_PCS_PMA_RX_OS_END,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1,
+			   AIROHA_PCS_PMA_RX_PICAL_END |
+			   AIROHA_PCS_PMA_RX_PICAL_START,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x32) |
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4,
+			   AIROHA_PCS_PMA_RX_SDCAL_END |
+			   AIROHA_PCS_PMA_RX_SDCAL_START,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x32) |
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2,
+			   AIROHA_PCS_PMA_RX_PDOS_END |
+			   AIROHA_PCS_PMA_RX_PDOS_START,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x32) |
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3,
+			   AIROHA_PCS_PMA_RX_FEOS_END |
+			   AIROHA_PCS_PMA_RX_FEOS_START,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x32) |
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2));
+
+	/* Setup By Serdes*/
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+			   AIROHA_PCS_PMA_FORCE_DA_OSR_SEL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr));
+
+	/* Setup RX OSR */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV,
+			   AIROHA_PCS_ANA_CDR_PD_EDGE_DIS,
+			   osr ? AIROHA_PCS_ANA_CDR_PD_EDGE_DIS : 0);
+
+	/* Setup CDR LPF Ratio */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO,
+			   AIROHA_PCS_ANA_CDR_LPF_TOP_LIM |
+			   AIROHA_PCS_ANA_CDR_LPF_RATIO,
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_TOP_LIM, 0x20000) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_RATIO, osr));
+
+	/* Setup CDR PR */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC,
+			   AIROHA_PCS_ANA_CDR_PR_KBAND_DIV |
+			   AIROHA_PCS_ANA_CDR_PR_BETA_SEL |
+			   AIROHA_PCS_ANA_CDR_PR_VCOADC_OS |
+			   AIROHA_PCS_ANA_CDR_PR_BETA_DAC,
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_KBAND_DIV, 0x4) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_SEL, 0x1) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VCOADC_OS, 0x8) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_DAC, pr_cdr_beta_dac));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL,
+			   AIROHA_PCS_ANA_CDR_PR_FBKSEL |
+			   AIROHA_PCS_ANA_CDR_PR_VREG_DAC_BAND |
+			   AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL |
+			   AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL,
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_FBKSEL, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_DAC_BAND, pr_cdr_beta_dac) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL, 0x6) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL, 0x6));
+
+	/* Setup Eye Mon */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_3,
+			   AIROHA_PCS_PMA_EQ_DEBUG_SEL |
+			   AIROHA_PCS_PMA_FOM_NUM_ORDER |
+			   AIROHA_PCS_PMA_A_SEL,
+			   FIELD_PREP(AIROHA_PCS_PMA_EQ_DEBUG_SEL, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) |
+			   FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2,
+			   AIROHA_PCS_PMA_DATA_SHIFT |
+			   AIROHA_PCS_PMA_EYECNT_FAST,
+			   AIROHA_PCS_PMA_EYECNT_FAST);
+
+	/* Calibration Start */
+
+	/* Enable SYS */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0,
+			   AIROHA_PCS_PMA_RX_SYS_EN_SEL,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1));
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0,
+			AIROHA_PCS_PMA_SW_LCPLL_EN);
+
+	usleep_range(500, 600);
+
+	/* Setup FLL PR FMeter (bypass mode)*/
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,
+			  AIROHA_PCS_PMA_DISB_FBCK_LOCK);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+			AIROHA_PCS_PMA_FORCE_FBCK_LOCK);
+
+	/* Enable CMLEQ */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN,
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN |
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN |
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN |
+			   AIROHA_PCS_ANA_RX_FE_EQ_HZEN,
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN |
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN |
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN);
+
+	/* Setup CDR PR */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN,
+			   AIROHA_PCS_ANA_CDR_PR_CAP_EN |
+			   AIROHA_PCS_ANA_CDR_BUF_IN_SR,
+			   (cdr_pr_cap_en ? AIROHA_PCS_ANA_CDR_PR_CAP_EN : 0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_BUF_IN_SR, cdr_pr_buf_in_sr));
+
+	/* Setup CDR xxx Pwdb, set force and disable */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+			  AIROHA_PCS_PMA_XPON_CDR_PR_PD_PWDB |
+			  AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+			  AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+			  AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+	/* FIXME: Ask Airoha WHY it's cleared? */
+	/* regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
+	 *		  AIROHA_PCS_ANA_RX_FE_50OHMS_SEL);
+	 */
+
+	/* Setup SigDet */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
+			   AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL |
+			   AIROHA_PCS_ANA_RX_SIGDET_PEAK,
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL, sigdet_vth_sel) |
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_PEAK, BIT(1)));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_RANGE,
+			   AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL,
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL, BIT(1) | BIT(0)));
+
+	/* Disable SigDet Pwdb */
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+			  AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+
+	/* Setup PHYCK */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV,
+			   AIROHA_PCS_ANA_RX_TDC_CK_SEL |
+			   AIROHA_PCS_ANA_RX_PHYCK_RSTB |
+			   AIROHA_PCS_ANA_RX_PHYCK_SEL |
+			   AIROHA_PCS_ANA_RX_PHYCK_DIV,
+			   AIROHA_PCS_ANA_RX_PHYCK_RSTB |
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_SEL, phyck_sel) |
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_DIV, phyck_div));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL,
+			   AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE |
+			   AIROHA_PCS_ANA_RX_PHY_CK_SEL,
+			   AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE);
+
+	usleep_range(100, 200);
+
+	/* Enable CDR xxx Pwdb */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+			AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+			AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+			AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+			AIROHA_PCS_PMA_XPON_CDR_PR_PD_PWDB |
+			AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+			AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+			AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+	/* Enable SigDet Pwdb */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+			AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+}
+
+static unsigned int airoha_pcs_apply_cdr_pr_idac(struct airoha_pcs_priv *priv,
+						 u32 cdr_pr_idac)
+{
+	u32 val;
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+			   AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+				      cdr_pr_idac));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+			   AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+			   AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+			   AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+			   AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL);
+
+	usleep_range(5000, 7000);
+
+	regmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+
+	return FIELD_GET(AIROHA_PCS_PMA_FL_OUT, val);
+}
+
+static void airoha_pcs_rx_prcal(struct airoha_pcs_priv *priv,
+				phy_interface_t interface)
+{
+	unsigned int remaining_prcal_search_bits;
+	unsigned int fl_out_diff = UINT_MAX;
+	u32 best_prcal_search_bit;
+	unsigned int prcal_search;
+	int prcal_search_bit;
+	unsigned int fl_out;
+	int cdr_pr_idac = 0;
+
+	u32 target_fl_out;
+	u32 cyclecnt;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:  /* DS_1.25G      / US_1.25G  */
+	case PHY_INTERFACE_MODE_1000BASEX:
+		target_fl_out = 0xa3d6;
+		cyclecnt = 32767;
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX: /* DS_9.95328G   / US_9.95328G */
+		target_fl_out = 0xa000;
+		cyclecnt = 20000;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII: /* DS_10.3125G  / US_1.25G */
+	case PHY_INTERFACE_MODE_10GBASER:
+		target_fl_out = 0x9edf;
+		cyclecnt = 32767;
+		break;
+	default:
+		return;
+	}
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			AIROHA_PCS_PMA_SW_REF_RST_N);
+
+	usleep_range(100, 200);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_2,
+			   AIROHA_PCS_PMA_LOCK_TARGET_END |
+			   AIROHA_PCS_PMA_LOCK_TARGET_BEG,
+			   FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_END, target_fl_out + 100) |
+			   FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_BEG, target_fl_out - 100));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1,
+			   AIROHA_PCS_PMA_UNLOCK_CYCLECNT |
+			   AIROHA_PCS_PMA_LOCK_CYCLECNT,
+			   FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, cyclecnt) |
+			   FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, cyclecnt));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+			   AIROHA_PCS_PMA_LOCK_UNLOCKTH |
+			   AIROHA_PCS_PMA_LOCK_LOCKTH,
+			   FIELD_PREP(AIROHA_PCS_PMA_LOCK_UNLOCKTH, 3) |
+			   FIELD_PREP(AIROHA_PCS_PMA_LOCK_LOCKTH, 3));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_3,
+			   AIROHA_PCS_PMA_UNLOCK_TARGET_END |
+			   AIROHA_PCS_PMA_UNLOCK_TARGET_BEG,
+			   FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_END, target_fl_out + 100) |
+			   FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, target_fl_out - 100));
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE,
+			AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			  AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+	/* Calibration logic:
+	 * First check the major value by looping with every
+	 * value in the last 3 bit of CDR_PR_IDAC.
+	 * Get the signal level and save the value that is closer to
+	 * the target.
+	 *
+	 * Then check each remaining 7 bits in search of the deadline
+	 * where the signal gets farther than signal target.
+	 *
+	 * Finally fine tune for the remaining bits to find the one that
+	 * produce the closest signal level.
+	 */
+	for (prcal_search = 0; prcal_search < 8 ; prcal_search++) {
+		unsigned int fl_out_diff_new;
+		u32 cdr_pr_idac_tmp;
+
+		/* try to find the upper value by setting the last 3 bit */
+		cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+					     prcal_search);
+		fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);
+
+		/* Use absolute values to find the closest one to target */
+		fl_out_diff_new = abs(fl_out - target_fl_out);
+		if (fl_out_diff_new < fl_out_diff) {
+			cdr_pr_idac = cdr_pr_idac_tmp;
+			fl_out_diff = fl_out_diff_new;
+		}
+	}
+
+	/* Deadline search part.
+	 * We start from top bits to bottom as we progressively decrease the
+	 * signal.
+	 */
+	for (prcal_search_bit = 7; prcal_search_bit >= 0; prcal_search_bit--) {
+		unsigned int fl_out_diff_new;
+		u32 cdr_pr_idac_tmp;
+
+		cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
+		fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);
+
+		/* Use absolute values to find the closest one to target */
+		fl_out_diff_new = abs(fl_out - target_fl_out);
+		if (fl_out_diff_new < fl_out_diff) {
+			best_prcal_search_bit = prcal_search_bit;
+			fl_out_diff = fl_out_diff_new;
+		}
+	}
+
+	/* Set the idac with the best value we found and
+	 * reset the search bit to start from bottom to top.
+	 */
+	cdr_pr_idac |= BIT(best_prcal_search_bit);
+	remaining_prcal_search_bits = best_prcal_search_bit;
+	prcal_search_bit = 0;
+
+	/* Fine tune part.
+	 * Test remaining bits to find an even closer signal level to target
+	 * by increasing the signal.
+	 */
+	while (remaining_prcal_search_bits) {
+		unsigned int fl_out_diff_new;
+		u32 cdr_pr_idac_tmp;
+
+		cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
+		fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);
+
+		/* Use absolute values to find the closest one to target */
+		fl_out_diff_new = abs(fl_out - target_fl_out);
+		/* Assume we found the deadline when the new absolue signal difference
+		 * from target is greater than the previous and the difference is at
+		 * least 10% greater between the old and new value.
+		 * This is to account for signal detection level tollerance making
+		 * sure we are actually over a deadline (AKA we are getting farther
+		 * from target)
+		 */
+		if (fl_out_diff_new > fl_out_diff &&
+		    (abs(fl_out_diff_new - fl_out_diff) * 100) / fl_out_diff > 10) {
+			/* Exit early if we are already at the deadline */
+			if (prcal_search_bit == 0)
+				break;
+
+			/* We found the deadline, set the value to the previous
+			 * bit, and reset the loop to fine tune with the
+			 * remaining values.
+			 */
+			cdr_pr_idac |= BIT(prcal_search_bit - 1);
+			remaining_prcal_search_bits = prcal_search_bit - 1;
+			prcal_search_bit = 0;
+		} else {
+			/* Update the signal level diff and try the next bit */
+			fl_out_diff = fl_out_diff_new;
+
+			/* If we didn't found the deadline, set the last bit
+			 * and reset the loop to fine tune with the remainig
+			 * values.
+			 */
+			if (prcal_search_bit == remaining_prcal_search_bits - 1) {
+				cdr_pr_idac |= BIT(prcal_search_bit);
+				remaining_prcal_search_bits = prcal_search_bit;
+				prcal_search_bit = 0;
+			} else {
+				prcal_search_bit++;
+			}
+		}
+	}
+
+	fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac);
+	dev_dbg(priv->dev, "Selected CDR Pr Idac: %x Fl Out: %x\n", cdr_pr_idac, fl_out);
+	if (abs(fl_out - target_fl_out) > 100)
+		dev_dbg(priv->dev, "Fl Out is %d far from target %d on intermediate calibration.\n",
+			abs(fl_out - target_fl_out), target_fl_out);
+
+	/* Setup Load Band */
+	regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE,
+			  AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF);
+
+	/* Disable force of LPF C previously enabled */
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+			  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+			  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_B,
+			AIROHA_PCS_PMA_LOAD_EN);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_1,
+			   AIROHA_PCS_PMA_LPATH_IDAC,
+			   FIELD_PREP(AIROHA_PCS_PMA_LPATH_IDAC, cdr_pr_idac));
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			  AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			  AIROHA_PCS_PMA_SW_REF_RST_N);
+
+	usleep_range(100, 200);
+}
+
+/* This is used to both calibrate and lock to signal (after a previous
+ * calibration) after a global reset.
+ */
+static void airoha_pcs_cdr_reset(struct airoha_pcs_priv *priv,
+				 phy_interface_t interface, bool calibrate)
+{
+	/* Setup LPF L2D force and disable */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+
+	/* Calibrate IDAC and setup Load Band */
+	if (calibrate)
+		airoha_pcs_rx_prcal(priv, interface);
+
+	/* Setup LPF RSTB force and disable */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+	usleep_range(700, 1000);
+
+	/* Force Enable LPF RSTB */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);
+
+	usleep_range(100, 200);
+
+	/* Force Enable LPF L2D */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA);
+
+	/* Disable LPF RSTB force bit */
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+	/* Disable LPF L2D force bit */
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+}
+
+static int airoha_pcs_phya_bringup(struct airoha_pcs_priv *priv,
+				   phy_interface_t interface)
+{
+	int calibration_try = 0;
+	u32 val;
+
+	airoha_pcs_tx_bringup(priv, interface);
+	airoha_pcs_rx_bringup(priv, interface);
+
+	usleep_range(100, 200);
+
+retry_calibration:
+	airoha_pcs_cdr_reset(priv, interface, true);
+
+	/* Global reset clear */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			   AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+			   AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+			   AIROHA_PCS_PMA_SW_HSG_RXPCS_BIST_RST_N |
+			   AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+			   AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+			   AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+			   AIROHA_PCS_PMA_SW_REF_RST_N |
+			   AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+			   AIROHA_PCS_PMA_SW_PMA_RST_N |
+			   AIROHA_PCS_PMA_SW_TX_RST_N |
+			   AIROHA_PCS_PMA_SW_RX_RST_N |
+			   AIROHA_PCS_PMA_SW_RX_FIFO_RST_N,
+			   AIROHA_PCS_PMA_SW_REF_RST_N);
+
+	usleep_range(100, 200);
+
+	/* Global reset */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+			AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+			AIROHA_PCS_PMA_SW_HSG_RXPCS_BIST_RST_N |
+			AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+			AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+			AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+			AIROHA_PCS_PMA_SW_REF_RST_N |
+			AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+			AIROHA_PCS_PMA_SW_PMA_RST_N |
+			AIROHA_PCS_PMA_SW_TX_RST_N |
+			AIROHA_PCS_PMA_SW_RX_RST_N |
+			AIROHA_PCS_PMA_SW_RX_FIFO_RST_N);
+
+	usleep_range(5000, 7000);
+
+	airoha_pcs_cdr_reset(priv, interface, false);
+
+	/* It was discovered that after a global reset and auto mode gets
+	 * actually enabled, the fl_out from calibration might change and
+	 * might deviates a lot from the expected value it was calibrated for.
+	 * To correctly work, the PCS FreqDet module needs to Lock to the fl_out
+	 * (frequency level output) or no signal can correctly be transmitted.
+	 * This is detected by checking the FreqDet module Lock bit.
+	 *
+	 * If it's detected that the FreqDet module is not locked, retry
+	 * calibration. From observation on real hardware with a 10g SFP module,
+	 * it required a maximum of an additional calibration to actually make
+	 * the FreqDet module to lock. Try 10 times before failing to handle
+	 * really strange case.
+	 */
+	regmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+	if (!(val & AIROHA_PCS_PMA_FBCK_LOCK)) {
+		if (calibration_try > AIROHA_PCS_MAX_CALIBRATION_TRY) {
+			dev_err(priv->dev, "No FBCK Lock from FreqDet module after %d calibration try. PCS won't work.\n",
+				AIROHA_PCS_MAX_CALIBRATION_TRY);
+			return -EIO;
+		}
+
+		calibration_try++;
+
+		dev_dbg(priv->dev, "No FBCK Lock from FreqDet module, retry calibration.\n");
+		goto retry_calibration;
+	}
+
+	return 0;
+}
+
+static void airoha_pcs_get_state_sgmii(struct airoha_pcs_priv *priv,
+				       unsigned int neg_mode,
+				       struct phylink_link_state *state)
+{
+	u32 bmsr, lpa;
+
+	regmap_read(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,
+		    &bmsr);
+	regmap_read(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5,
+		    &lpa);
+
+	bmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |
+		AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |
+		AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |
+		AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr;
+	lpa = AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY & lpa;
+
+	phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa);
+}
+
+static void airoha_pcs_get_state_usxgmii(struct airoha_pcs_priv *priv,
+					 struct phylink_link_state *state)
+{
+	u32 lpa;
+
+	/* Toggle AN Status */
+	regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+			AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+			  AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+
+	regmap_read(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, &lpa);
+
+	state->link = !!(lpa & MDIO_USXGMII_LINK);
+	state->an_complete = state->link;
+
+	phylink_decode_usxgmii_word(state, lpa);
+}
+
+static void airoha_pcs_get_state(struct phylink_pcs *pcs,
+				 unsigned int neg_mode,
+				 struct phylink_link_state *state)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+	switch (state->interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		airoha_pcs_get_state_sgmii(priv, neg_mode, state);
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		airoha_pcs_get_state_usxgmii(priv, state);
+		break;
+	default:
+		return;
+	}
+}
+
+static void airoha_pcs_pre_config(struct phylink_pcs *pcs,
+				  phy_interface_t interface)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+	/* MPI MBI disable */
+	regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+			AIROHA_PCS_XFI_RXMPI_STOP |
+			AIROHA_PCS_XFI_RXMBI_STOP |
+			AIROHA_PCS_XFI_TXMPI_STOP |
+			AIROHA_PCS_XFI_TXMBI_STOP);
+
+	/* Write 1 to trigger reset and clear */
+	regmap_clear_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,
+			  AIROHA_PCS_XFI_MAC_LOGIC_RST);
+	regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,
+			AIROHA_PCS_XFI_MAC_LOGIC_RST);
+
+	usleep_range(1000, 2000);
+
+	/* Clear XFI MAC counter */
+	regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_CNT_CLR,
+			AIROHA_PCS_XFI_GLB_CNT_CLR);
+}
+
+static int airoha_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+			     phy_interface_t interface,
+			     const unsigned long *advertising,
+			     bool permit_pause_to_mac)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+	u32 rate_adapt;
+	int ret;
+
+	priv->interface = interface;
+
+	/* Select HSGMII or USXGMII in SCU regs */
+	airoha_pcs_setup_scu(priv, interface);
+
+	/* Enable Analog Common Lane */
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CMN_EN,
+			AIROHA_PCS_ANA_CMN_EN);
+
+	/* Setup PLL */
+	airoha_pcs_pll_bringup(priv, interface);
+
+	/* Setup PHYA */
+	ret = airoha_pcs_phya_bringup(priv, interface);
+	if (ret)
+		return ret;
+
+	/* Set final configuration for various modes */
+	airoha_pcs_init(priv, interface);
+
+	/* Configure Interrupt for various modes */
+	airoha_pcs_interrupt_init(priv, interface);
+
+	/* FIXME: With an attached Aeonsemi PHY, rate adaption is needed
+	 * even with no inband.
+	 */
+	rate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+		     AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN;
+
+	/* AN Auto Settings (Rate Adaptation) */
+	regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0,
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS |
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN, rate_adapt);
+
+	/* FIXME: With an attached Aeonsemi PHY, AN is needed
+	 * even with no inband.
+	 */
+	if (interface == PHY_INTERFACE_MODE_USXGMII ||
+	    interface == PHY_INTERFACE_MODE_10GBASER) {
+		regmap_set_bits(priv->usxgmii_pcs,
+				AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+				AIROHA_PCS_USXGMII_AN_ENABLE);
+	}
+
+	/* Clear any force bit that my be set by bootloader */
+	if (interface == PHY_INTERFACE_MODE_SGMII ||
+	    interface == PHY_INTERFACE_MODE_1000BASEX ||
+	    interface == PHY_INTERFACE_MODE_2500BASEX) {
+		regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+				  AIROHA_PCS_LINK_MODE_P0 |
+				  AIROHA_PCS_FORCE_SPD_MODE_P0 |
+				  AIROHA_PCS_FORCE_LINKDOWN_P0 |
+				  AIROHA_PCS_FORCE_LINKUP_P0);
+	}
+
+	/* Toggle Rate Adaption for SGMII/HSGMII mode */
+	if (interface == PHY_INTERFACE_MODE_SGMII ||
+	    interface == PHY_INTERFACE_MODE_1000BASEX ||
+	    interface == PHY_INTERFACE_MODE_2500BASEX) {
+		if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+			regmap_clear_bits(priv->hsgmii_rate_adp,
+					  AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+					  AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+		else
+			regmap_set_bits(priv->hsgmii_rate_adp,
+					AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+					AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+	}
+
+	/* Setup AN Link Timer */
+	if (interface == PHY_INTERFACE_MODE_SGMII ||
+	    interface == PHY_INTERFACE_MODE_1000BASEX ||
+	    interface == PHY_INTERFACE_MODE_2500BASEX) {
+		u32 an_timer;
+
+		an_timer = phylink_get_link_timer_ns(interface);
+
+		/* Value needs to be shifted by 4, seems value is internally * 16 */
+		regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11,
+				   AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+				   FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+					      an_timer >> 4));
+
+		regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_3,
+				   AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+				   FIELD_PREP(AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+					      an_timer >> 4));
+	}
+
+	/* Setup SGMII AN and advertisement in DEV_ABILITY */
+	if (interface == PHY_INTERFACE_MODE_SGMII &&
+	    neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+		int advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
+									 advertising);
+		if (advertise < 0)
+			return advertise;
+
+		regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+				AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+
+		regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4,
+				   AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+				   FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+					      advertise));
+	} else {
+		regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+				  AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+	}
+
+	if (interface == PHY_INTERFACE_MODE_SGMII ||
+	    interface == PHY_INTERFACE_MODE_1000BASEX) {
+		u32 if_mode = AIROHA_PCS_HSGMII_AN_SGMII_EN |
+			      AIROHA_PCS_HSGMII_AN_SIDEBAND_EN;
+
+		if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+			regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+					AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+
+			/* Clear force speed bits and MAC mode */
+			regmap_clear_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+					  AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+					  AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+					  AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+					  AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+					  AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL |
+					  AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+		} else {
+			if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN;
+
+			regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+					  AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+
+			/* AN off force rate adaption, speed is set later in Link Up */
+			regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+					   AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+					   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT,
+					   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+		}
+
+		regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+				   AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0, if_mode);
+
+		/* FIXME: Airoha apply a different configuration here */
+		/* They force rate adaption */
+		regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+				AIROHA_PCS_HSGMII_PCS_TX_ENABLE |
+				AIROHA_PCS_HSGMII_PCS_MODE2_EN);
+	}
+
+	if (interface == PHY_INTERFACE_MODE_1000BASEX &&
+	    neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+		regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+				AIROHA_PCS_SGMII_SEND_AN_ERR_EN);
+
+		regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37,
+				AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE);
+	}
+
+	/* Configure Flow Control on XFI */
+	regmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+			   AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN,
+			   permit_pause_to_mac ?
+				AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN :
+				0);
+
+	return 0;
+}
+
+static void airoha_pcs_an_restart(struct phylink_pcs *pcs)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+	switch (priv->interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+				AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+		udelay(3);
+		regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+				  AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+		regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+				AIROHA_PCS_USXGMII_AN_RESTART);
+		udelay(3);
+		regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+				  AIROHA_PCS_USXGMII_AN_RESTART);
+	default:
+		return;
+	}
+}
+
+static void airoha_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+			       phy_interface_t interface, int speed, int duplex)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+		if (interface == PHY_INTERFACE_MODE_SGMII) {
+			regmap_update_bits(priv->hsgmii_rate_adp,
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+					   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0x0) |
+					   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x0));
+			udelay(1);
+			regmap_update_bits(priv->hsgmii_rate_adp,
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+					   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0xf) |
+					   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x5));
+		}
+	} else {
+		if (interface == PHY_INTERFACE_MODE_USXGMII ||
+		    interface == PHY_INTERFACE_MODE_10GBASER) {
+			u32 mode;
+			u32 rate_adapt;
+
+			switch (speed) {
+			case SPEED_10000:
+				rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000;
+				mode = AIROHA_PCS_USXGMII_MODE_10000;
+				break;
+			case SPEED_5000:
+				rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000;
+				mode = AIROHA_PCS_USXGMII_MODE_5000;
+				break;
+			case SPEED_2500:
+				rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500;
+				mode = AIROHA_PCS_USXGMII_MODE_2500;
+				break;
+			case SPEED_1000:
+				rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000;
+				mode = AIROHA_PCS_USXGMII_MODE_1000;
+				break;
+			case SPEED_100:
+				rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100;
+				mode = AIROHA_PCS_USXGMII_MODE_100;
+				break;
+			}
+
+			/* Trigger USXGMII change mode and force selected speed */
+			regmap_update_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+					   AIROHA_PCS_USXGMII_RATE_UPDATE_MODE |
+					   AIROHA_PCS_USXGMII_MODE,
+					   AIROHA_PCS_USXGMII_RATE_UPDATE_MODE | mode);
+
+			regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11,
+					   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+					   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE,
+					   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+					   rate_adapt);
+		}
+
+		if (interface == PHY_INTERFACE_MODE_SGMII ||
+		    interface == PHY_INTERFACE_MODE_1000BASEX) {
+			u32 force_speed;
+			u32 rate_adapt;
+
+			switch (speed) {
+			case SPEED_1000:
+				force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000;
+				rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000;
+				break;
+			case SPEED_100:
+				force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100;
+				rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100;
+				break;
+			case SPEED_10:
+				force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10;
+				rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10;
+				break;
+			}
+
+			regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+					   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+					   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+					   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+					   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL,
+					   force_speed | rate_adapt);
+		}
+
+		if (interface == PHY_INTERFACE_MODE_SGMII ||
+		    interface == PHY_INTERFACE_MODE_2500BASEX) {
+			u32 ck_gen_mode;
+			u32 speed_reg;
+			u32 if_mode;
+
+			switch (speed) {
+			case SPEED_2500:
+				speed_reg = AIROHA_PCS_LINK_MODE_P0_2_5G;
+				break;
+			case SPEED_1000:
+				speed_reg = AIROHA_PCS_LINK_MODE_P0_1G;
+				if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000;
+				ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000;
+				break;
+			case SPEED_100:
+				speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
+				if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100;
+				ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100;
+				break;
+			case SPEED_10:
+				speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
+				if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10;
+				ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10;
+				break;
+			}
+
+			if (interface == PHY_INTERFACE_MODE_SGMII) {
+				regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+						   AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE,
+						   if_mode);
+
+				regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE,
+						   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE |
+						   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL,
+						   ck_gen_mode |
+						   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL);
+			}
+
+			regmap_update_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+					   AIROHA_PCS_LINK_MODE_P0 |
+					   AIROHA_PCS_FORCE_SPD_MODE_P0,
+					   speed_reg |
+					   AIROHA_PCS_FORCE_SPD_MODE_P0);
+		}
+	}
+
+	/* Reset TXPCS on link up */
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			  AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+
+	usleep_range(100, 200);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+
+	/* BPI BMI enable */
+	regmap_clear_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+			  AIROHA_PCS_XFI_RXMPI_STOP |
+			  AIROHA_PCS_XFI_RXMBI_STOP |
+			  AIROHA_PCS_XFI_TXMPI_STOP |
+			  AIROHA_PCS_XFI_TXMBI_STOP);
+}
+
+static void airoha_pcs_link_down(struct phylink_pcs *pcs)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+	/* MPI MBI disable */
+	regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+			AIROHA_PCS_XFI_RXMPI_STOP |
+			AIROHA_PCS_XFI_RXMBI_STOP |
+			AIROHA_PCS_XFI_TXMPI_STOP |
+			AIROHA_PCS_XFI_TXMBI_STOP);
+}
+
+static const struct phylink_pcs_ops airoha_pcs_ops = {
+	.pcs_get_state = airoha_pcs_get_state,
+	.pcs_pre_config = airoha_pcs_pre_config,
+	.pcs_config = airoha_pcs_config,
+	.pcs_an_restart = airoha_pcs_an_restart,
+	.pcs_link_up = airoha_pcs_link_up,
+	.pcs_link_down = airoha_pcs_link_down,
+};
+
+static const struct regmap_config airoha_pcs_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+};
+
+static int airoha_pcs_probe(struct platform_device *pdev)
+{
+	struct regmap_config syscon_config = airoha_pcs_regmap_config;
+	struct device *dev = &pdev->dev;
+	struct airoha_pcs_priv *priv;
+	void __iomem *base;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	priv->data = of_device_get_match_data(dev);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "xfi_mac");
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	syscon_config.name = "xfi_mac";
+	priv->xfi_mac = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->xfi_mac))
+		return PTR_ERR(priv->xfi_mac);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_an");
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	syscon_config.name = "hsgmii_an";
+	priv->hsgmii_an = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->hsgmii_an))
+		return PTR_ERR(priv->hsgmii_an);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_pcs");
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	syscon_config.name = "hsgmii_pcs";
+	priv->hsgmii_pcs = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->hsgmii_pcs))
+		return PTR_ERR(priv->hsgmii_pcs);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_rate_adp");
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	syscon_config.name = "hsgmii_rate_adp";
+	priv->hsgmii_rate_adp = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->hsgmii_rate_adp))
+		return PTR_ERR(priv->hsgmii_rate_adp);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "multi_sgmii");
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	syscon_config.name = "multi_sgmii";
+	priv->multi_sgmii = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->multi_sgmii))
+		return PTR_ERR(priv->multi_sgmii);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "usxgmii");
+	if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
+		return PTR_ERR(base);
+
+	syscon_config.name = "usxgmii";
+	priv->usxgmii_pcs = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->usxgmii_pcs))
+		return PTR_ERR(priv->usxgmii_pcs);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "xfi_pma");
+	if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
+		return PTR_ERR(base);
+
+	syscon_config.name = "xfi_pma";
+	priv->xfi_pma = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->xfi_pma))
+		return PTR_ERR(priv->xfi_pma);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "xfi_ana");
+	if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
+		return PTR_ERR(base);
+
+	syscon_config.name = "xfi_ana";
+	priv->xfi_ana = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->xfi_ana))
+		return PTR_ERR(priv->xfi_ana);
+
+	/* SCU is used to toggle XFI or HSGMII in global SoC registers */
+	priv->scu = syscon_regmap_lookup_by_compatible("airoha,en7581-scu");
+	if (IS_ERR(priv->scu))
+		return PTR_ERR(priv->scu);
+
+	priv->rsts[0].id = "mac";
+	priv->rsts[1].id = "phy";
+	ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(priv->rsts),
+						    priv->rsts);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to get bulk reset lines\n");
+
+	platform_set_drvdata(pdev, priv);
+
+	priv->pcs.ops = &airoha_pcs_ops;
+	priv->pcs.poll = true;
+
+	__set_bit(PHY_INTERFACE_MODE_SGMII, priv->pcs.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_1000BASEX, priv->pcs.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_2500BASEX, priv->pcs.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_10GBASER, priv->pcs.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_USXGMII, priv->pcs.supported_interfaces);
+
+	return fwnode_pcs_add_provider(dev_fwnode(dev), fwnode_pcs_simple_get,
+				   &priv->pcs);
+}
+
+static void airoha_pcs_remove(struct platform_device *pdev)
+{
+	struct airoha_pcs_priv *priv = platform_get_drvdata(pdev);
+
+	fwnode_pcs_del_provider(dev_fwnode(&pdev->dev));
+
+	rtnl_lock();
+	phylink_release_pcs(&priv->pcs);
+	rtnl_unlock();
+}
+
+static const struct airoha_pcs_match_data an7581_pcs_eth = {
+	.port_type = AIROHA_PCS_ETH,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_pon = {
+	.port_type = AIROHA_PCS_PON,
+};
+
+static const struct of_device_id airoha_pcs_of_table[] = {
+	{ .compatible = "airoha,an7581-pcs-eth", .data = &an7581_pcs_eth },
+	{ .compatible = "airoha,an7581-pcs-pon", .data = &an7581_pcs_pon },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, airoha_pcs_of_table);
+
+static struct platform_driver airoha_pcs_driver = {
+	.driver = {
+		.name	 = "airoha-pcs",
+		.of_match_table = airoha_pcs_of_table,
+	},
+	.probe = airoha_pcs_probe,
+	.remove = airoha_pcs_remove,
+};
+module_platform_driver(airoha_pcs_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Airoha PCS driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth at gmail.com>");
-- 
2.48.1



From ansuelsmth at gmail.com  Sat May 10 03:23:30 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sat, 10 May 2025 12:23:30 +0200
Subject: [net-next PATCH v3 10/11] dt-bindings: net: pcs: Document support for Airoha Ethernet PCS
In-Reply-To: <20250510102348.14134-1-ansuelsmth@gmail.com>
References: <20250510102348.14134-1-ansuelsmth@gmail.com>
Message-ID: <20250510102348.14134-11-ansuelsmth@gmail.com>

Document support for Airoha Ethernet PCS for AN7581 SoC.

Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
the various Serdes port supporting different Media Independent Interface
(10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).

This follow the new PCS provider with the use of #pcs-cells property.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 .../bindings/net/pcs/airoha,pcs.yaml          | 112 ++++++++++++++++++
 1 file changed, 112 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml

diff --git a/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
new file mode 100644
index 000000000000..8bcf7757c728
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/airoha,pcs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha Ethernet PCS and Serdes
+
+maintainers:
+  - Christian Marangi <ansuelsmth at gmail.com>
+
+description:
+  Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
+  the various Serdes port supporting different Media Independent Interface
+  (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).
+
+properties:
+  compatible:
+    enum:
+      - airoha,an7581-pcs-eth
+      - airoha,an7581-pcs-pon
+
+  reg:
+    items:
+      - description: XFI MAC reg
+      - description: HSGMII AN reg
+      - description: HSGMII PCS reg
+      - description: MULTI SGMII reg
+      - description: USXGMII reg
+      - description: HSGMII rate adaption reg
+      - description: XFI Analog register
+      - description: XFI PMA (Physical Medium Attachment) register
+
+  reg-names:
+    items:
+      - const: xfi_mac
+      - const: hsgmii_an
+      - const: hsgmii_pcs
+      - const: multi_sgmii
+      - const: usxgmii
+      - const: hsgmii_rate_adp
+      - const: xfi_ana
+      - const: xfi_pma
+
+  resets:
+    items:
+      - description: MAC reset
+      - description: PHY reset
+
+  reset-names:
+    items:
+      - const: mac
+      - const: phy
+
+  "#pcs-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - resets
+  - reset-names
+  - "#pcs-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/reset/airoha,en7581-reset.h>
+
+    pcs at 1fa08000 {
+        compatible = "airoha,an7581-pcs-pon";
+        reg = <0x1fa08000 0x1000>,
+              <0x1fa80000 0x60>,
+              <0x1fa80a00 0x164>,
+              <0x1fa84000 0x450>,
+              <0x1fa85900 0x338>,
+              <0x1fa86000 0x300>,
+              <0x1fa8a000 0x1000>,
+              <0x1fa8b000 0x1000>;
+        reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
+                    "multi_sgmii", "usxgmii",
+                    "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
+
+        resets = <&scuclk EN7581_XPON_MAC_RST>,
+                 <&scuclk EN7581_XPON_PHY_RST>;
+        reset-names = "mac", "phy";
+
+        #pcs-cells = <0>;
+    };
+
+    pcs at 1fa09000 {
+        compatible = "airoha,an7581-pcs-eth";
+        reg = <0x1fa09000 0x1000>,
+              <0x1fa70000 0x60>,
+              <0x1fa70a00 0x164>,
+              <0x1fa74000 0x450>,
+              <0x1fa75900 0x338>,
+              <0x1fa76000 0x300>,
+              <0x1fa7a000 0x1000>,
+              <0x1fa7b000 0x1000>;
+        reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
+                    "multi_sgmii", "usxgmii",
+                    "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
+
+        resets = <&scuclk EN7581_XSI_MAC_RST>,
+                 <&scuclk EN7581_XSI_PHY_RST>;
+        reset-names = "mac", "phy";
+
+        #pcs-cells = <0>;
+    };
-- 
2.48.1



From ansuelsmth at gmail.com  Sat May 10 03:23:31 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sat, 10 May 2025 12:23:31 +0200
Subject: [net-next PATCH v3 11/11] net: airoha: add phylink support for GDM2/3/4
In-Reply-To: <20250510102348.14134-1-ansuelsmth@gmail.com>
References: <20250510102348.14134-1-ansuelsmth@gmail.com>
Message-ID: <20250510102348.14134-12-ansuelsmth@gmail.com>

Add phylink support for GDM2/3/4 port that require configuration of the
PCS to make the external PHY or attached SFP cage work.

These needs to be defined in the GDM port node using the pcs-handle
property.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/ethernet/airoha/airoha_eth.c  | 138 ++++++++++++++++++++++
 drivers/net/ethernet/airoha/airoha_eth.h  |   3 +
 drivers/net/ethernet/airoha/airoha_regs.h |  12 ++
 3 files changed, 153 insertions(+)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 16c7896f931f..17521be820b5 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -7,6 +7,7 @@
 #include <linux/of_net.h>
 #include <linux/platform_device.h>
 #include <linux/tcp.h>
+#include <linux/pcs/pcs.h>
 #include <linux/u64_stats_sync.h>
 #include <net/dst_metadata.h>
 #include <net/page_pool/helpers.h>
@@ -79,6 +80,11 @@ static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
 	return port->id == 1;
 }
 
+static bool airhoa_is_phy_external(struct airoha_gdm_port *port)
+{
+	return port->id != 1;
+}
+
 static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
 {
 	struct airoha_eth *eth = port->qdma->eth;
@@ -1613,6 +1619,17 @@ static int airoha_dev_open(struct net_device *dev)
 	struct airoha_gdm_port *port = netdev_priv(dev);
 	struct airoha_qdma *qdma = port->qdma;
 
+	if (airhoa_is_phy_external(port)) {
+		err = phylink_of_phy_connect(port->phylink, dev->dev.of_node, 0);
+		if (err) {
+			netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
+				   err);
+			return err;
+		}
+
+		phylink_start(port->phylink);
+	}
+
 	netif_tx_start_all_queues(dev);
 	err = airoha_set_vip_for_gdm_port(port, true);
 	if (err)
@@ -1665,6 +1682,11 @@ static int airoha_dev_stop(struct net_device *dev)
 		}
 	}
 
+	if (airhoa_is_phy_external(port)) {
+		phylink_stop(port->phylink);
+		phylink_disconnect_phy(port->phylink);
+	}
+
 	return 0;
 }
 
@@ -2795,6 +2817,110 @@ bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
 	return false;
 }
 
+static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,
+			       unsigned int mode, phy_interface_t interface,
+			       int speed, int duplex, bool tx_pause, bool rx_pause)
+{
+	struct airoha_gdm_port *port = container_of(config, struct airoha_gdm_port,
+						    phylink_config);
+	struct airoha_qdma *qdma = port->qdma;
+	struct airoha_eth *eth = qdma->eth;
+	u32 frag_size_tx, frag_size_rx;
+
+	switch (speed) {
+	case SPEED_10000:
+	case SPEED_5000:
+		frag_size_tx = 8;
+		frag_size_rx = 8;
+		break;
+	case SPEED_2500:
+		frag_size_tx = 2;
+		frag_size_rx = 1;
+		break;
+	default:
+		frag_size_tx = 1;
+		frag_size_rx = 0;
+	}
+
+	/* Configure TX/RX frag based on speed */
+	if (port->id == 4) {
+		airoha_fe_rmw(eth, REG_GDMA4_TMBI_FRAG, GDMA4_SGMII0_TX_FRAG_SIZE,
+			      FIELD_PREP(GDMA4_SGMII0_TX_FRAG_SIZE, frag_size_tx));
+
+		airoha_fe_rmw(eth, REG_GDMA4_RMBI_FRAG, GDMA4_SGMII0_RX_FRAG_SIZE,
+			      FIELD_PREP(GDMA4_SGMII0_RX_FRAG_SIZE, frag_size_rx));
+	}
+}
+
+static const struct phylink_mac_ops airoha_phylink_ops = {
+	.mac_link_up = airoha_mac_link_up,
+};
+
+static int airoha_setup_phylink(struct net_device *dev)
+{
+	struct airoha_gdm_port *port = netdev_priv(dev);
+	struct device_node *np = dev->dev.of_node;
+	struct phylink_pcs **available_pcs;
+	phy_interface_t phy_mode;
+	struct phylink *phylink;
+	unsigned int num_pcs;
+	int err;
+
+	err = of_get_phy_mode(np, &phy_mode);
+	if (err) {
+		dev_err(&dev->dev, "incorrect phy-mode\n");
+		return err;
+	}
+
+	port->phylink_config.dev = &dev->dev;
+	port->phylink_config.type = PHYLINK_NETDEV;
+	port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+						MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD |
+						MAC_5000FD | MAC_10000FD;
+
+	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), NULL, &num_pcs);
+	if (err)
+		return err;
+
+	available_pcs = kcalloc(num_pcs, sizeof(*available_pcs), GFP_KERNEL);
+	if (!available_pcs)
+		return -ENOMEM;
+
+	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), available_pcs,
+				       &num_pcs);
+	if (err)
+		goto out;
+
+	port->phylink_config.available_pcs = available_pcs;
+	port->phylink_config.num_available_pcs = num_pcs;
+
+	__set_bit(PHY_INTERFACE_MODE_SGMII,
+		  port->phylink_config.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_1000BASEX,
+		  port->phylink_config.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_2500BASEX,
+		  port->phylink_config.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_USXGMII,
+		  port->phylink_config.supported_interfaces);
+
+	phy_interface_copy(port->phylink_config.pcs_interfaces,
+			   port->phylink_config.supported_interfaces);
+
+	phylink = phylink_create(&port->phylink_config,
+				 of_fwnode_handle(np),
+				 phy_mode, &airoha_phylink_ops);
+	if (IS_ERR(phylink)) {
+		err = PTR_ERR(phylink);
+		goto out;
+	}
+
+	port->phylink = phylink;
+out:
+	kfree(available_pcs);
+
+	return err;
+}
+
 static int airoha_alloc_gdm_port(struct airoha_eth *eth,
 				 struct device_node *np, int index)
 {
@@ -2873,6 +2999,12 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
 	if (err)
 		return err;
 
+	if (airhoa_is_phy_external(port)) {
+		err = airoha_setup_phylink(dev);
+		if (err)
+			return err;
+	}
+
 	return register_netdev(dev);
 }
 
@@ -2967,6 +3099,9 @@ static int airoha_probe(struct platform_device *pdev)
 		struct airoha_gdm_port *port = eth->ports[i];
 
 		if (port && port->dev->reg_state == NETREG_REGISTERED) {
+			if (airhoa_is_phy_external(port))
+				phylink_destroy(port->phylink);
+
 			unregister_netdev(port->dev);
 			airoha_metadata_dst_free(port);
 		}
@@ -2994,6 +3129,9 @@ static void airoha_remove(struct platform_device *pdev)
 			continue;
 
 		airoha_dev_stop(port->dev);
+		if (airhoa_is_phy_external(port))
+			phylink_destroy(port->phylink);
+
 		unregister_netdev(port->dev);
 		airoha_metadata_dst_free(port);
 	}
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index 53f39083a8b0..73a500474076 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -498,6 +498,9 @@ struct airoha_gdm_port {
 	struct net_device *dev;
 	int id;
 
+	struct phylink *phylink;
+	struct phylink_config phylink_config;
+
 	struct airoha_hw_stats stats;
 
 	DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
index d931530fc96f..71c63108f0a8 100644
--- a/drivers/net/ethernet/airoha/airoha_regs.h
+++ b/drivers/net/ethernet/airoha/airoha_regs.h
@@ -357,6 +357,18 @@
 #define IP_FRAGMENT_PORT_MASK		GENMASK(8, 5)
 #define IP_FRAGMENT_NBQ_MASK		GENMASK(4, 0)
 
+#define REG_GDMA4_TMBI_FRAG		0x2028
+#define GDMA4_SGMII1_TX_WEIGHT		GENMASK(31, 26)
+#define GDMA4_SGMII1_TX_FRAG_SIZE	GENMASK(25, 16)
+#define GDMA4_SGMII0_TX_WEIGHT		GENMASK(15, 10)
+#define GDMA4_SGMII0_TX_FRAG_SIZE	GENMASK(9, 0)
+
+#define REG_GDMA4_RMBI_FRAG		0x202c
+#define GDMA4_SGMII1_RX_WEIGHT		GENMASK(31, 26)
+#define GDMA4_SGMII1_RX_FRAG_SIZE	GENMASK(25, 16)
+#define GDMA4_SGMII0_RX_WEIGHT		GENMASK(15, 10)
+#define GDMA4_SGMII0_RX_FRAG_SIZE	GENMASK(9, 0)
+
 #define REG_MC_VLAN_EN			0x2100
 #define MC_VLAN_EN_MASK			BIT(0)
 
-- 
2.48.1



From frank-w at public-files.de  Sat May 10 04:35:56 2025
From: frank-w at public-files.de (Frank Wunderlich)
Date: Sat, 10 May 2025 11:35:56 +0000
Subject: Aw: [PATCH v4 0/8] Add Bananapi R4 variants and add xsphy
In-Reply-To: <20250422132438.15735-1-linux@fw-web.de>
References: <20250422132438.15735-1-linux@fw-web.de>
Message-ID: <trinity-02bca72f-3997-456e-8182-d5ef1358ac9f-1746876955936@trinity-msg-rest-gmx-gmx-live-74d694d854-5prkz>

Hi

just a gentle ping. is something missing or can this series be applied?

regards Frank


From lorenzo at kernel.org  Sat May 10 05:23:20 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Sat, 10 May 2025 14:23:20 +0200
Subject: [net-next PATCH v3 11/11] net: airoha: add phylink support for
 GDM2/3/4
In-Reply-To: <20250510102348.14134-12-ansuelsmth@gmail.com>
References: <20250510102348.14134-1-ansuelsmth@gmail.com>
 <20250510102348.14134-12-ansuelsmth@gmail.com>
Message-ID: <aB9FOFYEHueMe5L3@lore-desk>

> Add phylink support for GDM2/3/4 port that require configuration of the
> PCS to make the external PHY or attached SFP cage work.
> 
> These needs to be defined in the GDM port node using the pcs-handle
> property.

Hi Christian,

thx for the patch. Some comments inline.

Regards,
Lorenzo

> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---
>  drivers/net/ethernet/airoha/airoha_eth.c  | 138 ++++++++++++++++++++++
>  drivers/net/ethernet/airoha/airoha_eth.h  |   3 +
>  drivers/net/ethernet/airoha/airoha_regs.h |  12 ++
>  3 files changed, 153 insertions(+)
> 
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index 16c7896f931f..17521be820b5 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -7,6 +7,7 @@
>  #include <linux/of_net.h>
>  #include <linux/platform_device.h>
>  #include <linux/tcp.h>
> +#include <linux/pcs/pcs.h>
>  #include <linux/u64_stats_sync.h>
>  #include <net/dst_metadata.h>
>  #include <net/page_pool/helpers.h>
> @@ -79,6 +80,11 @@ static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
>  	return port->id == 1;
>  }
>  
> +static bool airhoa_is_phy_external(struct airoha_gdm_port *port)
> +{
> +	return port->id != 1;
> +}
> +
>  static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
>  {
>  	struct airoha_eth *eth = port->qdma->eth;
> @@ -1613,6 +1619,17 @@ static int airoha_dev_open(struct net_device *dev)
>  	struct airoha_gdm_port *port = netdev_priv(dev);
>  	struct airoha_qdma *qdma = port->qdma;
>  
> +	if (airhoa_is_phy_external(port)) {
> +		err = phylink_of_phy_connect(port->phylink, dev->dev.of_node, 0);
> +		if (err) {
> +			netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
> +				   err);
> +			return err;
> +		}
> +
> +		phylink_start(port->phylink);
> +	}
> +
>  	netif_tx_start_all_queues(dev);
>  	err = airoha_set_vip_for_gdm_port(port, true);
>  	if (err)
> @@ -1665,6 +1682,11 @@ static int airoha_dev_stop(struct net_device *dev)
>  		}
>  	}
>  
> +	if (airhoa_is_phy_external(port)) {
> +		phylink_stop(port->phylink);
> +		phylink_disconnect_phy(port->phylink);
> +	}
> +
>  	return 0;
>  }
>  
> @@ -2795,6 +2817,110 @@ bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
>  	return false;
>  }
>  
> +static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,
> +			       unsigned int mode, phy_interface_t interface,
> +			       int speed, int duplex, bool tx_pause, bool rx_pause)
> +{
> +	struct airoha_gdm_port *port = container_of(config, struct airoha_gdm_port,
> +						    phylink_config);
> +	struct airoha_qdma *qdma = port->qdma;
> +	struct airoha_eth *eth = qdma->eth;
> +	u32 frag_size_tx, frag_size_rx;

I guess we can just return here if port->id != 4 and avoid setting
frag_size_tx/frag_size_rx

> +
> +	switch (speed) {
> +	case SPEED_10000:
> +	case SPEED_5000:
> +		frag_size_tx = 8;
> +		frag_size_rx = 8;
> +		break;
> +	case SPEED_2500:
> +		frag_size_tx = 2;
> +		frag_size_rx = 1;
> +		break;
> +	default:
> +		frag_size_tx = 1;
> +		frag_size_rx = 0;
> +	}
> +
> +	/* Configure TX/RX frag based on speed */
> +	if (port->id == 4) {
> +		airoha_fe_rmw(eth, REG_GDMA4_TMBI_FRAG, GDMA4_SGMII0_TX_FRAG_SIZE,
> +			      FIELD_PREP(GDMA4_SGMII0_TX_FRAG_SIZE, frag_size_tx));
> +
> +		airoha_fe_rmw(eth, REG_GDMA4_RMBI_FRAG, GDMA4_SGMII0_RX_FRAG_SIZE,
> +			      FIELD_PREP(GDMA4_SGMII0_RX_FRAG_SIZE, frag_size_rx));
> +	}
> +}
> +
> +static const struct phylink_mac_ops airoha_phylink_ops = {
> +	.mac_link_up = airoha_mac_link_up,
> +};
> +
> +static int airoha_setup_phylink(struct net_device *dev)
> +{
> +	struct airoha_gdm_port *port = netdev_priv(dev);
> +	struct device_node *np = dev->dev.of_node;
> +	struct phylink_pcs **available_pcs;
> +	phy_interface_t phy_mode;
> +	struct phylink *phylink;
> +	unsigned int num_pcs;
> +	int err;
> +
> +	err = of_get_phy_mode(np, &phy_mode);
> +	if (err) {
> +		dev_err(&dev->dev, "incorrect phy-mode\n");
> +		return err;
> +	}
> +
> +	port->phylink_config.dev = &dev->dev;
> +	port->phylink_config.type = PHYLINK_NETDEV;
> +	port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
> +						MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD |
> +						MAC_5000FD | MAC_10000FD;
> +
> +	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), NULL, &num_pcs);
> +	if (err)
> +		return err;
> +
> +	available_pcs = kcalloc(num_pcs, sizeof(*available_pcs), GFP_KERNEL);
> +	if (!available_pcs)
> +		return -ENOMEM;

since airoha_setup_phylink() is just run in the following path:

airoha_probe() -> airoha_alloc_gdm_port()

we can use devm_kcalloc() and get rid of the kfree and the end of the routine.

> +
> +	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), available_pcs,
> +				       &num_pcs);
> +	if (err)
> +		goto out;
> +
> +	port->phylink_config.available_pcs = available_pcs;
> +	port->phylink_config.num_available_pcs = num_pcs;
> +
> +	__set_bit(PHY_INTERFACE_MODE_SGMII,
> +		  port->phylink_config.supported_interfaces);
> +	__set_bit(PHY_INTERFACE_MODE_1000BASEX,
> +		  port->phylink_config.supported_interfaces);
> +	__set_bit(PHY_INTERFACE_MODE_2500BASEX,
> +		  port->phylink_config.supported_interfaces);
> +	__set_bit(PHY_INTERFACE_MODE_USXGMII,
> +		  port->phylink_config.supported_interfaces);
> +
> +	phy_interface_copy(port->phylink_config.pcs_interfaces,
> +			   port->phylink_config.supported_interfaces);
> +
> +	phylink = phylink_create(&port->phylink_config,
> +				 of_fwnode_handle(np),
> +				 phy_mode, &airoha_phylink_ops);
> +	if (IS_ERR(phylink)) {
> +		err = PTR_ERR(phylink);
> +		goto out;
> +	}
> +
> +	port->phylink = phylink;
> +out:
> +	kfree(available_pcs);
> +
> +	return err;
> +}
> +
>  static int airoha_alloc_gdm_port(struct airoha_eth *eth,
>  				 struct device_node *np, int index)
>  {
> @@ -2873,6 +2999,12 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
>  	if (err)
>  		return err;
>  
> +	if (airhoa_is_phy_external(port)) {
> +		err = airoha_setup_phylink(dev);
> +		if (err)
> +			return err;
> +	}
> +
>  	return register_netdev(dev);

we should run phylink_destroy() if register_netdev() fails. Please take a
look to:

https://lore.kernel.org/netdev/aB8MPkMYXWvoaA03 at lore-desk/T/#m0a036b0759384a38d2518025db46306858b5707b

>  }
>  
> @@ -2967,6 +3099,9 @@ static int airoha_probe(struct platform_device *pdev)
>  		struct airoha_gdm_port *port = eth->ports[i];
>  
>  		if (port && port->dev->reg_state == NETREG_REGISTERED) {
> +			if (airhoa_is_phy_external(port))
> +				phylink_destroy(port->phylink);
> +
>  			unregister_netdev(port->dev);
>  			airoha_metadata_dst_free(port);
>  		}
> @@ -2994,6 +3129,9 @@ static void airoha_remove(struct platform_device *pdev)
>  			continue;
>  
>  		airoha_dev_stop(port->dev);
> +		if (airhoa_is_phy_external(port))
> +			phylink_destroy(port->phylink);
> +
>  		unregister_netdev(port->dev);
>  		airoha_metadata_dst_free(port);
>  	}
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
> index 53f39083a8b0..73a500474076 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.h
> +++ b/drivers/net/ethernet/airoha/airoha_eth.h
> @@ -498,6 +498,9 @@ struct airoha_gdm_port {
>  	struct net_device *dev;
>  	int id;
>  
> +	struct phylink *phylink;
> +	struct phylink_config phylink_config;
> +
>  	struct airoha_hw_stats stats;
>  
>  	DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
> diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
> index d931530fc96f..71c63108f0a8 100644
> --- a/drivers/net/ethernet/airoha/airoha_regs.h
> +++ b/drivers/net/ethernet/airoha/airoha_regs.h
> @@ -357,6 +357,18 @@
>  #define IP_FRAGMENT_PORT_MASK		GENMASK(8, 5)
>  #define IP_FRAGMENT_NBQ_MASK		GENMASK(4, 0)
>  
> +#define REG_GDMA4_TMBI_FRAG		0x2028
> +#define GDMA4_SGMII1_TX_WEIGHT		GENMASK(31, 26)
> +#define GDMA4_SGMII1_TX_FRAG_SIZE	GENMASK(25, 16)
> +#define GDMA4_SGMII0_TX_WEIGHT		GENMASK(15, 10)
> +#define GDMA4_SGMII0_TX_FRAG_SIZE	GENMASK(9, 0)

in order to be consistent with the codebase, can you please add _MASK suffix
here?

> +
> +#define REG_GDMA4_RMBI_FRAG		0x202c
> +#define GDMA4_SGMII1_RX_WEIGHT		GENMASK(31, 26)
> +#define GDMA4_SGMII1_RX_FRAG_SIZE	GENMASK(25, 16)
> +#define GDMA4_SGMII0_RX_WEIGHT		GENMASK(15, 10)
> +#define GDMA4_SGMII0_RX_FRAG_SIZE	GENMASK(9, 0)
> +
>  #define REG_MC_VLAN_EN			0x2100
>  #define MC_VLAN_EN_MASK			BIT(0)
>  
> -- 
> 2.48.1
> 
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From lkp at intel.com  Sat May 10 06:37:53 2025
From: lkp at intel.com (kernel test robot)
Date: Sat, 10 May 2025 21:37:53 +0800
Subject: [PATCH 2/2] wifi: mt76: mt7925: add test mode support
In-Reply-To: <20250505233618.1951021-2-sean.wang@kernel.org>
References: <20250505233618.1951021-2-sean.wang@kernel.org>
Message-ID: <202505102153.oOZ0YXsZ-lkp@intel.com>

Hi,

kernel test robot noticed the following build warnings:

[auto build test WARNING on wireless-next/main]
[also build test WARNING on wireless/main linus/master v6.15-rc5 next-20250509]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/sean-wang-kernel-org/wifi-mt76-mt7925-add-test-mode-support/20250506-115641
base:   https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next.git main
patch link:    https://lore.kernel.org/r/20250505233618.1951021-2-sean.wang%40kernel.org
patch subject: [PATCH 2/2] wifi: mt76: mt7925: add test mode support
config: loongarch-allyesconfig (https://download.01.org/0day-ci/archive/20250510/202505102153.oOZ0YXsZ-lkp at intel.com/config)
compiler: loongarch64-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250510/202505102153.oOZ0YXsZ-lkp at intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505102153.oOZ0YXsZ-lkp at intel.com/

All warnings (new ones prefixed by >>):

   drivers/net/wireless/mediatek/mt76/mt7925/testmode.c: In function 'mt7925_tm_query':
>> drivers/net/wireless/mediatek/mt76/mt7925/testmode.c:92:38: warning: variable 'evt' set but not used [-Wunused-but-set-variable]
      92 |         struct uni_cmd_testmode_evt *evt;
         |                                      ^~~


vim +/evt +92 drivers/net/wireless/mediatek/mt76/mt7925/testmode.c

    85	
    86	static int
    87	mt7925_tm_query(struct mt792x_dev *dev, struct mt7925_tm_cmd *req,
    88			char *evt_resp)
    89	{
    90		struct mt7925_rftest_cmd cmd;
    91		char *pcmd = (char *)&cmd;
  > 92		struct uni_cmd_testmode_evt *evt;
    93		struct sk_buff *skb = NULL;
    94		int ret = 1;
    95	
    96		memset(pcmd, 0, sizeof(*pcmd));
    97		memcpy(pcmd + 4, (char *)&req->c, sizeof(struct uni_cmd_testmode_ctrl));
    98	
    99		if (*((uint16_t *)req->padding) == MCU_UNI_CMD_TESTMODE_CTRL)
   100			ret = mt76_mcu_send_and_get_msg(&dev->mt76, MCU_UNI_QUERY(TESTMODE_CTRL),
   101							&cmd, sizeof(cmd), true, &skb);
   102		else if (*((uint16_t *)req->padding) == MCU_UNI_CMD_TESTMODE_RX_STAT)
   103			ret = mt76_mcu_send_and_get_msg(&dev->mt76, MCU_UNI_QUERY(TESTMODE_RX_STAT),
   104							&cmd, sizeof(cmd), true, &skb);
   105	
   106		if (ret)
   107			goto out;
   108	
   109		evt = (struct uni_cmd_testmode_evt *)skb->data;
   110	
   111		memcpy((char *)evt_resp, (char *)skb->data + 8, MT7925_EVT_RSP_LEN);
   112	
   113	out:
   114		dev_kfree_skb(skb);
   115	
   116		return ret;
   117	}
   118	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki


From lkp at intel.com  Sat May 10 10:26:50 2025
From: lkp at intel.com (kernel test robot)
Date: Sun, 11 May 2025 01:26:50 +0800
Subject: [net-next PATCH v3 11/11] net: airoha: add phylink support for
 GDM2/3/4
In-Reply-To: <20250510102348.14134-12-ansuelsmth@gmail.com>
References: <20250510102348.14134-12-ansuelsmth@gmail.com>
Message-ID: <202505110156.WGym4cxS-lkp@intel.com>

Hi Christian,

kernel test robot noticed the following build warnings:

[auto build test WARNING on net-next/main]

url:    https://github.com/intel-lab-lkp/linux/commits/Christian-Marangi/net-phylink-keep-and-use-MAC-supported_interfaces-in-phylink-struct/20250510-182833
base:   net-next/main
patch link:    https://lore.kernel.org/r/20250510102348.14134-12-ansuelsmth%40gmail.com
patch subject: [net-next PATCH v3 11/11] net: airoha: add phylink support for GDM2/3/4
config: sh-randconfig-002-20250510 (https://download.01.org/0day-ci/archive/20250511/202505110156.WGym4cxS-lkp at intel.com/config)
compiler: sh4-linux-gcc (GCC) 11.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250511/202505110156.WGym4cxS-lkp at intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505110156.WGym4cxS-lkp at intel.com/

All warnings (new ones prefixed by >>):

   In file included from drivers/net/ethernet/airoha/airoha_eth.c:10:
>> include/linux/pcs/pcs.h:90:1: warning: 'fwnode_phylink_pcs_get_from_fwnode' defined but not used [-Wunused-function]
      90 | fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
         | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> include/linux/pcs/pcs.h:78:12: warning: 'register_fwnode_pcs_notifier' defined but not used [-Wunused-function]
      78 | static int register_fwnode_pcs_notifier(struct notifier_block *nb)
         |            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~


vim +/fwnode_phylink_pcs_get_from_fwnode +90 include/linux/pcs/pcs.h

91110a42083f1a Christian Marangi 2025-05-10  24  
90fbe52edd2a1f Christian Marangi 2025-05-10  25  /**
90fbe52edd2a1f Christian Marangi 2025-05-10  26   * fwnode_pcs_get - Retrieves a PCS from a firmware node
90fbe52edd2a1f Christian Marangi 2025-05-10  27   * @fwnode: firmware node
90fbe52edd2a1f Christian Marangi 2025-05-10  28   * @index: index fwnode PCS handle in firmware node
90fbe52edd2a1f Christian Marangi 2025-05-10  29   *
90fbe52edd2a1f Christian Marangi 2025-05-10  30   * Get a PCS from the firmware node at index.
90fbe52edd2a1f Christian Marangi 2025-05-10  31   *
90fbe52edd2a1f Christian Marangi 2025-05-10  32   * Returns a pointer to the phylink_pcs or a negative
90fbe52edd2a1f Christian Marangi 2025-05-10  33   * error pointer. Can return -EPROBE_DEFER if the PCS is not
90fbe52edd2a1f Christian Marangi 2025-05-10  34   * present in global providers list (either due to driver
90fbe52edd2a1f Christian Marangi 2025-05-10  35   * still needs to be probed or it failed to probe/removed)
90fbe52edd2a1f Christian Marangi 2025-05-10  36   */
90fbe52edd2a1f Christian Marangi 2025-05-10  37  struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
90fbe52edd2a1f Christian Marangi 2025-05-10  38  				   int index);
90fbe52edd2a1f Christian Marangi 2025-05-10  39  
91110a42083f1a Christian Marangi 2025-05-10  40  /**
91110a42083f1a Christian Marangi 2025-05-10  41   * fwnode_phylink_pcs_get_from_fwnode - Retrieves the PCS provided
91110a42083f1a Christian Marangi 2025-05-10  42   *					by the firmware node from a
91110a42083f1a Christian Marangi 2025-05-10  43   *					firmware node
91110a42083f1a Christian Marangi 2025-05-10  44   * @fwnode: firmware node
91110a42083f1a Christian Marangi 2025-05-10  45   * @pcs_fwnode: PCS firmware node
91110a42083f1a Christian Marangi 2025-05-10  46   *
91110a42083f1a Christian Marangi 2025-05-10  47   * Parse 'pcs-handle' in 'fwnode' and get the PCS that match
91110a42083f1a Christian Marangi 2025-05-10  48   * 'pcs_fwnode' firmware node.
91110a42083f1a Christian Marangi 2025-05-10  49   *
91110a42083f1a Christian Marangi 2025-05-10  50   * Returns a pointer to the phylink_pcs or a negative
91110a42083f1a Christian Marangi 2025-05-10  51   * error pointer. Can return -EPROBE_DEFER if the PCS is not
91110a42083f1a Christian Marangi 2025-05-10  52   * present in global providers list (either due to driver
91110a42083f1a Christian Marangi 2025-05-10  53   * still needs to be probed or it failed to probe/removed)
91110a42083f1a Christian Marangi 2025-05-10  54   */
91110a42083f1a Christian Marangi 2025-05-10  55  struct phylink_pcs *
91110a42083f1a Christian Marangi 2025-05-10  56  fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
91110a42083f1a Christian Marangi 2025-05-10  57  				   struct fwnode_handle *pcs_fwnode);
91110a42083f1a Christian Marangi 2025-05-10  58  
90fbe52edd2a1f Christian Marangi 2025-05-10  59  /**
90fbe52edd2a1f Christian Marangi 2025-05-10  60   * fwnode_phylink_pcs_parse - generic PCS parse for fwnode PCS provider
90fbe52edd2a1f Christian Marangi 2025-05-10  61   * @fwnode: firmware node
90fbe52edd2a1f Christian Marangi 2025-05-10  62   * @available_pcs: pointer to preallocated array of PCS
90fbe52edd2a1f Christian Marangi 2025-05-10  63   * @num_pcs: where to store count of parsed PCS
90fbe52edd2a1f Christian Marangi 2025-05-10  64   *
90fbe52edd2a1f Christian Marangi 2025-05-10  65   * Generic helper function to fill available_pcs array with PCS parsed
90fbe52edd2a1f Christian Marangi 2025-05-10  66   * from a "pcs-handle" fwnode property defined in firmware node up to
90fbe52edd2a1f Christian Marangi 2025-05-10  67   * passed num_pcs.
90fbe52edd2a1f Christian Marangi 2025-05-10  68   *
90fbe52edd2a1f Christian Marangi 2025-05-10  69   * If available_pcs is NULL, num_pcs is updated with the count of the
90fbe52edd2a1f Christian Marangi 2025-05-10  70   * parsed PCS.
90fbe52edd2a1f Christian Marangi 2025-05-10  71   *
90fbe52edd2a1f Christian Marangi 2025-05-10  72   * Returns 0 or a negative error.
90fbe52edd2a1f Christian Marangi 2025-05-10  73   */
90fbe52edd2a1f Christian Marangi 2025-05-10  74  int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
90fbe52edd2a1f Christian Marangi 2025-05-10  75  			     struct phylink_pcs **available_pcs,
90fbe52edd2a1f Christian Marangi 2025-05-10  76  			     unsigned int *num_pcs);
90fbe52edd2a1f Christian Marangi 2025-05-10  77  #else
91110a42083f1a Christian Marangi 2025-05-10 @78  static int register_fwnode_pcs_notifier(struct notifier_block *nb)
91110a42083f1a Christian Marangi 2025-05-10  79  {
91110a42083f1a Christian Marangi 2025-05-10  80  	return -EOPNOTSUPP;
91110a42083f1a Christian Marangi 2025-05-10  81  }
91110a42083f1a Christian Marangi 2025-05-10  82  
90fbe52edd2a1f Christian Marangi 2025-05-10  83  static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
90fbe52edd2a1f Christian Marangi 2025-05-10  84  						 int index)
90fbe52edd2a1f Christian Marangi 2025-05-10  85  {
90fbe52edd2a1f Christian Marangi 2025-05-10  86  	return ERR_PTR(-ENOENT);
90fbe52edd2a1f Christian Marangi 2025-05-10  87  }
90fbe52edd2a1f Christian Marangi 2025-05-10  88  
91110a42083f1a Christian Marangi 2025-05-10  89  static struct phylink_pcs *
91110a42083f1a Christian Marangi 2025-05-10 @90  fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
91110a42083f1a Christian Marangi 2025-05-10  91  				   struct fwnode_handle *pcs_fwnode)
91110a42083f1a Christian Marangi 2025-05-10  92  {
91110a42083f1a Christian Marangi 2025-05-10  93  	return ERR_PTR(-ENOENT);
91110a42083f1a Christian Marangi 2025-05-10  94  }
91110a42083f1a Christian Marangi 2025-05-10  95  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki


From linux at fw-web.de  Sat May 10 10:49:32 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Sat, 10 May 2025 19:49:32 +0200
Subject: [net-next, PATCH v2] net: phy: mediatek: do not require syscon compatible for pio property
Message-ID: <20250510174933.154589-1-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Current implementation requires syscon compatible for pio property
which is used for driving the switch leds on mt7988.

Replace syscon_regmap_lookup_by_phandle with of_parse_phandle and
device_node_to_regmap to get the regmap already assigned by pinctrl
driver.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---

v2:
- out of RFC

---
 drivers/net/phy/mediatek/mtk-ge-soc.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediatek/mtk-ge-soc.c
index 175cf5239bba..21975ef946d5 100644
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -7,6 +7,7 @@
 #include <linux/pinctrl/consumer.h>
 #include <linux/phy.h>
 #include <linux/regmap.h>
+#include <linux/of.h>
 
 #include "../phylib.h"
 #include "mtk.h"
@@ -1319,6 +1320,7 @@ static int mt7988_phy_probe_shared(struct phy_device *phydev)
 {
 	struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
 	struct mtk_socphy_shared *shared = phy_package_get_priv(phydev);
+	struct device_node *pio_np;
 	struct regmap *regmap;
 	u32 reg;
 	int ret;
@@ -1336,7 +1338,13 @@ static int mt7988_phy_probe_shared(struct phy_device *phydev)
 	 * The 4 bits in TPBANK0 are kept as package shared data and are used to
 	 * set LED polarity for each of the LED0.
 	 */
-	regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
+	pio_np = of_parse_phandle(np, "mediatek,pio", 0);
+	if (!pio_np)
+		return -ENODEV;
+
+	regmap = device_node_to_regmap(pio_np);
+	of_node_put(pio_np);
+
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
-- 
2.43.0



From sam8641 at gmail.com  Sat May 10 17:53:09 2025
From: sam8641 at gmail.com (Samuel Williams)
Date: Sat, 10 May 2025 19:53:09 -0500
Subject: [PATCH] wifi: mt76: mt7921: add 160 MHz AP for mt7922 device
Message-ID: <20250511005316.1118961-1-sam8641@gmail.com>

This allows mt7922 in hostapd mode to transmit up to 1.4 Gbps.

Signed-off-by: Samuel Williams <sam8641 at gmail.com>
---
 drivers/net/wireless/mediatek/mt76/mt7921/main.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/main.c b/drivers/net/wireless/mediatek/mt76/mt7921/main.c
index 826c48a2ee69..1fffa43379b2 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7921/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7921/main.c
@@ -83,6 +83,11 @@ mt7921_init_he_caps(struct mt792x_phy *phy, enum nl80211_band band,
 			he_cap_elem->phy_cap_info[9] |=
 				IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
 				IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
+
+			if (is_mt7922(phy->mt76->dev)) {
+				he_cap_elem->phy_cap_info[0] |=
+					IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
+			}
 			break;
 		case NL80211_IFTYPE_STATION:
 			he_cap_elem->mac_cap_info[1] |=
-- 
2.47.2



From linux at fw-web.de  Sun May 11 07:19:16 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:19:16 +0200
Subject: [PATCH v1 00/14] further mt7988 devicetree work
Message-ID: <20250511141942.10284-1-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

This series continues mt7988 devicetree work

- Add SPI with BPI-R4 nand to reach eMMC
- Add thermal protection (fan+cooling-points)
- Extend cpu frequency scaling with CCI
- Basic network-support (ethernet controller + builtin switch + SFP Cages)

depencies (i hope this list is complete and latest patches/series linked):

"Add Bananapi R4 variants and add xsphy" (reviewed, but not yet applied):
https://patchwork.kernel.org/project/linux-mediatek/list/?series=955733

"net: phy: mediatek: do not require syscon compatible for pio property":
https://patchwork.kernel.org/project/netdevbpf/patch/20250510174933.154589-1-linux at fw-web.de/
for phy led function (RFC not yet reviewed, resent without RFC)

for 2.5g phy function (currently disabled):
- net: ethernet: mtk_eth_soc: add support for MT7988 internal 2.5G PHY (already merged to 6.15-net-next)
- net: phy: mediatek: add driver for built-in 2.5G ethernet PHY on MT7988
  https://patchwork.kernel.org/project/netdevbpf/patch/20250219083910.2255981-4-SkyLake.Huang at mediatek.com/
  requested updated patch due to comments

for SFP-Function (macs currently disabled):

PCS clearance which is a 1.5 year discussion currently ongoing

e.g. something like this (one of):
* https://patchwork.kernel.org/project/netdevbpf/patch/20250510102348.14134-4-ansuelsmth at gmail.com/ 
  (changes requested, but no comment on the pcs part)
* https://patchwork.kernel.org/project/netdevbpf/patch/20250415193323.2794214-3-sean.anderson at linux.dev/
  (changes requested)
* https://patchwork.kernel.org/project/netdevbpf/patch/ba4e359584a6b3bc4b3470822c42186d5b0856f9.1721910728.git.daniel at makrotopia.org/

full usxgmii driver:
https://patchwork.kernel.org/project/netdevbpf/patch/07845ec900ba41ff992875dce12c622277592c32.1702352117.git.daniel at makrotopia.org/

first PCS-discussion is here:
https://patchwork.kernel.org/project/netdevbpf/patch/8aa905080bdb6760875d62cb3b2b41258837f80e.1702352117.git.daniel at makrotopia.org/

and then dts nodes for sgmiisys+usxgmii

when above depencies are solved the mac1+2 can be enabled and 2.5G phy and SFP slots will work.

Frank Wunderlich (14):
  dt-bindings: net: mediatek,net: update for mt7988
  dt-bindings: net: dsa: mediatek,mt7530: add dsa-port definition for
    mt7988
  dt-bindings: net: dsa: mediatek,mt7530: add internal mdio bus
  arm64: dts: mediatek: mt7988: add spi controllers
  arm64: dts: mediatek: mt7988: move uart0 and spi1 pins to soc dtsi
  arm64: dts: mediatek: mt7988: add cci node
  arm64: dts: mediatek: mt7988: add phy calibration efuse subnodes
  arm64: dts: mediatek: mt7988: add basic ethernet-nodes
  arm64: dts: mediatek: mt7988: add switch node
  arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and coolingmaps
  arm64: dts: mediatek: mt7988a-bpi-r4: configure spi-nodes
  arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply for cci
  arm64: dts: mediatek: mt7988a-bpi-r4: add sfp cages and link to gmac
  arm64: dts: mediatek: mt7988a-bpi-r4: configure switch phys and leds

 .../bindings/net/dsa/mediatek,mt7530.yaml     |  17 +-
 .../devicetree/bindings/net/mediatek,net.yaml |   9 +-
 .../mediatek/mt7988a-bananapi-bpi-r4-2g5.dts  |  11 +
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts  |  18 +
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 137 +++++-
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi     | 402 +++++++++++++++++-
 6 files changed, 574 insertions(+), 20 deletions(-)

-- 
2.43.0



From linux at fw-web.de  Sun May 11 07:19:22 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:19:22 +0200
Subject: [PATCH v1 06/14] arm64: dts: mediatek: mt7988: add cci node
In-Reply-To: <20250511141942.10284-1-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
Message-ID: <20250511141942.10284-7-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Add cci devicetree node for cpu frequency scaling.

Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index ab6fc09940b8..64466acb0e71 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -12,6 +12,35 @@ / {
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	cci: cci {
+		compatible = "mediatek,mt8183-cci";
+		clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
+			 <&topckgen CLK_TOP_XTAL>;
+		clock-names = "cci", "intermediate";
+		operating-points-v2 = <&cci_opp>;
+	};
+
+	cci_opp: opp-table-cci {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp-480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <850000>;
+		};
+		opp-660000000 {
+			opp-hz = /bits/ 64 <660000000>;
+			opp-microvolt = <850000>;
+		};
+		opp-900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = <850000>;
+		};
+		opp-1080000000 {
+			opp-hz = /bits/ 64 <1080000000>;
+			opp-microvolt = <900000>;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -25,6 +54,7 @@ cpu0: cpu at 0 {
 				 <&topckgen CLK_TOP_XTAL>;
 			clock-names = "cpu", "intermediate";
 			operating-points-v2 = <&cluster0_opp>;
+			mediatek,cci = <&cci>;
 		};
 
 		cpu1: cpu at 1 {
@@ -36,6 +66,7 @@ cpu1: cpu at 1 {
 				 <&topckgen CLK_TOP_XTAL>;
 			clock-names = "cpu", "intermediate";
 			operating-points-v2 = <&cluster0_opp>;
+			mediatek,cci = <&cci>;
 		};
 
 		cpu2: cpu at 2 {
@@ -47,6 +78,7 @@ cpu2: cpu at 2 {
 				 <&topckgen CLK_TOP_XTAL>;
 			clock-names = "cpu", "intermediate";
 			operating-points-v2 = <&cluster0_opp>;
+			mediatek,cci = <&cci>;
 		};
 
 		cpu3: cpu at 3 {
@@ -58,6 +90,7 @@ cpu3: cpu at 3 {
 				 <&topckgen CLK_TOP_XTAL>;
 			clock-names = "cpu", "intermediate";
 			operating-points-v2 = <&cluster0_opp>;
+			mediatek,cci = <&cci>;
 		};
 
 		cluster0_opp: opp-table-0 {
-- 
2.43.0



From linux at fw-web.de  Sun May 11 07:19:18 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:19:18 +0200
Subject: [PATCH v1 02/14] dt-bindings: net: dsa: mediatek,mt7530: add dsa-port definition for mt7988
In-Reply-To: <20250511141942.10284-1-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
Message-ID: <20250511141942.10284-3-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Add own dsa-port binding for SoC with internal switch where only phy-mode
'internal' is valid.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 .../bindings/net/dsa/mediatek,mt7530.yaml          | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
index ea979bcae1d6..bb22c36749fc 100644
--- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
+++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
@@ -186,6 +186,18 @@ required:
   - reg
 
 $defs:
+  builtin-dsa-port:
+    patternProperties:
+      "^(ethernet-)?ports$":
+        patternProperties:
+          "^(ethernet-)?port@[0-6]$":
+            if:
+              required: [ ethernet ]
+            then:
+              properties:
+                phy-mode:
+                  const: internal
+
   mt7530-dsa-port:
     patternProperties:
       "^(ethernet-)?ports$":
@@ -292,7 +304,7 @@ allOf:
             - mediatek,mt7988-switch
             - airoha,en7581-switch
     then:
-      $ref: "#/$defs/mt7530-dsa-port"
+      $ref: "#/$defs/builtin-dsa-port"
       properties:
         gpio-controller: false
         mediatek,mcm: false
-- 
2.43.0



From linux at fw-web.de  Sun May 11 07:19:19 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:19:19 +0200
Subject: [PATCH v1 03/14] dt-bindings: net: dsa: mediatek,mt7530: add internal mdio bus
In-Reply-To: <20250511141942.10284-1-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
Message-ID: <20250511141942.10284-4-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Mt7988 buildin switch has own mdio bus where ge-phys are connected.
Add related property for this.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
index bb22c36749fc..5f1363278f43 100644
--- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
+++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
@@ -156,6 +156,9 @@ properties:
     maxItems: 1
 
 patternProperties:
+  "^mdio(-bus)?$":
+    $ref: /schemas/net/mdio.yaml#
+
   "^(ethernet-)?ports$":
     type: object
     additionalProperties: true
-- 
2.43.0



From linux at fw-web.de  Sun May 11 07:19:21 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:19:21 +0200
Subject: [PATCH v1 05/14] arm64: dts: mediatek: mt7988: move uart0 and spi1 pins to soc dtsi
In-Reply-To: <20250511141942.10284-1-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
Message-ID: <20250511141942.10284-6-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

In order to use uart0 or spi1 there is only 1 possible pin definition
so move them to soc dtsi to reuse them in other boards and avoiding
conflict if defined twice.

Suggested-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi  | 14 --------------
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi      | 18 ++++++++++++++++++
 2 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index 37e541a98ee1..23b267cd47ac 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -328,13 +328,6 @@ mux {
 		};
 	};
 
-	uart0_pins: uart0-pins {
-		mux {
-			function = "uart";
-			groups =  "uart0";
-		};
-	};
-
 	snfi_pins: snfi-pins {
 		mux {
 			function = "flash";
@@ -356,13 +349,6 @@ mux {
 		};
 	};
 
-	spi1_pins: spi1-pins {
-		mux {
-			function = "spi";
-			groups = "spi1";
-		};
-	};
-
 	spi2_pins: spi2-pins {
 		mux {
 			function = "spi";
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 8c31935f4ab0..ab6fc09940b8 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -209,6 +209,20 @@ mux {
 						 "pcie_wake_n3_0";
 				};
 			};
+
+			spi1_pins: spi1-pins {
+				mux {
+					function = "spi";
+					groups = "spi1";
+				};
+			};
+
+			uart0_pins: uart0-pins {
+				mux {
+					function = "uart";
+					groups =  "uart0";
+				};
+			};
 		};
 
 		pwm: pwm at 10048000 {
@@ -244,6 +258,8 @@ serial0: serial at 11000000 {
 			clocks = <&topckgen CLK_TOP_UART_SEL>,
 				 <&infracfg CLK_INFRA_52M_UART0_CK>;
 			clock-names = "baud", "bus";
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_pins>;
 			status = "disabled";
 		};
 
@@ -338,6 +354,8 @@ spi1: spi at 11008000 {
 				      "hclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi1_pins>;
 			status = "disabled";
 		};
 
-- 
2.43.0



From linux at fw-web.de  Sun May 11 07:19:17 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:19:17 +0200
Subject: [PATCH v1 01/14] dt-bindings: net: mediatek,net: update for mt7988
In-Reply-To: <20250511141942.10284-1-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
Message-ID: <20250511141942.10284-2-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Update binding for mt7988 which has 3 gmac and 2 reg items.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 Documentation/devicetree/bindings/net/mediatek,net.yaml | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml
index 9e02fd80af83..5d249da02c3a 100644
--- a/Documentation/devicetree/bindings/net/mediatek,net.yaml
+++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml
@@ -28,7 +28,8 @@ properties:
       - ralink,rt5350-eth
 
   reg:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
 
   clocks:
     minItems: 2
@@ -381,8 +382,12 @@ allOf:
             - const: xgp2
             - const: xgp3
 
+        reg:
+          minItems: 2
+          maxItems: 2
+
 patternProperties:
-  "^mac@[0-1]$":
+  "^mac@[0-2]$":
     type: object
     unevaluatedProperties: false
     allOf:
-- 
2.43.0



From linux at fw-web.de  Sun May 11 07:19:25 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:19:25 +0200
Subject: [PATCH v1 09/14] arm64: dts: mediatek: mt7988: add switch node
In-Reply-To: <20250511141942.10284-1-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
Message-ID: <20250511141942.10284-10-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Add mt7988 builtin mt753x switch nodes.

Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 166 ++++++++++++++++++++++
 1 file changed, 166 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index aa0947a555aa..ab7612916a13 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -5,6 +5,7 @@
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/pinctrl/mt65xx.h>
 #include <dt-bindings/reset/mediatek,mt7988-resets.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "mediatek,mt7988a";
@@ -742,6 +743,171 @@ ethsys: clock-controller at 15000000 {
 			#reset-cells = <1>;
 		};
 
+		switch: switch at 15020000 {
+			compatible = "mediatek,mt7988-switch";
+			reg = <0 0x15020000 0 0x8000>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				gsw_port0: port at 0 {
+					reg = <0>;
+					label = "wan";
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy0>;
+				};
+
+				gsw_port1: port at 1 {
+					reg = <1>;
+					label = "lan1";
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy1>;
+				};
+
+				gsw_port2: port at 2 {
+					reg = <2>;
+					label = "lan2";
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy2>;
+				};
+
+				gsw_port3: port at 3 {
+					reg = <3>;
+					label = "lan3";
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy3>;
+				};
+
+				port at 6 {
+					reg = <6>;
+					ethernet = <&gmac0>;
+					phy-mode = "internal";
+
+					fixed-link {
+						speed = <10000>;
+						full-duplex;
+						pause;
+					};
+				};
+			};
+
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				mediatek,pio = <&pio>;
+
+				gsw_phy0: ethernet-phy at 0 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <0>;
+					interrupts = <0>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p0>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy0_led0: led at 0 {
+							reg = <0>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+
+						gsw_phy0_led1: led at 1 {
+							reg = <1>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+					};
+				};
+
+				gsw_phy1: ethernet-phy at 1 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <1>;
+					interrupts = <1>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p1>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy1_led0: led at 0 {
+							reg = <0>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+
+						gsw_phy1_led1: led at 1 {
+							reg = <1>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+					};
+				};
+
+				gsw_phy2: ethernet-phy at 2 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <2>;
+					interrupts = <2>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p2>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy2_led0: led at 0 {
+							reg = <0>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+
+						gsw_phy2_led1: led at 1 {
+							reg = <1>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+					};
+				};
+
+				gsw_phy3: ethernet-phy at 3 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <3>;
+					interrupts = <3>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p3>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy3_led0: led at 0 {
+							reg = <0>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+
+						gsw_phy3_led1: led at 1 {
+							reg = <1>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+					};
+				};
+			};
+		};
+
 		ethwarp: clock-controller at 15031000 {
 			compatible = "mediatek,mt7988-ethwarp";
 			reg = <0 0x15031000 0 0x1000>;
-- 
2.43.0



From linux at fw-web.de  Sun May 11 07:19:23 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:19:23 +0200
Subject: [PATCH v1 07/14] arm64: dts: mediatek: mt7988: add phy calibration efuse subnodes
In-Reply-To: <20250511141942.10284-1-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
Message-ID: <20250511141942.10284-8-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

MT7988 contains buildin mt753x switch which needs calibration data from
efuse.

Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 64466acb0e71..029699e4eb02 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -696,6 +696,22 @@ efuse at 11f50000 {
 			lvts_calibration: calib at 918 {
 				reg = <0x918 0x28>;
 			};
+
+			phy_calibration_p0: calib at 940 {
+				reg = <0x940 0x10>;
+			};
+
+			phy_calibration_p1: calib at 954 {
+				reg = <0x954 0x10>;
+			};
+
+			phy_calibration_p2: calib at 968 {
+				reg = <0x968 0x10>;
+			};
+
+			phy_calibration_p3: calib at 97c {
+				reg = <0x97c 0x10>;
+			};
 		};
 
 		clock-controller at 15000000 {
-- 
2.43.0



From linux at fw-web.de  Sun May 11 07:19:20 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:19:20 +0200
Subject: [PATCH v1 04/14] arm64: dts: mediatek: mt7988: add spi controllers
In-Reply-To: <20250511141942.10284-1-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
Message-ID: <20250511141942.10284-5-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Add SPI controllers for mt7988.

Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 45 +++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 8f6d1dfae24a..8c31935f4ab0 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -311,6 +311,51 @@ i2c2: i2c at 11005000 {
 			status = "disabled";
 		};
 
+		spi0: spi at 11007000 {
+			compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";
+			reg = <0 0x11007000 0 0x100>;
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&topckgen CLK_TOP_MPLL_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg CLK_INFRA_104M_SPI0>,
+				 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk",
+				      "hclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi1: spi at 11008000 {
+			compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm";
+			reg = <0 0x11008000 0 0x100>;
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&topckgen CLK_TOP_MPLL_D2>,
+				 <&topckgen CLK_TOP_SPIM_MST_SEL>,
+				 <&infracfg CLK_INFRA_104M_SPI1>,
+				 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk",
+				      "hclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi2: spi at 11009000 {
+			compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";
+			reg = <0 0x11009000 0 0x100>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&topckgen CLK_TOP_MPLL_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
+				 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk",
+				      "hclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		lvts: lvts at 1100a000 {
 			compatible = "mediatek,mt7988-lvts-ap";
 			#thermal-sensor-cells = <1>;
-- 
2.43.0



From linux at fw-web.de  Sun May 11 07:19:24 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:19:24 +0200
Subject: [PATCH v1 08/14] arm64: dts: mediatek: mt7988: add basic ethernet-nodes
In-Reply-To: <20250511141942.10284-1-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
Message-ID: <20250511141942.10284-9-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Add basic ethernet related nodes.

Mac1+2 needs pcs (sgmii+usxgmii) to work correctly which will be linked
later when driver is merged.

Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 124 +++++++++++++++++++++-
 1 file changed, 121 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 029699e4eb02..aa0947a555aa 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -680,7 +680,28 @@ xphyu3port0: usb-phy at 11e13000 {
 			};
 		};
 
-		clock-controller at 11f40000 {
+		xfi_tphy0: phy at 11f20000 {
+			compatible = "mediatek,mt7988-xfi-tphy";
+			reg = <0 0x11f20000 0 0x10000>;
+			resets = <&watchdog 14>;
+			clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
+				 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
+			clock-names = "xfipll", "topxtal";
+			mediatek,usxgmii-performance-errata;
+			#phy-cells = <0>;
+		};
+
+		xfi_tphy1: phy at 11f30000 {
+			compatible = "mediatek,mt7988-xfi-tphy";
+			reg = <0 0x11f30000 0 0x10000>;
+			resets = <&watchdog 15>;
+			clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
+				 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
+			clock-names = "xfipll", "topxtal";
+			#phy-cells = <0>;
+		};
+
+		xfi_pll: clock-controller at 11f40000 {
 			compatible = "mediatek,mt7988-xfi-pll";
 			reg = <0 0x11f40000 0 0x1000>;
 			resets = <&watchdog 16>;
@@ -714,19 +735,116 @@ phy_calibration_p3: calib at 97c {
 			};
 		};
 
-		clock-controller at 15000000 {
+		ethsys: clock-controller at 15000000 {
 			compatible = "mediatek,mt7988-ethsys", "syscon";
 			reg = <0 0x15000000 0 0x1000>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
 
-		clock-controller at 15031000 {
+		ethwarp: clock-controller at 15031000 {
 			compatible = "mediatek,mt7988-ethwarp";
 			reg = <0 0x15031000 0 0x1000>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
+
+		eth: ethernet at 15100000 {
+			compatible = "mediatek,mt7988-eth";
+			reg = <0 0x15100000 0 0x80000>,
+			      <0 0x15400000 0 0x200000>;
+			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ethsys CLK_ETHDMA_CRYPT0_EN>,
+				 <&ethsys CLK_ETHDMA_FE_EN>,
+				 <&ethsys CLK_ETHDMA_GP2_EN>,
+				 <&ethsys CLK_ETHDMA_GP1_EN>,
+				 <&ethsys CLK_ETHDMA_GP3_EN>,
+				 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
+				 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
+				 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
+				 <&ethsys CLK_ETHDMA_ESW_EN>,
+				 <&topckgen CLK_TOP_ETH_GMII_SEL>,
+				 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
+				 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
+				 <&topckgen CLK_TOP_ETH_SYS_SEL>,
+				 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
+				 <&topckgen CLK_TOP_ETH_MII_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_WARP_SEL>,
+				 <&ethsys CLK_ETHDMA_XGP1_EN>,
+				 <&ethsys CLK_ETHDMA_XGP2_EN>,
+				 <&ethsys CLK_ETHDMA_XGP3_EN>;
+			clock-names = "crypto", "fe", "gp2", "gp1",
+				      "gp3",
+				      "ethwarp_wocpu2", "ethwarp_wocpu1",
+				      "ethwarp_wocpu0", "esw", "top_eth_gmii_sel",
+				      "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
+				      "top_eth_sys_sel", "top_eth_xgmii_sel",
+				      "top_eth_mii_sel", "top_netsys_sel",
+				      "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
+				      "top_netsys_sync_250m_sel",
+				      "top_netsys_ppefb_250m_sel",
+				      "top_netsys_warp_sel","xgp1", "xgp2", "xgp3";
+			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
+					  <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
+					  <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
+					  <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
+					  <&topckgen CLK_TOP_SGM_0_SEL>,
+					  <&topckgen CLK_TOP_SGM_1_SEL>;
+			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
+						 <&topckgen CLK_TOP_NET1PLL_D4>,
+						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
+						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
+						 <&apmixedsys CLK_APMIXED_SGMPLL>,
+						 <&apmixedsys CLK_APMIXED_SGMPLL>;
+			mediatek,ethsys = <&ethsys>;
+			mediatek,infracfg = <&topmisc>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gmac0: mac at 0 {
+				compatible = "mediatek,eth-mac";
+				reg = <0>;
+				phy-mode = "internal";
+
+				fixed-link {
+					speed = <10000>;
+					full-duplex;
+					pause;
+				};
+			};
+
+			gmac1: mac at 1 {
+				compatible = "mediatek,eth-mac";
+				reg = <1>;
+				status = "disabled";
+			};
+
+			gmac2: mac at 2 {
+				compatible = "mediatek,eth-mac";
+				reg = <2>;
+				status = "disabled";
+			};
+
+			mdio_bus: mdio-bus {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				/* internal 2.5G PHY */
+				int_2p5g_phy: ethernet-phy at f {
+					reg = <15>;
+					compatible = "ethernet-phy-ieee802.3-c45";
+					phy-mode = "internal";
+				};
+			};
+		};
 	};
 
 	thermal-zones {
-- 
2.43.0



From frank-w at public-files.de  Sun May 11 07:25:48 2025
From: frank-w at public-files.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:25:48 +0200
Subject: [PATCH v1 09/14] arm64: dts: mediatek: mt7988: add switch node
Message-ID: <20250511142549.10881-1-frank-w@public-files.de>

Add mt7988 builtin mt753x switch nodes.

Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 166 ++++++++++++++++++++++
 1 file changed, 166 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index aa0947a555aa..ab7612916a13 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -5,6 +5,7 @@
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/pinctrl/mt65xx.h>
 #include <dt-bindings/reset/mediatek,mt7988-resets.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "mediatek,mt7988a";
@@ -742,6 +743,171 @@ ethsys: clock-controller at 15000000 {
 			#reset-cells = <1>;
 		};
 
+		switch: switch at 15020000 {
+			compatible = "mediatek,mt7988-switch";
+			reg = <0 0x15020000 0 0x8000>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				gsw_port0: port at 0 {
+					reg = <0>;
+					label = "wan";
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy0>;
+				};
+
+				gsw_port1: port at 1 {
+					reg = <1>;
+					label = "lan1";
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy1>;
+				};
+
+				gsw_port2: port at 2 {
+					reg = <2>;
+					label = "lan2";
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy2>;
+				};
+
+				gsw_port3: port at 3 {
+					reg = <3>;
+					label = "lan3";
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy3>;
+				};
+
+				port at 6 {
+					reg = <6>;
+					ethernet = <&gmac0>;
+					phy-mode = "internal";
+
+					fixed-link {
+						speed = <10000>;
+						full-duplex;
+						pause;
+					};
+				};
+			};
+
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				mediatek,pio = <&pio>;
+
+				gsw_phy0: ethernet-phy at 0 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <0>;
+					interrupts = <0>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p0>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy0_led0: led at 0 {
+							reg = <0>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+
+						gsw_phy0_led1: led at 1 {
+							reg = <1>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+					};
+				};
+
+				gsw_phy1: ethernet-phy at 1 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <1>;
+					interrupts = <1>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p1>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy1_led0: led at 0 {
+							reg = <0>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+
+						gsw_phy1_led1: led at 1 {
+							reg = <1>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+					};
+				};
+
+				gsw_phy2: ethernet-phy at 2 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <2>;
+					interrupts = <2>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p2>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy2_led0: led at 0 {
+							reg = <0>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+
+						gsw_phy2_led1: led at 1 {
+							reg = <1>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+					};
+				};
+
+				gsw_phy3: ethernet-phy at 3 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <3>;
+					interrupts = <3>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p3>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy3_led0: led at 0 {
+							reg = <0>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+
+						gsw_phy3_led1: led at 1 {
+							reg = <1>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+					};
+				};
+			};
+		};
+
 		ethwarp: clock-controller at 15031000 {
 			compatible = "mediatek,mt7988-ethwarp";
 			reg = <0 0x15031000 0 0x1000>;
-- 
2.43.0



From frank-w at public-files.de  Sun May 11 07:26:53 2025
From: frank-w at public-files.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:26:53 +0200
Subject: [PATCH v1 13/14] arm64: dts: mediatek: mt7988a-bpi-r4: add sfp cages and link to gmac
In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de>
References: <20250511142655.11007-1-frank-w@public-files.de>
Message-ID: <20250511142655.11007-4-frank-w@public-files.de>

Add SFP cages to Bananapi-R4 board. The 2.5g phy variant only contains the
wan-SFP, so add this to common dtsi and the lan-sfp only to the dual-SFP
variant.

Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 .../mediatek/mt7988a-bananapi-bpi-r4-2g5.dts   | 11 +++++++++++
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts   | 18 ++++++++++++++++++
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi  | 18 ++++++++++++++++++
 3 files changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts
index 53de9c113f60..574ac1b853a6 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts
@@ -9,3 +9,14 @@ / {
 	model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)";
 	chassis-type = "embedded";
 };
+
+&gmac1 {
+	phy-mode = "internal";
+	phy-connection-type = "internal";
+	phy = <&int_2p5g_phy>;
+};
+
+&int_2p5g_phy {
+	pinctrl-names = "i2p5gbe-led";
+	pinctrl-0 = <&i2p5gbe_led0_pins>;
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
index 36bd1ef2efab..3136dc4ba4cc 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -8,6 +8,24 @@ / {
 	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
 	model = "Banana Pi BPI-R4 (2x SFP+)";
 	chassis-type = "embedded";
+
+	/* SFP2 cage (LAN) */
+	sfp2: sfp2 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp2>;
+		los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>;
+		tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
+		rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
+		maximum-power-milliwatt = <3000>;
+	};
+};
+
+&gmac1 {
+	sfp = <&sfp2>;
+	managed = "in-band-status";
+	phy-mode = "usxgmii";
 };
 
 &pca9545 {
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index afa9e3b2b16a..d40c8dbcd18e 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -38,6 +38,18 @@ reg_3p3v: regulator-3p3v {
 		regulator-boot-on;
 		regulator-always-on;
 	};
+
+	/* SFP1 cage (WAN) */
+	sfp1: sfp1 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp1>;
+		los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
+		tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
+		rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
+		maximum-power-milliwatt = <3000>;
+	};
 };
 
 &cci {
@@ -108,6 +120,12 @@ map-cpu-active-low {
 	};
 };
 
+&gmac2 {
+	sfp = <&sfp1>;
+	managed = "in-band-status";
+	phy-mode = "usxgmii";
+};
+
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_pins>;
-- 
2.43.0



From frank-w at public-files.de  Sun May 11 07:26:54 2025
From: frank-w at public-files.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:26:54 +0200
Subject: [PATCH v1 14/14] arm64: dts: mediatek: mt7988a-bpi-r4: configure switch phys and leds
In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de>
References: <20250511142655.11007-1-frank-w@public-files.de>
Message-ID: <20250511142655.11007-5-frank-w@public-files.de>

Assign pinctrl to switch phys and leds.

Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index d40c8dbcd18e..c67b1211af18 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -126,6 +126,46 @@ &gmac2 {
 	phy-mode = "usxgmii";
 };
 
+&gsw_phy0 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe0_led0_pins>;
+};
+
+&gsw_phy0_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy1 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe1_led0_pins>;
+};
+
+&gsw_phy1_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy2 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe2_led0_pins>;
+};
+
+&gsw_phy2_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy3 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe3_led0_pins>;
+};
+
+&gsw_phy3_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_pins>;
-- 
2.43.0



From frank-w at public-files.de  Sun May 11 07:26:50 2025
From: frank-w at public-files.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:26:50 +0200
Subject: [PATCH v1 10/14] arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and coolingmaps
Message-ID: <20250511142655.11007-1-frank-w@public-files.de>

Add Fan and cooling maps for Bananpi-R4 board.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index 23b267cd47ac..c6f84de82a4d 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -12,6 +12,15 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		/* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */
+		cooling-levels = <0 80 128 255>;
+		#cooling-cells = <2>;
+		pwms = <&pwm 0 50000>;
+		status = "okay";
+	};
+
 	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
@@ -73,6 +82,26 @@ cpu_trip_active_low: active-low {
 			type = "active";
 		};
 	};
+
+	cooling-maps {
+		map-cpu-active-high {
+			/* active: set fan to cooling level 2 */
+			cooling-device = <&fan 3 3>;
+			trip = <&cpu_trip_active_high>;
+		};
+
+		map-cpu-active-med {
+			/* active: set fan to cooling level 1 */
+			cooling-device = <&fan 2 2>;
+			trip = <&cpu_trip_active_med>;
+		};
+
+		map-cpu-active-low {
+			/* active: set fan to cooling level 0 */
+			cooling-device = <&fan 1 1>;
+			trip = <&cpu_trip_active_low>;
+		};
+	};
 };
 
 &i2c0 {
-- 
2.43.0



From frank-w at public-files.de  Sun May 11 07:26:51 2025
From: frank-w at public-files.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:26:51 +0200
Subject: [PATCH v1 11/14] arm64: dts: mediatek: mt7988a-bpi-r4: configure spi-nodes
In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de>
References: <20250511142655.11007-1-frank-w@public-files.de>
Message-ID: <20250511142655.11007-2-frank-w@public-files.de>

Configure and enable SPI nodes on Bananapi R4 board.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index c6f84de82a4d..81ba045e0e0e 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -401,6 +401,38 @@ &serial0 {
 	status = "okay";
 };
 
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+	status = "okay";
+
+	spi_nand: flash at 0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&spi1 {
+	status = "okay";
+};
+
+&spi_nand {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition at 0 {
+			label = "bl2";
+			reg = <0x0 0x200000>;
+			read-only;
+		};
+	};
+};
+
 &ssusb1 {
 	status = "okay";
 };
-- 
2.43.0



From frank-w at public-files.de  Sun May 11 07:26:52 2025
From: frank-w at public-files.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:26:52 +0200
Subject: [PATCH v1 12/14] arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply for cci
In-Reply-To: <20250511142655.11007-1-frank-w@public-files.de>
References: <20250511142655.11007-1-frank-w@public-files.de>
Message-ID: <20250511142655.11007-3-frank-w@public-files.de>

CCI requires proc-supply. Add it on board level.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index 81ba045e0e0e..afa9e3b2b16a 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -40,6 +40,10 @@ reg_3p3v: regulator-3p3v {
 	};
 };
 
+&cci {
+	proc-supply = <&rt5190_buck3>;
+};
+
 &cpu0 {
 	proc-supply = <&rt5190_buck3>;
 };
-- 
2.43.0



From frank-w at public-files.de  Sun May 11 09:06:24 2025
From: frank-w at public-files.de (Frank Wunderlich)
Date: Sun, 11 May 2025 16:06:24 +0000
Subject: Aw: [PATCH v1 00/14] further mt7988 devicetree work
In-Reply-To: <20250511141942.10284-1-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
Message-ID: <trinity-9fe03bba-54ab-4395-b6ae-4cf1d91e1b72-1746979584333@trinity-msg-rest-gmx-gmx-live-74d694d854-wjlx8>

sorry for splitted series and duplicate part 9

my mail provider responded with "5.7.1 Command rejected" at part 9 and i had to use another one.

regards Frank


From andrew at lunn.ch  Sun May 11 09:34:30 2025
From: andrew at lunn.ch (Andrew Lunn)
Date: Sun, 11 May 2025 18:34:30 +0200
Subject: [PATCH v1 02/14] dt-bindings: net: dsa: mediatek,mt7530: add
 dsa-port definition for mt7988
In-Reply-To: <20250511141942.10284-3-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
 <20250511141942.10284-3-linux@fw-web.de>
Message-ID: <043d1a0a-1932-42f3-bcd8-17fad10c5543@lunn.ch>

On Sun, May 11, 2025 at 04:19:18PM +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w at public-files.de>
> 
> Add own dsa-port binding for SoC with internal switch where only phy-mode
> 'internal' is valid.

So these internal PHYs don't have LEDs?

	Andrew


From andrew at lunn.ch  Sun May 11 09:38:49 2025
From: andrew at lunn.ch (Andrew Lunn)
Date: Sun, 11 May 2025 18:38:49 +0200
Subject: [PATCH v1 08/14] arm64: dts: mediatek: mt7988: add basic
 ethernet-nodes
In-Reply-To: <20250511141942.10284-9-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
 <20250511141942.10284-9-linux@fw-web.de>
Message-ID: <78abbdb9-70d8-4e53-8593-91735cde73ec@lunn.ch>

> +			gmac0: mac at 0 {
> +				compatible = "mediatek,eth-mac";
> +				reg = <0>;
> +				phy-mode = "internal";
> +
> +				fixed-link {
> +					speed = <10000>;
> +					full-duplex;
> +					pause;
> +				};

Does phy-mode internal and fixed-link used together make any sense?
Please could you explain this.

	Andrew


From andrew at lunn.ch  Sun May 11 09:42:16 2025
From: andrew at lunn.ch (Andrew Lunn)
Date: Sun, 11 May 2025 18:42:16 +0200
Subject: [PATCH v1 09/14] arm64: dts: mediatek: mt7988: add switch node
In-Reply-To: <20250511141942.10284-10-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
 <20250511141942.10284-10-linux@fw-web.de>
Message-ID: <bfa0c158-4205-4070-9b72-f6bde9cd9997@lunn.ch>

On Sun, May 11, 2025 at 04:19:25PM +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w at public-files.de>
> 
> Add mt7988 builtin mt753x switch nodes.
> 
> Signed-off-by: Daniel Golle <daniel at makrotopia.org>
> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> ---
>  arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 166 ++++++++++++++++++++++
>  1 file changed, 166 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> index aa0947a555aa..ab7612916a13 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> @@ -5,6 +5,7 @@
>  #include <dt-bindings/phy/phy.h>
>  #include <dt-bindings/pinctrl/mt65xx.h>
>  #include <dt-bindings/reset/mediatek,mt7988-resets.h>
> +#include <dt-bindings/leds/common.h>
>  
>  / {
>  	compatible = "mediatek,mt7988a";
> @@ -742,6 +743,171 @@ ethsys: clock-controller at 15000000 {
>  			#reset-cells = <1>;
>  		};
>  
> +		switch: switch at 15020000 {
> +			compatible = "mediatek,mt7988-switch";
> +			reg = <0 0x15020000 0 0x8000>;
> +			interrupt-controller;
> +			#interrupt-cells = <1>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
> +			resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				gsw_port0: port at 0 {
> +					reg = <0>;
> +					label = "wan";

I would expect the label to be in the board .dts file, since it is a
board property, not a SoC property.

	Andrew


From andrew at lunn.ch  Sun May 11 09:45:12 2025
From: andrew at lunn.ch (Andrew Lunn)
Date: Sun, 11 May 2025 18:45:12 +0200
Subject: [PATCH v1 02/14] dt-bindings: net: dsa: mediatek,mt7530: add
 dsa-port definition for mt7988
In-Reply-To: <043d1a0a-1932-42f3-bcd8-17fad10c5543@lunn.ch>
References: <20250511141942.10284-1-linux@fw-web.de>
 <20250511141942.10284-3-linux@fw-web.de>
 <043d1a0a-1932-42f3-bcd8-17fad10c5543@lunn.ch>
Message-ID: <88d93b58-84f3-4394-80ed-9adf67d525f4@lunn.ch>

On Sun, May 11, 2025 at 06:34:30PM +0200, Andrew Lunn wrote:
> On Sun, May 11, 2025 at 04:19:18PM +0200, Frank Wunderlich wrote:
> > From: Frank Wunderlich <frank-w at public-files.de>
> > 
> > Add own dsa-port binding for SoC with internal switch where only phy-mode
> > 'internal' is valid.
> 
> So these internal PHYs don't have LEDs?

Ah, i got that wrong, sorry.

What i don't know about here is if you should be defining your own
ds-port binding, or taking the existing binding and add a constraint.

	Andrew


From frank-w at public-files.de  Sun May 11 10:11:38 2025
From: frank-w at public-files.de (Frank Wunderlich)
Date: Sun, 11 May 2025 17:11:38 +0000
Subject: Aw: Re: [PATCH v1 02/14] dt-bindings: net: dsa: mediatek,mt7530:
 add dsa-port definition for mt7988
In-Reply-To: <88d93b58-84f3-4394-80ed-9adf67d525f4@lunn.ch>
References: <20250511141942.10284-1-linux@fw-web.de>
 <20250511141942.10284-3-linux@fw-web.de>
 <043d1a0a-1932-42f3-bcd8-17fad10c5543@lunn.ch>
 <88d93b58-84f3-4394-80ed-9adf67d525f4@lunn.ch>
Message-ID: <trinity-a7d75144-e618-4e09-ab4b-42e8557adb93-1746983498805@trinity-msg-rest-gmx-gmx-live-74d694d854-64x2n>

> Gesendet: Sonntag, 11. Mai 2025 um 18:45
> Von: "Andrew Lunn" <andrew at lunn.ch>
> Betreff: Re: [PATCH v1 02/14] dt-bindings: net: dsa: mediatek,mt7530: add dsa-port definition for mt7988
>
> On Sun, May 11, 2025 at 06:34:30PM +0200, Andrew Lunn wrote:
> > On Sun, May 11, 2025 at 04:19:18PM +0200, Frank Wunderlich wrote:
> > > From: Frank Wunderlich <frank-w at public-files.de>
> > > 
> > > Add own dsa-port binding for SoC with internal switch where only phy-mode
> > > 'internal' is valid.
> > 
> > So these internal PHYs don't have LEDs?
> 
> Ah, i got that wrong, sorry.
> 
> What i don't know about here is if you should be defining your own
> ds-port binding, or taking the existing binding and add a constraint.

Hi Andrew

thank you for first review.

this patch is only for allowing the phy-mode 'internal' and corrects the wrong mapping to mt7530-das-port which allows rgmii and sgmii which are invalid on mt7530.
i splitted the changes in binding to not squash different changes.

the phys with leds are on the builtin mt7530 internal mdio-bus which i add in patch 3.

regards Frank


From frank-w at public-files.de  Sun May 11 10:29:52 2025
From: frank-w at public-files.de (Frank Wunderlich)
Date: Sun, 11 May 2025 17:29:52 +0000
Subject: Aw: Re: [PATCH v1 09/14] arm64: dts: mediatek: mt7988: add switch
 node
In-Reply-To: <bfa0c158-4205-4070-9b72-f6bde9cd9997@lunn.ch>
References: <20250511141942.10284-1-linux@fw-web.de>
 <20250511141942.10284-10-linux@fw-web.de>
 <bfa0c158-4205-4070-9b72-f6bde9cd9997@lunn.ch>
Message-ID: <trinity-0edcdb4e-bcc9-47bb-b958-a018f5980128-1746984591926@trinity-msg-rest-gmx-gmx-live-74d694d854-ls6fz>


> Gesendet: Sonntag, 11. Mai 2025 um 18:42
> Von: "Andrew Lunn" <andrew at lunn.ch>
> Betreff: Re: [PATCH v1 09/14] arm64: dts: mediatek: mt7988: add switch node
>
> On Sun, May 11, 2025 at 04:19:25PM +0200, Frank Wunderlich wrote:
> > From: Frank Wunderlich <frank-w at public-files.de>
> > 
> > Add mt7988 builtin mt753x switch nodes.
> > 
> > Signed-off-by: Daniel Golle <daniel at makrotopia.org>
> > Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 166 ++++++++++++++++++++++
> >  1 file changed, 166 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> > index aa0947a555aa..ab7612916a13 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> > @@ -5,6 +5,7 @@
> >  #include <dt-bindings/phy/phy.h>
> >  #include <dt-bindings/pinctrl/mt65xx.h>
> >  #include <dt-bindings/reset/mediatek,mt7988-resets.h>
> > +#include <dt-bindings/leds/common.h>
> >  
> >  / {
> >  	compatible = "mediatek,mt7988a";
> > @@ -742,6 +743,171 @@ ethsys: clock-controller at 15000000 {
> >  			#reset-cells = <1>;
> >  		};
> >  
> > +		switch: switch at 15020000 {
> > +			compatible = "mediatek,mt7988-switch";
> > +			reg = <0 0x15020000 0 0x8000>;
> > +			interrupt-controller;
> > +			#interrupt-cells = <1>;
> > +			interrupt-parent = <&gic>;
> > +			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
> > +			resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
> > +
> > +			ports {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +
> > +				gsw_port0: port at 0 {
> > +					reg = <0>;
> > +					label = "wan";
> 
> I would expect the label to be in the board .dts file, since it is a
> board property, not a SoC property.

i will move that into the board dtsi file in v2 because "normal" bpi-r4 and 2g5 variant are same here.

regards Frank


From ansuelsmth at gmail.com  Sun May 11 13:12:26 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sun, 11 May 2025 22:12:26 +0200
Subject: [net-next PATCH v4 00/11] net: pcs: Introduce support for fwnode PCS
Message-ID: <20250511201250.3789083-1-ansuelsmth@gmail.com>

This series introduce a most awaited feature that is correctly
provide PCS with fwnode without having to use specific export symbol
and additional handling of PCS in phylink.

There is currently an equivalent series for this feature where
a wrapper implementation is proposed. I honestly don't really like
introducing layer of layer of wrapping to workaround stuff, so
this is my attempt at giving a more direct approach to this.

---
First the PCS fwnode:

The concept is to implement a producer-consumer API similar to other
subsystem like clock or PHY.

That seems to be the best solution to the problem as PCS driver needs
to be detached from phylink and implement a simple way to provide a
PCS while maintaining support for probe defer or driver removal.

To keep the implementation simple, the PCS driver devs needs some
collaboration to correctly implement this. This is O.K. as helper
to correctly implement this are provided hence it's really a matter
of following a pattern to correct follow removal of a PCS driver.

A PCS provider have to implement and call fwnode_pcs_add_provider() in
probe function and define an xlate function to define how the PCS
should be provided based on the requested interface and phandle spec
defined in fwnode (based on the #pcs-cells)

fwnode_pcs_get() is provided to provide a specific PCS declared in
fwnode at index.

A simple xlate function is provided for simple single PCS
implementation, fwnode_pcs_simple_get.

A PCS provider on driver removal should first call
fwnode_pcs_del_provider() to delete itself as a provider and then
release the PCS from phylink with phylink_release_pcs() under rtnl
lock.

---
Second PCS handling in phylink:

We have the PCS problem for the only reason that in initial
implementation, we permitted way too much flexibility to MAC driver
and things started to deviate. At times we couldn't think SoC
would start to put PCS outside the MAC hence it was OK to assume
they would live in the same driver. With the introduction of
10g in more consumer devices, we are observing a rapid growth
of this pattern with multiple PCS external to MAC.

To put a stop on this, the only solution is to give back to phylink
control on PCS handling and enforce more robust supported interface
definition from both MAC and PCS side.

It's suggested to read patch 0003 of this series for more info, here
a brief explaination of the idea:

This series introduce handling of PCS in phylink and try to deprecate
.mac_select_pcs.

Phylink now might contain a linked list of available PCS and
those will be used for PCS selection on phylink_major_config.

MAC driver needs to define pcs_interfaces mask in phylink_config
for every interface that needs a dedicated PCS.

These PCS needs to be provided to phylink at phylink_create time
by setting the available_pcs and num_available_pcs in phylink_config.
A helper to parse PCS from fwnode is provided
fwnode_phylink_pcs_parse() that will fill a preallocated array of
PCS. (the same function can be used to get the number of PCS
defined in DT, more info in patch 0005)

phylink_create() will fill the internal PCS list with the passed
array of PCS. phylink_major_config and other user of .mac_select_pcs
are adapted to make use of this new PCS list.

The supported interface value is also moved internally to phylink
struct. This is to handle late removal and addition of PCS.
(the bonus effect to this is giving phylink a clear idea of what
is actually supported by the MAC and his constraint with PCS)

The supported interface mask in phylink is done by OR the
supported_interfaces in phylink_config with every PCS in PCS list.

PCS removal is supported by forcing a mac_config, refresh the
supported interfaces and run a phy_resolve().

PCS late addition is supported by introducing a global notifier
for PCS provider. If a phylink have the pcs_interfaces mask not
zero, it's registered to this notifier.

PCS provider will emit a global PCS add event to signal any
interface that a new PCS might be avialable.

The function will then check if the PCS is related to the MAC
fwnode and add it accordingly.

A user for this new implementation is provided as an Airoha PCS
driver. This was also tested downstream with the IPQ95xx QCOM SoC
and with the help of Daniel also on the various Mediatek MT7988
SoC with both SFP cage implementation and DSA attached.

Lots of tests were done with driver unbind/bind and with interface
up/down also by adding print to make sure major_config_fail gets
correctly triggered and reset once the PCS comes back.

The dedicated commits have longer description on the implementation
so it's suggested to also check there for additional info.

---

Changes v4:
- Move patch 0002 phy_interface_copy to 0002 (fix bisectability
  problem)
- Address review from Lorenzo for Airoha ethernet driver
- Fix kdoc error with missing Return (actually missing : before Return)
- Fix UNMET dependency reported error for CONFIG_FWNODE_PCS
- Revert to pcs.c instead of core.c (due to name conflict with other kmod)
- Fix clang compilation error for Airoha PCS driver
- Add missing inline function to pcs.h function
Changes v3:
- Out of RFC
- Fix various spelling mistake
- Drop circular dependency patch
- Complete Airoha Ethernet phylink integration
- Introduce .pcs_link_down PCS OP
Changes v2:
- Switch to fwnode
- Implement PCS provider notifier
- Better split changes
- Move supported_interfaces to phylink
- Add circular dependency patch
- Rework handling with indirect addition/removal and
  trigger of phylink_resolve()

Christian Marangi (11):
  net: phy: introduce phy_interface_copy helper
  net: phylink: keep and use MAC supported_interfaces in phylink struct
  net: phylink: introduce internal phylink PCS handling
  net: phylink: add phylink_release_pcs() to externally release a PCS
  net: pcs: implement Firmware node support for PCS driver
  net: phylink: support late PCS provider attach
  dt-bindings: net: ethernet-controller: permit to define multiple PCS
  net: phylink: add .pcs_link_down PCS OP
  dt-bindings: net: pcs: Document support for Airoha Ethernet PCS
  net: pcs: airoha: add PCS driver for Airoha SoC
  net: airoha: add phylink support for GDM2/3/4

 .../bindings/net/ethernet-controller.yaml     |    2 -
 .../bindings/net/pcs/airoha,pcs.yaml          |  112 +
 drivers/net/ethernet/airoha/airoha_eth.c      |  155 +-
 drivers/net/ethernet/airoha/airoha_eth.h      |    3 +
 drivers/net/ethernet/airoha/airoha_regs.h     |   12 +
 drivers/net/pcs/Kconfig                       |   13 +
 drivers/net/pcs/Makefile                      |    2 +
 drivers/net/pcs/pcs-airoha.c                  | 2921 +++++++++++++++++
 drivers/net/pcs/pcs.c                         |  241 ++
 drivers/net/phy/phylink.c                     |  287 +-
 include/linux/pcs/pcs-provider.h              |   41 +
 include/linux/pcs/pcs.h                       |  104 +
 include/linux/phy.h                           |    5 +
 include/linux/phylink.h                       |   14 +
 14 files changed, 3883 insertions(+), 29 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
 create mode 100644 drivers/net/pcs/pcs-airoha.c
 create mode 100644 drivers/net/pcs/pcs.c
 create mode 100644 include/linux/pcs/pcs-provider.h
 create mode 100644 include/linux/pcs/pcs.h

-- 
2.48.1



From ansuelsmth at gmail.com  Sun May 11 13:12:27 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sun, 11 May 2025 22:12:27 +0200
Subject: [net-next PATCH v4 01/11] net: phy: introduce phy_interface_copy helper
In-Reply-To: <20250511201250.3789083-1-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
Message-ID: <20250511201250.3789083-2-ansuelsmth@gmail.com>

Introduce phy_interface_copy helper as a shorthand to copy the PHY
interface bitmap to a different location.

This is useful if a PHY interface bitmap needs to be stored in a
different variable and needs to be reset to an original value saved in a
different bitmap.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 include/linux/phy.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/linux/phy.h b/include/linux/phy.h
index d62d292024bc..9f0e5fb30d63 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -173,6 +173,11 @@ static inline void phy_interface_or(unsigned long *dst, const unsigned long *a,
 	bitmap_or(dst, a, b, PHY_INTERFACE_MODE_MAX);
 }
 
+static inline void phy_interface_copy(unsigned long *dst, const unsigned long *src)
+{
+	bitmap_copy(dst, src, PHY_INTERFACE_MODE_MAX);
+}
+
 static inline void phy_interface_set_rgmii(unsigned long *intf)
 {
 	__set_bit(PHY_INTERFACE_MODE_RGMII, intf);
-- 
2.48.1



From ansuelsmth at gmail.com  Sun May 11 13:12:28 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sun, 11 May 2025 22:12:28 +0200
Subject: [net-next PATCH v4 02/11] net: phylink: keep and use MAC supported_interfaces in phylink struct
In-Reply-To: <20250511201250.3789083-1-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
Message-ID: <20250511201250.3789083-3-ansuelsmth@gmail.com>

Add in phylink struct a copy of supported_interfaces from phylink_config
and make use of that instead of relying on phylink_config value.

This in preparation for support of PCS handling internally to phylink
where a PCS can be removed or added after the phylink is created and we
need both a reference of the supported_interfaces value from
phylink_config and an internal value that can be updated with the new
PCS info.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/phy/phylink.c | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 0faa3d97e06b..ec42fd278604 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -59,6 +59,11 @@ struct phylink {
 	/* The link configuration settings */
 	struct phylink_link_state link_config;
 
+	/* What interface are supported by the current link.
+	 * Can change on removal or addition of new PCS.
+	 */
+	DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+
 	/* The current settings */
 	phy_interface_t cur_interface;
 
@@ -610,7 +615,7 @@ static int phylink_validate_mask(struct phylink *pl, struct phy_device *phy,
 static int phylink_validate(struct phylink *pl, unsigned long *supported,
 			    struct phylink_link_state *state)
 {
-	const unsigned long *interfaces = pl->config->supported_interfaces;
+	const unsigned long *interfaces = pl->supported_interfaces;
 
 	if (state->interface == PHY_INTERFACE_MODE_NA)
 		return phylink_validate_mask(pl, NULL, supported, state,
@@ -1809,6 +1814,9 @@ struct phylink *phylink_create(struct phylink_config *config,
 	mutex_init(&pl->state_mutex);
 	INIT_WORK(&pl->resolve, phylink_resolve);
 
+	phy_interface_copy(pl->supported_interfaces,
+			   config->supported_interfaces);
+
 	pl->config = config;
 	if (config->type == PHYLINK_NETDEV) {
 		pl->netdev = to_net_dev(config->dev);
@@ -1967,7 +1975,7 @@ static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy,
 		 * those which the host supports.
 		 */
 		phy_interface_and(interfaces, phy->possible_interfaces,
-				  pl->config->supported_interfaces);
+				  pl->supported_interfaces);
 
 		if (phy_interface_empty(interfaces)) {
 			phylink_err(pl, "PHY has no common interfaces\n");
@@ -2684,12 +2692,12 @@ static phy_interface_t phylink_sfp_select_interface(struct phylink *pl,
 		return interface;
 	}
 
-	if (!test_bit(interface, pl->config->supported_interfaces)) {
+	if (!test_bit(interface, pl->supported_interfaces)) {
 		phylink_err(pl,
 			    "selection of interface failed, SFP selected %s (%u) but MAC supports %*pbl\n",
 			    phy_modes(interface), interface,
 			    (int)PHY_INTERFACE_MODE_MAX,
-			    pl->config->supported_interfaces);
+			    pl->supported_interfaces);
 		return PHY_INTERFACE_MODE_NA;
 	}
 
@@ -3576,14 +3584,14 @@ static int phylink_sfp_config_optical(struct phylink *pl)
 
 	phylink_dbg(pl, "optical SFP: interfaces=[mac=%*pbl, sfp=%*pbl]\n",
 		    (int)PHY_INTERFACE_MODE_MAX,
-		    pl->config->supported_interfaces,
+		    pl->supported_interfaces,
 		    (int)PHY_INTERFACE_MODE_MAX,
 		    pl->sfp_interfaces);
 
 	/* Find the union of the supported interfaces by the PCS/MAC and
 	 * the SFP module.
 	 */
-	phy_interface_and(interfaces, pl->config->supported_interfaces,
+	phy_interface_and(interfaces, pl->supported_interfaces,
 			  pl->sfp_interfaces);
 	if (phy_interface_empty(interfaces)) {
 		phylink_err(pl, "unsupported SFP module: no common interface modes\n");
@@ -3729,7 +3737,7 @@ static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)
 
 	/* Set the PHY's host supported interfaces */
 	phy_interface_and(phy->host_interfaces, phylink_sfp_interfaces,
-			  pl->config->supported_interfaces);
+			  pl->supported_interfaces);
 
 	/* Do the initial configuration */
 	return phylink_sfp_config_phy(pl, phy);
-- 
2.48.1



From ansuelsmth at gmail.com  Sun May 11 13:12:29 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sun, 11 May 2025 22:12:29 +0200
Subject: [net-next PATCH v4 03/11] net: phylink: introduce internal phylink PCS handling
In-Reply-To: <20250511201250.3789083-1-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
Message-ID: <20250511201250.3789083-4-ansuelsmth@gmail.com>

Introduce internal handling of PCS for phylink. This is an alternative
to .mac_select_pcs that moves the selection logic of the PCS entirely to
phylink with the usage of the supported_interface value in the PCS
struct.

MAC should now provide an array of available PCS in phylink_config in
.available_pcs and fill the .num_available_pcs with the number of
elements in the array. MAC should also define a new bitmap,
pcs_interfaces, in phylink_config to define for what interface mode a
dedicated PCS is required.

On phylink_create() this array is parsed and a linked list of PCS is
created based on the PCS passed in phylink_config.
Also the supported_interface value in phylink struct is updated with the
new supported_interface from the provided PCS.

On phylink_start() every PCS in phylink PCS list gets attached to the
phylink instance. This is done by setting the phylink value in
phylink_pcs struct to the phylink instance.

On phylink_stop(), every PCS in phylink PCS list is detached from the
phylink instance. This is done by setting the phylink value in
phylink_pcs struct to NULL.

phylink_validate_mac_and_pcs(), phylink_major_config() and
phylink_inband_caps() are updated to support this new implementation
with the PCS list stored in phylink.

They will make use of phylink_validate_pcs_interface() that will loop
for every PCS in the phylink PCS available list and find one that supports
the passed interface.

phylink_validate_pcs_interface() applies the same logic of .mac_select_pcs
where if a supported_interface value is not set for the PCS struct, then
it's assumed every interface is supported.

A MAC is required to implement either a .mac_select_pcs or make use of
the PCS list implementation. Implementing both will result in a fail
on MAC/PCS validation.

phylink value in phylink_pcs struct with this implementation is used to
track from PCS side when it's attached to a phylink instance. PCS driver
will make use of this information to correctly detach from a phylink
instance if needed.

The .mac_select_pcs implementation is not changed but it's expected that
every MAC driver migrates to the new implementation to later deprecate
and remove .mac_select_pcs.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/phy/phylink.c | 147 +++++++++++++++++++++++++++++++++-----
 include/linux/phylink.h   |  10 +++
 2 files changed, 139 insertions(+), 18 deletions(-)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index ec42fd278604..95d7e06dee56 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -59,6 +59,9 @@ struct phylink {
 	/* The link configuration settings */
 	struct phylink_link_state link_config;
 
+	/* List of available PCS */
+	struct list_head pcs_list;
+
 	/* What interface are supported by the current link.
 	 * Can change on removal or addition of new PCS.
 	 */
@@ -144,6 +147,8 @@ static const phy_interface_t phylink_sfp_interface_preference[] = {
 
 static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);
 
+static void phylink_run_resolve(struct phylink *pl);
+
 /**
  * phylink_set_port_modes() - set the port type modes in the ethtool mask
  * @mask: ethtool link mode mask
@@ -499,22 +504,59 @@ static void phylink_validate_mask_caps(unsigned long *supported,
 	linkmode_and(state->advertising, state->advertising, mask);
 }
 
+static int phylink_validate_pcs_interface(struct phylink_pcs *pcs,
+					  phy_interface_t interface)
+{
+	/* If PCS define an empty supported_interfaces value, assume
+	 * all interface are supported.
+	 */
+	if (phy_interface_empty(pcs->supported_interfaces))
+		return 0;
+
+	/* Ensure that this PCS supports the interface mode */
+	if (!test_bit(interface, pcs->supported_interfaces))
+		return -EINVAL;
+
+	return 0;
+}
+
 static int phylink_validate_mac_and_pcs(struct phylink *pl,
 					unsigned long *supported,
 					struct phylink_link_state *state)
 {
-	struct phylink_pcs *pcs = NULL;
 	unsigned long capabilities;
+	struct phylink_pcs *pcs;
+	bool pcs_found = false;
 	int ret;
 
 	/* Get the PCS for this interface mode */
 	if (pl->mac_ops->mac_select_pcs) {
+		/* Make sure either PCS internal validation or .mac_select_pcs
+		 * is used. Return error if both are defined.
+		 */
+		if (!list_empty(&pl->pcs_list)) {
+			phylink_err(pl, "either phylink_pcs_add() or .mac_select_pcs must be used\n");
+			return -EINVAL;
+		}
+
 		pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
 		if (IS_ERR(pcs))
 			return PTR_ERR(pcs);
+
+		pcs_found = !!pcs;
+	} else {
+		/* Check every assigned PCS and search for one that supports
+		 * the interface.
+		 */
+		list_for_each_entry(pcs, &pl->pcs_list, list) {
+			if (!phylink_validate_pcs_interface(pcs, state->interface)) {
+				pcs_found = true;
+				break;
+			}
+		}
 	}
 
-	if (pcs) {
+	if (pcs_found) {
 		/* The PCS, if present, must be setup before phylink_create()
 		 * has been called. If the ops is not initialised, print an
 		 * error and backtrace rather than oopsing the kernel.
@@ -526,13 +568,10 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
 			return -EINVAL;
 		}
 
-		/* Ensure that this PCS supports the interface which the MAC
-		 * returned it for. It is an error for the MAC to return a PCS
-		 * that does not support the interface mode.
-		 */
-		if (!phy_interface_empty(pcs->supported_interfaces) &&
-		    !test_bit(state->interface, pcs->supported_interfaces)) {
-			phylink_err(pl, "MAC returned PCS which does not support %s\n",
+		/* Recheck PCS to handle legacy way for .mac_select_pcs */
+		ret = phylink_validate_pcs_interface(pcs, state->interface);
+		if (ret) {
+			phylink_err(pl, "selected PCS does not support %s\n",
 				    phy_modes(state->interface));
 			return -EINVAL;
 		}
@@ -937,12 +976,22 @@ static unsigned int phylink_inband_caps(struct phylink *pl,
 					 phy_interface_t interface)
 {
 	struct phylink_pcs *pcs;
+	bool pcs_found = false;
 
-	if (!pl->mac_ops->mac_select_pcs)
-		return 0;
+	if (pl->mac_ops->mac_select_pcs) {
+		pcs = pl->mac_ops->mac_select_pcs(pl->config,
+						  interface);
+		pcs_found = !!pcs;
+	} else {
+		list_for_each_entry(pcs, &pl->pcs_list, list) {
+			if (!phylink_validate_pcs_interface(pcs, interface)) {
+				pcs_found = true;
+				break;
+			}
+		}
+	}
 
-	pcs = pl->mac_ops->mac_select_pcs(pl->config, interface);
-	if (!pcs)
+	if (!pcs_found)
 		return 0;
 
 	return phylink_pcs_inband_caps(pcs, interface);
@@ -1228,10 +1277,36 @@ static void phylink_major_config(struct phylink *pl, bool restart,
 			pl->major_config_failed = true;
 			return;
 		}
+	/* Find a PCS in available PCS list for the requested interface.
+	 * This doesn't overwrite the previous .mac_select_pcs as either
+	 * .mac_select_pcs or PCS list implementation are permitted.
+	 *
+	 * Skip searching if the MAC doesn't require a dedicaed PCS for
+	 * the requested interface.
+	 */
+	} else if (test_bit(state->interface, pl->config->pcs_interfaces)) {
+		bool pcs_found = false;
+
+		list_for_each_entry(pcs, &pl->pcs_list, list) {
+			if (!phylink_validate_pcs_interface(pcs,
+							    state->interface)) {
+				pcs_found = true;
+				break;
+			}
+		}
+
+		if (!pcs_found) {
+			phylink_err(pl,
+				    "couldn't find a PCS for %s\n",
+				    phy_modes(state->interface));
 
-		pcs_changed = pl->pcs != pcs;
+			pl->major_config_failed = true;
+			return;
+		}
 	}
 
+	pcs_changed = pl->pcs != pcs;
+
 	phylink_pcs_neg_mode(pl, pcs, state->interface, state->advertising);
 
 	phylink_dbg(pl, "major config, active %s/%s/%s\n",
@@ -1258,10 +1333,12 @@ static void phylink_major_config(struct phylink *pl, bool restart,
 	if (pcs_changed) {
 		phylink_pcs_disable(pl->pcs);
 
-		if (pl->pcs)
-			pl->pcs->phylink = NULL;
+		if (pl->mac_ops->mac_select_pcs) {
+			if (pl->pcs)
+				pl->pcs->phylink = NULL;
 
-		pcs->phylink = pl;
+			pcs->phylink = pl;
+		}
 
 		pl->pcs = pcs;
 	}
@@ -1797,8 +1874,9 @@ struct phylink *phylink_create(struct phylink_config *config,
 			       phy_interface_t iface,
 			       const struct phylink_mac_ops *mac_ops)
 {
+	struct phylink_pcs *pcs;
 	struct phylink *pl;
-	int ret;
+	int i, ret;
 
 	/* Validate the supplied configuration */
 	if (phy_interface_empty(config->supported_interfaces)) {
@@ -1813,9 +1891,21 @@ struct phylink *phylink_create(struct phylink_config *config,
 
 	mutex_init(&pl->state_mutex);
 	INIT_WORK(&pl->resolve, phylink_resolve);
+	INIT_LIST_HEAD(&pl->pcs_list);
+
+	/* Fill the PCS list with available PCS from phylink config */
+	for (i = 0; i < config->num_available_pcs; i++) {
+		pcs = config->available_pcs[i];
+
+		list_add(&pcs->list, &pl->pcs_list);
+	}
 
 	phy_interface_copy(pl->supported_interfaces,
 			   config->supported_interfaces);
+	list_for_each_entry(pcs, &pl->pcs_list, list)
+		phy_interface_or(pl->supported_interfaces,
+				 pl->supported_interfaces,
+				 pcs->supported_interfaces);
 
 	pl->config = config;
 	if (config->type == PHYLINK_NETDEV) {
@@ -1894,10 +1984,16 @@ EXPORT_SYMBOL_GPL(phylink_create);
  */
 void phylink_destroy(struct phylink *pl)
 {
+	struct phylink_pcs *pcs, *tmp;
+
 	sfp_bus_del_upstream(pl->sfp_bus);
 	if (pl->link_gpio)
 		gpiod_put(pl->link_gpio);
 
+	/* Remove every PCS from phylink PCS list */
+	list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list)
+		list_del(&pcs->list);
+
 	cancel_work_sync(&pl->resolve);
 	kfree(pl);
 }
@@ -2374,6 +2470,7 @@ static irqreturn_t phylink_link_handler(int irq, void *data)
  */
 void phylink_start(struct phylink *pl)
 {
+	struct phylink_pcs *pcs;
 	bool poll = false;
 
 	ASSERT_RTNL();
@@ -2400,6 +2497,10 @@ void phylink_start(struct phylink *pl)
 
 	pl->pcs_state = PCS_STATE_STARTED;
 
+	/* link available PCS to phylink struct */
+	list_for_each_entry(pcs, &pl->pcs_list, list)
+		pcs->phylink = pl;
+
 	phylink_enable_and_run_resolve(pl, PHYLINK_DISABLE_STOPPED);
 
 	if (pl->cfg_link_an_mode == MLO_AN_FIXED && pl->link_gpio) {
@@ -2444,6 +2545,8 @@ EXPORT_SYMBOL_GPL(phylink_start);
  */
 void phylink_stop(struct phylink *pl)
 {
+	struct phylink_pcs *pcs;
+
 	ASSERT_RTNL();
 
 	if (pl->sfp_bus)
@@ -2461,6 +2564,14 @@ void phylink_stop(struct phylink *pl)
 	pl->pcs_state = PCS_STATE_DOWN;
 
 	phylink_pcs_disable(pl->pcs);
+
+	/* Drop link between phylink and PCS */
+	list_for_each_entry(pcs, &pl->pcs_list, list)
+		pcs->phylink = NULL;
+
+	/* Restore original supported interfaces */
+	phy_interface_copy(pl->supported_interfaces,
+			   pl->config->supported_interfaces);
 }
 EXPORT_SYMBOL_GPL(phylink_stop);
 
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index 30659b615fca..ef0b5a0729c8 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -150,12 +150,16 @@ enum phylink_op_type {
  *		     if MAC link is at %MLO_AN_FIXED mode.
  * @supported_interfaces: bitmap describing which PHY_INTERFACE_MODE_xxx
  *                        are supported by the MAC/PCS.
+ * @pcs_interfaces: bitmap describing for which PHY_INTERFACE_MODE_xxx a
+ *		    dedicated PCS is required.
  * @lpi_interfaces: bitmap describing which PHY interface modes can support
  *		    LPI signalling.
  * @mac_capabilities: MAC pause/speed/duplex capabilities.
  * @lpi_capabilities: MAC speeds which can support LPI signalling
  * @lpi_timer_default: Default EEE LPI timer setting.
  * @eee_enabled_default: If set, EEE will be enabled by phylink at creation time
+ * @available_pcs: array of available phylink_pcs PCS
+ * @num_available_pcs: num of available phylink_pcs PCS
  */
 struct phylink_config {
 	struct device *dev;
@@ -168,11 +172,14 @@ struct phylink_config {
 	void (*get_fixed_state)(struct phylink_config *config,
 				struct phylink_link_state *state);
 	DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+	DECLARE_PHY_INTERFACE_MASK(pcs_interfaces);
 	DECLARE_PHY_INTERFACE_MASK(lpi_interfaces);
 	unsigned long mac_capabilities;
 	unsigned long lpi_capabilities;
 	u32 lpi_timer_default;
 	bool eee_enabled_default;
+	struct phylink_pcs **available_pcs;
+	unsigned int num_available_pcs;
 };
 
 void phylink_limit_mac_speed(struct phylink_config *config, u32 max_speed);
@@ -469,6 +476,9 @@ struct phylink_pcs {
 	struct phylink *phylink;
 	bool poll;
 	bool rxc_always_on;
+
+	/* private: */
+	struct list_head list;
 };
 
 /**
-- 
2.48.1



From ansuelsmth at gmail.com  Sun May 11 13:12:30 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sun, 11 May 2025 22:12:30 +0200
Subject: [net-next PATCH v4 04/11] net: phylink: add phylink_release_pcs() to externally release a PCS
In-Reply-To: <20250511201250.3789083-1-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
Message-ID: <20250511201250.3789083-5-ansuelsmth@gmail.com>

Add phylink_release_pcs() to externally release a PCS from a phylink
instance. This can be used to handle case when a single PCS needs to be
removed and the phylink instance needs to be refreshed.

On calling phylink_release_pcs(), the PCS will be removed from the
phylink internal PCS list and the phylink supported_interfaces value is
reparsed with the remaining PCS interfaces.

Also a phylink resolve is triggered to handle the PCS removal.

A flag to make phylink resolve reconfigure the interface (even if it
didn't change) is also added. This is needed to handle the special
case when the current PCS used by phylink is removed and a major_config
is needed to propagae the configuration change. With this option
enabled we also force mac_config even if the PHY link is not up for
the in-band case.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/phy/phylink.c | 58 ++++++++++++++++++++++++++++++++++++++-
 include/linux/phylink.h   |  2 ++
 2 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 95d7e06dee56..2f28c4c83062 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -84,6 +84,7 @@ struct phylink {
 	bool link_failed;
 	bool suspend_link_up;
 	bool major_config_failed;
+	bool reconfig_interface;
 	bool mac_supports_eee_ops;
 	bool mac_supports_eee;
 	bool phy_enable_tx_lpi;
@@ -895,6 +896,55 @@ static void phylink_resolve_an_pause(struct phylink_link_state *state)
 	}
 }
 
+/**
+ * phylink_release_pcs - Removes a PCS from the phylink PCS available list
+ * @pcs: a pointer to the phylink_pcs struct to be released
+ *
+ * This function release a PCS from the phylink PCS available list if
+ * actually in use. It also refreshes the supported interfaces of the
+ * phylink instance by copying the supported interfaces from the phylink
+ * conf and merging the supported interfaces of the remaining available PCS
+ * in the list and trigger a resolve.
+ */
+void phylink_release_pcs(struct phylink_pcs *pcs)
+{
+	struct phylink *pl;
+
+	ASSERT_RTNL();
+
+	pl = pcs->phylink;
+	if (!pl)
+		return;
+
+	list_del(&pcs->list);
+	pcs->phylink = NULL;
+
+	/* Check if we are removing the PCS currently
+	 * in use by phylink. If this is the case,
+	 * force phylink resolve to reconfigure the interface
+	 * mode and set the phylink PCS to NULL.
+	 */
+	if (pl->pcs == pcs) {
+		mutex_lock(&pl->state_mutex);
+
+		pl->reconfig_interface = true;
+		pl->pcs = NULL;
+
+		mutex_unlock(&pl->state_mutex);
+	}
+
+	/* Refresh supported interfaces */
+	phy_interface_copy(pl->supported_interfaces,
+			   pl->config->supported_interfaces);
+	list_for_each_entry(pcs, &pl->pcs_list, list)
+		phy_interface_or(pl->supported_interfaces,
+				 pl->supported_interfaces,
+				 pcs->supported_interfaces);
+
+	phylink_run_resolve(pl);
+}
+EXPORT_SYMBOL_GPL(phylink_release_pcs);
+
 static unsigned int phylink_pcs_inband_caps(struct phylink_pcs *pcs,
 				    phy_interface_t interface)
 {
@@ -1688,6 +1738,10 @@ static void phylink_resolve(struct work_struct *w)
 		if (pl->phydev)
 			link_state.link &= pl->phy_state.link;
 
+		/* Force mac_config if we need to reconfig the interface */
+		if (pl->reconfig_interface)
+			mac_config = true;
+
 		/* Only update if the PHY link is up */
 		if (pl->phydev && pl->phy_state.link) {
 			/* If the interface has changed, force a link down
@@ -1722,7 +1776,8 @@ static void phylink_resolve(struct work_struct *w)
 		phylink_apply_manual_flow(pl, &link_state);
 
 	if (mac_config) {
-		if (link_state.interface != pl->link_config.interface) {
+		if (link_state.interface != pl->link_config.interface ||
+		    pl->reconfig_interface) {
 			/* The interface has changed, force the link down and
 			 * then reconfigure.
 			 */
@@ -1732,6 +1787,7 @@ static void phylink_resolve(struct work_struct *w)
 			}
 			phylink_major_config(pl, false, &link_state);
 			pl->link_config.interface = link_state.interface;
+			pl->reconfig_interface = false;
 		}
 	}
 
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index ef0b5a0729c8..c5496c063b6a 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -717,6 +717,8 @@ void phylink_disconnect_phy(struct phylink *);
 int phylink_set_fixed_link(struct phylink *,
 			   const struct phylink_link_state *);
 
+void phylink_release_pcs(struct phylink_pcs *pcs);
+
 void phylink_mac_change(struct phylink *, bool up);
 void phylink_pcs_change(struct phylink_pcs *, bool up);
 
-- 
2.48.1



From ansuelsmth at gmail.com  Sun May 11 13:12:31 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sun, 11 May 2025 22:12:31 +0200
Subject: [net-next PATCH v4 05/11] net: pcs: implement Firmware node support for PCS driver
In-Reply-To: <20250511201250.3789083-1-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
Message-ID: <20250511201250.3789083-6-ansuelsmth@gmail.com>

Implement the foundation of Firmware node support for PCS driver.

To support this, implement a simple Provider API where a PCS driver can
expose multiple PCS with an xlate .get function.

PCS driver will have to call fwnode_pcs_add_provider() and pass the
firmware node pointer and a xlate function to return the correct PCS for
the passed #pcs-cells.

This will register the PCS in a global list of providers so that
consumer can access it.

The consumer will then use fwnode_pcs_get() to get the actual PCS by
passing the firmware node pointer and the index for #pcs-cells.

For a simple implementation where #pcs-cells is 0 and the PCS driver
expose a single PCS, the xlate function fwnode_pcs_simple_get() is
provided.

For an advanced implementation a custom xlate function is required.

One removal the PCS driver should first delete itself from the provider
list using fwnode_pcs_del_provider() and then call phylink_release_pcs()
on every PCS the driver provides.

A generic function fwnode_phylink_pcs_parse() is provided for MAC driver
that will declare PCS in DT (or ACPI).
This function will parse "pcs-handle" property and fill the passed array
with the parsed PCS in availabel_pcs up to the passed num_pcs value.
It's also possible to pass NULL as array to only parse the PCS and
update the num_pcs value with the count of scanned PCS.

Co-developed-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/pcs/Kconfig          |   6 +
 drivers/net/pcs/Makefile         |   1 +
 drivers/net/pcs/pcs.c            | 201 +++++++++++++++++++++++++++++++
 include/linux/pcs/pcs-provider.h |  41 +++++++
 include/linux/pcs/pcs.h          |  56 +++++++++
 5 files changed, 305 insertions(+)
 create mode 100644 drivers/net/pcs/pcs.c
 create mode 100644 include/linux/pcs/pcs-provider.h
 create mode 100644 include/linux/pcs/pcs.h

diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index f6aa437473de..0d54bea1f663 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -5,6 +5,12 @@
 
 menu "PCS device drivers"
 
+config FWNODE_PCS
+	tristate
+	depends on (ACPI || OF)
+	help
+		Firmware node PCS accessors
+
 config PCS_XPCS
 	tristate "Synopsys DesignWare Ethernet XPCS"
 	select PHYLINK
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index 4f7920618b90..3005cdd89ab7 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 # Makefile for Linux PCS drivers
 
+obj-$(CONFIG_FWNODE_PCS)	+= pcs.o
 pcs_xpcs-$(CONFIG_PCS_XPCS)	:= pcs-xpcs.o pcs-xpcs-plat.o \
 				   pcs-xpcs-nxp.o pcs-xpcs-wx.o
 
diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
new file mode 100644
index 000000000000..26d07a2edfce
--- /dev/null
+++ b/drivers/net/pcs/pcs.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <linux/mutex.h>
+#include <linux/property.h>
+#include <linux/phylink.h>
+#include <linux/pcs/pcs.h>
+#include <linux/pcs/pcs-provider.h>
+
+MODULE_DESCRIPTION("PCS library");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth at gmail.com>");
+MODULE_LICENSE("GPL");
+
+struct fwnode_pcs_provider {
+	struct list_head link;
+
+	struct fwnode_handle *fwnode;
+	struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+				   void *data);
+
+	void *data;
+};
+
+static LIST_HEAD(fwnode_pcs_providers);
+static DEFINE_MUTEX(fwnode_pcs_mutex);
+
+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
+					  void *data)
+{
+	return data;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_simple_get);
+
+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+			    struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+						       void *data),
+			    void *data)
+{
+	struct fwnode_pcs_provider *pp;
+
+	if (!fwnode)
+		return 0;
+
+	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
+	if (!pp)
+		return -ENOMEM;
+
+	pp->fwnode = fwnode_handle_get(fwnode);
+	pp->data = data;
+	pp->get = get;
+
+	mutex_lock(&fwnode_pcs_mutex);
+	list_add(&pp->link, &fwnode_pcs_providers);
+	mutex_unlock(&fwnode_pcs_mutex);
+	pr_debug("Added pcs provider from %pfwf\n", fwnode);
+
+	fwnode_dev_initialized(fwnode, true);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
+
+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode)
+{
+	struct fwnode_pcs_provider *pp;
+
+	if (!fwnode)
+		return;
+
+	mutex_lock(&fwnode_pcs_mutex);
+	list_for_each_entry(pp, &fwnode_pcs_providers, link) {
+		if (pp->fwnode == fwnode) {
+			list_del(&pp->link);
+			fwnode_dev_initialized(pp->fwnode, false);
+			fwnode_handle_put(pp->fwnode);
+			kfree(pp);
+			break;
+		}
+	}
+	mutex_unlock(&fwnode_pcs_mutex);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_del_provider);
+
+static int fwnode_parse_pcsspec(const struct fwnode_handle *fwnode, int index,
+				const char *name,
+				struct fwnode_reference_args *out_args)
+{
+	int ret;
+
+	if (!fwnode)
+		return -ENOENT;
+
+	if (name)
+		index = fwnode_property_match_string(fwnode, "pcs-names",
+						     name);
+
+	ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+						 "#pcs-cells",
+						 -1, index, out_args);
+	if (ret || (name && index < 0))
+		return ret;
+
+	return 0;
+}
+
+static struct phylink_pcs *
+fwnode_pcs_get_from_pcsspec(struct fwnode_reference_args *pcsspec)
+{
+	struct fwnode_pcs_provider *provider;
+	struct phylink_pcs *pcs = ERR_PTR(-EPROBE_DEFER);
+
+	if (!pcsspec)
+		return ERR_PTR(-EINVAL);
+
+	mutex_lock(&fwnode_pcs_mutex);
+	list_for_each_entry(provider, &fwnode_pcs_providers, link) {
+		if (provider->fwnode == pcsspec->fwnode) {
+			pcs = provider->get(pcsspec, provider->data);
+			if (!IS_ERR(pcs))
+				break;
+		}
+	}
+	mutex_unlock(&fwnode_pcs_mutex);
+
+	return pcs;
+}
+
+static struct phylink_pcs *__fwnode_pcs_get(struct fwnode_handle *fwnode,
+					    int index, const char *con_id)
+{
+	struct fwnode_reference_args pcsspec;
+	struct phylink_pcs *pcs;
+	int ret;
+
+	ret = fwnode_parse_pcsspec(fwnode, index, con_id, &pcsspec);
+	if (ret)
+		return ERR_PTR(ret);
+
+	pcs = fwnode_pcs_get_from_pcsspec(&pcsspec);
+	fwnode_handle_put(pcsspec.fwnode);
+
+	return pcs;
+}
+
+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, int index)
+{
+	return __fwnode_pcs_get(fwnode, index, NULL);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_get);
+
+static int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode,
+				    unsigned int *num_pcs)
+{
+	struct fwnode_reference_args out_args;
+	int index = 0;
+	int ret;
+
+	while (true) {
+		ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+							 "#pcs-cells",
+							 -1, index, &out_args);
+		/* We expect to reach an -ENOENT error while counting */
+		if (ret)
+			break;
+
+		fwnode_handle_put(out_args.fwnode);
+		index++;
+	}
+
+	/* Update num_pcs with parsed PCS */
+	*num_pcs = index;
+
+	/* Return error if we didn't found any PCS */
+	return index > 0 ? 0 : -ENOENT;
+}
+
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+			     struct phylink_pcs **available_pcs,
+			     unsigned int *num_pcs)
+{
+	int i;
+
+	if (!fwnode_property_present(fwnode, "pcs-handle"))
+		return -ENODEV;
+
+	/* With available_pcs NULL, only count the PCS */
+	if (!available_pcs)
+		return fwnode_phylink_pcs_count(fwnode, num_pcs);
+
+	for (i = 0; i < *num_pcs; i++) {
+		struct phylink_pcs *pcs;
+
+		pcs = fwnode_pcs_get(fwnode, i);
+		if (IS_ERR(pcs))
+			return PTR_ERR(pcs);
+
+		available_pcs[i] = pcs;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_parse);
diff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h
new file mode 100644
index 000000000000..ae51c108147e
--- /dev/null
+++ b/include/linux/pcs/pcs-provider.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_PROVIDER_H
+#define __LINUX_PCS_PROVIDER_H
+
+/**
+ * fwnode_pcs_simple_get - Simple xlate function to retrieve PCS
+ * @pcsspec: reference arguments
+ * @data: Context data (assumed assigned to the single PCS)
+ *
+ * Returns: the PCS pointed by data.
+ */
+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
+					  void *data);
+
+/**
+ * fwnode_pcs_add_provider - Registers a new PCS provider
+ * @fwnode: Firmware node
+ * @get: xlate function to retrieve the PCS
+ * @data: Context data
+ *
+ * Register and add a new PCS to the global providers list
+ * for the firmware node. A function to get the PCS from
+ * firmware node with the use fwnode reference arguments.
+ * To the get function is also passed the interface type
+ * requested for the PHY. PCS driver will use the passed
+ * interface to understand if the PCS can support it or not.
+ *
+ * Returns: 0 on success or -ENOMEM on allocation failure.
+ */
+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+			    struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+						       void *data),
+			    void *data);
+
+/**
+ * fwnode_pcs_del_provider - Removes a PCS provider
+ * @fwnode: Firmware node
+ */
+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode);
+
+#endif /* __LINUX_PCS_PROVIDER_H */
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
new file mode 100644
index 000000000000..33244e3a442b
--- /dev/null
+++ b/include/linux/pcs/pcs.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_H
+#define __LINUX_PCS_H
+
+#include <linux/phylink.h>
+
+#if IS_ENABLED(CONFIG_FWNODE_PCS)
+/**
+ * fwnode_pcs_get - Retrieves a PCS from a firmware node
+ * @fwnode: firmware node
+ * @index: index fwnode PCS handle in firmware node
+ *
+ * Get a PCS from the firmware node at index.
+ *
+ * Returns: a pointer to the phylink_pcs or a negative
+ * error pointer. Can return -EPROBE_DEFER if the PCS is not
+ * present in global providers list (either due to driver
+ * still needs to be probed or it failed to probe/removed)
+ */
+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
+				   int index);
+
+/**
+ * fwnode_phylink_pcs_parse - generic PCS parse for fwnode PCS provider
+ * @fwnode: firmware node
+ * @available_pcs: pointer to preallocated array of PCS
+ * @num_pcs: where to store count of parsed PCS
+ *
+ * Generic helper function to fill available_pcs array with PCS parsed
+ * from a "pcs-handle" fwnode property defined in firmware node up to
+ * passed num_pcs.
+ *
+ * If available_pcs is NULL, num_pcs is updated with the count of the
+ * parsed PCS.
+ *
+ * Returns: 0 or a negative error.
+ */
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+			     struct phylink_pcs **available_pcs,
+			     unsigned int *num_pcs);
+#else
+static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
+						 int index)
+{
+	return ERR_PTR(-ENOENT);
+}
+
+static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+					   struct phylink_pcs **available_pcs,
+					   unsigned int *num_pcs)
+{
+	return -EOPNOTSUPP;
+}
+#endif
+
+#endif /* __LINUX_PCS_H */
-- 
2.48.1



From ansuelsmth at gmail.com  Sun May 11 13:12:32 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sun, 11 May 2025 22:12:32 +0200
Subject: [net-next PATCH v4 06/11] net: phylink: support late PCS provider attach
In-Reply-To: <20250511201250.3789083-1-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
Message-ID: <20250511201250.3789083-7-ansuelsmth@gmail.com>

Add support for late PCS provider attachment to a phylink instance.
This works by creating a global notifier for the PCS provider and
making each phylink instance that makes use of fwnode subscribe to
this notifier.

The PCS notifier will emit the event FWNODE_PCS_PROVIDER_ADD every time
a new PCS provider is added.

phylink will then react to this event and will call the new function
fwnode_phylink_pcs_get_from_fwnode() that will check if the PCS fwnode
provided by the event is present in the phy-handle property of the
phylink instance.

If a related PCS is found, then such PCS is added to the phylink
instance PCS list.

Then we link the PCS to the phylink instance if it's not disable and we
refresh the supported interfaces of the phylink instance.

Finally we check if we are in a major_config_failed scenario and trigger
an interface reconfiguration in the next phylink resolve.

In the example scenario where the link was previously torn down due to
removal of PCS, the link will be established again as the PCS came back
and is now available to phylink.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/pcs/pcs.c     | 40 ++++++++++++++++++++++++++++++
 drivers/net/phy/phylink.c | 52 +++++++++++++++++++++++++++++++++++++++
 include/linux/pcs/pcs.h   | 48 ++++++++++++++++++++++++++++++++++++
 3 files changed, 140 insertions(+)

diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
index 26d07a2edfce..409d06658167 100644
--- a/drivers/net/pcs/pcs.c
+++ b/drivers/net/pcs/pcs.c
@@ -22,6 +22,13 @@ struct fwnode_pcs_provider {
 
 static LIST_HEAD(fwnode_pcs_providers);
 static DEFINE_MUTEX(fwnode_pcs_mutex);
+static BLOCKING_NOTIFIER_HEAD(fwnode_pcs_notify_list);
+
+int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_register(&fwnode_pcs_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(register_fwnode_pcs_notifier);
 
 struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
 					  void *data)
@@ -55,6 +62,10 @@ int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
 
 	fwnode_dev_initialized(fwnode, true);
 
+	blocking_notifier_call_chain(&fwnode_pcs_notify_list,
+				     FWNODE_PCS_PROVIDER_ADD,
+				     fwnode);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
@@ -147,6 +158,35 @@ struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, int index)
 }
 EXPORT_SYMBOL_GPL(fwnode_pcs_get);
 
+struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+				   struct fwnode_handle *pcs_fwnode)
+{
+	struct fwnode_reference_args pcsspec;
+	int index = 0;
+	int ret;
+
+	/* Loop until we find a matching PCS node or
+	 * fwnode_parse_pcsspec() returns error
+	 * if we don't have any other PCS reference to check.
+	 */
+	while (true) {
+		ret = fwnode_parse_pcsspec(fwnode, index, NULL, &pcsspec);
+		if (ret)
+			return ERR_PTR(ret);
+
+		/* Exit loop if we found the matching PCS node */
+		if (pcsspec.fwnode == pcs_fwnode)
+			break;
+
+		/* Check the next PCS reference */
+		index++;
+	}
+
+	return fwnode_pcs_get(fwnode, index);
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_get_from_fwnode);
+
 static int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode,
 				    unsigned int *num_pcs)
 {
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 2f28c4c83062..1a4df0d24aa2 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -12,6 +12,7 @@
 #include <linux/netdevice.h>
 #include <linux/of.h>
 #include <linux/of_mdio.h>
+#include <linux/pcs/pcs.h>
 #include <linux/phy.h>
 #include <linux/phy_fixed.h>
 #include <linux/phylink.h>
@@ -61,6 +62,7 @@ struct phylink {
 
 	/* List of available PCS */
 	struct list_head pcs_list;
+	struct notifier_block fwnode_pcs_nb;
 
 	/* What interface are supported by the current link.
 	 * Can change on removal or addition of new PCS.
@@ -1909,6 +1911,51 @@ int phylink_set_fixed_link(struct phylink *pl,
 }
 EXPORT_SYMBOL_GPL(phylink_set_fixed_link);
 
+static int pcs_provider_notify(struct notifier_block *self,
+			       unsigned long val, void *data)
+{
+	struct phylink *pl = container_of(self, struct phylink, fwnode_pcs_nb);
+	struct fwnode_handle *pcs_fwnode = data;
+	struct phylink_pcs *pcs;
+
+	/* Check if the just added PCS provider is
+	 * in the phylink instance phy-handle property
+	 */
+	pcs = fwnode_phylink_pcs_get_from_fwnode(dev_fwnode(pl->config->dev),
+						 pcs_fwnode);
+	if (IS_ERR(pcs))
+		return NOTIFY_DONE;
+
+	/* Add the PCS */
+	rtnl_lock();
+
+	list_add(&pcs->list, &pl->pcs_list);
+
+	/* Link phylink if we are started */
+	if (!pl->phylink_disable_state)
+		pcs->phylink = pl;
+
+	/* Refresh supported interfaces */
+	phy_interface_copy(pl->supported_interfaces,
+			   pl->config->supported_interfaces);
+	list_for_each_entry(pcs, &pl->pcs_list, list)
+		phy_interface_or(pl->supported_interfaces,
+				 pl->supported_interfaces,
+				 pcs->supported_interfaces);
+
+	mutex_lock(&pl->state_mutex);
+	/* Force an interface reconfig if major config fail */
+	if (pl->major_config_failed)
+		pl->reconfig_interface = true;
+	mutex_unlock(&pl->state_mutex);
+
+	rtnl_unlock();
+
+	phylink_run_resolve(pl);
+
+	return NOTIFY_OK;
+}
+
 /**
  * phylink_create() - create a phylink instance
  * @config: a pointer to the target &struct phylink_config
@@ -1963,6 +2010,11 @@ struct phylink *phylink_create(struct phylink_config *config,
 				 pl->supported_interfaces,
 				 pcs->supported_interfaces);
 
+	if (!phy_interface_empty(config->pcs_interfaces)) {
+		pl->fwnode_pcs_nb.notifier_call = pcs_provider_notify;
+		register_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
+	}
+
 	pl->config = config;
 	if (config->type == PHYLINK_NETDEV) {
 		pl->netdev = to_net_dev(config->dev);
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
index 33244e3a442b..dfd3dc0f86f6 100644
--- a/include/linux/pcs/pcs.h
+++ b/include/linux/pcs/pcs.h
@@ -4,7 +4,24 @@
 
 #include <linux/phylink.h>
 
+enum fwnode_pcs_notify_event {
+	FWNODE_PCS_PROVIDER_ADD,
+};
+
 #if IS_ENABLED(CONFIG_FWNODE_PCS)
+/**
+ * register_fwnode_pcs_notifier - Register a notifier block for fwnode
+ *				  PCS events
+ * @nb: pointer to the notifier block
+ *
+ * Registers a notifier block to the fwnode_pcs_notify_list blocking
+ * notifier chain. This allows phylink instance to subscribe for
+ * PCS provider events.
+ *
+ * Returns: 0 or a negative error.
+ */
+int register_fwnode_pcs_notifier(struct notifier_block *nb);
+
 /**
  * fwnode_pcs_get - Retrieves a PCS from a firmware node
  * @fwnode: firmware node
@@ -20,6 +37,25 @@
 struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
 				   int index);
 
+/**
+ * fwnode_phylink_pcs_get_from_fwnode - Retrieves the PCS provided
+ *					by the firmware node from a
+ *					firmware node
+ * @fwnode: firmware node
+ * @pcs_fwnode: PCS firmware node
+ *
+ * Parse 'pcs-handle' in 'fwnode' and get the PCS that match
+ * 'pcs_fwnode' firmware node.
+ *
+ * Returns: a pointer to the phylink_pcs or a negative
+ * error pointer. Can return -EPROBE_DEFER if the PCS is not
+ * present in global providers list (either due to driver
+ * still needs to be probed or it failed to probe/removed)
+ */
+struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+				   struct fwnode_handle *pcs_fwnode);
+
 /**
  * fwnode_phylink_pcs_parse - generic PCS parse for fwnode PCS provider
  * @fwnode: firmware node
@@ -39,12 +75,24 @@ int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
 			     struct phylink_pcs **available_pcs,
 			     unsigned int *num_pcs);
 #else
+static inline int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+	return -EOPNOTSUPP;
+}
+
 static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
 						 int index)
 {
 	return ERR_PTR(-ENOENT);
 }
 
+static inline struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+				   struct fwnode_handle *pcs_fwnode)
+{
+	return ERR_PTR(-ENOENT);
+}
+
 static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
 					   struct phylink_pcs **available_pcs,
 					   unsigned int *num_pcs)
-- 
2.48.1



From ansuelsmth at gmail.com  Sun May 11 13:12:33 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sun, 11 May 2025 22:12:33 +0200
Subject: [net-next PATCH v4 07/11] dt-bindings: net: ethernet-controller: permit to define multiple PCS
In-Reply-To: <20250511201250.3789083-1-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
Message-ID: <20250511201250.3789083-8-ansuelsmth@gmail.com>

Drop the limitation of a single PCS in pcs-handle property. Multiple PCS
can be defined for an ethrnet-controller node to support various PHY
interface mode type.

It's very common for SoCs to have a 2 or more dedicated PCS for Base-X
(for example SGMII, 1000base-x, 2500base-x, ...) and Base-R (for example
USXGMII,10base-r, ...) with the MAC selecting one of the other based on
the attached PHY.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 Documentation/devicetree/bindings/net/ethernet-controller.yaml | 2 --
 1 file changed, 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
index 7cbf11bbe99c..60605b34d242 100644
--- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
@@ -84,8 +84,6 @@ properties:
 
   pcs-handle:
     $ref: /schemas/types.yaml#/definitions/phandle-array
-    items:
-      maxItems: 1
     description:
       Specifies a reference to a node representing a PCS PHY device on a MDIO
       bus to link with an external PHY (phy-handle) if exists.
-- 
2.48.1



From ansuelsmth at gmail.com  Sun May 11 13:12:34 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sun, 11 May 2025 22:12:34 +0200
Subject: [net-next PATCH v4 08/11] net: phylink: add .pcs_link_down PCS OP
In-Reply-To: <20250511201250.3789083-1-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
Message-ID: <20250511201250.3789083-9-ansuelsmth@gmail.com>

Permit for PCS driver to define specific operation to torn down the link
between the MAC and the PCS.

This might be needed for some PCS that reset counter or require special
reset to correctly work if the link needs to be restored later.

On phylink_link_down() call, the additional phylink_pcs_link_down() will
be called before .mac_link_down to torn down the link.

PCS driver will need to define .pcs_link_down to make use of this.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/phy/phylink.c | 8 ++++++++
 include/linux/phylink.h   | 2 ++
 2 files changed, 10 insertions(+)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 1a4df0d24aa2..39cd15e30598 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -1009,6 +1009,12 @@ static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
 		pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex);
 }
 
+static void phylink_pcs_link_down(struct phylink_pcs *pcs)
+{
+	if (pcs && pcs->ops->pcs_link_down)
+		pcs->ops->pcs_link_down(pcs);
+}
+
 static void phylink_pcs_disable_eee(struct phylink_pcs *pcs)
 {
 	if (pcs && pcs->ops->pcs_disable_eee)
@@ -1686,6 +1692,8 @@ static void phylink_link_down(struct phylink *pl)
 
 	phylink_deactivate_lpi(pl);
 
+	phylink_pcs_link_down(pl->pcs);
+
 	pl->mac_ops->mac_link_down(pl->config, pl->act_link_an_mode,
 				   pl->cur_interface);
 	phylink_info(pl, "Link is Down\n");
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index c5496c063b6a..8b3d1dfb83a1 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -494,6 +494,7 @@ struct phylink_pcs {
  * @pcs_an_restart: restart 802.3z BaseX autonegotiation.
  * @pcs_link_up: program the PCS for the resolved link configuration
  *               (where necessary).
+ * @pcs_link_down: torn down link between MAC and PCS.
  * @pcs_disable_eee: optional notification to PCS that EEE has been disabled
  *		     at the MAC.
  * @pcs_enable_eee: optional notification to PCS that EEE will be enabled at
@@ -521,6 +522,7 @@ struct phylink_pcs_ops {
 	void (*pcs_an_restart)(struct phylink_pcs *pcs);
 	void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode,
 			    phy_interface_t interface, int speed, int duplex);
+	void (*pcs_link_down)(struct phylink_pcs *pcs);
 	void (*pcs_disable_eee)(struct phylink_pcs *pcs);
 	void (*pcs_enable_eee)(struct phylink_pcs *pcs);
 	int (*pcs_pre_init)(struct phylink_pcs *pcs);
-- 
2.48.1



From ansuelsmth at gmail.com  Sun May 11 13:12:35 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sun, 11 May 2025 22:12:35 +0200
Subject: [net-next PATCH v4 09/11] dt-bindings: net: pcs: Document support for Airoha Ethernet PCS
In-Reply-To: <20250511201250.3789083-1-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
Message-ID: <20250511201250.3789083-10-ansuelsmth@gmail.com>

Document support for Airoha Ethernet PCS for AN7581 SoC.

Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
the various Serdes port supporting different Media Independent Interface
(10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).

This follow the new PCS provider with the use of #pcs-cells property.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 .../bindings/net/pcs/airoha,pcs.yaml          | 112 ++++++++++++++++++
 1 file changed, 112 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml

diff --git a/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
new file mode 100644
index 000000000000..8bcf7757c728
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/airoha,pcs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha Ethernet PCS and Serdes
+
+maintainers:
+  - Christian Marangi <ansuelsmth at gmail.com>
+
+description:
+  Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
+  the various Serdes port supporting different Media Independent Interface
+  (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).
+
+properties:
+  compatible:
+    enum:
+      - airoha,an7581-pcs-eth
+      - airoha,an7581-pcs-pon
+
+  reg:
+    items:
+      - description: XFI MAC reg
+      - description: HSGMII AN reg
+      - description: HSGMII PCS reg
+      - description: MULTI SGMII reg
+      - description: USXGMII reg
+      - description: HSGMII rate adaption reg
+      - description: XFI Analog register
+      - description: XFI PMA (Physical Medium Attachment) register
+
+  reg-names:
+    items:
+      - const: xfi_mac
+      - const: hsgmii_an
+      - const: hsgmii_pcs
+      - const: multi_sgmii
+      - const: usxgmii
+      - const: hsgmii_rate_adp
+      - const: xfi_ana
+      - const: xfi_pma
+
+  resets:
+    items:
+      - description: MAC reset
+      - description: PHY reset
+
+  reset-names:
+    items:
+      - const: mac
+      - const: phy
+
+  "#pcs-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - resets
+  - reset-names
+  - "#pcs-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/reset/airoha,en7581-reset.h>
+
+    pcs at 1fa08000 {
+        compatible = "airoha,an7581-pcs-pon";
+        reg = <0x1fa08000 0x1000>,
+              <0x1fa80000 0x60>,
+              <0x1fa80a00 0x164>,
+              <0x1fa84000 0x450>,
+              <0x1fa85900 0x338>,
+              <0x1fa86000 0x300>,
+              <0x1fa8a000 0x1000>,
+              <0x1fa8b000 0x1000>;
+        reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
+                    "multi_sgmii", "usxgmii",
+                    "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
+
+        resets = <&scuclk EN7581_XPON_MAC_RST>,
+                 <&scuclk EN7581_XPON_PHY_RST>;
+        reset-names = "mac", "phy";
+
+        #pcs-cells = <0>;
+    };
+
+    pcs at 1fa09000 {
+        compatible = "airoha,an7581-pcs-eth";
+        reg = <0x1fa09000 0x1000>,
+              <0x1fa70000 0x60>,
+              <0x1fa70a00 0x164>,
+              <0x1fa74000 0x450>,
+              <0x1fa75900 0x338>,
+              <0x1fa76000 0x300>,
+              <0x1fa7a000 0x1000>,
+              <0x1fa7b000 0x1000>;
+        reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
+                    "multi_sgmii", "usxgmii",
+                    "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
+
+        resets = <&scuclk EN7581_XSI_MAC_RST>,
+                 <&scuclk EN7581_XSI_PHY_RST>;
+        reset-names = "mac", "phy";
+
+        #pcs-cells = <0>;
+    };
-- 
2.48.1



From ansuelsmth at gmail.com  Sun May 11 13:12:36 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sun, 11 May 2025 22:12:36 +0200
Subject: [net-next PATCH v4 10/11] net: pcs: airoha: add PCS driver for Airoha SoC
In-Reply-To: <20250511201250.3789083-1-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
Message-ID: <20250511201250.3789083-11-ansuelsmth@gmail.com>

Add PCS driver for Airoha SoC for Ethernet Serdes and PCS and permit
usage of external PHY or connected SFP cage. Supported modes are
USXGMII, 10-BASER, 2500BASE-X, 1000BASE-X and SGMII.

The driver register as a PCS provider and supports poll mode to detect
PCS port state. While interrupt is supported by the HW, there are some
defect with the interrupt not fired on cable detach.

The PCS require complex calibration to correctly work and might require
multiple try until the signal detection module "lock" on the signal
level to correct work with the attached PHY.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/pcs/Kconfig      |    7 +
 drivers/net/pcs/Makefile     |    1 +
 drivers/net/pcs/pcs-airoha.c | 2921 ++++++++++++++++++++++++++++++++++
 3 files changed, 2929 insertions(+)
 create mode 100644 drivers/net/pcs/pcs-airoha.c

diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index 0d54bea1f663..724f1eeef133 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -11,6 +11,13 @@ config FWNODE_PCS
 	help
 		Firmware node PCS accessors
 
+config PCS_AIROHA
+	tristate "Airoha PCS driver"
+	select FWNODE_PCS
+	help
+	  This module provides helper to phylink for managing the Airoha
+	  PCS for SoC Ethernet Serdes and PCS.
+
 config PCS_XPCS
 	tristate "Synopsys DesignWare Ethernet XPCS"
 	select PHYLINK
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index 3005cdd89ab7..c48450f08fb7 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -2,6 +2,7 @@
 # Makefile for Linux PCS drivers
 
 obj-$(CONFIG_FWNODE_PCS)	+= pcs.o
+obj-$(CONFIG_PCS_AIROHA)	+= pcs-airoha.o
 pcs_xpcs-$(CONFIG_PCS_XPCS)	:= pcs-xpcs.o pcs-xpcs-plat.o \
 				   pcs-xpcs-nxp.o pcs-xpcs-wx.o
 
diff --git a/drivers/net/pcs/pcs-airoha.c b/drivers/net/pcs/pcs-airoha.c
new file mode 100644
index 000000000000..367158aa4f7b
--- /dev/null
+++ b/drivers/net/pcs/pcs-airoha.c
@@ -0,0 +1,2921 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth at gmail.com>
+ */
+
+#include <linux/device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pcs/pcs-provider.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/rtnetlink.h>
+
+/* SCU*/
+#define AIROHA_SCU_WAN_CONF			0x70
+#define   AIROHA_SCU_WAN_SEL			GENMASK(7, 0)
+#define   AIROHA_SCU_WAN_SEL_SGMII		FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10)
+#define   AIROHA_SCU_WAN_SEL_HSGMII		FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11)
+#define   AIROHA_SCU_WAN_SEL_USXGMII		FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x12)
+#define AIROHA_SCU_SSR3				0x94
+#define   AIROHA_SCU_ETH_XSI_SEL		GENMASK(14, 13)
+#define   AIROHA_SCU_ETH_XSI_USXGMII		FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x1)
+#define   AIROHA_SCU_ETH_XSI_HSGMII		FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x2)
+#define AIROHA_SCU_SSTR				0x9c
+#define   AIROHA_SCU_PON_XSI_SEL		GENMASK(10, 9)
+#define   AIROHA_SCU_PON_XSI_USXGMII		FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x1)
+#define   AIROHA_SCU_PON_XSI_HSGMII		FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x2)
+
+/* XFI_MAC */
+#define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG		0x0
+#define   AIROHA_PCS_XFI_RX_FRAG_LEN		GENMASK(26, 22)
+#define   AIROHA_PCS_XFI_TX_FRAG_LEN		GENMASK(21, 17)
+#define   AIROHA_PCS_XFI_IPG_NUM		GENMASK(15, 10)
+#define   AIROHA_PCS_XFI_TX_FC_EN		BIT(5)
+#define   AIROHA_PCS_XFI_RX_FC_EN		BIT(4)
+#define   AIROHA_PCS_XFI_RXMPI_STOP		BIT(3)
+#define   AIROHA_PCS_XFI_RXMBI_STOP		BIT(2)
+#define   AIROHA_PCS_XFI_TXMPI_STOP		BIT(1)
+#define   AIROHA_PCS_XFI_TXMBI_STOP		BIT(0)
+#define AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST	0x10
+#define   AIROHA_PCS_XFI_MAC_LOGIC_RST		BIT(0)
+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRH		0x60
+#define   AIROHA_PCS_XFI_MAC_MACADDRH		GENMASK(15, 0)
+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRL		0x64
+#define   AIROHA_PCS_XFI_MAC_MACADDRL		GENMASK(31, 0)
+#define AIROHA_PCS_XFI_MAC_XFI_CNT_CLR		0x100
+#define   AIROHA_PCS_XFI_GLB_CNT_CLR		BIT(0)
+
+/* HSGMII_AN */
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0	0x0
+#define   AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE	BIT(12)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART	BIT(9)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1	0x4 /* BMSR */
+#define   AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4	0x10
+#define   AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5	0x14 /* LPA */
+#define   AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11	0x2c
+#define   AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER	GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13	0x34
+#define   AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0)
+#define     AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5)
+#define     AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4)
+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2)
+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2)
+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1)
+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0)
+#define     AIROHA_PCS_HSGMII_AN_SIDEBAND_EN	BIT(1)
+#define     AIROHA_PCS_HSGMII_AN_SGMII_EN	BIT(0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60
+#define   AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE	BIT(0)
+
+/* HSGMII_PCS */
+#define AIROHA_PCS_HSGMII_PCS_CTROL_1		0x0
+#define   AIROHA_PCS_TBI_10B_MODE		BIT(30)
+#define   AIROHA_PCS_SGMII_SEND_AN_ERR_EN	BIT(24)
+#define   AIROHA_PCS_REMOTE_FAULT_DIS		BIT(12)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_3		0x8
+#define   AIROHA_PCS_HSGMII_PCS_LINK_STSTIME	GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_6		0x14
+#define   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14)
+#define   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13)
+#define   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12)
+#define   AIROHA_PCS_HSGMII_PCS_MAC_MODE	BIT(8)
+#define   AIROHA_PCS_HSGMII_PCS_TX_ENABLE	BIT(4)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT	BIT(1)
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_EN	BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20
+#define   AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11)
+#define   AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT	BIT(4)
+#define   AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2)
+#define   AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT	BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0)
+#define ARIOHA_PCS_HSGMII_PCS_STATE_2		0x104
+#define   AIROHA_PCS_HSGMII_PCS_RX_SYNC		BIT(5)
+#define   AIROHA_PCS_HSGMII_PCS_AN_DONE		BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_INT_STATE		0x15c
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4)
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS	BIT(3)
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2)
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC	BIT(1)
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE	BIT(0)
+
+/* MULTI_SGMII */
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0	0x14
+#define   AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0	BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18
+#define   AIROHA_PCS_LINK_MODE_P0		GENMASK(5, 4)
+#define   AIROHA_PCS_LINK_MODE_P0_2_5G		FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x3)
+#define   AIROHA_PCS_LINK_MODE_P0_1G		FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x2)
+#define   AIROHA_PCS_LINK_MODE_P0_100M		FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x1)
+#define   AIROHA_PCS_LINK_MODE_P0_10M		FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x0)
+#define   AIROHA_PCS_FORCE_SPD_MODE_P0		BIT(2)
+#define   AIROHA_PCS_FORCE_LINKDOWN_P0		BIT(1)
+#define   AIROHA_PCS_FORCE_LINKUP_P0		BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0	0x100
+#define   AIROHA_PCS_HSGMII_XFI_SEL		BIT(28)
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL	0x14c
+#define   AIROHA_PCS_HSGMII_PCS_INT		BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15	0x43c
+#define   AIROHA_PCS_LINK_STS_P0		BIT(3)
+#define   AIROHA_PCS_SPEED_STS_P0		GENMASK(2, 0)
+#define   AIROHA_PCS_SPEED_STS_P0_1G		FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x2)
+#define   AIROHA_PCS_SPEED_STS_P0_100M		FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x1)
+#define   AIROHA_PCS_SPEED_STS_P0_10M		FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18	0x448
+#define   AIROHA_PCS_P0_SGMII_IS_10		BIT(2)
+#define   AIROHA_PCS_P0_SGMII_IS_100		BIT(1)
+#define   AIROHA_PCS_P0_SGMII_IS_1000		BIT(0)
+
+/* HSGMII_RATE_ADP */
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0	0x0
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27)
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26)
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN	BIT(4)
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN	BIT(0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1	0x4
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16)
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6	0x18
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8	0x20
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11	0x2c
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \
+	FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \
+	FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \
+	FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \
+	FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \
+	FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6)
+#define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0	0x100
+#define   AIROHA_PCS_HSGMII_P0_DIS_MII_MODE	BIT(31)
+
+/* USXGMII */
+#define AIROHA_PCS_USXGMII_PCS_CTROL_1		0x0
+#define   AIROHA_PCS_USXGMII_SPEED_SEL_H	BIT(13)
+#define AIROHA_PCS_USXGMII_PCS_STUS_1		0x30
+#define   AIROHA_PCS_USXGMII_RX_LINK_STUS	BIT(12)
+#define   AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3)
+#define   AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2)
+#define   AIROHA_PCS_USXGMII_PCS_BLK_LK		BIT(0)
+#define AIROHA_PCS_USGMII_VENDOR_DEFINE_116	0x22c
+#define AIROHA_PCS_USXGMII_PCS_CTRL_0		0x2c0
+#define   AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN	BIT(24)
+#define   AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN	BIT(16)
+#define   AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN	BIT(8)
+#define   AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_1		0x2c4
+#define   AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN	BIT(24)
+#define   AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN	BIT(16)
+#define   AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8)
+#define   AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_2		0x2c8
+#define   AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24)
+#define   AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN	BIT(16)
+#define   AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN	BIT(8)
+#define   AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_3		0x2cc
+#define   AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24)
+#define   AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16)
+#define   AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN	BIT(8)
+#define   AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_2	0x2d8
+#define   AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24)
+#define   AIROHA_PCS_USXGMII_R_TYPE_E_INT	BIT(16)
+#define   AIROHA_PCS_USXGMII_R_TYPE_T_INT	BIT(8)
+#define   AIROHA_PCS_USXGMII_R_TYPE_D_INT	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_3	0x2dc
+#define   AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24)
+#define   AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16)
+#define   AIROHA_PCS_USXGMII_LINK_UP_ST_INT	BIT(8)
+#define   AIROHA_PCS_USXGMII_HI_BER_ST_INT	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_4		0x2e0
+#define   AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_4	0x2e4
+#define   AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0	0x2f8
+#define   AIROHA_PCS_USXGMII_AN_RESTART		BIT(8)
+#define   AIROHA_PCS_USXGMII_AN_ENABLE		BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_0	0x310
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE	GENMASK(30, 28)
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x0)
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x1)
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x2)
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x3)
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x4)
+#define   AIROHA_PCS_USXGMII_PARTNER_ABILITY	GENMASK(15, 0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_2	0x318
+#define   AIROHA_PCS_USXGMII_PCS_AN_COMPLETE	BIT(24)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6	0x31c
+#define   AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7	0x320
+#define   AIROHA_PCS_USXGMII_RATE_UPDATE_MODE	BIT(12)
+#define   AIROHA_PCS_USXGMII_MODE		GENMASK(10, 8)
+#define   AIROHA_PCS_USXGMII_MODE_10000		FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x0)
+#define   AIROHA_PCS_USXGMII_MODE_5000		FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x1)
+#define   AIROHA_PCS_USXGMII_MODE_2500		FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x2)
+#define   AIROHA_PCS_USXGMII_MODE_1000		FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x3)
+#define   AIROHA_PCS_USXGMII_MODE_100		FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x4)
+
+/* PMA_PHYA */
+#define AIROHA_PCS_ANA_PXP_CMN_EN		0x0
+#define   AIROHA_PCS_ANA_CMN_EN			BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN	0x4
+#define   AIROHA_PCS_ANA_JCPLL_CHP_IOFST	GENMASK(29, 24)
+#define   AIROHA_PCS_ANA_JCPLL_CHP_IBIAS	GENMASK(21, 16)
+#define   AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN	BIT(8)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR		0x8
+#define   AIROHA_PCS_ANA_JCPLL_LPF_BWR		GENMASK(28, 24)
+#define   AIROHA_PCS_ANA_JCPLL_LPF_BP		GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_JCPLL_LPF_BC		GENMASK(12, 8)
+#define   AIROHA_PCS_ANA_JCPLL_LPF_BR		GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC	0xc
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_DIV	GENMASK(26, 24)
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_CODE	GENMASK(23, 16)
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_OPTION	BIT(8)
+#define   AIROHA_PCS_ANA_JCPLL_LPF_BWC		GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC	0x10
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_KS		GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_KF		GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_KFC	GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14
+#define   AIROHA_PCS_ANA_JCPLL_POSTDIV_D5	BIT(24)
+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE	GENMASK(1, 0)
+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x3)
+#define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY	0x1c
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS	GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x3)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_EN	BIT(16)
+#define   AIROHA_PCS_ANA_JCPLL_PLL_RSTB		BIT(8)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY		GENMASK(2, 0)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x3)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x4)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x5)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x6)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM	0x20
+#define   AIROHA_PCS_ANA_JCPLL_SDM_OUT		BIT(24)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD		GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x3)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_MODE		GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_IFM		BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN	0x24
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF	GENMASK(28, 24)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN	GENMASK(18, 16)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x3)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x4)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN	BIT(8)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_HREN		BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN	0x28
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW	GENMASK(26, 24)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x3)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x4)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x6)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN	BIT(16)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW	GENMASK(26, 24)
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV		0x2c
+#define   AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR	GENMASK(26, 24)
+#define   AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN	BIT(16)
+#define   AIROHA_PCS_ANA_JCPLL_VCO_CFIX		GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_JCPLL_VCODIV		GENMASK(1, 0)
+#define   AIROHA_PCS_ANA_JCPLL_VCODIV_1		FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_VCODIV_2		FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x1)
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR	0x30
+#define   AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI	BIT(17)
+#define   AIROHA_PCS_ANA_JCPLL_SSC_EN		BIT(16)
+#define   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8)
+#define   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3)
+#define   AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR	GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN	0x34
+#define   AIROHA_PCS_ANA_JCPLL_SSC_DELTA1	GENMASK(23, 8)
+#define   AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN	BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA	0x38
+#define   AIROHA_PCS_ANA_JCPLL_SSC_PERIOD	GENMASK(31, 16)
+#define   AIROHA_PCS_ANA_JCPLL_SSC_DELTA	GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H	0x48
+#define   AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF	GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_JCPLL_SPARE_L		GENMASK(15, 8)
+#define     AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5))
+#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS	0x50
+#define   AIROHA_PCS_ANA_TXPLL_LPF_BC		GENMASK(28, 24)
+#define   AIROHA_PCS_ANA_TXPLL_LPF_BR		GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_TXPLL_CHP_IOFST	GENMASK(13, 8)
+#define   AIROHA_PCS_ANA_TXPLL_CHP_IBIAS	GENMASK(5, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP		0x54
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_OPTION	BIT(24)
+#define   AIROHA_PCS_ANA_TXPLL_LPF_BWC		GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_TXPLL_LPF_BWR		GENMASK(12, 8)
+#define   AIROHA_PCS_ANA_TXPLL_LPF_BP		GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE	0x58
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_KF		GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_KFC	GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_DIV	GENMASK(10, 8)
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_CODE	GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS	0x5c
+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE	GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x3)
+#define   AIROHA_PCS_ANA_TXPLL_POSTDIV_EN	BIT(8)
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_KS		GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL	0x64
+#define   AIROHA_PCS_ANA_TXPLL_PLL_RSTB		BIT(24)
+#define   AIROHA_PCS_ANA_TXPLL_RST_DLY		GENMASK(18, 16)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV	GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x3)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL	BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN	0x68
+#define   AIROHA_PCS_ANA_TXPLL_SDM_MODE		GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_IFM		BIT(16)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS	GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x3)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_EN	BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD	0x6c
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN	BIT(24)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_HREN		BIT(16)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_OUT		BIT(8)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD		GENMASK(1, 0)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x3)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN	0x70
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF	GENMASK(12, 8)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN	GENMASK(2, 0)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x3)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x4)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN	0x74
+#define   AIROHA_PCS_ANA_TXPLL_VCO_CFIX		GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_TXPLL_VCODIV		GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_TXPLL_VCODIV_1		FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_VCODIV_2		FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_VCODIV_2		FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW	GENMASK(10, 8)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x3)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x4)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x6)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN	BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN	0x78
+#define   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27)
+#define   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24)
+#define   AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR	GENMASK(18, 16)
+#define   AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR	GENMASK(10, 8)
+#define   AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN	BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN		0x7c
+#define   AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN	BIT(16)
+#define   AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI	BIT(8)
+#define   AIROHA_PCS_ANA_TXPLL_SSC_EN		BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1	0x80
+#define   AIROHA_PCS_ANA_TXPLL_SSC_DELTA	GENMASK(31, 16)
+#define   AIROHA_PCS_ANA_TXPLL_SSC_DELTA1	GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD	0x84
+#define   AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT	GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_TXPLL_LDO_OUT		GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_TXPLL_SSC_PERIOD	GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF	0x94
+#define   AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF	GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN		0xc4
+#define   AIROHA_PCS_ANA_TX_DMEDGEGEN_EN	BIT(24)
+#define   AIROHA_PCS_ANA_TX_CKLDO_EN		BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL	0xcc
+#define    AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE	BIT(24)
+#define    AIROHA_PCS_ANA_RX_PHY_CK_SEL		BIT(16) /* 0: from PR 1: from DES */
+#define AIROHA_PCS_ANA_PXP_RX_REV_0		0xd4
+#define   AIROHA_PCS_ANA_RX_REV_1		GENMASK(31, 16)
+#define     AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define     AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define     AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define     AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK	GENMASK(19, 18)
+#define     AIROHA_PCS_ANA_REV_1_FECUR_PWDB	BIT(16)
+#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV		0xd8
+#define   AIROHA_PCS_ANA_RX_TDC_CK_SEL		BIT(24)
+#define   AIROHA_PCS_ANA_RX_PHYCK_RSTB		BIT(16)
+#define   AIROHA_PCS_ANA_RX_PHYCK_SEL		GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_RX_PHYCK_DIV		GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc
+#define   AIROHA_PCS_ANA_CDR_PD_EDGE_DIS	BIT(8)
+#define   AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV	BIT(0)
+#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO	0xe8
+#define   AIROHA_PCS_ANA_CDR_LPF_TOP_LIM	GENMASK(26, 8)
+#define   AIROHA_PCS_ANA_CDR_LPF_RATIO		GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE	0xf4
+#define   AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF	BIT(24)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC	0xf8
+#define   AIROHA_PCS_ANA_CDR_PR_KBAND_DIV	GENMASK(26, 24)
+#define   AIROHA_PCS_ANA_CDR_PR_BETA_SEL	GENMASK(19, 16)
+#define   AIROHA_PCS_ANA_CDR_PR_VCOADC_OS	GENMASK(11, 8)
+#define   AIROHA_PCS_ANA_CDR_PR_BETA_DAC	GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc
+#define   AIROHA_PCS_ANA_CDR_PR_FBKSEL		GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_CDR_PR_VREG_DAC_BAND	GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL	GENMASK(10, 8)
+#define   AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL	GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN	0x10c
+#define   AIROHA_PCS_ANA_RX_DAC_MON		GENMASK(28, 24)
+#define   AIROHA_PCS_ANA_CDR_PR_CAP_EN		BIT(19)
+#define   AIROHA_PCS_ANA_CDR_BUF_IN_SR		GENMASK(18, 16)
+#define   AIROHA_PCS_ANA_CDR_PR_XFICK_EN	BIT(2)
+#define   AIROHA_PCS_ANA_CDR_PR_MONDPI_EN	BIT(1)
+#define   AIROHA_PCS_ANA_CDR_PR_MONDPR_EN	BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE		0x110
+#define   AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL	GENMASK(25, 24)
+#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH	0x114
+#define   AIROHA_PCS_ANA_RX_FE_50OHMS_SEL	GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL	GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_RX_SIGDET_PEAK		GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN	0x118
+#define   AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN	BIT(24)
+#define   AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN	BIT(16)
+#define   AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN	BIT(8)
+#define   AIROHA_PCS_ANA_RX_FE_EQ_HZEN		BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB	0x11c
+#define   AIROHA_PCS_ANA_FE_VCM_GEN_PWDB	BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW	0x120
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE		GENMASK(17, 8)
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(0))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(1))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(2))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(3))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(4))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(5))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(6))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(7))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(8))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(9))
+#define AIROHA_PCS_ANA_PXP_AEQ_CFORCE		0x13c
+#define   AIROHA_PCS_ANA_AEQ_OFORCE		GENMASK(19, 8)
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_SAOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(0))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(1))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(2))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(3))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(4))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(5))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(6))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(7))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_VGA		FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(8))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_CTLE	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(9))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_ATT		FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(10))
+#define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144
+#define   AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ	BIT(24)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ	0x148
+#define   AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ	BIT(24)
+#define   AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ	BIT(16)
+#define   AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ	BIT(8)
+#define   AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ	BIT(0)
+
+/* PMA_PHYD */
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0	0x0
+#define   AIROHA_PCS_PMA_SW_LCPLL_EN		BIT(24)
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1	0x4
+#define   AIROHA_PCS_PMA_LCPLL_MAN_PWDB		BIT(0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2	0x88
+#define   AIROHA_PCS_PMA_DATA_SHIFT		BIT(8)
+#define   AIROHA_PCS_PMA_EYECNT_FAST		BIT(0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0	0x8c
+#define   AIROHA_PCS_PMA_RX_OS_START		GENMASK(23, 8)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT		GENMASK(2, 0)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x0)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x1)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x2)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x3)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x4)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x5)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x6)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x7)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1	0x90
+#define   AIROHA_PCS_PMA_RX_PICAL_END		GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_RX_PICAL_START		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2	0x94
+#define   AIROHA_PCS_PMA_RX_PDOS_END		GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_RX_PDOS_START		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3	0x98
+#define   AIROHA_PCS_PMA_RX_FEOS_END		GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_RX_FEOS_START		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4	0x9c
+#define   AIROHA_PCS_PMA_RX_SDCAL_END		GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_RX_SDCAL_START		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5	0x100
+#define   AIROHA_PCS_PMA_RX_RDY			GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_RX_BLWC_RDY_EN		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6	0x104
+#define   AIROHA_PCS_PMA_RX_OS_END		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c
+#define   AIROHA_PCS_PMA_DISB_RX_RDY		BIT(24)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114
+#define   AIROHA_PCS_PMA_FORCE_RX_RDY		BIT(24)
+#define AIROHA_PCS_PMA_PHY_EQ_CTRL_3		0x120
+#define   AIROHA_PCS_PMA_EQ_DEBUG_SEL		GENMASK(17, 16)
+#define   AIROHA_PCS_PMA_FOM_NUM_ORDER		GENMASK(12, 8)
+#define   AIROHA_PCS_PMA_A_SEL			GENMASK(1, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1		0x14c
+#define   AIROHA_PCS_PMA_UNLOCK_CYCLECNT	GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_LOCK_CYCLECNT		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2		0x150
+#define   AIROHA_PCS_PMA_LOCK_TARGET_END	GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_LOCK_TARGET_BEG	GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3		0x154
+#define   AIROHA_PCS_PMA_UNLOCK_TARGET_END	GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_UNLOCK_TARGET_BEG	GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4		0x158
+#define   AIROHA_PCS_PMA_LOCK_UNLOCKTH		GENMASK(15, 12)
+#define   AIROHA_PCS_PMA_LOCK_LOCKTH		GENMASK(11, 8)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN	GENMASK(2, 0)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x0)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x1)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT	FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL	FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7)
+#define AIROHA_PCS_PMA_SS_RX_SIGDET_1		0x16c
+#define   AIROHA_PCS_PMA_SIGDET_EN		BIT(0)
+#define AIROHA_PCS_PMA_RX_FLL_1			0x174
+#define   AIROHA_PCS_PMA_LPATH_IDAC		GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_2			0x178
+#define   AIROHA_PCS_PMA_CK_RATE		GENMASK(18, 16)
+#define   AIROHA_PCS_PMA_CK_RATE_20		FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0)
+#define   AIROHA_PCS_PMA_CK_RATE_10		FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1)
+#define   AIROHA_PCS_PMA_CK_RATE_5		FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2)
+#define AIROHA_PCS_PMA_RX_FLL_5			0x184
+#define   AIROHA_PCS_PMA_FLL_IDAC_MIN		GENMASK(26, 16)
+#define   AIROHA_PCS_PMA_FLL_IDAC_MAX		GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_B		        0x19c
+#define   AIROHA_PCS_PMA_LOAD_EN		BIT(0)
+#define AIROHA_PCS_PMA_RX_RESET_1		0x208
+#define   AIROHA_PCS_PMA_SIGDET_RST_B		BIT(8)
+#define AIROHA_PCS_PMA_TX_RST_B			0x260
+#define   AIROHA_PCS_PMA_TXCALIB_RST_B		BIT(8)
+#define   AIROHA_PCS_PMA_TX_TOP_RST_B		BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_4		0x320
+#define   AIROHA_PCS_PMA_DISB_BLWC_OFFSET	BIT(24)
+#define AIROHA_PCS_PMA_RX_FORCE_MODE_9		0x330
+#define   AIROHA_PCS_PMA_FORCE_FBCK_LOCK	BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_8		0x33c
+#define   AIROHA_PCS_PMA_DISB_FBCK_LOCK		BIT(0)
+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0		0x38c
+#define   AIROHA_PCS_PMA_RX_SYS_EN_SEL		GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0	0x390
+#define   AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT	GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1	0x394
+#define   AIROHA_PCS_PMA_PLL_LOCK_TARGET_END	GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG	GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3	0x39c
+#define   AIROHA_PCS_PMA_PLL_LOCK_LOCKTH	GENMASK(11, 8)
+#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL		0x48c
+#define   AIROHA_PCS_PMA_DISB_LEQ		BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0	0x34c
+#define   AIROHA_PCS_PMA_XPON_CDR_PR_PD_PWDB	BIT(24)
+#define   AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB	BIT(16)
+#define   AIROHA_PCS_PMA_XPON_CDR_PW_PWDB	BIT(8)
+#define   AIROHA_PCS_PMA_XPON_RX_FE_PWDB	BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1	0x350
+#define   AIROHA_PCS_PMA_RX_SIDGET_PWDB		BIT(0)
+#define AIROHA_PCS_PMA_DIG_RESERVE_0		0x360
+#define AIROHA_PCS_PMA_DIG_RO_RESERVE_2		0x380
+#define AIROHA_PCS_PMA_XPON_RX_RESERVED_1	0x374
+#define   AIROHA_PCS_PMA_XPON_RX_RATE_CTRL	GENMASK(1, 0)
+#define AIROHA_PCS_PMA_SW_RST_SET		0x460
+#define   AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N	BIT(11)
+#define   AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N	BIT(10)
+#define   AIROHA_PCS_PMA_SW_HSG_RXPCS_BIST_RST_N BIT(9)
+#define   AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N	BIT(8)
+#define   AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N	BIT(7)
+#define   AIROHA_PCS_PMA_SW_TX_FIFO_RST_N	BIT(6)
+#define   AIROHA_PCS_PMA_SW_REF_RST_N		BIT(5)
+#define   AIROHA_PCS_PMA_SW_ALLPCS_RST_N	BIT(4)
+#define   AIROHA_PCS_PMA_SW_PMA_RST_N		BIT(3)
+#define   AIROHA_PCS_PMA_SW_TX_RST_N		BIT(2)
+#define   AIROHA_PCS_PMA_SW_RX_RST_N		BIT(1)
+#define   AIROHA_PCS_PMA_SW_RX_FIFO_RST_N	BIT(0)
+#define AIROHA_PCS_PMA_XPON_INT_EN_3		0x474
+#define   AIROHA_PCS_PMA_RX_SIGDET_INT_EN	BIT(16)
+#define AIROHA_PCS_PMA_XPON_INT_STA_3		0x47c
+#define   AIROHA_PCS_PMA_RX_SIGDET_INT		BIT(16)
+#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL		0x48c
+#define   AIROHA_PCS_PMA_DISB_LEQ		BIT(0)
+#define AIROHA_PCS_PMA_RX_FREQDET		0x530
+#define   AIROHA_PCS_PMA_FL_OUT			GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_FBCK_LOCK		BIT(0)
+#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL	0x580
+#define   AIROHA_PCS_PMA_PON_TX_RATE_CTRL	GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN	0x768
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PEAKING_CTRL BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_PEAKING_CTRL GENMASK(19, 16)
+#define AIROHA_PCS_PMA_PXP_AEQ_SPEED		0x76c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL	BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_OSR_SEL	GENMASK(17, 16)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C0B		0x778
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1	GENMASK(20, 16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B	GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_TERM_SEL		0x77c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL	GENMASK(2, 0)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C1		0x780
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2	GENMASK(20, 16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1	GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL		0x784
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC		0x794
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC	GENMASK(10, 0)
+#define     AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8)
+#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW	0x798
+#define   AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW	GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_VOS		0x79c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS	BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_FE_VOS	GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW	0x800
+#define   AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW	GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_AEQ_BYPASS		0x80c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON	BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON	BIT(16)
+#define AIROHA_PCS_PMA_PXP_AEQ_RSTB		0x814
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL	BIT(16)
+#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA	0x818
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB	BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB		0x81c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN	0x820
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB	0x824
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB	BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN	0x828
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN	BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN	BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B	0x84c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B	 BIT(0)
+#define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN	0x854
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN	BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN	BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN		0x874
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL	BIT(16)
+#define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL		0x88c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_PWDB		0x894
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN	BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB	 BIT(0)
+
+#define AIROHA_PCS_MAX_CALIBRATION_TRY		50
+#define AIROHA_PCS_MAX_NUM_RSTS			2
+
+enum xfi_port_type {
+	AIROHA_PCS_ETH,
+	AIROHA_PCS_PON,
+};
+
+struct airoha_pcs_match_data {
+	enum xfi_port_type port_type;
+};
+
+struct airoha_pcs_priv {
+	struct device *dev;
+	const struct airoha_pcs_match_data *data;
+	phy_interface_t interface;
+
+	struct regmap *scu;
+
+	struct regmap *xfi_mac;
+	struct regmap *hsgmii_an;
+	struct regmap *hsgmii_pcs;
+	struct regmap *hsgmii_rate_adp;
+	struct regmap *multi_sgmii;
+	struct regmap *usxgmii_pcs;
+
+	struct regmap *xfi_pma;
+	struct regmap *xfi_ana;
+
+	struct reset_control_bulk_data rsts[AIROHA_PCS_MAX_NUM_RSTS];
+
+	struct phylink_pcs pcs;
+};
+
+static struct airoha_pcs_priv *phylink_pcs_to_airoha_pcs_port(struct phylink_pcs *pcs)
+{
+	return container_of(pcs, struct airoha_pcs_priv, pcs);
+}
+
+static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv,
+				     phy_interface_t interface)
+{
+	u32 xsi_sel;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		xsi_sel = AIROHA_SCU_ETH_XSI_HSGMII;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+	default:
+		xsi_sel = AIROHA_SCU_ETH_XSI_USXGMII;
+	}
+
+	regmap_update_bits(priv->scu, AIROHA_SCU_SSR3,
+			   AIROHA_SCU_ETH_XSI_SEL,
+			   xsi_sel);
+}
+
+static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv,
+				     phy_interface_t interface)
+{
+	u32 xsi_sel, wan_sel;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+		wan_sel = AIROHA_SCU_WAN_SEL_SGMII;
+		xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX:
+		wan_sel = AIROHA_SCU_WAN_SEL_HSGMII;
+		xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+	default:
+		wan_sel = AIROHA_SCU_WAN_SEL_USXGMII;
+		xsi_sel = AIROHA_SCU_PON_XSI_USXGMII;
+	}
+
+	regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+			   AIROHA_SCU_PON_XSI_SEL,
+			   xsi_sel);
+
+	regmap_update_bits(priv->scu, AIROHA_SCU_WAN_CONF,
+			   AIROHA_SCU_WAN_SEL,
+			   wan_sel);
+}
+
+static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv,
+				phy_interface_t interface)
+{
+	int ret;
+
+	switch (priv->data->port_type) {
+	case AIROHA_PCS_ETH:
+		airoha_pcs_setup_scu_eth(priv, interface);
+		break;
+	case AIROHA_PCS_PON:
+		airoha_pcs_setup_scu_pon(priv, interface);
+		break;
+	}
+
+	ret = reset_control_bulk_assert(ARRAY_SIZE(priv->rsts),
+					priv->rsts);
+	if (ret)
+		return ret;
+
+	ret = reset_control_bulk_deassert(ARRAY_SIZE(priv->rsts),
+					  priv->rsts);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv)
+{
+	regmap_set_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+			AIROHA_PCS_HSGMII_XFI_SEL);
+
+	/* Disable Hibernation */
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1,
+			  AIROHA_PCS_USXGMII_SPEED_SEL_H);
+
+	/* FIXME: wait Airoha */
+	/* Avoid PCS sending garbage to MAC in some HW revision (E0) */
+	regmap_write(priv->usxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0);
+}
+
+static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv)
+{
+	regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+			  AIROHA_PCS_HSGMII_XFI_SEL);
+
+	regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+			AIROHA_PCS_TBI_10B_MODE);
+}
+
+static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv)
+{
+	regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+			  AIROHA_PCS_HSGMII_XFI_SEL);
+
+	regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+			AIROHA_PCS_TBI_10B_MODE);
+
+	regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6,
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L,
+			   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, 0x07070707));
+
+	regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8,
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C,
+			   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, 0xff));
+}
+
+static void airoha_pcs_init(struct airoha_pcs_priv *priv,
+			    phy_interface_t interface)
+{
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+		airoha_pcs_init_sgmii(priv);
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX:
+		airoha_pcs_init_hsgmii(priv);
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		airoha_pcs_init_usxgmii(priv);
+		break;
+	default:
+		return;
+	}
+}
+
+static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv)
+{
+	/* Disable every interrupt */
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+			  AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT |
+			  AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT |
+			  AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT |
+			  AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT |
+			  AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT);
+
+	/* Clear interrupt */
+	regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+			AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+			AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+			AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+			AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+			AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+			  AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+			  AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+			  AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+			  AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+			  AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+}
+
+static void airoha_pcs_interrupt_init_usxgmii(struct airoha_pcs_priv *priv)
+{
+	/* Disable every Interrupt */
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_0,
+			  AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN |
+			  AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN |
+			  AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN |
+			  AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN);
+
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_1,
+			  AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN |
+			  AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN |
+			  AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN |
+			  AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN);
+
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_2,
+			  AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN |
+			  AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN |
+			  AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN |
+			  AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN);
+
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_3,
+			  AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN |
+			  AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN |
+			  AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN |
+			  AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN);
+
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_4,
+			  AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN);
+
+	/* Clear any pending interrupt */
+	regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_2,
+			AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT |
+			AIROHA_PCS_USXGMII_R_TYPE_E_INT |
+			AIROHA_PCS_USXGMII_R_TYPE_T_INT |
+			AIROHA_PCS_USXGMII_R_TYPE_D_INT);
+
+	regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_3,
+			AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT |
+			AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT |
+			AIROHA_PCS_USXGMII_LINK_UP_ST_INT |
+			AIROHA_PCS_USXGMII_HI_BER_ST_INT);
+
+	regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_4,
+			AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT);
+
+	/* Interrupt saddly seems to be not weel supported for Link Down.
+	 * PCS Poll is a must to correctly read and react on Cable Deatch
+	 * as only cable attach interrupt are fired and Link Down interrupt
+	 * are fired only in special case like AN restart.
+	 */
+}
+
+static void airoha_pcs_interrupt_init(struct airoha_pcs_priv *priv,
+				      phy_interface_t interface)
+{
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		return airoha_pcs_interrupt_init_sgmii(priv);
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		return airoha_pcs_interrupt_init_usxgmii(priv);
+	default:
+		return;
+	}
+}
+
+static void airoha_pcs_jcpll_bringup(struct airoha_pcs_priv *priv,
+				     phy_interface_t interface)
+{
+	u32 kband_vref;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		kband_vref = 0x10;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		kband_vref = 0xf;
+		break;
+	default:
+		return;
+	}
+
+	/* Setup LDO */
+	usleep_range(200, 300);
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H,
+			AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO);
+
+	/* Setup RSTB */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,
+			   AIROHA_PCS_ANA_JCPLL_RST_DLY,
+			   AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200);
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,
+			AIROHA_PCS_ANA_JCPLL_PLL_RSTB);
+
+	/* Enable PLL force selection and Force Disable */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN);
+
+	/* Setup SDM */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,
+			   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS |
+			   AIROHA_PCS_ANA_JCPLL_SDM_DI_EN,
+			   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM,
+			   AIROHA_PCS_ANA_JCPLL_SDM_OUT |
+			   AIROHA_PCS_ANA_JCPLL_SDM_ORD |
+			   AIROHA_PCS_ANA_JCPLL_SDM_MODE |
+			   AIROHA_PCS_ANA_JCPLL_SDM_IFM,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0) |
+			   AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_MODE, 0x0));
+
+	regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN,
+			  AIROHA_PCS_ANA_JCPLL_SDM_HREN);
+
+	/* Setup SSC */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA,
+			   AIROHA_PCS_ANA_JCPLL_SSC_PERIOD |
+			   AIROHA_PCS_ANA_JCPLL_SSC_DELTA,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_PERIOD, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA, 0x0));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN,
+			   AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 |
+			   AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA1, 0x0));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR,
+			   AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI |
+			   AIROHA_PCS_ANA_JCPLL_SSC_EN |
+			   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L |
+			   AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x0));
+
+	/* Setup LPF */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN,
+			   AIROHA_PCS_ANA_JCPLL_CHP_IOFST |
+			   AIROHA_PCS_ANA_JCPLL_CHP_IBIAS |
+			   AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IOFST, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IBIAS, 0x18));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR,
+			   AIROHA_PCS_ANA_JCPLL_LPF_BWR |
+			   AIROHA_PCS_ANA_JCPLL_LPF_BP |
+			   AIROHA_PCS_ANA_JCPLL_LPF_BC |
+			   AIROHA_PCS_ANA_JCPLL_LPF_BR,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWR, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BP, 0x10) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BC, 0x1f) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BR, BIT(3) | BIT(1)));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC,
+			   AIROHA_PCS_ANA_JCPLL_LPF_BWC,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWC, 0x0));
+
+	/* Setup VCO */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV,
+			   AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR |
+			   AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN |
+			   AIROHA_PCS_ANA_JCPLL_VCO_CFIX,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR, 0x4) |
+			   AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_CFIX, 0x1));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR,
+			   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L |
+			   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H |
+			   AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H, 0x3) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x3));
+
+	/* Setup PCW */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW,
+			   AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW,
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, 0x25800000));
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW);
+
+	/* Setup DIV */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE,
+			   AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 |
+			   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE,
+			   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV,
+			   AIROHA_PCS_ANA_JCPLL_VCODIV,
+			   AIROHA_PCS_ANA_JCPLL_VCODIV_1);
+
+	/* Setup KBand */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC,
+			   AIROHA_PCS_ANA_JCPLL_KBAND_KS |
+			   AIROHA_PCS_ANA_JCPLL_KBAND_KF |
+			   AIROHA_PCS_ANA_JCPLL_KBAND_KFC,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KS, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KF, 0x3) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KFC, 0x0));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC,
+			   AIROHA_PCS_ANA_JCPLL_KBAND_DIV |
+			   AIROHA_PCS_ANA_JCPLL_KBAND_CODE |
+			   AIROHA_PCS_ANA_JCPLL_KBAND_OPTION,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_DIV, 0x2) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_CODE, 0xe4));
+
+	/* Setup TCL */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H,
+			   AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF, kband_vref));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN,
+			   AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF |
+			   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN |
+			   AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF, 0x5) |
+			   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 |
+			   AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN,
+			   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW |
+			   AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN,
+			   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 |
+			   AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN);
+
+	/* Enable PLL */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+			AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN);
+
+	/* Enale PLL Output */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN |
+			AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN);
+}
+
+static void airoha_pcs_txpll_bringup(struct airoha_pcs_priv *priv,
+				     phy_interface_t interface)
+{
+	u32 lpf_chp_ibias, lpf_bp, lpf_bwr, lpf_bwc;
+	u32 vco_cfix;
+	u32 pcw;
+	u32 tcl_amp_vref;
+	bool sdm_hren;
+	bool vcodiv;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+		lpf_chp_ibias = 0xf;
+		lpf_bp = BIT(1);
+		lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+		lpf_bwc = BIT(4) | BIT(3);
+		vco_cfix = BIT(1) | BIT(0);
+		pcw = BIT(27);
+		tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+		vcodiv = false;
+		sdm_hren = false;
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX:
+		lpf_chp_ibias = 0xa;
+		lpf_bp = BIT(2) | BIT(0);
+		lpf_bwr = 0;
+		lpf_bwc = 0;
+		vco_cfix = 0;
+		pcw = BIT(27) | BIT(25);
+		tcl_amp_vref = BIT(3) | BIT(2) | BIT(0);
+		vcodiv = true;
+		sdm_hren = false;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		lpf_chp_ibias = 0xf;
+		lpf_bp = BIT(1);
+		lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+		lpf_bwc = BIT(4) | BIT(3);
+		vco_cfix = BIT(0);
+		pcw = BIT(27) | BIT(22);
+		tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+		vcodiv = false;
+		sdm_hren = true;
+		break;
+	default:
+		return;
+	}
+
+	/* Setup VCO LDO Output */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD,
+			   AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT |
+			   AIROHA_PCS_ANA_TXPLL_LDO_OUT,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT, 0x1) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_OUT, 0x1));
+
+	/* Setup RSTB */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL,
+			   AIROHA_PCS_ANA_TXPLL_PLL_RSTB |
+			   AIROHA_PCS_ANA_TXPLL_RST_DLY |
+			   AIROHA_PCS_ANA_TXPLL_REFIN_DIV |
+			   AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL,
+			   AIROHA_PCS_ANA_TXPLL_PLL_RSTB |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_RST_DLY, 0x4) |
+			   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 |
+			   AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL);
+
+	/* Enable PLL force selection and Force Disable */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN);
+
+	/* Setup SDM */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN,
+			   AIROHA_PCS_ANA_TXPLL_SDM_MODE |
+			   AIROHA_PCS_ANA_TXPLL_SDM_IFM |
+			   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS |
+			   AIROHA_PCS_ANA_TXPLL_SDM_DI_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SDM_MODE, 0) |
+			   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD,
+			   AIROHA_PCS_ANA_TXPLL_SDM_HREN |
+			   AIROHA_PCS_ANA_TXPLL_SDM_OUT |
+			   AIROHA_PCS_ANA_TXPLL_SDM_ORD,
+			   (sdm_hren ? AIROHA_PCS_ANA_TXPLL_SDM_HREN : 0) |
+			   AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM);
+
+	/* Setup SSC */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1,
+			   AIROHA_PCS_ANA_TXPLL_SSC_DELTA |
+			   AIROHA_PCS_ANA_TXPLL_SSC_DELTA1,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA1, 0x0));
+
+	regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN,
+			  AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN |
+			  AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI |
+			  AIROHA_PCS_ANA_TXPLL_SSC_EN);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD,
+			   AIROHA_PCS_ANA_TXPLL_SSC_PERIOD,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_PERIOD, 0x0));
+
+	/* Setup LPF */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS,
+			   AIROHA_PCS_ANA_TXPLL_LPF_BC |
+			   AIROHA_PCS_ANA_TXPLL_LPF_BR |
+			   AIROHA_PCS_ANA_TXPLL_CHP_IOFST |
+			   AIROHA_PCS_ANA_TXPLL_CHP_IBIAS,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BC, 0x1f) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BR, 0x5) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IOFST, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IBIAS, lpf_chp_ibias));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,
+			   AIROHA_PCS_ANA_TXPLL_LPF_BWC |
+			   AIROHA_PCS_ANA_TXPLL_LPF_BWR |
+			   AIROHA_PCS_ANA_TXPLL_LPF_BP,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWC, lpf_bwc) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWR, lpf_bwr) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BP, lpf_bp));
+
+	/* Setup VCO */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
+			   AIROHA_PCS_ANA_TXPLL_VCO_CFIX,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_CFIX, vco_cfix));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN,
+			   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L |
+			   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H |
+			   AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR |
+			   AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR |
+			   AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H, 0x4) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR, 0x4) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR, 0x7) |
+			   AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN);
+
+	/* Setup PCW */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW,
+			   AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW);
+
+	/* Setup KBand */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE,
+			   AIROHA_PCS_ANA_TXPLL_KBAND_KF |
+			   AIROHA_PCS_ANA_TXPLL_KBAND_KFC |
+			   AIROHA_PCS_ANA_TXPLL_KBAND_DIV |
+			   AIROHA_PCS_ANA_TXPLL_KBAND_CODE,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KF, 0x3) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KFC, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_DIV, 0x4) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_CODE, 0xe4));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS,
+			   AIROHA_PCS_ANA_TXPLL_KBAND_KS,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KS, 0x1));
+
+	regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,
+			  AIROHA_PCS_ANA_TXPLL_KBAND_OPTION);
+
+	/* Setup DIV */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS,
+			   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE |
+			   AIROHA_PCS_ANA_TXPLL_POSTDIV_EN,
+			   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
+			   AIROHA_PCS_ANA_TXPLL_VCODIV,
+			   vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 :
+				    AIROHA_PCS_ANA_TXPLL_VCODIV_1);
+
+	/* Setup TCL */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF,
+			   AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF, 0xf));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN,
+			   AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF |
+			   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF, tcl_amp_vref) |
+			   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
+			   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW |
+			   AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN,
+			   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 |
+			   AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN);
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD,
+			AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN);
+
+	/* Enable PLL */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+			AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN);
+
+	/* Enale PLL Output */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN |
+			AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN);
+}
+
+static void airoha_pcs_pll_bringup(struct airoha_pcs_priv *priv,
+				   phy_interface_t interface)
+{
+	airoha_pcs_jcpll_bringup(priv, interface);
+
+	usleep_range(200, 300);
+
+	airoha_pcs_txpll_bringup(priv, interface);
+
+	usleep_range(200, 300);
+}
+
+static void airoha_pcs_tx_bringup(struct airoha_pcs_priv *priv,
+				  phy_interface_t interface)
+{
+	u32 tx_rate_ctrl;
+	u32 ckin_divisor;
+	u32 fir_cn1, fir_c0b, fir_c1;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+		ckin_divisor = BIT(1);
+		tx_rate_ctrl = BIT(0);
+		fir_cn1 = 0;
+		fir_c0b = 12;
+		fir_c1 = 0;
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX:
+		ckin_divisor = BIT(2);
+		tx_rate_ctrl = BIT(0);
+		fir_cn1 = 0;
+		fir_c0b = 11;
+		fir_c1 = 1;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		ckin_divisor = BIT(2) | BIT(0);
+		tx_rate_ctrl = BIT(1);
+		fir_cn1 = 1;
+		fir_c0b = 1;
+		fir_c1 = 11;
+		break;
+	default:
+		return;
+	}
+
+	/* Set TX rate ctrl */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL,
+			   AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+			   FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+				      tx_rate_ctrl));
+
+	/* Setup TX Config */
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TX_CKLDO_EN,
+			AIROHA_PCS_ANA_TX_DMEDGEGEN_EN |
+			AIROHA_PCS_ANA_TX_CKLDO_EN);
+
+	udelay(1);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL |
+			AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL);
+
+	/* FIXME: Ask Airoha TX term is OK to reset? */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR,
+				      ckin_divisor) |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL, 0x0));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+				      tx_rate_ctrl));
+
+	/* Setup TX FIR Load Parameters (Reference 660mV) */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1));
+
+	/* Reset TX Bar */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_TX_RST_B,
+			AIROHA_PCS_PMA_TXCALIB_RST_B | AIROHA_PCS_PMA_TX_TOP_RST_B);
+}
+
+static void airoha_pcs_rx_bringup(struct airoha_pcs_priv *priv,
+				  phy_interface_t interface)
+{
+	u32 rx_rate_ctrl;
+	u32 osr;
+	u32 pr_cdr_beta_dac;
+	u32 cdr_pr_buf_in_sr;
+	bool cdr_pr_cap_en;
+	u32 sigdet_vth_sel;
+	u32 phyck_div, phyck_sel;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+		osr = BIT(1) | BIT(0); /* 1.25G */
+		pr_cdr_beta_dac = BIT(3);
+		rx_rate_ctrl = 0;
+		cdr_pr_cap_en = false;
+		cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+		sigdet_vth_sel = BIT(2) | BIT(1);
+		phyck_div = BIT(5) | BIT(3) | BIT(0);
+		phyck_sel = BIT(0);
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX:
+		osr = BIT(0); /* 2.5G */
+		pr_cdr_beta_dac = BIT(2) | BIT(1);
+		rx_rate_ctrl = 0;
+		cdr_pr_cap_en = true;
+		cdr_pr_buf_in_sr = BIT(2) | BIT(1);
+		sigdet_vth_sel = BIT(2) | BIT(1);
+		phyck_div = BIT(3) | BIT(1) | BIT(0);
+		phyck_sel = BIT(0);
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		osr = 0; /* 10G */
+		cdr_pr_cap_en = false;
+		pr_cdr_beta_dac = BIT(3);
+		rx_rate_ctrl = BIT(1);
+		cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+		sigdet_vth_sel = BIT(1);
+		phyck_div = BIT(6) | BIT(1);
+		phyck_sel = BIT(1);
+		break;
+	default:
+		return;
+	}
+
+	/* Set RX rate ctrl */
+	if (interface == PHY_INTERFACE_MODE_2500BASEX)
+		regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_2,
+				   AIROHA_PCS_PMA_CK_RATE,
+				   AIROHA_PCS_PMA_CK_RATE_10);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1,
+			   AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,
+			   FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL, rx_rate_ctrl));
+
+	/* Setup RX Path */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_5,
+			   AIROHA_PCS_PMA_FLL_IDAC_MIN |
+			   AIROHA_PCS_PMA_FLL_IDAC_MAX,
+			   FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) |
+			   FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x3ff));
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ,
+			AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ |
+			AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ |
+			AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ |
+			AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ);
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB,
+			AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ);
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB,
+			AIROHA_PCS_ANA_FE_VCM_GEN_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1,
+			AIROHA_PCS_PMA_LCPLL_MAN_PWDB);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_AEQ_CFORCE,
+			   AIROHA_PCS_ANA_AEQ_OFORCE,
+			   AIROHA_PCS_ANA_AEQ_OFORCE_CTLE);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW,
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE,
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4,
+			  AIROHA_PCS_PMA_DISB_BLWC_OFFSET);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL,
+			  AIROHA_PCS_PMA_DISB_LEQ);
+
+	regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV,
+			  AIROHA_PCS_ANA_CDR_PD_EDGE_DIS |
+			  AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_BYPASS,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON |
+			   AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL |
+			AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN,
+			   AIROHA_PCS_ANA_RX_DAC_MON |
+			   AIROHA_PCS_ANA_CDR_PR_XFICK_EN |
+			   AIROHA_PCS_ANA_CDR_PR_MONDPI_EN |
+			   AIROHA_PCS_ANA_CDR_PR_MONDPR_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_DAC_MON, 0x0) |
+			   AIROHA_PCS_ANA_CDR_PR_XFICK_EN);
+
+	/* Setup FE Gain and FE Peacking */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, 0x0));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PEAKING_CTRL |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_PEAKING_CTRL,
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_PEAKING_CTRL, 0x0));
+
+	/* Setup FE VOS */
+	if (interface != PHY_INTERFACE_MODE_USXGMII &&
+	    interface != PHY_INTERFACE_MODE_10GBASER)
+		regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+				   AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+				   AIROHA_PCS_PMA_FORCE_DA_FE_VOS,
+				   AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+				   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_FE_VOS, 0x0));
+
+	/* Setup FLL PR FMeter (no bypass mode)*/
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_0,
+			   AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT,
+			   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, 0x1));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_1,
+			   AIROHA_PCS_PMA_PLL_LOCK_TARGET_END |
+			   AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG,
+			   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_END, 0xffff) |
+			   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, 0x0));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_3,
+			   AIROHA_PCS_PMA_PLL_LOCK_LOCKTH,
+			   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, 0x1));
+
+	/* FIXME: Warn and Ask Airoha about typo in air_eth_xsgmii.c line 1391 */
+	/* AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL is set 0x0 in SDK but seems a typo */
+	/* Setup REV */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_REV_0,
+			   AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL |
+			   AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL |
+			   AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK,
+			   FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL, BIT(2)) |
+			   FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL, BIT(2)) |
+			   FIELD_PREP(AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK, 0x0));
+
+	/* Setup Rdy Timeout */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5,
+			   AIROHA_PCS_PMA_RX_RDY |
+			   AIROHA_PCS_PMA_RX_BLWC_RDY_EN,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) |
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5));
+
+	/* Setup CaBoundry Init */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0,
+			   AIROHA_PCS_PMA_RX_OS_START |
+			   AIROHA_PCS_PMA_OSC_SPEED_OPT,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1) |
+			   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6,
+			   AIROHA_PCS_PMA_RX_OS_END,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1,
+			   AIROHA_PCS_PMA_RX_PICAL_END |
+			   AIROHA_PCS_PMA_RX_PICAL_START,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x32) |
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4,
+			   AIROHA_PCS_PMA_RX_SDCAL_END |
+			   AIROHA_PCS_PMA_RX_SDCAL_START,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x32) |
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2,
+			   AIROHA_PCS_PMA_RX_PDOS_END |
+			   AIROHA_PCS_PMA_RX_PDOS_START,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x32) |
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3,
+			   AIROHA_PCS_PMA_RX_FEOS_END |
+			   AIROHA_PCS_PMA_RX_FEOS_START,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x32) |
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2));
+
+	/* Setup By Serdes*/
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+			   AIROHA_PCS_PMA_FORCE_DA_OSR_SEL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr));
+
+	/* Setup RX OSR */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV,
+			   AIROHA_PCS_ANA_CDR_PD_EDGE_DIS,
+			   osr ? AIROHA_PCS_ANA_CDR_PD_EDGE_DIS : 0);
+
+	/* Setup CDR LPF Ratio */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO,
+			   AIROHA_PCS_ANA_CDR_LPF_TOP_LIM |
+			   AIROHA_PCS_ANA_CDR_LPF_RATIO,
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_TOP_LIM, 0x20000) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_RATIO, osr));
+
+	/* Setup CDR PR */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC,
+			   AIROHA_PCS_ANA_CDR_PR_KBAND_DIV |
+			   AIROHA_PCS_ANA_CDR_PR_BETA_SEL |
+			   AIROHA_PCS_ANA_CDR_PR_VCOADC_OS |
+			   AIROHA_PCS_ANA_CDR_PR_BETA_DAC,
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_KBAND_DIV, 0x4) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_SEL, 0x1) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VCOADC_OS, 0x8) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_DAC, pr_cdr_beta_dac));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL,
+			   AIROHA_PCS_ANA_CDR_PR_FBKSEL |
+			   AIROHA_PCS_ANA_CDR_PR_VREG_DAC_BAND |
+			   AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL |
+			   AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL,
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_FBKSEL, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_DAC_BAND, pr_cdr_beta_dac) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL, 0x6) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL, 0x6));
+
+	/* Setup Eye Mon */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_3,
+			   AIROHA_PCS_PMA_EQ_DEBUG_SEL |
+			   AIROHA_PCS_PMA_FOM_NUM_ORDER |
+			   AIROHA_PCS_PMA_A_SEL,
+			   FIELD_PREP(AIROHA_PCS_PMA_EQ_DEBUG_SEL, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) |
+			   FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2,
+			   AIROHA_PCS_PMA_DATA_SHIFT |
+			   AIROHA_PCS_PMA_EYECNT_FAST,
+			   AIROHA_PCS_PMA_EYECNT_FAST);
+
+	/* Calibration Start */
+
+	/* Enable SYS */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0,
+			   AIROHA_PCS_PMA_RX_SYS_EN_SEL,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1));
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0,
+			AIROHA_PCS_PMA_SW_LCPLL_EN);
+
+	usleep_range(500, 600);
+
+	/* Setup FLL PR FMeter (bypass mode)*/
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,
+			  AIROHA_PCS_PMA_DISB_FBCK_LOCK);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+			AIROHA_PCS_PMA_FORCE_FBCK_LOCK);
+
+	/* Enable CMLEQ */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN,
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN |
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN |
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN |
+			   AIROHA_PCS_ANA_RX_FE_EQ_HZEN,
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN |
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN |
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN);
+
+	/* Setup CDR PR */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN,
+			   AIROHA_PCS_ANA_CDR_PR_CAP_EN |
+			   AIROHA_PCS_ANA_CDR_BUF_IN_SR,
+			   (cdr_pr_cap_en ? AIROHA_PCS_ANA_CDR_PR_CAP_EN : 0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_BUF_IN_SR, cdr_pr_buf_in_sr));
+
+	/* Setup CDR xxx Pwdb, set force and disable */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+			  AIROHA_PCS_PMA_XPON_CDR_PR_PD_PWDB |
+			  AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+			  AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+			  AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+	/* FIXME: Ask Airoha WHY it's cleared? */
+	/* regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
+	 *		  AIROHA_PCS_ANA_RX_FE_50OHMS_SEL);
+	 */
+
+	/* Setup SigDet */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
+			   AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL |
+			   AIROHA_PCS_ANA_RX_SIGDET_PEAK,
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL, sigdet_vth_sel) |
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_PEAK, BIT(1)));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_RANGE,
+			   AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL,
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL, BIT(1) | BIT(0)));
+
+	/* Disable SigDet Pwdb */
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+			  AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+
+	/* Setup PHYCK */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV,
+			   AIROHA_PCS_ANA_RX_TDC_CK_SEL |
+			   AIROHA_PCS_ANA_RX_PHYCK_RSTB |
+			   AIROHA_PCS_ANA_RX_PHYCK_SEL |
+			   AIROHA_PCS_ANA_RX_PHYCK_DIV,
+			   AIROHA_PCS_ANA_RX_PHYCK_RSTB |
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_SEL, phyck_sel) |
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_DIV, phyck_div));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL,
+			   AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE |
+			   AIROHA_PCS_ANA_RX_PHY_CK_SEL,
+			   AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE);
+
+	usleep_range(100, 200);
+
+	/* Enable CDR xxx Pwdb */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+			AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+			AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+			AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+			AIROHA_PCS_PMA_XPON_CDR_PR_PD_PWDB |
+			AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+			AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+			AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+	/* Enable SigDet Pwdb */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+			AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+}
+
+static unsigned int airoha_pcs_apply_cdr_pr_idac(struct airoha_pcs_priv *priv,
+						 u32 cdr_pr_idac)
+{
+	u32 val;
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+			   AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+				      cdr_pr_idac));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+			   AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+			   AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+			   AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+			   AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL);
+
+	usleep_range(5000, 7000);
+
+	regmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+
+	return FIELD_GET(AIROHA_PCS_PMA_FL_OUT, val);
+}
+
+static void airoha_pcs_rx_prcal(struct airoha_pcs_priv *priv,
+				phy_interface_t interface)
+{
+	unsigned int remaining_prcal_search_bits;
+	unsigned int fl_out_diff = UINT_MAX;
+	u32 best_prcal_search_bit;
+	unsigned int prcal_search;
+	int prcal_search_bit;
+	unsigned int fl_out;
+	int cdr_pr_idac = 0;
+
+	u32 target_fl_out;
+	u32 cyclecnt;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:  /* DS_1.25G      / US_1.25G  */
+	case PHY_INTERFACE_MODE_1000BASEX:
+		target_fl_out = 0xa3d6;
+		cyclecnt = 32767;
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX: /* DS_9.95328G   / US_9.95328G */
+		target_fl_out = 0xa000;
+		cyclecnt = 20000;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII: /* DS_10.3125G  / US_1.25G */
+	case PHY_INTERFACE_MODE_10GBASER:
+		target_fl_out = 0x9edf;
+		cyclecnt = 32767;
+		break;
+	default:
+		return;
+	}
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			AIROHA_PCS_PMA_SW_REF_RST_N);
+
+	usleep_range(100, 200);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_2,
+			   AIROHA_PCS_PMA_LOCK_TARGET_END |
+			   AIROHA_PCS_PMA_LOCK_TARGET_BEG,
+			   FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_END, target_fl_out + 100) |
+			   FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_BEG, target_fl_out - 100));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1,
+			   AIROHA_PCS_PMA_UNLOCK_CYCLECNT |
+			   AIROHA_PCS_PMA_LOCK_CYCLECNT,
+			   FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, cyclecnt) |
+			   FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, cyclecnt));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+			   AIROHA_PCS_PMA_LOCK_UNLOCKTH |
+			   AIROHA_PCS_PMA_LOCK_LOCKTH,
+			   FIELD_PREP(AIROHA_PCS_PMA_LOCK_UNLOCKTH, 3) |
+			   FIELD_PREP(AIROHA_PCS_PMA_LOCK_LOCKTH, 3));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_3,
+			   AIROHA_PCS_PMA_UNLOCK_TARGET_END |
+			   AIROHA_PCS_PMA_UNLOCK_TARGET_BEG,
+			   FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_END, target_fl_out + 100) |
+			   FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, target_fl_out - 100));
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE,
+			AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			  AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+	/* Calibration logic:
+	 * First check the major value by looping with every
+	 * value in the last 3 bit of CDR_PR_IDAC.
+	 * Get the signal level and save the value that is closer to
+	 * the target.
+	 *
+	 * Then check each remaining 7 bits in search of the deadline
+	 * where the signal gets farther than signal target.
+	 *
+	 * Finally fine tune for the remaining bits to find the one that
+	 * produce the closest signal level.
+	 */
+	for (prcal_search = 0; prcal_search < 8 ; prcal_search++) {
+		unsigned int fl_out_diff_new;
+		u32 cdr_pr_idac_tmp;
+
+		/* try to find the upper value by setting the last 3 bit */
+		cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+					     prcal_search);
+		fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);
+
+		/* Use absolute values to find the closest one to target */
+		fl_out_diff_new = abs(fl_out - target_fl_out);
+		if (fl_out_diff_new < fl_out_diff) {
+			cdr_pr_idac = cdr_pr_idac_tmp;
+			fl_out_diff = fl_out_diff_new;
+		}
+	}
+
+	/* Deadline search part.
+	 * We start from top bits to bottom as we progressively decrease the
+	 * signal.
+	 */
+	for (prcal_search_bit = 7; prcal_search_bit >= 0; prcal_search_bit--) {
+		unsigned int fl_out_diff_new;
+		u32 cdr_pr_idac_tmp;
+
+		cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
+		fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);
+
+		/* Use absolute values to find the closest one to target */
+		fl_out_diff_new = abs(fl_out - target_fl_out);
+		if (fl_out_diff_new < fl_out_diff) {
+			best_prcal_search_bit = prcal_search_bit;
+			fl_out_diff = fl_out_diff_new;
+		}
+	}
+
+	/* Set the idac with the best value we found and
+	 * reset the search bit to start from bottom to top.
+	 */
+	cdr_pr_idac |= BIT(best_prcal_search_bit);
+	remaining_prcal_search_bits = best_prcal_search_bit;
+	prcal_search_bit = 0;
+
+	/* Fine tune part.
+	 * Test remaining bits to find an even closer signal level to target
+	 * by increasing the signal.
+	 */
+	while (remaining_prcal_search_bits) {
+		unsigned int fl_out_diff_new;
+		u32 cdr_pr_idac_tmp;
+
+		cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
+		fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);
+
+		/* Use absolute values to find the closest one to target */
+		fl_out_diff_new = abs(fl_out - target_fl_out);
+		/* Assume we found the deadline when the new absolue signal difference
+		 * from target is greater than the previous and the difference is at
+		 * least 10% greater between the old and new value.
+		 * This is to account for signal detection level tollerance making
+		 * sure we are actually over a deadline (AKA we are getting farther
+		 * from target)
+		 */
+		if (fl_out_diff_new > fl_out_diff &&
+		    (abs(fl_out_diff_new - fl_out_diff) * 100) / fl_out_diff > 10) {
+			/* Exit early if we are already at the deadline */
+			if (prcal_search_bit == 0)
+				break;
+
+			/* We found the deadline, set the value to the previous
+			 * bit, and reset the loop to fine tune with the
+			 * remaining values.
+			 */
+			cdr_pr_idac |= BIT(prcal_search_bit - 1);
+			remaining_prcal_search_bits = prcal_search_bit - 1;
+			prcal_search_bit = 0;
+		} else {
+			/* Update the signal level diff and try the next bit */
+			fl_out_diff = fl_out_diff_new;
+
+			/* If we didn't found the deadline, set the last bit
+			 * and reset the loop to fine tune with the remainig
+			 * values.
+			 */
+			if (prcal_search_bit == remaining_prcal_search_bits - 1) {
+				cdr_pr_idac |= BIT(prcal_search_bit);
+				remaining_prcal_search_bits = prcal_search_bit;
+				prcal_search_bit = 0;
+			} else {
+				prcal_search_bit++;
+			}
+		}
+	}
+
+	fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac);
+	dev_dbg(priv->dev, "Selected CDR Pr Idac: %x Fl Out: %x\n", cdr_pr_idac, fl_out);
+	if (abs(fl_out - target_fl_out) > 100)
+		dev_dbg(priv->dev, "Fl Out is %d far from target %d on intermediate calibration.\n",
+			abs(fl_out - target_fl_out), target_fl_out);
+
+	/* Setup Load Band */
+	regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE,
+			  AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF);
+
+	/* Disable force of LPF C previously enabled */
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+			  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+			  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_B,
+			AIROHA_PCS_PMA_LOAD_EN);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_1,
+			   AIROHA_PCS_PMA_LPATH_IDAC,
+			   FIELD_PREP(AIROHA_PCS_PMA_LPATH_IDAC, cdr_pr_idac));
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			  AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			  AIROHA_PCS_PMA_SW_REF_RST_N);
+
+	usleep_range(100, 200);
+}
+
+/* This is used to both calibrate and lock to signal (after a previous
+ * calibration) after a global reset.
+ */
+static void airoha_pcs_cdr_reset(struct airoha_pcs_priv *priv,
+				 phy_interface_t interface, bool calibrate)
+{
+	/* Setup LPF L2D force and disable */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+
+	/* Calibrate IDAC and setup Load Band */
+	if (calibrate)
+		airoha_pcs_rx_prcal(priv, interface);
+
+	/* Setup LPF RSTB force and disable */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+	usleep_range(700, 1000);
+
+	/* Force Enable LPF RSTB */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);
+
+	usleep_range(100, 200);
+
+	/* Force Enable LPF L2D */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA);
+
+	/* Disable LPF RSTB force bit */
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+	/* Disable LPF L2D force bit */
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+}
+
+static int airoha_pcs_phya_bringup(struct airoha_pcs_priv *priv,
+				   phy_interface_t interface)
+{
+	int calibration_try = 0;
+	u32 val;
+
+	airoha_pcs_tx_bringup(priv, interface);
+	airoha_pcs_rx_bringup(priv, interface);
+
+	usleep_range(100, 200);
+
+retry_calibration:
+	airoha_pcs_cdr_reset(priv, interface, true);
+
+	/* Global reset clear */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			   AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+			   AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+			   AIROHA_PCS_PMA_SW_HSG_RXPCS_BIST_RST_N |
+			   AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+			   AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+			   AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+			   AIROHA_PCS_PMA_SW_REF_RST_N |
+			   AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+			   AIROHA_PCS_PMA_SW_PMA_RST_N |
+			   AIROHA_PCS_PMA_SW_TX_RST_N |
+			   AIROHA_PCS_PMA_SW_RX_RST_N |
+			   AIROHA_PCS_PMA_SW_RX_FIFO_RST_N,
+			   AIROHA_PCS_PMA_SW_REF_RST_N);
+
+	usleep_range(100, 200);
+
+	/* Global reset */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+			AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+			AIROHA_PCS_PMA_SW_HSG_RXPCS_BIST_RST_N |
+			AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+			AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+			AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+			AIROHA_PCS_PMA_SW_REF_RST_N |
+			AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+			AIROHA_PCS_PMA_SW_PMA_RST_N |
+			AIROHA_PCS_PMA_SW_TX_RST_N |
+			AIROHA_PCS_PMA_SW_RX_RST_N |
+			AIROHA_PCS_PMA_SW_RX_FIFO_RST_N);
+
+	usleep_range(5000, 7000);
+
+	airoha_pcs_cdr_reset(priv, interface, false);
+
+	/* It was discovered that after a global reset and auto mode gets
+	 * actually enabled, the fl_out from calibration might change and
+	 * might deviates a lot from the expected value it was calibrated for.
+	 * To correctly work, the PCS FreqDet module needs to Lock to the fl_out
+	 * (frequency level output) or no signal can correctly be transmitted.
+	 * This is detected by checking the FreqDet module Lock bit.
+	 *
+	 * If it's detected that the FreqDet module is not locked, retry
+	 * calibration. From observation on real hardware with a 10g SFP module,
+	 * it required a maximum of an additional calibration to actually make
+	 * the FreqDet module to lock. Try 10 times before failing to handle
+	 * really strange case.
+	 */
+	regmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+	if (!(val & AIROHA_PCS_PMA_FBCK_LOCK)) {
+		if (calibration_try > AIROHA_PCS_MAX_CALIBRATION_TRY) {
+			dev_err(priv->dev, "No FBCK Lock from FreqDet module after %d calibration try. PCS won't work.\n",
+				AIROHA_PCS_MAX_CALIBRATION_TRY);
+			return -EIO;
+		}
+
+		calibration_try++;
+
+		dev_dbg(priv->dev, "No FBCK Lock from FreqDet module, retry calibration.\n");
+		goto retry_calibration;
+	}
+
+	return 0;
+}
+
+static void airoha_pcs_get_state_sgmii(struct airoha_pcs_priv *priv,
+				       unsigned int neg_mode,
+				       struct phylink_link_state *state)
+{
+	u32 bmsr, lpa;
+
+	regmap_read(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,
+		    &bmsr);
+	regmap_read(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5,
+		    &lpa);
+
+	bmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |
+		AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |
+		AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |
+		AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr;
+	lpa = AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY & lpa;
+
+	phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa);
+}
+
+static void airoha_pcs_get_state_usxgmii(struct airoha_pcs_priv *priv,
+					 struct phylink_link_state *state)
+{
+	u32 lpa;
+
+	/* Toggle AN Status */
+	regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+			AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+			  AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+
+	regmap_read(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, &lpa);
+
+	state->link = !!(lpa & MDIO_USXGMII_LINK);
+	state->an_complete = state->link;
+
+	phylink_decode_usxgmii_word(state, lpa);
+}
+
+static void airoha_pcs_get_state(struct phylink_pcs *pcs,
+				 unsigned int neg_mode,
+				 struct phylink_link_state *state)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+	switch (state->interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		airoha_pcs_get_state_sgmii(priv, neg_mode, state);
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		airoha_pcs_get_state_usxgmii(priv, state);
+		break;
+	default:
+		return;
+	}
+}
+
+static void airoha_pcs_pre_config(struct phylink_pcs *pcs,
+				  phy_interface_t interface)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+	/* MPI MBI disable */
+	regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+			AIROHA_PCS_XFI_RXMPI_STOP |
+			AIROHA_PCS_XFI_RXMBI_STOP |
+			AIROHA_PCS_XFI_TXMPI_STOP |
+			AIROHA_PCS_XFI_TXMBI_STOP);
+
+	/* Write 1 to trigger reset and clear */
+	regmap_clear_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,
+			  AIROHA_PCS_XFI_MAC_LOGIC_RST);
+	regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,
+			AIROHA_PCS_XFI_MAC_LOGIC_RST);
+
+	usleep_range(1000, 2000);
+
+	/* Clear XFI MAC counter */
+	regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_CNT_CLR,
+			AIROHA_PCS_XFI_GLB_CNT_CLR);
+}
+
+static int airoha_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+			     phy_interface_t interface,
+			     const unsigned long *advertising,
+			     bool permit_pause_to_mac)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+	u32 rate_adapt;
+	int ret;
+
+	priv->interface = interface;
+
+	/* Select HSGMII or USXGMII in SCU regs */
+	airoha_pcs_setup_scu(priv, interface);
+
+	/* Enable Analog Common Lane */
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CMN_EN,
+			AIROHA_PCS_ANA_CMN_EN);
+
+	/* Setup PLL */
+	airoha_pcs_pll_bringup(priv, interface);
+
+	/* Setup PHYA */
+	ret = airoha_pcs_phya_bringup(priv, interface);
+	if (ret)
+		return ret;
+
+	/* Set final configuration for various modes */
+	airoha_pcs_init(priv, interface);
+
+	/* Configure Interrupt for various modes */
+	airoha_pcs_interrupt_init(priv, interface);
+
+	/* FIXME: With an attached Aeonsemi PHY, rate adaption is needed
+	 * even with no inband.
+	 */
+	rate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+		     AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN;
+
+	/* AN Auto Settings (Rate Adaptation) */
+	regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0,
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS |
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN, rate_adapt);
+
+	/* FIXME: With an attached Aeonsemi PHY, AN is needed
+	 * even with no inband.
+	 */
+	if (interface == PHY_INTERFACE_MODE_USXGMII ||
+	    interface == PHY_INTERFACE_MODE_10GBASER) {
+		regmap_set_bits(priv->usxgmii_pcs,
+				AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+				AIROHA_PCS_USXGMII_AN_ENABLE);
+	}
+
+	/* Clear any force bit that my be set by bootloader */
+	if (interface == PHY_INTERFACE_MODE_SGMII ||
+	    interface == PHY_INTERFACE_MODE_1000BASEX ||
+	    interface == PHY_INTERFACE_MODE_2500BASEX) {
+		regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+				  AIROHA_PCS_LINK_MODE_P0 |
+				  AIROHA_PCS_FORCE_SPD_MODE_P0 |
+				  AIROHA_PCS_FORCE_LINKDOWN_P0 |
+				  AIROHA_PCS_FORCE_LINKUP_P0);
+	}
+
+	/* Toggle Rate Adaption for SGMII/HSGMII mode */
+	if (interface == PHY_INTERFACE_MODE_SGMII ||
+	    interface == PHY_INTERFACE_MODE_1000BASEX ||
+	    interface == PHY_INTERFACE_MODE_2500BASEX) {
+		if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+			regmap_clear_bits(priv->hsgmii_rate_adp,
+					  AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+					  AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+		else
+			regmap_set_bits(priv->hsgmii_rate_adp,
+					AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+					AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+	}
+
+	/* Setup AN Link Timer */
+	if (interface == PHY_INTERFACE_MODE_SGMII ||
+	    interface == PHY_INTERFACE_MODE_1000BASEX ||
+	    interface == PHY_INTERFACE_MODE_2500BASEX) {
+		u32 an_timer;
+
+		an_timer = phylink_get_link_timer_ns(interface);
+
+		/* Value needs to be shifted by 4, seems value is internally * 16 */
+		regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11,
+				   AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+				   FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+					      an_timer >> 4));
+
+		regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_3,
+				   AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+				   FIELD_PREP(AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+					      an_timer >> 4));
+	}
+
+	/* Setup SGMII AN and advertisement in DEV_ABILITY */
+	if (interface == PHY_INTERFACE_MODE_SGMII &&
+	    neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+		int advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
+									 advertising);
+		if (advertise < 0)
+			return advertise;
+
+		regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+				AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+
+		regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4,
+				   AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+				   FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+					      advertise));
+	} else {
+		regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+				  AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+	}
+
+	if (interface == PHY_INTERFACE_MODE_SGMII ||
+	    interface == PHY_INTERFACE_MODE_1000BASEX) {
+		u32 if_mode = AIROHA_PCS_HSGMII_AN_SGMII_EN |
+			      AIROHA_PCS_HSGMII_AN_SIDEBAND_EN;
+
+		if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+			regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+					AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+
+			/* Clear force speed bits and MAC mode */
+			regmap_clear_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+					  AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+					  AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+					  AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+					  AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+					  AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL |
+					  AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+		} else {
+			if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN;
+
+			regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+					  AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+
+			/* AN off force rate adaption, speed is set later in Link Up */
+			regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+					   AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+					   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT,
+					   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+		}
+
+		regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+				   AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0, if_mode);
+
+		/* FIXME: Airoha apply a different configuration here */
+		/* They force rate adaption */
+		regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+				AIROHA_PCS_HSGMII_PCS_TX_ENABLE |
+				AIROHA_PCS_HSGMII_PCS_MODE2_EN);
+	}
+
+	if (interface == PHY_INTERFACE_MODE_1000BASEX &&
+	    neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+		regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+				AIROHA_PCS_SGMII_SEND_AN_ERR_EN);
+
+		regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37,
+				AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE);
+	}
+
+	/* Configure Flow Control on XFI */
+	regmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+			   AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN,
+			   permit_pause_to_mac ?
+				AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN :
+				0);
+
+	return 0;
+}
+
+static void airoha_pcs_an_restart(struct phylink_pcs *pcs)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+	switch (priv->interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+				AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+		udelay(3);
+		regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+				  AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+		regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+				AIROHA_PCS_USXGMII_AN_RESTART);
+		udelay(3);
+		regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+				  AIROHA_PCS_USXGMII_AN_RESTART);
+		break;
+	default:
+		return;
+	}
+}
+
+static void airoha_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+			       phy_interface_t interface, int speed, int duplex)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+		if (interface == PHY_INTERFACE_MODE_SGMII) {
+			regmap_update_bits(priv->hsgmii_rate_adp,
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+					   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0x0) |
+					   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x0));
+			udelay(1);
+			regmap_update_bits(priv->hsgmii_rate_adp,
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+					   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0xf) |
+					   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x5));
+		}
+	} else {
+		if (interface == PHY_INTERFACE_MODE_USXGMII ||
+		    interface == PHY_INTERFACE_MODE_10GBASER) {
+			u32 mode;
+			u32 rate_adapt;
+
+			switch (speed) {
+			case SPEED_10000:
+				rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000;
+				mode = AIROHA_PCS_USXGMII_MODE_10000;
+				break;
+			case SPEED_5000:
+				rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000;
+				mode = AIROHA_PCS_USXGMII_MODE_5000;
+				break;
+			case SPEED_2500:
+				rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500;
+				mode = AIROHA_PCS_USXGMII_MODE_2500;
+				break;
+			case SPEED_1000:
+				rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000;
+				mode = AIROHA_PCS_USXGMII_MODE_1000;
+				break;
+			case SPEED_100:
+				rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100;
+				mode = AIROHA_PCS_USXGMII_MODE_100;
+				break;
+			}
+
+			/* Trigger USXGMII change mode and force selected speed */
+			regmap_update_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+					   AIROHA_PCS_USXGMII_RATE_UPDATE_MODE |
+					   AIROHA_PCS_USXGMII_MODE,
+					   AIROHA_PCS_USXGMII_RATE_UPDATE_MODE | mode);
+
+			regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11,
+					   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+					   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE,
+					   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+					   rate_adapt);
+		}
+
+		if (interface == PHY_INTERFACE_MODE_SGMII ||
+		    interface == PHY_INTERFACE_MODE_1000BASEX) {
+			u32 force_speed;
+			u32 rate_adapt;
+
+			switch (speed) {
+			case SPEED_1000:
+				force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000;
+				rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000;
+				break;
+			case SPEED_100:
+				force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100;
+				rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100;
+				break;
+			case SPEED_10:
+				force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10;
+				rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10;
+				break;
+			}
+
+			regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+					   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+					   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+					   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+					   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL,
+					   force_speed | rate_adapt);
+		}
+
+		if (interface == PHY_INTERFACE_MODE_SGMII ||
+		    interface == PHY_INTERFACE_MODE_2500BASEX) {
+			u32 ck_gen_mode;
+			u32 speed_reg;
+			u32 if_mode;
+
+			switch (speed) {
+			case SPEED_2500:
+				speed_reg = AIROHA_PCS_LINK_MODE_P0_2_5G;
+				break;
+			case SPEED_1000:
+				speed_reg = AIROHA_PCS_LINK_MODE_P0_1G;
+				if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000;
+				ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000;
+				break;
+			case SPEED_100:
+				speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
+				if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100;
+				ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100;
+				break;
+			case SPEED_10:
+				speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
+				if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10;
+				ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10;
+				break;
+			}
+
+			if (interface == PHY_INTERFACE_MODE_SGMII) {
+				regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+						   AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE,
+						   if_mode);
+
+				regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE,
+						   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE |
+						   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL,
+						   ck_gen_mode |
+						   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL);
+			}
+
+			regmap_update_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+					   AIROHA_PCS_LINK_MODE_P0 |
+					   AIROHA_PCS_FORCE_SPD_MODE_P0,
+					   speed_reg |
+					   AIROHA_PCS_FORCE_SPD_MODE_P0);
+		}
+	}
+
+	/* Reset TXPCS on link up */
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			  AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+
+	usleep_range(100, 200);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+
+	/* BPI BMI enable */
+	regmap_clear_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+			  AIROHA_PCS_XFI_RXMPI_STOP |
+			  AIROHA_PCS_XFI_RXMBI_STOP |
+			  AIROHA_PCS_XFI_TXMPI_STOP |
+			  AIROHA_PCS_XFI_TXMBI_STOP);
+}
+
+static void airoha_pcs_link_down(struct phylink_pcs *pcs)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+	/* MPI MBI disable */
+	regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+			AIROHA_PCS_XFI_RXMPI_STOP |
+			AIROHA_PCS_XFI_RXMBI_STOP |
+			AIROHA_PCS_XFI_TXMPI_STOP |
+			AIROHA_PCS_XFI_TXMBI_STOP);
+}
+
+static const struct phylink_pcs_ops airoha_pcs_ops = {
+	.pcs_get_state = airoha_pcs_get_state,
+	.pcs_pre_config = airoha_pcs_pre_config,
+	.pcs_config = airoha_pcs_config,
+	.pcs_an_restart = airoha_pcs_an_restart,
+	.pcs_link_up = airoha_pcs_link_up,
+	.pcs_link_down = airoha_pcs_link_down,
+};
+
+static const struct regmap_config airoha_pcs_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+};
+
+static int airoha_pcs_probe(struct platform_device *pdev)
+{
+	struct regmap_config syscon_config = airoha_pcs_regmap_config;
+	struct device *dev = &pdev->dev;
+	struct airoha_pcs_priv *priv;
+	void __iomem *base;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	priv->data = of_device_get_match_data(dev);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "xfi_mac");
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	syscon_config.name = "xfi_mac";
+	priv->xfi_mac = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->xfi_mac))
+		return PTR_ERR(priv->xfi_mac);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_an");
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	syscon_config.name = "hsgmii_an";
+	priv->hsgmii_an = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->hsgmii_an))
+		return PTR_ERR(priv->hsgmii_an);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_pcs");
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	syscon_config.name = "hsgmii_pcs";
+	priv->hsgmii_pcs = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->hsgmii_pcs))
+		return PTR_ERR(priv->hsgmii_pcs);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_rate_adp");
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	syscon_config.name = "hsgmii_rate_adp";
+	priv->hsgmii_rate_adp = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->hsgmii_rate_adp))
+		return PTR_ERR(priv->hsgmii_rate_adp);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "multi_sgmii");
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	syscon_config.name = "multi_sgmii";
+	priv->multi_sgmii = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->multi_sgmii))
+		return PTR_ERR(priv->multi_sgmii);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "usxgmii");
+	if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
+		return PTR_ERR(base);
+
+	syscon_config.name = "usxgmii";
+	priv->usxgmii_pcs = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->usxgmii_pcs))
+		return PTR_ERR(priv->usxgmii_pcs);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "xfi_pma");
+	if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
+		return PTR_ERR(base);
+
+	syscon_config.name = "xfi_pma";
+	priv->xfi_pma = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->xfi_pma))
+		return PTR_ERR(priv->xfi_pma);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "xfi_ana");
+	if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
+		return PTR_ERR(base);
+
+	syscon_config.name = "xfi_ana";
+	priv->xfi_ana = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->xfi_ana))
+		return PTR_ERR(priv->xfi_ana);
+
+	/* SCU is used to toggle XFI or HSGMII in global SoC registers */
+	priv->scu = syscon_regmap_lookup_by_compatible("airoha,en7581-scu");
+	if (IS_ERR(priv->scu))
+		return PTR_ERR(priv->scu);
+
+	priv->rsts[0].id = "mac";
+	priv->rsts[1].id = "phy";
+	ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(priv->rsts),
+						    priv->rsts);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to get bulk reset lines\n");
+
+	platform_set_drvdata(pdev, priv);
+
+	priv->pcs.ops = &airoha_pcs_ops;
+	priv->pcs.poll = true;
+
+	__set_bit(PHY_INTERFACE_MODE_SGMII, priv->pcs.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_1000BASEX, priv->pcs.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_2500BASEX, priv->pcs.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_10GBASER, priv->pcs.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_USXGMII, priv->pcs.supported_interfaces);
+
+	return fwnode_pcs_add_provider(dev_fwnode(dev), fwnode_pcs_simple_get,
+				   &priv->pcs);
+}
+
+static void airoha_pcs_remove(struct platform_device *pdev)
+{
+	struct airoha_pcs_priv *priv = platform_get_drvdata(pdev);
+
+	fwnode_pcs_del_provider(dev_fwnode(&pdev->dev));
+
+	rtnl_lock();
+	phylink_release_pcs(&priv->pcs);
+	rtnl_unlock();
+}
+
+static const struct airoha_pcs_match_data an7581_pcs_eth = {
+	.port_type = AIROHA_PCS_ETH,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_pon = {
+	.port_type = AIROHA_PCS_PON,
+};
+
+static const struct of_device_id airoha_pcs_of_table[] = {
+	{ .compatible = "airoha,an7581-pcs-eth", .data = &an7581_pcs_eth },
+	{ .compatible = "airoha,an7581-pcs-pon", .data = &an7581_pcs_pon },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, airoha_pcs_of_table);
+
+static struct platform_driver airoha_pcs_driver = {
+	.driver = {
+		.name	 = "airoha-pcs",
+		.of_match_table = airoha_pcs_of_table,
+	},
+	.probe = airoha_pcs_probe,
+	.remove = airoha_pcs_remove,
+};
+module_platform_driver(airoha_pcs_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Airoha PCS driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth at gmail.com>");
-- 
2.48.1



From ansuelsmth at gmail.com  Sun May 11 13:12:37 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sun, 11 May 2025 22:12:37 +0200
Subject: [net-next PATCH v4 11/11] net: airoha: add phylink support for GDM2/3/4
In-Reply-To: <20250511201250.3789083-1-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
Message-ID: <20250511201250.3789083-12-ansuelsmth@gmail.com>

Add phylink support for GDM2/3/4 port that require configuration of the
PCS to make the external PHY or attached SFP cage work.

These needs to be defined in the GDM port node using the pcs-handle
property.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/ethernet/airoha/airoha_eth.c  | 155 +++++++++++++++++++++-
 drivers/net/ethernet/airoha/airoha_eth.h  |   3 +
 drivers/net/ethernet/airoha/airoha_regs.h |  12 ++
 3 files changed, 169 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 16c7896f931f..3be1ae077a76 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -7,6 +7,7 @@
 #include <linux/of_net.h>
 #include <linux/platform_device.h>
 #include <linux/tcp.h>
+#include <linux/pcs/pcs.h>
 #include <linux/u64_stats_sync.h>
 #include <net/dst_metadata.h>
 #include <net/page_pool/helpers.h>
@@ -79,6 +80,11 @@ static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
 	return port->id == 1;
 }
 
+static bool airhoa_is_phy_external(struct airoha_gdm_port *port)
+{
+	return port->id != 1;
+}
+
 static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
 {
 	struct airoha_eth *eth = port->qdma->eth;
@@ -1613,6 +1619,17 @@ static int airoha_dev_open(struct net_device *dev)
 	struct airoha_gdm_port *port = netdev_priv(dev);
 	struct airoha_qdma *qdma = port->qdma;
 
+	if (airhoa_is_phy_external(port)) {
+		err = phylink_of_phy_connect(port->phylink, dev->dev.of_node, 0);
+		if (err) {
+			netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
+				   err);
+			return err;
+		}
+
+		phylink_start(port->phylink);
+	}
+
 	netif_tx_start_all_queues(dev);
 	err = airoha_set_vip_for_gdm_port(port, true);
 	if (err)
@@ -1665,6 +1682,11 @@ static int airoha_dev_stop(struct net_device *dev)
 		}
 	}
 
+	if (airhoa_is_phy_external(port)) {
+		phylink_stop(port->phylink);
+		phylink_disconnect_phy(port->phylink);
+	}
+
 	return 0;
 }
 
@@ -2795,6 +2817,115 @@ bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
 	return false;
 }
 
+static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,
+			       unsigned int mode, phy_interface_t interface,
+			       int speed, int duplex, bool tx_pause, bool rx_pause)
+{
+	struct airoha_gdm_port *port = container_of(config, struct airoha_gdm_port,
+						    phylink_config);
+	struct airoha_qdma *qdma = port->qdma;
+	struct airoha_eth *eth = qdma->eth;
+	u32 frag_size_tx, frag_size_rx;
+
+	if (port->id != 4)
+		return;
+
+	switch (speed) {
+	case SPEED_10000:
+	case SPEED_5000:
+		frag_size_tx = 8;
+		frag_size_rx = 8;
+		break;
+	case SPEED_2500:
+		frag_size_tx = 2;
+		frag_size_rx = 1;
+		break;
+	default:
+		frag_size_tx = 1;
+		frag_size_rx = 0;
+	}
+
+	/* Configure TX/RX frag based on speed */
+	airoha_fe_rmw(eth, REG_GDMA4_TMBI_FRAG,
+		      GDMA4_SGMII0_TX_FRAG_SIZE_MASK,
+		      FIELD_PREP(GDMA4_SGMII0_TX_FRAG_SIZE_MASK,
+				 frag_size_tx));
+
+	airoha_fe_rmw(eth, REG_GDMA4_RMBI_FRAG,
+		      GDMA4_SGMII0_RX_FRAG_SIZE_MASK,
+		      FIELD_PREP(GDMA4_SGMII0_RX_FRAG_SIZE_MASK,
+				 frag_size_rx));
+}
+
+static const struct phylink_mac_ops airoha_phylink_ops = {
+	.mac_link_up = airoha_mac_link_up,
+};
+
+static int airoha_setup_phylink(struct net_device *dev)
+{
+	struct airoha_gdm_port *port = netdev_priv(dev);
+	struct device_node *np = dev->dev.of_node;
+	struct phylink_pcs **available_pcs;
+	phy_interface_t phy_mode;
+	struct phylink *phylink;
+	unsigned int num_pcs;
+	int err;
+
+	err = of_get_phy_mode(np, &phy_mode);
+	if (err) {
+		dev_err(&dev->dev, "incorrect phy-mode\n");
+		return err;
+	}
+
+	port->phylink_config.dev = &dev->dev;
+	port->phylink_config.type = PHYLINK_NETDEV;
+	port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+						MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD |
+						MAC_5000FD | MAC_10000FD;
+
+	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), NULL, &num_pcs);
+	if (err)
+		return err;
+
+	available_pcs = kcalloc(num_pcs, sizeof(*available_pcs), GFP_KERNEL);
+	if (!available_pcs)
+		return -ENOMEM;
+
+	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), available_pcs,
+				       &num_pcs);
+	if (err)
+		goto out;
+
+	port->phylink_config.available_pcs = available_pcs;
+	port->phylink_config.num_available_pcs = num_pcs;
+
+	__set_bit(PHY_INTERFACE_MODE_SGMII,
+		  port->phylink_config.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_1000BASEX,
+		  port->phylink_config.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_2500BASEX,
+		  port->phylink_config.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_USXGMII,
+		  port->phylink_config.supported_interfaces);
+
+	phy_interface_copy(port->phylink_config.pcs_interfaces,
+			   port->phylink_config.supported_interfaces);
+
+	phylink = phylink_create(&port->phylink_config,
+				 of_fwnode_handle(np),
+				 phy_mode, &airoha_phylink_ops);
+	if (IS_ERR(phylink)) {
+		err = PTR_ERR(phylink);
+		goto out;
+	}
+
+	port->phylink = phylink;
+out:
+	kfree(available_pcs);
+
+	return err;
+}
+
 static int airoha_alloc_gdm_port(struct airoha_eth *eth,
 				 struct device_node *np, int index)
 {
@@ -2873,7 +3004,23 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
 	if (err)
 		return err;
 
-	return register_netdev(dev);
+	if (airhoa_is_phy_external(port)) {
+		err = airoha_setup_phylink(dev);
+		if (err)
+			return err;
+	}
+
+	err = register_netdev(dev);
+	if (err)
+		goto free_phylink;
+
+	return 0;
+
+free_phylink:
+	if (airhoa_is_phy_external(port))
+		phylink_destroy(port->phylink);
+
+	return err;
 }
 
 static int airoha_probe(struct platform_device *pdev)
@@ -2967,6 +3114,9 @@ static int airoha_probe(struct platform_device *pdev)
 		struct airoha_gdm_port *port = eth->ports[i];
 
 		if (port && port->dev->reg_state == NETREG_REGISTERED) {
+			if (airhoa_is_phy_external(port))
+				phylink_destroy(port->phylink);
+
 			unregister_netdev(port->dev);
 			airoha_metadata_dst_free(port);
 		}
@@ -2994,6 +3144,9 @@ static void airoha_remove(struct platform_device *pdev)
 			continue;
 
 		airoha_dev_stop(port->dev);
+		if (airhoa_is_phy_external(port))
+			phylink_destroy(port->phylink);
+
 		unregister_netdev(port->dev);
 		airoha_metadata_dst_free(port);
 	}
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index 53f39083a8b0..73a500474076 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -498,6 +498,9 @@ struct airoha_gdm_port {
 	struct net_device *dev;
 	int id;
 
+	struct phylink *phylink;
+	struct phylink_config phylink_config;
+
 	struct airoha_hw_stats stats;
 
 	DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
index d931530fc96f..54f7079b28b0 100644
--- a/drivers/net/ethernet/airoha/airoha_regs.h
+++ b/drivers/net/ethernet/airoha/airoha_regs.h
@@ -357,6 +357,18 @@
 #define IP_FRAGMENT_PORT_MASK		GENMASK(8, 5)
 #define IP_FRAGMENT_NBQ_MASK		GENMASK(4, 0)
 
+#define REG_GDMA4_TMBI_FRAG		0x2028
+#define GDMA4_SGMII1_TX_WEIGHT_MASK	GENMASK(31, 26)
+#define GDMA4_SGMII1_TX_FRAG_SIZE_MASK	GENMASK(25, 16)
+#define GDMA4_SGMII0_TX_WEIGHT_MASK	GENMASK(15, 10)
+#define GDMA4_SGMII0_TX_FRAG_SIZE_MASK	GENMASK(9, 0)
+
+#define REG_GDMA4_RMBI_FRAG		0x202c
+#define GDMA4_SGMII1_RX_WEIGHT_MASK	GENMASK(31, 26)
+#define GDMA4_SGMII1_RX_FRAG_SIZE_MASK	GENMASK(25, 16)
+#define GDMA4_SGMII0_RX_WEIGHT_MASK	GENMASK(15, 10)
+#define GDMA4_SGMII0_RX_FRAG_SIZE_MASK	GENMASK(9, 0)
+
 #define REG_MC_VLAN_EN			0x2100
 #define MC_VLAN_EN_MASK			BIT(0)
 
-- 
2.48.1



From andrew at lunn.ch  Sun May 11 14:25:27 2025
From: andrew at lunn.ch (Andrew Lunn)
Date: Sun, 11 May 2025 23:25:27 +0200
Subject: [PATCH v1 09/14] arm64: dts: mediatek: mt7988: add switch
 node
In-Reply-To: <trinity-0edcdb4e-bcc9-47bb-b958-a018f5980128-1746984591926@trinity-msg-rest-gmx-gmx-live-74d694d854-ls6fz>
References: <20250511141942.10284-1-linux@fw-web.de>
 <20250511141942.10284-10-linux@fw-web.de>
 <bfa0c158-4205-4070-9b72-f6bde9cd9997@lunn.ch>
 <trinity-0edcdb4e-bcc9-47bb-b958-a018f5980128-1746984591926@trinity-msg-rest-gmx-gmx-live-74d694d854-ls6fz>
Message-ID: <74afe286-2adb-42d3-9491-881379053e36@lunn.ch>

> i will move that into the board dtsi file in v2 because "normal" bpi-r4 and 2g5 variant are same here.

Maybe you just need to expand the commit message? What does this .dtsi
actually represent? The SoC, or what is common across a number of
boards?

	Andrew


From daniel at makrotopia.org  Sun May 11 14:55:50 2025
From: daniel at makrotopia.org (Daniel Golle)
Date: Sun, 11 May 2025 22:55:50 +0100
Subject: [PATCH v1 09/14] arm64: dts: mediatek: mt7988: add switch
 node
In-Reply-To: <74afe286-2adb-42d3-9491-881379053e36@lunn.ch>
References: <20250511141942.10284-1-linux@fw-web.de>
 <20250511141942.10284-10-linux@fw-web.de>
 <bfa0c158-4205-4070-9b72-f6bde9cd9997@lunn.ch>
 <trinity-0edcdb4e-bcc9-47bb-b958-a018f5980128-1746984591926@trinity-msg-rest-gmx-gmx-live-74d694d854-ls6fz>
 <74afe286-2adb-42d3-9491-881379053e36@lunn.ch>
Message-ID: <aCEc5tYPivxvRVDK@makrotopia.org>

On Sun, May 11, 2025 at 11:25:27PM +0200, Andrew Lunn wrote:
> > i will move that into the board dtsi file in v2 because "normal" bpi-r4 and 2g5 variant are same here.
> 
> Maybe you just need to expand the commit message? What does this .dtsi
> actually represent? The SoC, or what is common across a number of
> boards?

mt7988a.dtsi represents the SoC, and thus there shouldn't be any
labels assigned to the DSA ports.

In case of the BananaPi R4 there are two different boards, one with 2x
SFP+ and one with 1x SFP+ + 1x 2500Base-T (with PoE-in), hence there is
a dtsi files for all the parts shared among the two boards. I suppose
Frank meant to move the labels to that board dtsi file, and that's
correct imho as the labels of the 1G switch ports are the same on BPi-R4
and BPi-R4-PoE.


From Mingyen.Hsieh at mediatek.com  Sun May 11 22:40:23 2025
From: Mingyen.Hsieh at mediatek.com (=?utf-8?B?TWluZ3llbiBIc2llaCAo6Kyd5piO6Ku6KQ==?=)
Date: Mon, 12 May 2025 05:40:23 +0000
Subject: [PATCH] wifi: mt76: disable napi on driver removal
In-Reply-To: <20250506115540.19045-1-pchelkin@ispras.ru>
References: <20250506115540.19045-1-pchelkin@ispras.ru>
Message-ID: <03c357a6054c31bfdca8ce5e87b74a0f0c1da3bd.camel@mediatek.com>

On Tue, 2025-05-06 at 14:55 +0300, Fedor Pchelkin wrote:
> A warning on driver removal started occurring after commit
> 9dd05df8403b
> ("net: warn if NAPI instance wasn't shut down"). Disable tx napi
> before
> deleting it in mt76_dma_cleanup().
> 
> ?WARNING: CPU: 4 PID: 18828 at net/core/dev.c:7288
> __netif_napi_del_locked+0xf0/0x100
> ?CPU: 4 UID: 0 PID: 18828 Comm: modprobe Not tainted 6.15.0-rc4 #4
> PREEMPT(lazy)
> ?Hardware name: ASUS System Product Name/PRIME X670E-PRO WIFI, BIOS
> 3035 09/05/2024
> ?RIP: 0010:__netif_napi_del_locked+0xf0/0x100
> ?Call Trace:
> ?<TASK>
> ?mt76_dma_cleanup+0x54/0x2f0 [mt76]
> ?mt7921_pci_remove+0xd5/0x190 [mt7921e]
> ?pci_device_remove+0x47/0xc0
> ?device_release_driver_internal+0x19e/0x200
> ?driver_detach+0x48/0x90
> ?bus_remove_driver+0x6d/0xf0
> ?pci_unregister_driver+0x2e/0xb0
> ?__do_sys_delete_module.isra.0+0x197/0x2e0
> ?do_syscall_64+0x7b/0x160
> ?entry_SYSCALL_64_after_hwframe+0x76/0x7e
> 
> Tested with mt7921e but the same pattern can be actually applied to
> other
> mt76 drivers calling mt76_dma_cleanup() during removal. Tx napi is
> enabled
> in their *_dma_init() functions and only toggled off and on again
> inside
> their suspend/resume/reset paths. So it should be okay to disable tx
> napi in such a generic way.
> 
> Found by Linux Verification Center (linuxtesting.org).
> 
> Fixes: 2ac515a5d74f ("mt76: mt76x02: use napi polling for tx
> cleanup")
> Cc: stable at vger.kernel.org
> Signed-off-by: Fedor Pchelkin <pchelkin at ispras.ru>
> ---
> ?drivers/net/wireless/mediatek/mt76/dma.c | 1 +
> ?1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/net/wireless/mediatek/mt76/dma.c
> b/drivers/net/wireless/mediatek/mt76/dma.c
> index 844af16ee551..35b4ec91979e 100644
> --- a/drivers/net/wireless/mediatek/mt76/dma.c
> +++ b/drivers/net/wireless/mediatek/mt76/dma.c
> @@ -1011,6 +1011,7 @@ void mt76_dma_cleanup(struct mt76_dev *dev)
> ?	int i;
> ?
> ?	mt76_worker_disable(&dev->tx_worker);
> +	napi_disable(&dev->tx_napi);
> ?	netif_napi_del(&dev->tx_napi);
> ?
> ?	for (i = 0; i < ARRAY_SIZE(dev->phys); i++) {

Tested-by: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>

From Crystal.Guo at mediatek.com  Mon May 12 00:36:53 2025
From: Crystal.Guo at mediatek.com (=?utf-8?B?Q3J5c3RhbCBHdW8gKOmDreaZtik=?=)
Date: Mon, 12 May 2025 07:36:53 +0000
Subject: [PATCH v4 2/2] memory/mediatek: Add an interface to get current
 DDR data rate
In-Reply-To: <5f4dfd0295c2ceb6fd774569e625cc6272d4bd76.camel@mediatek.com>
References: <20250403065030.22761-1-crystal.guo@mediatek.com>
	 <20250403065030.22761-3-crystal.guo@mediatek.com>
	 <20250404-soft-pumpkin-bettong-09abfc@shite>
	 <5f4dfd0295c2ceb6fd774569e625cc6272d4bd76.camel@mediatek.com>
Message-ID: <db549de43db09d2ab90f30d7489bb38e7c13bb1f.camel@mediatek.com>

On Wed, 2025-04-09 at 15:42 +0800, crystal guo wrote:
> > 

> On Fri, 2025-04-04 at 13:11 +0200, Krzysztof Kozlowski wrote:
> > External email : Please do not click links or open attachments
> > until
> > you have verified the sender or the content.
> > 
> > 
> > Please use subject prefixes matching the subsystem. You can get
> > them
> > for
> > example with 'git log --oneline -- DIRECTORY_OR_FILE' on the
> > directory
> > your patch is touching. For bindings, the preferred subjects are
> > explained here:
> > 
> 
> 
https://urldefense.com/v3/__https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html*i-for-patch-submitters__;Iw!!CTRNKA9wMg0ARbw!i9YnJLxKI_KuaW2pzwPR_GjZT8IzcZVycscosWKhQjWxvSouP0La_YLNk6lFRLpwDSUbgg8EGbZjbOjX$
> > 
> > memory: mediatek:
> 
> Thanks for the suggestion, I will use the correct subject prefixes in
> the next version:
> 'memory: mediatek: Add an interface to get current DDR data rate'
> 
> > 
> > On Thu, Apr 03, 2025 at 02:48:48PM GMT, Crystal Guo wrote:
> > > Add MediaTek DRAMC driver to provide an interface that can
> > > obtain current DDR data rate.
> > > 
> > > Signed-off-by: Crystal Guo <crystal.guo at mediatek.com>
> > > ---
> > >  drivers/memory/Kconfig              |   1 +
> > >  drivers/memory/Makefile             |   1 +
> > >  drivers/memory/mediatek/Kconfig     |  20 +++
> > >  drivers/memory/mediatek/Makefile    |   2 +
> > >  drivers/memory/mediatek/mtk-dramc.c | 223
> > > ++++++++++++++++++++++++++++
> > >  5 files changed, 247 insertions(+)
> > >  create mode 100644 drivers/memory/mediatek/Kconfig
> > >  create mode 100644 drivers/memory/mediatek/Makefile
> > >  create mode 100644 drivers/memory/mediatek/mtk-dramc.c
> > > 
> > > diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
> > > index c82d8d8a16ea..b1698549ff81 100644
> > > --- a/drivers/memory/Kconfig
> > > +++ b/drivers/memory/Kconfig
> > > @@ -227,5 +227,6 @@ config STM32_FMC2_EBI
> > > 
> > >  source "drivers/memory/samsung/Kconfig"
> > >  source "drivers/memory/tegra/Kconfig"
> > > +source "drivers/memory/mediatek/Kconfig"
> > 
> > m goes before s, so this goes before samsung source.
> > 
> 
> Okay, I will update it in the next version.
> 
> > > 
> > >  endif
> > > diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
> > > index d2e6ca9abbe0..c0facf529803 100644
> > > --- a/drivers/memory/Makefile
> > > +++ b/drivers/memory/Makefile
> > > @@ -27,6 +27,7 @@ obj-$(CONFIG_STM32_FMC2_EBI)        += stm32-
> > > fmc2-ebi.o
> > > 
> > >  obj-$(CONFIG_SAMSUNG_MC)     += samsung/
> > >  obj-$(CONFIG_TEGRA_MC)               += tegra/
> > > +obj-$(CONFIG_MEDIATEK_MC)    += mediatek/
> > >  obj-$(CONFIG_TI_EMIF_SRAM)   += ti-emif-sram.o
> > >  obj-$(CONFIG_FPGA_DFL_EMIF)  += dfl-emif.o
> > > 
> > > diff --git a/drivers/memory/mediatek/Kconfig
> > > b/drivers/memory/mediatek/Kconfig
> > > new file mode 100644
> > > index 000000000000..eadc11ec0f1c
> > > --- /dev/null
> > > +++ b/drivers/memory/mediatek/Kconfig
> > > @@ -0,0 +1,20 @@
> > > +# SPDX-License-Identifier: GPL-2.0-only
> > > +config MEDIATEK_MC
> > > +     bool "MediaTek Memory Controller support"
> > > +     default y
> > 
> > Why this has to be enabled for every compile test build? Look how
> > other
> > platforms do it.
> > 
> > I'll fix the tegra.
> > 
> 
> Okay, I will change 'default Y' to 'default ARCH_MEDIATEK' in the
> next
> version.
> 
> > 
> > > +     depends on ARCH_MEDIATEK || COMPILE_TEST
> > > +     help
> > > +       This option allows to enable MediaTek memory controller
> > > drivers,
> > > +       which may include controllers for DRAM or others.
> > > +
> > > +if MEDIATEK_MC
> > > +
> > > +config MTK_DRAMC
> > > +     tristate "MediaTek DRAMC driver"
> > > +     default y
> > 
> > This matters less, could stay or could be also ARCH_MDIATEK.
> > 
> 
> Understood, I will keep this part unchanged in the next version. 
> Thank you for your suggestion.
> 
> > > +     help
> > > +       This driver is for the DRAM Controller found in MediaTek
> > > SoCs
> > > +       and provides a sysfs interface for reporting the current
> > > DRAM
> > > +       data rate.
> > > +
> > > +endif
> > 
> > ...
> > 
> > > +
> > > +static unsigned int read_reg_field(void __iomem *base, unsigned
> > > int offset, unsigned int mask)
> > > +{
> > > +     unsigned int val = readl(base + offset);
> > > +     unsigned int shift = __ffs(mask);
> > > +
> > > +     return (val & mask) >> shift;
> > > +}
> > > +
> > > +static int mtk_dramc_probe(struct platform_device *pdev)
> > 
> > Weird ordering. probe() is one of the last functions. Only other
> > driver
> > struct functions (like remove, suspend/resume) go after, not some
> > regular code.
> 
> Understood. I will adjust the order of the probe function in the next
> version.
> 
> > 
> > > +{
> > > +     struct mtk_dramc *dramc;
> > > +     const struct mtk_dramc_pdata *pdata;
> > > +
> > > +     dramc = devm_kzalloc(&pdev->dev, sizeof(struct mtk_dramc),
> > > GFP_KERNEL);
> > > +     if (!dramc)
> > > +             return dev_err_probe(&pdev->dev, -ENOMEM, "Failed
> > > to
> > > allocate memory\n");
> > > +
> > > +     pdata = of_device_get_match_data(&pdev->dev);
> > > +     if (!pdata)
> > > +             return dev_err_probe(&pdev->dev, -EINVAL, "No
> > > platform data available\n");
> > 
> > Just return. That's impossible condition, so no need for printing
> > errors.
> 
> Okay, will return directly in the next version.
> 
> > 
> > > +
> > > +     dramc->pdata = pdata;
> > 
> > Why do you need pdata variable in the first place? Make this code
> > simple, not complicated.
> 
> Okay, will remove redundant 'pdata' in the next version.
> 
> > 
> > > +
> > > +     dramc->anaphy_base = devm_platform_ioremap_resource(pdev,
> > > 0);
> > > +     if (IS_ERR(dramc->anaphy_base))
> > > +             return dev_err_probe(&pdev->dev, PTR_ERR(dramc-
> > > > anaphy_base),
> > > 
> > > +                                  "Unable to map ANAPHY
> > > base\n");
> > > +
> > > +     dramc->ddrphy_base = devm_platform_ioremap_resource(pdev,
> > > 1);
> > > +     if (IS_ERR(dramc->ddrphy_base))
> > > +             return dev_err_probe(&pdev->dev, PTR_ERR(dramc-
> > > > ddrphy_base),
> > > 
> > > +                                  "Unable to map DDRPHY
> > > base\n");
> > > +
> > > +     platform_set_drvdata(pdev, dramc);
> > > +     return 0;
> > > +}
> > > +
> > > +static unsigned int mtk_fmeter_v1(struct mtk_dramc *dramc)
> > > +{
> > > +     const struct mtk_dramc_pdata *pdata = dramc->pdata;
> > > +     unsigned int shu_level, pll_sel, offset;
> > > +     unsigned int sdmpcw, posdiv, clkdiv, fbksel, sopen,
> > > async_ca,
> > > ser_mode;
> > > +     unsigned int prediv_freq, posdiv_freq, vco_freq;
> > > +     unsigned int final_rate;
> > > +
> > > +     shu_level = read_reg_field(dramc->ddrphy_base, pdata-
> > > > regs[DRAMC_DPHY_DVFS_STA],
> > > 
> > > +                                pdata-
> > > > masks[DRAMC_DPHY_DVFS_SHU_LV]);
> > 
> > Don't creat your own wrappers. Use existing FIELD_PREP stuff.
> 
> Since the mask is not a constant, using FIELD_GET will result in a
> compilation error. Can I keep using 'read_reg_field' in the next
> version?
> 
> > 
> > > +     pll_sel = read_reg_field(dramc->ddrphy_base, pdata-
> > > > regs[DRAMC_DPHY_DVFS_STA],
> > > 
> > > +                              pdata-
> > > > masks[DRAMC_DPHY_DVFS_PLL_SEL]);
> > > 
> > > +     offset = pdata->shuffle_offset * shu_level;
> > > +
> > > +     sdmpcw = read_reg_field(dramc->anaphy_base,
> > > +                             ((pll_sel == 0) ?
> > > +                             pdata->regs[DRAMC_APHY_SHU_PHYPLL2] 
> > > :
> > > +                             pdata-
> > > >regs[DRAMC_APHY_SHU_CLRPLL2])
> > > + offset,
> > > +                             pdata-
> > > > masks[DRAMC_APHY_PLL2_SDMPCW]);
> > > 
> > > +     posdiv = read_reg_field(dramc->anaphy_base,
> > > +                             ((pll_sel == 0) ?
> > > +                             pdata->regs[DRAMC_APHY_SHU_PHYPLL3] 
> > > :
> > > +                             pdata-
> > > >regs[DRAMC_APHY_SHU_CLRPLL3])
> > > + offset,
> > > +                             pdata-
> > > > masks[DRAMC_APHY_PLL3_POSDIV]);
> > > 
> > > +     fbksel = read_reg_field(dramc->anaphy_base, pdata-
> > > > regs[DRAMC_APHY_SHU_PHYPLL4] + offset,
> > > 
> > > +                             pdata-
> > > > masks[DRAMC_APHY_PLL4_FBKSEL]);
> > > 
> > > +     sopen = read_reg_field(dramc->anaphy_base, pdata-
> > > > regs[DRAMC_APHY_ARPI0] + offset,
> > > 
> > > +                            pdata-
> > > >masks[DRAMC_APHY_ARPI0_SOPEN]);
> > > +     async_ca = read_reg_field(dramc->anaphy_base, pdata-
> > > > regs[DRAMC_APHY_CA_ARDLL1] + offset,
> > > 
> > > +                               pdata-
> > > > masks[DRAMC_APHY_ARDLL1_CK_EN]);
> > > 
> > > +     ser_mode = read_reg_field(dramc->anaphy_base, pdata-
> > > > regs[DRAMC_APHY_B0_TX0] + offset,
> > > 
> > > +                               pdata-
> > > > masks[DRAMC_APHY_B0_TX0_SER_MODE]);
> > > 
> > > +
> > > +     clkdiv = (ser_mode == 1) ? 1 : 0;
> > > +     posdiv &= ~(pdata->posdiv_purify);
> > > +
> > > +     prediv_freq = pdata->ref_freq_mhz * (sdmpcw >> pdata-
> > > > prediv);
> > > 
> > > +     posdiv_freq = (prediv_freq >> posdiv) >> 1;
> > > +     vco_freq = posdiv_freq << fbksel;
> > > +     final_rate = vco_freq >> clkdiv;
> > > +
> > > +     if (sopen == 1 && async_ca == 1)
> > > +             final_rate >>= 1;
> > > +
> > > +     return final_rate;
> > > +}
> > > +
> > > +/**
> > > + * mtk_dramc_get_data_rate - Calculate the current DRAM data
> > > rate
> > > + * @dev: Device pointer
> > > + *
> > > + * Return: DRAM Data Rate in Mbps or negative number for error
> > > + */
> > > +static unsigned int mtk_dramc_get_data_rate(struct device *dev)
> > > +{
> > > +     struct mtk_dramc *dramc = dev_get_drvdata(dev);
> > > +
> > > +     if (dramc->pdata->fmeter_version == 1)
> > 
> > Drop, it's not possible to have other case.
> 
> Thank you for your suggestion.
> In the future, other SoCs might use different fmeter version to
> calculate the DDR data rate. If we remove the fmeter_version now,
> future SoCs that cannot share mtk_fmeter_v1 will still need to add
> the
> fmeter_version variable.
> Therefore, can I keep the current implementation for now.
> 
> > 
> > > +             return mtk_fmeter_v1(dramc);
> > > +
> > > +     dev_err(dev, "Frequency meter version %u not supported\n",
> > > dramc->pdata->fmeter_version);
> > > +     return -EINVAL;
> > > +}
> > > +
> > > +static ssize_t dram_data_rate_show(struct device *dev,
> > > +                                struct device_attribute *attr,
> > > char *buf)
> > 
> > No ABI doc.
> > 
> > Why existing interconnect interface is not suitable here?  This
> > should
> > be an interconnect, otherwise what is the point of this driver?
> > What
> > do
> > you exactly configure here?
> > 
> 
> This driver specifically focuses on displaying the current DDR data
> rate, which is used for the DVFS (Dynamic Voltage and Frequency
> Scaling) feature to verify that DDR frequency adjustments are
> correctly
> executed. 
> I will add the ABI documentation for the dram_data_rate attribute as
> follows, is this ok?
> 
> What:		/sys/devices/platform/soc/XXXXXXXX.memory-
> controller/dram_data_rate
> Date:		April 2025
> KernelVersion:	6.14
> Contact:	Crystal Guo <crystal.guo at mediatek.com>
> Description:
> 		Reports the current DRAM data rate in Mbps.
> 
> 		Access: Read
> 

Hi Krzysztof,

Sorry to bother you,  may I proceed with the next version based on the
content of my previous response regarding your suggestions?

Thanks
Crystal

> > > +{
> > > +     return snprintf(buf, PAGE_SIZE, "DRAM data rate = %u\n",
> > > +                     mtk_dramc_get_data_rate(dev));
> > > +}
> > > +
> > > +static DEVICE_ATTR_RO(dram_data_rate);
> > > +
> > > +static struct attribute *mtk_dramc_attrs[] = {
> > > +     &dev_attr_dram_data_rate.attr,
> > > +     NULL
> > > +};
> > > +ATTRIBUTE_GROUPS(mtk_dramc);
> > > +
> > > +static const struct mtk_dramc_pdata dramc_pdata_mt8196 = {
> > > +     .fmeter_version = 1,
> > > +     .ref_freq_mhz = 26,
> > > +     .regs = mtk_dramc_regs_mt8196,
> > > +     .masks = mtk_dramc_masks_mt8196,
> > > +     .posdiv_purify = BIT(2),
> > > +     .prediv = 7,
> > > +     .shuffle_offset = 0x700,
> > > +};
> > > +
> > > +static const struct of_device_id mtk_dramc_of_ids[] = {
> > > +     { .compatible = "mediatek,mt8196-dramc", .data =
> > > &dramc_pdata_mt8196 },
> > > +     { /* sentinel */ }
> > > +};
> > > +MODULE_DEVICE_TABLE(of, mtk_dramc_of_ids);
> > > +
> > > +static struct platform_driver mtk_dramc_driver = {
> > > +     .probe = mtk_dramc_probe,
> > > +     .driver = {
> > > +             .name = "mtk-dramc",
> > > +             .of_match_table = mtk_dramc_of_ids,
> > > +             .dev_groups = mtk_dramc_groups,
> > > +     },
> > > +};
> > > +module_platform_driver(mtk_dramc_driver);
> > > +
> > > +MODULE_AUTHOR("Crystal Guo <crystal.guo at mediatek.com>");
> > > +MODULE_DESCRIPTION("MediaTek DRAM Controller Driver");
> > > +MODULE_LICENSE("GPL");
> > > --
> > > 2.18.0
> > > 

From karol.bednaszewski at ventrixio.pl  Mon May 12 01:15:52 2025
From: karol.bednaszewski at ventrixio.pl (Karol Bednaszewski)
Date: Mon, 12 May 2025 08:15:52 GMT
Subject: =?UTF-8?Q?Mniejsze_wydatki_na_samoch=C3=B3d?=
Message-ID: <20250512064500-0.1.26.m37i.0.pjwjj9giv6@ventrixio.pl>

Dzie? dobry!

Czy m?g?bym przedstawi? rozwi?zanie, kt?re umo?liwia monitoring ka?dego auta w czasie rzeczywistym w tym jego pozycj?, zu?ycie paliwa i przebieg?

Dodatkowo nasze narz?dzie minimalizuje koszty utrzymania samochod?w, skraca czas przejazd?w, a tak?e umo?liwia tworzenie planu tras czy dostaw.

Z naszej wiedzy i do?wiadczenia korzysta ju? ponad 49 tys. Klient?w. Monitorujemy 809 000 pojazd?w na ca?ym ?wiecie, co jest nasz? najlepsz? wizyt?wk?.

Bardzo prosz? o e-maila zwrotnego, je?li mogliby?my wsp?lnie om?wi? potencja? wykorzystania takiego rozwi?zania w Pa?stwa firmie.


Pozdrawiam
Karol Bednaszewski


From lorenzo at kernel.org  Mon May 12 02:21:47 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Mon, 12 May 2025 11:21:47 +0200
Subject: [net-next PATCH v4 11/11] net: airoha: add phylink support for
 GDM2/3/4
In-Reply-To: <20250511201250.3789083-12-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-12-ansuelsmth@gmail.com>
Message-ID: <aCG9q6i7HomgilI6@lore-desk>

> Add phylink support for GDM2/3/4 port that require configuration of the
> PCS to make the external PHY or attached SFP cage work.
> 
> These needs to be defined in the GDM port node using the pcs-handle
> property.
> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---
>  drivers/net/ethernet/airoha/airoha_eth.c  | 155 +++++++++++++++++++++-
>  drivers/net/ethernet/airoha/airoha_eth.h  |   3 +
>  drivers/net/ethernet/airoha/airoha_regs.h |  12 ++
>  3 files changed, 169 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index 16c7896f931f..3be1ae077a76 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -7,6 +7,7 @@
>  #include <linux/of_net.h>
>  #include <linux/platform_device.h>
>  #include <linux/tcp.h>
> +#include <linux/pcs/pcs.h>
>  #include <linux/u64_stats_sync.h>
>  #include <net/dst_metadata.h>
>  #include <net/page_pool/helpers.h>
> @@ -79,6 +80,11 @@ static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
>  	return port->id == 1;
>  }
>  
> +static bool airhoa_is_phy_external(struct airoha_gdm_port *port)
> +{
> +	return port->id != 1;
> +}
> +
>  static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
>  {
>  	struct airoha_eth *eth = port->qdma->eth;
> @@ -1613,6 +1619,17 @@ static int airoha_dev_open(struct net_device *dev)
>  	struct airoha_gdm_port *port = netdev_priv(dev);
>  	struct airoha_qdma *qdma = port->qdma;
>  
> +	if (airhoa_is_phy_external(port)) {
> +		err = phylink_of_phy_connect(port->phylink, dev->dev.of_node, 0);

nit: even if it is not strictly required, in order to align with the rest of the
codebase, can you please stay below 79 columns?

> +		if (err) {
> +			netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
> +				   err);

same here

> +			return err;
> +		}
> +
> +		phylink_start(port->phylink);
> +	}
> +
>  	netif_tx_start_all_queues(dev);
>  	err = airoha_set_vip_for_gdm_port(port, true);
>  	if (err)
> @@ -1665,6 +1682,11 @@ static int airoha_dev_stop(struct net_device *dev)
>  		}
>  	}
>  
> +	if (airhoa_is_phy_external(port)) {
> +		phylink_stop(port->phylink);
> +		phylink_disconnect_phy(port->phylink);
> +	}
> +
>  	return 0;
>  }
>  
> @@ -2795,6 +2817,115 @@ bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
>  	return false;
>  }
>  
> +static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,
> +			       unsigned int mode, phy_interface_t interface,
> +			       int speed, int duplex, bool tx_pause, bool rx_pause)

ditto.

> +{
> +	struct airoha_gdm_port *port = container_of(config, struct airoha_gdm_port,
> +						    phylink_config);

ditto.

> +	struct airoha_qdma *qdma = port->qdma;
> +	struct airoha_eth *eth = qdma->eth;
> +	u32 frag_size_tx, frag_size_rx;
> +
> +	if (port->id != 4)
> +		return;
> +
> +	switch (speed) {
> +	case SPEED_10000:
> +	case SPEED_5000:
> +		frag_size_tx = 8;
> +		frag_size_rx = 8;
> +		break;
> +	case SPEED_2500:
> +		frag_size_tx = 2;
> +		frag_size_rx = 1;
> +		break;
> +	default:
> +		frag_size_tx = 1;
> +		frag_size_rx = 0;
> +	}
> +
> +	/* Configure TX/RX frag based on speed */
> +	airoha_fe_rmw(eth, REG_GDMA4_TMBI_FRAG,
> +		      GDMA4_SGMII0_TX_FRAG_SIZE_MASK,
> +		      FIELD_PREP(GDMA4_SGMII0_TX_FRAG_SIZE_MASK,
> +				 frag_size_tx));
> +
> +	airoha_fe_rmw(eth, REG_GDMA4_RMBI_FRAG,
> +		      GDMA4_SGMII0_RX_FRAG_SIZE_MASK,
> +		      FIELD_PREP(GDMA4_SGMII0_RX_FRAG_SIZE_MASK,
> +				 frag_size_rx));
> +}
> +
> +static const struct phylink_mac_ops airoha_phylink_ops = {
> +	.mac_link_up = airoha_mac_link_up,
> +};
> +
> +static int airoha_setup_phylink(struct net_device *dev)
> +{
> +	struct airoha_gdm_port *port = netdev_priv(dev);
> +	struct device_node *np = dev->dev.of_node;
> +	struct phylink_pcs **available_pcs;
> +	phy_interface_t phy_mode;
> +	struct phylink *phylink;
> +	unsigned int num_pcs;
> +	int err;
> +
> +	err = of_get_phy_mode(np, &phy_mode);
> +	if (err) {
> +		dev_err(&dev->dev, "incorrect phy-mode\n");
> +		return err;
> +	}
> +
> +	port->phylink_config.dev = &dev->dev;
> +	port->phylink_config.type = PHYLINK_NETDEV;
> +	port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
> +						MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD |
> +						MAC_5000FD | MAC_10000FD;

over 79 columns

> +
> +	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), NULL, &num_pcs);
> +	if (err)
> +		return err;
> +
> +	available_pcs = kcalloc(num_pcs, sizeof(*available_pcs), GFP_KERNEL);

I guess you can use devm_kcalloc() and get rid of kfree() here.

> +	if (!available_pcs)
> +		return -ENOMEM;
> +
> +	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), available_pcs,
> +				       &num_pcs);
> +	if (err)
> +		goto out;
> +
> +	port->phylink_config.available_pcs = available_pcs;
> +	port->phylink_config.num_available_pcs = num_pcs;
> +
> +	__set_bit(PHY_INTERFACE_MODE_SGMII,
> +		  port->phylink_config.supported_interfaces);
> +	__set_bit(PHY_INTERFACE_MODE_1000BASEX,
> +		  port->phylink_config.supported_interfaces);
> +	__set_bit(PHY_INTERFACE_MODE_2500BASEX,
> +		  port->phylink_config.supported_interfaces);
> +	__set_bit(PHY_INTERFACE_MODE_USXGMII,
> +		  port->phylink_config.supported_interfaces);
> +
> +	phy_interface_copy(port->phylink_config.pcs_interfaces,
> +			   port->phylink_config.supported_interfaces);
> +
> +	phylink = phylink_create(&port->phylink_config,
> +				 of_fwnode_handle(np),
> +				 phy_mode, &airoha_phylink_ops);
> +	if (IS_ERR(phylink)) {
> +		err = PTR_ERR(phylink);
> +		goto out;
> +	}
> +
> +	port->phylink = phylink;
> +out:
> +	kfree(available_pcs);
> +
> +	return err;
> +}
> +
>  static int airoha_alloc_gdm_port(struct airoha_eth *eth,
>  				 struct device_node *np, int index)
>  {
> @@ -2873,7 +3004,23 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
>  	if (err)
>  		return err;
>  
> -	return register_netdev(dev);
> +	if (airhoa_is_phy_external(port)) {
> +		err = airoha_setup_phylink(dev);

This will re-introduce the issue reported here:
https://lore.kernel.org/netdev/5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet at wanadoo.fr/

> +		if (err)
> +			return err;
> +	}
> +
> +	err = register_netdev(dev);
> +	if (err)
> +		goto free_phylink;
> +
> +	return 0;
> +
> +free_phylink:
> +	if (airhoa_is_phy_external(port))
> +		phylink_destroy(port->phylink);
> +
> +	return err;
>  }
>  
>  static int airoha_probe(struct platform_device *pdev)
> @@ -2967,6 +3114,9 @@ static int airoha_probe(struct platform_device *pdev)
>  		struct airoha_gdm_port *port = eth->ports[i];
>  
>  		if (port && port->dev->reg_state == NETREG_REGISTERED) {
> +			if (airhoa_is_phy_external(port))
> +				phylink_destroy(port->phylink);
> +
>  			unregister_netdev(port->dev);
>  			airoha_metadata_dst_free(port);
>  		}
> @@ -2994,6 +3144,9 @@ static void airoha_remove(struct platform_device *pdev)
>  			continue;
>  
>  		airoha_dev_stop(port->dev);
> +		if (airhoa_is_phy_external(port))
> +			phylink_destroy(port->phylink);
> +
>  		unregister_netdev(port->dev);
>  		airoha_metadata_dst_free(port);
>  	}
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
> index 53f39083a8b0..73a500474076 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.h
> +++ b/drivers/net/ethernet/airoha/airoha_eth.h
> @@ -498,6 +498,9 @@ struct airoha_gdm_port {
>  	struct net_device *dev;
>  	int id;
>  
> +	struct phylink *phylink;
> +	struct phylink_config phylink_config;
> +
>  	struct airoha_hw_stats stats;
>  
>  	DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
> diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
> index d931530fc96f..54f7079b28b0 100644
> --- a/drivers/net/ethernet/airoha/airoha_regs.h
> +++ b/drivers/net/ethernet/airoha/airoha_regs.h
> @@ -357,6 +357,18 @@
>  #define IP_FRAGMENT_PORT_MASK		GENMASK(8, 5)
>  #define IP_FRAGMENT_NBQ_MASK		GENMASK(4, 0)
>  
> +#define REG_GDMA4_TMBI_FRAG		0x2028
> +#define GDMA4_SGMII1_TX_WEIGHT_MASK	GENMASK(31, 26)
> +#define GDMA4_SGMII1_TX_FRAG_SIZE_MASK	GENMASK(25, 16)
> +#define GDMA4_SGMII0_TX_WEIGHT_MASK	GENMASK(15, 10)
> +#define GDMA4_SGMII0_TX_FRAG_SIZE_MASK	GENMASK(9, 0)
> +
> +#define REG_GDMA4_RMBI_FRAG		0x202c
> +#define GDMA4_SGMII1_RX_WEIGHT_MASK	GENMASK(31, 26)
> +#define GDMA4_SGMII1_RX_FRAG_SIZE_MASK	GENMASK(25, 16)
> +#define GDMA4_SGMII0_RX_WEIGHT_MASK	GENMASK(15, 10)
> +#define GDMA4_SGMII0_RX_FRAG_SIZE_MASK	GENMASK(9, 0)
> +
>  #define REG_MC_VLAN_EN			0x2100
>  #define MC_VLAN_EN_MASK			BIT(0)
>  
> -- 
> 2.48.1
> 
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From jason-jh.lin at mediatek.com  Mon May 12 02:19:22 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:22 +0800
Subject: [PATCH RESEND v5 00/20] Add GCE support for MT8196
Message-ID: <20250512092252.905629-1-jason-jh.lin@mediatek.com>

This patch series adds support for the MediaTek MT8196 SoC in the CMDQ
driver and related subsystems. The changes include adding compatible
names and iommus property, updating driver data to accommodate hardware
changes, and modifying the usage of CMDQ APIs to support non-subsys ID
hardware.

---
Change in RESEND v5:
1. Separate the removal of cmdq_get_shift_pa() from [PATCH v5 03/19] to a
   single patch [PATCH RESEND v5 10/20].

Change in v5:
1. Rebase on tag: next-20250424 + patch [1].
2. Split adding driver data for MT8196 patch to 3 independent patch
   and add more detail commit message to each patch.
3. Refine passing shift_pa as the parameter in API to storing it into
   the cmdq_pkt.
4. Refine DMA address potential issue in cmdq mailbox driver.
5. Change the mminfra_offset related mbox API to passing it by cmdq_pkt.
6. Add new cmdq_pkt_write_pa() and cmdq_pkt_write_subsys() APIs to
   replace the cmdq_pkt_write().

[1] mailbox: mtk-cmdq: Refine GCE_GCTL_VALUE setting
- https://patchwork.kernel.org/project/linux-mediatek/patch/20250421035650.441383-1-jason-jh.lin at mediatek.com/

Change in v4:
1. Remove dt-binding header and add a gce header in dts folder.
2. Remove dot in sign-off name.
3. Change addr type from u32 to dma_addr_t for cmdq_reg_shift_addr() and
   cmdq_reg_revert_addr().

Change in v3:
1. Merge 2 dt-bindings pathes together and add more detail commit message.
2. Change type u32 to phys_addr_t for pa_base of struct cmdq_client_reg.
3. Remove cmdq_subsys_is_valid() and subsys_num in CMDQ driver.
4. Add CMDQ_SUBSYS_INVALID to check subsys instead of using
   cmdq_subsys_is_invalid().
5. Make use of CMDQ_THR_SPR0 define to the parameter of CMDQ APIs.
6. Rebase on the new MACRO in mtk-mdp3-comp.h.

Change in v2:
1. Remove the constant and fix warning in dt-bindings.
2. Remove the pa_base parameter of CMDQ APIs and related modification.
3. Move subsys checking to client drivers and use 2 alternative
   CMDQ APIs to achieve the same functionality.
---

Jason-JH Lin (20):
  arm64: dts: mediatek: Add GCE header for MT8196
  mailbox: mtk-cmdq: Refine DMA address handling for the command buffer
  mailbox: mtk-cmdq: Add cmdq private data to cmdq_pkt for generating
    instruction
  soc: mediatek: mtk-cmdq: Add cmdq_get_mbox_priv() in cmdq_pkt_create()
  soc: mediatek: mtk-cmdq: Add cmdq_pkt_jump_rel_temp() for removing
    shift_pa
  media: platform: mtk-mdp3: Change cmdq_pkt_jump_rel() to
    cmdq_pkt_jump_rel_temp()
  soc: mediatek: mtk-cmdq: Remove shift_pa parameter from
    cmdq_pkt_jump()
  media: platform: mtk-mdp3: Use cmdq_pkt_jump_rel() without shift_pa
  soc: mediatek: mtk-cmdq: Remove cmdq_pkt_jump() and
    cmdq_pkt_jump_rel_temp()
  mailbox: mtk-cmdq: Remove unsued cmdq_get_shift_pa()
  mailbox: mtk-cmdq: Add GCE hardware virtualization configuration
  mailbox: mtk-cmdq: Add mminfra_offset configuration for DRAM
    transaction
  mailbox: mtk-cmdq: Add driver data to support for MT8196
  soc: mediatek: mtk-cmdq: Add pa_base parsing for hardware without
    subsys ID support
  soc: mediatek: mtk-cmdq: Add new APIs to replace cmdq_pkt_write() and
    cmdq_pkt_write_mask()
  soc: mediatek: mtk-cmdq: Add mminfra_offset adjustment for DRAM
    addresses
  soc: mediatek: Add programming flow for unsupported subsys ID hardware
  drm/mediatek: Add programming flow for unsupported subsys ID hardware
  media: mediatek: mdp3: Add programming flow for unsupported subsys ID
    hardware
  soc: mediatek: mtk-cmdq: Remove cmdq_pkt_write() and
    cmdq_pkt_write_mask()

 arch/arm64/boot/dts/mediatek/mt8196-gce.h     | 612 ++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c       |  24 +-
 drivers/mailbox/mtk-cmdq-mailbox.c            | 115 +++-
 .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c    |  16 +-
 .../platform/mediatek/mdp3/mtk-mdp3-comp.h    |  70 +-
 .../platform/mediatek/mdp3/mtk-mdp3-core.c    |   2 -
 .../platform/mediatek/mdp3/mtk-mdp3-core.h    |   1 -
 drivers/soc/mediatek/mtk-cmdq-helper.c        |  68 +-
 drivers/soc/mediatek/mtk-mmsys.c              |  12 +-
 drivers/soc/mediatek/mtk-mutex.c              |   8 +-
 include/linux/mailbox/mtk-cmdq-mailbox.h      |  19 +-
 include/linux/soc/mediatek/mtk-cmdq.h         |  83 ++-
 12 files changed, 941 insertions(+), 89 deletions(-)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8196-gce.h

-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:29 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:29 +0800
Subject: [PATCH RESEND v5 07/20] soc: mediatek: mtk-cmdq: Remove shift_pa parameter from cmdq_pkt_jump()
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-8-jason-jh.lin@mediatek.com>

Since shift_pa will be stored in the cmdq_mbox_priv structure within
cmdq_pkt, all shift_pa parameters in CMDQ helper APIs can be removed.

Remove the shift_pa parameters from cmdq_pkt_jump(), cmdq_pkt_jump_abs(),
and cmdq_pkt_jump_rel().

Fixes: ade176534112 ("soc: mediatek: cmdq: Add parameter shift_pa to cmdq_pkt_jump()")
Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/soc/mediatek/mtk-cmdq-helper.c |  8 ++++----
 include/linux/soc/mediatek/mtk-cmdq.h  | 20 ++++++++------------
 2 files changed, 12 insertions(+), 16 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index 8feeaa320359..a40919555d4d 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -494,22 +494,22 @@ int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value)
 }
 EXPORT_SYMBOL(cmdq_pkt_assign);
 
-int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa)
+int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr)
 {
 	struct cmdq_instruction inst = {
 		.op = CMDQ_CODE_JUMP,
 		.offset = CMDQ_JUMP_ABSOLUTE,
-		.value = addr >> shift_pa
+		.value = addr >> pkt->priv.shift_pa
 	};
 	return cmdq_pkt_append_command(pkt, inst);
 }
 EXPORT_SYMBOL(cmdq_pkt_jump_abs);
 
-int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa)
+int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset)
 {
 	struct cmdq_instruction inst = {
 		.op = CMDQ_CODE_JUMP,
-		.value = (u32)offset >> shift_pa
+		.value = (u32)offset >> pkt->priv.shift_pa
 	};
 	return cmdq_pkt_append_command(pkt, inst);
 }
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 67fd0924747b..ee4ec64a7322 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -350,17 +350,15 @@ int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u32 mas
  *			 contains more instruction.
  * @pkt:        the CMDQ packet
  * @addr:       absolute physical address of target instruction buffer
- * @shift_pa:	shift bits of physical address in CMDQ instruction. This value
- *		is got by cmdq_get_shift_pa().
  *
  * Return: 0 for success; else the error code is returned
  */
-int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa);
+int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr);
 
 /* This wrapper has to be removed after all users migrated to jump_abs */
-static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa)
+static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr)
 {
-	return cmdq_pkt_jump_abs(pkt, addr, shift_pa);
+	return cmdq_pkt_jump_abs(pkt, addr);
 }
 
 /**
@@ -370,17 +368,15 @@ static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_
  *			 target address should contains more instruction.
  * @pkt:	the CMDQ packet
  * @offset:	relative offset of target instruction buffer from current PC.
- * @shift_pa:	shift bits of physical address in CMDQ instruction. This value
- *		is got by cmdq_get_shift_pa().
  *
  * Return: 0 for success; else the error code is returned
  */
-int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa);
+int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset);
 
 /* This wrapper has to be removed after all users migrated to jump_rel */
 static int cmdq_pkt_jump_rel_temp(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa)
 {
-	return cmdq_pkt_jump_rel(pkt, addr, shift_pa);
+	return cmdq_pkt_jump_rel(pkt, addr);
 }
 
 /**
@@ -497,17 +493,17 @@ static inline int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32
 	return -EINVAL;
 }
 
-static inline int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa)
+static inline int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr)
 {
 	return -EINVAL;
 }
 
-static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa)
+static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr)
 {
 	return -EINVAL;
 }
 
-static inline int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa)
+static inline int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset)
 {
 	return -EINVAL;
 }
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:33 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:33 +0800
Subject: [PATCH RESEND v5 11/20] mailbox: mtk-cmdq: Add GCE hardware virtualization configuration
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-12-jason-jh.lin@mediatek.com>

The GCE hardware virtualization configuration supports the isolation of
GCE hardware resources across different OS environments. Each OS is
treated as a virtual machine (VM) for GCE purposes.
There are 6 VMs and 1 host VM. The host VM has main control over the
GCE virtualization settings for all VMs.

To properly access the GCE thread registers, it is necessary to
configure access permissions for specific GCE threads assigned to
different VMs.
Currently, since only the host VM is being used, it is required to
enable access permissions for all GCE threads for the host VM.

There are 2 VM configurations:
1. VM_ID_MAP
There are 4 registers to allocate 32 GCE threads across different VMs:
VM_ID_MAP0 for threads 0-9, VM_ID_MAP1 for threads 10-19,
VM_ID_MAP2 for threads 20-29, and VM_ID_MAP3 for threads 30-31.
Each thread has a 3-bit configuration, where setting all bits to 1
configures the thread for the host VM.

2. VM_CPR_GSIZE
It is used to allocate the CPR SRAM size to each VM. Each VM has 4-bit
configuration, where setting bit 0-3 to configures the size of host VM.
This setting must be configured before the VM configuration to prevent
resource leakage.

Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 52 ++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index b18808855680..c946766c215a 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -43,6 +43,13 @@
 #define GCE_CTRL_BY_SW				GENMASK(2, 0)
 #define GCE_DDR_EN				GENMASK(18, 16)
 
+#define GCE_VM_ID_MAP(n)		(0x5018 + (n) / 10 * 4)
+#define GCE_VM_ID_MAP_THR_FLD_SHIFT(n)		((n) % 10 * 3)
+#define GCE_VM_ID_MAP_HOST_VM			GENMASK(2, 0)
+#define GCE_VM_CPR_GSIZE		0x50c4
+#define GCE_VM_CPR_GSIZE_FLD_SHIFT(vm_id)	((vm_id) * 4)
+#define GCE_VM_CPR_GSIZE_MAX			GENMASK(3, 0)
+
 #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
 #define CMDQ_THR_ENABLED		0x1
 #define CMDQ_THR_DISABLED		0x0
@@ -89,6 +96,7 @@ struct gce_plat {
 	u8 shift;
 	bool control_by_sw;
 	bool sw_ddr_en;
+	bool gce_vm;
 	u32 gce_num;
 };
 
@@ -110,6 +118,47 @@ void cmdq_get_mbox_priv(struct mbox_chan *chan, struct cmdq_mbox_priv *priv)
 }
 EXPORT_SYMBOL(cmdq_get_mbox_priv);
 
+static void cmdq_vm_toggle(struct cmdq *cmdq, bool enable)
+{
+	int i;
+	u32 vm_cpr_gsize = 0, vm_id_map = 0;
+	u32 *vm_map = NULL;
+
+	if (!cmdq->pdata->gce_vm)
+		return;
+
+	vm_map = kcalloc(cmdq->pdata->thread_nr, sizeof(*vm_map), GFP_KERNEL);
+	if (!vm_map)
+		return;
+
+	if (enable) {
+		/* only configure the max CPR SRAM size to host vm (vm_id = 0) currently */
+		vm_cpr_gsize = GCE_VM_CPR_GSIZE_MAX << GCE_VM_CPR_GSIZE_FLD_SHIFT(0);
+
+		/* set all thread mapping to host vm currently */
+		for (i = 0; i < cmdq->pdata->thread_nr; i++)
+			vm_map[i] = GCE_VM_ID_MAP_HOST_VM << GCE_VM_ID_MAP_THR_FLD_SHIFT(i);
+	}
+
+	/* set the amount of CPR SRAM to allocate to each VM */
+	writel(vm_cpr_gsize, cmdq->base + GCE_VM_CPR_GSIZE);
+
+	/* config CPR_GSIZE before setting VM_ID_MAP to avoid data leakage */
+	for (i = 0; i < cmdq->pdata->thread_nr; i++) {
+		vm_id_map |= vm_map[i];
+		/* config every 10 threads, e.g., thread id=0~9, 10~19, ..., into one register */
+		if ((i + 1) % 10 == 0) {
+			writel(vm_id_map, cmdq->base + GCE_VM_ID_MAP(i));
+			vm_id_map = 0;
+		}
+	}
+	/* config remaining threads settings */
+	if (cmdq->pdata->thread_nr % 10 != 0)
+		writel(vm_id_map, cmdq->base + GCE_VM_ID_MAP(cmdq->pdata->thread_nr - 1));
+
+	kfree(vm_map);
+}
+
 static void cmdq_gctl_value_toggle(struct cmdq *cmdq, bool ddr_enable)
 {
 	u32 val = cmdq->pdata->control_by_sw ? GCE_CTRL_BY_SW : 0;
@@ -154,6 +203,7 @@ static void cmdq_init(struct cmdq *cmdq)
 
 	WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks));
 
+	cmdq_vm_toggle(cmdq, true);
 	cmdq_gctl_value_toggle(cmdq, true);
 
 	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
@@ -327,6 +377,7 @@ static int cmdq_runtime_resume(struct device *dev)
 	if (ret)
 		return ret;
 
+	cmdq_vm_toggle(cmdq, true);
 	cmdq_gctl_value_toggle(cmdq, true);
 	return 0;
 }
@@ -336,6 +387,7 @@ static int cmdq_runtime_suspend(struct device *dev)
 	struct cmdq *cmdq = dev_get_drvdata(dev);
 
 	cmdq_gctl_value_toggle(cmdq, false);
+	cmdq_vm_toggle(cmdq, false);
 	clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
 	return 0;
 }
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:27 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:27 +0800
Subject: [PATCH RESEND v5 05/20] soc: mediatek: mtk-cmdq: Add cmdq_pkt_jump_rel_temp() for removing shift_pa
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-6-jason-jh.lin@mediatek.com>

Since shift_pa will be stored into the cmdq_mobx_priv of cmdq_pkt, all
the shif_pa parameters in CMDQ helper APIs can be removed.

Add cmdq_pkt_jump_rel_temp() for the current users of cmdq_jump_rel(),
and then remove shift_pa after all users have migrated to the new APIs.

Fixes: ade176534112 ("soc: mediatek: cmdq: Add parameter shift_pa to cmdq_pkt_jump()")
Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 include/linux/soc/mediatek/mtk-cmdq.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 0c3906e8ad19..67fd0924747b 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -377,6 +377,12 @@ static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_
  */
 int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa);
 
+/* This wrapper has to be removed after all users migrated to jump_rel */
+static int cmdq_pkt_jump_rel_temp(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa)
+{
+	return cmdq_pkt_jump_rel(pkt, addr, shift_pa);
+}
+
 /**
  * cmdq_pkt_eoc() - Append EOC and ask GCE to generate an IRQ at end of execution
  * @pkt:	The CMDQ packet
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:36 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:36 +0800
Subject: [PATCH RESEND v5 14/20] soc: mediatek: mtk-cmdq: Add pa_base parsing for hardware without subsys ID support
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-15-jason-jh.lin@mediatek.com>

When GCE executes instructions, it typically locates the corresponding
hardware register using the subsys ID. For hardware that does not
support subsys ID, the subsys ID is set to an invalid value, and the
physical address must be used to generate GCE instructions.

The main advantage of using subsys ID is to reduce the number of
instructions. Without subsys ID, an additional `ASSIGN` instruction
is needed to assign the high bytes of the physical address, which can
impact performance if too many instructions are required. However, if
the hardware does not support subsys ID, using the physical address
is the only option to achieve the same functionality.

This commit adds a pa_base parsing flow to the cmdq_client_reg structure
to handle hardware without subsys ID support.

Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/soc/mediatek/mtk-cmdq-helper.c | 15 +++++++++++++--
 include/linux/soc/mediatek/mtk-cmdq.h  |  3 +++
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index a40919555d4d..bae6753bd4a7 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -8,6 +8,7 @@
 #include <linux/module.h>
 #include <linux/mailbox_controller.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/soc/mediatek/mtk-cmdq.h>
 
 #define CMDQ_WRITE_ENABLE_MASK	BIT(0)
@@ -60,20 +61,30 @@ int cmdq_dev_get_client_reg(struct device *dev,
 			    struct cmdq_client_reg *client_reg, int idx)
 {
 	struct of_phandle_args spec;
+	struct resource res;
 	int err;
 
 	if (!client_reg)
 		return -ENOENT;
 
+	if (of_address_to_resource(dev->of_node, 0, &res) != 0) {
+		dev_err(dev, "Missing reg in %s node\n", dev->of_node->full_name);
+		return -EINVAL;
+	}
+	client_reg->pa_base = res.start;
+
 	err = of_parse_phandle_with_fixed_args(dev->of_node,
 					       "mediatek,gce-client-reg",
 					       3, idx, &spec);
 	if (err < 0) {
-		dev_warn(dev,
+		dev_dbg(dev,
 			"error %d can't parse gce-client-reg property (%d)",
 			err, idx);
 
-		return err;
+		/* make subsys invalid */
+		client_reg->subsys = CMDQ_SUBSYS_INVALID;
+
+		return 0;
 	}
 
 	client_reg->subsys = (u8)spec.args[0];
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index f956ee9a0b34..f9a48262cb95 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -23,6 +23,8 @@
 #define CMDQ_THR_SPR_IDX2	(2)
 #define CMDQ_THR_SPR_IDX3	(3)
 
+#define CMDQ_SUBSYS_INVALID	(U8_MAX)
+
 struct cmdq_pkt;
 
 enum cmdq_logic_op {
@@ -52,6 +54,7 @@ struct cmdq_operand {
 
 struct cmdq_client_reg {
 	u8 subsys;
+	phys_addr_t pa_base;
 	u16 offset;
 	u16 size;
 };
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:30 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:30 +0800
Subject: [PATCH RESEND v5 08/20] media: platform: mtk-mdp3: Use cmdq_pkt_jump_rel() without shift_pa
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-9-jason-jh.lin@mediatek.com>

With the removal of the shift_pa parameter, cmdq_pkt_jump_rel_temp()
can be replaced by the new cmdq_pkt_jump_rel() without shift_pa.

Then, remove the cmdq_shift_pa variable in the mdp_dev structure for
each mbox client.

Fixes: ade176534112 ("soc: mediatek: cmdq: Add parameter shift_pa to cmdq_pkt_jump()")
Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 2 +-
 drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c | 2 --
 drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h | 1 -
 3 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
index aa245bf7e7c4..c4e0d376a055 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
@@ -628,7 +628,7 @@ static struct mdp_cmdq_cmd *mdp_cmdq_prepare(struct mdp_dev *mdp,
 		goto err_free_path;
 	}
 	cmdq_pkt_eoc(&cmd->pkt);
-	cmdq_pkt_jump_rel_temp(&cmd->pkt, CMDQ_INST_SIZE, mdp->cmdq_shift_pa[pp_idx]);
+	cmdq_pkt_jump_rel(&cmd->pkt, CMDQ_INST_SIZE);
 
 	for (i = 0; i < num_comp; i++) {
 		s32 inner_id = MDP_COMP_NONE;
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c
index f571f561f070..5e94ff0d0756 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c
@@ -312,8 +312,6 @@ static int mdp_probe(struct platform_device *pdev)
 			ret = PTR_ERR(mdp->cmdq_clt[i]);
 			goto err_mbox_destroy;
 		}
-
-		mdp->cmdq_shift_pa[i] = cmdq_get_shift_pa(mdp->cmdq_clt[i]->chan);
 	}
 
 	init_waitqueue_head(&mdp->callback_wq);
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
index 05cade1d098e..430251f63754 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
@@ -126,7 +126,6 @@ struct mdp_dev {
 	u32					id_count;
 	struct ida				mdp_ida;
 	struct cmdq_client			*cmdq_clt[MDP_PP_MAX];
-	u8					cmdq_shift_pa[MDP_PP_MAX];
 	wait_queue_head_t			callback_wq;
 
 	struct v4l2_device			v4l2_dev;
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:35 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:35 +0800
Subject: [PATCH RESEND v5 13/20] mailbox: mtk-cmdq: Add driver data to support for MT8196
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-14-jason-jh.lin@mediatek.com>

MT8196 has 2 new hardware configuration compared with the previous SoC,
which correspond to the 2 new driver data:

1. mminfra_offset: For GCE data path control
   Since GCE has been moved into mminfra, GCE needs to append the
   mminfra offset to the DRAM address when accessing the DRAM.

2. gce_vm: For GCE hardware virtualization control
   Currently, the first version of the mt8196 mailbox controller only
   requires setting the VM-related registers to enable the permissions
   of a host VM.

Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 45de11e51088..e543b26dbba9 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -14,6 +14,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/sizes.h>
 #include <linux/mailbox_controller.h>
 #include <linux/mailbox/mtk-cmdq-mailbox.h>
 #include <linux/of.h>
@@ -844,6 +845,16 @@ static const struct gce_plat gce_plat_mt8195 = {
 	.gce_num = 2
 };
 
+static const struct gce_plat gce_plat_mt8196 = {
+	.thread_nr = 32,
+	.shift = 3,
+	.mminfra_offset = SZ_2G,
+	.control_by_sw = true,
+	.sw_ddr_en = true,
+	.gce_vm = true,
+	.gce_num = 2
+};
+
 static const struct of_device_id cmdq_of_ids[] = {
 	{.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_mt6779},
 	{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_mt8173},
@@ -852,6 +863,7 @@ static const struct of_device_id cmdq_of_ids[] = {
 	{.compatible = "mediatek,mt8188-gce", .data = (void *)&gce_plat_mt8188},
 	{.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_mt8192},
 	{.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_mt8195},
+	{.compatible = "mediatek,mt8196-gce", .data = (void *)&gce_plat_mt8196},
 	{}
 };
 MODULE_DEVICE_TABLE(of, cmdq_of_ids);
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:40 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:40 +0800
Subject: [PATCH RESEND v5 18/20] drm/mediatek: Add programming flow for unsupported subsys ID hardware
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-19-jason-jh.lin@mediatek.com>

To support hardware without subsys IDs on new SoCs, add a programming
flow that checks whether the subsys ID is valid.

If the subsys ID is valid, the flow will call cmdq_pkt_write_subsys()
instead of the original cmdq_pkt_write().

If the subsys ID is invalid, the flow will call cmdq_pkt_write_mask_pa()
to achieve the same functionality.

Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index edc6417639e6..726539f83918 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -66,14 +66,28 @@ struct mtk_ddp_comp_dev {
 	struct cmdq_client_reg cmdq_reg;
 };
 
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+static int mtk_ddp_write_cmdq_pkt(struct cmdq_pkt *cmdq_pkt, struct cmdq_client_reg *cmdq_reg,
+				  unsigned int offset, unsigned int value, unsigned int mask)
+{
+	offset += cmdq_reg->offset;
+
+	if (cmdq_reg->subsys != CMDQ_SUBSYS_INVALID)
+		return cmdq_pkt_write_mask_subsys(cmdq_pkt, cmdq_reg->subsys, cmdq_reg->pa_base,
+						  offset, value, mask);
+	else /* only MMIO access, no need to check mminfro_offset */
+		return cmdq_pkt_write_mask_pa(cmdq_pkt, cmdq_reg->subsys, cmdq_reg->pa_base,
+					      offset, value, mask);
+}
+#endif
+
 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
 		   struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
 		   unsigned int offset)
 {
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	if (cmdq_pkt)
-		cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
-			       cmdq_reg->offset + offset, value);
+		mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0));
 	else
 #endif
 		writel(value, regs + offset);
@@ -85,8 +99,7 @@ void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
 {
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	if (cmdq_pkt)
-		cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
-			       cmdq_reg->offset + offset, value);
+		mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0));
 	else
 #endif
 		writel_relaxed(value, regs + offset);
@@ -98,8 +111,7 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
 {
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	if (cmdq_pkt) {
-		cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
-				    cmdq_reg->offset + offset, value, mask);
+		mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, mask);
 	} else {
 #endif
 		u32 tmp = readl(regs + offset);
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:34 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:34 +0800
Subject: [PATCH RESEND v5 12/20] mailbox: mtk-cmdq: Add mminfra_offset configuration for DRAM transaction
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-13-jason-jh.lin@mediatek.com>

The GCE in MT8196 is placed in MMINFRA and requires all addresses
in GCE instructions for DRAM transactions to be IOVA.

Due to MMIO, if the GCE needs to access a hardware register at
0x1000_0000, but the SMMU is also mapping a DRAM block at 0x1000_0000,
the MMINFRA will not know whether to write to the hardware register or
the DRAM.
To solve this, MMINFRA treats addresses greater than 2G as data paths
and those less than 2G as config paths because the DRAM start address
is currently at 2G (0x8000_0000). On the data path, MMINFRA remaps
DRAM addresses by subtracting 2G, allowing SMMU to map DRAM addresses
less than 2G.
For example, if the DRAM start address 0x8000_0000 is mapped to
IOVA=0x0, when GCE accesses IOVA=0x0, it must add a 2G offset to
the address in the GCE instruction. MMINFRA will then see it as a
data path (IOVA >= 2G) and subtract 2G, allowing GCE to access IOVA=0x0.

Since the MMINFRA remap subtracting 2G is done in hardware and cannot
be configured by software, the address of DRAM in GCE instruction must
always add 2G to ensure proper access.
This 2G adjustment is referred to as mminfra_offset in the CMDQ driver.
CMDQ helper can get the mminfra_offset from the cmdq_mbox_priv of
cmdq_pkt and add the mminfra_offset to the DRAM address in GCE
instructions.

Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c       | 6 ++++--
 include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index c946766c215a..45de11e51088 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -94,6 +94,7 @@ struct cmdq {
 struct gce_plat {
 	u32 thread_nr;
 	u8 shift;
+	dma_addr_t mminfra_offset;
 	bool control_by_sw;
 	bool sw_ddr_en;
 	bool gce_vm;
@@ -102,12 +103,12 @@ struct gce_plat {
 
 static inline u32 cmdq_reg_shift_addr(dma_addr_t addr, const struct gce_plat *pdata)
 {
-	return (addr >> pdata->shift);
+	return ((addr + pdata->mminfra_offset) >> pdata->shift);
 }
 
 static inline dma_addr_t cmdq_reg_revert_addr(u32 addr, const struct gce_plat *pdata)
 {
-	return ((dma_addr_t)addr << pdata->shift);
+	return (((dma_addr_t)addr << pdata->shift) - pdata->mminfra_offset);
 }
 
 void cmdq_get_mbox_priv(struct mbox_chan *chan, struct cmdq_mbox_priv *priv)
@@ -115,6 +116,7 @@ void cmdq_get_mbox_priv(struct mbox_chan *chan, struct cmdq_mbox_priv *priv)
 	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
 
 	priv->shift_pa = cmdq->pdata->shift;
+	priv->mminfra_offset = cmdq->pdata->mminfra_offset;
 }
 EXPORT_SYMBOL(cmdq_get_mbox_priv);
 
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index 822958f92135..a42b44d5fd49 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -72,6 +72,7 @@ struct cmdq_cb_data {
 
 struct cmdq_mbox_priv {
 	u8 shift_pa;
+	dma_addr_t mminfra_offset;
 };
 
 struct cmdq_pkt {
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:25 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:25 +0800
Subject: [PATCH RESEND v5 03/20] mailbox: mtk-cmdq: Add cmdq private data to cmdq_pkt for generating instruction
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-4-jason-jh.lin@mediatek.com>

Add the cmdq_mbox_priv structure to store the private data of GCE,
such as the shift bits of the physical address. Then, include the
cmdq_mbox_priv structure within the cmdq_pkt structure.

This allows CMDQ users to utilize the private data in cmdq_pkt to
generate GCE instructions when needed. Additionally, having
cmdq_mbox_priv makes it easier to expand and reference other GCE
private data in the future.

Add cmdq_get_mbox_priv() for CMDQ users to get all the private data
into the cmdq_mbox_priv of the cmdq_pkt.

Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform")
Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c       |  8 ++++++++
 include/linux/mailbox/mtk-cmdq-mailbox.h | 18 ++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index a3d94f1eb1a3..db72dcd9b8b6 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -102,6 +102,14 @@ static inline dma_addr_t cmdq_reg_revert_addr(u32 addr, const struct gce_plat *p
 	return ((dma_addr_t)addr << pdata->shift);
 }
 
+void cmdq_get_mbox_priv(struct mbox_chan *chan, struct cmdq_mbox_priv *priv)
+{
+	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
+
+	priv->shift_pa = cmdq->pdata->shift;
+}
+EXPORT_SYMBOL(cmdq_get_mbox_priv);
+
 u8 cmdq_get_shift_pa(struct mbox_chan *chan)
 {
 	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index e1555e06e7e5..73b70be4a8a7 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -70,13 +70,31 @@ struct cmdq_cb_data {
 	struct cmdq_pkt		*pkt;
 };
 
+struct cmdq_mbox_priv {
+	u8 shift_pa;
+};
+
 struct cmdq_pkt {
 	void			*va_base;
 	dma_addr_t		pa_base;
 	size_t			cmd_buf_size; /* command occupied size */
 	size_t			buf_size; /* real buffer size */
+	struct cmdq_mbox_priv	priv; /* for generating instruction */
 };
 
+/**
+ * cmdq_get_mbox_priv() - get the private data of mailbox channel
+ * @chan: mailbox channel
+ * @priv: pointer to store the private data of mailbox channel
+ *
+ * While generating the GCE instruction to command buffer, the private data
+ * of GCE hardware may need to be referenced, such as the shift bits of
+ * physical address.
+ *
+ * This function should be called before generating the GCE instruction.
+ */
+void cmdq_get_mbox_priv(struct mbox_chan *chan, struct cmdq_mbox_priv *priv);
+
 /**
  * cmdq_get_shift_pa() - get the shift bits of physical address
  * @chan: mailbox channel
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:23 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:23 +0800
Subject: [PATCH RESEND v5 01/20] arm64: dts: mediatek: Add GCE header for MT8196
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-2-jason-jh.lin@mediatek.com>

Add GCE header define for GCE Thread Priority and GCE Event IDs
that used in the MT8196 dtsi.

Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8196-gce.h | 612 ++++++++++++++++++++++
 1 file changed, 612 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8196-gce.h

diff --git a/arch/arm64/boot/dts/mediatek/mt8196-gce.h b/arch/arm64/boot/dts/mediatek/mt8196-gce.h
new file mode 100644
index 000000000000..457dc73aeed3
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8196-gce.h
@@ -0,0 +1,612 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ *
+ */
+
+#ifndef __DTS_GCE_MT8196_H
+#define __DTS_GCE_MT8196_H
+
+/* GCE Thread Priority
+ * The GCE core has multiple GCE threads, each of which can independently
+ * execute its own sequence of instructions.
+ * However, the GCE threads on the same core cannot run in parallel.
+ * Different GCE threads can determine thread priority based on the scenario,
+ * thereby serving different user needs.
+ *
+ * Low priority thread is executed when no high priority thread is active.
+ * Same priority thread is scheduled by round robin.
+ */
+#define CMDQ_THR_PRIO_LOWEST	0
+#define CMDQ_THR_PRIO_1		1
+#define CMDQ_THR_PRIO_2		2
+#define CMDQ_THR_PRIO_3		3
+#define CMDQ_THR_PRIO_4		4
+#define CMDQ_THR_PRIO_5		5
+#define CMDQ_THR_PRIO_6		6
+#define CMDQ_THR_PRIO_HIGHEST	7
+
+/*
+ * GCE0 Hardware Event IDs
+ * Different SoCs will have varying numbers of hardware event signals,
+ * which are sent from the corresponding hardware to the GCE.
+ * Each hardware event signal corresponds to an event ID in the GCE.
+ * The CMDQ driver can use the following event ID definitions to allow
+ * the client driver to use wait and clear APIs provided by CMDQ, enabling
+ * the GCE to execute operations in the instructions for that event ID.
+ *
+ * The event IDs of GCE0 are mainly used by display hardware.
+ */
+/* CMDQ_EVENT_DISP0_STREAM_SOF0 ~ 15: 0 ~ 15 */
+#define CMDQ_EVENT_DISP0_STREAM_SOF(n)						(0 + (n))
+/* CMDQ_EVENT_DISP0_FRAME_DONE_SEL0 ~ 15: 16 ~ 31 */
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL(n)					(16 + (n))
+#define CMDQ_EVENT_DISP0_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT			32
+#define CMDQ_EVENT_DISP0_DISP_WDMA0_SW_RST_DONE_ENG_EVENT			33
+#define CMDQ_EVENT_DISP0_DISP_POSTMASK1_RST_DONE_ENG_EVENT			34
+#define CMDQ_EVENT_DISP0_DISP_POSTMASK0_RST_DONE_ENG_EVENT			35
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_TIMEOUT_ENG_EVENT				36
+/* CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT0 ~ 15: 37 ~ 52 */
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT(n)			(37 + (n))
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_GET_RELEASE_ENG_EVENT			53
+#define CMDQ_EVENT_DISP0_DISP_MDP_RDMA0_SW_RST_DONE_ENG_EVENT			54
+/* CMDQ_EVENT_DISP1_STREAM_SOF0 ~ 15: 55 ~ 70 */
+#define CMDQ_EVENT_DISP1_STREAM_SOF(n)						(55 + (n))
+/* CMDQ_EVENT_DISP1_FRAME_DONE_SEL0 ~ 15: 71 ~ 86 */
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL(n)					(71 + (n))
+/* CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT0 ~ 15: 87 ~ 102 */
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT(n)				(87 + (n))
+/* CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 103 ~ 118 */
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT(n)				(103 + (n))
+#define CMDQ_EVENT_DISP1_OCIP_SUBSYS_SRAM_ISOINT_ENG_EVENT			119
+#define CMDQ_EVENT_DISP1_DISP_WDMA4_TARGET_LINE_END_ENG_EVENT			120
+#define CMDQ_EVENT_DISP1_DISP_WDMA4_SW_RST_DONE_ENG_EVENT			121
+#define CMDQ_EVENT_DISP1_DISP_WDMA3_TARGET_LINE_END_ENG_EVENT			122
+#define CMDQ_EVENT_DISP1_DISP_WDMA3_SW_RST_DONE_ENG_EVENT			123
+#define CMDQ_EVENT_DISP1_DISP_WDMA2_TARGET_LINE_END_ENG_EVENT			124
+#define CMDQ_EVENT_DISP1_DISP_WDMA2_SW_RST_DONE_ENG_EVENT			125
+#define CMDQ_EVENT_DISP1_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT			126
+#define CMDQ_EVENT_DISP1_DISP_WDMA1_SW_RST_DONE_ENG_EVENT			127
+#define CMDQ_EVENT_DISP1_DISP_MUTEX0_TIMEOUT_ENG_EVENT				128
+#define CMDQ_EVENT_DISP1_DISP_MUTEX0_GET_RLZ_ENG_EVENT				129
+#define CMDQ_EVENT_DISP1_DISP_MDP_RDMA1_SW_RST_DONE_ENG_EVENT			130
+#define CMDQ_EVENT_DISP1_DISP_GDMA0_SW_RST_DONE_ENG_EVENT			131
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VSYNC_START_ENG_EVENT		132
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VSYNC_END_ENG_EVENT		133
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VRR_VFP_LAST_SAFE_BLANK_ENG_EVENT	134
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VFP_START_ENG_EVENT		135
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VFP_LAST_LINE_ENG_EVENT		136
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VDE_END_ENG_EVENT			137
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TRIGGER_LOOP_CLR_ENG_EVENT	138
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TARGET_LINE1_ENG_EVENT		139
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TARGET_LINE0_ENG_EVENT		140
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VSYNC_START_ENG_EVENT		141
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VSYNC_END_ENG_EVENT		142
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VDE_START_ENG_EVENT		143
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VDE_END_ENG_EVENT			144
+/* CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT0 ~ 10: 145 ~ 155 */
+#define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT(n)					(145 + (n))
+/* CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT0 ~ 21: 156 ~ 177 */
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT(n)					(156 + (n))
+/* CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT0 ~ 10: 178 ~ 188 */
+#define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT(n)					(178 + (n))
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VSYNC_START_ENG_EVENT			189
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VSYNC_END_ENG_EVENT			190
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VDE_START_ENG_EVENT			191
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VDE_END_ENG_EVENT			192
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_TARGET_LINE_ENG_EVENT			193
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VSYNC_START_ENG_EVENT			194
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VSYNC_END_ENG_EVENT			195
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VDE_START_ENG_EVENT			196
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VDE_END_ENG_EVENT			197
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_TARGET_LINE_ENG_EVENT			198
+/* CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT0 ~ 10: 199 ~ 209 */
+#define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT(n)				(199 + (n))
+/* CMDQ_EVENT_MML0_STREAM_SOF0 ~ 15: 210 ~ 225 */
+#define CMDQ_EVENT_MML0_STREAM_SOF(n)						(210 + (n))
+/* CMDQ_EVENT_MML0_FRAME_DONE_SEL0 ~ 15: 226 ~ 241 */
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL(n)					(226 + (n))
+/* CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 242 ~ 257 */
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT(n)				(242 + (n))
+#define CMDQ_EVENT_MML0_MDP_WROT2_SW_RST_DONE_ENG_EVENT				258
+#define CMDQ_EVENT_MML0_MDP_WROT1_SW_RST_DONE_ENG_EVENT				259
+#define CMDQ_EVENT_MML0_MDP_WROT0_SW_RST_DONE_ENG_EVENT				260
+#define CMDQ_EVENT_MML0_MDP_RROT0_SW_RST_DONE_ENG_EVENT				261
+#define CMDQ_EVENT_MML0_MDP_RDMA2_SW_RST_DONE_ENG_EVENT				262
+#define CMDQ_EVENT_MML0_MDP_RDMA1_SW_RST_DONE_ENG_EVENT				263
+#define CMDQ_EVENT_MML0_MDP_RDMA0_SW_RST_DONE_ENG_EVENT				264
+#define CMDQ_EVENT_MML0_MDP_MERGE0_SW_RST_DONE_ENG_EVENT			265
+#define CMDQ_EVENT_MML0_DISP_MUTEX0_TIMEOUT_ENG_EVENT				266
+#define CMDQ_EVENT_MML0_DISP_MUTEX0_GET_RLZ_ENG_EVENT				267
+/* CMDQ_EVENT_MML1_STREAM_SOF0 ~ 15: 268 ~ 283 */
+#define CMDQ_EVENT_MML1_STREAM_SOF(n)						(268 + (n))
+/* CMDQ_EVENT_MML1_FRAME_DONE_SEL0 ~ 15: 284 ~ 299 */
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL(n)					(284 + (n))
+/* CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 300 ~ 315 */
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT0				(300 + (n))
+#define CMDQ_EVENT_MML1_MDP_WROT2_SW_RST_DONE_ENG_EVENT				316
+#define CMDQ_EVENT_MML1_MDP_WROT1_SW_RST_DONE_ENG_EVENT				317
+#define CMDQ_EVENT_MML1_MDP_WROT0_SW_RST_DONE_ENG_EVENT				318
+#define CMDQ_EVENT_MML1_MDP_RROT0_SW_RST_DONE_ENG_EVENT				319
+#define CMDQ_EVENT_MML1_MDP_RDMA2_SW_RST_DONE_ENG_EVENT				320
+#define CMDQ_EVENT_MML1_MDP_RDMA1_SW_RST_DONE_ENG_EVENT				321
+#define CMDQ_EVENT_MML1_MDP_RDMA0_SW_RST_DONE_ENG_EVENT				322
+#define CMDQ_EVENT_MML1_MDP_MERGE0_SW_RST_DONE_ENG_EVENT			323
+#define CMDQ_EVENT_MML1_DISP_MUTEX0_TIMEOUT_ENG_EVENT				324
+#define CMDQ_EVENT_MML1_DISP_MUTEX0_GET_RLZ_ENG_EVENT				325
+/* CMDQ_EVENT_OVL0_STREAM_SOF0 ~ 15: 326 ~ 341 */
+#define CMDQ_EVENT_OVL0_STREAM_SOF(n)						(326 + (n))
+/* CMDQ_EVENT_OVL0_FRAME_DONE_SEL0 ~ 15: 342 ~ 357 */
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL(n)					(342 + (n))
+#define CMDQ_EVENT_OVL0_OVL_UFBC_WDMA0_TARGET_LINE_END_ENG_EVENT		358
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_TIMEOUT_ENG_EVENT				359
+/* CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 360 ~ 375 */
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT(n)			(360 + (n))
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_GET_RELEASE_ENG_EVENT			376
+#define CMDQ_EVENT_OVL0_OVL_MDP_RDMA1_SW_RST_DONE_ENG_EVENT			377
+#define CMDQ_EVENT_OVL0_OVL_MDP_RDMA0_SW_RST_DONE_ENG_EVENT			378
+#define CMDQ_EVENT_OVL0_OVL_EXDMA9_FRAME_RESET_DONE_ENG_EVENT			379
+#define CMDQ_EVENT_OVL0_OVL_EXDMA8_FRAME_RESET_DONE_ENG_EVENT			380
+#define CMDQ_EVENT_OVL0_OVL_EXDMA7_FRAME_RESET_DONE_ENG_EVENT			381
+#define CMDQ_EVENT_OVL0_OVL_EXDMA6_FRAME_RESET_DONE_ENG_EVENT			382
+#define CMDQ_EVENT_OVL0_OVL_EXDMA5_FRAME_RESET_DONE_ENG_EVENT			383
+#define CMDQ_EVENT_OVL0_OVL_EXDMA4_FRAME_RESET_DONE_ENG_EVENT			384
+#define CMDQ_EVENT_OVL0_OVL_EXDMA3_FRAME_RESET_DONE_ENG_EVENT			385
+#define CMDQ_EVENT_OVL0_OVL_EXDMA2_FRAME_RESET_DONE_ENG_EVENT			386
+#define CMDQ_EVENT_OVL0_OVL_EXDMA1_FRAME_RESET_DONE_ENG_EVENT			387
+#define CMDQ_EVENT_OVL0_OVL_EXDMA0_FRAME_RESET_DONE_ENG_EVENT			388
+#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT		389
+#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA1_SW_RST_DONE_END_ENG_EVENT		390
+#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT		391
+#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA0_SW_RST_DONE_END_ENG_EVENT		392
+#define CMDQ_EVENT_OVL0_OVL_BWM0_FRAME_RESET_DONE_ENG_EVENT			393
+/* CMDQ_EVENT_OVL1_STREAM_SOF0 ~ 15: 394 ~ 409 */
+#define CMDQ_EVENT_OVL1_STREAM_SOF(n)						(394 + (n))
+/* CMDQ_EVENT_OVL1_FRAME_DONE_SEL0 ~ 15: 410 ~ 425 */
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL(n)					(410 + (n))
+#define CMDQ_EVENT_OVL1_OVL_UFBC_WDMA0_TARGET_LINE_END_ENG_EVENT		426
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_TIMEOUT_ENG_EVENT				427
+/* CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 428 ~ 443 */
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT(n)			(428 + (n))
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_GET_RELEASE_ENG_EVENT			444
+#define CMDQ_EVENT_OVL1_OVL_MDP_RDMA1_SW_RST_DONE_ENG_EVENT			445
+#define CMDQ_EVENT_OVL1_OVL_MDP_RDMA0_SW_RST_DONE_ENG_EVENT			446
+#define CMDQ_EVENT_OVL1_OVL_EXDMA9_FRAME_RESET_DONE_ENG_EVENT			447
+#define CMDQ_EVENT_OVL1_OVL_EXDMA8_FRAME_RESET_DONE_ENG_EVENT			448
+#define CMDQ_EVENT_OVL1_OVL_EXDMA7_FRAME_RESET_DONE_ENG_EVENT			449
+#define CMDQ_EVENT_OVL1_OVL_EXDMA6_FRAME_RESET_DONE_ENG_EVENT			450
+#define CMDQ_EVENT_OVL1_OVL_EXDMA5_FRAME_RESET_DONE_ENG_EVENT			451
+#define CMDQ_EVENT_OVL1_OVL_EXDMA4_FRAME_RESET_DONE_ENG_EVENT			452
+#define CMDQ_EVENT_OVL1_OVL_EXDMA3_FRAME_RESET_DONE_ENG_EVENT			453
+#define CMDQ_EVENT_OVL1_OVL_EXDMA2_FRAME_RESET_DONE_ENG_EVENT			454
+#define CMDQ_EVENT_OVL1_OVL_EXDMA1_FRAME_RESET_DONE_ENG_EVENT			455
+#define CMDQ_EVENT_OVL1_OVL_EXDMA0_FRAME_RESET_DONE_ENG_EVENT			456
+#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT		457
+#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA1_SW_RST_DONE_END_ENG_EVENT		458
+#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT		459
+#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA0_SW_RST_DONE_END_ENG_EVENT		460
+#define CMDQ_EVENT_OVL1_OVL_BWM0_FRAME_RESET_DONE_ENG_EVENT			461
+#define CMDQ_EVENT_DPC_DT_DONE0							462
+#define CMDQ_EVENT_DPC_DT_DONE1							463
+#define CMDQ_EVENT_DPC_DT_DONE2_0_MERGE						464
+#define CMDQ_EVENT_DPC_DT_DONE2_1_MERGE						465
+#define CMDQ_EVENT_DPC_DT_DONE2_2_MERGE						466
+#define CMDQ_EVENT_DPC_DT_DONE2_3_MERGE						467
+#define CMDQ_EVENT_DPC_DT_DONE3							468
+#define CMDQ_EVENT_DPC_DT_DONE4_MERGE						469
+#define CMDQ_EVENT_DPC_DT_DONE5							470
+#define CMDQ_EVENT_DPC_DT_DONE6_0_MERGE						471
+#define CMDQ_EVENT_DPC_DT_DONE6_1_MERGE						472
+#define CMDQ_EVENT_DPC_DT_DONE6_2_MERGE						473
+#define CMDQ_EVENT_DPC_DT_DONE6_3_MERGE						474
+#define CMDQ_EVENT_DPC_DT_DONE7							475
+#define CMDQ_EVENT_DPC_DT_DONE32_MERGE						476
+#define CMDQ_EVENT_DPC_DT_DONE33						477
+#define CMDQ_EVENT_DPC_DT_DONE34_0						478
+#define CMDQ_EVENT_DPC_DT_DONE35						479
+#define CMDQ_EVENT_DPC_DISP_SSYS_DT_ERR_ON_BEFORE_OFF				480
+#define CMDQ_EVENT_DPC_DISP_SSYS_DT_ERR_PRETE_BEFORE_ON				481
+#define CMDQ_EVENT_DPC_DISP_DVFS_DT_ERR_ON_BEFORE_OFF				482
+#define CMDQ_EVENT_DPC_DISP_DVFS_DT_ERR_PRETE_BEFORE_ON				483
+#define CMDQ_EVENT_DPC_DISP_SB_DT_ERR_ON_BEFORE_OFF				484
+#define CMDQ_EVENT_DPC_DISP_SB_DT_ERR_PRETE_BEFORE_ON				485
+#define CMDQ_EVENT_DPC_DISP_SW_CONFIG_WHEN_MTCMOS_OFF				486
+#define CMDQ_EVENT_DPC_MML_SSYS_DT_ERR_ON_BEFORE_OFF				487
+#define CMDQ_EVENT_DPC_MML_SSYS_DT_ERR_PRETE_BEFORE_ON				488
+#define CMDQ_EVENT_DPC_MML_DVFS_DT_ERR_ON_BEFORE_OFF				489
+#define CMDQ_EVENT_DPC_MML_DVFS_DT_ERR_PRETE_BEFORE_ON				490
+#define CMDQ_EVENT_DPC_MML_SB_DT_ERR_ON_BEFORE_OFF				491
+#define CMDQ_EVENT_DPC_MML_SB_DT_ERR_PRETE_BEFORE_ON				492
+#define CMDQ_EVENT_DPC_MML_SW_CONFIG_WHEN_MTCMOS_OFF				493
+/* CMDQ_EVENT_DPTX_DPTX_EVENT0 ~ 3: 494 ~ 497 */
+#define CMDQ_EVENT_DPTX_DPTX_EVENT(n)						(494 + (n))
+/* CMDQ_EVENT_EDPTX_EDPTX_EVENT0 ~ 1: 498 ~ 499 */
+#define CMDQ_EVENT_EDPTX_EDPTX_EVENT(n)						(498 + (n))
+
+#define CMDQ_EVENT_DSI0_TE_I_DSI0_TE_I						898
+#define CMDQ_EVENT_DSI1_TE_I_DSI1_TE_I						899
+#define CMDQ_EVENT_DSI2_TE_I_DSI2_TE_I						900
+/* CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK0 ~ 23: 901 ~ 924 */
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK(n)			(901 + (n))
+/* CMDQ_EVENT_GCE_EVENT_DPTX_GCE_EVENT_DPTX0 ~ 1: 925 ~ 926 */
+#define CMDQ_EVENT_GCE_EVENT_DPTX_GCE_EVENT_DPTX(n)				(925 + (n))
+/* CMDQ_EVENT_GCE_EVENT_DPTX_P1_GCE_EVENT_DPTX_P10 ~ 1: 927 ~ 928 */
+#define CMDQ_EVENT_GCE_EVENT_DPTX_P1_GCE_EVENT_DPTX_P1(n)			(927 + (n))
+/* CMDQ_EVENT_GCE_EVENT_EDPTX_GCE_EVENT_EDPTX0 ~ 1: 929 ~ 930 */
+#define CMDQ_EVENT_GCE_EVENT_EDPTX_GCE_EVENT_EDPTX(n)				(929 + (n))
+#define CMDQ_EVENT_DSI3_TE_I_DSI3_TE_I						931
+#define CMDQ_EVENT_SPI0_FINISH_EVENT_DSI4_TE_I					932
+#define CMDQ_EVENT_SPI0_EVENT_EVENT_DSI5_TE_I					933
+
+/*
+ * GCE1 Hardware Event IDs
+ * Different SoCs will have varying numbers of hardware event signals,
+ * which are sent from the corresponding hardware to the GCE.
+ * Each hardware event signal corresponds to an event ID in the GCE.
+ * The CMDQ driver can use the following event ID definitions to allow
+ * the client driver to use wait and clear APIs provided by CMDQ, enabling
+ * the GCE to execute operations in the instructions for that event ID.
+ *
+ * The event IDs of GCE1 are mainly used by non-display hardware.
+ */
+#define CMDQ_EVENT_VENC3_VENC_RESERVED						0
+#define CMDQ_EVENT_VENC3_VENC_FRAME_DONE					1
+#define CMDQ_EVENT_VENC3_VENC_PAUSE_DONE					2
+#define CMDQ_EVENT_VENC3_JPGENC_DONE						3
+#define CMDQ_EVENT_VENC3_VENC_MB_DONE						4
+#define CMDQ_EVENT_VENC3_VENC_128BYTE_DONE					5
+#define CMDQ_EVENT_VENC3_JPGDEC_DONE						6
+#define CMDQ_EVENT_VENC3_JPGDEC_C1_DONE						7
+#define CMDQ_EVENT_VENC3_JPGDEC_INSUFF_DONE					8
+#define CMDQ_EVENT_VENC3_JPGDEC_C1_INSUFF_DONE					9
+#define CMDQ_EVENT_VENC3_WP_2ND_STAGE_DONE					10
+#define CMDQ_EVENT_VENC3_WP_3RD_STAGE_DONE					11
+#define CMDQ_EVENT_VENC3_PPS_HEADER_DONE					12
+#define CMDQ_EVENT_VENC3_SPS_HEADER_DONE					13
+#define CMDQ_EVENT_VENC3_VPS_HEADER_DONE					14
+#define CMDQ_EVENT_VENC3_VENC_SLICE_DONE					15
+#define CMDQ_EVENT_VENC3_VENC_SOC_SLICE_DONE					16
+#define CMDQ_EVENT_VENC3_VENC_SOC_FRAME_DONE					17
+
+#define CMDQ_EVENT_VENC2_VENC_FRAME_DONE					33
+#define CMDQ_EVENT_VENC2_VENC_PAUSE_DONE					34
+#define CMDQ_EVENT_VENC2_JPGENC_DONE						35
+#define CMDQ_EVENT_VENC2_VENC_MB_DONE						36
+#define CMDQ_EVENT_VENC2_VENC_128BYTE_DONE					37
+#define CMDQ_EVENT_VENC2_JPGDEC_DONE						38
+#define CMDQ_EVENT_VENC2_JPGDEC_C1_DONE						39
+#define CMDQ_EVENT_VENC2_JPGDEC_INSUFF_DONE					40
+#define CMDQ_EVENT_VENC2_JPGDEC_C1_INSUFF_DONE					41
+#define CMDQ_EVENT_VENC2_WP_2ND_STAGE_DONE					42
+#define CMDQ_EVENT_VENC2_WP_3RD_STAGE_DONE					43
+#define CMDQ_EVENT_VENC2_PPS_HEADER_DONE					44
+#define CMDQ_EVENT_VENC2_SPS_HEADER_DONE					45
+#define CMDQ_EVENT_VENC2_VPS_HEADER_DONE					46
+#define CMDQ_EVENT_VENC2_VENC_SLICE_DONE					47
+#define CMDQ_EVENT_VENC2_VENC_SOC_SLICE_DONE					48
+#define CMDQ_EVENT_VENC2_VENC_SOC_FRAME_DONE					49
+
+#define CMDQ_EVENT_VENC1_VENC_FRAME_DONE					65
+#define CMDQ_EVENT_VENC1_VENC_PAUSE_DONE					66
+#define CMDQ_EVENT_VENC1_JPGENC_DONE						67
+#define CMDQ_EVENT_VENC1_VENC_MB_DONE						68
+#define CMDQ_EVENT_VENC1_VENC_128BYTE_DONE					69
+#define CMDQ_EVENT_VENC1_JPGDEC_DONE						70
+#define CMDQ_EVENT_VENC1_JPGDEC_C1_DONE						71
+#define CMDQ_EVENT_VENC1_JPGDEC_INSUFF_DONE					72
+#define CMDQ_EVENT_VENC1_JPGDEC_C1_INSUFF_DONE					73
+#define CMDQ_EVENT_VENC1_WP_2ND_STAGE_DONE					74
+#define CMDQ_EVENT_VENC1_WP_3RD_STAGE_DONE					75
+#define CMDQ_EVENT_VENC1_PPS_HEADER_DONE					76
+#define CMDQ_EVENT_VENC1_SPS_HEADER_DONE					77
+#define CMDQ_EVENT_VENC1_VPS_HEADER_DONE					78
+#define CMDQ_EVENT_VENC1_VENC_SLICE_DONE					79
+#define CMDQ_EVENT_VENC1_VENC_SOC_SLICE_DONE					80
+#define CMDQ_EVENT_VENC1_VENC_SOC_FRAME_DONE					81
+
+#define CMDQ_EVENT_VDEC1_VDEC_LINE_CNT_INT					192
+#define CMDQ_EVENT_VDEC1_VDEC_INT						193
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_2						194
+#define CMDQ_EVENT_VDEC1_VDEC_DEC_ERR						195
+#define CMDQ_EVENT_VDEC1_VDEC_BUSY_OVERFLOW					196
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_5						197
+#define CMDQ_EVENT_VDEC1_VDEC_INI_FETCH_RDY					198
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_7						199
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_8						200
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_9						201
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_10						202
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_11						203
+
+#define CMDQ_EVENT_VDEC1_VDEC_GCE_CNT_OP_THR					207
+
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_32						224
+#define CMDQ_EVENT_VDEC1_VDEC_LAT_INT						225
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_34						226
+#define CMDQ_EVENT_VDEC1_VDEC_LAT_DEC_ERR					227
+#define CMDQ_EVENT_VDEC1_VDEC_LAT_BUSY_OVERFLOW					228
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_37						229
+#define CMDQ_EVENT_VDEC1_VDEC_LAT_INI_FETCH_RDY					230
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_39						231
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_40						232
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_41						233
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_42						234
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_43						235
+
+#define CMDQ_EVENT_VDEC1_VDEC_LAT_GCE_CNT_OP_THR				239
+
+#define CMDQ_EVENT_IMG_IMG_EVENT_0						256
+/* CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_0 ~ 5: 257 ~  262 */
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0(n)				(257 + (n))
+#define CMDQ_EVENT_IMG_TRAW0_DMA_ERR_EVENT					263
+#define CMDQ_EVENT_IMG_TRAW0_DUMMY_0						264
+/* CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_0 ~ 5: 265 ~ 270 */
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0(n)				(265 + (n))
+#define CMDQ_EVENT_IMG_TRAW1_DMA_ERR_EVENT					271
+#define CMDQ_EVENT_IMG_ADL_TILE_DONE_EVENT					272
+#define CMDQ_EVENT_IMG_ADLWR0_TILE_DONE_EVENT					273
+#define CMDQ_EVENT_IMG_ADLWR1_TILE_DONE_EVENT					274
+#define CMDQ_EVENT_IMG_IMGSYS_IPE_ME_DONE					275
+#define CMDQ_EVENT_IMG_IMGSYS_IPE_MMG_DONE					276
+/* CMDQ_EVENT_IMG_QOF_ACK_EVENT0 ~ 19: 277 ~ 296 */
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT(n)						(277 + (n))
+/* CMDQ_EVENT_IMG_QOF_ON_EVENT0 ~ 4: 297 ~ 301 */
+#define CMDQ_EVENT_IMG_QOF_ON_EVENT(n)						(297 + (n))
+/* CMDQ_EVENT_IMG_QOF_OFF_EVENT0 ~ 4: 302 ~ 306 */
+#define CMDQ_EVENT_IMG_QOF_OFF_EVENT(n)						(302 + (n))
+/* CMDQ_EVENT_IMG_QOF_SAVE_EVENT0 ~ 4: 307 ~ 311 */
+#define CMDQ_EVENT_IMG_QOF_SAVE_EVENT(n)					(307 + (n))
+/* CMDQ_EVENT_IMG_QOF_RESTORE_EVENT0 ~ 4: 312 ~ 316 */
+#define CMDQ_EVENT_IMG_QOF_RESTORE_EVENT(n)					(312 + (n))
+/* CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P20~5: 317 ~ 322 */
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2(n)					(317 + (n))
+#define CMDQ_EVENT_IMG_DIP_DMA_ERR_EVENT					323
+#define CMDQ_EVENT_IMG_DIP_NR_DMA_ERR_EVENT					324
+#define CMDQ_EVENT_IMG_DIP_DUMMY_0						325
+#define CMDQ_EVENT_IMG_WPE_EIS_GCE_FRAME_DONE					326
+#define CMDQ_EVENT_IMG_WPE_EIS_DONE_SYNC_OUT					327
+/* CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P20 ~ 5: 328 ~ 333 */
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2(n)				(328 + (n))
+/* CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P20 ~ 5: 334 ~ 339 */
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2(n)				(334 + (n))
+#define CMDQ_EVENT_IMG_PQA_DMA_ERR_EVENT					340
+/* CMDQ_EVENT_IMG_WPE0_DUMMY0~2: 341 ~ 343 */
+#define CMDQ_EVENT_IMG_WPE0_DUMMY(n)						(341 + (n))
+#define CMDQ_EVENT_IMG_OMC_TNR_GCE_FRAME_DONE					344
+#define CMDQ_EVENT_IMG_OMC_TNR_DONE_SYNC_OUT					345
+/* CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P20 ~ 5: 346 ~ 351 */
+#define CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P2(n)				(346 + (n))
+/* CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P20 ~ 5: 352 ~ 357 */
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2(n)				(352 + (n))
+#define CMDQ_EVENT_IMG_PQB_DMA_ERR_EVENT					358
+/* CMDQ_EVENT_IMG_WPE1_DUMMY0 ~ 2: 359 ~ 361 */
+#define CMDQ_EVENT_IMG_WPE1_DUMMY(n)						(359 + (n))
+#define CMDQ_EVENT_IMG_WPE_LITE_GCE_FRAME_DONE					362
+#define CMDQ_EVENT_IMG_WPE_LITE_DONE_SYNC_OUT					363
+/* CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P20 ~ 5: 364 ~ 369 */
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2(n)				(364 + (n))
+#define CMDQ_EVENT_IMG_OMC_LITE_GCE_FRAME_DONE					370
+#define CMDQ_EVENT_IMG_OMC_LITE_DONE_SYNC_OUT					371
+/* CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P20 ~ 5: 372 ~ 377 */
+#define CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P2(n)				(372 + (n))
+/* CMDQ_EVENT_IMG_WPE2_DUMMY0 ~ 2: 378 ~ 380 */
+#define CMDQ_EVENT_IMG_WPE2_DUMMY(n)						(378 + (n))
+#define CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT0_DONE					381
+#define CMDQ_EVENT_IMG_IMG_EVENT_126						382
+#define CMDQ_EVENT_IMG_IMG_EVENT_127						383
+#define CMDQ_EVENT_CAM_CAM_EVENT_0						384
+#define CMDQ_EVENT_CAM_CAM_SUBA_SW_PASS1_DONE					385
+#define CMDQ_EVENT_CAM_CAM_SUBB_SW_PASS1_DONE					386
+#define CMDQ_EVENT_CAM_CAM_SUBC_SW_PASS1_DONE					387
+#define CMDQ_EVENT_CAM_CAM_SUBA_TFMR_PASS1_DONE					388
+#define CMDQ_EVENT_CAM_CAM_SUBB_TFMR_PASS1_DONE					389
+#define CMDQ_EVENT_CAM_CAM_SUBC_TFMR_PASS1_DONE					390
+/* CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE0 ~ 3: 391 ~ 394 */
+#define CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE(n)					(391 + (n))
+/* CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE0 ~ 3: 395 ~ 398 */
+#define CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE(n)					(395 + (n))
+/* CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE0 ~ 3: 399 + 402 */
+#define CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE(n)					(399 + (n))
+/* CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE0 ~ 3: 403 ~ 406 */
+#define CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE(n)					(403 + (n))
+/* CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE0 ~ 3: 407 ~ 409 */
+#define CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE(n)					(407 + (n))
+/* CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE0 ~ 3: 411 ~ 413 */
+#define CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE(n)					(411 + (n))
+#define CMDQ_EVENT_CAM_MRAW0_SW_PASS1_DONE					415
+#define CMDQ_EVENT_CAM_MRAW1_SW_PASS1_DONE					416
+#define CMDQ_EVENT_CAM_MRAW2_SW_PASS1_DONE					417
+#define CMDQ_EVENT_CAM_MRAW3_SW_PASS1_DONE					418
+#define CMDQ_EVENT_CAM_UISP_SW_PASS1_DONE					419
+#define CMDQ_EVENT_CAM_TG_MRAW0_OUT_SOF						420
+#define CMDQ_EVENT_CAM_TG_MRAW1_OUT_SOF						421
+#define CMDQ_EVENT_CAM_TG_MRAW2_OUT_SOF						422
+#define CMDQ_EVENT_CAM_TG_MRAW3_OUT_SOF						423
+#define CMDQ_EVENT_CAM_PDA0_IRQO_EVENT_DONE_D1					424
+#define CMDQ_EVENT_CAM_PDA1_IRQO_EVENT_DONE_D1					425
+#define CMDQ_EVENT_CAM_DPE_DVP_CMQ_EVENT					426
+#define CMDQ_EVENT_CAM_DPE_DVS_CMQ_EVENT					427
+#define CMDQ_EVENT_CAM_DPE_DVFG_CMQ_EVENT					428
+#define CMDQ_EVENT_CAM_CAM_EVENT_45						429
+#define CMDQ_EVENT_CAM_CAM_EVENT_46						430
+#define CMDQ_EVENT_CAM_CAM_EVENT_47						431
+#define CMDQ_EVENT_CAM_CAM_EVENT_48						432
+/* CMDQ_EVENT_CAM_CAM_SUBA_TG_INT1 ~ 4: 433 ~ 436 */
+#define CMDQ_EVENT_CAM_CAM_SUBA_TG_INT(n)					(433 + (n) - 1)
+/* CMDQ_EVENT_CAM_CAM_SUBB_TG_INT1 ~ 4: 437 ~ 440 */
+#define CMDQ_EVENT_CAM_CAM_SUBB_TG_INT(n)					(437 + (n) - 1)
+/* CMDQ_EVENT_CAM_CAM_SUBC_TG_INT1 ~ 4: 441 ~ 444 */
+#define CMDQ_EVENT_CAM_CAM_SUBC_TG_INT(n)					(441 + (n) - 1)
+#define CMDQ_EVENT_CAM_RAW_O_SOF_SUBA						445
+#define CMDQ_EVENT_CAM_RAW_O_SOF_SUBB						446
+#define CMDQ_EVENT_CAM_RAW_O_SOF_SUBC						447
+#define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBA					448
+#define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBB					449
+#define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBC					450
+#define CMDQ_EVENT_CAM_RAW_SEL_SOF_UISP						451
+#define CMDQ_EVENT_CAM_CAM_SUBA_RING_BUFFER_OVERFLOW_INT_IN			452
+#define CMDQ_EVENT_CAM_CAM_SUBB_RING_BUFFER_OVERFLOW_INT_IN			453
+#define CMDQ_EVENT_CAM_CAM_SUBC_RING_BUFFER_OVERFLOW_INT_IN			454
+#define CMDQ_EVENT_CAM_CAM_EVENT_71						455
+#define CMDQ_EVENT_CAM_ADL_WR_FRAME_DONE					456
+#define CMDQ_EVENT_CAM_ADL_RD_FRAME_DONE					457
+#define CMDQ_EVENT_CAM_QOF_RAWA_POWER_ON_EVENT					458
+#define CMDQ_EVENT_CAM_QOF_RAWB_POWER_ON_EVENT					459
+#define CMDQ_EVENT_CAM_QOF_RAWC_POWER_ON_EVENT					460
+#define CMDQ_EVENT_CAM_QOF_RAWA_POWER_OFF_EVENT					461
+#define CMDQ_EVENT_CAM_QOF_RAWB_POWER_OFF_EVENT					462
+#define CMDQ_EVENT_CAM_QOF_RAWC_POWER_OFF_EVENT					463
+#define CMDQ_EVENT_CAM_QOF_RAWA_SAVE_EVENT					464
+#define CMDQ_EVENT_CAM_QOF_RAWB_SAVE_EVENT					465
+#define CMDQ_EVENT_CAM_QOF_RAWC_SAVE_EVENT					466
+#define CMDQ_EVENT_CAM_QOF_RAWA_RESTORE_EVENT					467
+#define CMDQ_EVENT_CAM_QOF_RAWB_RESTORE_EVENT					468
+#define CMDQ_EVENT_CAM_QOF_RAWC_RESTORE_EVENT					469
+/* CMDQ_EVENT_CAM_QOF_CAM_EVENT0 ~ 11: 470 ~ 481 */
+#define CMDQ_EVENT_CAM_QOF_CAM_EVENT(n)						(470 + (n))
+/* CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT0 ~ 11: 482 ~ 495 */
+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT(n)					(482 + (n))
+#define CMDQ_EVENT_CAM_CCU0_TO_GCE_NON_SEC_IRQ					496
+#define CMDQ_EVENT_CAM_CCU0_TO_GCE_SEC_IRQ					497
+#define CMDQ_EVENT_CAM_CCU0_TO_GCE_VM_IRQ					498
+#define CMDQ_EVENT_CAM_CCU0_TO_GCE_EXCH_VM_IRQ					499
+#define CMDQ_EVENT_CAM_CCU1_TO_GCE_NON_SEC_IRQ					500
+#define CMDQ_EVENT_CAM_CCU1_TO_GCE_SEC_IRQ					501
+#define CMDQ_EVENT_CAM_CCU1_TO_GCE_VM_IRQ					502
+#define CMDQ_EVENT_CAM_CCU1_TO_GCE_EXCH_VM_IRQ					503
+/* CMDQ_EVENT_CAM_I2C_CH2_EVENT0 ~ 4: 504 ~ 509 */
+#define CMDQ_EVENT_CAM_I2C_CH2_EVENT(n)						(504 + (n))
+#define CMDQ_EVENT_CAM_CAM_EVENT_125						509
+#define CMDQ_EVENT_CAM_CAM_EVENT_126						510
+#define CMDQ_EVENT_CAM_CAM_EVENT_127						511
+
+#define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_MMSRAM_COMM_SMIASSER			898
+#define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_MDP_COMM_SMIASSER			899
+#define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_DISP_COMM_SMIASSER			900
+
+/*
+ * GCE Software Tokens
+ * Apart from the event IDs that are already bound to hardware event signals,
+ * the remaining event IDs can be used as software tokens.
+ * This allows the client driver to name and operate them independently,
+ * and their usage is the same as that of hardware events.
+ */
+/* Begin of GCE0 software token */
+/* Config thread notify trigger thread */
+#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY			640
+/* Trigger thread notify config thread */
+#define CMDQ_SYNC_TOKEN_STREAM_EOF			641
+/* Block Trigger thread until the ESD check finishes */
+#define CMDQ_SYNC_TOKEN_ESD_EOF				642
+#define CMDQ_SYNC_TOKEN_STREAM_BLOCK			643
+/* Check CABC setup finish */
+#define CMDQ_SYNC_TOKEN_CABC_EOF			644
+/* VFP period token for Msync */
+#define CMDQ_SYNC_TOKEN_VFP_PERIOD			645
+/* Software sync token for dual display */
+#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_1			694
+#define CMDQ_SYNC_TOKEN_STREAM_EOF_1			695
+#define CMDQ_SYNC_TOKEN_ESD_EOF_1			696
+#define CMDQ_SYNC_TOKEN_STREAM_BLOCK_1			697
+#define CMDQ_SYNC_TOKEN_CABC_EOF_1			698
+
+/*
+ * GPR access tokens (for HW register backup)
+ * There are 15 32-bit GPR, form 3 GPR as a set
+ * (64-bit for address, 32-bit for value)
+ *
+ * CMDQ_SYNC_TOKEN_GPR_SET0 ~ 4: 700 ~ 704
+ */
+#define CMDQ_SYNC_TOKEN_GPR_SET(n)			(700 + (n))
+#define CMDQ_SYNC_TOKEN_TE_0				705
+#define CMDQ_SYNC_TOKEN_PREFETCH_TE_0			706
+#define CMDQ_SYNC_TOKEN_VIDLE_POWER_ON			707
+#define CMDQ_SYNC_TOKEN_CHECK_TRIGGER_MERGE		708
+
+/* Resource lock event to control resource in GCE thread */
+#define CMDQ_SYNC_RESOURCE_WROT0			710
+#define CMDQ_SYNC_RESOURCE_WROT1			711
+/* Hardware TRACE software token */
+#define CMDQ_SYNC_TOKEN_HW_TRACE_WAIT			712
+#define CMDQ_SYNC_TOKEN_HW_TRACE_LOCK			713
+/* Software sync token for dual display */
+#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_3			714
+#define CMDQ_SYNC_TOKEN_STREAM_EOF_3			715
+#define CMDQ_SYNC_TOKEN_ESD_EOF_3			716
+#define CMDQ_SYNC_TOKEN_STREAM_BLOCK_3			717
+#define CMDQ_SYNC_TOKEN_CABC_EOF_3			718
+/* End of GCE0 software token */
+
+/* Begin of GCE1 software token */
+/* CMDQ_SYNC_TOKEN_IMGSYS_POOL0 ~ 300: 512 ~ 812 */
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL(n)			(512 + (n))
+/* ISP software token */
+#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS			813
+#define CMDQ_SYNC_TOKEN_IMGSYS_OMC_TNR			814
+#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_LITE			815
+#define CMDQ_SYNC_TOKEN_IMGSYS_TRAW			816
+#define CMDQ_SYNC_TOKEN_IMGSYS_LTRAW			817
+#define CMDQ_SYNC_TOKEN_IMGSYS_XTRAW			818
+#define CMDQ_SYNC_TOKEN_IMGSYS_DIP			819
+#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A			820
+#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B			821
+#define CMDQ_SYNC_TOKEN_IPESYS_ME			822
+#define CMDQ_SYNC_TOKEN_APUSYS_APU			823
+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_TRAW			824
+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_LTRAW		825
+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_XTRAW		826
+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_DIP			827
+#define CMDQ_SYNC_TOKEN_IMGSYS_OMC_LITE			828
+/* IMG software token for QoS */
+#define CMDQ_SYNC_TOKEN_IMGSYS_QOS_LOCK			829
+/* IMG software token for Qof */
+#define CMDQ_SYNC_TOKEN_DIP_POWER_CTRL			830
+#define CMDQ_SYNC_TOKEN_DIP_TRIG_PWR_ON			831
+#define CMDQ_SYNC_TOKEN_DIP_PWR_ON			832
+#define CMDQ_SYNC_TOKEN_DIP_TRIG_PWR_OFF		833
+#define CMDQ_SYNC_TOKEN_DIP_PWR_OFF			834
+#define CMDQ_SYNC_TOKEN_DIP_PWR_HAND_SHAKE		835
+#define CMDQ_SYNC_TOKEN_TRAW_POWER_CTRL			836
+#define CMDQ_SYNC_TOKEN_TRAW_TRIG_PWR_ON		837
+#define CMDQ_SYNC_TOKEN_TRAW_PWR_ON			838
+#define CMDQ_SYNC_TOKEN_TRAW_TRIG_PWR_OFF		839
+#define CMDQ_SYNC_TOKEN_TRAW_PWR_OFF			840
+#define CMDQ_SYNC_TOKEN_TRAW_PWR_HAND_SHAKE		841
+/* End of GCE1 software token */
+
+/* Begin of common software token */
+/*
+ * Notify normal CMDQ there are some secure task done
+ * MUST NOT CHANGE, this token sync with secure world
+ */
+#define CMDQ_SYNC_SECURE_THR_EOF			940
+/* CMDQ use software token */
+#define CMDQ_SYNC_TOKEN_USER_0				941
+#define CMDQ_SYNC_TOKEN_USER_1				942
+#define CMDQ_SYNC_TOKEN_POLL_MONITOR			943
+#define CMDQ_SYNC_TOKEN_TPR_LOCK			942
+/* TZMP software token */
+#define CMDQ_SYNC_TOKEN_TZMP_DISP_WAIT			943
+#define CMDQ_SYNC_TOKEN_TZMP_DISP_SET			944
+#define CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT			945
+#define CMDQ_SYNC_TOKEN_TZMP_ISP_SET			946
+#define CMDQ_SYNC_TOKEN_TZMP_AIE_WAIT			947
+#define CMDQ_SYNC_TOKEN_TZMP_AIE_SET			948
+#define CMDQ_SYNC_TOKEN_TZMP_ADL_WAIT			949
+#define CMDQ_SYNC_TOKEN_TZMP_ADL_SET			950
+/* PREBUILT software token */
+#define CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK		951
+#define CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK		952
+#define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK		953
+#define CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK		954
+#define CMDQ_SYNC_TOKEN_DISP_VA_START			955
+#define CMDQ_SYNC_TOKEN_DISP_VA_END			956
+
+/*
+ * Event for GPR timer, used in sleep and poll with timeout
+ *
+ * CMDQ_TOKEN_GPR_TIMER_R0~15: 994 ~ 1009
+ */
+#define CMDQ_TOKEN_GPR_TIMER_R(n)			(994 + (n))
+/* End of common software token */
+
+#endif
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:38 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:38 +0800
Subject: [PATCH RESEND v5 16/20] soc: mediatek: mtk-cmdq: Add mminfra_offset adjustment for DRAM addresses
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-17-jason-jh.lin@mediatek.com>

Since GCE has been moved to MMINFRA in MT8196, all transactions from
MMINFRA to DRAM will have their addresses adjusted by subtracting a
mminfra_offset.

Therefore, the CMDQ helper driver needs to get the mminfra_offset value
of the SoC from cmdq_mbox_priv of cmdq_pkt and then add it to the DRAM
address when generating instructions to ensure GCE accesses the correct
DRAM address. CMDQ users can then call CMDQ helper APIs as usual.

Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/soc/mediatek/mtk-cmdq-helper.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index fd978fbd684b..0a718ffa5f3b 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -358,6 +358,7 @@ int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_t dst_
 	int ret;
 
 	/* read the value of src_addr into high_addr_reg_idx */
+	src_addr += pkt->priv.mminfra_offset;
 	ret = cmdq_pkt_assign(pkt, high_addr_reg_idx, CMDQ_ADDR_HIGH(src_addr));
 	if (ret < 0)
 		return ret;
@@ -366,6 +367,7 @@ int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_t dst_
 		return ret;
 
 	/* write the value of value_reg_idx into dst_addr */
+	dst_addr += pkt->priv.mminfra_offset;
 	ret = cmdq_pkt_assign(pkt, high_addr_reg_idx, CMDQ_ADDR_HIGH(dst_addr));
 	if (ret < 0)
 		return ret;
@@ -491,7 +493,7 @@ int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u32 mas
 	inst.op = CMDQ_CODE_MASK;
 	inst.dst_t = CMDQ_REG_TYPE;
 	inst.sop = CMDQ_POLL_ADDR_GPR;
-	inst.value = addr;
+	inst.value = addr + pkt->priv.mminfra_offset;
 	ret = cmdq_pkt_append_command(pkt, inst);
 	if (ret < 0)
 		return ret;
@@ -551,7 +553,7 @@ int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr)
 	struct cmdq_instruction inst = {
 		.op = CMDQ_CODE_JUMP,
 		.offset = CMDQ_JUMP_ABSOLUTE,
-		.value = addr >> pkt->priv.shift_pa
+		.value = (addr +  pkt->priv.mminfra_offset) >> pkt->priv.shift_pa
 	};
 	return cmdq_pkt_append_command(pkt, inst);
 }
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:37 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:37 +0800
Subject: [PATCH RESEND v5 15/20] soc: mediatek: mtk-cmdq: Add new APIs to replace cmdq_pkt_write() and cmdq_pkt_write_mask()
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-16-jason-jh.lin@mediatek.com>

To support generating GCE write instructions using both pa_base and
subsys, the original cmdq_pkt_write() and cmdq_pkt_write_mask() have
been expanded into four new APIs:
- Replaced cmdq_pkt_write() to cmdq_pkt_write_pa() and
  cmdq_pkt_write_subsys().
- Replaced cmdq_pkt_write_mask() to cmdq_pkt_write_mask_pa() and
  cmdq_pkt_write_mask_subsys().

The original cmdq_pkt_write() and cmdq_pkt_write_mask() will be removed
after all CMDQ users have migrated to the new APIs.

Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/soc/mediatek/mtk-cmdq-helper.c | 41 +++++++++++++
 include/linux/soc/mediatek/mtk-cmdq.h  | 79 ++++++++++++++++++++++++++
 2 files changed, 120 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index bae6753bd4a7..fd978fbd684b 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -213,6 +213,26 @@ int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
 }
 EXPORT_SYMBOL(cmdq_pkt_write);
 
+int cmdq_pkt_write_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/, u32 pa_base,
+		      u16 offset, u32 value)
+{
+	int err;
+
+	err = cmdq_pkt_assign(pkt, CMDQ_THR_SPR_IDX0, CMDQ_ADDR_HIGH(pa_base));
+	if (err < 0)
+		return err;
+
+	return cmdq_pkt_write_s_value(pkt, CMDQ_THR_SPR_IDX0, CMDQ_ADDR_LOW(offset), value);
+}
+EXPORT_SYMBOL(cmdq_pkt_write_pa);
+
+int cmdq_pkt_write_subsys(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base /*unused*/,
+			  u16 offset, u32 value)
+{
+	return cmdq_pkt_write(pkt, subsys, offset, value);
+}
+EXPORT_SYMBOL(cmdq_pkt_write_subsys);
+
 int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
 			u16 offset, u32 value, u32 mask)
 {
@@ -230,6 +250,27 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
 }
 EXPORT_SYMBOL(cmdq_pkt_write_mask);
 
+int cmdq_pkt_write_mask_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/, u32 pa_base,
+			   u16 offset, u32 value, u32 mask)
+{
+	int err;
+
+	err = cmdq_pkt_assign(pkt, CMDQ_THR_SPR_IDX0, CMDQ_ADDR_HIGH(pa_base));
+	if (err < 0)
+		return err;
+
+	return cmdq_pkt_write_s_mask_value(pkt, CMDQ_THR_SPR_IDX0,
+					   CMDQ_ADDR_LOW(offset), value, mask);
+}
+EXPORT_SYMBOL(cmdq_pkt_write_mask_pa);
+
+int cmdq_pkt_write_mask_subsys(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base /*unused*/,
+			       u16 offset, u32 value, u32 mask)
+{
+	return cmdq_pkt_write_mask(pkt, subsys, offset, value, mask);
+}
+EXPORT_SYMBOL(cmdq_pkt_write_mask_subsys);
+
 int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, u16 addr_low,
 		    u16 reg_idx)
 {
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index f9a48262cb95..4a2acceb8581 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -124,6 +124,32 @@ void cmdq_pkt_destroy(struct cmdq_client *client, struct cmdq_pkt *pkt);
  */
 int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);
 
+/**
+ * cmdq_pkt_write_pa() - append write command to the CMDQ packet with pa_base
+ * @pkt:	the CMDQ packet
+ * @subsys:	unused parameter
+ * @pa_base:	the physical address base of the hardware register
+ * @offset:	register offset from CMDQ sub system
+ * @value:	the specified target register value
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_write_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,
+		      u32 pa_base, u16 offset, u32 value);
+
+/**
+ * cmdq_pkt_write_subsys() - append write command to the CMDQ packet with subsys
+ * @pkt:	the CMDQ packet
+ * @subsys:	the CMDQ sub system code
+ * @pa_base:	unused parameter
+ * @offset:	register offset from CMDQ sub system
+ * @value:	the specified target register value
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_write_subsys(struct cmdq_pkt *pkt, u8 subsys,
+			  u32 pa_base /*unused*/, u16 offset, u32 value);
+
 /**
  * cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet
  * @pkt:	the CMDQ packet
@@ -137,6 +163,34 @@ int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);
 int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
 			u16 offset, u32 value, u32 mask);
 
+/**
+ * cmdq_pkt_write_mask_pa() - append write command with mask to the CMDQ packet with pa
+ * @pkt:	the CMDQ packet
+ * @subsys:	unused parameter
+ * @pa_base:	the physical address base of the hardware register
+ * @offset:	register offset from CMDQ sub system
+ * @value:	the specified target register value
+ * @mask:	the specified target register mask
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_write_mask_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,
+			   u32 pa_base, u16 offset, u32 value, u32 mask);
+
+/**
+ * cmdq_pkt_write_mask_subsys() - append write command with mask to the CMDQ packet with subsys
+ * @pkt:	the CMDQ packet
+ * @subsys:	the CMDQ sub system code
+ * @pa_base:	unused parameter
+ * @offset:	register offset from CMDQ sub system
+ * @value:	the specified target register value
+ * @mask:	the specified target register mask
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_write_mask_subsys(struct cmdq_pkt *pkt, u8 subsys,
+			       u32 pa_base /*unused*/, u16 offset, u32 value, u32 mask);
+
 /*
  * cmdq_pkt_read_s() - append read_s command to the CMDQ packet
  * @pkt:	the CMDQ packet
@@ -411,12 +465,37 @@ static inline int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u3
 	return -ENOENT;
 }
 
+static inline int cmdq_pkt_write_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,
+				    u32 pa_base, u16 offset, u32 value)
+{
+	return -ENOENT;
+}
+
+static inline int cmdq_pkt_write_subsys(struct cmdq_pkt *pkt, u8 subsys,
+					u32 pa_base /*unused*/, u16 offset, u32 value)
+{
+	return -ENOENT;
+}
+
 static inline int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
 				      u16 offset, u32 value, u32 mask)
 {
 	return -ENOENT;
 }
 
+static inline int cmdq_pkt_write_mask_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,
+					 u32 pa_base, u16 offset, u32 value, u32 mask)
+{
+	return -ENOENT;
+}
+
+static inline int cmdq_pkt_write_mask_subsys(struct cmdq_pkt *pkt, u8 subsys,
+					     u32 pa_base /*unused*/, u16 offset,
+					     u32 value, u32 mask)
+{
+	return -ENOENT;
+}
+
 static inline int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
 				  u16 addr_low, u16 reg_idx)
 {
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:32 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:32 +0800
Subject: [PATCH RESEND v5 10/20] mailbox: mtk-cmdq: Remove unsued cmdq_get_shift_pa()
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-11-jason-jh.lin@mediatek.com>

Since the mailbox driver data can be obtained using cmdq_get_mbox_priv()
and all CMDQ users have transitioned to cmdq_get_mbox_priv(),
cmdq_get_shift_pa() can be removed.

Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform")
Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c       |  8 --------
 include/linux/mailbox/mtk-cmdq-mailbox.h | 12 ------------
 2 files changed, 20 deletions(-)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index db72dcd9b8b6..b18808855680 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -110,14 +110,6 @@ void cmdq_get_mbox_priv(struct mbox_chan *chan, struct cmdq_mbox_priv *priv)
 }
 EXPORT_SYMBOL(cmdq_get_mbox_priv);
 
-u8 cmdq_get_shift_pa(struct mbox_chan *chan)
-{
-	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
-
-	return cmdq->pdata->shift;
-}
-EXPORT_SYMBOL(cmdq_get_shift_pa);
-
 static void cmdq_gctl_value_toggle(struct cmdq *cmdq, bool ddr_enable)
 {
 	u32 val = cmdq->pdata->control_by_sw ? GCE_CTRL_BY_SW : 0;
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index 73b70be4a8a7..822958f92135 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -95,16 +95,4 @@ struct cmdq_pkt {
  */
 void cmdq_get_mbox_priv(struct mbox_chan *chan, struct cmdq_mbox_priv *priv);
 
-/**
- * cmdq_get_shift_pa() - get the shift bits of physical address
- * @chan: mailbox channel
- *
- * GCE can only fetch the command buffer address from a 32-bit register.
- * Some SOCs support more than 32-bit command buffer address for GCE, which
- * requires some shift bits to make the address fit into the 32-bit register.
- *
- * Return: the shift bits of physical address
- */
-u8 cmdq_get_shift_pa(struct mbox_chan *chan);
-
 #endif /* __MTK_CMDQ_MAILBOX_H__ */
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:39 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:39 +0800
Subject: [PATCH RESEND v5 17/20] soc: mediatek: Add programming flow for unsupported subsys ID hardware
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-18-jason-jh.lin@mediatek.com>

To support hardware without subsys IDs on new SoCs, add a programming
flow that checks whether the subsys ID is valid.

If the subsys ID is valid, the flow will call cmdq_pkt_write_subsys()
and cmdq_pkt_write_mask_subsys() instead of the original
cmdq_pkt_write() and cmdq_pkt_write_mask().

If the subsys ID is invalid, the flow will call cmdq_pkt_write_pa() and
cmdq_pkt_write_mask_pa() to achieve the same functionality.

Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/soc/mediatek/mtk-mmsys.c | 12 +++++++++---
 drivers/soc/mediatek/mtk-mutex.c |  8 ++++++--
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index bb4639ca0b8c..0c324846e334 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -167,9 +167,15 @@ static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask,
 	u32 tmp;
 
 	if (mmsys->cmdq_base.size && cmdq_pkt) {
-		ret = cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
-					  mmsys->cmdq_base.offset + offset, val,
-					  mask);
+		offset += mmsys->cmdq_base.offset;
+		if (mmsys->cmdq_base.subsys != CMDQ_SUBSYS_INVALID)
+			ret = cmdq_pkt_write_mask_subsys(cmdq_pkt, mmsys->cmdq_base.subsys,
+							 mmsys->cmdq_base.pa_base, offset,
+							 val, mask);
+		else /* only MMIO access, no need to check mminfro_offset */
+			ret = cmdq_pkt_write_mask_pa(cmdq_pkt, mmsys->cmdq_base.subsys,
+						     mmsys->cmdq_base.pa_base, offset, val, mask);
+
 		if (ret)
 			pr_debug("CMDQ unavailable: using CPU write\n");
 		else
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index aaa965d4b050..ce444c1998f0 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -969,6 +969,7 @@ int mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex, void *pkt)
 	struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
 						 mutex[mutex->id]);
 	struct cmdq_pkt *cmdq_pkt = (struct cmdq_pkt *)pkt;
+	dma_addr_t en_addr = mtx->addr + DISP_REG_MUTEX_EN(mutex->id);
 
 	WARN_ON(&mtx->mutex[mutex->id] != mutex);
 
@@ -977,8 +978,11 @@ int mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex, void *pkt)
 		return -ENODEV;
 	}
 
-	cmdq_pkt_write(cmdq_pkt, mtx->cmdq_reg.subsys,
-		       mtx->addr + DISP_REG_MUTEX_EN(mutex->id), 1);
+	if (mtx->cmdq_reg.subsys != CMDQ_SUBSYS_INVALID)
+		cmdq_pkt_write_subsys(cmdq_pkt, mtx->cmdq_reg.subsys, en_addr, en_addr, 1);
+	else /* only MMIO access, no need to check mminfro_offset */
+		cmdq_pkt_write_pa(cmdq_pkt, mtx->cmdq_reg.subsys, en_addr, en_addr, 1);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:41 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:41 +0800
Subject: [PATCH RESEND v5 19/20] media: mediatek: mdp3: Add programming flow for unsupported subsys ID hardware
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-20-jason-jh.lin@mediatek.com>

To support hardware without subsys IDs on new SoCs, add a programming
flow that checks whether the subsys ID is valid.

If the subsys ID is valid, the flow will call cmdq_pkt_write_subsys()
and cmdq_pkt_write_mask_subsys() instead of the original
cmdq_pkt_write() and cmdq_pkt_write_mask().

If the subsys ID is invalid, the flow will call cmdq_pkt_write_pa() and
cmdq_pkt_write_mask_pa() to achieve the same functionality.

Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c    | 14 +++-
 .../platform/mediatek/mdp3/mtk-mdp3-comp.h    | 70 ++++++++++++++-----
 2 files changed, 64 insertions(+), 20 deletions(-)

diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
index c4e0d376a055..c35fe0e3a4d5 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
@@ -321,7 +321,12 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd,
 	/* Enable mux settings */
 	for (index = 0; index < ctrl->num_sets; index++) {
 		set = &ctrl->sets[index];
-		cmdq_pkt_write(&cmd->pkt, set->subsys_id, set->reg, set->value);
+		if (set->subsys_id != CMDQ_SUBSYS_INVALID)
+			cmdq_pkt_write_subsys(&cmd->pkt, set->subsys_id, set->reg,
+					      set->reg, set->value);
+		else /* only MMIO access, no need to check mminfro_offset */
+			cmdq_pkt_write_pa(&cmd->pkt, set->subsys_id, set->reg,
+					  set->reg, set->value);
 	}
 	/* Config sub-frame information */
 	for (index = (num_comp - 1); index >= 0; index--) {
@@ -376,7 +381,12 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd,
 	/* Disable mux settings */
 	for (index = 0; index < ctrl->num_sets; index++) {
 		set = &ctrl->sets[index];
-		cmdq_pkt_write(&cmd->pkt, set->subsys_id, set->reg, 0);
+		if (set->subsys_id != CMDQ_SUBSYS_INVALID)
+			cmdq_pkt_write_subsys(&cmd->pkt, set->subsys_id, set->reg,
+					      set->reg, 0);
+		else /* only MMIO access, no need to check mminfro_offset */
+			cmdq_pkt_write_pa(&cmd->pkt, set->subsys_id, set->reg,
+					  set->reg, 0);
 	}
 
 	return 0;
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
index 681906c16419..ea65a988a26b 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
@@ -9,17 +9,35 @@
 
 #include "mtk-mdp3-cmdq.h"
 
-#define MM_REG_WRITE_MASK(cmd, id, base, ofst, val, mask)	\
-do {								\
-	typeof(mask) (m) = (mask);				\
-	cmdq_pkt_write_mask(&((cmd)->pkt), id, (base) + (ofst),	\
-			    (val),				\
-		(((m) & (ofst##_MASK)) == (ofst##_MASK)) ?	\
-			(0xffffffff) : (m));			\
+#define MM_REG_WRITE_MASK(cmd, id, base, ofst, val, mask)		\
+do {									\
+	typeof(cmd) (_c) = (cmd);					\
+	typeof(id) (_i) = (id);						\
+	typeof(base) (_b) = (base);					\
+	typeof(ofst) (_o) = (ofst);					\
+	typeof(val) (_v) = (val);					\
+	typeof(mask) (_m) = (mask);					\
+	_m = ((_m & (ofst##_MASK)) == (ofst##_MASK)) ? 0xffffffff : _m;	\
+	if (_i != CMDQ_SUBSYS_INVALID)					\
+		cmdq_pkt_write_mask_subsys(&_c->pkt, _i, _b, _b + _o,	\
+					   _v, _m);			\
+	else /* only MMIO access, no need to check mminfro_offset */	\
+		cmdq_pkt_write_mask_pa(&_c->pkt, _i, _b, _b + _o,	\
+				       _v, _m);				\
 } while (0)
 
-#define MM_REG_WRITE(cmd, id, base, ofst, val)			\
-	cmdq_pkt_write(&((cmd)->pkt), id, (base) + (ofst), (val))
+#define MM_REG_WRITE(cmd, id, base, ofst, val)				\
+do {									\
+	typeof(cmd) (_c) = (cmd);					\
+	typeof(id) (_i) = (id);						\
+	typeof(base) (_b) = (base);					\
+	typeof(ofst) (_o) = (ofst);					\
+	typeof(val) (_v) = (val);					\
+	if (_i != CMDQ_SUBSYS_INVALID)					\
+		cmdq_pkt_write_subsys(&_c->pkt, _i, _b, _b + _o, _v);	\
+	else /* only MMIO access, no need to check mminfro_offset */	\
+		cmdq_pkt_write_pa(&_c->pkt, _i, _b, _b + _o, _v);	\
+} while (0)
 
 #define MM_REG_WAIT(cmd, evt)					\
 do {								\
@@ -49,17 +67,33 @@ do {								\
 	cmdq_pkt_set_event(&((c)->pkt), (e));			\
 } while (0)
 
-#define MM_REG_POLL_MASK(cmd, id, base, ofst, val, _mask)	\
-do {								\
-	typeof(_mask) (_m) = (_mask);				\
-	cmdq_pkt_poll_mask(&((cmd)->pkt), id,			\
-		(base) + (ofst), (val),				\
-		(((_m) & (ofst##_MASK)) == (ofst##_MASK)) ?	\
-			(0xffffffff) : (_m));			\
+#define MM_REG_POLL_MASK(cmd, id, base, ofst, val, mask)		\
+do {									\
+	typeof(cmd) (_c) = (cmd);					\
+	typeof(id) (_i) = (id);						\
+	typeof(base) (_b) = (base);					\
+	typeof(ofst) (_o) = (ofst);					\
+	typeof(val) (_v) = (val);					\
+	typeof(mask) (_m) = (mask);					\
+	_m = ((_m & (ofst##_MASK)) == (ofst##_MASK)) ? 0xffffffff : _m;	\
+	if (_i != CMDQ_SUBSYS_INVALID)					\
+		cmdq_pkt_poll_mask(&_c->pkt, _i, _b + _o, _v, _m);	\
+	else /* POLL not support SPR, so use cmdq_pkt_poll_addr() */	\
+		cmdq_pkt_poll_addr(&_c->pkt, _b + _o, _v, _m);		\
 } while (0)
 
-#define MM_REG_POLL(cmd, id, base, ofst, val)			\
-	cmdq_pkt_poll(&((cmd)->pkt), id, (base) + (ofst), (val))
+#define MM_REG_POLL(cmd, id, base, ofst, val)				\
+do {									\
+	typeof(cmd) (_c) = (cmd);					\
+	typeof(id) (_i) = (id);						\
+	typeof(base) (_b) = (base);					\
+	typeof(ofst) (_o) = (ofst);					\
+	typeof(val) (_v) = (val);					\
+	if (_i != CMDQ_SUBSYS_INVALID)					\
+		cmdq_pkt_poll(&_c->pkt, _i, _b + _o, _v);		\
+	else /* POLL not support SPR, so use cmdq_pkt_poll_addr() */	\
+		cmdq_pkt_poll_addr(&_c->pkt, _b + _o, _v, 0xffffffff);	\
+} while (0)
 
 enum mtk_mdp_comp_id {
 	MDP_COMP_NONE = -1,	/* Invalid engine */
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:24 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:24 +0800
Subject: [PATCH RESEND v5 02/20] mailbox: mtk-cmdq: Refine DMA address handling for the command buffer
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-3-jason-jh.lin@mediatek.com>

GCE can only fetch the command buffer address from a 32-bit register.
Some SoCs support a 35-bit command buffer address for GCE, which
requires a right shift of 3 bits before setting the address into
the 32-bit register. A comment has been added to the header of
cmdq_get_shift_pa() to explain this requirement.

To prevent the GCE command buffer address from being DMA mapped beyond
its supported bit range, the DMA bit mask for the device is set during
initialization.

Additionally, to ensure the correct shift is applied when setting or
reading the register that stores the GCE command buffer address,
new APIs, cmdq_reg_shift_addr() and cmdq_reg_revert_addr(), have been
introduced for consistent operations on this register.

The variable type for the command buffer address has been standardized
to dma_addr_t to prevent handling issues caused by type mismatches.

Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform")
Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c       | 43 ++++++++++++++++--------
 include/linux/mailbox/mtk-cmdq-mailbox.h | 10 ++++++
 2 files changed, 39 insertions(+), 14 deletions(-)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index ab4e8d1954a1..a3d94f1eb1a3 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -92,6 +92,16 @@ struct gce_plat {
 	u32 gce_num;
 };
 
+static inline u32 cmdq_reg_shift_addr(dma_addr_t addr, const struct gce_plat *pdata)
+{
+	return (addr >> pdata->shift);
+}
+
+static inline dma_addr_t cmdq_reg_revert_addr(u32 addr, const struct gce_plat *pdata)
+{
+	return ((dma_addr_t)addr << pdata->shift);
+}
+
 u8 cmdq_get_shift_pa(struct mbox_chan *chan)
 {
 	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
@@ -188,13 +198,12 @@ static void cmdq_task_insert_into_thread(struct cmdq_task *task)
 	struct cmdq_task *prev_task = list_last_entry(
 			&thread->task_busy_list, typeof(*task), list_entry);
 	u64 *prev_task_base = prev_task->pkt->va_base;
+	u32 shift_addr = cmdq_reg_shift_addr(task->pa_base, task->cmdq->pdata);
 
 	/* let previous task jump to this task */
 	dma_sync_single_for_cpu(dev, prev_task->pa_base,
 				prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
-	prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
-		(u64)CMDQ_JUMP_BY_PA << 32 |
-		(task->pa_base >> task->cmdq->pdata->shift);
+	prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] = (u64)CMDQ_JUMP_BY_PA << 32 | shift_addr;
 	dma_sync_single_for_device(dev, prev_task->pa_base,
 				   prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
 
@@ -237,7 +246,8 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq,
 				    struct cmdq_thread *thread)
 {
 	struct cmdq_task *task, *tmp, *curr_task = NULL;
-	u32 curr_pa, irq_flag, task_end_pa;
+	u32 irq_flag, shift_addr;
+	dma_addr_t curr_pa, task_end_pa;
 	bool err;
 
 	irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS);
@@ -259,7 +269,8 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq,
 	else
 		return;
 
-	curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->pdata->shift;
+	shift_addr = readl(thread->base + CMDQ_THR_CURR_ADDR);
+	curr_pa = cmdq_reg_revert_addr(shift_addr, cmdq->pdata);
 
 	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
 				 list_entry) {
@@ -378,7 +389,8 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
 	struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
 	struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
 	struct cmdq_task *task;
-	unsigned long curr_pa, end_pa;
+	u32 shift_addr;
+	dma_addr_t curr_pa, end_pa;
 	int ret;
 
 	/* Client should not flush new tasks if suspended. */
@@ -409,20 +421,20 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
 		 */
 		WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
 
-		writel(task->pa_base >> cmdq->pdata->shift,
-		       thread->base + CMDQ_THR_CURR_ADDR);
-		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->pdata->shift,
-		       thread->base + CMDQ_THR_END_ADDR);
+		shift_addr = cmdq_reg_shift_addr(task->pa_base, cmdq->pdata);
+		writel(shift_addr, thread->base + CMDQ_THR_CURR_ADDR);
+		shift_addr = cmdq_reg_shift_addr(task->pa_base + pkt->cmd_buf_size, cmdq->pdata);
+		writel(shift_addr, thread->base + CMDQ_THR_END_ADDR);
 
 		writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
 		writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
 		writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
 	} else {
 		WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
-		curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
-			cmdq->pdata->shift;
-		end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
-			cmdq->pdata->shift;
+		shift_addr = readl(thread->base + CMDQ_THR_CURR_ADDR);
+		curr_pa = cmdq_reg_revert_addr(shift_addr, cmdq->pdata);
+		shift_addr = readl(thread->base + CMDQ_THR_END_ADDR);
+		end_pa = cmdq_reg_revert_addr(shift_addr, cmdq->pdata);
 		/* check boundary */
 		if (curr_pa == end_pa - CMDQ_INST_SIZE ||
 		    curr_pa == end_pa) {
@@ -656,6 +668,9 @@ static int cmdq_probe(struct platform_device *pdev)
 	if (err)
 		return err;
 
+	dma_set_coherent_mask(dev,
+			      DMA_BIT_MASK(sizeof(u32) * BITS_PER_BYTE + cmdq->pdata->shift));
+
 	cmdq->mbox.dev = dev;
 	cmdq->mbox.chans = devm_kcalloc(dev, cmdq->pdata->thread_nr,
 					sizeof(*cmdq->mbox.chans), GFP_KERNEL);
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index 4c1a91b07de3..e1555e06e7e5 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -77,6 +77,16 @@ struct cmdq_pkt {
 	size_t			buf_size; /* real buffer size */
 };
 
+/**
+ * cmdq_get_shift_pa() - get the shift bits of physical address
+ * @chan: mailbox channel
+ *
+ * GCE can only fetch the command buffer address from a 32-bit register.
+ * Some SOCs support more than 32-bit command buffer address for GCE, which
+ * requires some shift bits to make the address fit into the 32-bit register.
+ *
+ * Return: the shift bits of physical address
+ */
 u8 cmdq_get_shift_pa(struct mbox_chan *chan);
 
 #endif /* __MTK_CMDQ_MAILBOX_H__ */
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:31 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:31 +0800
Subject: [PATCH RESEND v5 09/20] soc: mediatek: mtk-cmdq: Remove cmdq_pkt_jump() and cmdq_pkt_jump_rel_temp()
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-10-jason-jh.lin@mediatek.com>

Since all users have migrated to the new cmdq_pkt_jump* APIs without
shift_pa, the wrapper APIs cmdq_pkt_jump() and cmdq_pkt_jump_rel_temp()
can be removed.

Fixes: ade176534112 ("soc: mediatek: cmdq: Add parameter shift_pa to cmdq_pkt_jump()")
Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 include/linux/soc/mediatek/mtk-cmdq.h | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index ee4ec64a7322..f956ee9a0b34 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -355,12 +355,6 @@ int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u32 mas
  */
 int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr);
 
-/* This wrapper has to be removed after all users migrated to jump_abs */
-static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr)
-{
-	return cmdq_pkt_jump_abs(pkt, addr);
-}
-
 /**
  * cmdq_pkt_jump_rel() - Append jump command to the CMDQ packet, ask GCE
  *			 to execute an instruction that change current thread
@@ -373,12 +367,6 @@ static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr)
  */
 int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset);
 
-/* This wrapper has to be removed after all users migrated to jump_rel */
-static int cmdq_pkt_jump_rel_temp(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa)
-{
-	return cmdq_pkt_jump_rel(pkt, addr);
-}
-
 /**
  * cmdq_pkt_eoc() - Append EOC and ask GCE to generate an IRQ at end of execution
  * @pkt:	The CMDQ packet
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:28 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:28 +0800
Subject: [PATCH RESEND v5 06/20] media: platform: mtk-mdp3: Change cmdq_pkt_jump_rel() to cmdq_pkt_jump_rel_temp()
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-7-jason-jh.lin@mediatek.com>

To facilitate the removal of the shift_pa parameter from
cmdq_pkt_jump_rel(), current users of cmdq_pkt_jump_rel() need to
transition to using cmdq_pkt_jump_rel_temp() before the API change
is implemented.

Fixes: ade176534112 ("soc: mediatek: cmdq: Add parameter shift_pa to cmdq_pkt_jump()")
Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
index e5ccf673e152..aa245bf7e7c4 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
@@ -628,7 +628,7 @@ static struct mdp_cmdq_cmd *mdp_cmdq_prepare(struct mdp_dev *mdp,
 		goto err_free_path;
 	}
 	cmdq_pkt_eoc(&cmd->pkt);
-	cmdq_pkt_jump_rel(&cmd->pkt, CMDQ_INST_SIZE, mdp->cmdq_shift_pa[pp_idx]);
+	cmdq_pkt_jump_rel_temp(&cmd->pkt, CMDQ_INST_SIZE, mdp->cmdq_shift_pa[pp_idx]);
 
 	for (i = 0; i < num_comp; i++) {
 		s32 inner_id = MDP_COMP_NONE;
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:26 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:26 +0800
Subject: [PATCH RESEND v5 04/20] soc: mediatek: mtk-cmdq: Add cmdq_get_mbox_priv() in cmdq_pkt_create()
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-5-jason-jh.lin@mediatek.com>

Add cmdq_get_mbox_priv() in cmdq_pkt_create() to ensure getting private
data before generating GCE instructions.

Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform")
Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/soc/mediatek/mtk-cmdq-helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index 455221e8de24..8feeaa320359 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -140,6 +140,7 @@ int cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, size_t siz
 	}
 
 	pkt->pa_base = dma_addr;
+	cmdq_get_mbox_priv(client->chan, &pkt->priv);
 
 	return 0;
 }
-- 
2.43.0



From jason-jh.lin at mediatek.com  Mon May 12 02:19:42 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Mon, 12 May 2025 17:19:42 +0800
Subject: [PATCH RESEND v5 20/20] soc: mediatek: mtk-cmdq: Remove cmdq_pkt_write() and cmdq_pkt_write_mask()
In-Reply-To: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
References: <20250512092252.905629-1-jason-jh.lin@mediatek.com>
Message-ID: <20250512092252.905629-21-jason-jh.lin@mediatek.com>

The original cmdq_pkt_write() and cmdq_pkt_write_mask() only supported
generating GCE instructions with subsys ID. They have been replaced by
cmdq_pkt_write_pa(), cmdq_pkt_write_subsys(), cmdq_pkt_write_mask_pa()
and cmdq_pkt_write_mask_subsys().

These 2 functions can now be removed as they are no longer in use.

Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/soc/mediatek/mtk-cmdq-helper.c | 49 ++++++++++----------------
 include/linux/soc/mediatek/mtk-cmdq.h  | 35 ------------------
 2 files changed, 18 insertions(+), 66 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index 0a718ffa5f3b..5822a3d13bda 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -201,18 +201,6 @@ static int cmdq_pkt_mask(struct cmdq_pkt *pkt, u32 mask)
 	return cmdq_pkt_append_command(pkt, inst);
 }
 
-int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
-{
-	struct cmdq_instruction inst = {
-		.op = CMDQ_CODE_WRITE,
-		.value = value,
-		.offset = offset,
-		.subsys = subsys
-	};
-	return cmdq_pkt_append_command(pkt, inst);
-}
-EXPORT_SYMBOL(cmdq_pkt_write);
-
 int cmdq_pkt_write_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/, u32 pa_base,
 		      u16 offset, u32 value)
 {
@@ -229,27 +217,16 @@ EXPORT_SYMBOL(cmdq_pkt_write_pa);
 int cmdq_pkt_write_subsys(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base /*unused*/,
 			  u16 offset, u32 value)
 {
-	return cmdq_pkt_write(pkt, subsys, offset, value);
+	struct cmdq_instruction inst = {
+		.op = CMDQ_CODE_WRITE,
+		.value = value,
+		.offset = offset,
+		.subsys = subsys
+	};
+	return cmdq_pkt_append_command(pkt, inst);
 }
 EXPORT_SYMBOL(cmdq_pkt_write_subsys);
 
-int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
-			u16 offset, u32 value, u32 mask)
-{
-	u16 offset_mask = offset;
-	int err;
-
-	if (mask != GENMASK(31, 0)) {
-		err = cmdq_pkt_mask(pkt, mask);
-		if (err < 0)
-			return err;
-
-		offset_mask |= CMDQ_WRITE_ENABLE_MASK;
-	}
-	return cmdq_pkt_write(pkt, subsys, offset_mask, value);
-}
-EXPORT_SYMBOL(cmdq_pkt_write_mask);
-
 int cmdq_pkt_write_mask_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/, u32 pa_base,
 			   u16 offset, u32 value, u32 mask)
 {
@@ -267,7 +244,17 @@ EXPORT_SYMBOL(cmdq_pkt_write_mask_pa);
 int cmdq_pkt_write_mask_subsys(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base /*unused*/,
 			       u16 offset, u32 value, u32 mask)
 {
-	return cmdq_pkt_write_mask(pkt, subsys, offset, value, mask);
+	u16 offset_mask = offset;
+	int err;
+
+	if (mask != GENMASK(31, 0)) {
+		err = cmdq_pkt_mask(pkt, mask);
+		if (err < 0)
+			return err;
+
+		offset_mask |= CMDQ_WRITE_ENABLE_MASK;
+	}
+	return cmdq_pkt_write_subsys(pkt, subsys, pa_base, offset_mask, value);
 }
 EXPORT_SYMBOL(cmdq_pkt_write_mask_subsys);
 
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 4a2acceb8581..f4663fbfb5a0 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -113,17 +113,6 @@ int cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, size_t siz
  */
 void cmdq_pkt_destroy(struct cmdq_client *client, struct cmdq_pkt *pkt);
 
-/**
- * cmdq_pkt_write() - append write command to the CMDQ packet
- * @pkt:	the CMDQ packet
- * @subsys:	the CMDQ sub system code
- * @offset:	register offset from CMDQ sub system
- * @value:	the specified target register value
- *
- * Return: 0 for success; else the error code is returned
- */
-int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);
-
 /**
  * cmdq_pkt_write_pa() - append write command to the CMDQ packet with pa_base
  * @pkt:	the CMDQ packet
@@ -150,19 +139,6 @@ int cmdq_pkt_write_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,
 int cmdq_pkt_write_subsys(struct cmdq_pkt *pkt, u8 subsys,
 			  u32 pa_base /*unused*/, u16 offset, u32 value);
 
-/**
- * cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet
- * @pkt:	the CMDQ packet
- * @subsys:	the CMDQ sub system code
- * @offset:	register offset from CMDQ sub system
- * @value:	the specified target register value
- * @mask:	the specified target register mask
- *
- * Return: 0 for success; else the error code is returned
- */
-int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
-			u16 offset, u32 value, u32 mask);
-
 /**
  * cmdq_pkt_write_mask_pa() - append write command with mask to the CMDQ packet with pa
  * @pkt:	the CMDQ packet
@@ -460,11 +436,6 @@ static inline int cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *p
 
 static inline void cmdq_pkt_destroy(struct cmdq_client *client, struct cmdq_pkt *pkt) { }
 
-static inline int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
-{
-	return -ENOENT;
-}
-
 static inline int cmdq_pkt_write_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,
 				    u32 pa_base, u16 offset, u32 value)
 {
@@ -477,12 +448,6 @@ static inline int cmdq_pkt_write_subsys(struct cmdq_pkt *pkt, u8 subsys,
 	return -ENOENT;
 }
 
-static inline int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
-				      u16 offset, u32 value, u32 mask)
-{
-	return -ENOENT;
-}
-
 static inline int cmdq_pkt_write_mask_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,
 					 u32 pa_base, u16 offset, u32 value, u32 mask)
 {
-- 
2.43.0



From ansuelsmth at gmail.com  Mon May 12 02:27:14 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Mon, 12 May 2025 11:27:14 +0200
Subject: [net-next PATCH v4 11/11] net: airoha: add phylink support for
 GDM2/3/4
In-Reply-To: <aCG9q6i7HomgilI6@lore-desk>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-12-ansuelsmth@gmail.com>
 <aCG9q6i7HomgilI6@lore-desk>
Message-ID: <6821bef5.5d0a0220.319347.d533@mx.google.com>

On Mon, May 12, 2025 at 11:21:47AM +0200, Lorenzo Bianconi wrote:
> > Add phylink support for GDM2/3/4 port that require configuration of the
> > PCS to make the external PHY or attached SFP cage work.
> > 
> > These needs to be defined in the GDM port node using the pcs-handle
> > property.
> > 
> > Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> > ---
> >  drivers/net/ethernet/airoha/airoha_eth.c  | 155 +++++++++++++++++++++-
> >  drivers/net/ethernet/airoha/airoha_eth.h  |   3 +
> >  drivers/net/ethernet/airoha/airoha_regs.h |  12 ++
> >  3 files changed, 169 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> > index 16c7896f931f..3be1ae077a76 100644
> > --- a/drivers/net/ethernet/airoha/airoha_eth.c
> > +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> > @@ -7,6 +7,7 @@
> >  #include <linux/of_net.h>
> >  #include <linux/platform_device.h>
> >  #include <linux/tcp.h>
> > +#include <linux/pcs/pcs.h>
> >  #include <linux/u64_stats_sync.h>
> >  #include <net/dst_metadata.h>
> >  #include <net/page_pool/helpers.h>
> > @@ -79,6 +80,11 @@ static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
> >  	return port->id == 1;
> >  }
> >  
> > +static bool airhoa_is_phy_external(struct airoha_gdm_port *port)
> > +{
> > +	return port->id != 1;
> > +}
> > +
> >  static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
> >  {
> >  	struct airoha_eth *eth = port->qdma->eth;
> > @@ -1613,6 +1619,17 @@ static int airoha_dev_open(struct net_device *dev)
> >  	struct airoha_gdm_port *port = netdev_priv(dev);
> >  	struct airoha_qdma *qdma = port->qdma;
> >  
> > +	if (airhoa_is_phy_external(port)) {
> > +		err = phylink_of_phy_connect(port->phylink, dev->dev.of_node, 0);
> 
> nit: even if it is not strictly required, in order to align with the rest of the
> codebase, can you please stay below 79 columns?
> 
> > +		if (err) {
> > +			netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
> > +				   err);
> 
> same here
> 
> > +			return err;
> > +		}
> > +
> > +		phylink_start(port->phylink);
> > +	}
> > +
> >  	netif_tx_start_all_queues(dev);
> >  	err = airoha_set_vip_for_gdm_port(port, true);
> >  	if (err)
> > @@ -1665,6 +1682,11 @@ static int airoha_dev_stop(struct net_device *dev)
> >  		}
> >  	}
> >  
> > +	if (airhoa_is_phy_external(port)) {
> > +		phylink_stop(port->phylink);
> > +		phylink_disconnect_phy(port->phylink);
> > +	}
> > +
> >  	return 0;
> >  }
> >  
> > @@ -2795,6 +2817,115 @@ bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
> >  	return false;
> >  }
> >  
> > +static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,
> > +			       unsigned int mode, phy_interface_t interface,
> > +			       int speed, int duplex, bool tx_pause, bool rx_pause)
> 
> ditto.
> 
> > +{
> > +	struct airoha_gdm_port *port = container_of(config, struct airoha_gdm_port,
> > +						    phylink_config);
> 
> ditto.
> 
> > +	struct airoha_qdma *qdma = port->qdma;
> > +	struct airoha_eth *eth = qdma->eth;
> > +	u32 frag_size_tx, frag_size_rx;
> > +
> > +	if (port->id != 4)
> > +		return;
> > +
> > +	switch (speed) {
> > +	case SPEED_10000:
> > +	case SPEED_5000:
> > +		frag_size_tx = 8;
> > +		frag_size_rx = 8;
> > +		break;
> > +	case SPEED_2500:
> > +		frag_size_tx = 2;
> > +		frag_size_rx = 1;
> > +		break;
> > +	default:
> > +		frag_size_tx = 1;
> > +		frag_size_rx = 0;
> > +	}
> > +
> > +	/* Configure TX/RX frag based on speed */
> > +	airoha_fe_rmw(eth, REG_GDMA4_TMBI_FRAG,
> > +		      GDMA4_SGMII0_TX_FRAG_SIZE_MASK,
> > +		      FIELD_PREP(GDMA4_SGMII0_TX_FRAG_SIZE_MASK,
> > +				 frag_size_tx));
> > +
> > +	airoha_fe_rmw(eth, REG_GDMA4_RMBI_FRAG,
> > +		      GDMA4_SGMII0_RX_FRAG_SIZE_MASK,
> > +		      FIELD_PREP(GDMA4_SGMII0_RX_FRAG_SIZE_MASK,
> > +				 frag_size_rx));
> > +}
> > +
> > +static const struct phylink_mac_ops airoha_phylink_ops = {
> > +	.mac_link_up = airoha_mac_link_up,
> > +};
> > +
> > +static int airoha_setup_phylink(struct net_device *dev)
> > +{
> > +	struct airoha_gdm_port *port = netdev_priv(dev);
> > +	struct device_node *np = dev->dev.of_node;
> > +	struct phylink_pcs **available_pcs;
> > +	phy_interface_t phy_mode;
> > +	struct phylink *phylink;
> > +	unsigned int num_pcs;
> > +	int err;
> > +
> > +	err = of_get_phy_mode(np, &phy_mode);
> > +	if (err) {
> > +		dev_err(&dev->dev, "incorrect phy-mode\n");
> > +		return err;
> > +	}
> > +
> > +	port->phylink_config.dev = &dev->dev;
> > +	port->phylink_config.type = PHYLINK_NETDEV;
> > +	port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
> > +						MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD |
> > +						MAC_5000FD | MAC_10000FD;
> 
> over 79 columns
> 
> > +
> > +	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), NULL, &num_pcs);
> > +	if (err)
> > +		return err;
> > +
> > +	available_pcs = kcalloc(num_pcs, sizeof(*available_pcs), GFP_KERNEL);
> 
> I guess you can use devm_kcalloc() and get rid of kfree() here.
>

I forgot to answer to this in the previous revision. No devm can't be
used there available_pcs is just an array allocated for phylink_config.

Phylink then copy the data in it and doesn't use it anymore hence it
just needs to be allocated here and doesn't need to stay till the driver
gets removed.

> > +	if (!available_pcs)
> > +		return -ENOMEM;
> > +
> > +	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), available_pcs,
> > +				       &num_pcs);
> > +	if (err)
> > +		goto out;
> > +
> > +	port->phylink_config.available_pcs = available_pcs;
> > +	port->phylink_config.num_available_pcs = num_pcs;
> > +
> > +	__set_bit(PHY_INTERFACE_MODE_SGMII,
> > +		  port->phylink_config.supported_interfaces);
> > +	__set_bit(PHY_INTERFACE_MODE_1000BASEX,
> > +		  port->phylink_config.supported_interfaces);
> > +	__set_bit(PHY_INTERFACE_MODE_2500BASEX,
> > +		  port->phylink_config.supported_interfaces);
> > +	__set_bit(PHY_INTERFACE_MODE_USXGMII,
> > +		  port->phylink_config.supported_interfaces);
> > +
> > +	phy_interface_copy(port->phylink_config.pcs_interfaces,
> > +			   port->phylink_config.supported_interfaces);
> > +
> > +	phylink = phylink_create(&port->phylink_config,
> > +				 of_fwnode_handle(np),
> > +				 phy_mode, &airoha_phylink_ops);
> > +	if (IS_ERR(phylink)) {
> > +		err = PTR_ERR(phylink);
> > +		goto out;
> > +	}
> > +
> > +	port->phylink = phylink;
> > +out:
> > +	kfree(available_pcs);
> > +
> > +	return err;
> > +}
> > +
> >  static int airoha_alloc_gdm_port(struct airoha_eth *eth,
> >  				 struct device_node *np, int index)
> >  {
> > @@ -2873,7 +3004,23 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
> >  	if (err)
> >  		return err;
> >  
> > -	return register_netdev(dev);
> > +	if (airhoa_is_phy_external(port)) {
> > +		err = airoha_setup_phylink(dev);
> 
> This will re-introduce the issue reported here:
> https://lore.kernel.org/netdev/5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet at wanadoo.fr/
> 

I'm confused about this. The suggestion wasn't that register_netdev
might fail and I need to destroy phylink? Or the linked patch was merged
and I need to rebase on top of net-next?

I didn't include that change to not cause conflicts but once it's merged
I will rebase and include that fix.

> > +		if (err)
> > +			return err;
> > +	}
> > +
> > +	err = register_netdev(dev);
> > +	if (err)
> > +		goto free_phylink;
> > +
> > +	return 0;
> > +
> > +free_phylink:
> > +	if (airhoa_is_phy_external(port))
> > +		phylink_destroy(port->phylink);
> > +
> > +	return err;
> >  }
> >  
> >  static int airoha_probe(struct platform_device *pdev)
> > @@ -2967,6 +3114,9 @@ static int airoha_probe(struct platform_device *pdev)
> >  		struct airoha_gdm_port *port = eth->ports[i];
> >  
> >  		if (port && port->dev->reg_state == NETREG_REGISTERED) {
> > +			if (airhoa_is_phy_external(port))
> > +				phylink_destroy(port->phylink);
> > +
> >  			unregister_netdev(port->dev);
> >  			airoha_metadata_dst_free(port);
> >  		}
> > @@ -2994,6 +3144,9 @@ static void airoha_remove(struct platform_device *pdev)
> >  			continue;
> >  
> >  		airoha_dev_stop(port->dev);
> > +		if (airhoa_is_phy_external(port))
> > +			phylink_destroy(port->phylink);
> > +
> >  		unregister_netdev(port->dev);
> >  		airoha_metadata_dst_free(port);
> >  	}
> > diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
> > index 53f39083a8b0..73a500474076 100644
> > --- a/drivers/net/ethernet/airoha/airoha_eth.h
> > +++ b/drivers/net/ethernet/airoha/airoha_eth.h
> > @@ -498,6 +498,9 @@ struct airoha_gdm_port {
> >  	struct net_device *dev;
> >  	int id;
> >  
> > +	struct phylink *phylink;
> > +	struct phylink_config phylink_config;
> > +
> >  	struct airoha_hw_stats stats;
> >  
> >  	DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
> > diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
> > index d931530fc96f..54f7079b28b0 100644
> > --- a/drivers/net/ethernet/airoha/airoha_regs.h
> > +++ b/drivers/net/ethernet/airoha/airoha_regs.h
> > @@ -357,6 +357,18 @@
> >  #define IP_FRAGMENT_PORT_MASK		GENMASK(8, 5)
> >  #define IP_FRAGMENT_NBQ_MASK		GENMASK(4, 0)
> >  
> > +#define REG_GDMA4_TMBI_FRAG		0x2028
> > +#define GDMA4_SGMII1_TX_WEIGHT_MASK	GENMASK(31, 26)
> > +#define GDMA4_SGMII1_TX_FRAG_SIZE_MASK	GENMASK(25, 16)
> > +#define GDMA4_SGMII0_TX_WEIGHT_MASK	GENMASK(15, 10)
> > +#define GDMA4_SGMII0_TX_FRAG_SIZE_MASK	GENMASK(9, 0)
> > +
> > +#define REG_GDMA4_RMBI_FRAG		0x202c
> > +#define GDMA4_SGMII1_RX_WEIGHT_MASK	GENMASK(31, 26)
> > +#define GDMA4_SGMII1_RX_FRAG_SIZE_MASK	GENMASK(25, 16)
> > +#define GDMA4_SGMII0_RX_WEIGHT_MASK	GENMASK(15, 10)
> > +#define GDMA4_SGMII0_RX_FRAG_SIZE_MASK	GENMASK(9, 0)
> > +
> >  #define REG_MC_VLAN_EN			0x2100
> >  #define MC_VLAN_EN_MASK			BIT(0)
> >  
> > -- 
> > 2.48.1
> > 



-- 
	Ansuel


From sirius.wang at mediatek.com  Mon May 12 04:53:47 2025
From: sirius.wang at mediatek.com (Sirius Wang)
Date: Mon, 12 May 2025 19:53:47 +0800
Subject: [PATCH v3 0/3] Add mt8189 dts evalution board and Makefile
Message-ID: <20250512115355.923342-1-sirius.wang@mediatek.com>

We add basic chip support for Mediatek MT8189 on evalution board.

In this series, we also add dt-bindings document definition for MT8189.

This series is based on tag: next-20250509

Changs in v3:
 - Move ulposc and ulposc3 before cpu nodes.
 - Refactor cpu-map to a single cluster0.
 - Change cpu nodes name from medium core to big core.
 - Move psci before timer nodes.

Changs in v2:
 - Fix warning issues for make CHECK_DTBS=y
 - Add mediatek,uart.yaml document


Sirius Wang (3):
  dt-bindings: arm: Add compatible for MediaTek MT8189
  dt-bindings: serial: mediatek,uart: Add compatible for MT8189
  arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile

 .../devicetree/bindings/arm/mediatek.yaml     |   4 +
 .../bindings/serial/mediatek,uart.yaml        |   1 +
 arch/arm64/boot/dts/mediatek/Makefile         |   1 +
 arch/arm64/boot/dts/mediatek/mt8189-evb.dts   |  20 +
 arch/arm64/boot/dts/mediatek/mt8189.dtsi      | 427 ++++++++++++++++++
 5 files changed, 453 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi

-- 
2.45.2



From sirius.wang at mediatek.com  Mon May 12 04:53:48 2025
From: sirius.wang at mediatek.com (Sirius Wang)
Date: Mon, 12 May 2025 19:53:48 +0800
Subject: [PATCH v3 1/3] dt-bindings: arm: Add compatible for MediaTek MT8189
In-Reply-To: <20250512115355.923342-1-sirius.wang@mediatek.com>
References: <20250512115355.923342-1-sirius.wang@mediatek.com>
Message-ID: <20250512115355.923342-2-sirius.wang@mediatek.com>

This commit adds dt-binding documentation for the MediaTek MT8189
reference board.

Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
---
 Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index fa1646bc0bac..05e827076a7f 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -372,6 +372,10 @@ properties:
           - enum:
               - mediatek,mt8188-evb
           - const: mediatek,mt8188
+      - items:
+          - enum:
+              - mediatek,mt8189-evb
+          - const: mediatek,mt8189
       - description: Google Hayato
         items:
           - const: google,hayato-rev1
-- 
2.45.2



From sirius.wang at mediatek.com  Mon May 12 04:53:49 2025
From: sirius.wang at mediatek.com (Sirius Wang)
Date: Mon, 12 May 2025 19:53:49 +0800
Subject: [PATCH v3 2/3] dt-bindings: serial: mediatek,uart: Add compatible for MT8189
In-Reply-To: <20250512115355.923342-1-sirius.wang@mediatek.com>
References: <20250512115355.923342-1-sirius.wang@mediatek.com>
Message-ID: <20250512115355.923342-3-sirius.wang@mediatek.com>

Add compatible string for serial on MT8189 SoC.

Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Acked-by: Conor Dooley <conor.dooley at microchip.com>
---
 Documentation/devicetree/bindings/serial/mediatek,uart.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
index c55d9a0efa19..fabc22d47cb3 100644
--- a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
+++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
@@ -46,6 +46,7 @@ properties:
               - mediatek,mt8183-uart
               - mediatek,mt8186-uart
               - mediatek,mt8188-uart
+              - mediatek,mt8189-uart
               - mediatek,mt8192-uart
               - mediatek,mt8195-uart
               - mediatek,mt8365-uart
-- 
2.45.2



From sirius.wang at mediatek.com  Mon May 12 04:53:50 2025
From: sirius.wang at mediatek.com (Sirius Wang)
Date: Mon, 12 May 2025 19:53:50 +0800
Subject: [PATCH v3 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile
In-Reply-To: <20250512115355.923342-1-sirius.wang@mediatek.com>
References: <20250512115355.923342-1-sirius.wang@mediatek.com>
Message-ID: <20250512115355.923342-4-sirius.wang@mediatek.com>

Add mt8189 dts evaluation board and Mafefile

Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>
---
 arch/arm64/boot/dts/mediatek/Makefile       |   1 +
 arch/arm64/boot/dts/mediatek/mt8189-evb.dts |  20 +
 arch/arm64/boot/dts/mediatek/mt8189.dtsi    | 427 ++++++++++++++++++++
 3 files changed, 448 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 3aa06476c6c0..ad2ac9e1bb79 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8189-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
new file mode 100644
index 000000000000..e5d9ce1b8e61
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ * Author: Sirius Wang <sirius.wang at mediatek.com>
+ */
+/dts-v1/;
+#include "mt8189.dtsi"
+
+/ {
+	model = "MediaTek MT8189 evaluation board";
+	compatible = "mediatek,mt8189-evb", "mediatek,mt8189";
+
+	chosen: chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
new file mode 100644
index 000000000000..f8794c6fba7b
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "mediatek,mt8189";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	clk32k: oscillator-clk32k {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32000>;
+		clock-output-names = "clk32k";
+	};
+
+	clk13m: oscillator-clk13m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk26m>;
+		clock-mult = <1>;
+		clock-div = <2>;
+		clock-output-names = "clk13m";
+	};
+
+	clk26m: oscillator-clk26m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+		clock-output-names = "clk26m";
+	};
+
+	clk104m: oscillator-clk104m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk26m>;
+		clock-mult = <4>;
+		clock-div = <1>;
+		clock-output-names = "clk104m";
+	};
+
+	ulposc: oscillator-ulposc {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <520000000>;
+		clock-output-names = "ulposc";
+	};
+
+	ulposc3: oscillator-ulposc3 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+		clock-output-names = "ulposc3";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x000>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu1: cpu at 100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu2: cpu at 200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu3: cpu at 300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu4: cpu at 400 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x400>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu5: cpu at 500 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x500>;
+			enable-method = "psci";
+			clock-frequency = <2000000000>;
+			capacity-dmips-mhz = <742>;
+			cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu6: cpu at 600 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78";
+			reg = <0x600>;
+			enable-method = "psci";
+			clock-frequency = <3000000000>;
+			capacity-dmips-mhz = <958>;
+			cpu-idle-states = <&cpu_off_b>, <&cpu_cluster_off_b>, <&cpu_mcusys_off_b>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <65536>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <65536>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_1>;
+			performance-domains = <&performance 1>;
+			#cooling-cells = <2>;
+		};
+
+		cpu7: cpu at 700 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78";
+			reg = <0x700>;
+			enable-method = "psci";
+			clock-frequency = <3000000000>;
+			capacity-dmips-mhz = <958>;
+			cpu-idle-states = <&cpu_off_b>, <&cpu_cluster_off_b>, <&cpu_mcusys_off_b>,
+					  <&cpu_system_vcore>, <&cpu_s2idle>;
+			i-cache-size = <65536>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <65536>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_1>;
+			performance-domains = <&performance 1>;
+			#cooling-cells = <2>;
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+				core4 {
+					cpu = <&cpu4>;
+				};
+				core5 {
+					cpu = <&cpu5>;
+				};
+				core6 {
+					cpu = <&cpu6>;
+				};
+				core7 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			cpu_off_l: cpu-off-l {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x00010000>;
+				local-timer-stop;
+				entry-latency-us = <97>;
+				exit-latency-us = <252>;
+				min-residency-us = <6710>;
+			};
+
+			cpu_off_b: cpu-off-b {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x00010000>;
+				local-timer-stop;
+				entry-latency-us = <53>;
+				exit-latency-us = <143>;
+				min-residency-us = <2120>;
+			};
+
+			cpu_cluster_off_l: cpu-cluster-off-l {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x01010001>;
+				local-timer-stop;
+				entry-latency-us = <109>;
+				exit-latency-us = <325>;
+				min-residency-us = <6710>;
+			};
+
+			cpu_cluster_off_b: cpu-cluster-off-b {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x01010001>;
+				local-timer-stop;
+				entry-latency-us = <59>;
+				exit-latency-us = <188>;
+				min-residency-us = <2120>;
+			};
+
+			cpu_mcusys_off_l: cpu-mcusys-off-l {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x02010007>;
+				local-timer-stop;
+				entry-latency-us = <1357>;
+				exit-latency-us = <835>;
+				min-residency-us = <6710>;
+			};
+
+			cpu_mcusys_off_b: cpu-mcusys-off-b {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x02010007>;
+				local-timer-stop;
+				entry-latency-us = <1202>;
+				exit-latency-us = <679>;
+				min-residency-us = <2120>;
+			};
+
+			cpu_system_vcore: cpu-system-vcore {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x020100ff>;
+				local-timer-stop;
+				entry-latency-us = <940>;
+				exit-latency-us = <3500>;
+				min-residency-us = <35200>;
+			};
+
+			cpu_s2idle: cpu-s2idle {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x020180ff>;
+				local-timer-stop;
+				entry-latency-us = <10000>;
+				exit-latency-us = <10000>;
+				min-residency-us = <4294967295>;
+			};
+		};
+
+		l2_0: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <131072>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			next-level-cache = <&l3_0>;
+			cache-unified;
+		};
+
+		l2_1: l2-cache1 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <262144>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			next-level-cache = <&l3_0>;
+			cache-unified;
+		};
+
+		l3_0: l3-cache {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-size = <1048576>;
+			cache-line-size = <64>;
+			cache-sets = <2048>;
+			cache-unified;
+		};
+	};
+
+	memory: memory at 40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0xC0000000>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+
+		performance: performance-controller at 11bc10 {
+			compatible = "mediatek,cpufreq-hw";
+			reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+			#performance-domain-cells = <1>;
+		};
+
+		gic: interrupt-controller at c000000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <4>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			reg = <0 0xc000000 0 0x40000>, /* distributor */
+			      <0 0xc040000 0 0x200000>; /* redistributor */
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+			ppi-partitions {
+				ppi_cluster0: interrupt-partition-0 {
+					affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
+				};
+
+				ppi_cluster1: interrupt-partition-1 {
+					affinity = <&cpu6 &cpu7>;
+				};
+			};
+		};
+
+		uart0: serial at 11001000 {
+			compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart";
+			reg = <0 0x11001000 0 0x1000>;
+			interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&clk26m>, <&clk26m>;
+			clock-names = "baud", "bus";
+			status = "disabled";
+		};
+	};
+};
-- 
2.45.2



From lorenzo at kernel.org  Mon May 12 05:53:18 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Mon, 12 May 2025 14:53:18 +0200
Subject: [net-next PATCH v4 11/11] net: airoha: add phylink support for
 GDM2/3/4
In-Reply-To: <6821bef5.5d0a0220.319347.d533@mx.google.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-12-ansuelsmth@gmail.com>
 <aCG9q6i7HomgilI6@lore-desk>
 <6821bef5.5d0a0220.319347.d533@mx.google.com>
Message-ID: <aCHvPoZDGUrCVif1@lore-desk>

[...]
> > 
> > I guess you can use devm_kcalloc() and get rid of kfree() here.
> >
> 
> I forgot to answer to this in the previous revision. No devm can't be
> used there available_pcs is just an array allocated for phylink_config.
> 
> Phylink then copy the data in it and doesn't use it anymore hence it
> just needs to be allocated here and doesn't need to stay till the driver
> gets removed.

I guess this is exactly the point. Since available_pcs is used just here and
this is not a hot-path, I think the code would be simpler, but I do not have
a strong opinion about it.

> 
> > > +	if (!available_pcs)
> > > +		return -ENOMEM;
> > > +
> > > +	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), available_pcs,
> > > +				       &num_pcs);
> > > +	if (err)
> > > +		goto out;
> > > +
> > > +	port->phylink_config.available_pcs = available_pcs;
> > > +	port->phylink_config.num_available_pcs = num_pcs;
> > > +
> > > +	__set_bit(PHY_INTERFACE_MODE_SGMII,
> > > +		  port->phylink_config.supported_interfaces);
> > > +	__set_bit(PHY_INTERFACE_MODE_1000BASEX,
> > > +		  port->phylink_config.supported_interfaces);
> > > +	__set_bit(PHY_INTERFACE_MODE_2500BASEX,
> > > +		  port->phylink_config.supported_interfaces);
> > > +	__set_bit(PHY_INTERFACE_MODE_USXGMII,
> > > +		  port->phylink_config.supported_interfaces);
> > > +
> > > +	phy_interface_copy(port->phylink_config.pcs_interfaces,
> > > +			   port->phylink_config.supported_interfaces);
> > > +
> > > +	phylink = phylink_create(&port->phylink_config,
> > > +				 of_fwnode_handle(np),
> > > +				 phy_mode, &airoha_phylink_ops);
> > > +	if (IS_ERR(phylink)) {
> > > +		err = PTR_ERR(phylink);
> > > +		goto out;
> > > +	}
> > > +
> > > +	port->phylink = phylink;
> > > +out:
> > > +	kfree(available_pcs);
> > > +
> > > +	return err;
> > > +}
> > > +
> > >  static int airoha_alloc_gdm_port(struct airoha_eth *eth,
> > >  				 struct device_node *np, int index)
> > >  {
> > > @@ -2873,7 +3004,23 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
> > >  	if (err)
> > >  		return err;
> > >  
> > > -	return register_netdev(dev);
> > > +	if (airhoa_is_phy_external(port)) {
> > > +		err = airoha_setup_phylink(dev);
> > 
> > This will re-introduce the issue reported here:
> > https://lore.kernel.org/netdev/5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet at wanadoo.fr/
> > 
> 
> I'm confused about this. The suggestion wasn't that register_netdev
> might fail and I need to destroy phylink? Or the linked patch was merged
> and I need to rebase on top of net-next?

what I mean here is if register_netdev() or airoha_setup_phylink() fails, we
should free metadata_dst running airoha_metadata_dst_free() as pointed out by
Christophe. I think this path depends on Christophe's one.

Regards,
Lorenzo

> 
> I didn't include that change to not cause conflicts but once it's merged
> I will rebase and include that fix.
> 
> > > +		if (err)
> > > +			return err;
> > > +	}
> > > +
> > > +	err = register_netdev(dev);
> > > +	if (err)
> > > +		goto free_phylink;
> > > +
> > > +	return 0;
> > > +
> > > +free_phylink:
> > > +	if (airhoa_is_phy_external(port))
> > > +		phylink_destroy(port->phylink);
> > > +
> > > +	return err;
> > >  }
> > >  
> > >  static int airoha_probe(struct platform_device *pdev)
> > > @@ -2967,6 +3114,9 @@ static int airoha_probe(struct platform_device *pdev)
> > >  		struct airoha_gdm_port *port = eth->ports[i];
> > >  
> > >  		if (port && port->dev->reg_state == NETREG_REGISTERED) {
> > > +			if (airhoa_is_phy_external(port))
> > > +				phylink_destroy(port->phylink);
> > > +
> > >  			unregister_netdev(port->dev);
> > >  			airoha_metadata_dst_free(port);
> > >  		}
> > > @@ -2994,6 +3144,9 @@ static void airoha_remove(struct platform_device *pdev)
> > >  			continue;
> > >  
> > >  		airoha_dev_stop(port->dev);
> > > +		if (airhoa_is_phy_external(port))
> > > +			phylink_destroy(port->phylink);
> > > +
> > >  		unregister_netdev(port->dev);
> > >  		airoha_metadata_dst_free(port);
> > >  	}
> > > diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
> > > index 53f39083a8b0..73a500474076 100644
> > > --- a/drivers/net/ethernet/airoha/airoha_eth.h
> > > +++ b/drivers/net/ethernet/airoha/airoha_eth.h
> > > @@ -498,6 +498,9 @@ struct airoha_gdm_port {
> > >  	struct net_device *dev;
> > >  	int id;
> > >  
> > > +	struct phylink *phylink;
> > > +	struct phylink_config phylink_config;
> > > +
> > >  	struct airoha_hw_stats stats;
> > >  
> > >  	DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
> > > diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
> > > index d931530fc96f..54f7079b28b0 100644
> > > --- a/drivers/net/ethernet/airoha/airoha_regs.h
> > > +++ b/drivers/net/ethernet/airoha/airoha_regs.h
> > > @@ -357,6 +357,18 @@
> > >  #define IP_FRAGMENT_PORT_MASK		GENMASK(8, 5)
> > >  #define IP_FRAGMENT_NBQ_MASK		GENMASK(4, 0)
> > >  
> > > +#define REG_GDMA4_TMBI_FRAG		0x2028
> > > +#define GDMA4_SGMII1_TX_WEIGHT_MASK	GENMASK(31, 26)
> > > +#define GDMA4_SGMII1_TX_FRAG_SIZE_MASK	GENMASK(25, 16)
> > > +#define GDMA4_SGMII0_TX_WEIGHT_MASK	GENMASK(15, 10)
> > > +#define GDMA4_SGMII0_TX_FRAG_SIZE_MASK	GENMASK(9, 0)
> > > +
> > > +#define REG_GDMA4_RMBI_FRAG		0x202c
> > > +#define GDMA4_SGMII1_RX_WEIGHT_MASK	GENMASK(31, 26)
> > > +#define GDMA4_SGMII1_RX_FRAG_SIZE_MASK	GENMASK(25, 16)
> > > +#define GDMA4_SGMII0_RX_WEIGHT_MASK	GENMASK(15, 10)
> > > +#define GDMA4_SGMII0_RX_FRAG_SIZE_MASK	GENMASK(9, 0)
> > > +
> > >  #define REG_MC_VLAN_EN			0x2100
> > >  #define MC_VLAN_EN_MASK			BIT(0)
> > >  
> > > -- 
> > > 2.48.1
> > > 
> 
> 
> 
> -- 
> 	Ansuel
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From tanghuan at vivo.com  Mon May 12 06:15:19 2025
From: tanghuan at vivo.com (Huan Tang)
Date: Mon, 12 May 2025 21:15:19 +0800
Subject: [PATCH v2] ufs: core: Add HID support
Message-ID: <20250512131519.138-1-tanghuan@vivo.com>

Follow JESD220G, support HID(Host Initiated Defragmentation)
through sysfs, the relevant sysfs nodes are as follows:
	1.hid_analysis_trigger
	2.hid_defrag_trigger
	3.hid_fragmented_size
	4.hid_defrag_size
	5.hid_progress_ratio
	6.hid_state
The detailed definition	of the six nodes can be	found in the sysfs
documentation.

HID's execution policy is given to user-space.

Changelog
===
v1 - > v2:
	1.Refactor the HID code according to Bart and Peter and
	Arvi's suggestions

v1
	https://lore.kernel.org/all/20250417125008.123-1-tanghuan at vivo.com/

Signed-off-by: Huan Tang <tanghuan at vivo.com>
Signed-off-by: Wenxing Cheng <wenxing.cheng at vivo.com>
---
 Documentation/ABI/testing/sysfs-driver-ufs |  83 +++++++++
 drivers/ufs/core/ufs-sysfs.c               | 195 +++++++++++++++++++++
 drivers/ufs/core/ufshcd.c                  |   4 +
 include/ufs/ufs.h                          |  25 +++
 4 files changed, 307 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-driver-ufs b/Documentation/ABI/testing/sysfs-driver-ufs
index d4140dc6c5ba..8c4678305f94 100644
--- a/Documentation/ABI/testing/sysfs-driver-ufs
+++ b/Documentation/ABI/testing/sysfs-driver-ufs
@@ -1685,3 +1685,86 @@ Description:
 		================  ========================================
 
 		The file is read only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/ufs_hid/hid_analysis_trigger
+What:		/sys/bus/platform/devices/*.ufs/ufs_hid/hid_analysis_trigger
+Date:		April 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The host can enable or disable HID analysis operation.
+
+		=======  =========================================
+		disable   disable HID analysis operation
+		enable    enable HID analysis operation
+		=======  =========================================
+
+		The file is write only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/ufs_hid/hid_defrag_trigger
+What:		/sys/bus/platform/devices/*.ufs/ufs_hid/hid_defrag_trigger
+Date:		April 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The host can enable or disable HID defragmentation operation.
+
+		=======  =========================================
+		disable   disable HID defragmentation operation
+		enable    enable HID defragmentation operation
+		=======  =========================================
+
+		The attribute is write only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/ufs_hid/hid_fragmented_size
+What:		/sys/bus/platform/devices/*.ufs/ufs_hid/hid_fragmented_size
+Date:		April 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The total fragmented size in the device is reported through
+		this attribute.
+
+		The attribute is read only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/ufs_hid/hid_defrag_size
+What:		/sys/bus/platform/devices/*.ufs/ufs_hid/hid_defrag_size
+Date:		April 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The host sets the size to be defragmented by an HID
+		defragmentation operation.
+
+		The attribute is read/write.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/ufs_hid/hid_progress_ratio
+What:		/sys/bus/platform/devices/*.ufs/ufs_hid/hid_progress_ratio
+Date:		April 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		Defragmentation progress is reported by this attribute,
+		indicateds the ratio of the completed defragmentation size
+		over the requested defragmentation size.
+
+		====  ============================================
+		1     1%
+		...
+		100   100%
+		====  ============================================
+
+		The attribute is read only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/ufs_hid/hid_state
+What:		/sys/bus/platform/devices/*.ufs/ufs_hid/hid_state
+Date:		April 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The HID state is reported by this attribute.
+
+		====================   ===========================
+		idle			Idle(analysis required)
+		analysis_in_progress    Analysis in progress
+		defrag_required      	Defrag required
+		defrag_in_progress      Defrag in progress
+		defrag_completed      	Defrag completed
+		defrag_not_required     Defrag is not required
+		====================   ===========================
+
+		The attribute is read only.
diff --git a/drivers/ufs/core/ufs-sysfs.c b/drivers/ufs/core/ufs-sysfs.c
index de8b6acd4058..e993468b6a4e 100644
--- a/drivers/ufs/core/ufs-sysfs.c
+++ b/drivers/ufs/core/ufs-sysfs.c
@@ -87,6 +87,26 @@ static const char *ufs_wb_resize_status_to_string(enum wb_resize_status status)
 	}
 }
 
+static const char *ufs_hid_state_to_string(enum ufs_hid_state state)
+{
+	switch (state) {
+	case HID_IDLE:
+		return "idle";
+	case ANALYSIS_IN_PROGRESS:
+		return "analysis_in_progress";
+	case DEFRAG_REQUIRED:
+		return "defrag_required";
+	case DEFRAG_IN_PROGRESS:
+		return "defrag_in_progress";
+	case DEFRAG_COMPLETED:
+		return "defrag_completed";
+	case DEFRAG_IS_NOT_REQUIRED:
+		return "defrag_not_required";
+	default:
+		return "unknown";
+	}
+}
+
 static const char *ufshcd_uic_link_state_to_string(
 			enum uic_link_state state)
 {
@@ -1780,6 +1800,167 @@ static const struct attribute_group *ufs_sysfs_groups[] = {
 	NULL,
 };
 
+static int hid_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
+			enum attr_idn idn, u32 *attr_val)
+{
+	int ret;
+
+	down(&hba->host_sem);
+	if (!ufshcd_is_user_access_allowed(hba)) {
+		up(&hba->host_sem);
+		return -EBUSY;
+	}
+
+	ufshcd_rpm_get_sync(hba);
+	ret = ufshcd_query_attr(hba, opcode, idn, 0, 0, attr_val);
+	ufshcd_rpm_put_sync(hba);
+
+	up(&hba->host_sem);
+	return ret;
+}
+
+static const char * const hid_trigger_mode[] = {"disable", "enable"};
+
+static ssize_t hid_analysis_trigger_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	int mode;
+	int ret;
+
+	mode = sysfs_match_string(hid_trigger_mode, buf);
+	if (mode < 0)
+		return -EINVAL;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_WO(hid_analysis_trigger);
+
+static ssize_t hid_defrag_trigger_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	int mode;
+	int ret;
+
+	mode = sysfs_match_string(hid_trigger_mode, buf);
+	if (mode < 0)
+		return -EINVAL;
+
+	if (mode)
+		mode = HID_ANALYSIS_AND_DEFRAG_ENABLE;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_WO(hid_defrag_trigger);
+
+static ssize_t hid_fragmented_size_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_AVAILABLE_SIZE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%u\n", value);
+}
+
+static DEVICE_ATTR_RO(hid_fragmented_size);
+
+static ssize_t hid_defrag_size_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_SIZE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%u\n", value);
+}
+
+static ssize_t hid_defrag_size_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	if (kstrtou32(buf, 0, &value))
+		return -EINVAL;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_SIZE, &value);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_RW(hid_defrag_size);
+
+static ssize_t hid_progress_ratio_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_PROGRESS_RATIO, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%u\n", value);
+}
+
+static DEVICE_ATTR_RO(hid_progress_ratio);
+
+static ssize_t hid_state_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_STATE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%s\n", ufs_hid_state_to_string(value));
+}
+
+static DEVICE_ATTR_RO(hid_state);
+
+static struct attribute *ufs_sysfs_ufs_hid[] = {
+	&dev_attr_hid_analysis_trigger.attr,
+	&dev_attr_hid_defrag_trigger.attr,
+	&dev_attr_hid_fragmented_size.attr,
+	&dev_attr_hid_defrag_size.attr,
+	&dev_attr_hid_progress_ratio.attr,
+	&dev_attr_hid_state.attr,
+	NULL,
+};
+
+static const struct attribute_group ufs_sysfs_ufs_hid_group = {
+	.name = "ufs_hid",
+	.attrs = ufs_sysfs_ufs_hid,
+};
+
 #define UFS_LUN_DESC_PARAM(_pname, _puname, _duname, _size)		\
 static ssize_t _pname##_show(struct device *dev,			\
 	struct device_attribute *attr, char *buf)			\
@@ -1898,6 +2079,7 @@ const struct attribute_group ufs_sysfs_lun_attributes_group = {
 
 void ufs_sysfs_add_nodes(struct device *dev)
 {
+	struct ufs_hba *hba = dev_get_drvdata(dev);
 	int ret;
 
 	ret = sysfs_create_groups(&dev->kobj, ufs_sysfs_groups);
@@ -1905,9 +2087,22 @@ void ufs_sysfs_add_nodes(struct device *dev)
 		dev_err(dev,
 			"%s: sysfs groups creation failed (err = %d)\n",
 			__func__, ret);
+
+	if (hba->dev_info.hid_sup) {
+		ret = sysfs_create_group(&dev->kobj, &ufs_sysfs_ufs_hid_group);
+		if (ret)
+			dev_err(dev,
+				"%s: sysfs ufs_hid group creation failed (err = %d)\n",
+				__func__, ret);
+	}
 }
 
 void ufs_sysfs_remove_nodes(struct device *dev)
 {
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+
 	sysfs_remove_groups(&dev->kobj, ufs_sysfs_groups);
+
+	if (hba->dev_info.hid_sup)
+		sysfs_remove_group(&dev->kobj, &ufs_sysfs_ufs_hid_group);
 }
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index dc55c94fa45e..fb67eb582826 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -8392,6 +8392,10 @@ static int ufs_get_device_desc(struct ufs_hba *hba)
 
 	dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP];
 
+	dev_info->hid_sup = get_unaligned_be32(desc_buf +
+				DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP) &
+				UFS_DEV_HID_SUPPORT;
+
 	model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
 
 	err = ufshcd_read_string_desc(hba, model_index,
diff --git a/include/ufs/ufs.h b/include/ufs/ufs.h
index c0c59a8f7256..e61caa40f7cd 100644
--- a/include/ufs/ufs.h
+++ b/include/ufs/ufs.h
@@ -182,6 +182,11 @@ enum attr_idn {
 	QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE        = 0x1F,
 	QUERY_ATTR_IDN_TIMESTAMP		= 0x30,
 	QUERY_ATTR_IDN_DEV_LVL_EXCEPTION_ID     = 0x34,
+	QUERY_ATTR_IDN_HID_DEFRAG_OPERATION	= 0x35,
+	QUERY_ATTR_IDN_HID_AVAILABLE_SIZE	= 0x36,
+	QUERY_ATTR_IDN_HID_SIZE			= 0x37,
+	QUERY_ATTR_IDN_HID_PROGRESS_RATIO	= 0x38,
+	QUERY_ATTR_IDN_HID_STATE		= 0x39,
 	QUERY_ATTR_IDN_WB_BUF_RESIZE_HINT	= 0x3C,
 	QUERY_ATTR_IDN_WB_BUF_RESIZE_EN		= 0x3D,
 	QUERY_ATTR_IDN_WB_BUF_RESIZE_STATUS	= 0x3E,
@@ -401,6 +406,7 @@ enum {
 	UFS_DEV_HPB_SUPPORT		= BIT(7),
 	UFS_DEV_WRITE_BOOSTER_SUP	= BIT(8),
 	UFS_DEV_LVL_EXCEPTION_SUP       = BIT(12),
+	UFS_DEV_HID_SUPPORT		= BIT(13),
 };
 #define UFS_DEV_HPB_SUPPORT_VERSION		0x310
 
@@ -466,6 +472,23 @@ enum ufs_ref_clk_freq {
 	REF_CLK_FREQ_INVAL	= -1,
 };
 
+/* bDefragOperation attribute values */
+enum ufs_hid_defrag_operation {
+	HID_ANALYSIS_AND_DEFRAG_DISABLE	= 0,
+	HID_ANALYSIS_ENABLE		= 1,
+	HID_ANALYSIS_AND_DEFRAG_ENABLE	= 2,
+};
+
+/* bHIDState attribute values */
+enum ufs_hid_state {
+	HID_IDLE		= 0,
+	ANALYSIS_IN_PROGRESS	= 1,
+	DEFRAG_REQUIRED		= 2,
+	DEFRAG_IN_PROGRESS	= 3,
+	DEFRAG_COMPLETED	= 4,
+	DEFRAG_IS_NOT_REQUIRED	= 5,
+};
+
 /* bWriteBoosterBufferResizeEn attribute */
 enum wb_resize_en {
 	WB_RESIZE_EN_IDLE	= 0,
@@ -625,6 +648,8 @@ struct ufs_dev_info {
 	u32 rtc_update_period;
 
 	u8 rtt_cap; /* bDeviceRTTCap */
+
+	bool hid_sup;
 };
 
 /*
-- 
2.39.0



From vignesh.raman at collabora.com  Mon May 12 06:19:24 2025
From: vignesh.raman at collabora.com (Vignesh Raman)
Date: Mon, 12 May 2025 18:49:24 +0530
Subject: [PATCH v4] arm64: defconfig: mediatek: enable PHY drivers
Message-ID: <20250512131933.1247830-1-vignesh.raman@collabora.com>

The mediatek display driver fails to probe on mt8173-elm-hana and
mt8183-kukui-jacuzzi-juniper-sku16 in v6.14-rc4 due to missing PHY
configurations.

Commit 924d66011f24 ("drm/mediatek: stop selecting foreign drivers")
stopped selecting the MediaTek PHY drivers, requiring them to be
explicitly enabled in defconfig.

Enable the following PHY drivers for MediaTek platforms:
CONFIG_PHY_MTK_HDMI=m for HDMI display
CONFIG_PHY_MTK_MIPI_DSI=m for DSI display
CONFIG_PHY_MTK_DP=m for DP display

Fixes: 924d66011f24 ("drm/mediatek: stop selecting foreign drivers")
Reviewed-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
Signed-off-by: Vignesh Raman <vignesh.raman at collabora.com>
---

v2:
  - Include board details in the commit message.  
  - Sort newly added PHY configs in defconfig.

v3:
  - Use defconfig/savedefconfig to get the correct configs ordering.
  - Removed PHY_MTK_XSPHY since it is not required for probing display driver.
  - Add the commit details which deselected the MediaTek PHY drivers and
    added a Fixes tag.
  - Enabled CONFIG_PHY_MTK_DP, which was previously deselected.

v4:
  - Reword commit message.

---
 arch/arm64/configs/defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5bb8f09422a2..fa973f6328df 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1587,6 +1587,9 @@ CONFIG_PHY_HISTB_COMBPHY=y
 CONFIG_PHY_HISI_INNO_USB2=y
 CONFIG_PHY_MVEBU_CP110_COMPHY=y
 CONFIG_PHY_MTK_TPHY=y
+CONFIG_PHY_MTK_HDMI=m
+CONFIG_PHY_MTK_MIPI_DSI=m
+CONFIG_PHY_MTK_DP=m
 CONFIG_PHY_QCOM_EDP=m
 CONFIG_PHY_QCOM_PCIE2=m
 CONFIG_PHY_QCOM_QMP=m
-- 
2.47.2



From horms at kernel.org  Mon May 12 06:33:42 2025
From: horms at kernel.org (Simon Horman)
Date: Mon, 12 May 2025 14:33:42 +0100
Subject: [PATCH net-next v2 2/2] net: airoha: Add the capability to
 allocate hw buffers in SRAM
In-Reply-To: <20250509-airopha-desc-sram-v2-2-9dc3d8076dfb@kernel.org>
References: <20250509-airopha-desc-sram-v2-0-9dc3d8076dfb@kernel.org>
 <20250509-airopha-desc-sram-v2-2-9dc3d8076dfb@kernel.org>
Message-ID: <20250512133342.GB3339421@horms.kernel.org>

On Fri, May 09, 2025 at 04:51:34PM +0200, Lorenzo Bianconi wrote:
> In order to improve packet processing and packet forwarding
> performances, EN7581 SoC supports allocating buffers for hw forwarding
> queues in SRAM instead of DRAM if available on the system.
> Rely on SRAM for buffers allocation if available on the system and use
> DRAM as fallback.
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>

Reviewed-by: Simon Horman <horms at kernel.org>

> ---
>  drivers/net/ethernet/airoha/airoha_eth.c | 57 +++++++++++++++++++++++++++-----
>  1 file changed, 48 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c

...

> @@ -1088,12 +1091,45 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
>  
>  	airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr);
>  
> -	size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM;
> -	qdma->hfwd.q = dmam_alloc_coherent(eth->dev, size, &dma_addr,
> -					   GFP_KERNEL);
> -	if (!qdma->hfwd.q)
> +	name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id);
> +	if (!name)
>  		return -ENOMEM;
>  
> +	index = of_property_match_string(eth->dev->of_node,
> +					 "memory-region-names", name);
> +	if (index >= 0) { /* buffers in sram */
> +		struct reserved_mem *rmem;
> +		struct device_node *np;
> +		void *q;
> +
> +		np = of_parse_phandle(eth->dev->of_node, "memory-region",
> +				      index);
> +		if (!np)
> +			return -ENODEV;
> +
> +		rmem = of_reserved_mem_lookup(np);
> +		of_node_put(np);
> +
> +		/* SRAM is actual memory and supports transparent access just
> +		 * like DRAM. Hence we don't require __iomem being set and
> +		 * we don't need to use accessor routines to read from or write
> +		 * to SRAM.
> +		 */

Thanks for this comment. IMHO It is really useful.

> +		q = (void __force *)devm_ioremap(eth->dev, rmem->base,
> +						 rmem->size);
> +		if (!q)
> +			return -ENOMEM;
> +
> +		qdma->hfwd.q = q;
> +		dma_addr = rmem->base;
> +	} else {
> +		size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM;
> +		qdma->hfwd.q = dmam_alloc_coherent(eth->dev, size, &dma_addr,
> +						   GFP_KERNEL);
> +		if (!qdma->hfwd.q)
> +			return -ENOMEM;
> +	}
> +
>  	airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr);
>  
>  	airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG,

...


From conor at kernel.org  Mon May 12 09:00:50 2025
From: conor at kernel.org (Conor Dooley)
Date: Mon, 12 May 2025 17:00:50 +0100
Subject: [PATCH v3 1/3] dt-bindings: arm: Add compatible for MediaTek
 MT8189
In-Reply-To: <20250512115355.923342-2-sirius.wang@mediatek.com>
References: <20250512115355.923342-1-sirius.wang@mediatek.com>
 <20250512115355.923342-2-sirius.wang@mediatek.com>
Message-ID: <20250512-ferret-willed-348cdc19fe4e@spud>

On Mon, May 12, 2025 at 07:53:48PM +0800, Sirius Wang wrote:
> This commit adds dt-binding documentation for the MediaTek MT8189
> reference board.
> 
> Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

Acked-by: Conor Dooley <conor.dooley at microchip.com>

> ---
>  Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
> index fa1646bc0bac..05e827076a7f 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
> @@ -372,6 +372,10 @@ properties:
>            - enum:
>                - mediatek,mt8188-evb
>            - const: mediatek,mt8188
> +      - items:
> +          - enum:
> +              - mediatek,mt8189-evb
> +          - const: mediatek,mt8189
>        - description: Google Hayato
>          items:
>            - const: google,hayato-rev1
> -- 
> 2.45.2
> 
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From conor at kernel.org  Mon May 12 09:21:45 2025
From: conor at kernel.org (Conor Dooley)
Date: Mon, 12 May 2025 17:21:45 +0100
Subject: [PATCH v1 01/14] dt-bindings: net: mediatek,net: update for
 mt7988
In-Reply-To: <20250511141942.10284-2-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
 <20250511141942.10284-2-linux@fw-web.de>
Message-ID: <20250512-nibble-freemason-69e0279f2f99@spud>

On Sun, May 11, 2025 at 04:19:17PM +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w at public-files.de>
> 
> Update binding for mt7988 which has 3 gmac and 2 reg items.
> 
> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> ---
>  Documentation/devicetree/bindings/net/mediatek,net.yaml | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml
> index 9e02fd80af83..5d249da02c3a 100644
> --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml
> +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml
> @@ -28,7 +28,8 @@ properties:
>        - ralink,rt5350-eth
>  
>    reg:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 2

This should become an items list, with an explanation of what each of
the reg items represents.

>  
>    clocks:
>      minItems: 2
> @@ -381,8 +382,12 @@ allOf:
>              - const: xgp2
>              - const: xgp3
>  
> +        reg:
> +          minItems: 2
> +          maxItems: 2
> +
>  patternProperties:
> -  "^mac@[0-1]$":
> +  "^mac@[0-2]$":
>      type: object
>      unevaluatedProperties: false
>      allOf:
> -- 
> 2.43.0
> 
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From conor at kernel.org  Mon May 12 09:34:09 2025
From: conor at kernel.org (Conor Dooley)
Date: Mon, 12 May 2025 17:34:09 +0100
Subject: [PATCH 01/14] dt-bindings: media: mediatek: vcodec: add decoder
 dt-bindings for mt8196
In-Reply-To: <20250510075357.11761-2-yunfei.dong@mediatek.com>
References: <20250510075357.11761-1-yunfei.dong@mediatek.com>
 <20250510075357.11761-2-yunfei.dong@mediatek.com>
Message-ID: <20250512-cilantro-aviation-4328d79e02b6@spud>

On Sat, May 10, 2025 at 03:53:31PM +0800, Yunfei Dong wrote:
> Add compatible for video decoder on MT8196 platform, which is a
> lat + single core architecture.

Please mention what makes this different from the existing devices since
a fallback compatible is not permitted.

> 
> Signed-off-by: Yunfei Dong <yunfei.dong at mediatek.com>
> ---
>  .../bindings/media/mediatek,vcodec-subdev-decoder.yaml           | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
> index bf8082d87ac0..74e1d88d3056 100644
> --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
> +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
> @@ -76,6 +76,7 @@ properties:
>        - mediatek,mt8186-vcodec-dec
>        - mediatek,mt8188-vcodec-dec
>        - mediatek,mt8195-vcodec-dec
> +      - mediatek,mt8196-vcodec-dec
>  
>    reg:
>      minItems: 1
> -- 
> 2.46.0
> 
> 
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From linux at fw-web.de  Mon May 12 09:54:13 2025
From: linux at fw-web.de (Frank Wunderlich (linux))
Date: Mon, 12 May 2025 18:54:13 +0200
Subject: [PATCH v1 08/14] arm64: dts: mediatek: mt7988: add basic
 ethernet-nodes
In-Reply-To: <78abbdb9-70d8-4e53-8593-91735cde73ec@lunn.ch>
References: <20250511141942.10284-1-linux@fw-web.de>
 <20250511141942.10284-9-linux@fw-web.de>
 <78abbdb9-70d8-4e53-8593-91735cde73ec@lunn.ch>
Message-ID: <acc9ca84eadb1f78308f0c3e2b527406@fw-web.de>

Am 2025-05-11 18:38, schrieb Andrew Lunn:
>> +			gmac0: mac at 0 {
>> +				compatible = "mediatek,eth-mac";
>> +				reg = <0>;
>> +				phy-mode = "internal";
>> +
>> +				fixed-link {
>> +					speed = <10000>;
>> +					full-duplex;
>> +					pause;
>> +				};
> 
> Does phy-mode internal and fixed-link used together make any sense?
> Please could you explain this.

Hi,

the fixed link is used to bring up the mac and switch cpu port up with 
the right settings.
Of course we can hardcode it in driver for mt7988, but driver already 
supports the generic
definition via devicetree. So imho adding driver code for whats already 
supported via devicetree
does not make sense for me and devicetree shows the right settings 
(speed,duplex,flow control) without digging in the driver code.

e.g. we could disable flow-control there (but it causes retransmitts) 
without changing driver.

Imho this is the cleanest way without adding unnecessary driver code and 
SoC conditions and
devicetree describes hardware ;).

regards Frank


From linux at fw-web.de  Mon May 12 10:33:22 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Mon, 12 May 2025 19:33:22 +0200
Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v1_01/14=5D_dt-bindings=3A_n?=
 =?US-ASCII?Q?et=3A_mediatek=2Cnet=3A_update_for_mt7988?=
In-Reply-To: <20250512-nibble-freemason-69e0279f2f99@spud>
References: <20250511141942.10284-1-linux@fw-web.de> <20250511141942.10284-2-linux@fw-web.de> <20250512-nibble-freemason-69e0279f2f99@spud>
Message-ID: <05760B5E-955E-4E0E-9B69-E762783CC37B@fw-web.de>

Am 12. Mai 2025 18:21:45 MESZ schrieb Conor Dooley <conor at kernel.org>:
>On Sun, May 11, 2025 at 04:19:17PM +0200, Frank Wunderlich wrote:
>> From: Frank Wunderlich <frank-w at public-files.de>
>> 
>> Update binding for mt7988 which has 3 gmac and 2 reg items.
>> 
>> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
>> ---
>>  Documentation/devicetree/bindings/net/mediatek,net.yaml | 9 +++++++--
>>  1 file changed, 7 insertions(+), 2 deletions(-)
>> 
>> diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml
>> index 9e02fd80af83..5d249da02c3a 100644
>> --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml
>> +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml
>> @@ -28,7 +28,8 @@ properties:
>>        - ralink,rt5350-eth
>>  
>>    reg:
>> -    maxItems: 1
>> +    minItems: 1
>> +    maxItems: 2
>
>This should become an items list, with an explanation of what each of
>the reg items represents.

I would change to this

  reg:
    items:
      - description: Register for accessing the MACs.
      - description: SoC internal SRAM used for DMA operations.
    minItems: 1

Would this be OK this way?

>>  
>>    clocks:
>>      minItems: 2
>> @@ -381,8 +382,12 @@ allOf:
>>              - const: xgp2
>>              - const: xgp3
>>  
>> +        reg:
>> +          minItems: 2
>> +          maxItems: 2
>> +
>>  patternProperties:
>> -  "^mac@[0-1]$":
>> +  "^mac@[0-2]$":
>>      type: object
>>      unevaluatedProperties: false
>>      allOf:
>> -- 
>> 2.43.0
>> 

Hi Conor

Thank you for review.
regards Frank


From conor at kernel.org  Mon May 12 14:01:10 2025
From: conor at kernel.org (Conor Dooley)
Date: Mon, 12 May 2025 22:01:10 +0100
Subject: [PATCH v1 01/14] dt-bindings: net: mediatek,net: update for
 mt7988
In-Reply-To: <05760B5E-955E-4E0E-9B69-E762783CC37B@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
 <20250511141942.10284-2-linux@fw-web.de>
 <20250512-nibble-freemason-69e0279f2f99@spud>
 <05760B5E-955E-4E0E-9B69-E762783CC37B@fw-web.de>
Message-ID: <20250512-spooky-overbuilt-abc946ba1f55@spud>

On Mon, May 12, 2025 at 07:33:22PM +0200, Frank Wunderlich wrote:
> Am 12. Mai 2025 18:21:45 MESZ schrieb Conor Dooley <conor at kernel.org>:
> >On Sun, May 11, 2025 at 04:19:17PM +0200, Frank Wunderlich wrote:
> >> From: Frank Wunderlich <frank-w at public-files.de>
> >> 
> >> Update binding for mt7988 which has 3 gmac and 2 reg items.
> >> 
> >> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> >> ---
> >>  Documentation/devicetree/bindings/net/mediatek,net.yaml | 9 +++++++--
> >>  1 file changed, 7 insertions(+), 2 deletions(-)
> >> 
> >> diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml
> >> index 9e02fd80af83..5d249da02c3a 100644
> >> --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml
> >> +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml
> >> @@ -28,7 +28,8 @@ properties:
> >>        - ralink,rt5350-eth
> >>  
> >>    reg:
> >> -    maxItems: 1
> >> +    minItems: 1
> >> +    maxItems: 2
> >
> >This should become an items list, with an explanation of what each of
> >the reg items represents.
> 
> I would change to this
> 
>   reg:
>     items:
>       - description: Register for accessing the MACs.
>       - description: SoC internal SRAM used for DMA operations.
>     minItems: 1
> 
> Would this be OK this way?

Ye, that looks good.

> 
> >>  
> >>    clocks:
> >>      minItems: 2
> >> @@ -381,8 +382,12 @@ allOf:
> >>              - const: xgp2
> >>              - const: xgp3
> >>  
> >> +        reg:
> >> +          minItems: 2
> >> +          maxItems: 2

You also shouldn't need to set maxItems here, since the list has 2 items
total.

> >> +
> >>  patternProperties:
> >> -  "^mac@[0-1]$":
> >> +  "^mac@[0-2]$":
> >>      type: object
> >>      unevaluatedProperties: false
> >>      allOf:
> >> -- 
> >> 2.43.0
> >> 
> 
> Hi Conor
> 
> Thank you for review.
> regards Frank
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From bvanassche at acm.org  Mon May 12 15:21:49 2025
From: bvanassche at acm.org (Bart Van Assche)
Date: Mon, 12 May 2025 15:21:49 -0700
Subject: [PATCH v2] ufs: core: support updating device command timeout
In-Reply-To: <20250510080345.595798-1-peter.wang@mediatek.com>
References: <20250510080345.595798-1-peter.wang@mediatek.com>
Message-ID: <a399d7d5-7829-42d6-84d8-d0956d07f8f0@acm.org>

On 5/10/25 1:01 AM, peter.wang at mediatek.com wrote:
> The default device command timeout remains 1.5 seconds,
> but platform drivers can override it if needed.
> 
> Some UFS device commands may timeout due to being blocked
> by regular SCSI write commands. Therefore, the maximun timeout
> needs to be extended to 30 seconds, matching the SCSI write
> command timeout. And for error injection purposes, set the
> minimum value to 1 ms.

Reviewed-by: Bart Van Assche <bvanassche at acm.org>


From martin.petersen at oracle.com  Mon May 12 19:37:11 2025
From: martin.petersen at oracle.com (Martin K. Petersen)
Date: Mon, 12 May 2025 22:37:11 -0400
Subject: [PATCH v3] ufs: core: change hwq_id type and value
In-Reply-To: <20250509021648.412098-1-peter.wang@mediatek.com> (peter wang's
	message of "Fri, 9 May 2025 10:16:12 +0800")
References: <20250509021648.412098-1-peter.wang@mediatek.com>
Message-ID: <yq1h61pqlrm.fsf@ca-mkp.ca.oracle.com>


> Change the type of hwq_id to u32 because the member id of struct
> ufs_hw_queue is u32 (hwq->id) and the trace entry hwq_id is also u32.
> Set hwq_id to 0 if mcq is not supported, as SDB mode only supports one
> hardware queue.

Applied to 6.16/scsi-staging, thanks!

-- 
Martin K. Petersen


From martin.petersen at oracle.com  Mon May 12 19:39:07 2025
From: martin.petersen at oracle.com (Martin K. Petersen)
Date: Mon, 12 May 2025 22:39:07 -0400
Subject: [PATCH v2] ufs: core: support updating device command timeout
In-Reply-To: <20250510080345.595798-1-peter.wang@mediatek.com> (peter wang's
	message of "Sat, 10 May 2025 16:01:01 +0800")
References: <20250510080345.595798-1-peter.wang@mediatek.com>
Message-ID: <yq1bjrxqlof.fsf@ca-mkp.ca.oracle.com>


> The default device command timeout remains 1.5 seconds, but platform
> drivers can override it if needed.

Applied to 6.16/scsi-staging, thanks!

-- 
Martin K. Petersen


From daniel at makrotopia.org  Mon May 12 21:27:30 2025
From: daniel at makrotopia.org (Daniel Golle)
Date: Tue, 13 May 2025 05:27:30 +0100
Subject: [PATCH net] net: ethernet: mtk_eth_soc: fix typo for declaration
 MT7988 ESW capability
Message-ID: <b8b37f409d1280fad9c4d32521e6207f63cd3213.1747110258.git.daniel@makrotopia.org>

From: Bo-Cun Chen <bc-bocun.chen at mediatek.com>

Since MTK_ESW_BIT is a bit number rather than a bitmap, it causes
MTK_HAS_CAPS to produce incorrect results. This leads to the ETH
driver not declaring MAC capabilities correctly for the MT7988 ESW.

Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC")
Signed-off-by: Bo-Cun Chen <bc-bocun.chen at mediatek.com>
Signed-off-by: Daniel Golle <daniel at makrotopia.org>
---
 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 22a532695fb0..6c92072b4c28 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -4748,7 +4748,7 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
 	}
 
 	if (mtk_is_netsys_v3_or_greater(mac->hw) &&
-	    MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) &&
+	    MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW) &&
 	    id == MTK_GMAC1_ID) {
 		mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
 						       MAC_SYM_PAUSE |
-- 
2.49.0


From michal.swiatkowski at linux.intel.com  Mon May 12 22:21:25 2025
From: michal.swiatkowski at linux.intel.com (Michal Swiatkowski)
Date: Tue, 13 May 2025 07:21:25 +0200
Subject: [PATCH net] net: ethernet: mtk_eth_soc: fix typo for declaration
 MT7988 ESW capability
In-Reply-To: <b8b37f409d1280fad9c4d32521e6207f63cd3213.1747110258.git.daniel@makrotopia.org>
References: <b8b37f409d1280fad9c4d32521e6207f63cd3213.1747110258.git.daniel@makrotopia.org>
Message-ID: <aCLW1ZAVQvs8fkUm@mev-dev.igk.intel.com>

On Tue, May 13, 2025 at 05:27:30AM +0100, Daniel Golle wrote:
> From: Bo-Cun Chen <bc-bocun.chen at mediatek.com>
> 
> Since MTK_ESW_BIT is a bit number rather than a bitmap, it causes
> MTK_HAS_CAPS to produce incorrect results. This leads to the ETH
> driver not declaring MAC capabilities correctly for the MT7988 ESW.
> 
> Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC")
> Signed-off-by: Bo-Cun Chen <bc-bocun.chen at mediatek.com>
> Signed-off-by: Daniel Golle <daniel at makrotopia.org>
> ---
>  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> index 22a532695fb0..6c92072b4c28 100644
> --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> @@ -4748,7 +4748,7 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
>  	}
>  
>  	if (mtk_is_netsys_v3_or_greater(mac->hw) &&
> -	    MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) &&
> +	    MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW) &&
>  	    id == MTK_GMAC1_ID) {
>  		mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
>  						       MAC_SYM_PAUSE |

Looks like other usage of MTK_HAS_CAPS is fine, thanks for fixing.

Reviewed-by: Michal Swiatkowski <michal.swiatkowski at linux.intel.com>

> -- 
> 2.49.0


From adrian.liszka at novaplan.pl  Tue May 13 01:00:24 2025
From: adrian.liszka at novaplan.pl (Adrian Liszka)
Date: Tue, 13 May 2025 08:00:24 GMT
Subject: =?UTF-8?Q?Prosz=C4=99_o_kontakt?=
Message-ID: <20250513084500-0.1.li.1wfdx.0.ip106es90y@novaplan.pl>

Dzie? dobry,

Czy jest mo?liwo?? nawi?zania wsp??pracy z Pa?stwem?

Z ch?ci? porozmawiam z osob? zajmuj?c? si? dzia?aniami zwi?zanymi ze sprzeda??.

Pomagamy skutecznie pozyskiwa? nowych klient?w.

Zapraszam do kontaktu.


Z pozdrowieniami
Adrian Liszka


From SkyLake.Huang at mediatek.com  Tue May 13 02:45:26 2025
From: SkyLake.Huang at mediatek.com (=?utf-8?B?U2t5TGFrZSBIdWFuZyAo6buD5ZWf5r6kKQ==?=)
Date: Tue, 13 May 2025 09:45:26 +0000
Subject: [PATCH net-next v2 1/3] net: phy: mediatek: Add 2.5Gphy firmware
 dt-bindings and dts node
In-Reply-To: <8bc68f1a-5abd-478c-9b9d-2c8baa6bb36a@lunn.ch>
References: <20250219083910.2255981-1-SkyLake.Huang@mediatek.com>
	 <20250219083910.2255981-2-SkyLake.Huang@mediatek.com>
	 <a15cfd5d-7c1a-45b2-af14-aa4e8761111f@lunn.ch>
	 <Z7X5Dta3oUgmhnmk@makrotopia.org>
	 <ff96f5d38e089fdd76294265f33d7230c573ba69.camel@mediatek.com>
	 <176f8fe1-f4cf-4bbd-9aea-5f407cef8ac5@lunn.ch>
	 <c5728ec30db963c97b6e292b51e73e2c075d1757.camel@mediatek.com>
	 <8bc68f1a-5abd-478c-9b9d-2c8baa6bb36a@lunn.ch>
Message-ID: <a7f1848eb200c1ee117ba4aa192751f4266efc6e.camel@mediatek.com>

On Wed, 2025-02-26 at 14:26 +0100, Andrew Lunn wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> > So I guess I can do the following according to the previous
> > discussion:
> > 1) Reserve a memory region in mt7988.dtsi
> > reserved-memory {
> > ????? #address-cells = <2>;
> > ????? #size-celss = <2>;
> > ????? ranges;
> > 
> > ????? /* 0x0f0100000~0x0f1f0024 are specific for built-in 2.5Gphy.
> > ?????? * In this range, it includes "PMB_FW_BASE"(0x0f100000)
> > ?????? * and "MCU_CSR_BASE"(0x0f0f0000)
> > ?????? */
> > ????? i2p5g: i2p5g at 0f100000 {
> > ????????????? reg = <0 0x0f010000 0 0x1e0024>;
> > ????????????? no-map;
> > ????? };
> > };
> 
> Do you even need these? I assume this is in the IO space, not DRAM.
> So
> the kernel is not going to use it by default. That is why you need to
> specifically ioremap() it.

Agree. I'll remove this.

> 
> > 2) Since PHYs don't use compatibles, hardcode address in mtk-
> > 2p5ge.c:
> > /* MTK_ prefix means that the macro is used for both MT7988 &
> > MT7987*/
> > #define MTK_2P5GPHY_PMB_FW_BASE?????????????? (0x0f100000)
> > #define MT7988_2P5GE_PMB_FW_LEN?????????????? (0x20000)
> > #define MT7987_2P5GE_PMB_FW_LEN?????????????? (0x18000)
> > #define MTK_2P5GPHY_MCU_CSR_BASE????? (0x0f0f0000)
> > #define MTK_2P5GPHY_MCU_CSR_LEN?????????????? (0x20)
> > 
> > /* On MT7987, we separate firmware bin to 2 files and total size
> > ?* is decreased from 128KB(mediatek/mt7988/i2p5ge-phy-pmb.bin) to
> > ?* 96KB(mediatek/mt7987/i2p5ge-phy-pmb.bin)+
> > ?* 28KB(mediatek/mt7987/i2p5ge-phy-DSPBitTb.bin)
> > ?* And i2p5ge-phy-DSPBitTb.bin will be loaded to
> > ?* MT7987_2P5GE_XBZ_PMA_RX_BASE
> > ?*/
> > #define MT7987_2P5GE_XBZ_PMA_RX_BASE? (0x0f080000)
> > #define MT7987_2P5GE_XBZ_PMA_RX_LEN?? (0x5228)
> > #define MT7987_2P5GE_DSPBITTB_SIZE??? (0x7000)
> > 
> > /* MT7987 requires these base addresses to manipulate some
> > ?* registers before loading firmware.
> > ?*/
> > #define MT7987_2P5GE_APB_BASE???????? (0x11c30000)
> > #define MT7987_2P5GE_APB_LEN????????? (0x9c)
> > #define MT7987_2P5GE_PMD_REG_BASE???? (0x0f010000)
> > #define MT7987_2P5GE_PMD_REG_LEN????? (0x210)
> > #define MT7987_2P5GE_XBZ_PCS_REG_BASE (0x0f030000)
> > #define MT7987_2P5GE_XBZ_PCS_REG_LEN? (0x844)
> 
> Should the PCS registers actually be in the PCS driver, not the PHY
> driver? Hard to say until we know what these registers actually are.
> 
These PCS registers are in different domain with USXGMII's PCS on
MT7988. These PCS registers are only used by built-in 2.5Gphy when
loading firmware. I'll submit MT7987's built-in 2.5Gphy driver later
and we can check if another PCS driver is needed or not.

> > #define MT7987_2P5GE_CHIP_SCU_BASE??? (0x0f0cf800)
> > #define MT7987_2P5GE_CHIP_SCU_LEN???? (0x12c)
> > 
> > static int mt7988_2p5ge_phy_load_fw(struct phy_device *phydev)
> > {
> > ????? struct mtk_i2p5ge_phy_priv *priv = phydev->priv;
> > ????? void __iomem *mcu_csr_base, *pmb_addr;
> > ????? struct device *dev = &phydev->mdio.dev;
> > ????? const struct firmware *fw;
> > ????? int ret, i;
> > ????? u32 reg;
> > 
> > ????? if (priv->fw_loaded)
> > ????????????? return 0;
> > 
> > ????? pmb_addr = ioremap(MTK_2P5GPHY_PMB_FW_BASE,
> > ???????????????????????? MT7988_2P5GE_PMB_FW_LEN);
> > ????? if (!pmb_addr)
> > ????????????? return -ENOMEM;
> > ????? mcu_csr_base = ioremap(MTK_2P5GPHY_MCU_CSR_BASE,
> > ???????????????????????????? MTK_2P5GPHY_MCU_CSR_LEN);
> > ????? if (!mcu_csr_base) {
> > ????????????? ret = -ENOMEM;
> > ????????????? goto free_pmb;
> > ????? }
> > ...
> > free:
> > ????? iounmap(mcu_csr_base);
> > free_pmb:
> > ????? iounmap(pmb_addr);
> > ...
> > }
> 
> This looks O.K. It is basically what we did before device tree was
> used.
> 
> ??????? Andrew

OK. I'll submit v3 in this way.

BRs,
Sky

From SkyLake.Huang at mediatek.com  Tue May 13 03:12:04 2025
From: SkyLake.Huang at mediatek.com (=?utf-8?B?U2t5TGFrZSBIdWFuZyAo6buD5ZWf5r6kKQ==?=)
Date: Tue, 13 May 2025 10:12:04 +0000
Subject: [PATCH net-next v2 3/3] net: phy: mediatek: add driver for
 built-in 2.5G ethernet PHY on MT7988
In-Reply-To: <Z7WleP9v6Igx2MjC@shell.armlinux.org.uk>
References: <20250219083910.2255981-1-SkyLake.Huang@mediatek.com>
	 <20250219083910.2255981-4-SkyLake.Huang@mediatek.com>
	 <Z7WleP9v6Igx2MjC@shell.armlinux.org.uk>
Message-ID: <74ce0275952a9c60af87ded9d64ca7301fd69d0f.camel@mediatek.com>

On Wed, 2025-02-19 at 09:33 +0000, Russell King (Oracle) wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On Wed, Feb 19, 2025 at 04:39:10PM +0800, Sky Huang wrote:
> > +static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
> > +{
> > +???? struct pinctrl *pinctrl;
> > +???? int ret;
> > +
> > +???? /* Check if PHY interface type is compatible */
> > +???? if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL)
> > +???????????? return -ENODEV;
> > +
> > +???? ret = mt798x_2p5ge_phy_load_fw(phydev);
> > +???? if (ret < 0)
> > +???????????? return ret;
> 
> Firmware should not be loaded in the .config_init method. The above
> call will block while holding the RTNL which will prevent all other
> network configuration until the firmware has been loaded or the load
> fails.
> 
> Thanks.
> 
> --
> RMK's Patch system:
> https://urldefense.com/v3/__https://www.armlinux.org.uk/developer/patches/__;!!CTRNKA9wMg0ARbw!iV-1ViPFsUV-lLj7aIycan8nery6sQO3t6mkpdlb_GW8hswhxc4ejJozxqkU3s2WzxSizs4kfdC77yr7HGGRIuU$
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Actually, I wrote fw loading flow in .probe. However, during boot time,
.probe is called at very early stage (about the first 2s after booting
into Linux Kernel). At that time, filesystem isn't ready yet and phy
driver can't locate /lib/firmware/mediatek/mt7988/i2p5ge-phy-pmb.bin.
Adding "-EPROBE_DEFER" doesn't help at this moment. I'm not sure how
aquantia and qt2025 drivers handle this.

But anyway, mt7988's built-in phy driver loads firmware in only a few
ms. This is via internal bus instead of MDIO bus, so loading speed is
much faster. Will this have any impact, if that's the case?

BRs,
Sky

From SkyLake.Huang at mediatek.com  Tue May 13 03:55:57 2025
From: SkyLake.Huang at mediatek.com (=?utf-8?B?U2t5TGFrZSBIdWFuZyAo6buD5ZWf5r6kKQ==?=)
Date: Tue, 13 May 2025 10:55:57 +0000
Subject: [PATCH net-next v2 3/3] net: phy: mediatek: add driver for
 built-in 2.5G ethernet PHY on MT7988
In-Reply-To: <724eff11-c6d1-40e1-a99f-205f5426a07d@lunn.ch>
References: <20250219083910.2255981-1-SkyLake.Huang@mediatek.com>
	 <20250219083910.2255981-4-SkyLake.Huang@mediatek.com>
	 <724eff11-c6d1-40e1-a99f-205f5426a07d@lunn.ch>
Message-ID: <062fff7f65bb9654922be4cac34e3c6fe01d7029.camel@mediatek.com>

On Wed, 2025-02-19 at 16:47 +0100, Andrew Lunn wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> > +config MEDIATEK_2P5GE_PHY
> > +???? tristate "MediaTek 2.5Gb Ethernet PHYs"
> > +???? depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
> > +???? select MTK_NET_PHYLIB
> > +???? help
> > +?????? Supports MediaTek SoC built-in 2.5Gb Ethernet PHYs.
> > +
> > +?????? This will load necessary firmware and add appropriate time
> > delay.
> > +?????? Accelerate this procedure through internal pbus instead of
> > MDIO
> > +?????? bus. Certain link-up issues will also be fixed here.
> 
> Please keep the file sorted, this should be the first entry.
> 
I'll sort in this way in v3:
config MEDIATEK_2P5GE_PHY
...
config MEDIATEK_GE_SOC_PHY
...
config MTK_NET_PHYLIB
...
config MEDIATEK_GE_PHY
...

> > diff --git a/drivers/net/phy/mediatek/Makefile
> > b/drivers/net/phy/mediatek/Makefile
> > index 814879d0abe5..c6db8abd2c9c 100644
> > --- a/drivers/net/phy/mediatek/Makefile
> > +++ b/drivers/net/phy/mediatek/Makefile
> > @@ -2,3 +2,4 @@
> > ?obj-$(CONFIG_MTK_NET_PHYLIB)???????? += mtk-phy-lib.o
> > ?obj-$(CONFIG_MEDIATEK_GE_PHY)??????????????? += mtk-ge.o
> > ?obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)??? += mtk-ge-soc.o
> > +obj-$(CONFIG_MEDIATEK_2P5GE_PHY)???? += mtk-2p5ge.o
> 
> I suppose you could say this file is sorted in reverse order so is
> correct?
> 
I'll change this in v3 in this way:
obj-$(CONFIG_MEDIATEK_2P5GE_PHY)     += mtk-2p5ge.o
obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)    += mtk-ge-soc.o
obj-$(CONFIG_MTK_NET_PHYLIB)         += mtk-phy-lib.o
obj-$(CONFIG_MEDIATEK_GE_PHY)        += mtk-ge.o

> > diff --git a/drivers/net/phy/mediatek/mtk-2p5ge.c
> > b/drivers/net/phy/mediatek/mtk-2p5ge.c
> > new file mode 100644
> > index 000000000000..adb03df331ab
> > --- /dev/null
> > +++ b/drivers/net/phy/mediatek/mtk-2p5ge.c
> > @@ -0,0 +1,346 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +#include <linux/bitfield.h>
> > +#include <linux/firmware.h>
> > +#include <linux/module.h>
> > +#include <linux/nvmem-consumer.h>
> 
> Is this header needed?
> 
> > +#include <linux/of_address.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/pinctrl/consumer.h>
> > +#include <linux/phy.h>
> > +#include <linux/pm_domain.h>
> > +#include <linux/pm_runtime.h>
> 
> And these two? Please only use those that are needed.
> 
I'll remove linux/nvmem-
consumer.h>/<linux/pm_domain.h>/<linux/pm_runtime.h> in v3. I forgot
removing them after developing this driver.

> > +static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev)
> > +{
> > +
> > +???? writew(reg & ~MD32_EN, mcu_csr_base + MD32_EN_CFG);
> > +???? writew(reg | MD32_EN, mcu_csr_base + MD32_EN_CFG);
> > +???? phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
> > +???? /* We need a delay here to stabilize initialization of MCU */
> > +???? usleep_range(7000, 8000);
> 
> Does the reset bit clear when the MCU is ready? That is what 802.3
> defines. phy_poll_reset() might do what you need.

CL22 reset bit will be cleared right after I set it on MT7988.
usleep_range() here is used to allow the MCU to stabilize, rather than
to wait for the reset to complete.
> 
> > +???? dev_info(dev, "Firmware loading/trigger ok.\n");
> 
> dev_dbg(), if at all. You have already spammed the log with the
> firmware version, so this adds nothing useful.

Well then... In v3, I'll remove this line and print firmware version at
last like this:

for (i = 0; i < MT7988_2P5GE_PMB_FW_SIZE - 1; i += 4)
	writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);

writew(reg & ~MD32_EN, mcu_csr_base + MD32_EN_CFG);
writew(reg | MD32_EN, mcu_csr_base + MD32_EN_CFG);
phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
/* We need a delay here to stabilize initialization of MCU */
usleep_range(7000, 8000);

dev_info(dev, "Firmware date code: %x/%x/%x, version: %x.%x\n",
	 be16_to_cpu(*((__be16 *)(fw->data +
				  MT7988_2P5GE_PMB_FW_SIZE - 8))),
	 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 6),
	 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 5),
	 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 2),
	 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 1));

priv->fw_loaded = true;

> > +???????????? phydev->duplex = DUPLEX_FULL;
> > +???????????? /* FIXME:
> > +????????????? * The current firmware always enables rate
> > adaptation mode.
> > +????????????? */
> > +???????????? phydev->rate_matching = RATE_MATCH_PAUSE;
> 
> Can we tell current firmware for future firmware? Is this actually
> fixable?
> 
We decided to always enable rate adaptation mode for MT7988's current
and future built-in 2.5GbE firmware. I'll remove FIXME comment here in
v3.

> > +???? }
> > +
> > +???? return 0;
> > +}
> > +
> 
> 
> 
> > +static int mt798x_2p5ge_phy_probe(struct phy_device *phydev)
> > +{
> > +???? struct mtk_i2p5ge_phy_priv *priv;
> > +
> > +???? priv = devm_kzalloc(&phydev->mdio.dev,
> > +???????????????????????? sizeof(struct mtk_i2p5ge_phy_priv),
> > GFP_KERNEL);
> > +???? if (!priv)
> > +???????????? return -ENOMEM;
> > +
> > +???? switch (phydev->drv->phy_id) {
> > +???? case MTK_2P5GPHY_ID_MT7988:
> > +???????????? /* The original hardware only sets MDIO_DEVS_PMAPMD
> > */
> 
> What do you mean by "original hardware"?
> 
> You use PHY_ID_MATCH_MODEL(MTK_2P5GPHY_ID_MT7988), so do you mean
> revision 0 is broken, but revision 1 fixed it?
> 
I'll fix this ambiguous comment to:
/* This built-in 2.5GbE hardware only sets MDIO_DEVS_PMAPMD. Set the  *
rest by this driver since PCS/AN/VEND1/VEND2 mmds exist.
 */

> 
> > +???????????? phydev->c45_ids.mmds_present |= MDIO_DEVS_PCS |
> > +???????????????????????????????????????????? MDIO_DEVS_AN |
> > +???????????????????????????????????????????? MDIO_DEVS_VEND1 |
> > +???????????????????????????????????????????? MDIO_DEVS_VEND2;
> > +???????????? break;
> > +???? default:
> > +???????????? return -EINVAL;
> > +???? }
> > +
> > +???? priv->fw_loaded = false;
> > +???? phydev->priv = priv;
> > +
> > +???? mtk_phy_leds_state_init(phydev);
> 
> The LEDs work without firmware?
> 
> ??? Andrew
> 
> ---
> pw-bot: cr
I'll remove this line v3 and propose LED part in later patchset.

BRs,
Sky

From SkyLake.Huang at mediatek.com  Tue May 13 04:01:57 2025
From: SkyLake.Huang at mediatek.com (=?utf-8?B?U2t5TGFrZSBIdWFuZyAo6buD5ZWf5r6kKQ==?=)
Date: Tue, 13 May 2025 11:01:57 +0000
Subject: [PATCH net-next v2 3/3] net: phy: mediatek: add driver for
 built-in 2.5G ethernet PHY on MT7988
In-Reply-To: <74ce0275952a9c60af87ded9d64ca7301fd69d0f.camel@mediatek.com>
References: <20250219083910.2255981-1-SkyLake.Huang@mediatek.com>
	 <20250219083910.2255981-4-SkyLake.Huang@mediatek.com>
	 <Z7WleP9v6Igx2MjC@shell.armlinux.org.uk>
	 <74ce0275952a9c60af87ded9d64ca7301fd69d0f.camel@mediatek.com>
Message-ID: <0f52f7d005e2bf6449568812002ee95dc9b6c346.camel@mediatek.com>

On Tue, 2025-05-13 at 18:12 +0800, SkyLake.Huang wrote:
> On Wed, 2025-02-19 at 09:33 +0000, Russell King (Oracle) wrote:
> > 
> > External email : Please do not click links or open attachments
> > until
> > you have verified the sender or the content.
> > 
> > 
> > On Wed, Feb 19, 2025 at 04:39:10PM +0800, Sky Huang wrote:
> > > +static int mt798x_2p5ge_phy_config_init(struct phy_device
> > > *phydev)
> > > +{
> > > +???? struct pinctrl *pinctrl;
> > > +???? int ret;
> > > +
> > > +???? /* Check if PHY interface type is compatible */
> > > +???? if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL)
> > > +???????????? return -ENODEV;
> > > +
> > > +???? ret = mt798x_2p5ge_phy_load_fw(phydev);
> > > +???? if (ret < 0)
> > > +???????????? return ret;
> > 
> > Firmware should not be loaded in the .config_init method. The above
> > call will block while holding the RTNL which will prevent all other
> > network configuration until the firmware has been loaded or the
> > load
> > fails.
> > 
> > Thanks.
> > 
> > --
> > RMK's Patch system:
> > https://urldefense.com/v3/__https://www.armlinux.org.uk/developer/patches/__;!!CTRNKA9wMg0ARbw!iV-1ViPFsUV-lLj7aIycan8nery6sQO3t6mkpdlb_GW8hswhxc4ejJozxqkU3s2WzxSizs4kfdC77yr7HGGRIuU$
> > FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
> 
> Actually, I wrote fw loading flow in .probe. However, during boot
> time,
> .probe is called at very early stage (about the first 2s after
> booting
> into Linux Kernel). At that time, filesystem isn't ready yet and phy
> driver can't locate /lib/firmware/mediatek/mt7988/i2p5ge-phy-pmb.bin.
> Adding "-EPROBE_DEFER" doesn't help at this moment. I'm not sure how
> aquantia and qt2025 drivers handle this.
> 
> But anyway, mt7988's built-in phy driver loads firmware in only a few
> ms. This is via internal bus instead of MDIO bus, so loading speed is
> much faster. Will this have any impact, if that's the case?
> 
> BRs,
> Sky

This message is replied in wrong place. Please ignore, thanks.

BRs,
Sky

From SkyLake.Huang at mediatek.com  Tue May 13 04:13:04 2025
From: SkyLake.Huang at mediatek.com (=?utf-8?B?U2t5TGFrZSBIdWFuZyAo6buD5ZWf5r6kKQ==?=)
Date: Tue, 13 May 2025 11:13:04 +0000
Subject: [PATCH net-next v2 3/3] net: phy: mediatek: add driver for
 built-in 2.5G ethernet PHY on MT7988
In-Reply-To: <Z77kcqzmCqdT6lE0@shell.armlinux.org.uk>
References: <20250219083910.2255981-1-SkyLake.Huang@mediatek.com>
	 <20250219083910.2255981-4-SkyLake.Huang@mediatek.com>
	 <Z7WleP9v6Igx2MjC@shell.armlinux.org.uk>
	 <5fae9c69a09320b0b24f25a178137bd0256a72d8.camel@mediatek.com>
	 <Z77kcqzmCqdT6lE0@shell.armlinux.org.uk>
Message-ID: <23205135c80c77b99fe32ef7bbe4ee421ac80bb4.camel@mediatek.com>

On Wed, 2025-02-26 at 09:52 +0000, Russell King (Oracle) wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On Wed, Feb 26, 2025 at 06:48:34AM +0000, SkyLake Huang (???) wrote:
> > On Wed, 2025-02-19 at 09:33 +0000, Russell King (Oracle) wrote:
> > > 
> > > External email : Please do not click links or open attachments
> > > until
> > > you have verified the sender or the content.
> > > 
> > > 
> > > On Wed, Feb 19, 2025 at 04:39:10PM +0800, Sky Huang wrote:
> > > > +static int mt798x_2p5ge_phy_config_init(struct phy_device
> > > > *phydev)
> > > > +{
> > > > +???? struct pinctrl *pinctrl;
> > > > +???? int ret;
> > > > +
> > > > +???? /* Check if PHY interface type is compatible */
> > > > +???? if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL)
> > > > +???????????? return -ENODEV;
> > > > +
> > > > +???? ret = mt798x_2p5ge_phy_load_fw(phydev);
> > > > +???? if (ret < 0)
> > > > +???????????? return ret;
> > > 
> > > Firmware should not be loaded in the .config_init method. The
> > > above
> > > call will block while holding the RTNL which will prevent all
> > > other
> > > network configuration until the firmware has been loaded or the
> > > load
> > > fails.
> > > 
> > > Thanks.
> > > 
> > > --
> > > RMK's Patch system:
> > > https://urldefense.com/v3/__https://www.armlinux.org.uk/developer/patches/__;!!CTRNKA9wMg0ARbw!iV-1ViPFsUV-lLj7aIycan8nery6sQO3t6mkpdlb_GW8hswhxc4ejJozxqkU3s2WzxSizs4kfdC77yr7HGGRIuU$
> > > FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
> > Hi Russell,
> > mt798x_p5ge_phy_load_fw() will only load firmware once after driver
> > is
> > probed through priv->fw_loaded. And actually, firmware loading
> > procedure only takes about 11ms. This was discussed earlier in:
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20240520113456.21675-6-SkyLake.Huang at mediatek.com/*25856462__;Iw!!CTRNKA9wMg0ARbw!lQ7b7kgD0JGOHR_CLeHtF5SF-knx3hZcm2u_tYbzgBnX91a7muRwqGhDUaP3XorHlu9qQozNX_pXDMIxO1DyVIY$
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20240520113456.21675-6-SkyLake.Huang at mediatek.com/*25857174__;Iw!!CTRNKA9wMg0ARbw!lQ7b7kgD0JGOHR_CLeHtF5SF-knx3hZcm2u_tYbzgBnX91a7muRwqGhDUaP3XorHlu9qQozNX_pXDMIxHDm1IuQ$
> 
> 1. Wouldn't it be a good idea to include the loading time in the
> patch
> ?? description or a comment in the patch?
> 
Sure. I'll include this in v3's commit message.

> 2. What about the time it takes for request_firmware() uses the sysfs
> ?? fallback, which essentially passes the firmware request to
> userspace
> ?? to deal with? That can block for an indeterminate amount of time.
> 
I'm not really sure how to achieve this. As far as I know, I can
provide fw via /sys/class/firmware/<device-name>/ after I boot into
Linux shell. But at that moment, we need to insmod phy driver again.
Users will also need to load fw file manually. This will add a lot of
complexity. Is this what upstream style expects?

> --
> RMK's Patch system:
> https://urldefense.com/v3/__https://www.armlinux.org.uk/developer/patches/__;!!CTRNKA9wMg0ARbw!lQ7b7kgD0JGOHR_CLeHtF5SF-knx3hZcm2u_tYbzgBnX91a7muRwqGhDUaP3XorHlu9qQozNX_pXDMIxE9f2xWs$
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

BRs,
Sky

From SkyLake.Huang at mediatek.com  Tue May 13 04:15:20 2025
From: SkyLake.Huang at mediatek.com (=?utf-8?B?U2t5TGFrZSBIdWFuZyAo6buD5ZWf5r6kKQ==?=)
Date: Tue, 13 May 2025 11:15:20 +0000
Subject: [PATCH net-next v2 3/3] net: phy: mediatek: add driver for
 built-in 2.5G ethernet PHY on MT7988
In-Reply-To: <73080f10-5077-4165-9fe8-e2ccca497feb@lunn.ch>
References: <20250219083910.2255981-1-SkyLake.Huang@mediatek.com>
	 <20250219083910.2255981-4-SkyLake.Huang@mediatek.com>
	 <Z7WleP9v6Igx2MjC@shell.armlinux.org.uk>
	 <5fae9c69a09320b0b24f25a178137bd0256a72d8.camel@mediatek.com>
	 <73080f10-5077-4165-9fe8-e2ccca497feb@lunn.ch>
Message-ID: <034a4ef542aec33a8ef44599114749ebd6af8ec5.camel@mediatek.com>

On Wed, 2025-02-26 at 14:32 +0100, Andrew Lunn wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On Wed, Feb 26, 2025 at 06:48:34AM +0000, SkyLake Huang (???) wrote:
> > On Wed, 2025-02-19 at 09:33 +0000, Russell King (Oracle) wrote:
> > > 
> > > External email : Please do not click links or open attachments
> > > until
> > > you have verified the sender or the content.
> > > 
> > > 
> > > On Wed, Feb 19, 2025 at 04:39:10PM +0800, Sky Huang wrote:
> > > > +static int mt798x_2p5ge_phy_config_init(struct phy_device
> > > > *phydev)
> > > > +{
> > > > +???? struct pinctrl *pinctrl;
> > > > +???? int ret;
> > > > +
> > > > +???? /* Check if PHY interface type is compatible */
> > > > +???? if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL)
> > > > +???????????? return -ENODEV;
> > > > +
> > > > +???? ret = mt798x_2p5ge_phy_load_fw(phydev);
> > > > +???? if (ret < 0)
> > > > +???????????? return ret;
> > > 
> > > Firmware should not be loaded in the .config_init method. The
> > > above
> > > call will block while holding the RTNL which will prevent all
> > > other
> > > network configuration until the firmware has been loaded or the
> > > load
> > > fails.
> > > 
> > > Thanks.
> > > 
> > > --
> > > RMK's Patch system:
> > > https://urldefense.com/v3/__https://www.armlinux.org.uk/developer/patches/__;!!CTRNKA9wMg0ARbw!iV-1ViPFsUV-lLj7aIycan8nery6sQO3t6mkpdlb_GW8hswhxc4ejJozxqkU3s2WzxSizs4kfdC77yr7HGGRIuU$
> > > FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
> > Hi Russell,
> > mt798x_p5ge_phy_load_fw() will only load firmware once after driver
> > is
> > probed through priv->fw_loaded. And actually, firmware loading
> > procedure only takes about 11ms. This was discussed earlier in:
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20240520113456.21675-6-SkyLake.Huang at mediatek.com/*25856462__;Iw!!CTRNKA9wMg0ARbw!nEJAqWq9eSPyvD4sikg0DKqNCU5OPGCJx42J6muU1dWrHsNliA4BR1OU7r_XBf53OC02GphE1odIIYTT6687$
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20240520113456.21675-6-SkyLake.Huang at mediatek.com/*25857174__;Iw!!CTRNKA9wMg0ARbw!nEJAqWq9eSPyvD4sikg0DKqNCU5OPGCJx42J6muU1dWrHsNliA4BR1OU7r_XBf53OC02GphE1odIIc2tO_Yi$
> 
> Ideally, all PHY drivers should look like each other. That makes
> maintenance simpler. Currently, air_en8811h.c, aquantia_main.c, and
> qt2025.rs load firmware in there probe function. Is there a good
> reason this driver needs to be different?
> 
> ?????? Andrew
  Actually, I wrote fw loading flow in .probe at first. However, during
boot time, .probe is called at very early stage (about the first 2s
after booting into Linux Kernel). At that time, filesystem isn't ready
yet and phy driver can't locate /lib/firmware/mediatek/mt7988/i2p5ge-
phy-pmb.bin. Also, adding "-EPROBE_DEFER" doesn't help.
  I'm not sure how aquantia and qt2025 drivers handle this.

BRs,
Sky

From andrew at lunn.ch  Tue May 13 05:32:40 2025
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 13 May 2025 14:32:40 +0200
Subject: [PATCH net-next v2 3/3] net: phy: mediatek: add driver for
 built-in 2.5G ethernet PHY on MT7988
In-Reply-To: <74ce0275952a9c60af87ded9d64ca7301fd69d0f.camel@mediatek.com>
References: <20250219083910.2255981-1-SkyLake.Huang@mediatek.com>
 <20250219083910.2255981-4-SkyLake.Huang@mediatek.com>
 <Z7WleP9v6Igx2MjC@shell.armlinux.org.uk>
 <74ce0275952a9c60af87ded9d64ca7301fd69d0f.camel@mediatek.com>
Message-ID: <8b67fa4c-a07a-4941-ba7b-23d4e1104451@lunn.ch>

On Tue, May 13, 2025 at 10:12:04AM +0000, SkyLake Huang (???) wrote:
> On Wed, 2025-02-19 at 09:33 +0000, Russell King (Oracle) wrote:
> > 
> > External email : Please do not click links or open attachments until
> > you have verified the sender or the content.
> > 
> > 
> > On Wed, Feb 19, 2025 at 04:39:10PM +0800, Sky Huang wrote:
> > > +static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
> > > +{
> > > +???? struct pinctrl *pinctrl;
> > > +???? int ret;
> > > +
> > > +???? /* Check if PHY interface type is compatible */
> > > +???? if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL)
> > > +???????????? return -ENODEV;
> > > +
> > > +???? ret = mt798x_2p5ge_phy_load_fw(phydev);
> > > +???? if (ret < 0)
> > > +???????????? return ret;
> > 
> > Firmware should not be loaded in the .config_init method. The above
> > call will block while holding the RTNL which will prevent all other
> > network configuration until the firmware has been loaded or the load
> > fails.
> > 
> > Thanks.
> > 
> > --
> > RMK's Patch system:
> > https://urldefense.com/v3/__https://www.armlinux.org.uk/developer/patches/__;!!CTRNKA9wMg0ARbw!iV-1ViPFsUV-lLj7aIycan8nery6sQO3t6mkpdlb_GW8hswhxc4ejJozxqkU3s2WzxSizs4kfdC77yr7HGGRIuU$
> > FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
> 
> Actually, I wrote fw loading flow in .probe. However, during boot time,
> .probe is called at very early stage (about the first 2s after booting
> into Linux Kernel). At that time, filesystem isn't ready yet and phy
> driver can't locate /lib/firmware/mediatek/mt7988/i2p5ge-phy-pmb.bin.

Tell Dracut or whatever you are using to build the initramfs to
include the firmware. That is what MODULE_FIRMWARE() is for.

	Andrew


From bvanassche at acm.org  Tue May 13 06:42:04 2025
From: bvanassche at acm.org (Bart Van Assche)
Date: Tue, 13 May 2025 06:42:04 -0700
Subject: [PATCH v2] ufs: core: support updating device command timeout
In-Reply-To: <20250510080345.595798-1-peter.wang@mediatek.com>
References: <20250510080345.595798-1-peter.wang@mediatek.com>
Message-ID: <4420fcd0-5125-43b1-89ff-c3e5edad2939@acm.org>

On 5/10/25 1:01 AM, peter.wang at mediatek.com wrote:
> V2:
> - Change minimun value to 1ms

For future patch submissions, please include the changelog below the
triple dash (---) such that it doesn't appear in the kernel changelog.

Thanks,

Bart.


From daniel.lezcano at linaro.org  Tue May 13 07:24:51 2025
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Tue, 13 May 2025 16:24:51 +0200
Subject: [PATCH v5 0/7] Add EcoNet EN751221 MIPS platform support
In-Reply-To: <20250507134500.390547-1-cjd@cjdns.fr>
References: <20250507134500.390547-1-cjd@cjdns.fr>
Message-ID: <aCNWM5Xq7wnHVCrc@mai.linaro.org>

On Wed, May 07, 2025 at 01:44:53PM +0000, Caleb James DeLisle wrote:
> EcoNet MIPS SoCs are big endian machines based on 34Kc and 1004Kc
> processors. They are found in xDSL and xPON modems, and contain PCM
> (VoIP), Ethernet, USB, GPIO, I2C, SPI (Flash), UART, and PCIe.
> 
> The EcoNet MIPS SoCs are divided broadly into two families, the
> EN751221 family based on the 34Kc, and the EN751627 family based on
> the 1004Kc. Individual SoCs within a family are very similar, only
> with different peripherals.
> 
> This patchset adds basic "boots to a console" support for the EN751221
> family and adds SmartFiber XP8421-B, a low cost commercially available
> board that is useful for testing and development.
> 
> Note that Airoha (AN7523, AN7581) is similar to EcoNet in terms of
> peripherals, and for historical reasons Airoha chips are sometimes
> referred to with the EN75xx prefix. However this is a different
> platform because Airoha chips are ARM based.
> 
> This patchset is against mips-next.
> 
> v4 -> v5
> * 2/7 clocksource/drivers: Add EcoNet Timer HPT driver:
>   * Improve explanation of HPT timer in changelog
>   * Move pr_info to pr_debug per recommendation
>   * Remove pointless debug on spurious interrupt
>   * Small code-style change

Shall I pick the clocksource + bindings changes through my tree ?

-- 

 <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog


From cjd at cjdns.fr  Tue May 13 07:31:05 2025
From: cjd at cjdns.fr (Caleb James DeLisle)
Date: Tue, 13 May 2025 16:31:05 +0200
Subject: [PATCH v5 0/7] Add EcoNet EN751221 MIPS platform support
In-Reply-To: <aCNWM5Xq7wnHVCrc@mai.linaro.org>
References: <20250507134500.390547-1-cjd@cjdns.fr>
 <aCNWM5Xq7wnHVCrc@mai.linaro.org>
Message-ID: <45166de2-8504-484d-90f6-6ef97c650b61@cjdns.fr>


On 13/05/2025 16:24, Daniel Lezcano wrote:
> On Wed, May 07, 2025 at 01:44:53PM +0000, Caleb James DeLisle wrote:
>> EcoNet MIPS SoCs are big endian machines based on 34Kc and 1004Kc
>> processors. They are found in xDSL and xPON modems, and contain PCM
>> (VoIP), Ethernet, USB, GPIO, I2C, SPI (Flash), UART, and PCIe.
>>
>> The EcoNet MIPS SoCs are divided broadly into two families, the
>> EN751221 family based on the 34Kc, and the EN751627 family based on
>> the 1004Kc. Individual SoCs within a family are very similar, only
>> with different peripherals.
>>
>> This patchset adds basic "boots to a console" support for the EN751221
>> family and adds SmartFiber XP8421-B, a low cost commercially available
>> board that is useful for testing and development.
>>
>> Note that Airoha (AN7523, AN7581) is similar to EcoNet in terms of
>> peripherals, and for historical reasons Airoha chips are sometimes
>> referred to with the EN75xx prefix. However this is a different
>> platform because Airoha chips are ARM based.
>>
>> This patchset is against mips-next.
>>
>> v4 -> v5
>> * 2/7 clocksource/drivers: Add EcoNet Timer HPT driver:
>>    * Improve explanation of HPT timer in changelog
>>    * Move pr_info to pr_debug per recommendation
>>    * Remove pointless debug on spurious interrupt
>>    * Small code-style change
> Shall I pick the clocksource + bindings changes through my tree ?
>
I'm new here so I don't know what that means for the merges which
will happen later, but I don't see any reason to do otherwise.


Thanks,

Caleb




From daniel.lezcano at linaro.org  Tue May 13 08:26:16 2025
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Tue, 13 May 2025 17:26:16 +0200
Subject: [PATCH v5 0/7] Add EcoNet EN751221 MIPS platform support
In-Reply-To: <45166de2-8504-484d-90f6-6ef97c650b61@cjdns.fr>
References: <20250507134500.390547-1-cjd@cjdns.fr>
 <aCNWM5Xq7wnHVCrc@mai.linaro.org>
 <45166de2-8504-484d-90f6-6ef97c650b61@cjdns.fr>
Message-ID: <aCNkmCJK1wOLGmgy@mai.linaro.org>

On Tue, May 13, 2025 at 04:31:05PM +0200, Caleb James DeLisle wrote:
> 
> On 13/05/2025 16:24, Daniel Lezcano wrote:
> > On Wed, May 07, 2025 at 01:44:53PM +0000, Caleb James DeLisle wrote:
> > > EcoNet MIPS SoCs are big endian machines based on 34Kc and 1004Kc
> > > processors. They are found in xDSL and xPON modems, and contain PCM
> > > (VoIP), Ethernet, USB, GPIO, I2C, SPI (Flash), UART, and PCIe.
> > > 
> > > The EcoNet MIPS SoCs are divided broadly into two families, the
> > > EN751221 family based on the 34Kc, and the EN751627 family based on
> > > the 1004Kc. Individual SoCs within a family are very similar, only
> > > with different peripherals.
> > > 
> > > This patchset adds basic "boots to a console" support for the EN751221
> > > family and adds SmartFiber XP8421-B, a low cost commercially available
> > > board that is useful for testing and development.
> > > 
> > > Note that Airoha (AN7523, AN7581) is similar to EcoNet in terms of
> > > peripherals, and for historical reasons Airoha chips are sometimes
> > > referred to with the EN75xx prefix. However this is a different
> > > platform because Airoha chips are ARM based.
> > > 
> > > This patchset is against mips-next.
> > > 
> > > v4 -> v5
> > > * 2/7 clocksource/drivers: Add EcoNet Timer HPT driver:
> > >    * Improve explanation of HPT timer in changelog
> > >    * Move pr_info to pr_debug per recommendation
> > >    * Remove pointless debug on spurious interrupt
> > >    * Small code-style change
> > Shall I pick the clocksource + bindings changes through my tree ?
> > 
> I'm new here so I don't know what that means for the merges which
> will happen later, but I don't see any reason to do otherwise.

The series introduces a new platform. The patches are touching
different susystems managed by different maintainers.

Usually, the changes are per subsystem, except when they are
interdependant.

Here you can choose to merge all the patches through the mips tree or
let the different maintainers to pick the changes related to the
subsystems they handle. You should clarify that in the cover
letter. If you choose the first alternative, then before merging the
changes, all maintainer should have blessed the patches with their
acked-by.


-- 

 <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog


From cjd at cjdns.fr  Tue May 13 08:53:24 2025
From: cjd at cjdns.fr (Caleb James DeLisle)
Date: Tue, 13 May 2025 17:53:24 +0200
Subject: [PATCH v5 0/7] Add EcoNet EN751221 MIPS platform support
In-Reply-To: <aCNkmCJK1wOLGmgy@mai.linaro.org>
References: <20250507134500.390547-1-cjd@cjdns.fr>
 <aCNWM5Xq7wnHVCrc@mai.linaro.org>
 <45166de2-8504-484d-90f6-6ef97c650b61@cjdns.fr>
 <aCNkmCJK1wOLGmgy@mai.linaro.org>
Message-ID: <927c8a59-ac1b-49dc-b889-22c3a65bb49c@cjdns.fr>


On 13/05/2025 17:26, Daniel Lezcano wrote:
> On Tue, May 13, 2025 at 04:31:05PM +0200, Caleb James DeLisle wrote:
>> On 13/05/2025 16:24, Daniel Lezcano wrote:
>>> On Wed, May 07, 2025 at 01:44:53PM +0000, Caleb James DeLisle wrote:
>>>> EcoNet MIPS SoCs are big endian machines based on 34Kc and 1004Kc
>>>> processors. They are found in xDSL and xPON modems, and contain PCM
>>>> (VoIP), Ethernet, USB, GPIO, I2C, SPI (Flash), UART, and PCIe.
>>>>
>>>> The EcoNet MIPS SoCs are divided broadly into two families, the
>>>> EN751221 family based on the 34Kc, and the EN751627 family based on
>>>> the 1004Kc. Individual SoCs within a family are very similar, only
>>>> with different peripherals.
>>>>
>>>> This patchset adds basic "boots to a console" support for the EN751221
>>>> family and adds SmartFiber XP8421-B, a low cost commercially available
>>>> board that is useful for testing and development.
>>>>
>>>> Note that Airoha (AN7523, AN7581) is similar to EcoNet in terms of
>>>> peripherals, and for historical reasons Airoha chips are sometimes
>>>> referred to with the EN75xx prefix. However this is a different
>>>> platform because Airoha chips are ARM based.
>>>>
>>>> This patchset is against mips-next.
>>>>
>>>> v4 -> v5
>>>> * 2/7 clocksource/drivers: Add EcoNet Timer HPT driver:
>>>>     * Improve explanation of HPT timer in changelog
>>>>     * Move pr_info to pr_debug per recommendation
>>>>     * Remove pointless debug on spurious interrupt
>>>>     * Small code-style change
>>> Shall I pick the clocksource + bindings changes through my tree ?
>>>
>> I'm new here so I don't know what that means for the merges which
>> will happen later, but I don't see any reason to do otherwise.
> The series introduces a new platform. The patches are touching
> different susystems managed by different maintainers.
>
> Usually, the changes are per subsystem, except when they are
> interdependant.
>
> Here you can choose to merge all the patches through the mips tree or
> let the different maintainers to pick the changes related to the
> subsystems they handle. You should clarify that in the cover
> letter. If you choose the first alternative, then before merging the
> changes, all maintainer should have blessed the patches with their
> acked-by.
>
Thank you for the explanation, this patchset has already started to be
taken piece-wise, and the only dependency that comes to mind
is the econet vendor prefix which Rob Herring took few weeks ago.

With that said, I see no reason not to continue taking it piece-wise.

Thanks,

Caleb



From nfraprado at collabora.com  Tue May 13 08:59:53 2025
From: nfraprado at collabora.com (=?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?=)
Date: Tue, 13 May 2025 11:59:53 -0400
Subject: [PATCH] arm64: dts: mediatek: mt8395-genio-1200-evk: Describe CPU
 supplies
Message-ID: <20250513-genio-1200-evk-cpu-supplies-v1-1-6f0066bb93db@collabora.com>

The Genio 1200 EVK board has the big and little CPU clusters fed by the
same regulators as MT8195-Cherry boards, so describe them in the same
way as commit 17b33dd9e4a3 ("arm64: dts: mediatek: cherry: Describe CPU
supplies").

This prevents the system from hanging during boot in the case that the
cpufreq-mediatek-hw driver tries to probe before the drivers for the
regulators have probed (which happens when using the current defconfig).

Fixes: f2b543a191b6 ("arm64: dts: mediatek: add device-tree for Genio 1200 EVK board")
Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
---
 .../boot/dts/mediatek/mt8395-genio-1200-evk.dts    | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
index be5e5f339e811728e91b1ffec45ada25f9b0208b..a71f1b70b0fd61792ac29e9568c30f723ed7c162 100644
--- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
@@ -179,6 +179,38 @@ wifi_fixed_3v3: regulator-2 {
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu1 {
+	cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu2 {
+	cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu3 {
+	cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&mt6315_6_vbuck1>;
+};
+
+&cpu5 {
+	cpu-supply = <&mt6315_6_vbuck1>;
+};
+
+&cpu6 {
+	cpu-supply = <&mt6315_6_vbuck1>;
+};
+
+&cpu7 {
+	cpu-supply = <&mt6315_6_vbuck1>;
+};
+
 &disp_pwm0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&disp_pwm0_pins>;

---
base-commit: edef457004774e598fc4c1b7d1d4f0bcd9d0bb30
change-id: 20250513-genio-1200-evk-cpu-supplies-8c435c203d89

Best regards,
-- 
N?colas F. R. A. Prado <nfraprado at collabora.com>



From Paul-pl.Chen at mediatek.com  Tue May 13 09:11:38 2025
From: Paul-pl.Chen at mediatek.com (=?utf-8?B?UGF1bC1wbCBDaGVuICjpmbPmn4/pnJYp?=)
Date: Tue, 13 May 2025 16:11:38 +0000
Subject: [PATCH v2 14/15] drm/mediatek: Add support for multiple mmsys in
 the one mediatek-drm driver
In-Reply-To: <6bf9d4b3e060461ec491a3703d7ba952f9c5dceb.camel@mediatek.com>
References: <20250321093435.94835-1-paul-pl.chen@mediatek.com>
	 <20250321093435.94835-15-paul-pl.chen@mediatek.com>
	 <6bf9d4b3e060461ec491a3703d7ba952f9c5dceb.camel@mediatek.com>
Message-ID: <a917b57f4392e1cba5798d97da4c4b24f1a5e990.camel@mediatek.com>

On Tue, 2025-03-25 at 03:44 +0000, CK Hu (???) wrote:
> On Fri, 2025-03-21 at 17:33 +0800, paul-pl.chen wrote:
> > From: Nancy Lin <nancy.lin at mediatek.com>
> > 
> > To support multiple mmsys instances in the one mediatek-drm
> > instance,
> > providing improved flexibility and scalability by the following
> > changes:
> > 
> > 1. Add DDP_COMPONENT_DRM_OVLSYS_ADAPTOR* to probe the
> > ? ovlsys_adaptor drivers and support different mmsys composition.
> > 2. Added new component types MTK_DISP_VIRTUAL to support the
> > ? routing to virtual display components.
> > 3. Added and adjusted the existed structure or interface to extend
> > ? the support of multiple mmsys instances.
> > 4. Modified the component matching and binding logic to support
> > ? multiple mmsys instances.
> > 
> > Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
> > Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
> > ---
> 
> [snip]
> 
> > ?
> > +enum mtk_drm_mmsys {
> > +	DISPSYS0,
> > +	DISPSYS1,
> > +	OVLSYS0,
> > +	OVLSYS1,
> > +	MAX_MMSYS,
> > +};
> 
> Let ovlsys sub driver control OVLSYS0 and OVLSYS1, so mediatek drm
> driver would not see them and this patch is not necessary.
> 
> Regards,
> CK
> 
> 
Hi CK, 

The DRM Driver needs the distinguish between ovlsys0,
ovlsys1, dispsys0, dispsys1 to connect the main, ext, third
CRTC Paths.


"ovlsys sub driver control OVLSYS0 and OVLSYS1, so mediatek drm
driver would not see them and this patch" 

This is significant change, we will fix this modification at the 
next version.

 

Best, Paul
> 
> 
> 
> 


From Paul-pl.Chen at mediatek.com  Tue May 13 09:22:42 2025
From: Paul-pl.Chen at mediatek.com (=?utf-8?B?UGF1bC1wbCBDaGVuICjpmbPmn4/pnJYp?=)
Date: Tue, 13 May 2025 16:22:42 +0000
Subject: [PATCH v2 09/15] drm/mediatek: Refine OVL format convert API and
 export to public
In-Reply-To: <da55e0ef9165d18a7af96fb9e2c2d6c2b47c0f1b.camel@mediatek.com>
References: <20250321093435.94835-1-paul-pl.chen@mediatek.com>
	 <20250321093435.94835-10-paul-pl.chen@mediatek.com>
	 <da55e0ef9165d18a7af96fb9e2c2d6c2b47c0f1b.camel@mediatek.com>
Message-ID: <726e9bd53f4b224e964728132623df7bff5bc398.camel@mediatek.com>

On Tue, 2025-03-25 at 02:57 +0000, CK Hu (???) wrote:
> On Fri, 2025-03-21 at 17:33 +0800, paul-pl.chen wrote:
> > From: Nancy Lin <nancy.lin at mediatek.com>
> > 
> > Refine OVL format convert API and export to public.
> > 
> > Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
> > Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
> > ---
> > ?drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 158 ++++++++++++++++----
> > ----
> > ?drivers/gpu/drm/mediatek/mtk_disp_ovl.h |? 16 +++
> > ?2 files changed, 122 insertions(+), 52 deletions(-)
> > ?create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl.h
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > index d0581c4e3c99..e2b125a717c6 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > @@ -18,6 +18,7 @@
> > ?#include "mtk_crtc.h"
> > ?#include "mtk_ddp_comp.h"
> > ?#include "mtk_disp_drv.h"
> > +#include "mtk_disp_ovl.h"
> > ?#include "mtk_drm_drv.h"
> > ?
> > ?#define DISP_REG_OVL_INTEN			0x0004
> > @@ -62,22 +63,15 @@
> > ?/* OVL_CON_RGB_SWAP works only if OVL_CON_CLRFMT_MAN is enabled */
> > ?#define OVL_CON_RGB_SWAP	BIT(25)
> > ?
> > -#define OVL_CON_CLRFMT_RGB	(1 << 12)
> > -#define OVL_CON_CLRFMT_ARGB8888	(2 << 12)
> > -#define OVL_CON_CLRFMT_RGBA8888	(3 << 12)
> > -#define OVL_CON_CLRFMT_ABGR8888	(OVL_CON_CLRFMT_ARGB8888 |
> > OVL_CON_BYTE_SWAP)
> > -#define OVL_CON_CLRFMT_BGRA8888	(OVL_CON_CLRFMT_RGBA8888 |
> > OVL_CON_BYTE_SWAP)
> > -#define OVL_CON_CLRFMT_UYVY	(4 << 12)
> > -#define OVL_CON_CLRFMT_YUYV	(5 << 12)
> > -#define OVL_CON_MTX_YUV_TO_RGB	(6 << 16)
> > -#define OVL_CON_CLRFMT_PARGB8888 ((3 << 12) | OVL_CON_CLRFMT_MAN)
> > -#define OVL_CON_CLRFMT_PABGR8888 (OVL_CON_CLRFMT_PARGB8888 |
> > OVL_CON_RGB_SWAP)
> > -#define OVL_CON_CLRFMT_PBGRA8888 (OVL_CON_CLRFMT_PARGB8888 |
> > OVL_CON_BYTE_SWAP)
> > -#define OVL_CON_CLRFMT_PRGBA8888 (OVL_CON_CLRFMT_PABGR8888 |
> > OVL_CON_BYTE_SWAP)
> > -#define OVL_CON_CLRFMT_RGB565(ovl)	((ovl)->data-
> > >fmt_rgb565_is_0 ? \
> > -					0 : OVL_CON_CLRFMT_RGB)
> > -#define OVL_CON_CLRFMT_RGB888(ovl)	((ovl)->data-
> > >fmt_rgb565_is_0 ? \
> > -					OVL_CON_CLRFMT_RGB : 0)
> > +#define OVL_CON_CLRFMT_RGB565(shift)	(0 << (shift))
> > +#define OVL_CON_CLRFMT_RGB888(shift)	(1 << (shift))
> > +#define OVL_CON_CLRFMT_ARGB8888(shift)	(2 << (shift))
> > +#define OVL_CON_CLRFMT_RGBA8888(shift)	(3 << (shift))
> > +#define OVL_CON_CLRFMT_UYVY(shift)	(4 << (shift))
> > +#define OVL_CON_CLRFMT_YUYV(shift)	(5 << (shift))
> > +#define OVL_CON_MTX_YUV_TO_RGB		(6 << 16)
> > +#define OVL_CON_CLRFMT_PARGB8888(shift, man) ((3 << (shift)) |
> > (man))
> > +
> > ?#define	OVL_CON_AEN		BIT(8)
> > ?#define	OVL_CON_ALPHA		0xff
> > ?#define	OVL_CON_VIRT_FLIP	BIT(9)
> > @@ -85,7 +79,7 @@
> > ?
> > ?#define OVL_COLOR_ALPHA		GENMASK(31, 24)
> > ?
> > -static inline bool is_10bit_rgb(u32 fmt)
> > +bool mtk_ovl_is_10bit_rgb(unsigned int fmt)
> > ?{
> > ?	switch (fmt) {
> > ?	case DRM_FORMAT_XRGB2101010:
> > @@ -295,7 +289,7 @@ static void mtk_ovl_set_bit_depth(struct device
> > *dev, int idx, u32 format,
> > ?	if (!ovl->data->supports_clrfmt_ext)
> > ?		return;
> > ?
> > -	if (is_10bit_rgb(format))
> > +	if (mtk_ovl_is_10bit_rgb(format))
> > ?		bit_depth = OVL_CON_CLRFMT_10_BIT;
> > ?
> > ?	mtk_ddp_write_mask(cmdq_pkt,
> > OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx),
> > @@ -394,10 +388,26 @@ void mtk_ovl_layer_off(struct device *dev,
> > unsigned int idx,
> > ?		????? DISP_REG_OVL_RDMA_CTRL(idx));
> > ?}
> > ?
> > -static unsigned int mtk_ovl_fmt_convert(struct mtk_disp_ovl *ovl,
> > -					struct mtk_plane_state
> > *state)
> > +bool mtk_ovl_is_ignore_pixel_alpha(struct mtk_plane_state *state,
> > unsigned int blend_mode)
> > +{
> 
> This modification is not related to the title, so separate to another
> patch.
> 
Sure, I will separate to another patch.
> > +	if (!state->base.fb)
> > +		return false;
> > +
> > +	/*
> > +	 * Although the alpha channel can be ignored, CONST_BLD
> > must be enabled
> > +	 * for XRGB format, otherwise OVL will still read the
> > value from memory.
> > +	 * For RGB888 related formats, whether CONST_BLD is
> > enabled or not won't
> > +	 * affect the result. Therefore we use !has_alpha as the
> > condition.
> > +	 */
> > +
> > +	if (blend_mode == DRM_MODE_BLEND_PIXEL_NONE || !state-
> > >base.fb->format->has_alpha)
> > +		return true;
> > +
> > +	return false;
> > +}
> > +
> > +unsigned int mtk_ovl_get_blend_mode(struct mtk_plane_state *state,
> > unsigned int blend_modes)
> > ?{
> > -	unsigned int fmt = state->pending.format;
> > ?	unsigned int blend_mode = DRM_MODE_BLEND_COVERAGE;
> > ?
> > ?	/*
> > @@ -412,52 +422,102 @@ static unsigned int
> > mtk_ovl_fmt_convert(struct mtk_disp_ovl *ovl,
> > ?	 * will get an error return from
> > drm_plane_create_blend_mode_property() and
> > ?	 * state->base.pixel_blend_mode should not be used.
> > ?	 */
> > -	if (ovl->data->blend_modes & BIT(DRM_MODE_BLEND_PREMULTI))
> > +	if (blend_modes & BIT(DRM_MODE_BLEND_PREMULTI))
> > ?		blend_mode = state->base.pixel_blend_mode;
> > ?
> > +	return blend_mode;
> > +}
> > +
> > +unsigned int mtk_ovl_fmt_convert(unsigned int fmt, unsigned int
> > blend_mode,
> > +				 bool fmt_rgb565_is_0, bool
> > color_convert,
> > +				 u8 clrfmt_shift, u32 clrfmt_man,
> > u32 byte_swap, u32 rgb_swap)
> > +{
> > +	unsigned int con = 0;
> > +	bool need_byte_swap = false, need_rgb_swap = false;
> > +
> > ?	switch (fmt) {
> > ?	default:
> > ?	case DRM_FORMAT_RGB565:
> > -		return OVL_CON_CLRFMT_RGB565(ovl);
> > +		con = fmt_rgb565_is_0 ?
> > +			OVL_CON_CLRFMT_RGB565(clrfmt_shift) :
> > OVL_CON_CLRFMT_RGB888(clrfmt_shift);
> > +	break;
> > ?	case DRM_FORMAT_BGR565:
> > -		return OVL_CON_CLRFMT_RGB565(ovl) |
> > OVL_CON_BYTE_SWAP;
> > +		con = fmt_rgb565_is_0 ?
> > +			OVL_CON_CLRFMT_RGB565(clrfmt_shift) :
> > OVL_CON_CLRFMT_RGB888(clrfmt_shift);
> > +		need_byte_swap = true;	/* RGB565 -> BGR565 */
> > +	break;
> > ?	case DRM_FORMAT_RGB888:
> > -		return OVL_CON_CLRFMT_RGB888(ovl);
> > +		con = fmt_rgb565_is_0 ?
> > +			OVL_CON_CLRFMT_RGB888(clrfmt_shift) :
> > OVL_CON_CLRFMT_RGB565(clrfmt_shift);
> > +	break;
> > ?	case DRM_FORMAT_BGR888:
> > -		return OVL_CON_CLRFMT_RGB888(ovl) |
> > OVL_CON_BYTE_SWAP;
> > +		con = fmt_rgb565_is_0 ?
> > +			OVL_CON_CLRFMT_RGB888(clrfmt_shift) :
> > OVL_CON_CLRFMT_RGB565(clrfmt_shift);
> > +		need_byte_swap = true;	/* RGB888 -> BGR888 */
> > +	break;
> > ?	case DRM_FORMAT_RGBX8888:
> > ?	case DRM_FORMAT_RGBA8888:
> > ?	case DRM_FORMAT_RGBX1010102:
> > ?	case DRM_FORMAT_RGBA1010102:
> > -		return blend_mode == DRM_MODE_BLEND_COVERAGE ?
> > -		?????? OVL_CON_CLRFMT_RGBA8888 :
> > -		?????? OVL_CON_CLRFMT_PRGBA8888;
> > +		if (blend_mode == DRM_MODE_BLEND_COVERAGE) {
> > +			con =
> > OVL_CON_CLRFMT_RGBA8888(clrfmt_shift);
> > +		} else {
> > +			con =
> > OVL_CON_CLRFMT_PARGB8888(clrfmt_shift, clrfmt_man);
> > +			need_byte_swap = true;	/* PARGB8888 ->
> > PBGRA8888 */
> > +			need_rgb_swap = true;	/* PBGRA8888 ->
> > PRGBA8888 */
> > +		}
> > +	break;
> > ?	case DRM_FORMAT_BGRX8888:
> > ?	case DRM_FORMAT_BGRA8888:
> > ?	case DRM_FORMAT_BGRX1010102:
> > ?	case DRM_FORMAT_BGRA1010102:
> > -		return blend_mode == DRM_MODE_BLEND_COVERAGE ?
> > -		?????? OVL_CON_CLRFMT_BGRA8888 :
> > -		?????? OVL_CON_CLRFMT_PBGRA8888;
> > +		if (blend_mode == DRM_MODE_BLEND_COVERAGE) {
> > +			con =
> > OVL_CON_CLRFMT_RGBA8888(clrfmt_shift);
> > +			need_byte_swap = true;	/* RGB8888 ->
> > BGR8888 */
> > +		} else {
> > +			con =
> > OVL_CON_CLRFMT_PARGB8888(clrfmt_shift, clrfmt_man);
> > +			need_byte_swap = true;	/* PARGB8888 ->
> > PBGRA8888 */
> > +		}
> > +	break;
> > ?	case DRM_FORMAT_XRGB8888:
> > ?	case DRM_FORMAT_ARGB8888:
> > ?	case DRM_FORMAT_XRGB2101010:
> > ?	case DRM_FORMAT_ARGB2101010:
> > -		return blend_mode == DRM_MODE_BLEND_COVERAGE ?
> > -		?????? OVL_CON_CLRFMT_ARGB8888 :
> > -		?????? OVL_CON_CLRFMT_PARGB8888;
> > +		if (blend_mode == DRM_MODE_BLEND_COVERAGE)
> > +			con =
> > OVL_CON_CLRFMT_ARGB8888(clrfmt_shift);
> > +		else
> > +			con =
> > OVL_CON_CLRFMT_PARGB8888(clrfmt_shift, clrfmt_man);
> > +	break;
> > ?	case DRM_FORMAT_XBGR8888:
> > ?	case DRM_FORMAT_ABGR8888:
> > ?	case DRM_FORMAT_XBGR2101010:
> > ?	case DRM_FORMAT_ABGR2101010:
> > -		return blend_mode == DRM_MODE_BLEND_COVERAGE ?
> > -		?????? OVL_CON_CLRFMT_ABGR8888 :
> > -		?????? OVL_CON_CLRFMT_PABGR8888;
> > +		if (blend_mode == DRM_MODE_BLEND_COVERAGE) {
> > +			con =
> > OVL_CON_CLRFMT_ARGB8888(clrfmt_shift);
> > +			need_rgb_swap = true;	/* ARGB8888 ->
> > ABGR8888 */
> > +		} else {
> > +			con =
> > OVL_CON_CLRFMT_PARGB8888(clrfmt_shift, clrfmt_man);
> > +			need_rgb_swap = true;	/* PARGB8888 ->
> > PABGR8888 */
> > +		}
> > +	break;
> > ?	case DRM_FORMAT_UYVY:
> > -		return OVL_CON_CLRFMT_UYVY |
> > OVL_CON_MTX_YUV_TO_RGB;
> > +		con = OVL_CON_CLRFMT_UYVY(clrfmt_shift);
> > +	break;
> > ?	case DRM_FORMAT_YUYV:
> > -		return OVL_CON_CLRFMT_YUYV |
> > OVL_CON_MTX_YUV_TO_RGB;
> > +		con = OVL_CON_CLRFMT_YUYV(clrfmt_shift);
> > +	break;
> > ?	}
> > +
> > +	if (color_convert)
> > +		con |= OVL_CON_MTX_YUV_TO_RGB;
> 
> Only YUV need this. RGB do not need this.
> 
> OK I will fix this part.
> > +
> > +	if (need_byte_swap)
> > +		con |= byte_swap;
> > +
> > +	if (need_rgb_swap)
> > +		con |= rgb_swap;
> > +
> > +	return con;
> > ?}
> > ?
> > ?static void mtk_ovl_afbc_layer_config(struct mtk_disp_ovl *ovl,
> > @@ -495,7 +555,7 @@ void mtk_ovl_layer_config(struct device *dev,
> > unsigned int idx,
> > ?	unsigned int rotation = pending->rotation;
> > ?	unsigned int offset = (pending->y << 16) | pending->x;
> > ?	unsigned int src_size = (pending->height << 16) | pending-
> > >width;
> > -	unsigned int blend_mode = state->base.pixel_blend_mode;
> > +	unsigned int blend_mode = mtk_ovl_get_blend_mode(state,
> > ovl->data->blend_modes);
> 
> This modification is not related to the title, so separate to another
> patch.
> 
> Sure, I will separate to another patch.
> > ?	unsigned int ignore_pixel_alpha = 0;
> > ?	unsigned int con;
> > ?
> > @@ -504,7 +564,8 @@ void mtk_ovl_layer_config(struct device *dev,
> > unsigned int idx,
> > ?		return;
> > ?	}
> > ?
> > -	con = mtk_ovl_fmt_convert(ovl, state);
> > +	con = mtk_ovl_fmt_convert(fmt, blend_mode, ovl->data-
> > >fmt_rgb565_is_0, true,
> > +				? 12, OVL_CON_CLRFMT_MAN,
> > OVL_CON_BYTE_SWAP, OVL_CON_RGB_SWAP);
> > ?	if (state->base.fb) {
> > ?		con |= state->base.alpha & OVL_CON_ALPHA;
> > ?
> > @@ -512,17 +573,8 @@ void mtk_ovl_layer_config(struct device *dev,
> > unsigned int idx,
> > ?		 * For blend_modes supported SoCs, always enable
> > alpha blending.
> > ?		 * For blend_modes unsupported SoCs, enable alpha
> > blending when has_alpha is set.
> > ?		 */
> > -		if (blend_mode || state->base.fb->format-
> > >has_alpha)
> > +		if (state->base.pixel_blend_mode || state-
> > >base.fb->format->has_alpha)
> 
> This modification is not related to the title, so separate to another
> patch.
> 
> Sure, I will separate to another patch.

> > ?			con |= OVL_CON_AEN;
> > -
> > -		/*
> > -		 * Although the alpha channel can be ignored,
> > CONST_BLD must be enabled
> > -		 * for XRGB format, otherwise OVL will still read
> > the value from memory.
> > -		 * For RGB888 related formats, whether CONST_BLD
> > is enabled or not won't
> > -		 * affect the result. Therefore we use !has_alpha
> > as the condition.
> > -		 */
> > -		if (blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
> > !state->base.fb->format->has_alpha)
> > -			ignore_pixel_alpha = OVL_CONST_BLEND;
> > ?	}
> > ?
> > ?	/*
> > @@ -548,6 +600,8 @@ void mtk_ovl_layer_config(struct device *dev,
> > unsigned int idx,
> > ?
> > ?	mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl-
> > >regs,
> > ?			????? DISP_REG_OVL_CON(idx));
> > +
> > +	ignore_pixel_alpha = mtk_ovl_is_ignore_pixel_alpha(state,
> > blend_mode) ? OVL_CONST_BLEND : 0;
> > ?	mtk_ddp_write_relaxed(cmdq_pkt, pitch_lsb |
> > ignore_pixel_alpha,
> > ?			????? &ovl->cmdq_reg, ovl->regs,
> > DISP_REG_OVL_PITCH(idx));
> > ?	mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg,
> > ovl->regs,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
> > new file mode 100644
> > index 000000000000..9bd5dc62d626
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
> > @@ -0,0 +1,16 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2025 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_DISP_OVL_H__
> > +#define __MTK_DISP_OVL_H__
> > +
> > +bool mtk_ovl_is_10bit_rgb(unsigned int fmt);
> > +bool mtk_ovl_is_ignore_pixel_alpha(struct mtk_plane_state *state,
> > unsigned int blend_mode);
> > +unsigned int mtk_ovl_get_blend_mode(struct mtk_plane_state *state,
> > unsigned int blend_modes);
> > +unsigned int mtk_ovl_fmt_convert(unsigned int fmt, unsigned int
> > blend_mode,
> > +				 bool fmt_rgb565_is_0, bool
> > color_convert,
> > +				 u8 clrfmt_shift, u32 clrfmt_man,
> > u32 byte_swap, u32 rgb_swap);
> > +
> > +#endif
> 


From lorenzo at kernel.org  Tue May 13 09:34:44 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Tue, 13 May 2025 18:34:44 +0200
Subject: [PATCH net] net: airoha: Fix page recycling in
 airoha_qdma_rx_process()
Message-ID: <20250513-airoha-fix-rx-process-error-condition-v1-1-e5d70cd7c066@kernel.org>

Do not recycle the page twice in airoha_qdma_rx_process routine in case
of error. Just run dev_kfree_skb() if the skb has been allocated and marked
for recycling. Run page_pool_put_full_page() directly if the skb has not
been allocated yet.
Moreover, rely on DMA address from queue entry element instead of reading
it from the DMA descriptor for DMA syncing in airoha_qdma_rx_process().

Fixes: e12182ddb6e71 ("net: airoha: Enable Rx Scatter-Gather")
---
 drivers/net/ethernet/airoha/airoha_eth.c | 22 +++++++++-------------
 1 file changed, 9 insertions(+), 13 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index d748dc6de92367365db9f9548f9af52a7fdac187..1e9ab65218ff144d99b47f5d4ad5ff4f9c227418 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -614,7 +614,6 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
 		struct airoha_queue_entry *e = &q->entry[q->tail];
 		struct airoha_qdma_desc *desc = &q->desc[q->tail];
 		u32 hash, reason, msg1 = le32_to_cpu(desc->msg1);
-		dma_addr_t dma_addr = le32_to_cpu(desc->addr);
 		struct page *page = virt_to_head_page(e->buf);
 		u32 desc_ctrl = le32_to_cpu(desc->ctrl);
 		struct airoha_gdm_port *port;
@@ -623,22 +622,16 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
 		if (!(desc_ctrl & QDMA_DESC_DONE_MASK))
 			break;
 
-		if (!dma_addr)
-			break;
-
-		len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl);
-		if (!len)
-			break;
-
 		q->tail = (q->tail + 1) % q->ndesc;
 		q->queued--;
 
-		dma_sync_single_for_cpu(eth->dev, dma_addr,
+		dma_sync_single_for_cpu(eth->dev, e->dma_addr,
 					SKB_WITH_OVERHEAD(q->buf_size), dir);
 
+		len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl);
 		data_len = q->skb ? q->buf_size
 				  : SKB_WITH_OVERHEAD(q->buf_size);
-		if (data_len < len)
+		if (!len || data_len < len)
 			goto free_frag;
 
 		p = airoha_qdma_get_gdm_port(eth, desc);
@@ -701,9 +694,12 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
 		q->skb = NULL;
 		continue;
 free_frag:
-		page_pool_put_full_page(q->page_pool, page, true);
-		dev_kfree_skb(q->skb);
-		q->skb = NULL;
+		if (q->skb) {
+			dev_kfree_skb(q->skb);
+			q->skb = NULL;
+		} else {
+			page_pool_put_full_page(q->page_pool, page, true);
+		}
 	}
 	airoha_qdma_fill_rx_queue(q);
 

---
base-commit: 4227ea91e2657f7965e34313448e9d0a2b67712e
change-id: 20250513-airoha-fix-rx-process-error-condition-b6e5db52fd4f

Best regards,
-- 
Lorenzo Bianconi <lorenzo at kernel.org>



From Paul-pl.Chen at mediatek.com  Tue May 13 10:12:21 2025
From: Paul-pl.Chen at mediatek.com (=?utf-8?B?UGF1bC1wbCBDaGVuICjpmbPmn4/pnJYp?=)
Date: Tue, 13 May 2025 17:12:21 +0000
Subject: [PATCH v2 11/15] drm/mediatek: add BLENDER support for MT8196
In-Reply-To: <0daf839388be6861c1d0d02d6167942a57ec8e38.camel@mediatek.com>
References: <20250321093435.94835-1-paul-pl.chen@mediatek.com>
	 <20250321093435.94835-12-paul-pl.chen@mediatek.com>
	 <0daf839388be6861c1d0d02d6167942a57ec8e38.camel@mediatek.com>
Message-ID: <127475f846bb15da731c1308f1933d361a6a906c.camel@mediatek.com>

On Mon, 2025-03-24 at 08:33 +0000, CK Hu (???) wrote:
> On Fri, 2025-03-21 at 17:33 +0800, paul-pl.chen wrote:
> > From: Nancy Lin <nancy.lin at mediatek.com>
> > 
> > BLENDER executes the alpha blending function for overlapping
> > layers from different sources, which is the primary function
> > of the overlapping system.
> > 
> > Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
> > Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
> > 
> > ---
> > ?drivers/gpu/drm/mediatek/Makefile?????????? |?? 1 +
> > ?drivers/gpu/drm/mediatek/mtk_ddp_comp.c???? |?? 1 +
> > ?drivers/gpu/drm/mediatek/mtk_ddp_comp.h???? |?? 1 +
> > ?drivers/gpu/drm/mediatek/mtk_disp_blender.c | 276
> > ++++++++++++++++++++
> > ?drivers/gpu/drm/mediatek/mtk_disp_blender.h |? 18 ++
> > ?drivers/gpu/drm/mediatek/mtk_disp_drv.h???? |? 12 +
> > ?drivers/gpu/drm/mediatek/mtk_drm_drv.c????? |?? 1 +
> > ?drivers/gpu/drm/mediatek/mtk_drm_drv.h????? |?? 1 +
> > ?8 files changed, 311 insertions(+)
> > ?create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_blender.c
> > ?create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_blender.h
> > 
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index db92f4fb353d..a7b9ebe27f68 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -3,6 +3,7 @@
> > ?mediatek-drm-y := mtk_crtc.o \
> > ?		? mtk_ddp_comp.o \
> > ?		? mtk_disp_aal.o \
> > +		? mtk_disp_blender.o \
> > ?		? mtk_disp_ccorr.o \
> > ?		? mtk_disp_color.o \
> > ?		? mtk_disp_exdma.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > index 3e0739d8e6f1..e65c6df987f2 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > @@ -445,6 +445,7 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> > ?	[MTK_DP_INTF] = "dp-intf",
> > ?	[MTK_DPI] = "dpi",
> > ?	[MTK_DSI] = "dsi",
> > +	[MTK_OVL_BLENDER] = "blender",
> > ?	[MTK_OVL_EXDMA] = "exdma",
> > ?};
> > ?
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > index 86dc0ee3924c..075ba5683f93 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > @@ -43,6 +43,7 @@ enum mtk_ddp_comp_type {
> > ?	MTK_DPI,
> > ?	MTK_DP_INTF,
> > ?	MTK_DSI,
> > +	MTK_OVL_BLENDER,
> > ?	MTK_OVL_EXDMA,
> > ?	MTK_DDP_COMP_TYPE_MAX,
> > ?};
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_blender.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_blender.c
> > new file mode 100644
> > index 000000000000..32c9e3d463a4
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_blender.c
> > @@ -0,0 +1,276 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2025 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <drm/drm_blend.h>
> > +#include <drm/drm_framebuffer.h>
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/reset.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +
> > +#include "mtk_crtc.h"
> > +#include "mtk_ddp_comp.h"
> > +#include "mtk_disp_drv.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_disp_blender.h"
> > +#include "mtk_disp_ovl.h"
> > +
> > +#define OVL_BLD_ALPHA					0xff
> > +#define DISP_REG_OVL_BLD_DATAPATH_CON			0x010
> > +#define
> > OVL_BLD_BGCLR_IN_SEL					BIT(0)
> > +#define
> > OVL_BLD_BGCLR_OUT_TO_PROC				BIT(4)
> > +#define
> > OVL_BLD_BGCLR_OUT_TO_NEXT_LAYER				BIT(5)
> > +
> > +#define DISP_REG_OVL_BLD_EN				0x020
> > +#define
> > OVL_BLD_EN						BIT(0)
> > +#define
> > OVL_BLD_FORCE_RELAY_MODE				BIT(4)
> > +#define
> > OVL_BLD_RELAY_MODE					BIT(5)
> > +#define DISP_REG_OVL_BLD_RST				0x024
> > +#define
> > OVL_BLD_RST						BIT(0)
> > +#define DISP_REG_OVL_BLD_SHADOW_CTRL			0x028
> > +#define
> > OVL_BLD_BYPASS_SHADOW					BIT(2)
> > +#define DISP_REG_OVL_BLD_BGCLR_BALCK			0xff000000
> > +#define DISP_REG_OVL_BLD_ROI_SIZE			0x030
> > +#define DISP_REG_OVL_BLD_L_EN				0x040
> > +#define
> > OVL_BLD_L_EN						BIT(0)
> > +#define
> > DISP_REG_OVL_BLD_OFFSET				0x044
> > +#define DISP_REG_OVL_BLD_SRC_SIZE			0x048
> > +#define DISP_REG_OVL_BLD_L0_CLRFMT			0x050
> > +#define
> > OVL_BLD_CON_FLD_CLRFMT					GENMASK(3, 0)
> > +#define
> > OVL_BLD_CON_CLRFMT_MAN					BIT(4)
> > +#define
> > OVL_BLD_CON_FLD_CLRFMT_NB				GENMASK(9, 8)
> > +#define
> > OVL_BLD_CON_CLRFMT_NB_10_BIT				BIT(8)
> > +#define
> > OVL_BLD_CON_BYTE_SWAP					BIT(16)
> > +#define
> > OVL_BLD_CON_RGB_SWAP					BIT(17)
> > +#define DISP_REG_OVL_BLD_BGCLR_CLR			0x104
> > +#define
> > DISP_REG_OVL_BLD_L_CON2				0x200
> > +#define
> > OVL_BLD_L_ALPHA						GENMASK(7, 0)
> > +#define
> > OVL_BLD_L_ALPHA_EN					BIT(12)
> > +#define DISP_REG_OVL_BLD_L0_PITCH			0x208
> 
> DISP_REG_OVL_BLD_L0_PITCH is useless, so drop it.
> 
> 
> This will be used in the mtk_disp_blender_config.
Sorry for the misleading, the naming would be
#define DISP_REG_OVL_BLD_L0_ALPHA_SEL	0x208
> 
> 
> > +#define
> > OVL_BLD_L0_CONST					BIT(24)
> > +#define
> > DISP_REG_OVL_BLD_L0_CLR				0x20c
> > +#define
> > OVL_BLD_CON_CLRFMT_MAN					BIT(4)
> > +#define
> > OVL_BLD_L0_SRC_PITCH					GENMASK(15, 0)
> > +#define DISP_REG_OVL_BLD_PITCH				0x2f4
> > +
> > +struct mtk_disp_blender {
> > +	void __iomem		*regs;
> > +	struct clk		*clk;
> > +	struct cmdq_client_reg	cmdq_reg;
> > +};
> > +
> > +void mtk_disp_blender_layer_config(struct device *dev, struct
> > mtk_plane_state *state,
> > +				?? struct cmdq_pkt *cmdq_pkt)
> > +{
> > +	struct mtk_disp_blender *priv = dev_get_drvdata(dev);
> > +	struct mtk_plane_pending_state *pending = &state->pending;
> > +	unsigned int align_width = ALIGN_DOWN(pending->width, 2);
> 
> If width is 101, changing width to 100 would get correct display
> output?
> 
> 
Yes, according to our internal experiments, the ALIGN_DOWN code can
be removed simultaneously from the drives for "EXDMA, BLENDER, 
OVLSYS_ADAPTOR". I will fix it.

> 
> > +	unsigned int alpha;
> > +	unsigned int clrfmt;
> > +	unsigned int blend_mode = mtk_ovl_get_blend_mode(state,
> > +							
> > BIT(DRM_MODE_BLEND_PREMULTI) |
> > +							
> > BIT(DRM_MODE_BLEND_COVERAGE) |
> > +							
> > BIT(DRM_MODE_BLEND_PIXEL_NONE));
> > +	unsigned int ignore_pixel_alpha = 0;
> > +
> > +	if (!pending->enable) {
> > +		mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv-
> > >regs, DISP_REG_OVL_BLD_L_EN);
> > +		return;
> > +	}
> > +
> > +	mtk_ddp_write(cmdq_pkt, pending->y << 16 | pending->x,
> > &priv->cmdq_reg, priv->regs,
> > +		????? DISP_REG_OVL_BLD_OFFSET);
> > +
> > +	mtk_ddp_write(cmdq_pkt, pending->height << 16 |
> > align_width, &priv->cmdq_reg,
> > +		????? priv->regs, DISP_REG_OVL_BLD_SRC_SIZE);
> > +
> > +	clrfmt = mtk_ovl_fmt_convert(pending->format, blend_mode,
> > true, false, 0,
> > +				???? OVL_BLD_CON_CLRFMT_MAN,
> > OVL_BLD_CON_BYTE_SWAP,
> > +				???? OVL_BLD_CON_RGB_SWAP);
> > +	clrfmt |= mtk_ovl_is_10bit_rgb(pending->format) ?
> > OVL_BLD_CON_CLRFMT_NB_10_BIT : 0;
> > +	mtk_ddp_write_mask(cmdq_pkt, clrfmt, &priv->cmdq_reg,
> > priv->regs,
> > +			?? DISP_REG_OVL_BLD_L0_CLRFMT,
> > OVL_BLD_CON_CLRFMT_MAN |
> > +			?? OVL_BLD_CON_RGB_SWAP |?
> > OVL_BLD_CON_BYTE_SWAP |
> > +			?? OVL_BLD_CON_FLD_CLRFMT |
> > OVL_BLD_CON_FLD_CLRFMT_NB);
> > +
> > +	alpha = (OVL_BLD_ALPHA & (state->base.alpha >> 8)) |
> > +		OVL_BLD_L_ALPHA_EN;
> > +
> > +	if (mtk_ovl_is_ignore_pixel_alpha(state, blend_mode))
> > +		ignore_pixel_alpha = OVL_BLD_L0_CONST;
> > +
> > +	mtk_ddp_write_mask(cmdq_pkt, pending->pitch |
> > ignore_pixel_alpha,
> > +			?? &priv->cmdq_reg, priv->regs,
> > +			?? DISP_REG_OVL_BLD_PITCH,
> > OVL_BLD_L0_CONST | OVL_BLD_L0_SRC_PITCH);
> 
> EXDMA already has pitch function, why BLENDER also has pitch
> function?
> What does BLENDER pitch do?

The input source of blender layer can be EXDMA layer output or 
the blender constanat itself.
The color setting is configured for the blender constant layer. 
> 
> > +
> > +	mtk_ddp_write_mask(cmdq_pkt, alpha, &priv->cmdq_reg, priv-
> > >regs,
> > +			?? DISP_REG_OVL_BLD_L_CON2,
> > OVL_BLD_L_ALPHA_EN | OVL_BLD_L_ALPHA);
> > +
> > +	mtk_ddp_write(cmdq_pkt, OVL_BLD_L_EN, &priv->cmdq_reg,
> > priv->regs, DISP_REG_OVL_BLD_L_EN);
> > +}
> > +
> > +void mtk_disp_blender_config(struct device *dev, unsigned int w,
> > +			???? unsigned int h, unsigned int
> > vrefresh,
> > +			???? unsigned int bpc, bool most_top,
> > +			???? bool most_bottom, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +	struct mtk_disp_blender *priv = dev_get_drvdata(dev);
> > +	u32 datapath;
> > +
> > +	dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
> > +	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg,
> > priv->regs,
> > +		????? DISP_REG_OVL_BLD_ROI_SIZE);
> > +	mtk_ddp_write(cmdq_pkt, DISP_REG_OVL_BLD_BGCLR_BALCK,
> > &priv->cmdq_reg, priv->regs,
> > +		????? DISP_REG_OVL_BLD_BGCLR_CLR);
> > +	mtk_ddp_write(cmdq_pkt, DISP_REG_OVL_BLD_BGCLR_BALCK,
> > &priv->cmdq_reg, priv->regs,
> > +		????? DISP_REG_OVL_BLD_L0_CLR);
> 
> I think I know what is BGLCR_CLR, but what is L0_CLR?
> 
> 
DISP_REG_OVL_BLD_L0_CLR controls te constant color for each
individual layer,
while OVL_BLD_BGCLR_CLR controls the background color for
the entire display.
> 
> 
> 
> > +
> > +	if (most_top)
> > +		datapath = OVL_BLD_BGCLR_OUT_TO_PROC;
> > +	else
> > +		datapath = OVL_BLD_BGCLR_OUT_TO_NEXT_LAYER;
> > +	/*
> > +	 * The primary input is from EXDMA and the second input
> > +	 * is optionally from another blender
> > +	 */
> > +	if (!most_bottom)
> > +		datapath |= OVL_BLD_BGCLR_IN_SEL;
> > +
> > +	mtk_ddp_write_mask(cmdq_pkt, datapath,
> > +			?? &priv->cmdq_reg, priv->regs,
> > DISP_REG_OVL_BLD_DATAPATH_CON,
> > +			?? OVL_BLD_BGCLR_OUT_TO_PROC |
> > OVL_BLD_BGCLR_OUT_TO_NEXT_LAYER |
> > +			?? OVL_BLD_BGCLR_IN_SEL);
> > +}
> > +
> > +void mtk_disp_blender_start(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +	struct mtk_disp_blender *priv = dev_get_drvdata(dev);
> > +	unsigned int tmp;
> > +
> > +	tmp = readl(priv->regs + DISP_REG_OVL_BLD_SHADOW_CTRL);
> > +	tmp = tmp | OVL_BLD_BYPASS_SHADOW;
> > +	writel(tmp, priv->regs + DISP_REG_OVL_BLD_SHADOW_CTRL);
> > +	mtk_ddp_write_mask(cmdq_pkt, OVL_BLD_EN, &priv->cmdq_reg,
> > priv->regs,
> > +			?? DISP_REG_OVL_BLD_EN, OVL_BLD_EN);
> > +}
> > +
> > +void mtk_disp_blender_stop(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +	struct mtk_disp_blender *priv = dev_get_drvdata(dev);
> > +
> > +	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > DISP_REG_OVL_BLD_L_EN);
> > +	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv-
> > >regs,
> > +			?? DISP_REG_OVL_BLD_EN, OVL_BLD_EN);
> 
> You already control OVL_BLD_EN in layer config, so it's not necessary
> to control here.
> 
> Regards,
> CK
> 
> OK I will fix it.
> 
> Best, Paul
> 
> > +	mtk_ddp_write_mask(cmdq_pkt, OVL_BLD_RST, &priv->cmdq_reg,
> > priv->regs,
> > +			?? DISP_REG_OVL_BLD_RST, OVL_BLD_RST);
> > +	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv-
> > >regs,
> > +			?? DISP_REG_OVL_BLD_RST, OVL_BLD_RST);
> > +}
> > +
> > 
> 


From sean.anderson at seco.com  Tue May 13 11:16:44 2025
From: sean.anderson at seco.com (Sean Anderson)
Date: Tue, 13 May 2025 14:16:44 -0400
Subject: [net-next PATCH v4 07/11] dt-bindings: net: ethernet-controller:
 permit to define multiple PCS
In-Reply-To: <20250511201250.3789083-8-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-8-ansuelsmth@gmail.com>
Message-ID: <50c9606b-e671-4c87-a126-6709c9364f47@seco.com>

On 5/11/25 16:12, Christian Marangi wrote:
> Drop the limitation of a single PCS in pcs-handle property. Multiple PCS
> can be defined for an ethrnet-controller node to support various PHY
> interface mode type.
> 
> It's very common for SoCs to have a 2 or more dedicated PCS for Base-X
> (for example SGMII, 1000base-x, 2500base-x, ...) and Base-R (for example
> USXGMII,10base-r, ...) with the MAC selecting one of the other based on
> the attached PHY.
> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---
>  Documentation/devicetree/bindings/net/ethernet-controller.yaml | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
> index 7cbf11bbe99c..60605b34d242 100644
> --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
> +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
> @@ -84,8 +84,6 @@ properties:
>  
>    pcs-handle:
>      $ref: /schemas/types.yaml#/definitions/phandle-array
> -    items:
> -      maxItems: 1
>      description:
>        Specifies a reference to a node representing a PCS PHY device on a MDIO
>        bus to link with an external PHY (phy-handle) if exists.

This just specifies the default. Bindings for individual macs can
override this. See fsl,fman-dtsec.yaml for an example.

--Sean


From sean.anderson at linux.dev  Tue May 13 11:18:02 2025
From: sean.anderson at linux.dev (Sean Anderson)
Date: Tue, 13 May 2025 14:18:02 -0400
Subject: [net-next PATCH v4 03/11] net: phylink: introduce internal
 phylink PCS handling
In-Reply-To: <20250511201250.3789083-4-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-4-ansuelsmth@gmail.com>
Message-ID: <5d004048-ef8f-42ad-8f17-d1e4d495f57f@linux.dev>

On 5/11/25 16:12, Christian Marangi wrote:
> Introduce internal handling of PCS for phylink. This is an alternative
> to .mac_select_pcs that moves the selection logic of the PCS entirely to
> phylink with the usage of the supported_interface value in the PCS
> struct.
> 
> MAC should now provide an array of available PCS in phylink_config in
> .available_pcs and fill the .num_available_pcs with the number of
> elements in the array. MAC should also define a new bitmap,
> pcs_interfaces, in phylink_config to define for what interface mode a
> dedicated PCS is required.
> 
> On phylink_create() this array is parsed and a linked list of PCS is
> created based on the PCS passed in phylink_config.
> Also the supported_interface value in phylink struct is updated with the
> new supported_interface from the provided PCS.
> 
> On phylink_start() every PCS in phylink PCS list gets attached to the
> phylink instance. This is done by setting the phylink value in
> phylink_pcs struct to the phylink instance.
> 
> On phylink_stop(), every PCS in phylink PCS list is detached from the
> phylink instance. This is done by setting the phylink value in
> phylink_pcs struct to NULL.
> 
> phylink_validate_mac_and_pcs(), phylink_major_config() and
> phylink_inband_caps() are updated to support this new implementation
> with the PCS list stored in phylink.
> 
> They will make use of phylink_validate_pcs_interface() that will loop
> for every PCS in the phylink PCS available list and find one that supports
> the passed interface.
> 
> phylink_validate_pcs_interface() applies the same logic of .mac_select_pcs
> where if a supported_interface value is not set for the PCS struct, then
> it's assumed every interface is supported.
> 
> A MAC is required to implement either a .mac_select_pcs or make use of
> the PCS list implementation. Implementing both will result in a fail
> on MAC/PCS validation.
> 
> phylink value in phylink_pcs struct with this implementation is used to
> track from PCS side when it's attached to a phylink instance. PCS driver
> will make use of this information to correctly detach from a phylink
> instance if needed.
> 
> The .mac_select_pcs implementation is not changed but it's expected that
> every MAC driver migrates to the new implementation to later deprecate
> and remove .mac_select_pcs.

This introduces a completely parallel PCS selection system used by a
single driver. I don't think we want the maintenance burden and
complexity of two systems in perpetuity. So what is your plan for
conversion of existing drivers to your new system?

DSA drivers typically have different PCSs for each port. At the moment
these are selected with mac_select_pcs, allowing the use of a single
phylink_config for each port. If you need to pass PCSs through
phylink_config then each port will needs its own config. This may prove
difficult to integrate with the existing API.

> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---
>  drivers/net/phy/phylink.c | 147 +++++++++++++++++++++++++++++++++-----
>  include/linux/phylink.h   |  10 +++
>  2 files changed, 139 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
> index ec42fd278604..95d7e06dee56 100644
> --- a/drivers/net/phy/phylink.c
> +++ b/drivers/net/phy/phylink.c
> @@ -59,6 +59,9 @@ struct phylink {
>  	/* The link configuration settings */
>  	struct phylink_link_state link_config;
>  
> +	/* List of available PCS */
> +	struct list_head pcs_list;
> +
>  	/* What interface are supported by the current link.
>  	 * Can change on removal or addition of new PCS.
>  	 */
> @@ -144,6 +147,8 @@ static const phy_interface_t phylink_sfp_interface_preference[] = {
>  
>  static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);
>  
> +static void phylink_run_resolve(struct phylink *pl);
> +
>  /**
>   * phylink_set_port_modes() - set the port type modes in the ethtool mask
>   * @mask: ethtool link mode mask
> @@ -499,22 +504,59 @@ static void phylink_validate_mask_caps(unsigned long *supported,
>  	linkmode_and(state->advertising, state->advertising, mask);
>  }
>  
> +static int phylink_validate_pcs_interface(struct phylink_pcs *pcs,
> +					  phy_interface_t interface)
> +{
> +	/* If PCS define an empty supported_interfaces value, assume
> +	 * all interface are supported.
> +	 */
> +	if (phy_interface_empty(pcs->supported_interfaces))
> +		return 0;
> +
> +	/* Ensure that this PCS supports the interface mode */
> +	if (!test_bit(interface, pcs->supported_interfaces))
> +		return -EINVAL;
> +
> +	return 0;
> +}
> +
>  static int phylink_validate_mac_and_pcs(struct phylink *pl,
>  					unsigned long *supported,
>  					struct phylink_link_state *state)
>  {
> -	struct phylink_pcs *pcs = NULL;
>  	unsigned long capabilities;
> +	struct phylink_pcs *pcs;
> +	bool pcs_found = false;
>  	int ret;
>  
>  	/* Get the PCS for this interface mode */
>  	if (pl->mac_ops->mac_select_pcs) {
> +		/* Make sure either PCS internal validation or .mac_select_pcs
> +		 * is used. Return error if both are defined.
> +		 */
> +		if (!list_empty(&pl->pcs_list)) {
> +			phylink_err(pl, "either phylink_pcs_add() or .mac_select_pcs must be used\n");
> +			return -EINVAL;
> +		}
> +

This validation should be done in phylink_create.

>  		pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
>  		if (IS_ERR(pcs))
>  			return PTR_ERR(pcs);
> +
> +		pcs_found = !!pcs;
> +	} else {
> +		/* Check every assigned PCS and search for one that supports
> +		 * the interface.
> +		 */
> +		list_for_each_entry(pcs, &pl->pcs_list, list) {
> +			if (!phylink_validate_pcs_interface(pcs, state->interface)) {
> +				pcs_found = true;
> +				break;
> +			}
> +		}
>  	}
>  
> -	if (pcs) {
> +	if (pcs_found) {
>  		/* The PCS, if present, must be setup before phylink_create()
>  		 * has been called. If the ops is not initialised, print an
>  		 * error and backtrace rather than oopsing the kernel.
> @@ -526,13 +568,10 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
>  			return -EINVAL;
>  		}
>  
> -		/* Ensure that this PCS supports the interface which the MAC
> -		 * returned it for. It is an error for the MAC to return a PCS
> -		 * that does not support the interface mode.
> -		 */
> -		if (!phy_interface_empty(pcs->supported_interfaces) &&
> -		    !test_bit(state->interface, pcs->supported_interfaces)) {
> -			phylink_err(pl, "MAC returned PCS which does not support %s\n",
> +		/* Recheck PCS to handle legacy way for .mac_select_pcs */
> +		ret = phylink_validate_pcs_interface(pcs, state->interface);
> +		if (ret) {
> +			phylink_err(pl, "selected PCS does not support %s\n",
>  				    phy_modes(state->interface));
>  			return -EINVAL;
>  		}
> @@ -937,12 +976,22 @@ static unsigned int phylink_inband_caps(struct phylink *pl,
>  					 phy_interface_t interface)
>  {
>  	struct phylink_pcs *pcs;
> +	bool pcs_found = false;
>  
> -	if (!pl->mac_ops->mac_select_pcs)
> -		return 0;
> +	if (pl->mac_ops->mac_select_pcs) {
> +		pcs = pl->mac_ops->mac_select_pcs(pl->config,
> +						  interface);
> +		pcs_found = !!pcs;
> +	} else {
> +		list_for_each_entry(pcs, &pl->pcs_list, list) {
> +			if (!phylink_validate_pcs_interface(pcs, interface)) {
> +				pcs_found = true;
> +				break;
> +			}
> +		}
> +	}
>  
> -	pcs = pl->mac_ops->mac_select_pcs(pl->config, interface);
> -	if (!pcs)
> +	if (!pcs_found)
>  		return 0;
>  
>  	return phylink_pcs_inband_caps(pcs, interface);
> @@ -1228,10 +1277,36 @@ static void phylink_major_config(struct phylink *pl, bool restart,
>  			pl->major_config_failed = true;
>  			return;
>  		}
> +	/* Find a PCS in available PCS list for the requested interface.
> +	 * This doesn't overwrite the previous .mac_select_pcs as either
> +	 * .mac_select_pcs or PCS list implementation are permitted.
> +	 *
> +	 * Skip searching if the MAC doesn't require a dedicaed PCS for

dedicated

> +	 * the requested interface.
> +	 */
> +	} else if (test_bit(state->interface, pl->config->pcs_interfaces)) {
> +		bool pcs_found = false;
> +
> +		list_for_each_entry(pcs, &pl->pcs_list, list) {
> +			if (!phylink_validate_pcs_interface(pcs,
> +							    state->interface)) {
> +				pcs_found = true;
> +				break;
> +			}
> +		}
> +
> +		if (!pcs_found) {
> +			phylink_err(pl,
> +				    "couldn't find a PCS for %s\n",
> +				    phy_modes(state->interface));
>  
> -		pcs_changed = pl->pcs != pcs;
> +			pl->major_config_failed = true;
> +			return;
> +		}
>  	}
>  
> +	pcs_changed = pl->pcs != pcs;
> +
>  	phylink_pcs_neg_mode(pl, pcs, state->interface, state->advertising);
>  
>  	phylink_dbg(pl, "major config, active %s/%s/%s\n",
> @@ -1258,10 +1333,12 @@ static void phylink_major_config(struct phylink *pl, bool restart,
>  	if (pcs_changed) {
>  		phylink_pcs_disable(pl->pcs);
>  
> -		if (pl->pcs)
> -			pl->pcs->phylink = NULL;
> +		if (pl->mac_ops->mac_select_pcs) {
> +			if (pl->pcs)
> +				pl->pcs->phylink = NULL;
>  
> -		pcs->phylink = pl;
> +			pcs->phylink = pl;
> +		}
>  
>  		pl->pcs = pcs;
>  	}
> @@ -1797,8 +1874,9 @@ struct phylink *phylink_create(struct phylink_config *config,
>  			       phy_interface_t iface,
>  			       const struct phylink_mac_ops *mac_ops)
>  {
> +	struct phylink_pcs *pcs;
>  	struct phylink *pl;
> -	int ret;
> +	int i, ret;
>  
>  	/* Validate the supplied configuration */
>  	if (phy_interface_empty(config->supported_interfaces)) {
> @@ -1813,9 +1891,21 @@ struct phylink *phylink_create(struct phylink_config *config,
>  
>  	mutex_init(&pl->state_mutex);
>  	INIT_WORK(&pl->resolve, phylink_resolve);
> +	INIT_LIST_HEAD(&pl->pcs_list);
> +
> +	/* Fill the PCS list with available PCS from phylink config */
> +	for (i = 0; i < config->num_available_pcs; i++) {
> +		pcs = config->available_pcs[i];
> +
> +		list_add(&pcs->list, &pl->pcs_list);
> +	}

Why do we have a separate linked list if we are getting all the PCSs
in an array at configuration time? From what I can tell there is no
dynamic configuration of PCSs.

>  
>  	phy_interface_copy(pl->supported_interfaces,
>  			   config->supported_interfaces);
> +	list_for_each_entry(pcs, &pl->pcs_list, list)
> +		phy_interface_or(pl->supported_interfaces,
> +				 pl->supported_interfaces,
> +				 pcs->supported_interfaces);
>  
>  	pl->config = config;
>  	if (config->type == PHYLINK_NETDEV) {
> @@ -1894,10 +1984,16 @@ EXPORT_SYMBOL_GPL(phylink_create);
>   */
>  void phylink_destroy(struct phylink *pl)
>  {
> +	struct phylink_pcs *pcs, *tmp;
> +
>  	sfp_bus_del_upstream(pl->sfp_bus);
>  	if (pl->link_gpio)
>  		gpiod_put(pl->link_gpio);
>  
> +	/* Remove every PCS from phylink PCS list */
> +	list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list)
> +		list_del(&pcs->list);
> +
>  	cancel_work_sync(&pl->resolve);
>  	kfree(pl);
>  }
> @@ -2374,6 +2470,7 @@ static irqreturn_t phylink_link_handler(int irq, void *data)
>   */
>  void phylink_start(struct phylink *pl)
>  {
> +	struct phylink_pcs *pcs;
>  	bool poll = false;
>  
>  	ASSERT_RTNL();
> @@ -2400,6 +2497,10 @@ void phylink_start(struct phylink *pl)
>  
>  	pl->pcs_state = PCS_STATE_STARTED;
>  
> +	/* link available PCS to phylink struct */
> +	list_for_each_entry(pcs, &pl->pcs_list, list)
> +		pcs->phylink = pl;
> +
>  	phylink_enable_and_run_resolve(pl, PHYLINK_DISABLE_STOPPED);
>  
>  	if (pl->cfg_link_an_mode == MLO_AN_FIXED && pl->link_gpio) {
> @@ -2444,6 +2545,8 @@ EXPORT_SYMBOL_GPL(phylink_start);
>   */
>  void phylink_stop(struct phylink *pl)
>  {
> +	struct phylink_pcs *pcs;
> +
>  	ASSERT_RTNL();
>  
>  	if (pl->sfp_bus)
> @@ -2461,6 +2564,14 @@ void phylink_stop(struct phylink *pl)
>  	pl->pcs_state = PCS_STATE_DOWN;
>  
>  	phylink_pcs_disable(pl->pcs);
> +
> +	/* Drop link between phylink and PCS */
> +	list_for_each_entry(pcs, &pl->pcs_list, list)
> +		pcs->phylink = NULL;
> +
> +	/* Restore original supported interfaces */
> +	phy_interface_copy(pl->supported_interfaces,
> +			   pl->config->supported_interfaces);
>  }
>  EXPORT_SYMBOL_GPL(phylink_stop);
>  
> diff --git a/include/linux/phylink.h b/include/linux/phylink.h
> index 30659b615fca..ef0b5a0729c8 100644
> --- a/include/linux/phylink.h
> +++ b/include/linux/phylink.h
> @@ -150,12 +150,16 @@ enum phylink_op_type {
>   *		     if MAC link is at %MLO_AN_FIXED mode.
>   * @supported_interfaces: bitmap describing which PHY_INTERFACE_MODE_xxx
>   *                        are supported by the MAC/PCS.
> + * @pcs_interfaces: bitmap describing for which PHY_INTERFACE_MODE_xxx a
> + *		    dedicated PCS is required.
>   * @lpi_interfaces: bitmap describing which PHY interface modes can support
>   *		    LPI signalling.
>   * @mac_capabilities: MAC pause/speed/duplex capabilities.
>   * @lpi_capabilities: MAC speeds which can support LPI signalling
>   * @lpi_timer_default: Default EEE LPI timer setting.
>   * @eee_enabled_default: If set, EEE will be enabled by phylink at creation time
> + * @available_pcs: array of available phylink_pcs PCS
> + * @num_available_pcs: num of available phylink_pcs PCS
>   */
>  struct phylink_config {
>  	struct device *dev;
> @@ -168,11 +172,14 @@ struct phylink_config {
>  	void (*get_fixed_state)(struct phylink_config *config,
>  				struct phylink_link_state *state);
>  	DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
> +	DECLARE_PHY_INTERFACE_MASK(pcs_interfaces);
>  	DECLARE_PHY_INTERFACE_MASK(lpi_interfaces);
>  	unsigned long mac_capabilities;
>  	unsigned long lpi_capabilities;
>  	u32 lpi_timer_default;
>  	bool eee_enabled_default;
> +	struct phylink_pcs **available_pcs;
> +	unsigned int num_available_pcs;
>  };
>  
>  void phylink_limit_mac_speed(struct phylink_config *config, u32 max_speed);
> @@ -469,6 +476,9 @@ struct phylink_pcs {
>  	struct phylink *phylink;
>  	bool poll;
>  	bool rxc_always_on;
> +
> +	/* private: */
> +	struct list_head list;
>  };
>  
>  /**


From sean.anderson at linux.dev  Tue May 13 11:18:24 2025
From: sean.anderson at linux.dev (Sean Anderson)
Date: Tue, 13 May 2025 14:18:24 -0400
Subject: [net-next PATCH v4 01/11] net: phy: introduce phy_interface_copy
 helper
In-Reply-To: <20250511201250.3789083-2-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-2-ansuelsmth@gmail.com>
Message-ID: <53d495b1-b593-4ca1-acf3-fe1907d9a56a@linux.dev>

On 5/11/25 16:12, Christian Marangi wrote:
> Introduce phy_interface_copy helper as a shorthand to copy the PHY
> interface bitmap to a different location.
> 
> This is useful if a PHY interface bitmap needs to be stored in a
> different variable and needs to be reset to an original value saved in a
> different bitmap.
> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---
>  include/linux/phy.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/include/linux/phy.h b/include/linux/phy.h
> index d62d292024bc..9f0e5fb30d63 100644
> --- a/include/linux/phy.h
> +++ b/include/linux/phy.h
> @@ -173,6 +173,11 @@ static inline void phy_interface_or(unsigned long *dst, const unsigned long *a,
>  	bitmap_or(dst, a, b, PHY_INTERFACE_MODE_MAX);
>  }
>  
> +static inline void phy_interface_copy(unsigned long *dst, const unsigned long *src)
> +{
> +	bitmap_copy(dst, src, PHY_INTERFACE_MODE_MAX);
> +}
> +
>  static inline void phy_interface_set_rgmii(unsigned long *intf)
>  {
>  	__set_bit(PHY_INTERFACE_MODE_RGMII, intf);

Reviewed-by: Sean Anderson <sean.anderson at linux.dev>


From sean.anderson at seco.com  Tue May 13 11:25:25 2025
From: sean.anderson at seco.com (Sean Anderson)
Date: Tue, 13 May 2025 14:25:25 -0400
Subject: [net-next PATCH v4 09/11] dt-bindings: net: pcs: Document support
 for Airoha Ethernet PCS
In-Reply-To: <20250511201250.3789083-10-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-10-ansuelsmth@gmail.com>
Message-ID: <500bf7f4-23aa-4dfb-acf1-d00626793f2b@seco.com>

Devicetree binding patches should come first in a series.

On 5/11/25 16:12, Christian Marangi wrote:
> Document support for Airoha Ethernet PCS for AN7581 SoC.
> 
> Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
> the various Serdes port supporting different Media Independent Interface
> (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).
> 
> This follow the new PCS provider with the use of #pcs-cells property.
> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---
>  .../bindings/net/pcs/airoha,pcs.yaml          | 112 ++++++++++++++++++
>  1 file changed, 112 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
> 
> diff --git a/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
> new file mode 100644
> index 000000000000..8bcf7757c728
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
> @@ -0,0 +1,112 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/pcs/airoha,pcs.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Airoha Ethernet PCS and Serdes
> +
> +maintainers:
> +  - Christian Marangi <ansuelsmth at gmail.com>
> +
> +description:
> +  Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for

The Airoha AN7581 SoC exposes multiple Physical Coding Sublayers (PCSs) for

> +  the various Serdes port supporting different Media Independent Interface

ports, Interfaces

> +  (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).

10GBase-R

> +
> +properties:
> +  compatible:
> +    enum:
> +      - airoha,an7581-pcs-eth
> +      - airoha,an7581-pcs-pon

What's the difference between these? There's no mention of PON above.

> +  reg:
> +    items:
> +      - description: XFI MAC reg
> +      - description: HSGMII AN reg
> +      - description: HSGMII PCS reg
> +      - description: MULTI SGMII reg
> +      - description: USXGMII reg
> +      - description: HSGMII rate adaption reg
> +      - description: XFI Analog register
> +      - description: XFI PMA (Physical Medium Attachment) register
> +
> +  reg-names:
> +    items:
> +      - const: xfi_mac
> +      - const: hsgmii_an
> +      - const: hsgmii_pcs
> +      - const: multi_sgmii
> +      - const: usxgmii
> +      - const: hsgmii_rate_adp
> +      - const: xfi_ana
> +      - const: xfi_pma
> +
> +  resets:
> +    items:
> +      - description: MAC reset
> +      - description: PHY reset
> +
> +  reset-names:
> +    items:
> +      - const: mac
> +      - const: phy
> +
> +  "#pcs-cells":
> +    const: 0

>From what I can tell you only have one PCS. So this is unnecessary.

--Sean

> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - resets
> +  - reset-names
> +  - "#pcs-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/reset/airoha,en7581-reset.h>
> +
> +    pcs at 1fa08000 {
> +        compatible = "airoha,an7581-pcs-pon";
> +        reg = <0x1fa08000 0x1000>,
> +              <0x1fa80000 0x60>,
> +              <0x1fa80a00 0x164>,
> +              <0x1fa84000 0x450>,
> +              <0x1fa85900 0x338>,
> +              <0x1fa86000 0x300>,
> +              <0x1fa8a000 0x1000>,
> +              <0x1fa8b000 0x1000>;
> +        reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
> +                    "multi_sgmii", "usxgmii",
> +                    "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
> +
> +        resets = <&scuclk EN7581_XPON_MAC_RST>,
> +                 <&scuclk EN7581_XPON_PHY_RST>;
> +        reset-names = "mac", "phy";
> +
> +        #pcs-cells = <0>;
> +    };
> +
> +    pcs at 1fa09000 {
> +        compatible = "airoha,an7581-pcs-eth";
> +        reg = <0x1fa09000 0x1000>,
> +              <0x1fa70000 0x60>,
> +              <0x1fa70a00 0x164>,
> +              <0x1fa74000 0x450>,
> +              <0x1fa75900 0x338>,
> +              <0x1fa76000 0x300>,
> +              <0x1fa7a000 0x1000>,
> +              <0x1fa7b000 0x1000>;
> +        reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
> +                    "multi_sgmii", "usxgmii",
> +                    "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
> +
> +        resets = <&scuclk EN7581_XSI_MAC_RST>,
> +                 <&scuclk EN7581_XSI_PHY_RST>;
> +        reset-names = "mac", "phy";
> +
> +        #pcs-cells = <0>;
> +    };


From robh at kernel.org  Tue May 13 11:28:28 2025
From: robh at kernel.org (Rob Herring)
Date: Tue, 13 May 2025 13:28:28 -0500
Subject: [GIT,PULL,1/2] MediaTek ARM64 DTS updates for v6.16
In-Reply-To: <20250506091736.125733-1-angelogioacchino.delregno@collabora.com>
References: <20250506091736.125733-1-angelogioacchino.delregno@collabora.com>
Message-ID: <CAL_JsqKmQxaOUykYfoUCaVe9jg5_fWnoLhxn5j3WmQC1Tm8ZGw@mail.gmail.com>

On Tue, May 6, 2025 at 6:55?AM AngeloGioacchino Del Regno
<angelogioacchino.delregno at collabora.com> wrote:
>
> The following changes since commit 0af2f6be1b4281385b618cb86ad946eded089ac8:
>
>   Linux 6.15-rc1 (2025-04-06 13:11:33 -0700)
>
> are available in the Git repository at:
>
>   https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux.git tags/mtk-dts64-for-v6.16
>
> for you to fetch changes up to 1fe38d2a19950fa6dbc384ee8967c057aef9faf4:
>
>   arm64: dts: mt6359: Add missing 'compatible' property to regulators node (2025-05-06 10:35:45 +0200)
>
> ----------------------------------------------------------------
> MediaTek ARM64 DTS updates for v6.16
>
> This adds new MT8186-based Google Ponyta Chromebooks and improves
> support for already supported SoCs and machines.
>
> In particular, SoCs changes:
>  - MT6893
>    - Added pinmux header for this SoC
>  - MT8183
>    - Added port node for dsi_out in mt8183.dtsi to fix some DT
>      validation warnings.
>  - MT8188
>    - Adds an important fix for its Display Controller's Read DMA 0
>      (RDMA0), as it was using the wrong IOMMU and failing;
>    - Multimedia Data Path 3 (MDP3) devicetree nodes were added: now
>      hardware assisted color format conversions are available;
>    - Since SCP firmwares are available on linux-firmware, the
>      necessary nodes for the dual-core SCP were added to devicetree
>      along with the firmware-name property in mt8390-genio-common,
>      enabling hardware video encoders and decoders on the MediaTek
>      Genio 510 and Genio 700 EVKs.
>  - MT8195
>    - Power domains for video decoders and encoders were reparented
>      as the secondary vdec/venc core needs the primary core to be
>      also powered, as those are sharing the LAT hardware and SRAM;
>    - Missing power domain was added to the primary DisplayPort
>      Interface (dp_intf0) node.
>  - MT8196
>    - Added pinmux header for this SoC
>
> ... and machine-specific changes:
>  - Radxa NIO-12L (MT8395)
>    - Added support for Audio DSP and sound output through 3.5mm jack;
>  - MediaTek Genio 1200 EVK (MT8395)
>    - Support for this EVK's DSI display was added and enabled;
>    - Secondary display backlight was disabled as it was unused
>  - MediaTek Genio 510/700 (MT8370/MT8390)
>    - Added support for the DSI display on these EVKs too;
>    - Fixed an issue with integrated USB Bluetooth getting unplugged
>      permanently due to wrong declaration of the ID GPIO polarity of
>      the secondary USB port on the SSUSB2 controller;
>
> Other than that, some other devicetree validation fixes were added
> on the MT6357 and MT6359 PMIC DTs: for the former, all of the
> compatible strings in all regulators were dropped as those were
> wrong and causing DT kselftest failures - and for the latter, the
> compatible string for the main `regulators` node was added as it
> was missing.
>
> ----------------------------------------------------------------
> AngeloGioacchino Del Regno (6):
>       arm64: dts: mediatek: mt8195: Reparent vdec1/2 and venc1 power domains
>       dt-bindings: display: mediatek: Add compatibles for MT8188 MDP3
>       dt-bindings: media: mediatek: mdp3: Add compatibles for MT8188 MDP3
>       arm64: dts: mediatek: mt8188: Add all Multimedia Data Path 3 nodes

I reported this already with no response, but this commit adds a crap
load of DT warnings. This is on top of the many existing Mediatek
warnings. Mediatek has the most warnings on arm64 and is about a fifth
of the total (182 out of 932 on Linus' tree). If there's a fix for any
of these, I can't find it. Either fix these warnings or drop the dts
change.

(Note the number is the count for the specific warning in order to
avoid duplicates (N warnings for N boards)).

     33 (mediatek,mt8188-mdp3-wrot): '#dma-cells' is a required property
     33 (mediatek,mt8188-mdp3-tdshp): 'power-domains' does not match
any of the regexes: '^pinctrl-[0-9]+$'
     33 (mediatek,mt8188-mdp3-rsz): 'power-domains' does not match any
of the regexes: '^pinctrl-[0-9]+$'
     33 (mediatek,mt8188-mdp3-rsz): 'mediatek,gce-events' is a required property
     33 (mediatek,mt8188-mdp3-rdma): compatible: 'oneOf' conditional
failed, one must be fixed:
     33 (mediatek,mt8188-mdp3-hdr): 'power-domains' does not match any
of the regexes: '^pinctrl-[0-9]+$'
     33 (mediatek,mt8188-mdp3-fg): 'power-domains' does not match any
of the regexes: '^pinctrl-[0-9]+$'
     33 (mediatek,mt8188-mdp3-color): 'oneOf' conditional failed, one
must be fixed:
     33 (mediatek,mt8188-mdp3-aal): 'oneOf' conditional failed, one
must be fixed:
     11 (mediatek,mt8188-mdp3-tcc): 'power-domains' does not match any
of the regexes: '^pinctrl-[0-9]+$'
     11 (mediatek,mt8188-mdp3-ovl): 'oneOf' conditional failed, one
must be fixed:
     11 (mediatek,mt8188-mdp3-ovl): 'iommus' is a required property
      8 (mediatek,mt8188-mdp3-rdma): clocks: [[51, 12], [46, 186],
[46, 191]] is too long
      8 (mediatek,mt8188-mdp3-rdma): clocks: [[51, 10], [46, 186],
[46, 191]] is too long
      8 (mediatek,mt8188-mdp3-rdma): clocks: [[50, 12], [45, 186],
[45, 191]] is too long
      8 (mediatek,mt8188-mdp3-rdma): clocks: [[50, 10], [45, 186],
[45, 191]] is too long
      8 (mediatek,mt8188-mdp3-rdma): clocks: [[49, 24], [46, 185],
[46, 190], [49, 4], [49, 41], [49, 42], [49, 7], [51, 41], [51, 42],
[49, 8]] is too long
      8 (mediatek,mt8188-mdp3-rdma): clocks: [[48, 24], [45, 185],
[45, 190], [48, 4], [48, 41], [48, 42], [48, 7], [50, 41], [50, 42],
[48, 8]] is too long
      4 (mediatek,mt8188-mdp3-rsz): clocks: [[51, 24], [51, 25]] is too long
      4 (mediatek,mt8188-mdp3-rsz): clocks: [[51, 20], [51, 21]] is too long
      4 (mediatek,mt8188-mdp3-rsz): clocks: [[50, 24], [50, 25]] is too long
      4 (mediatek,mt8188-mdp3-rsz): clocks: [[50, 20], [50, 21]] is too long
      4 (mediatek,mt8188-mdp3-rdma): power-domains: [[67, 15], [67,
20]] is too long
      4 (mediatek,mt8188-mdp3-rdma): power-domains: [[66, 15], [66,
20]] is too long
      2 (mediatek,mt8188-mdp3-rdma): mboxes: [[121, 13, 1], [121, 14,
1], [121, 16, 1], [121, 21, 1]] is too short
      2 (mediatek,mt8188-mdp3-rdma): mboxes: [[120, 13, 1], [120, 14,
1], [120, 16, 1], [120, 21, 1]] is too short
      2 (mediatek,mt8188-mdp3-rdma): mboxes: [[119, 13, 1], [119, 14,
1], [119, 16, 1], [119, 21, 1]] is too short
      2 (mediatek,mt8188-mdp3-rdma): mboxes: [[118, 13, 1], [118, 14,
1], [118, 16, 1], [118, 21, 1]] is too short
      2 (mediatek,mt8188-mdp3-rdma): iommus: [[132, 164], [132, 166]]
is too long
      2 (mediatek,mt8188-mdp3-rdma): iommus: [[131, 164], [131, 166]]
is too long
      2 (mediatek,mt8188-mdp3-rdma): iommus: [[130, 164], [130, 166]]
is too long
      2 (mediatek,mt8188-mdp3-rdma): iommus: [[129, 164], [129, 166]]
is too long
      2 (mediatek,mt8188-mdp3-rdma): iommus: [[122, 192], [122, 194]]
is too long
      2 (mediatek,mt8188-mdp3-rdma): iommus: [[122, 128], [122, 131]]
is too long
      2 (mediatek,mt8188-mdp3-rdma): iommus: [[121, 192], [121, 194]]
is too long
      2 (mediatek,mt8188-mdp3-rdma): iommus: [[121, 128], [121, 131]]
is too long
      2 (mediatek,mt8188-mdp3-rdma): iommus: [[120, 192], [120, 194]]
is too long
      2 (mediatek,mt8188-mdp3-rdma): iommus: [[120, 128], [120, 131]]
is too long
      2 (mediatek,mt8188-mdp3-rdma): iommus: [[119, 192], [119, 194]]
is too long
      2 (mediatek,mt8188-mdp3-rdma): iommus: [[119, 128], [119, 131]]
is too long
      2 (mediatek,mt8188-mdp3-rdma): clocks: [[44, 12], [39, 186],
[39, 191]] is too long
      2 (mediatek,mt8188-mdp3-rdma): clocks: [[44, 10], [39, 186],
[39, 191]] is too long
      2 (mediatek,mt8188-mdp3-rdma): clocks: [[42, 24], [39, 185],
[39, 190], [42, 4], [42, 41], [42, 42], [42, 7], [44, 41], [44, 42],
[42, 8]] is too long
      2 (mediatek,mt8188-mdp3-rdma): clocks: [[42, 12], [37, 186],
[37, 191]] is too long
      2 (mediatek,mt8188-mdp3-rdma): clocks: [[42, 10], [37, 186],
[37, 191]] is too long
      2 (mediatek,mt8188-mdp3-rdma): clocks: [[40, 24], [37, 185],
[37, 190], [40, 4], [40, 41], [40, 42], [40, 7], [42, 41], [42, 42],
[40, 8]] is too long
      2 (mediatek,mt8188-mdp3-rdma): clocks: [[38, 12], [34, 186],
[34, 191]] is too long
      2 (mediatek,mt8188-mdp3-rdma): clocks: [[38, 10], [34, 186],
[34, 191]] is too long
      2 (mediatek,mt8188-mdp3-rdma): clocks: [[36, 24], [34, 185],
[34, 190], [36, 4], [36, 41], [36, 42], [36, 7], [38, 41], [38, 42],
[36, 8]] is too long
      1 (mediatek,mt8188-mdp3-rsz): clocks: [[44, 24], [44, 25]] is too long
      1 (mediatek,mt8188-mdp3-rsz): clocks: [[44, 20], [44, 21]] is too long
      1 (mediatek,mt8188-mdp3-rsz): clocks: [[42, 24], [42, 25]] is too long
      1 (mediatek,mt8188-mdp3-rsz): clocks: [[42, 20], [42, 21]] is too long
      1 (mediatek,mt8188-mdp3-rsz): clocks: [[38, 24], [38, 25]] is too long
      1 (mediatek,mt8188-mdp3-rsz): clocks: [[38, 20], [38, 21]] is too long
      1 (mediatek,mt8188-mdp3-rdma): power-domains: [[60, 15], [60,
20]] is too long
      1 (mediatek,mt8188-mdp3-rdma): power-domains: [[58, 15], [58,
20]] is too long
      1 (mediatek,mt8188-mdp3-rdma): power-domains: [[54, 15], [54,
20]] is too long
      1 (mediatek,mt8188-mdp3-rdma): mboxes: [[92, 13, 1], [92, 14,
1], [92, 16, 1], [92, 21, 1]] is too short
      1 (mediatek,mt8188-mdp3-rdma): mboxes: [[131, 13, 1], [131, 14,
1], [131, 16, 1], [131, 21, 1]] is too short
      1 (mediatek,mt8188-mdp3-rdma): mboxes: [[129, 13, 1], [129, 14,
1], [129, 16, 1], [129, 21, 1]] is too short
      1 (mediatek,mt8188-mdp3-rdma): iommus: [[93, 192], [93, 194]] is too long
      1 (mediatek,mt8188-mdp3-rdma): iommus: [[93, 128], [93, 131]] is too long
      1 (mediatek,mt8188-mdp3-rdma): iommus: [[142, 164], [142, 166]]
is too long
      1 (mediatek,mt8188-mdp3-rdma): iommus: [[140, 164], [140, 166]]
is too long
      1 (mediatek,mt8188-mdp3-rdma): iommus: [[132, 192], [132, 194]]
is too long
      1 (mediatek,mt8188-mdp3-rdma): iommus: [[132, 128], [132, 131]]
is too long
      1 (mediatek,mt8188-mdp3-rdma): iommus: [[130, 192], [130, 194]]
is too long
      1 (mediatek,mt8188-mdp3-rdma): iommus: [[130, 128], [130, 131]]
is too long
      1 (mediatek,mt8188-mdp3-rdma): iommus: [[103, 164], [103, 166]]
is too long


>       arm64: dts: mediatek: Add MT6893 pinmux macro header file
>       arm64: dts: mediatek: mt8390-genio-common: Add Display on DSI0
>
> Axe Yang (1):
>       arm64: dts: mediatek: mt8186-corsola: make SDIO card removable
>
> Cathy Xu (1):
>       arm64: dts: mediatek: mt8196: Add pinmux macro header file
>
> Chen-Yu Tsai (1):
>       arm64: dts: mediatek: mt8188: Fix IOMMU device for rdma0
>
> Jianeng Ceng (2):
>       dt-bindings: arm: mediatek: Add MT8186 Ponyta Chromebook
>       arm64: dts: mediatek: Add MT8186 Ponyta Chromebooks
>
> Julien Massot (4):
>       arm64: dts: mediatek: mt8395-nio-12l: Add scp firmware-name
>       arm64: dts: mediatek: mt8395-genio-1200-evk: Add scp firmware-name
>       arm64: dts: mediatek: mt8395-nio-12l: Enable Audio DSP and sound card
>       arm64: dts: mt6359: Add missing 'compatible' property to regulators node
>
> Louis-Alexis Eyraud (3):
>       arm64: dts: mediatek: mt8390-genio-common: Fix pcie pinctrl dtbs_check error
>       arm64: dts: mediatek: mt8395-genio-1200-evk: Add display on DSI0
>       arm64: dts: mediatek: mt8390-genio-common: Set ssusb2 default dual role mode to host
>
> Macpaul Lin (1):
>       arm64: dts: mediatek: mt8195: Add power domain for dp_intf0
>
> N?colas F. R. A. Prado (4):
>       arm64: dts: mediatek: mt8188: Describe SCP as a cluster with two cores
>       arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0
>       arm64: dts: mediatek: mt6357: Drop regulator-fixed compatibles
>       arm64: dts: mediatek: mt8395-genio-1200-evk: Disable unused backlight
>
> Pin-yen Lin (1):
>       arm64: dts: mt8183: Add port node to mt8183.dtsi
>
> Rob Herring (Arm) (1):
>       arm/arm64: dts: mediatek: Add missing "#sound-dai-cells" to linux,bt-sco
>
> ?ukasz Majczak (1):
>       arm64: dts: mediatek: mt8186: starmie: Fix external display
>
>  Documentation/devicetree/bindings/arm/mediatek.yaml                      |    7 +
>  Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml     |    4 +
>  Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml   |    4 +
>  Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml   |    4 +
>  Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml |   10 +-
>  Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml            |    8 +-
>  Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml           |    8 +-
>  Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml           |    1 +
>  Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml        |    8 +-
>  Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml           |    8 +-
>  Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml         |    8 +-
>  Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml          |    1 +
>  arch/arm/boot/dts/mediatek/mt2701-evb.dts                                |    1 +
>  arch/arm64/boot/dts/mediatek/Makefile                                    |    2 +
>  arch/arm64/boot/dts/mediatek/mt6357.dtsi                                 |   10 -
>  arch/arm64/boot/dts/mediatek/mt6359.dtsi                                 |    2 +
>  arch/arm64/boot/dts/mediatek/mt6893-pinfunc.h                            | 1356 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi                           |   11 +-
>  arch/arm64/boot/dts/mediatek/mt8183.dtsi                                 |    4 +
>  arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku0.dts              |   18 +
>  arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku1.dts              |   22 +
>  arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta.dtsi                  |   49 ++
>  arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie.dtsi                 |   45 --
>  arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi                         |    1 -
>  arch/arm64/boot/dts/mediatek/mt8188-evb.dts                              |    6 +-
>  arch/arm64/boot/dts/mediatek/mt8188.dtsi                                 |  349 ++++++++++++++-
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi                                 |   51 ++-
>  arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h                            | 1574 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi                    |  170 ++++++-
>  arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts                   |  127 +++++-
>  arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts                    |   59 ++-
>  31 files changed, 3797 insertions(+), 131 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt6893-pinfunc.h
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku0.dts
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku1.dts
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta.dtsi
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h
>
>


From robh at kernel.org  Tue May 13 11:40:41 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Tue, 13 May 2025 13:40:41 -0500
Subject: [PATCH] dt-bindings: crypto: Drop obsolete mediatek,eip97-crypto
Message-ID: <20250513184042.3051424-1-robh@kernel.org>

The mediatek,eip97-crypto binding is half abandoned. The driver was
dropped in 2020 as the Mediatek platforms use InsideSecure block and
the driver for it. All the platforms except MT7623 were updated. A
patch to update it was submitted, but never addressed the review
comments.

Link: https://lore.kernel.org/all/20210303080923.16761-1-vic.wu at mediatek.com/
Signed-off-by: Rob Herring (Arm) <robh at kernel.org>
---
 .../bindings/crypto/mediatek-crypto.txt       | 25 -------------------
 1 file changed, 25 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/crypto/mediatek-crypto.txt

diff --git a/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt b/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt
deleted file mode 100644
index 450da3661cad..000000000000
--- a/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-MediaTek cryptographic accelerators
-
-Required properties:
-- compatible: Should be "mediatek,eip97-crypto"
-- reg: Address and length of the register set for the device
-- interrupts: Should contain the five crypto engines interrupts in numeric
-	order. These are global system and four descriptor rings.
-- clocks: the clock used by the core
-- clock-names: Must contain "cryp".
-- power-domains: Must contain a reference to the PM domain.
-
-
-Example:
-	crypto: crypto at 1b240000 {
-		compatible = "mediatek,eip97-crypto";
-		reg = <0 0x1b240000 0 0x20000>;
-		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
-		clock-names = "cryp";
-		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
-	};
-- 
2.47.2



From sean.anderson at seco.com  Tue May 13 11:40:57 2025
From: sean.anderson at seco.com (Sean Anderson)
Date: Tue, 13 May 2025 14:40:57 -0400
Subject: [net-next PATCH v4 05/11] net: pcs: implement Firmware node
 support for PCS driver
In-Reply-To: <20250511201250.3789083-6-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-6-ansuelsmth@gmail.com>
Message-ID: <5fb7afec-c216-4912-bb7f-a2bd86dcfcad@seco.com>

On 5/11/25 16:12, Christian Marangi wrote:
> Implement the foundation of Firmware node support for PCS driver.
> 
> To support this, implement a simple Provider API where a PCS driver can
> expose multiple PCS with an xlate .get function.
> 
> PCS driver will have to call fwnode_pcs_add_provider() and pass the
> firmware node pointer and a xlate function to return the correct PCS for
> the passed #pcs-cells.
> 
> This will register the PCS in a global list of providers so that
> consumer can access it.
> 
> The consumer will then use fwnode_pcs_get() to get the actual PCS by
> passing the firmware node pointer and the index for #pcs-cells.
> 
> For a simple implementation where #pcs-cells is 0 and the PCS driver
> expose a single PCS, the xlate function fwnode_pcs_simple_get() is
> provided.
> 
> For an advanced implementation a custom xlate function is required.

There is no use case for this. All PCSs have a fwnode per PCS. Removing
support for pcs cells will simplify the lookup code as well as the
registration code and API.

> One removal the PCS driver should first delete itself from the provider
> list using fwnode_pcs_del_provider() and then call phylink_release_pcs()
> on every PCS the driver provides.

And things like this can be done automatically.

> A generic function fwnode_phylink_pcs_parse() is provided for MAC driver
> that will declare PCS in DT (or ACPI).
> This function will parse "pcs-handle" property and fill the passed array
> with the parsed PCS in availabel_pcs up to the passed num_pcs value.
> It's also possible to pass NULL as array to only parse the PCS and
> update the num_pcs value with the count of scanned PCS.

When is this useful?

> Co-developed-by: Daniel Golle <daniel at makrotopia.org>
> Signed-off-by: Daniel Golle <daniel at makrotopia.org>
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---
>  drivers/net/pcs/Kconfig          |   6 +
>  drivers/net/pcs/Makefile         |   1 +
>  drivers/net/pcs/pcs.c            | 201 +++++++++++++++++++++++++++++++
>  include/linux/pcs/pcs-provider.h |  41 +++++++
>  include/linux/pcs/pcs.h          |  56 +++++++++
>  5 files changed, 305 insertions(+)
>  create mode 100644 drivers/net/pcs/pcs.c
>  create mode 100644 include/linux/pcs/pcs-provider.h
>  create mode 100644 include/linux/pcs/pcs.h
> 
> diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
> index f6aa437473de..0d54bea1f663 100644
> --- a/drivers/net/pcs/Kconfig
> +++ b/drivers/net/pcs/Kconfig
> @@ -5,6 +5,12 @@
>  
>  menu "PCS device drivers"
>  
> +config FWNODE_PCS
> +	tristate
> +	depends on (ACPI || OF)
> +	help
> +		Firmware node PCS accessors
> +
>  config PCS_XPCS
>  	tristate "Synopsys DesignWare Ethernet XPCS"
>  	select PHYLINK
> diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
> index 4f7920618b90..3005cdd89ab7 100644
> --- a/drivers/net/pcs/Makefile
> +++ b/drivers/net/pcs/Makefile
> @@ -1,6 +1,7 @@
>  # SPDX-License-Identifier: GPL-2.0
>  # Makefile for Linux PCS drivers
>  
> +obj-$(CONFIG_FWNODE_PCS)	+= pcs.o
>  pcs_xpcs-$(CONFIG_PCS_XPCS)	:= pcs-xpcs.o pcs-xpcs-plat.o \
>  				   pcs-xpcs-nxp.o pcs-xpcs-wx.o
>  
> diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
> new file mode 100644
> index 000000000000..26d07a2edfce
> --- /dev/null
> +++ b/drivers/net/pcs/pcs.c
> @@ -0,0 +1,201 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +
> +#include <linux/mutex.h>
> +#include <linux/property.h>
> +#include <linux/phylink.h>
> +#include <linux/pcs/pcs.h>
> +#include <linux/pcs/pcs-provider.h>
> +
> +MODULE_DESCRIPTION("PCS library");
> +MODULE_AUTHOR("Christian Marangi <ansuelsmth at gmail.com>");
> +MODULE_LICENSE("GPL");
> +
> +struct fwnode_pcs_provider {
> +	struct list_head link;
> +
> +	struct fwnode_handle *fwnode;
> +	struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
> +				   void *data);
> +
> +	void *data;
> +};
> +
> +static LIST_HEAD(fwnode_pcs_providers);
> +static DEFINE_MUTEX(fwnode_pcs_mutex);
> +
> +struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
> +					  void *data)
> +{
> +	return data;
> +}
> +EXPORT_SYMBOL_GPL(fwnode_pcs_simple_get);
> +
> +int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
> +			    struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
> +						       void *data),
> +			    void *data)
> +{
> +	struct fwnode_pcs_provider *pp;
> +
> +	if (!fwnode)
> +		return 0;
> +
> +	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
> +	if (!pp)
> +		return -ENOMEM;
> +
> +	pp->fwnode = fwnode_handle_get(fwnode);
> +	pp->data = data;
> +	pp->get = get;
> +
> +	mutex_lock(&fwnode_pcs_mutex);
> +	list_add(&pp->link, &fwnode_pcs_providers);
> +	mutex_unlock(&fwnode_pcs_mutex);
> +	pr_debug("Added pcs provider from %pfwf\n", fwnode);
> +
> +	fwnode_dev_initialized(fwnode, true);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
> +
> +void fwnode_pcs_del_provider(struct fwnode_handle *fwnode)
> +{
> +	struct fwnode_pcs_provider *pp;
> +
> +	if (!fwnode)
> +		return;
> +
> +	mutex_lock(&fwnode_pcs_mutex);
> +	list_for_each_entry(pp, &fwnode_pcs_providers, link) {
> +		if (pp->fwnode == fwnode) {
> +			list_del(&pp->link);
> +			fwnode_dev_initialized(pp->fwnode, false);
> +			fwnode_handle_put(pp->fwnode);
> +			kfree(pp);
> +			break;
> +		}
> +	}
> +	mutex_unlock(&fwnode_pcs_mutex);
> +}
> +EXPORT_SYMBOL_GPL(fwnode_pcs_del_provider);
> +
> +static int fwnode_parse_pcsspec(const struct fwnode_handle *fwnode, int index,
> +				const char *name,
> +				struct fwnode_reference_args *out_args)
> +{
> +	int ret;
> +
> +	if (!fwnode)
> +		return -ENOENT;
> +
> +	if (name)
> +		index = fwnode_property_match_string(fwnode, "pcs-names",
> +						     name);
> +
> +	ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
> +						 "#pcs-cells",
> +						 -1, index, out_args);
> +	if (ret || (name && index < 0))
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static struct phylink_pcs *
> +fwnode_pcs_get_from_pcsspec(struct fwnode_reference_args *pcsspec)
> +{
> +	struct fwnode_pcs_provider *provider;
> +	struct phylink_pcs *pcs = ERR_PTR(-EPROBE_DEFER);
> +
> +	if (!pcsspec)
> +		return ERR_PTR(-EINVAL);
> +
> +	mutex_lock(&fwnode_pcs_mutex);
> +	list_for_each_entry(provider, &fwnode_pcs_providers, link) {
> +		if (provider->fwnode == pcsspec->fwnode) {
> +			pcs = provider->get(pcsspec, provider->data);
> +			if (!IS_ERR(pcs))
> +				break;
> +		}
> +	}
> +	mutex_unlock(&fwnode_pcs_mutex);
> +
> +	return pcs;
> +}
> +
> +static struct phylink_pcs *__fwnode_pcs_get(struct fwnode_handle *fwnode,
> +					    int index, const char *con_id)

Many existing drivers have to support non-standard PCS handle names
(e.g. pcsphy-handle, phy-handle, etc.). Support for this is important
for converting those drivers to use this system.

--Sean

> +{
> +	struct fwnode_reference_args pcsspec;
> +	struct phylink_pcs *pcs;
> +	int ret;
> +
> +	ret = fwnode_parse_pcsspec(fwnode, index, con_id, &pcsspec);
> +	if (ret)
> +		return ERR_PTR(ret);
> +
> +	pcs = fwnode_pcs_get_from_pcsspec(&pcsspec);
> +	fwnode_handle_put(pcsspec.fwnode);
> +
> +	return pcs;
> +}
> +
> +struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, int index)
> +{
> +	return __fwnode_pcs_get(fwnode, index, NULL);
> +}
> +EXPORT_SYMBOL_GPL(fwnode_pcs_get);
> +
> +static int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode,
> +				    unsigned int *num_pcs)
> +{
> +	struct fwnode_reference_args out_args;
> +	int index = 0;
> +	int ret;
> +
> +	while (true) {
> +		ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
> +							 "#pcs-cells",
> +							 -1, index, &out_args);
> +		/* We expect to reach an -ENOENT error while counting */
> +		if (ret)
> +			break;
> +
> +		fwnode_handle_put(out_args.fwnode);
> +		index++;
> +	}
> +
> +	/* Update num_pcs with parsed PCS */
> +	*num_pcs = index;
> +
> +	/* Return error if we didn't found any PCS */
> +	return index > 0 ? 0 : -ENOENT;
> +}
> +
> +int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
> +			     struct phylink_pcs **available_pcs,
> +			     unsigned int *num_pcs)
> +{
> +	int i;
> +
> +	if (!fwnode_property_present(fwnode, "pcs-handle"))
> +		return -ENODEV;
> +
> +	/* With available_pcs NULL, only count the PCS */
> +	if (!available_pcs)
> +		return fwnode_phylink_pcs_count(fwnode, num_pcs);
> +
> +	for (i = 0; i < *num_pcs; i++) {
> +		struct phylink_pcs *pcs;
> +
> +		pcs = fwnode_pcs_get(fwnode, i);
> +		if (IS_ERR(pcs))
> +			return PTR_ERR(pcs);
> +
> +		available_pcs[i] = pcs;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_parse);
> diff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h
> new file mode 100644
> index 000000000000..ae51c108147e
> --- /dev/null
> +++ b/include/linux/pcs/pcs-provider.h
> @@ -0,0 +1,41 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +#ifndef __LINUX_PCS_PROVIDER_H
> +#define __LINUX_PCS_PROVIDER_H
> +
> +/**
> + * fwnode_pcs_simple_get - Simple xlate function to retrieve PCS
> + * @pcsspec: reference arguments
> + * @data: Context data (assumed assigned to the single PCS)
> + *
> + * Returns: the PCS pointed by data.
> + */
> +struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
> +					  void *data);
> +
> +/**
> + * fwnode_pcs_add_provider - Registers a new PCS provider
> + * @fwnode: Firmware node
> + * @get: xlate function to retrieve the PCS
> + * @data: Context data
> + *
> + * Register and add a new PCS to the global providers list
> + * for the firmware node. A function to get the PCS from
> + * firmware node with the use fwnode reference arguments.
> + * To the get function is also passed the interface type
> + * requested for the PHY. PCS driver will use the passed
> + * interface to understand if the PCS can support it or not.
> + *
> + * Returns: 0 on success or -ENOMEM on allocation failure.
> + */
> +int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
> +			    struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
> +						       void *data),
> +			    void *data);
> +
> +/**
> + * fwnode_pcs_del_provider - Removes a PCS provider
> + * @fwnode: Firmware node
> + */
> +void fwnode_pcs_del_provider(struct fwnode_handle *fwnode);
> +
> +#endif /* __LINUX_PCS_PROVIDER_H */
> diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
> new file mode 100644
> index 000000000000..33244e3a442b
> --- /dev/null
> +++ b/include/linux/pcs/pcs.h
> @@ -0,0 +1,56 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +#ifndef __LINUX_PCS_H
> +#define __LINUX_PCS_H
> +
> +#include <linux/phylink.h>
> +
> +#if IS_ENABLED(CONFIG_FWNODE_PCS)
> +/**
> + * fwnode_pcs_get - Retrieves a PCS from a firmware node
> + * @fwnode: firmware node
> + * @index: index fwnode PCS handle in firmware node
> + *
> + * Get a PCS from the firmware node at index.
> + *
> + * Returns: a pointer to the phylink_pcs or a negative
> + * error pointer. Can return -EPROBE_DEFER if the PCS is not
> + * present in global providers list (either due to driver
> + * still needs to be probed or it failed to probe/removed)
> + */
> +struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
> +				   int index);
> +
> +/**
> + * fwnode_phylink_pcs_parse - generic PCS parse for fwnode PCS provider
> + * @fwnode: firmware node
> + * @available_pcs: pointer to preallocated array of PCS
> + * @num_pcs: where to store count of parsed PCS
> + *
> + * Generic helper function to fill available_pcs array with PCS parsed
> + * from a "pcs-handle" fwnode property defined in firmware node up to
> + * passed num_pcs.
> + *
> + * If available_pcs is NULL, num_pcs is updated with the count of the
> + * parsed PCS.
> + *
> + * Returns: 0 or a negative error.
> + */
> +int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
> +			     struct phylink_pcs **available_pcs,
> +			     unsigned int *num_pcs);
> +#else
> +static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
> +						 int index)
> +{
> +	return ERR_PTR(-ENOENT);
> +}
> +
> +static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
> +					   struct phylink_pcs **available_pcs,
> +					   unsigned int *num_pcs)
> +{
> +	return -EOPNOTSUPP;
> +}
> +#endif
> +
> +#endif /* __LINUX_PCS_H */


From sean.anderson at linux.dev  Tue May 13 11:44:42 2025
From: sean.anderson at linux.dev (Sean Anderson)
Date: Tue, 13 May 2025 14:44:42 -0400
Subject: [net-next PATCH v4 08/11] net: phylink: add .pcs_link_down PCS OP
In-Reply-To: <20250511201250.3789083-9-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-9-ansuelsmth@gmail.com>
Message-ID: <bb2a379e-c701-4b50-932a-20dcfbb0ebea@linux.dev>

On 5/11/25 16:12, Christian Marangi wrote:
> Permit for PCS driver to define specific operation to torn down the link
> between the MAC and the PCS.
> 
> This might be needed for some PCS that reset counter

Counters must be preserved across link u/down.

> or require special
> reset to correctly work if the link needs to be restored later.

Can you describe this in more detail?

> On phylink_link_down() call, the additional phylink_pcs_link_down() will
> be called before .mac_link_down to torn down the link.

tear

> PCS driver will need to define .pcs_link_down to make use of this.
> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---
>  drivers/net/phy/phylink.c | 8 ++++++++
>  include/linux/phylink.h   | 2 ++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
> index 1a4df0d24aa2..39cd15e30598 100644
> --- a/drivers/net/phy/phylink.c
> +++ b/drivers/net/phy/phylink.c
> @@ -1009,6 +1009,12 @@ static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
>  		pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex);
>  }
>  
> +static void phylink_pcs_link_down(struct phylink_pcs *pcs)
> +{
> +	if (pcs && pcs->ops->pcs_link_down)
> +		pcs->ops->pcs_link_down(pcs);
> +}
> +
>  static void phylink_pcs_disable_eee(struct phylink_pcs *pcs)
>  {
>  	if (pcs && pcs->ops->pcs_disable_eee)
> @@ -1686,6 +1692,8 @@ static void phylink_link_down(struct phylink *pl)
>  
>  	phylink_deactivate_lpi(pl);
>  
> +	phylink_pcs_link_down(pl->pcs);
> +
>  	pl->mac_ops->mac_link_down(pl->config, pl->act_link_an_mode,
>  				   pl->cur_interface);
>  	phylink_info(pl, "Link is Down\n");
> diff --git a/include/linux/phylink.h b/include/linux/phylink.h
> index c5496c063b6a..8b3d1dfb83a1 100644
> --- a/include/linux/phylink.h
> +++ b/include/linux/phylink.h
> @@ -494,6 +494,7 @@ struct phylink_pcs {
>   * @pcs_an_restart: restart 802.3z BaseX autonegotiation.
>   * @pcs_link_up: program the PCS for the resolved link configuration
>   *               (where necessary).
> + * @pcs_link_down: torn down link between MAC and PCS.

ops documentation should use imperative verbs.

You are also missing the longer documentation below.

>   * @pcs_disable_eee: optional notification to PCS that EEE has been disabled
>   *		     at the MAC.
>   * @pcs_enable_eee: optional notification to PCS that EEE will be enabled at
> @@ -521,6 +522,7 @@ struct phylink_pcs_ops {
>  	void (*pcs_an_restart)(struct phylink_pcs *pcs);
>  	void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode,
>  			    phy_interface_t interface, int speed, int duplex);
> +	void (*pcs_link_down)(struct phylink_pcs *pcs);
>  	void (*pcs_disable_eee)(struct phylink_pcs *pcs);
>  	void (*pcs_enable_eee)(struct phylink_pcs *pcs);
>  	int (*pcs_pre_init)(struct phylink_pcs *pcs);



From sean.anderson at seco.com  Tue May 13 11:50:49 2025
From: sean.anderson at seco.com (Sean Anderson)
Date: Tue, 13 May 2025 14:50:49 -0400
Subject: [net-next PATCH v4 11/11] net: airoha: add phylink support for
 GDM2/3/4
In-Reply-To: <20250511201250.3789083-12-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-12-ansuelsmth@gmail.com>
Message-ID: <19547e54-1253-409d-8e89-a395fed478a0@seco.com>

On 5/11/25 16:12, Christian Marangi wrote:
> Add phylink support for GDM2/3/4 port that require configuration of the
> PCS to make the external PHY or attached SFP cage work.
> 
> These needs to be defined in the GDM port node using the pcs-handle
> property.
> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---
>  drivers/net/ethernet/airoha/airoha_eth.c  | 155 +++++++++++++++++++++-
>  drivers/net/ethernet/airoha/airoha_eth.h  |   3 +
>  drivers/net/ethernet/airoha/airoha_regs.h |  12 ++
>  3 files changed, 169 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index 16c7896f931f..3be1ae077a76 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -7,6 +7,7 @@
>  #include <linux/of_net.h>
>  #include <linux/platform_device.h>
>  #include <linux/tcp.h>
> +#include <linux/pcs/pcs.h>
>  #include <linux/u64_stats_sync.h>
>  #include <net/dst_metadata.h>
>  #include <net/page_pool/helpers.h>
> @@ -79,6 +80,11 @@ static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
>  	return port->id == 1;
>  }
>  
> +static bool airhoa_is_phy_external(struct airoha_gdm_port *port)
> +{
> +	return port->id != 1;
> +}
> +
>  static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
>  {
>  	struct airoha_eth *eth = port->qdma->eth;
> @@ -1613,6 +1619,17 @@ static int airoha_dev_open(struct net_device *dev)
>  	struct airoha_gdm_port *port = netdev_priv(dev);
>  	struct airoha_qdma *qdma = port->qdma;
>  
> +	if (airhoa_is_phy_external(port)) {
> +		err = phylink_of_phy_connect(port->phylink, dev->dev.of_node, 0);
> +		if (err) {
> +			netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
> +				   err);
> +			return err;
> +		}
> +
> +		phylink_start(port->phylink);
> +	}
> +
>  	netif_tx_start_all_queues(dev);
>  	err = airoha_set_vip_for_gdm_port(port, true);
>  	if (err)
> @@ -1665,6 +1682,11 @@ static int airoha_dev_stop(struct net_device *dev)
>  		}
>  	}
>  
> +	if (airhoa_is_phy_external(port)) {
> +		phylink_stop(port->phylink);
> +		phylink_disconnect_phy(port->phylink);
> +	}
> +
>  	return 0;
>  }
>  
> @@ -2795,6 +2817,115 @@ bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
>  	return false;
>  }
>  
> +static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,
> +			       unsigned int mode, phy_interface_t interface,
> +			       int speed, int duplex, bool tx_pause, bool rx_pause)
> +{
> +	struct airoha_gdm_port *port = container_of(config, struct airoha_gdm_port,
> +						    phylink_config);
> +	struct airoha_qdma *qdma = port->qdma;
> +	struct airoha_eth *eth = qdma->eth;
> +	u32 frag_size_tx, frag_size_rx;
> +
> +	if (port->id != 4)
> +		return;
> +
> +	switch (speed) {
> +	case SPEED_10000:
> +	case SPEED_5000:
> +		frag_size_tx = 8;
> +		frag_size_rx = 8;
> +		break;
> +	case SPEED_2500:
> +		frag_size_tx = 2;
> +		frag_size_rx = 1;
> +		break;
> +	default:
> +		frag_size_tx = 1;
> +		frag_size_rx = 0;
> +	}
> +
> +	/* Configure TX/RX frag based on speed */
> +	airoha_fe_rmw(eth, REG_GDMA4_TMBI_FRAG,
> +		      GDMA4_SGMII0_TX_FRAG_SIZE_MASK,
> +		      FIELD_PREP(GDMA4_SGMII0_TX_FRAG_SIZE_MASK,
> +				 frag_size_tx));
> +
> +	airoha_fe_rmw(eth, REG_GDMA4_RMBI_FRAG,
> +		      GDMA4_SGMII0_RX_FRAG_SIZE_MASK,
> +		      FIELD_PREP(GDMA4_SGMII0_RX_FRAG_SIZE_MASK,
> +				 frag_size_rx));
> +}
> +
> +static const struct phylink_mac_ops airoha_phylink_ops = {
> +	.mac_link_up = airoha_mac_link_up,
> +};
> +
> +static int airoha_setup_phylink(struct net_device *dev)
> +{
> +	struct airoha_gdm_port *port = netdev_priv(dev);
> +	struct device_node *np = dev->dev.of_node;
> +	struct phylink_pcs **available_pcs;
> +	phy_interface_t phy_mode;
> +	struct phylink *phylink;
> +	unsigned int num_pcs;
> +	int err;
> +
> +	err = of_get_phy_mode(np, &phy_mode);
> +	if (err) {
> +		dev_err(&dev->dev, "incorrect phy-mode\n");
> +		return err;
> +	}
> +
> +	port->phylink_config.dev = &dev->dev;
> +	port->phylink_config.type = PHYLINK_NETDEV;
> +	port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
> +						MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD |
> +						MAC_5000FD | MAC_10000FD;
> +
> +	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), NULL, &num_pcs);
> +	if (err)
> +		return err;
> +
> +	available_pcs = kcalloc(num_pcs, sizeof(*available_pcs), GFP_KERNEL);
> +	if (!available_pcs)
> +		return -ENOMEM;
> +
> +	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), available_pcs,
> +				       &num_pcs);
> +	if (err)
> +		goto out;

OK, so say you have PCSs A, B, and C. phylink determines that you are
going to use B. But where do you select the PCS? Don't you have to
configure a mux or something?

--Sean

> +	port->phylink_config.available_pcs = available_pcs;
> +	port->phylink_config.num_available_pcs = num_pcs;
> +
> +	__set_bit(PHY_INTERFACE_MODE_SGMII,
> +		  port->phylink_config.supported_interfaces);
> +	__set_bit(PHY_INTERFACE_MODE_1000BASEX,
> +		  port->phylink_config.supported_interfaces);
> +	__set_bit(PHY_INTERFACE_MODE_2500BASEX,
> +		  port->phylink_config.supported_interfaces);
> +	__set_bit(PHY_INTERFACE_MODE_USXGMII,
> +		  port->phylink_config.supported_interfaces);
> +
> +	phy_interface_copy(port->phylink_config.pcs_interfaces,
> +			   port->phylink_config.supported_interfaces);
> +
> +	phylink = phylink_create(&port->phylink_config,
> +				 of_fwnode_handle(np),
> +				 phy_mode, &airoha_phylink_ops);
> +	if (IS_ERR(phylink)) {
> +		err = PTR_ERR(phylink);
> +		goto out;
> +	}
> +
> +	port->phylink = phylink;
> +out:
> +	kfree(available_pcs);
> +
> +	return err;
> +}
> +
>  static int airoha_alloc_gdm_port(struct airoha_eth *eth,
>  				 struct device_node *np, int index)
>  {
> @@ -2873,7 +3004,23 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
>  	if (err)
>  		return err;
>  
> -	return register_netdev(dev);
> +	if (airhoa_is_phy_external(port)) {
> +		err = airoha_setup_phylink(dev);
> +		if (err)
> +			return err;
> +	}
> +
> +	err = register_netdev(dev);
> +	if (err)
> +		goto free_phylink;
> +
> +	return 0;
> +
> +free_phylink:
> +	if (airhoa_is_phy_external(port))
> +		phylink_destroy(port->phylink);
> +
> +	return err;
>  }
>  
>  static int airoha_probe(struct platform_device *pdev)
> @@ -2967,6 +3114,9 @@ static int airoha_probe(struct platform_device *pdev)
>  		struct airoha_gdm_port *port = eth->ports[i];
>  
>  		if (port && port->dev->reg_state == NETREG_REGISTERED) {
> +			if (airhoa_is_phy_external(port))
> +				phylink_destroy(port->phylink);
> +
>  			unregister_netdev(port->dev);
>  			airoha_metadata_dst_free(port);
>  		}
> @@ -2994,6 +3144,9 @@ static void airoha_remove(struct platform_device *pdev)
>  			continue;
>  
>  		airoha_dev_stop(port->dev);
> +		if (airhoa_is_phy_external(port))
> +			phylink_destroy(port->phylink);
> +
>  		unregister_netdev(port->dev);
>  		airoha_metadata_dst_free(port);
>  	}
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
> index 53f39083a8b0..73a500474076 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.h
> +++ b/drivers/net/ethernet/airoha/airoha_eth.h
> @@ -498,6 +498,9 @@ struct airoha_gdm_port {
>  	struct net_device *dev;
>  	int id;
>  
> +	struct phylink *phylink;
> +	struct phylink_config phylink_config;
> +
>  	struct airoha_hw_stats stats;
>  
>  	DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
> diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
> index d931530fc96f..54f7079b28b0 100644
> --- a/drivers/net/ethernet/airoha/airoha_regs.h
> +++ b/drivers/net/ethernet/airoha/airoha_regs.h
> @@ -357,6 +357,18 @@
>  #define IP_FRAGMENT_PORT_MASK		GENMASK(8, 5)
>  #define IP_FRAGMENT_NBQ_MASK		GENMASK(4, 0)
>  
> +#define REG_GDMA4_TMBI_FRAG		0x2028
> +#define GDMA4_SGMII1_TX_WEIGHT_MASK	GENMASK(31, 26)
> +#define GDMA4_SGMII1_TX_FRAG_SIZE_MASK	GENMASK(25, 16)
> +#define GDMA4_SGMII0_TX_WEIGHT_MASK	GENMASK(15, 10)
> +#define GDMA4_SGMII0_TX_FRAG_SIZE_MASK	GENMASK(9, 0)
> +
> +#define REG_GDMA4_RMBI_FRAG		0x202c
> +#define GDMA4_SGMII1_RX_WEIGHT_MASK	GENMASK(31, 26)
> +#define GDMA4_SGMII1_RX_FRAG_SIZE_MASK	GENMASK(25, 16)
> +#define GDMA4_SGMII0_RX_WEIGHT_MASK	GENMASK(15, 10)
> +#define GDMA4_SGMII0_RX_FRAG_SIZE_MASK	GENMASK(9, 0)
> +
>  #define REG_MC_VLAN_EN			0x2100
>  #define MC_VLAN_EN_MASK			BIT(0)
>  


From daniel at makrotopia.org  Tue May 13 12:03:27 2025
From: daniel at makrotopia.org (Daniel Golle)
Date: Tue, 13 May 2025 20:03:27 +0100
Subject: [net-next PATCH v4 03/11] net: phylink: introduce internal
 phylink PCS handling
In-Reply-To: <5d004048-ef8f-42ad-8f17-d1e4d495f57f@linux.dev>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-4-ansuelsmth@gmail.com>
 <5d004048-ef8f-42ad-8f17-d1e4d495f57f@linux.dev>
Message-ID: <aCOXfw-krDZo9phk@makrotopia.org>

On Tue, May 13, 2025 at 02:18:02PM -0400, Sean Anderson wrote:
> On 5/11/25 16:12, Christian Marangi wrote:
> > Introduce internal handling of PCS for phylink. This is an alternative
> > to .mac_select_pcs that moves the selection logic of the PCS entirely to
> > phylink with the usage of the supported_interface value in the PCS
> > struct.
> > 
> > MAC should now provide an array of available PCS in phylink_config in
> > .available_pcs and fill the .num_available_pcs with the number of
> > elements in the array. MAC should also define a new bitmap,
> > pcs_interfaces, in phylink_config to define for what interface mode a
> > dedicated PCS is required.
> > 
> > On phylink_create() this array is parsed and a linked list of PCS is
> > created based on the PCS passed in phylink_config.
> > Also the supported_interface value in phylink struct is updated with the
> > new supported_interface from the provided PCS.
> > 
> > On phylink_start() every PCS in phylink PCS list gets attached to the
> > phylink instance. This is done by setting the phylink value in
> > phylink_pcs struct to the phylink instance.
> > 
> > On phylink_stop(), every PCS in phylink PCS list is detached from the
> > phylink instance. This is done by setting the phylink value in
> > phylink_pcs struct to NULL.
> > 
> > phylink_validate_mac_and_pcs(), phylink_major_config() and
> > phylink_inband_caps() are updated to support this new implementation
> > with the PCS list stored in phylink.
> > 
> > They will make use of phylink_validate_pcs_interface() that will loop
> > for every PCS in the phylink PCS available list and find one that supports
> > the passed interface.
> > 
> > phylink_validate_pcs_interface() applies the same logic of .mac_select_pcs
> > where if a supported_interface value is not set for the PCS struct, then
> > it's assumed every interface is supported.
> > 
> > A MAC is required to implement either a .mac_select_pcs or make use of
> > the PCS list implementation. Implementing both will result in a fail
> > on MAC/PCS validation.
> > 
> > phylink value in phylink_pcs struct with this implementation is used to
> > track from PCS side when it's attached to a phylink instance. PCS driver
> > will make use of this information to correctly detach from a phylink
> > instance if needed.
> > 
> > The .mac_select_pcs implementation is not changed but it's expected that
> > every MAC driver migrates to the new implementation to later deprecate
> > and remove .mac_select_pcs.
> 
> This introduces a completely parallel PCS selection system used by a
> single driver. I don't think we want the maintenance burden and
> complexity of two systems in perpetuity. So what is your plan for
> conversion of existing drivers to your new system?

Moving functionality duplicated in many drivers to a common shared
implementation is nothing unsual.

While this series proposes the new mechanism for Airoha SoC, they are
immediately useful (and long awaited) also for MediaTek and Qualcomm
SoCs.

Also in the series you posted at least the macb driver (in "[net-next
PATCH v4 09/11] net: macb: Move most of mac_config to  mac_prepare")
would benefit from that shared implementation, as all it does in it's
mac_select_pcs is selecting the PCS by a given phy_interface_t, which is
what most Ethernet drivers which use more than one PCS are doing in
their implementatio of mac_select_pcs().

Also axienet_mac_select_pcs() from "[net-next PATCH v4 08/11] net:
axienet: Convert to use PCS subsystem" could obviously very easily be
mirated to use the phylink-internal handling of PCS selection.


> 
> DSA drivers typically have different PCSs for each port. At the moment
> these are selected with mac_select_pcs, allowing the use of a single
> phylink_config for each port. If you need to pass PCSs through
> phylink_config then each port will needs its own config. This may prove
> difficult to integrate with the existing API.

This might be a misunderstanding. Also here there is only a single
phylink_config for each MAC or DSA port, just instead of having many
more or less identical implementations of .mac_select_pcs, this
functionality is moved into phylink. As a nice side-effect that also
makes managing the life-cycle of the PCS more easy, so we won't need all
the wrappers for all the PCS OPs.


From tsbogend at alpha.franken.de  Tue May 13 08:12:23 2025
From: tsbogend at alpha.franken.de (Thomas Bogendoerfer)
Date: Tue, 13 May 2025 17:12:23 +0200
Subject: [PATCH v5 0/7] Add EcoNet EN751221 MIPS platform support
In-Reply-To: <aCNWM5Xq7wnHVCrc@mai.linaro.org>
References: <20250507134500.390547-1-cjd@cjdns.fr>
 <aCNWM5Xq7wnHVCrc@mai.linaro.org>
Message-ID: <aCNhVw7oMRhHQNq_@alpha.franken.de>

On Tue, May 13, 2025 at 04:24:51PM +0200, Daniel Lezcano wrote:
> On Wed, May 07, 2025 at 01:44:53PM +0000, Caleb James DeLisle wrote:
> > EcoNet MIPS SoCs are big endian machines based on 34Kc and 1004Kc
> > processors. They are found in xDSL and xPON modems, and contain PCM
> > (VoIP), Ethernet, USB, GPIO, I2C, SPI (Flash), UART, and PCIe.
> > 
> > The EcoNet MIPS SoCs are divided broadly into two families, the
> > EN751221 family based on the 34Kc, and the EN751627 family based on
> > the 1004Kc. Individual SoCs within a family are very similar, only
> > with different peripherals.
> > 
> > This patchset adds basic "boots to a console" support for the EN751221
> > family and adds SmartFiber XP8421-B, a low cost commercially available
> > board that is useful for testing and development.
> > 
> > Note that Airoha (AN7523, AN7581) is similar to EcoNet in terms of
> > peripherals, and for historical reasons Airoha chips are sometimes
> > referred to with the EN75xx prefix. However this is a different
> > platform because Airoha chips are ARM based.
> > 
> > This patchset is against mips-next.
> > 
> > v4 -> v5
> > * 2/7 clocksource/drivers: Add EcoNet Timer HPT driver:
> >   * Improve explanation of HPT timer in changelog
> >   * Move pr_info to pr_debug per recommendation
> >   * Remove pointless debug on spurious interrupt
> >   * Small code-style change
> 
> Shall I pick the clocksource + bindings changes through my tree ?

please do, I'll take the remaining patches.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]


From sean.anderson at linux.dev  Tue May 13 12:23:32 2025
From: sean.anderson at linux.dev (Sean Anderson)
Date: Tue, 13 May 2025 15:23:32 -0400
Subject: [net-next PATCH v4 03/11] net: phylink: introduce internal
 phylink PCS handling
In-Reply-To: <aCOXfw-krDZo9phk@makrotopia.org>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-4-ansuelsmth@gmail.com>
 <5d004048-ef8f-42ad-8f17-d1e4d495f57f@linux.dev>
 <aCOXfw-krDZo9phk@makrotopia.org>
Message-ID: <7b50d202-e7f6-41cb-b868-6e6b33d4a2b9@linux.dev>

On 5/13/25 15:03, Daniel Golle wrote:
> On Tue, May 13, 2025 at 02:18:02PM -0400, Sean Anderson wrote:
>> On 5/11/25 16:12, Christian Marangi wrote:
>> > Introduce internal handling of PCS for phylink. This is an alternative
>> > to .mac_select_pcs that moves the selection logic of the PCS entirely to
>> > phylink with the usage of the supported_interface value in the PCS
>> > struct.
>> > 
>> > MAC should now provide an array of available PCS in phylink_config in
>> > .available_pcs and fill the .num_available_pcs with the number of
>> > elements in the array. MAC should also define a new bitmap,
>> > pcs_interfaces, in phylink_config to define for what interface mode a
>> > dedicated PCS is required.
>> > 
>> > On phylink_create() this array is parsed and a linked list of PCS is
>> > created based on the PCS passed in phylink_config.
>> > Also the supported_interface value in phylink struct is updated with the
>> > new supported_interface from the provided PCS.
>> > 
>> > On phylink_start() every PCS in phylink PCS list gets attached to the
>> > phylink instance. This is done by setting the phylink value in
>> > phylink_pcs struct to the phylink instance.
>> > 
>> > On phylink_stop(), every PCS in phylink PCS list is detached from the
>> > phylink instance. This is done by setting the phylink value in
>> > phylink_pcs struct to NULL.
>> > 
>> > phylink_validate_mac_and_pcs(), phylink_major_config() and
>> > phylink_inband_caps() are updated to support this new implementation
>> > with the PCS list stored in phylink.
>> > 
>> > They will make use of phylink_validate_pcs_interface() that will loop
>> > for every PCS in the phylink PCS available list and find one that supports
>> > the passed interface.
>> > 
>> > phylink_validate_pcs_interface() applies the same logic of .mac_select_pcs
>> > where if a supported_interface value is not set for the PCS struct, then
>> > it's assumed every interface is supported.
>> > 
>> > A MAC is required to implement either a .mac_select_pcs or make use of
>> > the PCS list implementation. Implementing both will result in a fail
>> > on MAC/PCS validation.
>> > 
>> > phylink value in phylink_pcs struct with this implementation is used to
>> > track from PCS side when it's attached to a phylink instance. PCS driver
>> > will make use of this information to correctly detach from a phylink
>> > instance if needed.
>> > 
>> > The .mac_select_pcs implementation is not changed but it's expected that
>> > every MAC driver migrates to the new implementation to later deprecate
>> > and remove .mac_select_pcs.
>> 
>> This introduces a completely parallel PCS selection system used by a
>> single driver. I don't think we want the maintenance burden and
>> complexity of two systems in perpetuity. So what is your plan for
>> conversion of existing drivers to your new system?
> 
> Moving functionality duplicated in many drivers to a common shared
> implementation is nothing unsual.
> 
> While this series proposes the new mechanism for Airoha SoC, they are
> immediately useful (and long awaited) also for MediaTek and Qualcomm
> SoCs.
>
> Also in the series you posted at least the macb driver (in "[net-next
> PATCH v4 09/11] net: macb: Move most of mac_config to  mac_prepare")
> would benefit from that shared implementation, as all it does in it's
> mac_select_pcs is selecting the PCS by a given phy_interface_t, which is
> what most Ethernet drivers which use more than one PCS are doing in
> their implementatio of mac_select_pcs().

I generally agree. The vast majority of select_pcs implementations just
determine the PCS based on the interface. But I don't think this is the
right approach. This touches a lot of other areas of the code and
reimplements much of the existing phylink machinery.

I would prefer something more self-contained like

phylink_generic_select_pcs(phylink, interface)
{
	for_each(pcs : phylink->available_pcss) {
		if (test_bit(pcs->supported, interface))
			return pcs;
	}

	return NULL;
}

which could be dropped into existing implementations in an incremental
manner.

I think the inclusion of PCS lifetime management in this patch
complicates things significantly.

> Also axienet_mac_select_pcs() from "[net-next PATCH v4 08/11] net:
> axienet: Convert to use PCS subsystem" could obviously very easily be
> mirated to use the phylink-internal handling of PCS selection.

But the bulk of the patch remains. We still have to add the external PCS
lookup. There still needs to be another case in mac_config to mux the
PCS correctly. And we would need to add some code to create a list of
PCSs. I don't know whether we win on the balance.

>> 
>> DSA drivers typically have different PCSs for each port. At the moment
>> these are selected with mac_select_pcs, allowing the use of a single
>> phylink_config for each port. If you need to pass PCSs through
>> phylink_config then each port will needs its own config. This may prove
>> difficult to integrate with the existing API.
> 
> This might be a misunderstanding. Also here there is only a single
> phylink_config for each MAC or DSA port,

My point is that while this is the case at the moment, it would not be
the case with a "generic" select pcs. You would need to modify the
config for each port to ensure the right PCSs are passed in.

> just instead of having many
> more or less identical implementations of .mac_select_pcs, this
> functionality is moved into phylink. As a nice side-effect that also
> makes managing the life-cycle of the PCS more easy, so we won't need all
> the wrappers for all the PCS OPs.

I think the wrapper approach is very obviously correct. This way has me
worried about exciting new concurrency bugs.

--Sean


From sean.anderson at linux.dev  Tue May 13 12:42:04 2025
From: sean.anderson at linux.dev (Sean Anderson)
Date: Tue, 13 May 2025 15:42:04 -0400
Subject: [net-next PATCH v4 03/11] net: phylink: introduce internal
 phylink PCS handling
In-Reply-To: <7b50d202-e7f6-41cb-b868-6e6b33d4a2b9@linux.dev>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-4-ansuelsmth@gmail.com>
 <5d004048-ef8f-42ad-8f17-d1e4d495f57f@linux.dev>
 <aCOXfw-krDZo9phk@makrotopia.org>
 <7b50d202-e7f6-41cb-b868-6e6b33d4a2b9@linux.dev>
Message-ID: <7ac6c796-cf4e-47ba-bde3-0f8c6203fea0@linux.dev>

On 5/13/25 15:23, Sean Anderson wrote:
> On 5/13/25 15:03, Daniel Golle wrote:
>> On Tue, May 13, 2025 at 02:18:02PM -0400, Sean Anderson wrote:
>>> DSA drivers typically have different PCSs for each port. At the moment
>>> these are selected with mac_select_pcs, allowing the use of a single
>>> phylink_config for each port. If you need to pass PCSs through
>>> phylink_config then each port will needs its own config. This may prove
>>> difficult to integrate with the existing API.
>> 
>> This might be a misunderstanding. Also here there is only a single
>> phylink_config for each MAC or DSA port,
> 
> My point is that while this is the case at the moment, it would not be
> the case with a "generic" select pcs. You would need to modify the
> config for each port to ensure the right PCSs are passed in.

I reread dsa_port_phylink_create and I think I missed the ds/dp
distinction the first time around.

--Sean



From nfraprado at collabora.com  Tue May 13 13:59:41 2025
From: nfraprado at collabora.com (=?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?=)
Date: Tue, 13 May 2025 16:59:41 -0400
Subject: [PATCH] arm64: defconfig: Enable configs for MediaTek Genio EVK
 boards
Message-ID: <20250513-genio-defconfig-v1-1-c3862f91b6b2@collabora.com>

Enable the missing configs to get all devices on the MediaTek Genio
1200, 700, 510 and 350 EVK boards probing, as indicated by the DT
kselftest.

This includes support for:

Genio 1200/700/510/350:
* MT6359/MT6357 PMICs Auxiliary ADC

Genio 1200/700/510:
* MDP3 (video scaling and color space conversion IP block)
* ITE IT5205 Type-C USB Alternate Mode Passive MUX
* Himax HX8279 controller based KD070FHFID078 DSI panel

Genio 700/510:
* Richtek RT1715 USB Type-C PD Controller

Genio 1200:
* MediaTek PCIe PHY
* Mediatek MT6360 USB Type-C Port Controller

Genio 350:
* STARTEK KD070FHFID015 DSI panel
* MediaTek UART DMA controller (APDMA)

Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
---
Depends on [1].

[1] "[PATCH v4] arm64: defconfig: mediatek: enable PHY drivers"
https://lore.kernel.org/all/20250512131933.1247830-1-vignesh.raman at collabora.com/
---
 arch/arm64/configs/defconfig | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index cb3eacd6406c3a508ce9ee5f4b5c9cd6a429ed3a..cb47d7bea02025d6034093ec3dd2f9f1c6ad4bc8 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -846,6 +846,7 @@ CONFIG_VIDEO_MEDIATEK_JPEG=m
 CONFIG_VIDEO_MEDIATEK_VCODEC=m
 CONFIG_VIDEO_WAVE_VPU=m
 CONFIG_VIDEO_E5010_JPEG_ENC=m
+CONFIG_VIDEO_MEDIATEK_MDP3=m
 CONFIG_VIDEO_IMX7_CSI=m
 CONFIG_VIDEO_IMX_MIPI_CSIS=m
 CONFIG_VIDEO_IMX8_ISI=m
@@ -912,6 +913,7 @@ CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
 CONFIG_DRM_PANEL_LVDS=m
 CONFIG_DRM_PANEL_SIMPLE=m
 CONFIG_DRM_PANEL_EDP=m
+CONFIG_DRM_PANEL_HIMAX_HX8279=m
 CONFIG_DRM_PANEL_ILITEK_ILI9882T=m
 CONFIG_DRM_PANEL_KHADAS_TS050=m
 CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
@@ -919,6 +921,7 @@ CONFIG_DRM_PANEL_NOVATEK_NT36672E=m
 CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
 CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
 CONFIG_DRM_PANEL_SITRONIX_ST7703=m
+CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m
 CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
 CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
 CONFIG_DRM_DISPLAY_CONNECTOR=m
@@ -1152,6 +1155,8 @@ CONFIG_USB_MASS_STORAGE=m
 CONFIG_TYPEC=m
 CONFIG_TYPEC_TCPM=m
 CONFIG_TYPEC_TCPCI=m
+CONFIG_TYPEC_RT1711H=m
+CONFIG_TYPEC_MT6360=m
 CONFIG_TYPEC_TCPCI_MAXIM=m
 CONFIG_TYPEC_FUSB302=m
 CONFIG_TYPEC_QCOM_PMIC=m
@@ -1162,6 +1167,7 @@ CONFIG_TYPEC_TPS6598X=m
 CONFIG_TYPEC_HD3SS3220=m
 CONFIG_TYPEC_MUX_FSA4480=m
 CONFIG_TYPEC_MUX_GPIO_SBU=m
+CONFIG_TYPEC_MUX_IT5205=m
 CONFIG_TYPEC_MUX_NB7VPQ904M=m
 CONFIG_TYPEC_MUX_PS883X=m
 CONFIG_TYPEC_MUX_WCD939X_USBSS=m
@@ -1271,6 +1277,7 @@ CONFIG_PL330_DMA=y
 CONFIG_TEGRA186_GPC_DMA=y
 CONFIG_TEGRA20_APB_DMA=y
 CONFIG_TEGRA210_ADMA=m
+CONFIG_MTK_UART_APDMA=m
 CONFIG_QCOM_BAM_DMA=y
 CONFIG_QCOM_GPI_DMA=m
 CONFIG_QCOM_HIDMA_MGMT=y
@@ -1515,6 +1522,7 @@ CONFIG_EXYNOS_ADC=y
 CONFIG_IMX8QXP_ADC=m
 CONFIG_IMX93_ADC=m
 CONFIG_MAX9611=m
+CONFIG_MEDIATEK_MT6359_AUXADC=m
 CONFIG_MEDIATEK_MT6577_AUXADC=m
 CONFIG_QCOM_SPMI_VADC=m
 CONFIG_QCOM_SPMI_ADC5=m
@@ -1578,6 +1586,7 @@ CONFIG_PHY_HI6220_USB=y
 CONFIG_PHY_HISTB_COMBPHY=y
 CONFIG_PHY_HISI_INNO_USB2=y
 CONFIG_PHY_MVEBU_CP110_COMPHY=y
+CONFIG_PHY_MTK_PCIE=m
 CONFIG_PHY_MTK_TPHY=y
 CONFIG_PHY_MTK_HDMI=m
 CONFIG_PHY_MTK_MIPI_DSI=m

---
base-commit: 0c6d548cd52870702eb4150c420d00e9289a79d2
change-id: 20250513-genio-defconfig-76d65f8643dd

Best regards,
-- 
N?colas F. R. A. Prado <nfraprado at collabora.com>



From daniel at makrotopia.org  Tue May 13 20:00:54 2025
From: daniel at makrotopia.org (Daniel Golle)
Date: Wed, 14 May 2025 04:00:54 +0100
Subject: [net-next PATCH v4 03/11] net: phylink: introduce internal
 phylink PCS handling
In-Reply-To: <7b50d202-e7f6-41cb-b868-6e6b33d4a2b9@linux.dev>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-4-ansuelsmth@gmail.com>
 <5d004048-ef8f-42ad-8f17-d1e4d495f57f@linux.dev>
 <aCOXfw-krDZo9phk@makrotopia.org>
 <7b50d202-e7f6-41cb-b868-6e6b33d4a2b9@linux.dev>
Message-ID: <aCQHZnAstBXbYzgy@makrotopia.org>

On Tue, May 13, 2025 at 03:23:32PM -0400, Sean Anderson wrote:
> On 5/13/25 15:03, Daniel Golle wrote:
> > just instead of having many
> > more or less identical implementations of .mac_select_pcs, this
> > functionality is moved into phylink. As a nice side-effect that also
> > makes managing the life-cycle of the PCS more easy, so we won't need all
> > the wrappers for all the PCS OPs.
> 
> I think the wrapper approach is very obviously correct. This way has me
> worried about exciting new concurrency bugs.

You may not be surprised to read that this was also our starting point 2
months ago, I had implemented support for standalone PCS very similar to
the approach you have published now, using refcnt'ed instances and
locked wrapper functions for all OPs. My approach, like yours, was to
create a new subsystem for standalone PCS drivers which is orthogonal to
phylink and only requires very few very small changes to phylink itself.
It was a draft and not as complete and well-documented like your series
now, of course.

I've then shared that implementation with Christian and some other
experienced OpenWrt developers and we concluded that having phylink handle
the PCS lifecycle and PCS selection would be the better and more elegant
approach for multiple reasons:
 - The lifetime management of the wrapper instances becomes tricky:
   We would either have to live with them being allocated by the
   MAC-driver (imagine test-case doing unbind and then bind in a loop
   for a while -- we would end up oom). Or we need some kind of garbage
   collecting mechanism which frees the wrapper once refcnt is zero --
   and as .select_pcs would 'get' the PCS (ie. bump refcnt) we'd need a
   'put' equivalent (eg. a .pcs_destroy() OP) in phylink.

   Russell repeatedly pointed me to the possibility of a PCS
   "disappearing" (and potentially "reappearing" some time later), and
   in this case it is unclear who would then ever call pcs_put(), or
   even notify the Ethernet driver or phylink about the PCS now being
   available (again). Using device_link_add(), like it is done in
   pcs-rzn1-miic.c, prevents the worst (ie. use-after-free), but also
   impacts all other netdevs exposed by the same Ethernet driver
   instance, and has a few other rather ugly implications.

 - phylink currently expects .mac_select_pcs to never fail. But we may
   need a mechanism similar to probe deferral in case the PCS is not
   yet available.
   Your series partially solves this in patch 11/11 "of: property: Add
   device link support for PCS", but also that still won't make the link
   come back in case of a PCS showing up late to the party, eg. due to
   constraints such as phy drivers (drivers/phy, not drivers/net/phy)
   waiting for nvmem providers, or PCS instances "going away" and
   "coming back" later.

 - removal of a PCS instance (eg. via sysfs unbind) would still
   require changes to phylink. there is no phylink function to
   impair the link in this case, and using dev_close() is a bit ugly,
   and also won't bring the link back up once the PCS (re-)appears.

 - phylink anyway is the only user of PCS drivers, and will very likely
   always be. So why create another subsystem?

All that being said I also see potential problems with Christians
current implementation as it doesn't prevent the Ethernet driver to
still store a pointer to struct phylink_pcs (returned eg. from
fwnode_pcs_get()).

Hence I would like to see an even more tight integration with phylink,
in the sense that pointers to 'struct phylink_pcs' should never be
exposed to the MAC driver, as only in that way we can be sure that
phylink, and only phylink, is responsible for reacting to a PCS "going
away".

Ie. instead of fwnode_phylink_pcs_parse() handing pointers to struct
phylink_pcs to the Ethernet driver, so it can use it to populate struct
phylink_config available_pcs member, this should be the responsibility
of phylink alltogether, directly populating the list of available PCS in
phylink's private structure.

Similarly, there should not be fwnode_pcs_get() but rather phylink
providing a function fwnode_phylink_pcs_register(phylink, fwnode) which
directly adds the PCS referenced to the internal list of available PCS.

I hope we can pick the best of all the suggested implementations, and
together come up with something even better.


From peter.wang at mediatek.com  Tue May 13 22:40:51 2025
From: peter.wang at mediatek.com (=?utf-8?B?UGV0ZXIgV2FuZyAo546L5L+h5Y+LKQ==?=)
Date: Wed, 14 May 2025 05:40:51 +0000
Subject: [PATCH v2] ufs: core: support updating device command timeout
In-Reply-To: <4420fcd0-5125-43b1-89ff-c3e5edad2939@acm.org>
References: <20250510080345.595798-1-peter.wang@mediatek.com>
	 <4420fcd0-5125-43b1-89ff-c3e5edad2939@acm.org>
Message-ID: <8ad2ef53658bd669fc2094b6ba0dea9f896ef740.camel@mediatek.com>

On Tue, 2025-05-13 at 06:42 -0700, Bart Van Assche wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 5/10/25 1:01 AM, peter.wang at mediatek.com?wrote:
> > V2:
> > - Change minimun value to 1ms
> 
> For future patch submissions, please include the changelog below the
> triple dash (---) such that it doesn't appear in the kernel
> changelog.
> 
> Thanks,
> 
> Bart.


Hi Bart

Yes, I also found the commit message section a bit redundant. 
I will remember to put it after the --- next time. 
Thanks for the reminder.

Peter



From krzk at kernel.org  Wed May 14 01:07:08 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Wed, 14 May 2025 10:07:08 +0200
Subject: [PATCH] arm64: defconfig: Enable configs for MediaTek Genio EVK
 boards
In-Reply-To: <20250513-genio-defconfig-v1-1-c3862f91b6b2@collabora.com>
References: <20250513-genio-defconfig-v1-1-c3862f91b6b2@collabora.com>
Message-ID: <ec74ae4e-7fd6-45e6-a5c0-4b98cc97d6e0@kernel.org>

On 13/05/2025 22:59, N?colas F. R. A. Prado wrote:
> Enable the missing configs to get all devices on the MediaTek Genio
> 1200, 700, 510 and 350 EVK boards probing, as indicated by the DT
> kselftest.
> 
> This includes support for:
> 
> Genio 1200/700/510/350:
> * MT6359/MT6357 PMICs Auxiliary ADC
> 
> Genio 1200/700/510:
> * MDP3 (video scaling and color space conversion IP block)
> * ITE IT5205 Type-C USB Alternate Mode Passive MUX
> * Himax HX8279 controller based KD070FHFID078 DSI panel
> 
> Genio 700/510:
> * Richtek RT1715 USB Type-C PD Controller
> 
> Genio 1200:
> * MediaTek PCIe PHY
> * Mediatek MT6360 USB Type-C Port Controller
> 
> Genio 350:
> * STARTEK KD070FHFID015 DSI panel
> * MediaTek UART DMA controller (APDMA)
> 
> Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Best regards,
Krzysztof


From angelogioacchino.delregno at collabora.com  Wed May 14 01:10:29 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 14 May 2025 10:10:29 +0200
Subject: [GIT,PULL,1/2] MediaTek ARM64 DTS updates for v6.16
In-Reply-To: <CAL_JsqKmQxaOUykYfoUCaVe9jg5_fWnoLhxn5j3WmQC1Tm8ZGw@mail.gmail.com>
References: <20250506091736.125733-1-angelogioacchino.delregno@collabora.com>
 <CAL_JsqKmQxaOUykYfoUCaVe9jg5_fWnoLhxn5j3WmQC1Tm8ZGw@mail.gmail.com>
Message-ID: <a5f45658-56fb-40bb-b5ed-c83428adbebd@collabora.com>

Il 13/05/25 20:28, Rob Herring ha scritto:
> On Tue, May 6, 2025 at 6:55?AM AngeloGioacchino Del Regno
> <angelogioacchino.delregno at collabora.com> wrote:
>>
>> The following changes since commit 0af2f6be1b4281385b618cb86ad946eded089ac8:
>>
>>    Linux 6.15-rc1 (2025-04-06 13:11:33 -0700)
>>
>> are available in the Git repository at:
>>
>>    https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux.git tags/mtk-dts64-for-v6.16
>>
>> for you to fetch changes up to 1fe38d2a19950fa6dbc384ee8967c057aef9faf4:
>>
>>    arm64: dts: mt6359: Add missing 'compatible' property to regulators node (2025-05-06 10:35:45 +0200)
>>
>> ----------------------------------------------------------------
>> MediaTek ARM64 DTS updates for v6.16
>>
>> This adds new MT8186-based Google Ponyta Chromebooks and improves
>> support for already supported SoCs and machines.
>>
>> In particular, SoCs changes:
>>   - MT6893
>>     - Added pinmux header for this SoC
>>   - MT8183
>>     - Added port node for dsi_out in mt8183.dtsi to fix some DT
>>       validation warnings.
>>   - MT8188
>>     - Adds an important fix for its Display Controller's Read DMA 0
>>       (RDMA0), as it was using the wrong IOMMU and failing;
>>     - Multimedia Data Path 3 (MDP3) devicetree nodes were added: now
>>       hardware assisted color format conversions are available;
>>     - Since SCP firmwares are available on linux-firmware, the
>>       necessary nodes for the dual-core SCP were added to devicetree
>>       along with the firmware-name property in mt8390-genio-common,
>>       enabling hardware video encoders and decoders on the MediaTek
>>       Genio 510 and Genio 700 EVKs.
>>   - MT8195
>>     - Power domains for video decoders and encoders were reparented
>>       as the secondary vdec/venc core needs the primary core to be
>>       also powered, as those are sharing the LAT hardware and SRAM;
>>     - Missing power domain was added to the primary DisplayPort
>>       Interface (dp_intf0) node.
>>   - MT8196
>>     - Added pinmux header for this SoC
>>
>> ... and machine-specific changes:
>>   - Radxa NIO-12L (MT8395)
>>     - Added support for Audio DSP and sound output through 3.5mm jack;
>>   - MediaTek Genio 1200 EVK (MT8395)
>>     - Support for this EVK's DSI display was added and enabled;
>>     - Secondary display backlight was disabled as it was unused
>>   - MediaTek Genio 510/700 (MT8370/MT8390)
>>     - Added support for the DSI display on these EVKs too;
>>     - Fixed an issue with integrated USB Bluetooth getting unplugged
>>       permanently due to wrong declaration of the ID GPIO polarity of
>>       the secondary USB port on the SSUSB2 controller;
>>
>> Other than that, some other devicetree validation fixes were added
>> on the MT6357 and MT6359 PMIC DTs: for the former, all of the
>> compatible strings in all regulators were dropped as those were
>> wrong and causing DT kselftest failures - and for the latter, the
>> compatible string for the main `regulators` node was added as it
>> was missing.
>>
>> ----------------------------------------------------------------
>> AngeloGioacchino Del Regno (6):
>>        arm64: dts: mediatek: mt8195: Reparent vdec1/2 and venc1 power domains
>>        dt-bindings: display: mediatek: Add compatibles for MT8188 MDP3
>>        dt-bindings: media: mediatek: mdp3: Add compatibles for MT8188 MDP3
>>        arm64: dts: mediatek: mt8188: Add all Multimedia Data Path 3 nodes
> 
> I reported this already with no response, but this commit adds a crap
> load of DT warnings. This is on top of the many existing Mediatek
> warnings. Mediatek has the most warnings on arm64 and is about a fifth
> of the total (182 out of 932 on Linus' tree). If there's a fix for any
> of these, I can't find it. Either fix these warnings or drop the dts
> change.

Sorry, your email slipped through the cracks and didn't see it.

Let me check if I can add a quick fix.

Thanks!
Angelo

> 
> (Note the number is the count for the specific warning in order to
> avoid duplicates (N warnings for N boards)).
> 
>       33 (mediatek,mt8188-mdp3-wrot): '#dma-cells' is a required property
>       33 (mediatek,mt8188-mdp3-tdshp): 'power-domains' does not match
> any of the regexes: '^pinctrl-[0-9]+$'
>       33 (mediatek,mt8188-mdp3-rsz): 'power-domains' does not match any
> of the regexes: '^pinctrl-[0-9]+$'
>       33 (mediatek,mt8188-mdp3-rsz): 'mediatek,gce-events' is a required property
>       33 (mediatek,mt8188-mdp3-rdma): compatible: 'oneOf' conditional
> failed, one must be fixed:
>       33 (mediatek,mt8188-mdp3-hdr): 'power-domains' does not match any
> of the regexes: '^pinctrl-[0-9]+$'
>       33 (mediatek,mt8188-mdp3-fg): 'power-domains' does not match any
> of the regexes: '^pinctrl-[0-9]+$'
>       33 (mediatek,mt8188-mdp3-color): 'oneOf' conditional failed, one
> must be fixed:
>       33 (mediatek,mt8188-mdp3-aal): 'oneOf' conditional failed, one
> must be fixed:
>       11 (mediatek,mt8188-mdp3-tcc): 'power-domains' does not match any
> of the regexes: '^pinctrl-[0-9]+$'
>       11 (mediatek,mt8188-mdp3-ovl): 'oneOf' conditional failed, one
> must be fixed:
>       11 (mediatek,mt8188-mdp3-ovl): 'iommus' is a required property
>        8 (mediatek,mt8188-mdp3-rdma): clocks: [[51, 12], [46, 186],
> [46, 191]] is too long
>        8 (mediatek,mt8188-mdp3-rdma): clocks: [[51, 10], [46, 186],
> [46, 191]] is too long
>        8 (mediatek,mt8188-mdp3-rdma): clocks: [[50, 12], [45, 186],
> [45, 191]] is too long
>        8 (mediatek,mt8188-mdp3-rdma): clocks: [[50, 10], [45, 186],
> [45, 191]] is too long
>        8 (mediatek,mt8188-mdp3-rdma): clocks: [[49, 24], [46, 185],
> [46, 190], [49, 4], [49, 41], [49, 42], [49, 7], [51, 41], [51, 42],
> [49, 8]] is too long
>        8 (mediatek,mt8188-mdp3-rdma): clocks: [[48, 24], [45, 185],
> [45, 190], [48, 4], [48, 41], [48, 42], [48, 7], [50, 41], [50, 42],
> [48, 8]] is too long
>        4 (mediatek,mt8188-mdp3-rsz): clocks: [[51, 24], [51, 25]] is too long
>        4 (mediatek,mt8188-mdp3-rsz): clocks: [[51, 20], [51, 21]] is too long
>        4 (mediatek,mt8188-mdp3-rsz): clocks: [[50, 24], [50, 25]] is too long
>        4 (mediatek,mt8188-mdp3-rsz): clocks: [[50, 20], [50, 21]] is too long
>        4 (mediatek,mt8188-mdp3-rdma): power-domains: [[67, 15], [67,
> 20]] is too long
>        4 (mediatek,mt8188-mdp3-rdma): power-domains: [[66, 15], [66,
> 20]] is too long
>        2 (mediatek,mt8188-mdp3-rdma): mboxes: [[121, 13, 1], [121, 14,
> 1], [121, 16, 1], [121, 21, 1]] is too short
>        2 (mediatek,mt8188-mdp3-rdma): mboxes: [[120, 13, 1], [120, 14,
> 1], [120, 16, 1], [120, 21, 1]] is too short
>        2 (mediatek,mt8188-mdp3-rdma): mboxes: [[119, 13, 1], [119, 14,
> 1], [119, 16, 1], [119, 21, 1]] is too short
>        2 (mediatek,mt8188-mdp3-rdma): mboxes: [[118, 13, 1], [118, 14,
> 1], [118, 16, 1], [118, 21, 1]] is too short
>        2 (mediatek,mt8188-mdp3-rdma): iommus: [[132, 164], [132, 166]]
> is too long
>        2 (mediatek,mt8188-mdp3-rdma): iommus: [[131, 164], [131, 166]]
> is too long
>        2 (mediatek,mt8188-mdp3-rdma): iommus: [[130, 164], [130, 166]]
> is too long
>        2 (mediatek,mt8188-mdp3-rdma): iommus: [[129, 164], [129, 166]]
> is too long
>        2 (mediatek,mt8188-mdp3-rdma): iommus: [[122, 192], [122, 194]]
> is too long
>        2 (mediatek,mt8188-mdp3-rdma): iommus: [[122, 128], [122, 131]]
> is too long
>        2 (mediatek,mt8188-mdp3-rdma): iommus: [[121, 192], [121, 194]]
> is too long
>        2 (mediatek,mt8188-mdp3-rdma): iommus: [[121, 128], [121, 131]]
> is too long
>        2 (mediatek,mt8188-mdp3-rdma): iommus: [[120, 192], [120, 194]]
> is too long
>        2 (mediatek,mt8188-mdp3-rdma): iommus: [[120, 128], [120, 131]]
> is too long
>        2 (mediatek,mt8188-mdp3-rdma): iommus: [[119, 192], [119, 194]]
> is too long
>        2 (mediatek,mt8188-mdp3-rdma): iommus: [[119, 128], [119, 131]]
> is too long
>        2 (mediatek,mt8188-mdp3-rdma): clocks: [[44, 12], [39, 186],
> [39, 191]] is too long
>        2 (mediatek,mt8188-mdp3-rdma): clocks: [[44, 10], [39, 186],
> [39, 191]] is too long
>        2 (mediatek,mt8188-mdp3-rdma): clocks: [[42, 24], [39, 185],
> [39, 190], [42, 4], [42, 41], [42, 42], [42, 7], [44, 41], [44, 42],
> [42, 8]] is too long
>        2 (mediatek,mt8188-mdp3-rdma): clocks: [[42, 12], [37, 186],
> [37, 191]] is too long
>        2 (mediatek,mt8188-mdp3-rdma): clocks: [[42, 10], [37, 186],
> [37, 191]] is too long
>        2 (mediatek,mt8188-mdp3-rdma): clocks: [[40, 24], [37, 185],
> [37, 190], [40, 4], [40, 41], [40, 42], [40, 7], [42, 41], [42, 42],
> [40, 8]] is too long
>        2 (mediatek,mt8188-mdp3-rdma): clocks: [[38, 12], [34, 186],
> [34, 191]] is too long
>        2 (mediatek,mt8188-mdp3-rdma): clocks: [[38, 10], [34, 186],
> [34, 191]] is too long
>        2 (mediatek,mt8188-mdp3-rdma): clocks: [[36, 24], [34, 185],
> [34, 190], [36, 4], [36, 41], [36, 42], [36, 7], [38, 41], [38, 42],
> [36, 8]] is too long
>        1 (mediatek,mt8188-mdp3-rsz): clocks: [[44, 24], [44, 25]] is too long
>        1 (mediatek,mt8188-mdp3-rsz): clocks: [[44, 20], [44, 21]] is too long
>        1 (mediatek,mt8188-mdp3-rsz): clocks: [[42, 24], [42, 25]] is too long
>        1 (mediatek,mt8188-mdp3-rsz): clocks: [[42, 20], [42, 21]] is too long
>        1 (mediatek,mt8188-mdp3-rsz): clocks: [[38, 24], [38, 25]] is too long
>        1 (mediatek,mt8188-mdp3-rsz): clocks: [[38, 20], [38, 21]] is too long
>        1 (mediatek,mt8188-mdp3-rdma): power-domains: [[60, 15], [60,
> 20]] is too long
>        1 (mediatek,mt8188-mdp3-rdma): power-domains: [[58, 15], [58,
> 20]] is too long
>        1 (mediatek,mt8188-mdp3-rdma): power-domains: [[54, 15], [54,
> 20]] is too long
>        1 (mediatek,mt8188-mdp3-rdma): mboxes: [[92, 13, 1], [92, 14,
> 1], [92, 16, 1], [92, 21, 1]] is too short
>        1 (mediatek,mt8188-mdp3-rdma): mboxes: [[131, 13, 1], [131, 14,
> 1], [131, 16, 1], [131, 21, 1]] is too short
>        1 (mediatek,mt8188-mdp3-rdma): mboxes: [[129, 13, 1], [129, 14,
> 1], [129, 16, 1], [129, 21, 1]] is too short
>        1 (mediatek,mt8188-mdp3-rdma): iommus: [[93, 192], [93, 194]] is too long
>        1 (mediatek,mt8188-mdp3-rdma): iommus: [[93, 128], [93, 131]] is too long
>        1 (mediatek,mt8188-mdp3-rdma): iommus: [[142, 164], [142, 166]]
> is too long
>        1 (mediatek,mt8188-mdp3-rdma): iommus: [[140, 164], [140, 166]]
> is too long
>        1 (mediatek,mt8188-mdp3-rdma): iommus: [[132, 192], [132, 194]]
> is too long
>        1 (mediatek,mt8188-mdp3-rdma): iommus: [[132, 128], [132, 131]]
> is too long
>        1 (mediatek,mt8188-mdp3-rdma): iommus: [[130, 192], [130, 194]]
> is too long
>        1 (mediatek,mt8188-mdp3-rdma): iommus: [[130, 128], [130, 131]]
> is too long
>        1 (mediatek,mt8188-mdp3-rdma): iommus: [[103, 164], [103, 166]]
> is too long
> 
> 
>>        arm64: dts: mediatek: Add MT6893 pinmux macro header file
>>        arm64: dts: mediatek: mt8390-genio-common: Add Display on DSI0
>>
>> Axe Yang (1):
>>        arm64: dts: mediatek: mt8186-corsola: make SDIO card removable
>>
>> Cathy Xu (1):
>>        arm64: dts: mediatek: mt8196: Add pinmux macro header file
>>
>> Chen-Yu Tsai (1):
>>        arm64: dts: mediatek: mt8188: Fix IOMMU device for rdma0
>>
>> Jianeng Ceng (2):
>>        dt-bindings: arm: mediatek: Add MT8186 Ponyta Chromebook
>>        arm64: dts: mediatek: Add MT8186 Ponyta Chromebooks
>>
>> Julien Massot (4):
>>        arm64: dts: mediatek: mt8395-nio-12l: Add scp firmware-name
>>        arm64: dts: mediatek: mt8395-genio-1200-evk: Add scp firmware-name
>>        arm64: dts: mediatek: mt8395-nio-12l: Enable Audio DSP and sound card
>>        arm64: dts: mt6359: Add missing 'compatible' property to regulators node
>>
>> Louis-Alexis Eyraud (3):
>>        arm64: dts: mediatek: mt8390-genio-common: Fix pcie pinctrl dtbs_check error
>>        arm64: dts: mediatek: mt8395-genio-1200-evk: Add display on DSI0
>>        arm64: dts: mediatek: mt8390-genio-common: Set ssusb2 default dual role mode to host
>>
>> Macpaul Lin (1):
>>        arm64: dts: mediatek: mt8195: Add power domain for dp_intf0
>>
>> N?colas F. R. A. Prado (4):
>>        arm64: dts: mediatek: mt8188: Describe SCP as a cluster with two cores
>>        arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0
>>        arm64: dts: mediatek: mt6357: Drop regulator-fixed compatibles
>>        arm64: dts: mediatek: mt8395-genio-1200-evk: Disable unused backlight
>>
>> Pin-yen Lin (1):
>>        arm64: dts: mt8183: Add port node to mt8183.dtsi
>>
>> Rob Herring (Arm) (1):
>>        arm/arm64: dts: mediatek: Add missing "#sound-dai-cells" to linux,bt-sco
>>
>> ?ukasz Majczak (1):
>>        arm64: dts: mediatek: mt8186: starmie: Fix external display
>>
>>   Documentation/devicetree/bindings/arm/mediatek.yaml                      |    7 +
>>   Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml     |    4 +
>>   Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml   |    4 +
>>   Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml   |    4 +
>>   Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml |   10 +-
>>   Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml            |    8 +-
>>   Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml           |    8 +-
>>   Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml           |    1 +
>>   Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml        |    8 +-
>>   Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml           |    8 +-
>>   Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml         |    8 +-
>>   Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml          |    1 +
>>   arch/arm/boot/dts/mediatek/mt2701-evb.dts                                |    1 +
>>   arch/arm64/boot/dts/mediatek/Makefile                                    |    2 +
>>   arch/arm64/boot/dts/mediatek/mt6357.dtsi                                 |   10 -
>>   arch/arm64/boot/dts/mediatek/mt6359.dtsi                                 |    2 +
>>   arch/arm64/boot/dts/mediatek/mt6893-pinfunc.h                            | 1356 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>>   arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi                           |   11 +-
>>   arch/arm64/boot/dts/mediatek/mt8183.dtsi                                 |    4 +
>>   arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku0.dts              |   18 +
>>   arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku1.dts              |   22 +
>>   arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta.dtsi                  |   49 ++
>>   arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie.dtsi                 |   45 --
>>   arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi                         |    1 -
>>   arch/arm64/boot/dts/mediatek/mt8188-evb.dts                              |    6 +-
>>   arch/arm64/boot/dts/mediatek/mt8188.dtsi                                 |  349 ++++++++++++++-
>>   arch/arm64/boot/dts/mediatek/mt8195.dtsi                                 |   51 ++-
>>   arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h                            | 1574 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>>   arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi                    |  170 ++++++-
>>   arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts                   |  127 +++++-
>>   arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts                    |   59 ++-
>>   31 files changed, 3797 insertions(+), 131 deletions(-)
>>   create mode 100644 arch/arm64/boot/dts/mediatek/mt6893-pinfunc.h
>>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku0.dts
>>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta-sku1.dts
>>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-ponyta.dtsi
>>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h
>>
>>


From julien.massot at collabora.com  Wed May 14 01:11:17 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Wed, 14 May 2025 10:11:17 +0200
Subject: [PATCH 1/4] dt-bindings: mfd: mediatek: mt6397: Add
 #sound-dai-cells property
In-Reply-To: <79148223-d87f-486e-9d51-979f9188a837@kernel.org>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
	 <20250505-mt8395-dtb-errors-v1-1-9c4714dcdcdb@collabora.com>
	 <79148223-d87f-486e-9d51-979f9188a837@kernel.org>
Message-ID: <5578490565f6d37fa435ca0c02fcfc2cb685baf8.camel@collabora.com>

Hi Krzysztof,

On Thu, 2025-05-08 at 08:01 +0200, Krzysztof Kozlowski wrote:
> On 05/05/2025 15:23, Julien Massot wrote:
> > The 'mt6359.dtsi' file already uses the '#sound-dai-cells' property.
> > Add the corresponding property to the binding to fix the following
> > dtb-check error:
> If this is a DAI, then you miss dai-common reference. If not, you need
> to explain it in commit msg.

Thanks for the review, I will add the missing dai-common reference in the v2.

Regards,
Julien


From darren.ye at mediatek.com  Wed May 14 01:11:02 2025
From: darren.ye at mediatek.com (Darren.Ye)
Date: Wed, 14 May 2025 16:11:02 +0800
Subject: [PATCH v3 00/10] ASoC: mediatek: Add support for MT8196 SoC
Message-ID: <20250514081125.24475-1-darren.ye@mediatek.com>

From: Darren Ye <darren.ye at mediatek.com>

This series of patches adds support for Mediatek AFE of MT8196 SoC.
Patches are based on broonie tree "for-next" branch.

Changes since v2:
? - remove the mtk_memif_set_channel interface modify.
? - remove duplicate definitions from the header file.
? - move the afe gate clk to the audio driver for management and registration
?   and manage the afe clk gate in each dai driver.
? - delete the useless clk source.
? - the i2s driver adds i2s clk gate management, removes the additional dts
?   configuration of i2s4.
? - the afe and i2s dai driver,memif and irq data structs are encapsulated using
?   macros to reduce the amount of code.
? - the volatile reg is modified as suggested.
? - mt6681 codec is not supported, the mt6681 keyword is removed.
? - the name of the machine driver is changed from mt8196-mt6681.c to mt8196-nau8825.c
? - remove the i2s4 configuration from mt8196-afe.yaml and make the modifications as suggested.
? - change the mt8196-mt6681.yaml to mt8196-nau8825.yaml and make the modifications as suggested.

Changes since v1:
? - modify mtk_memif_set_channel and mtk_afe_pcm_pointer interfaces
?   are improved to support mt8196.
? - remove duplicate definitions in the mt8196 common header file.
? - cm logic is merge into the afe platform driver.
? - modify afe clk to return judgment logic and remove useless clk sources.
? - refactor the mt8196 adda dai driver.
? - remove the gpio module and use SND_SOC_DAPM_PINCTRL to manage it.
? - removes CONNSYS_I2S related functions that are not supported in i2s dai driver.
? - fixed mt8196-afe.yaml and mt8196-mt6681.yaml syntax issues.
? - modify log printing in all modules.
? - optimize the header file included for machine driver.

Darren Ye (10):
  ASoC: mediatek: common: modify mtk afe platform driver for mt8196
  ASoC: mediatek: mt8196: add common header
  ASoC: mediatek: mt8196: support audio clock control
  ASoC: mediatek: mt8196: support ADDA in platform driver
  ASoC: mediatek: mt8196: support I2S in platform driver
  ASoC: mediatek: mt8196: support TDM in platform driver
  ASoC: mediatek: mt8196: add platform driver
  ASoC: dt-bindings: mediatek,mt8196-afe: add audio AFE document
  ASoC: mediatek: mt8196: add machine driver with nau8825
  ASoC: dt-bindings: mediatek,mt8196-nau8825: add mt8196-nau8825
    document

 .../bindings/sound/mediatek,mt8196-afe.yaml   |   155 +
 .../sound/mediatek,mt8196-nau8825.yaml        |   115 +
 sound/soc/mediatek/Kconfig                    |    30 +
 sound/soc/mediatek/Makefile                   |     1 +
 .../mediatek/common/mtk-afe-platform-driver.c |    47 +-
 .../mediatek/common/mtk-afe-platform-driver.h |     2 +
 sound/soc/mediatek/mt8196/Makefile            |    18 +
 sound/soc/mediatek/mt8196/mt8196-afe-clk.c    |   723 +
 sound/soc/mediatek/mt8196/mt8196-afe-clk.h    |   142 +
 sound/soc/mediatek/mt8196/mt8196-afe-common.h |   206 +
 sound/soc/mediatek/mt8196/mt8196-afe-pcm.c    |  2642 ++++
 sound/soc/mediatek/mt8196/mt8196-audsys-clk.c |   252 +
 sound/soc/mediatek/mt8196/mt8196-audsys-clk.h |    14 +
 .../soc/mediatek/mt8196/mt8196-audsys-clkid.h |    78 +
 sound/soc/mediatek/mt8196/mt8196-dai-adda.c   |   918 ++
 sound/soc/mediatek/mt8196/mt8196-dai-i2s.c    |  4052 ++++++
 sound/soc/mediatek/mt8196/mt8196-dai-tdm.c    |   862 ++
 .../mediatek/mt8196/mt8196-interconnection.h  |   121 +
 sound/soc/mediatek/mt8196/mt8196-nau8825.c    |   869 ++
 sound/soc/mediatek/mt8196/mt8196-reg.h        | 12068 ++++++++++++++++
 20 files changed, 23299 insertions(+), 16 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml
 create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt8196-nau8825.yaml
 create mode 100644 sound/soc/mediatek/mt8196/Makefile
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-clk.c
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-clk.h
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-common.h
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-pcm.c
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-audsys-clk.c
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-audsys-clk.h
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-audsys-clkid.h
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-dai-adda.c
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-dai-i2s.c
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-dai-tdm.c
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-interconnection.h
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-nau8825.c
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-reg.h

-- 
2.45.2



From darren.ye at mediatek.com  Wed May 14 01:11:03 2025
From: darren.ye at mediatek.com (Darren.Ye)
Date: Wed, 14 May 2025 16:11:03 +0800
Subject: [PATCH v3 01/10] ASoC: mediatek: common: modify mtk afe platform driver for mt8196
In-Reply-To: <20250514081125.24475-1-darren.ye@mediatek.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
Message-ID: <20250514081125.24475-2-darren.ye@mediatek.com>

From: Darren Ye <darren.ye at mediatek.com>

Mofify the pcm pointer interface to support 64-bit address access.

Signed-off-by: Darren Ye <darren.ye at mediatek.com>
---
 .../mediatek/common/mtk-afe-platform-driver.c | 47 ++++++++++++-------
 .../mediatek/common/mtk-afe-platform-driver.h |  2 +
 2 files changed, 33 insertions(+), 16 deletions(-)

diff --git a/sound/soc/mediatek/common/mtk-afe-platform-driver.c b/sound/soc/mediatek/common/mtk-afe-platform-driver.c
index 6b6330583941..a86594dca2b7 100644
--- a/sound/soc/mediatek/common/mtk-afe-platform-driver.c
+++ b/sound/soc/mediatek/common/mtk-afe-platform-driver.c
@@ -86,29 +86,44 @@ snd_pcm_uframes_t mtk_afe_pcm_pointer(struct snd_soc_component *component,
 	const struct mtk_base_memif_data *memif_data = memif->data;
 	struct regmap *regmap = afe->regmap;
 	struct device *dev = afe->dev;
-	int reg_ofs_base = memif_data->reg_ofs_base;
-	int reg_ofs_cur = memif_data->reg_ofs_cur;
-	unsigned int hw_ptr = 0, hw_base = 0;
-	int ret, pcm_ptr_bytes;
-
-	ret = regmap_read(regmap, reg_ofs_cur, &hw_ptr);
-	if (ret || hw_ptr == 0) {
-		dev_err(dev, "%s hw_ptr err\n", __func__);
-		pcm_ptr_bytes = 0;
+	unsigned int hw_ptr_lower32 = 0, hw_ptr_upper32 = 0;
+	unsigned int hw_base_lower32 = 0, hw_base_upper32 = 0;
+	unsigned long long hw_ptr = 0, hw_base = 0;
+	int ret;
+	unsigned long long pcm_ptr_bytes = 0;
+
+	ret = regmap_read(regmap, memif_data->reg_ofs_cur, &hw_ptr_lower32);
+	if (ret || hw_ptr_lower32 == 0) {
+		dev_err(dev, "%s hw_ptr_lower32 err\n", __func__);
 		goto POINTER_RETURN_FRAMES;
 	}
 
-	ret = regmap_read(regmap, reg_ofs_base, &hw_base);
-	if (ret || hw_base == 0) {
-		dev_err(dev, "%s hw_ptr err\n", __func__);
-		pcm_ptr_bytes = 0;
-		goto POINTER_RETURN_FRAMES;
+	if (memif_data->reg_ofs_cur_msb) {
+		ret = regmap_read(regmap, memif_data->reg_ofs_cur_msb, &hw_ptr_upper32);
+		if (ret) {
+			dev_err(dev, "%s hw_ptr_upper32 err\n", __func__);
+			goto POINTER_RETURN_FRAMES;
+		}
 	}
 
-	pcm_ptr_bytes = hw_ptr - hw_base;
+	ret = regmap_read(regmap, memif_data->reg_ofs_base, &hw_base_lower32);
+	if (ret || hw_base_lower32 == 0) {
+		dev_err(dev, "%s hw_base_lower32 err\n", __func__);
+		goto POINTER_RETURN_FRAMES;
+	}
+	if (memif_data->reg_ofs_base_msb) {
+		ret = regmap_read(regmap, memif_data->reg_ofs_base_msb, &hw_base_upper32);
+		if (ret) {
+			dev_err(dev, "%s hw_base_upper32 err\n", __func__);
+			goto POINTER_RETURN_FRAMES;
+		}
+	}
+	hw_ptr = ((unsigned long long)hw_ptr_upper32 << 32) + hw_ptr_lower32;
+	hw_base = ((unsigned long long)hw_base_upper32 << 32) + hw_base_lower32;
 
 POINTER_RETURN_FRAMES:
-	return bytes_to_frames(substream->runtime, pcm_ptr_bytes);
+	pcm_ptr_bytes = MTK_WORD_SIZE_ALIGN(hw_ptr - hw_base);
+	return bytes_to_frames(substream->runtime, (ssize_t)pcm_ptr_bytes);
 }
 EXPORT_SYMBOL_GPL(mtk_afe_pcm_pointer);
 
diff --git a/sound/soc/mediatek/common/mtk-afe-platform-driver.h b/sound/soc/mediatek/common/mtk-afe-platform-driver.h
index fcc923b88f12..9809e60db511 100644
--- a/sound/soc/mediatek/common/mtk-afe-platform-driver.h
+++ b/sound/soc/mediatek/common/mtk-afe-platform-driver.h
@@ -12,6 +12,8 @@
 #define AFE_PCM_NAME "mtk-afe-pcm"
 extern const struct snd_soc_component_driver mtk_afe_pcm_platform;
 
+#define MTK_WORD_SIZE_ALIGN(x) ((x) & (0xfffffffff0))
+
 struct mtk_base_afe;
 struct snd_pcm;
 struct snd_soc_component;
-- 
2.45.2



From darren.ye at mediatek.com  Wed May 14 01:11:05 2025
From: darren.ye at mediatek.com (Darren.Ye)
Date: Wed, 14 May 2025 16:11:05 +0800
Subject: [PATCH v3 03/10] ASoC: mediatek: mt8196: support audio clock control
In-Reply-To: <20250514081125.24475-1-darren.ye@mediatek.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
Message-ID: <20250514081125.24475-4-darren.ye@mediatek.com>

From: Darren Ye <darren.ye at mediatek.com>

Add audio clock wrapper and audio tuner control.

Signed-off-by: Darren Ye <darren.ye at mediatek.com>
---
 sound/soc/mediatek/mt8196/mt8196-afe-clk.c    | 723 ++++++++++++++++++
 sound/soc/mediatek/mt8196/mt8196-afe-clk.h    | 142 ++++
 sound/soc/mediatek/mt8196/mt8196-audsys-clk.c | 252 ++++++
 sound/soc/mediatek/mt8196/mt8196-audsys-clk.h |  14 +
 .../soc/mediatek/mt8196/mt8196-audsys-clkid.h |  78 ++
 5 files changed, 1209 insertions(+)
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-clk.c
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-clk.h
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-audsys-clk.c
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-audsys-clk.h
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-audsys-clkid.h

diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-clk.c b/sound/soc/mediatek/mt8196/mt8196-afe-clk.c
new file mode 100644
index 000000000000..83b5ee9d30ef
--- /dev/null
+++ b/sound/soc/mediatek/mt8196/mt8196-afe-clk.c
@@ -0,0 +1,723 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *  mt8196-afe-clk.c  --  Mediatek 8196 afe clock ctrl
+ *
+ *  Copyright (c) 2024 MediaTek Inc.
+ *  Author: Darren Ye <darren.ye at mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include "mt8196-afe-common.h"
+#include "mt8196-audsys-clk.h"
+#include "mt8196-afe-clk.h"
+
+static const char *aud_clks[MT8196_CLK_NUM] = {
+	/* vlp clk */
+	[MT8196_CLK_VLP_MUX_AUDIOINTBUS] = "top_aud_intbus",
+	[MT8196_CLK_VLP_MUX_AUD_ENG1] = "top_aud_eng1",
+	[MT8196_CLK_VLP_MUX_AUD_ENG2] = "top_aud_eng2",
+	[MT8196_CLK_VLP_MUX_AUDIO_H] = "top_aud_h",
+	[MT8196_CLK_VLP_CLK26M] = "vlp_clk26m",
+	/* pll */
+	[MT8196_CLK_TOP_APLL1_CK] = "apll1",
+	[MT8196_CLK_TOP_APLL2_CK] = "apll2",
+	/* divider */
+	[MT8196_CLK_TOP_APLL1_D4] = "apll1_d4",
+	[MT8196_CLK_TOP_APLL2_D4] = "apll2_d4",
+	[MT8196_CLK_TOP_APLL12_DIV_I2SIN0] = "apll12_div_i2sin0",
+	[MT8196_CLK_TOP_APLL12_DIV_I2SIN1] = "apll12_div_i2sin1",
+	[MT8196_CLK_TOP_APLL12_DIV_FMI2S] = "apll12_div_fmi2s",
+	[MT8196_CLK_TOP_APLL12_DIV_TDMOUT_M] = "apll12_div_tdmout_m",
+	[MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B] = "apll12_div_tdmout_b",
+	/* mux */
+	[MT8196_CLK_TOP_MUX_AUD_1] = "top_apll1",
+	[MT8196_CLK_TOP_MUX_AUD_2] = "top_apll2",
+	[MT8196_CLK_TOP_I2SIN0_M_SEL] = "top_i2sin0",
+	[MT8196_CLK_TOP_I2SIN1_M_SEL] = "top_i2sin1",
+	[MT8196_CLK_TOP_FMI2S_M_SEL] = "top_fmi2s",
+	[MT8196_CLK_TOP_TDMOUT_M_SEL] = "top_dptx",
+	[MT8196_CLK_TOP_ADSP_SEL] = "top_adsp",
+	/* top 26m*/
+	[MT8196_CLK_TOP_CLK26M] = "clk26m",
+	/* clock gate */
+	[MT8196_CLK_AFE_AUDIO_HOPPING] = "afe_audio_hopping_ck",
+	[MT8196_CLK_AFE_AUDIO_F26M] = "afe_audio_f26m_ck",
+	[MT8196_CLK_AFE_APLL1] = "afe_apll1_ck",
+	[MT8196_CLK_AFE_APLL2] = "afe_apll2_ck",
+	[MT8196_CLK_AFE_APLL_TUNER1] = "afe_apll_tuner1",
+	[MT8196_CLK_AFE_APLL_TUNER2] = "afe_apll_tuner2",
+	[MT8196_CLK_AFE_ETDM_OUT4] = "afe_etdm_out4",
+	[MT8196_CLK_AFE_ETDM_IN6] = "afe_etdm_in6",
+	[MT8196_CLK_AFE_ETDM_OUT6] = "afe_etdm_out6",
+	[MT8196_CLK_AFE_TDM_OUT] = "afe_tdm_out",
+	[MT8196_CLK_AFE_CM0] = "afe_cm0",
+	[MT8196_CLK_AFE_CM1] = "afe_cm1",
+	[MT8196_CLK_AFE_CM2] = "afe_cm2",
+};
+
+int mt8196_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
+{
+	int ret;
+
+	if (clk) {
+		ret = clk_prepare_enable(clk);
+		if (ret) {
+			dev_dbg(afe->dev, "failed to enable clk\n");
+			return ret;
+		}
+	} else {
+		dev_dbg(afe->dev, "NULL clk\n");
+	}
+	return 0;
+}
+EXPORT_SYMBOL_GPL(mt8196_afe_enable_clk);
+
+void mt8196_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
+{
+	if (clk)
+		clk_disable_unprepare(clk);
+	else
+		dev_dbg(afe->dev, "NULL clk\n");
+}
+EXPORT_SYMBOL_GPL(mt8196_afe_disable_clk);
+
+static int mt8196_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
+				   unsigned int rate)
+{
+	int ret;
+
+	if (clk) {
+		ret = clk_set_rate(clk, rate);
+		if (ret) {
+			dev_dbg(afe->dev, "failed to set clk rate\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int mt8196_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
+				     struct clk *parent)
+{
+	int ret;
+
+	if (clk && parent) {
+		ret = clk_set_parent(clk, parent);
+		if (ret) {
+			dev_dbg(afe->dev, "failed to set clk parent %d\n", ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static unsigned int get_top_cg_reg(unsigned int cg_type)
+{
+	switch (cg_type) {
+	case MT8196_AUDIO_26M_EN_ON:
+	case MT8196_AUDIO_F3P25M_EN_ON:
+	case MT8196_AUDIO_APLL1_EN_ON:
+	case MT8196_AUDIO_APLL2_EN_ON:
+		return AUDIO_ENGEN_CON0;
+	default:
+		return 0;
+	}
+}
+
+static unsigned int get_top_cg_mask(unsigned int cg_type)
+{
+	switch (cg_type) {
+	case MT8196_AUDIO_26M_EN_ON:
+		return AUDIO_26M_EN_ON_MASK_SFT;
+	case MT8196_AUDIO_F3P25M_EN_ON:
+		return AUDIO_F3P25M_EN_ON_MASK_SFT;
+	case MT8196_AUDIO_APLL1_EN_ON:
+		return AUDIO_APLL1_EN_ON_MASK_SFT;
+	case MT8196_AUDIO_APLL2_EN_ON:
+		return AUDIO_APLL2_EN_ON_MASK_SFT;
+	default:
+		return 0;
+	}
+}
+
+static unsigned int get_top_cg_on_val(unsigned int cg_type)
+{
+	switch (cg_type) {
+	case MT8196_AUDIO_26M_EN_ON:
+	case MT8196_AUDIO_F3P25M_EN_ON:
+	case MT8196_AUDIO_APLL1_EN_ON:
+	case MT8196_AUDIO_APLL2_EN_ON:
+		return get_top_cg_mask(cg_type);
+	default:
+		return 0;
+	}
+}
+
+static unsigned int get_top_cg_off_val(unsigned int cg_type)
+{
+	switch (cg_type) {
+	case MT8196_AUDIO_26M_EN_ON:
+	case MT8196_AUDIO_F3P25M_EN_ON:
+	case MT8196_AUDIO_APLL1_EN_ON:
+	case MT8196_AUDIO_APLL2_EN_ON:
+		return 0;
+	default:
+		return get_top_cg_mask(cg_type);
+	}
+}
+
+static int mt8196_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
+{
+	unsigned int reg = get_top_cg_reg(cg_type);
+	unsigned int mask = get_top_cg_mask(cg_type);
+	unsigned int val = get_top_cg_on_val(cg_type);
+
+	regmap_update_bits(afe->regmap, reg, mask, val);
+	return 0;
+}
+
+static int mt8196_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
+{
+	unsigned int reg = get_top_cg_reg(cg_type);
+	unsigned int mask = get_top_cg_mask(cg_type);
+	unsigned int val = get_top_cg_off_val(cg_type);
+
+	regmap_update_bits(afe->regmap, reg, mask, val);
+	return 0;
+}
+
+static int mt8196_afe_enable_afe_on(struct mtk_base_afe *afe)
+{
+	mt8196_afe_enable_top_cg(afe, MT8196_AUDIO_26M_EN_ON);
+	return 0;
+}
+
+static int mt8196_afe_disable_afe_on(struct mtk_base_afe *afe)
+{
+	mt8196_afe_disable_top_cg(afe, MT8196_AUDIO_26M_EN_ON);
+	return 0;
+}
+
+static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int ret = 0;
+
+	dev_dbg(afe->dev, "enable: %d\n", enable);
+
+	if (enable) {
+		ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1]);
+		if (ret)
+			return ret;
+
+		ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1],
+						afe_priv->clk[MT8196_CLK_TOP_APLL1_CK]);
+		if (ret)
+			return ret;
+
+		/* 180.6336 / 4 = 45.1584MHz */
+		ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG1]);
+		if (ret)
+			return ret;
+
+		ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG1],
+						afe_priv->clk[MT8196_CLK_TOP_APLL1_D4]);
+		if (ret)
+			return ret;
+
+		ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
+		if (ret)
+			return ret;
+
+		ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
+						afe_priv->clk[MT8196_CLK_TOP_APLL1_CK]);
+		if (ret)
+			return ret;
+	} else {
+		ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG1],
+						afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
+		if (ret)
+			return ret;
+
+		mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG1]);
+
+		ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1],
+						afe_priv->clk[MT8196_CLK_TOP_CLK26M]);
+		if (ret)
+			return ret;
+
+		mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1]);
+		mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
+					  afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
+		mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
+	}
+
+	return 0;
+}
+
+static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int ret = 0;
+
+	dev_dbg(afe->dev, "enable: %d\n", enable);
+
+	if (enable) {
+		ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2]);
+		if (ret)
+			return ret;
+
+		ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2],
+						afe_priv->clk[MT8196_CLK_TOP_APLL2_CK]);
+		if (ret)
+			return ret;
+
+		/* 196.608 / 4 = 49.152MHz */
+		ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG2]);
+		if (ret)
+			return ret;
+
+		ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG2],
+						afe_priv->clk[MT8196_CLK_TOP_APLL2_D4]);
+		if (ret)
+			return ret;
+
+		ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
+		if (ret)
+			return ret;
+
+		ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
+						afe_priv->clk[MT8196_CLK_TOP_APLL2_CK]);
+		if (ret)
+			return ret;
+	} else {
+		ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG2],
+						afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
+		if (ret)
+			return ret;
+
+		mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG2]);
+
+		ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2],
+						afe_priv->clk[MT8196_CLK_TOP_CLK26M]);
+		if (ret)
+			return ret;
+
+		mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2]);
+		mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
+					  afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
+		mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
+	}
+
+	return 0;
+}
+
+static int mt8196_afe_disable_apll(struct mtk_base_afe *afe)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int ret = 0;
+
+	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
+	if (ret)
+		return ret;
+
+	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1]);
+	if (ret)
+		goto clk_ck_mux_aud1_err;
+
+	ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1],
+					afe_priv->clk[MT8196_CLK_TOP_CLK26M]);
+	if (ret)
+		goto clk_ck_mux_aud1_parent_err;
+
+	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2]);
+	if (ret)
+		goto clk_ck_mux_aud2_err;
+
+	ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2],
+					afe_priv->clk[MT8196_CLK_TOP_CLK26M]);
+	if (ret)
+		goto clk_ck_mux_aud2_parent_err;
+
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1]);
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2]);
+	mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
+				  afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
+	return 0;
+
+clk_ck_mux_aud2_parent_err:
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2]);
+clk_ck_mux_aud2_err:
+	mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1],
+				  afe_priv->clk[MT8196_CLK_TOP_APLL1_CK]);
+clk_ck_mux_aud1_parent_err:
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1]);
+clk_ck_mux_aud1_err:
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
+
+	return ret;
+}
+
+static void mt8196_afe_apll_init(struct mtk_base_afe *afe)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+
+	if (afe_priv->vlp_ck) {
+		regmap_write(afe_priv->vlp_ck, VLP_APLL1_TUNER_CON0, VLP_APLL1_TUNER_CON0_VALUE);
+		regmap_write(afe_priv->vlp_ck, VLP_APLL2_TUNER_CON0, VLP_APLL2_TUNER_CON0_VALUE);
+	} else {
+		dev_warn(afe->dev, "vlp_ck regmap is null ptr\n");
+	}
+}
+
+int mt8196_apll1_enable(struct mtk_base_afe *afe)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int ret;
+
+	/* setting for APLL */
+	apll1_mux_setting(afe, true);
+
+	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL1]);
+	if (ret)
+		goto ERR_CLK_APLL1;
+
+	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER1]);
+	if (ret)
+		goto ERR_CLK_APLL1_TUNER;
+
+	/* sel 44.1kHz:1, apll_div:7, upper bound:3 */
+	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
+			   XTAL_EN_128FS_SEL_MASK_SFT | APLL_DIV_MASK_SFT | UPPER_BOUND_MASK_SFT,
+			   (0x1 << XTAL_EN_128FS_SEL_SFT) | (7 << APLL_DIV_SFT) |
+			   (3 << UPPER_BOUND_SFT));
+
+	/* apll1 freq tuner enable */
+	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
+			   FREQ_TUNER_EN_MASK_SFT,
+			   0x1 << FREQ_TUNER_EN_SFT);
+
+	/* audio apll1 on */
+	mt8196_afe_enable_top_cg(afe, MT8196_AUDIO_APLL1_EN_ON);
+
+	return 0;
+
+ERR_CLK_APLL1_TUNER:
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER1]);
+ERR_CLK_APLL1:
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL1]);
+	return ret;
+}
+
+void mt8196_apll1_disable(struct mtk_base_afe *afe)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+
+	/* audio apll1 off */
+	mt8196_afe_disable_top_cg(afe, MT8196_AUDIO_APLL1_EN_ON);
+
+	/* apll1 freq tuner disable */
+	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
+			   FREQ_TUNER_EN_MASK_SFT,
+			   0x0);
+
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER1]);
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL1]);
+	apll1_mux_setting(afe, false);
+}
+
+int mt8196_apll2_enable(struct mtk_base_afe *afe)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int ret;
+
+	/* setting for APLL */
+	apll2_mux_setting(afe, true);
+
+	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL2]);
+	if (ret)
+		goto ERR_CLK_APLL2;
+
+	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER2]);
+	if (ret)
+		goto ERR_CLK_APLL2_TUNER;
+
+	/* sel 48kHz: 2, apll_div: 7, upper bound: 3*/
+	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
+			   XTAL_EN_128FS_SEL_MASK_SFT | APLL_DIV_MASK_SFT | UPPER_BOUND_MASK_SFT,
+			   (0x2 << XTAL_EN_128FS_SEL_SFT) | (7 << APLL_DIV_SFT) |
+			   (3 << UPPER_BOUND_SFT));
+
+	/* apll2 freq tuner enable */
+	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
+			   FREQ_TUNER_EN_MASK_SFT,
+			   0x1 << FREQ_TUNER_EN_SFT);
+
+	/* audio apll2 on */
+	mt8196_afe_enable_top_cg(afe, MT8196_AUDIO_APLL2_EN_ON);
+	return 0;
+
+ERR_CLK_APLL2_TUNER:
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER2]);
+ERR_CLK_APLL2:
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL2]);
+	return ret;
+
+	return 0;
+}
+
+void mt8196_apll2_disable(struct mtk_base_afe *afe)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+
+	/* audio apll2 off */
+	mt8196_afe_disable_top_cg(afe, MT8196_AUDIO_APLL2_EN_ON);
+
+	/* apll2 freq tuner disable */
+	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
+			   FREQ_TUNER_EN_MASK_SFT,
+			   0x0);
+
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER2]);
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL2]);
+	apll2_mux_setting(afe, false);
+}
+
+int mt8196_get_apll_rate(struct mtk_base_afe *afe, int apll)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int clk_id = 0;
+
+	if (apll < MT8196_APLL1 || apll > MT8196_APLL2) {
+		dev_warn(afe->dev, "invalid clk id\n");
+		return 0;
+	}
+
+	if (apll == MT8196_APLL1)
+		clk_id = MT8196_CLK_TOP_APLL1_CK;
+	else
+		clk_id = MT8196_CLK_TOP_APLL2_CK;
+
+	return clk_get_rate(afe_priv->clk[clk_id]);
+}
+
+int mt8196_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
+{
+	return ((rate % 8000) == 0) ? MT8196_APLL2 : MT8196_APLL1;
+}
+
+int mt8196_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
+{
+	if (strcmp(name, APLL1_W_NAME) == 0)
+		return MT8196_APLL1;
+	else
+		return MT8196_APLL2;
+}
+
+/* mck */
+struct mt8196_mck_div {
+	int m_sel_id;
+	int div_clk_id;
+};
+
+static const struct mt8196_mck_div mck_div[MT8196_MCK_NUM] = {
+	[MT8196_I2SIN0_MCK] = {
+		.m_sel_id = MT8196_CLK_TOP_I2SIN0_M_SEL,
+		.div_clk_id = MT8196_CLK_TOP_APLL12_DIV_I2SIN0,
+	},
+	[MT8196_I2SIN1_MCK] = {
+		.m_sel_id = MT8196_CLK_TOP_I2SIN1_M_SEL,
+		.div_clk_id = MT8196_CLK_TOP_APLL12_DIV_I2SIN1,
+	},
+	[MT8196_FMI2S_MCK] = {
+		.m_sel_id = MT8196_CLK_TOP_FMI2S_M_SEL,
+		.div_clk_id = MT8196_CLK_TOP_APLL12_DIV_FMI2S,
+	},
+	[MT8196_TDMOUT_MCK] = {
+		.m_sel_id = MT8196_CLK_TOP_TDMOUT_M_SEL,
+		.div_clk_id = MT8196_CLK_TOP_APLL12_DIV_TDMOUT_M,
+	},
+	[MT8196_TDMOUT_BCK] = {
+		.m_sel_id = -1,
+		.div_clk_id = MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B,
+	},
+};
+
+int mt8196_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int apll = mt8196_get_apll_by_rate(afe, rate);
+	int apll_clk_id = apll == MT8196_APLL1 ?
+			  MT8196_CLK_TOP_MUX_AUD_1 : MT8196_CLK_TOP_MUX_AUD_2;
+	int m_sel_id = 0;
+	int div_clk_id = 0;
+	int ret = 0;
+
+	dev_dbg(afe->dev, "mck_id: %d, rate: %d\n", mck_id, rate);
+
+	if (mck_id >= MT8196_MCK_NUM || mck_id < 0)
+		return -EINVAL;
+
+	m_sel_id = mck_div[mck_id].m_sel_id;
+	div_clk_id = mck_div[mck_id].div_clk_id;
+
+	/* select apll */
+	if (m_sel_id >= 0) {
+		ret = mt8196_afe_enable_clk(afe, afe_priv->clk[m_sel_id]);
+		if (ret)
+			return ret;
+
+		ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[m_sel_id],
+						afe_priv->clk[apll_clk_id]);
+		if (ret)
+			return ret;
+	}
+
+	/* enable div, set rate */
+	if (div_clk_id < 0) {
+		dev_err(afe->dev, "invalid div_clk_id %d\n", div_clk_id);
+		return -EINVAL;
+	}
+	if (div_clk_id == MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B)
+		rate = rate * 16;
+
+	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[div_clk_id]);
+	if (ret)
+		return ret;
+
+	ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[div_clk_id], rate);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int mt8196_mck_disable(struct mtk_base_afe *afe, int mck_id)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int m_sel_id = 0;
+	int div_clk_id = 0;
+
+	dev_dbg(afe->dev, "mck_id: %d.\n", mck_id);
+
+	if (mck_id < 0) {
+		dev_err(afe->dev, "mck_id = %d < 0\n", mck_id);
+		return -EINVAL;
+	}
+
+	m_sel_id = mck_div[mck_id].m_sel_id;
+	div_clk_id = mck_div[mck_id].div_clk_id;
+
+	if (div_clk_id < 0) {
+		dev_err(afe->dev, "div_clk_id = %d < 0\n",
+			div_clk_id);
+		return -EINVAL;
+	}
+
+	mt8196_afe_disable_clk(afe, afe_priv->clk[div_clk_id]);
+
+	if (m_sel_id >= 0)
+		mt8196_afe_disable_clk(afe, afe_priv->clk[m_sel_id]);
+
+	return 0;
+}
+
+int mt8196_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+
+	/* bus clock for AFE external access, like DRAM */
+	mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_ADSP_SEL]);
+
+	/* bus clock for AFE internal access, like AFE SRAM */
+	mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIOINTBUS]);
+	mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIOINTBUS],
+				  afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
+	/* enable audio vlp clock source */
+	mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
+	mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
+				  afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
+
+	/* AFE hw clock */
+	/* IPM2.0: USE HOPPING & 26M */
+	mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_AUDIO_HOPPING]);
+	mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_AUDIO_F26M]);
+	return 0;
+}
+
+int mt8196_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+
+	/* IPM2.0: Use HOPPING & 26M */
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_AUDIO_HOPPING]);
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_AUDIO_F26M]);
+	mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
+				  afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
+
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
+	mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIOINTBUS],
+				  afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIOINTBUS]);
+	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_ADSP_SEL]);
+	return 0;
+}
+
+int mt8196_afe_enable_main_clock(struct mtk_base_afe *afe)
+{
+	mt8196_afe_enable_afe_on(afe);
+	return 0;
+}
+
+int mt8196_afe_disable_main_clock(struct mtk_base_afe *afe)
+{
+	mt8196_afe_disable_afe_on(afe);
+	return 0;
+}
+
+int mt8196_init_clock(struct mtk_base_afe *afe)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int ret = 0;
+	int i = 0;
+
+	ret = mt8196_audsys_clk_register(afe);
+	if (ret) {
+		dev_err(afe->dev, "register audsys clk fail %d\n", ret);
+		return ret;
+	}
+
+	afe_priv->clk = devm_kcalloc(afe->dev, MT8196_CLK_NUM, sizeof(*afe_priv->clk),
+				     GFP_KERNEL);
+	if (!afe_priv->clk)
+		return -ENOMEM;
+
+	for (i = 0; i < MT8196_CLK_NUM; i++) {
+		afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
+		if (IS_ERR(afe_priv->clk[i])) {
+			dev_err(afe->dev, "devm_clk_get %s fail\n", aud_clks[i]);
+			return PTR_ERR(afe_priv->clk[i]);
+		}
+	}
+
+	afe_priv->vlp_ck = syscon_regmap_lookup_by_phandle(afe->dev->of_node,
+							   "vlpcksys");
+	if (IS_ERR(afe_priv->vlp_ck)) {
+		dev_err(afe->dev, "Cannot find vlpcksys\n");
+		return PTR_ERR(afe_priv->vlp_ck);
+	}
+
+	mt8196_afe_apll_init(afe);
+
+	ret = mt8196_afe_disable_apll(afe);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-clk.h b/sound/soc/mediatek/mt8196/mt8196-afe-clk.h
new file mode 100644
index 000000000000..60f5e5a157d5
--- /dev/null
+++ b/sound/soc/mediatek/mt8196/mt8196-afe-clk.h
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * mt8196-afe-clk.h  --  Mediatek 8196 afe clock ctrl definition
+ *
+ * Copyright (c) 2024 MediaTek Inc.
+ *  Author: Darren Ye <darren.ye at mediatek.com>
+ */
+
+#ifndef _MT8196_AFE_CLOCK_CTRL_H_
+#define _MT8196_AFE_CLOCK_CTRL_H_
+
+/* vlp_cksys_clk: 0x1c016000 */
+#define VLP_APLL1_TUNER_CON0 0x02a4
+#define VLP_APLL2_TUNER_CON0 0x02a8
+
+/* vlp apll1 tuner default value*/
+#define VLP_APLL1_TUNER_CON0_VALUE 0x6f28bd4d
+/* vlp apll2 tuner default value + 1*/
+#define VLP_APLL2_TUNER_CON0_VALUE 0x78fd5265
+
+/* APLL */
+#define APLL1_W_NAME "APLL1"
+#define APLL2_W_NAME "APLL2"
+
+enum {
+	MT8196_APLL1 = 0,
+	MT8196_APLL2,
+};
+
+enum {
+	/* vlp clk */
+	MT8196_CLK_VLP_MUX_AUDIOINTBUS,
+	MT8196_CLK_VLP_MUX_AUD_ENG1,
+	MT8196_CLK_VLP_MUX_AUD_ENG2,
+	MT8196_CLK_VLP_MUX_AUDIO_H,
+	MT8196_CLK_VLP_CLK26M,
+	/* pll */
+	MT8196_CLK_TOP_APLL1_CK,
+	MT8196_CLK_TOP_APLL2_CK,
+	/* divider */
+	MT8196_CLK_TOP_APLL1_D4,
+	MT8196_CLK_TOP_APLL2_D4,
+	MT8196_CLK_TOP_APLL12_DIV_I2SIN0,
+	MT8196_CLK_TOP_APLL12_DIV_I2SIN1,
+	MT8196_CLK_TOP_APLL12_DIV_FMI2S,
+	MT8196_CLK_TOP_APLL12_DIV_TDMOUT_M,
+	MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B,
+	/* mux */
+	MT8196_CLK_TOP_MUX_AUD_1,
+	MT8196_CLK_TOP_MUX_AUD_2,
+	MT8196_CLK_TOP_I2SIN0_M_SEL,
+	MT8196_CLK_TOP_I2SIN1_M_SEL,
+	MT8196_CLK_TOP_FMI2S_M_SEL,
+	MT8196_CLK_TOP_TDMOUT_M_SEL,
+	MT8196_CLK_TOP_ADSP_SEL,
+	/* top 26m */
+	MT8196_CLK_TOP_CLK26M,
+	/* clock gate */
+	MT8196_CLK_AFE_PCM1,
+	MT8196_CLK_AFE_PCM0,
+	MT8196_CLK_AFE_CM2,
+	MT8196_CLK_AFE_CM1,
+	MT8196_CLK_AFE_CM0,
+	MT8196_CLK_AFE_STF,
+	MT8196_CLK_AFE_HW_GAIN23,
+	MT8196_CLK_AFE_HW_GAIN01,
+	MT8196_CLK_AFE_FM_I2S,
+	MT8196_CLK_AFE_MTKAIFV4,
+	MT8196_CLK_AFE_UL2_ADC_HIRES_TML,
+	MT8196_CLK_AFE_UL2_ADC_HIRES,
+	MT8196_CLK_AFE_UL2_TML,
+	MT8196_CLK_AFE_UL2_ADC,
+	MT8196_CLK_AFE_UL1_ADC_HIRES_TML,
+	MT8196_CLK_AFE_UL1_ADC_HIRES,
+	MT8196_CLK_AFE_UL1_TML,
+	MT8196_CLK_AFE_UL1_ADC,
+	MT8196_CLK_AFE_UL0_ADC_HIRES_TML,
+	MT8196_CLK_AFE_UL0_ADC_HIRES,
+	MT8196_CLK_AFE_UL0_TML,
+	MT8196_CLK_AFE_UL0_ADC,
+	MT8196_CLK_AFE_ETDM_IN6,
+	MT8196_CLK_AFE_ETDM_IN5,
+	MT8196_CLK_AFE_ETDM_IN4,
+	MT8196_CLK_AFE_ETDM_IN3,
+	MT8196_CLK_AFE_ETDM_IN2,
+	MT8196_CLK_AFE_ETDM_IN1,
+	MT8196_CLK_AFE_ETDM_IN0,
+	MT8196_CLK_AFE_ETDM_OUT6,
+	MT8196_CLK_AFE_ETDM_OUT5,
+	MT8196_CLK_AFE_ETDM_OUT4,
+	MT8196_CLK_AFE_ETDM_OUT3,
+	MT8196_CLK_AFE_ETDM_OUT2,
+	MT8196_CLK_AFE_ETDM_OUT1,
+	MT8196_CLK_AFE_ETDM_OUT0,
+	MT8196_CLK_AFE_TDM_OUT,
+	MT8196_CLK_AFE_GENERAL15_ASRC,
+	MT8196_CLK_AFE_GENERAL14_ASRC,
+	MT8196_CLK_AFE_GENERAL13_ASRC,
+	MT8196_CLK_AFE_GENERAL12_ASRC,
+	MT8196_CLK_AFE_GENERAL11_ASRC,
+	MT8196_CLK_AFE_GENERAL10_ASRC,
+	MT8196_CLK_AFE_GENERAL9_ASRC,
+	MT8196_CLK_AFE_GENERAL8_ASRC,
+	MT8196_CLK_AFE_GENERAL7_ASRC,
+	MT8196_CLK_AFE_GENERAL6_ASRC,
+	MT8196_CLK_AFE_GENERAL5_ASRC,
+	MT8196_CLK_AFE_GENERAL4_ASRC,
+	MT8196_CLK_AFE_GENERAL3_ASRC,
+	MT8196_CLK_AFE_GENERAL2_ASRC,
+	MT8196_CLK_AFE_GENERAL1_ASRC,
+	MT8196_CLK_AFE_GENERAL0_ASRC,
+	MT8196_CLK_AFE_CONNSYS_I2S_ASRC,
+	MT8196_CLK_AFE_AUDIO_HOPPING,
+	MT8196_CLK_AFE_AUDIO_F26M,
+	MT8196_CLK_AFE_APLL1,
+	MT8196_CLK_AFE_APLL2,
+	MT8196_CLK_AFE_H208M,
+	MT8196_CLK_AFE_APLL_TUNER2,
+	MT8196_CLK_AFE_APLL_TUNER1,
+	MT8196_CLK_NUM,
+};
+
+struct mtk_base_afe;
+
+int mt8196_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
+int mt8196_mck_disable(struct mtk_base_afe *afe, int mck_id);
+int mt8196_get_apll_rate(struct mtk_base_afe *afe, int apll);
+int mt8196_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
+int mt8196_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
+int mt8196_init_clock(struct mtk_base_afe *afe);
+int mt8196_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
+void mt8196_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
+int mt8196_apll1_enable(struct mtk_base_afe *afe);
+void mt8196_apll1_disable(struct mtk_base_afe *afe);
+int mt8196_apll2_enable(struct mtk_base_afe *afe);
+void mt8196_apll2_disable(struct mtk_base_afe *afe);
+int mt8196_afe_enable_main_clock(struct mtk_base_afe *afe);
+int mt8196_afe_disable_main_clock(struct mtk_base_afe *afe);
+int mt8196_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
+int mt8196_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);
+
+#endif
diff --git a/sound/soc/mediatek/mt8196/mt8196-audsys-clk.c b/sound/soc/mediatek/mt8196/mt8196-audsys-clk.c
new file mode 100644
index 000000000000..aa40f02698ac
--- /dev/null
+++ b/sound/soc/mediatek/mt8196/mt8196-audsys-clk.c
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * mt8196-audsys-clk.c  --  MediaTek 8196 audsys clock control
+ *
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Darren Ye <darren.ye at mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include "mt8196-afe-common.h"
+#include "mt8196-audsys-clk.h"
+#include "mt8196-audsys-clkid.h"
+#include "mt8196-reg.h"
+
+struct afe_gate {
+	int id;
+	const char *name;
+	const char *parent_name;
+	int reg;
+	u8 bit;
+	const struct clk_ops *ops;
+	unsigned long flags;
+	u8 cg_flags;
+};
+
+#define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
+		.id = _id,					\
+		.name = _name,					\
+		.parent_name = _parent,				\
+		.reg = _reg,					\
+		.bit = _bit,					\
+		.flags = _flags,				\
+		.cg_flags = _cgflags,				\
+	}
+
+#define GATE_AFE(_id, _name, _parent, _reg, _bit)		\
+	GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit,		\
+		       CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE)
+
+#define GATE_AUD0(_id, _name, _parent, _bit)			\
+	GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
+
+#define GATE_AUD1(_id, _name, _parent, _bit)			\
+	GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
+
+#define GATE_AUD2(_id, _name, _parent, _bit)			\
+	GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON2, _bit)
+
+#define GATE_AUD3(_id, _name, _parent, _bit)			\
+	GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit)
+
+#define GATE_AUD4(_id, _name, _parent, _bit)			\
+	GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON4, _bit)
+
+static const struct afe_gate aud_clks[CLK_AFE_NR_CLK] = {
+	/* AFE0 */
+	GATE_AUD0(CLK_AFE_PCM1, "afe_pcm1",
+		  "vlp_aud_clksq_ck", 13),
+	GATE_AUD0(CLK_AFE_PCM0, "afe_pcm0",
+		  "vlp_aud_clksq_ck", 14),
+	GATE_AUD0(CLK_AFE_CM2, "afe_cm2",
+		  "vlp_aud_clksq_ck", 16),
+	GATE_AUD0(CLK_AFE_CM1, "afe_cm1",
+		  "vlp_aud_clksq_ck", 17),
+	GATE_AUD0(CLK_AFE_CM0, "afe_cm0",
+		  "vlp_aud_clksq_ck", 18),
+	GATE_AUD0(CLK_AFE_STF, "afe_stf",
+		  "vlp_aud_clksq_ck", 19),
+	GATE_AUD0(CLK_AFE_HW_GAIN23, "afe_hw_gain23",
+		  "vlp_aud_clksq_ck", 20),
+	GATE_AUD0(CLK_AFE_HW_GAIN01, "afe_hw_gain01",
+		  "vlp_aud_clksq_ck", 21),
+	GATE_AUD0(CLK_AFE_FM_I2S, "afe_fm_i2s",
+		  "vlp_aud_clksq_ck", 24),
+	GATE_AUD0(CLK_AFE_MTKAIFV4, "afe_mtkaifv4",
+		  "vlp_aud_clksq_ck", 25),
+	/* AFE1 */
+	GATE_AUD1(CLK_AFE_UL2_ADC_HIRES_TML, "afe_ul2_aht",
+		  "vlp_audio_h_ck", 12),
+	GATE_AUD1(CLK_AFE_UL2_ADC_HIRES, "afe_ul2_adc_hires",
+		  "vlp_audio_h_ck", 13),
+	GATE_AUD1(CLK_AFE_UL2_TML, "afe_ul2_tml",
+		  "vlp_aud_clksq_ck", 14),
+	GATE_AUD1(CLK_AFE_UL2_ADC, "afe_ul2_adc",
+		  "vlp_aud_clksq_ck", 15),
+	GATE_AUD1(CLK_AFE_UL1_ADC_HIRES_TML, "afe_ul1_aht",
+		  "vlp_audio_h_ck", 16),
+	GATE_AUD1(CLK_AFE_UL1_ADC_HIRES, "afe_ul1_adc_hires",
+		  "vlp_audio_h_ck", 17),
+	GATE_AUD1(CLK_AFE_UL1_TML, "afe_ul1_tml",
+		  "vlp_aud_clksq_ck", 18),
+	GATE_AUD1(CLK_AFE_UL1_ADC, "afe_ul1_adc",
+		  "vlp_aud_clksq_ck", 19),
+	GATE_AUD1(CLK_AFE_UL0_ADC_HIRES_TML, "afe_ul0_aht",
+		  "vlp_audio_h_ck", 20),
+	GATE_AUD1(CLK_AFE_UL0_ADC_HIRES, "afe_ul0_adc_hires",
+		  "vlp_audio_h_ck", 21),
+	GATE_AUD1(CLK_AFE_UL0_TML, "afe_ul0_tml",
+		  "vlp_aud_clksq_ck", 22),
+	GATE_AUD1(CLK_AFE_UL0_ADC, "afe_ul0_adc",
+		  "vlp_aud_clksq_ck", 23),
+	/* AFE2 */
+	GATE_AUD2(CLK_AFE_ETDM_IN6, "afe_etdm_in6",
+		  "vlp_aud_clksq_ck", 7),
+	GATE_AUD2(CLK_AFE_ETDM_IN5, "afe_etdm_in5",
+		  "vlp_aud_clksq_ck", 8),
+	GATE_AUD2(CLK_AFE_ETDM_IN4, "afe_etdm_in4",
+		  "vlp_aud_clksq_ck", 9),
+	GATE_AUD2(CLK_AFE_ETDM_IN3, "afe_etdm_in3",
+		  "vlp_aud_clksq_ck", 10),
+	GATE_AUD2(CLK_AFE_ETDM_IN2, "afe_etdm_in2",
+		  "vlp_aud_clksq_ck", 11),
+	GATE_AUD2(CLK_AFE_ETDM_IN1, "afe_etdm_in1",
+		  "vlp_aud_clksq_ck", 12),
+	GATE_AUD2(CLK_AFE_ETDM_IN0, "afe_etdm_in0",
+		  "vlp_aud_clksq_ck", 13),
+	GATE_AUD2(CLK_AFE_ETDM_OUT6, "afe_etdm_out6",
+		  "vlp_aud_clksq_ck", 15),
+	GATE_AUD2(CLK_AFE_ETDM_OUT5, "afe_etdm_out5",
+		  "vlp_aud_clksq_ck", 16),
+	GATE_AUD2(CLK_AFE_ETDM_OUT4, "afe_etdm_out4",
+		  "vlp_aud_clksq_ck", 17),
+	GATE_AUD2(CLK_AFE_ETDM_OUT3, "afe_etdm_out3",
+		  "vlp_aud_clksq_ck", 18),
+	GATE_AUD2(CLK_AFE_ETDM_OUT2, "afe_etdm_out2",
+		  "vlp_aud_clksq_ck", 19),
+	GATE_AUD2(CLK_AFE_ETDM_OUT1, "afe_etdm_out1",
+		  "vlp_aud_clksq_ck", 20),
+	GATE_AUD2(CLK_AFE_ETDM_OUT0, "afe_etdm_out0",
+		  "vlp_aud_clksq_ck", 21),
+	GATE_AUD2(CLK_AFE_TDM_OUT, "afe_tdm_out",
+		  "ck_aud_1_ck", 24),
+	/* AFE3 */
+	GATE_AUD3(CLK_AFE_GENERAL15_ASRC, "afe_general15_asrc",
+		  "vlp_aud_clksq_ck", 9),
+	GATE_AUD3(CLK_AFE_GENERAL14_ASRC, "afe_general14_asrc",
+		  "vlp_aud_clksq_ck", 10),
+	GATE_AUD3(CLK_AFE_GENERAL13_ASRC, "afe_general13_asrc",
+		  "vlp_aud_clksq_ck", 11),
+	GATE_AUD3(CLK_AFE_GENERAL12_ASRC, "afe_general12_asrc",
+		  "vlp_aud_clksq_ck", 12),
+	GATE_AUD3(CLK_AFE_GENERAL11_ASRC, "afe_general11_asrc",
+		  "vlp_aud_clksq_ck", 13),
+	GATE_AUD3(CLK_AFE_GENERAL10_ASRC, "afe_general10_asrc",
+		  "vlp_aud_clksq_ck", 14),
+	GATE_AUD3(CLK_AFE_GENERAL9_ASRC, "afe_general9_asrc",
+		  "vlp_aud_clksq_ck", 15),
+	GATE_AUD3(CLK_AFE_GENERAL8_ASRC, "afe_general8_asrc",
+		  "vlp_aud_clksq_ck", 16),
+	GATE_AUD3(CLK_AFE_GENERAL7_ASRC, "afe_general7_asrc",
+		  "vlp_aud_clksq_ck", 17),
+	GATE_AUD3(CLK_AFE_GENERAL6_ASRC, "afe_general6_asrc",
+		  "vlp_aud_clksq_ck", 18),
+	GATE_AUD3(CLK_AFE_GENERAL5_ASRC, "afe_general5_asrc",
+		  "vlp_aud_clksq_ck", 19),
+	GATE_AUD3(CLK_AFE_GENERAL4_ASRC, "afe_general4_asrc",
+		  "vlp_aud_clksq_ck", 20),
+	GATE_AUD3(CLK_AFE_GENERAL3_ASRC, "afe_general3_asrc",
+		  "vlp_aud_clksq_ck", 21),
+	GATE_AUD3(CLK_AFE_GENERAL2_ASRC, "afe_general2_asrc",
+		  "vlp_aud_clksq_ck", 22),
+	GATE_AUD3(CLK_AFE_GENERAL1_ASRC, "afe_general1_asrc",
+		  "vlp_aud_clksq_ck", 23),
+	GATE_AUD3(CLK_AFE_GENERAL0_ASRC, "afe_general0_asrc",
+		  "vlp_aud_clksq_ck", 24),
+	GATE_AUD3(CLK_AFE_CONNSYS_I2S_ASRC, "afe_connsys_i2s_asrc",
+		  "vlp_aud_clksq_ck", 25),
+	/* AFE4 */
+	GATE_AUD4(CLK_AFE_AUDIO_HOPPING, "afe_audio_hopping_ck",
+		  "vlp_aud_clksq_ck", 0),
+	GATE_AUD4(CLK_AFE_AUDIO_F26M, "afe_audio_f26m_ck",
+		  "vlp_aud_clksq_ck", 1),
+	GATE_AUD4(CLK_AFE_APLL1, "afe_apll1_ck",
+		  "ck_aud_1_ck", 2),
+	GATE_AUD4(CLK_AFE_APLL2, "afe_apll2_ck",
+		  "ck_aud_2_ck", 3),
+	GATE_AUD4(CLK_AFE_H208M, "afe_h208m_ck",
+		  "vlp_audio_h_ck", 4),
+	GATE_AUD4(CLK_AFE_APLL_TUNER2, "afe_apll_tuner2",
+		  "vlp_aud_engen2_ck", 12),
+	GATE_AUD4(CLK_AFE_APLL_TUNER1, "afe_apll_tuner1",
+		  "vlp_aud_engen1_ck", 13),
+};
+
+static void mt8196_audsys_clk_unregister(void *data)
+{
+	struct mtk_base_afe *afe = data;
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	struct clk *clk;
+	struct clk_lookup *cl;
+	int i;
+
+	if (!afe_priv)
+		return;
+
+	for (i = 0; i < CLK_AFE_NR_CLK; i++) {
+		cl = afe_priv->lookup[i];
+		if (!cl)
+			continue;
+
+		clk = cl->clk;
+		clk_unregister_gate(clk);
+
+		clkdev_drop(cl);
+	}
+}
+
+int mt8196_audsys_clk_register(struct mtk_base_afe *afe)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	struct clk *clk;
+	struct clk_lookup *cl;
+	int i;
+
+	afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AFE_NR_CLK,
+					sizeof(*afe_priv->lookup),
+					GFP_KERNEL);
+
+	if (!afe_priv->lookup)
+		return -ENOMEM;
+
+	for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
+		const struct afe_gate *gate = &aud_clks[i];
+
+		clk = clk_register_gate(afe->dev, gate->name, gate->parent_name,
+					gate->flags, afe->base_addr + gate->reg,
+					gate->bit, gate->cg_flags, NULL);
+
+		if (IS_ERR(clk)) {
+			dev_err(afe->dev, "Failed to register clk %s: %ld\n",
+				gate->name, PTR_ERR(clk));
+			continue;
+		}
+
+		/* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */
+		cl = kzalloc(sizeof(*cl), GFP_KERNEL);
+		if (!cl)
+			return -ENOMEM;
+
+		cl->clk = clk;
+		cl->con_id = gate->name;
+		cl->dev_id = dev_name(afe->dev);
+		cl->clk_hw = NULL;
+		clkdev_add(cl);
+
+		afe_priv->lookup[i] = cl;
+	}
+
+	return devm_add_action_or_reset(afe->dev, mt8196_audsys_clk_unregister, afe);
+}
diff --git a/sound/soc/mediatek/mt8196/mt8196-audsys-clk.h b/sound/soc/mediatek/mt8196/mt8196-audsys-clk.h
new file mode 100644
index 000000000000..fad3a38a5ccb
--- /dev/null
+++ b/sound/soc/mediatek/mt8196/mt8196-audsys-clk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * mt8196-audsys-clk.h  --  MediaTek 8196 audsys clock definition
+ *
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Darren Ye <darren.ye at mediatek.com>
+ */
+
+#ifndef _MT8196_AUDSYS_CLK_H_
+#define _MT8196_AUDSYS_CLK_H_
+
+int mt8196_audsys_clk_register(struct mtk_base_afe *afe);
+
+#endif
diff --git a/sound/soc/mediatek/mt8196/mt8196-audsys-clkid.h b/sound/soc/mediatek/mt8196/mt8196-audsys-clkid.h
new file mode 100644
index 000000000000..b61db004eb2b
--- /dev/null
+++ b/sound/soc/mediatek/mt8196/mt8196-audsys-clkid.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * mt8196-audsys-clkid.h  --  MediaTek 8196 audsys clock id definition
+ *
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Darren Ye <darren.ye at mediatek.com>
+ */
+
+#ifndef _MT8196_AUDSYS_CLKID_H_
+#define _MT8196_AUDSYS_CLKID_H_
+
+enum{
+	/* AFE */
+	CLK_AFE_PCM1,
+	CLK_AFE_PCM0,
+	CLK_AFE_CM2,
+	CLK_AFE_CM1,
+	CLK_AFE_CM0,
+	CLK_AFE_STF,
+	CLK_AFE_HW_GAIN23,
+	CLK_AFE_HW_GAIN01,
+	CLK_AFE_FM_I2S,
+	CLK_AFE_MTKAIFV4,
+	CLK_AFE_UL2_ADC_HIRES_TML,
+	CLK_AFE_UL2_ADC_HIRES,
+	CLK_AFE_UL2_TML,
+	CLK_AFE_UL2_ADC,
+	CLK_AFE_UL1_ADC_HIRES_TML,
+	CLK_AFE_UL1_ADC_HIRES,
+	CLK_AFE_UL1_TML,
+	CLK_AFE_UL1_ADC,
+	CLK_AFE_UL0_ADC_HIRES_TML,
+	CLK_AFE_UL0_ADC_HIRES,
+	CLK_AFE_UL0_TML,
+	CLK_AFE_UL0_ADC,
+	CLK_AFE_ETDM_IN6,
+	CLK_AFE_ETDM_IN5,
+	CLK_AFE_ETDM_IN4,
+	CLK_AFE_ETDM_IN3,
+	CLK_AFE_ETDM_IN2,
+	CLK_AFE_ETDM_IN1,
+	CLK_AFE_ETDM_IN0,
+	CLK_AFE_ETDM_OUT6,
+	CLK_AFE_ETDM_OUT5,
+	CLK_AFE_ETDM_OUT4,
+	CLK_AFE_ETDM_OUT3,
+	CLK_AFE_ETDM_OUT2,
+	CLK_AFE_ETDM_OUT1,
+	CLK_AFE_ETDM_OUT0,
+	CLK_AFE_TDM_OUT,
+	CLK_AFE_GENERAL15_ASRC,
+	CLK_AFE_GENERAL14_ASRC,
+	CLK_AFE_GENERAL13_ASRC,
+	CLK_AFE_GENERAL12_ASRC,
+	CLK_AFE_GENERAL11_ASRC,
+	CLK_AFE_GENERAL10_ASRC,
+	CLK_AFE_GENERAL9_ASRC,
+	CLK_AFE_GENERAL8_ASRC,
+	CLK_AFE_GENERAL7_ASRC,
+	CLK_AFE_GENERAL6_ASRC,
+	CLK_AFE_GENERAL5_ASRC,
+	CLK_AFE_GENERAL4_ASRC,
+	CLK_AFE_GENERAL3_ASRC,
+	CLK_AFE_GENERAL2_ASRC,
+	CLK_AFE_GENERAL1_ASRC,
+	CLK_AFE_GENERAL0_ASRC,
+	CLK_AFE_CONNSYS_I2S_ASRC,
+	CLK_AFE_AUDIO_HOPPING,
+	CLK_AFE_AUDIO_F26M,
+	CLK_AFE_APLL1,
+	CLK_AFE_APLL2,
+	CLK_AFE_H208M,
+	CLK_AFE_APLL_TUNER2,
+	CLK_AFE_APLL_TUNER1,
+	CLK_AFE_NR_CLK,
+};
+
+#endif
-- 
2.45.2



From darren.ye at mediatek.com  Wed May 14 01:11:04 2025
From: darren.ye at mediatek.com (Darren.Ye)
Date: Wed, 14 May 2025 16:11:04 +0800
Subject: [PATCH v3 02/10] ASoC: mediatek: mt8196: add common header
In-Reply-To: <20250514081125.24475-1-darren.ye@mediatek.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
Message-ID: <20250514081125.24475-3-darren.ye@mediatek.com>

From: Darren Ye <darren.ye at mediatek.com>

Add header files for register definitions and structures.

Signed-off-by: Darren Ye <darren.ye at mediatek.com>
---
 sound/soc/mediatek/mt8196/mt8196-afe-common.h |   206 +
 .../mediatek/mt8196/mt8196-interconnection.h  |   121 +
 sound/soc/mediatek/mt8196/mt8196-reg.h        | 12068 ++++++++++++++++
 3 files changed, 12395 insertions(+)
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-common.h
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-interconnection.h
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-reg.h

diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-common.h b/sound/soc/mediatek/mt8196/mt8196-afe-common.h
new file mode 100644
index 000000000000..aef46bafb549
--- /dev/null
+++ b/sound/soc/mediatek/mt8196/mt8196-afe-common.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * mt8196-afe-common.h  --  Mediatek 8196 audio driver definitions
+ *
+ * Copyright (c) 2024 MediaTek Inc.
+ *  Author: Darren Ye <darren.ye at mediatek.com>
+ */
+
+#ifndef _MT_8196_AFE_COMMON_H_
+#define _MT_8196_AFE_COMMON_H_
+#include <sound/soc.h>
+#include <sound/pcm.h>
+#include <linux/clk.h>
+#include <linux/list.h>
+#include <linux/regmap.h>
+#include "mt8196-reg.h"
+#include "mtk-base-afe.h"
+
+/* HW IPM 2.0 */
+enum {
+	MTK_AFE_IPM2P0_RATE_8K = 0x0,
+	MTK_AFE_IPM2P0_RATE_11K = 0x1,
+	MTK_AFE_IPM2P0_RATE_12K = 0x2,
+	MTK_AFE_IPM2P0_RATE_16K = 0x4,
+	MTK_AFE_IPM2P0_RATE_22K = 0x5,
+	MTK_AFE_IPM2P0_RATE_24K = 0x6,
+	MTK_AFE_IPM2P0_RATE_32K = 0x8,
+	MTK_AFE_IPM2P0_RATE_44K = 0x9,
+	MTK_AFE_IPM2P0_RATE_48K = 0xa,
+	MTK_AFE_IPM2P0_RATE_88K = 0xd,
+	MTK_AFE_IPM2P0_RATE_96K = 0xe,
+	MTK_AFE_IPM2P0_RATE_176K = 0x11,
+	MTK_AFE_IPM2P0_RATE_192K = 0x12,
+	MTK_AFE_IPM2P0_RATE_352K = 0x15,
+	MTK_AFE_IPM2P0_RATE_384K = 0x16,
+};
+
+enum {
+	MTKAIF_PROTOCOL_1 = 0,
+	MTKAIF_PROTOCOL_2,
+	MTKAIF_PROTOCOL_2_CLK_P2,
+};
+
+enum {
+	MT8196_MEMIF_DL0,
+	MT8196_MEMIF_DL1,
+	MT8196_MEMIF_DL2,
+	MT8196_MEMIF_DL3,
+	MT8196_MEMIF_DL4,
+	MT8196_MEMIF_DL5,
+	MT8196_MEMIF_DL6,
+	MT8196_MEMIF_DL7,
+	MT8196_MEMIF_DL8,
+	MT8196_MEMIF_DL23,
+	MT8196_MEMIF_DL24,
+	MT8196_MEMIF_DL25,
+	MT8196_MEMIF_DL26,
+	MT8196_MEMIF_DL_4CH,
+	MT8196_MEMIF_DL_24CH,
+	MT8196_MEMIF_VUL0,
+	MT8196_MEMIF_VUL1,
+	MT8196_MEMIF_VUL2,
+	MT8196_MEMIF_VUL3,
+	MT8196_MEMIF_VUL4,
+	MT8196_MEMIF_VUL5,
+	MT8196_MEMIF_VUL6,
+	MT8196_MEMIF_VUL7,
+	MT8196_MEMIF_VUL8,
+	MT8196_MEMIF_VUL9,
+	MT8196_MEMIF_VUL10,
+	MT8196_MEMIF_VUL24,
+	MT8196_MEMIF_VUL25,
+	MT8196_MEMIF_VUL26,
+	MT8196_MEMIF_VUL_CM0,
+	MT8196_MEMIF_VUL_CM1,
+	MT8196_MEMIF_VUL_CM2,
+	MT8196_MEMIF_ETDM_IN0,
+	MT8196_MEMIF_ETDM_IN1,
+	MT8196_MEMIF_ETDM_IN2,
+	MT8196_MEMIF_ETDM_IN3,
+	MT8196_MEMIF_ETDM_IN4,
+	MT8196_MEMIF_ETDM_IN6,
+	MT8196_MEMIF_HDMI,
+	MT8196_MEMIF_NUM,
+	MT8196_DAI_ADDA = MT8196_MEMIF_NUM,
+	MT8196_DAI_ADDA_CH34,
+	MT8196_DAI_ADDA_CH56,
+	MT8196_DAI_AP_DMIC,
+	MT8196_DAI_AP_DMIC_CH34,
+	MT8196_DAI_AP_DMIC_MULTICH,
+	MT8196_DAI_I2S_IN0,
+	MT8196_DAI_I2S_IN1,
+	MT8196_DAI_I2S_IN2,
+	MT8196_DAI_I2S_IN3,
+	MT8196_DAI_I2S_IN4,
+	MT8196_DAI_I2S_IN6,
+	MT8196_DAI_I2S_OUT0,
+	MT8196_DAI_I2S_OUT1,
+	MT8196_DAI_I2S_OUT2,
+	MT8196_DAI_I2S_OUT3,
+	MT8196_DAI_I2S_OUT4,
+	MT8196_DAI_I2S_OUT6,
+	MT8196_DAI_FM_I2S_MASTER,
+	MT8196_DAI_TDM,
+	MT8196_DAI_TDM_DPTX,
+	MT8196_DAI_NUM,
+};
+
+#define MT8196_DAI_I2S_MAX_NUM 13 //depends each platform's max i2s num
+
+/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
+enum {
+	MT8196_IRQ_0,
+	MT8196_IRQ_1,
+	MT8196_IRQ_2,
+	MT8196_IRQ_3,
+	MT8196_IRQ_4,
+	MT8196_IRQ_5,
+	MT8196_IRQ_6,
+	MT8196_IRQ_7,
+	MT8196_IRQ_8,
+	MT8196_IRQ_9,
+	MT8196_IRQ_10,
+	MT8196_IRQ_11,
+	MT8196_IRQ_12,
+	MT8196_IRQ_13,
+	MT8196_IRQ_14,
+	MT8196_IRQ_15,
+	MT8196_IRQ_16,
+	MT8196_IRQ_17,
+	MT8196_IRQ_18,
+	MT8196_IRQ_19,
+	MT8196_IRQ_20,
+	MT8196_IRQ_21,
+	MT8196_IRQ_22,
+	MT8196_IRQ_23,
+	MT8196_IRQ_24,
+	MT8196_IRQ_25,
+	MT8196_IRQ_26,
+	MT8196_IRQ_31,  /* used only for TDM */
+	MT8196_IRQ_NUM,
+};
+
+/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
+enum {
+	MT8196_CUS_IRQ_TDM = 0,  /* used only for TDM */
+	MT8196_CUS_IRQ_NUM,
+};
+
+/* AUDIO_ENGEN_CON0 */
+enum {
+	MT8196_AUDIO_26M_EN_ON,
+	MT8196_AUDIO_F3P25M_EN_ON,
+	MT8196_AUDIO_APLL1_EN_ON,
+	MT8196_AUDIO_APLL2_EN_ON,
+	MT8196_AUDIO_F26M_EN_RST = 8,
+	MT8196_MULTI_USER_RST = 16,
+	MT8196_MULTI_USER_BYPASS = 17,
+	MT8196_AUDIO_ENGEN_NUM,
+};
+
+/* MCLK */
+enum {
+	MT8196_I2SIN0_MCK = 0,
+	MT8196_I2SIN1_MCK,
+	MT8196_FMI2S_MCK,
+	MT8196_TDMOUT_MCK,
+	MT8196_TDMOUT_BCK,
+	MT8196_MCK_NUM,
+};
+
+/* CM*/
+enum {
+	CM0,
+	CM1,
+	CM2,
+	CM_NUM,
+};
+
+struct mt8196_afe_private {
+	struct clk **clk;
+	struct clk_lookup **lookup;
+	struct regmap *vlp_ck;
+	int irq_cnt[MT8196_MEMIF_NUM];
+	int dram_resource_counter;
+
+	/* xrun assert */
+	int xrun_assert[MT8196_MEMIF_NUM];
+
+	/* dai */
+	void *dai_priv[MT8196_DAI_NUM];
+
+	/* mck */
+	int mck_rate[MT8196_MCK_NUM];
+
+	/* channel merge */
+	unsigned int cm_rate[CM_NUM];
+	unsigned int cm_channels;
+};
+
+int mt8196_dai_adda_register(struct mtk_base_afe *afe);
+int mt8196_dai_i2s_register(struct mtk_base_afe *afe);
+int mt8196_dai_tdm_register(struct mtk_base_afe *afe);
+int mt8196_dai_set_priv(struct mtk_base_afe *afe, int id,
+			int priv_size, const void *priv_data);
+#endif
diff --git a/sound/soc/mediatek/mt8196/mt8196-interconnection.h b/sound/soc/mediatek/mt8196/mt8196-interconnection.h
new file mode 100644
index 000000000000..e884ec3ecb31
--- /dev/null
+++ b/sound/soc/mediatek/mt8196/mt8196-interconnection.h
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Mediatek MT8196 audio driver interconnection definition
+ *
+ *  Copyright (c) 2024 MediaTek Inc.
+ *  Author: Darren Ye <darren.ye at mediatek.com>
+ */
+
+#ifndef _MT8196_INTERCONNECTION_H_
+#define _MT8196_INTERCONNECTION_H_
+
+/* in port define */
+
+#define I_CONNSYS_I2S_CH1 0
+#define I_CONNSYS_I2S_CH2 1
+#define I_GAIN0_OUT_CH1 6
+#define I_GAIN0_OUT_CH2 7
+#define I_GAIN1_OUT_CH1 8
+#define I_GAIN1_OUT_CH2 9
+#define I_GAIN2_OUT_CH1 10
+#define I_GAIN2_OUT_CH2 11
+#define I_GAIN3_OUT_CH1 12
+#define I_GAIN3_OUT_CH2 13
+#define I_STF_CH1 14
+#define I_ADDA_UL_CH1 16
+#define I_ADDA_UL_CH2 17
+#define I_ADDA_UL_CH3 18
+#define I_ADDA_UL_CH4 19
+#define I_UL_PROX_CH1 20
+#define I_UL_PROX_CH2 21
+#define I_ADDA_UL_CH5 24
+#define I_ADDA_UL_CH6 25
+#define I_DMIC0_CH1 28
+#define I_DMIC0_CH2 29
+#define I_DMIC1_CH1 30
+#define I_DMIC1_CH2 31
+
+/* in port define >= 32 */
+#define I_32_OFFSET 32
+#define I_DL0_CH1 (32 - I_32_OFFSET)
+#define I_DL0_CH2 (33 - I_32_OFFSET)
+#define I_DL1_CH1 (34 - I_32_OFFSET)
+#define I_DL1_CH2 (35 - I_32_OFFSET)
+#define I_DL2_CH1 (36 - I_32_OFFSET)
+#define I_DL2_CH2 (37 - I_32_OFFSET)
+#define I_DL3_CH1 (38 - I_32_OFFSET)
+#define I_DL3_CH2 (39 - I_32_OFFSET)
+#define I_DL4_CH1 (40 - I_32_OFFSET)
+#define I_DL4_CH2 (41 - I_32_OFFSET)
+#define I_DL5_CH1 (42 - I_32_OFFSET)
+#define I_DL5_CH2 (43 - I_32_OFFSET)
+#define I_DL6_CH1 (44 - I_32_OFFSET)
+#define I_DL6_CH2 (45 - I_32_OFFSET)
+#define I_DL7_CH1 (46 - I_32_OFFSET)
+#define I_DL7_CH2 (47 - I_32_OFFSET)
+#define I_DL8_CH1 (48 - I_32_OFFSET)
+#define I_DL8_CH2 (49 - I_32_OFFSET)
+#define I_DL_4CH_CH1 (50 - I_32_OFFSET)
+#define I_DL_4CH_CH2 (51 - I_32_OFFSET)
+#define I_DL_4CH_CH3 (52 - I_32_OFFSET)
+#define I_DL_4CH_CH4 (53 - I_32_OFFSET)
+#define I_DL_24CH_CH1 (54 - I_32_OFFSET)
+#define I_DL_24CH_CH2 (55 - I_32_OFFSET)
+#define I_DL_24CH_CH3 (56 - I_32_OFFSET)
+#define I_DL_24CH_CH4 (57 - I_32_OFFSET)
+#define I_DL_24CH_CH5 (58 - I_32_OFFSET)
+#define I_DL_24CH_CH6 (59 - I_32_OFFSET)
+#define I_DL_24CH_CH7 (60 - I_32_OFFSET)
+#define I_DL_24CH_CH8 (61 - I_32_OFFSET)
+
+/* in port define >= 64 */
+#define I_64_OFFSET 64
+#define I_DL23_CH1 (78 - I_64_OFFSET)
+#define I_DL23_CH2 (79 - I_64_OFFSET)
+#define I_DL24_CH1 (80 - I_64_OFFSET)
+#define I_DL24_CH2 (81 - I_64_OFFSET)
+#define I_DL25_CH1 (82 - I_64_OFFSET)
+#define I_DL25_CH2 (83 - I_64_OFFSET)
+#define I_DL26_CH1 (84 - I_64_OFFSET)
+#define I_DL26_CH2 (85 - I_64_OFFSET)
+
+/* in port define >= 128 */
+#define I_128_OFFSET 128
+#define I_PCM_0_CAP_CH1 (130 - I_128_OFFSET)
+#define I_PCM_0_CAP_CH2 (131 - I_128_OFFSET)
+#define I_PCM_1_CAP_CH1 (132 - I_128_OFFSET)
+#define I_PCM_1_CAP_CH2 (133 - I_128_OFFSET)
+#define I_I2SIN0_CH1 (134 - I_128_OFFSET)
+#define I_I2SIN0_CH2 (135 - I_128_OFFSET)
+#define I_I2SIN1_CH1 (136 - I_128_OFFSET)
+#define I_I2SIN1_CH2 (137 - I_128_OFFSET)
+#define I_I2SIN2_CH1 (138 - I_128_OFFSET)
+#define I_I2SIN2_CH2 (139 - I_128_OFFSET)
+#define I_I2SIN3_CH1 (140 - I_128_OFFSET)
+#define I_I2SIN3_CH2 (141 - I_128_OFFSET)
+#define I_I2SIN4_CH1 (142 - I_128_OFFSET)
+#define I_I2SIN4_CH2 (143 - I_128_OFFSET)
+#define I_I2SIN4_CH3 (144 - I_128_OFFSET)
+#define I_I2SIN4_CH4 (145 - I_128_OFFSET)
+#define I_I2SIN4_CH5 (146 - I_128_OFFSET)
+#define I_I2SIN4_CH6 (147 - I_128_OFFSET)
+#define I_I2SIN4_CH7 (148 - I_128_OFFSET)
+#define I_I2SIN4_CH8 (149 - I_128_OFFSET)
+
+/* in port define >= 160 */
+#define I_160_OFFSET 160
+#define I_I2SIN6_CH1 (166 - I_160_OFFSET)
+#define I_I2SIN6_CH2 (167 - I_160_OFFSET)
+
+/* in port define >= 192 */
+#define I_192_OFFSET 192
+#define I_SRC_0_OUT_CH1 (198 - I_192_OFFSET)
+#define I_SRC_0_OUT_CH2 (199 - I_192_OFFSET)
+#define I_SRC_1_OUT_CH1 (200 - I_192_OFFSET)
+#define I_SRC_1_OUT_CH2 (201 - I_192_OFFSET)
+#define I_SRC_2_OUT_CH1 (202 - I_192_OFFSET)
+#define I_SRC_2_OUT_CH2 (203 - I_192_OFFSET)
+#define I_SRC_3_OUT_CH1 (204 - I_192_OFFSET)
+#define I_SRC_3_OUT_CH2 (205 - I_192_OFFSET)
+
+#endif
diff --git a/sound/soc/mediatek/mt8196/mt8196-reg.h b/sound/soc/mediatek/mt8196/mt8196-reg.h
new file mode 100644
index 000000000000..df9c803637a6
--- /dev/null
+++ b/sound/soc/mediatek/mt8196/mt8196-reg.h
@@ -0,0 +1,12068 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * mt8196-reg.h  --  Mediatek 8196 audio driver reg definition
+ *
+ *  Copyright (c) 2024 MediaTek Inc.
+ *  Author: Darren Ye <darren.ye at mediatek.com>
+ */
+
+#ifndef _MT8196_REG_H_
+#define _MT8196_REG_H_
+
+ /* reg bit enum */
+enum {
+	MT8196_MEMIF_PBUF_SIZE_32_BYTES,
+	MT8196_MEMIF_PBUF_SIZE_64_BYTES,
+	MT8196_MEMIF_PBUF_SIZE_128_BYTES,
+	MT8196_MEMIF_PBUF_SIZE_256_BYTES,
+	MT8196_MEMIF_PBUF_SIZE_NUM,
+};
+
+enum {
+	MT8196_MEMIF_MAX_LEN_0_BYTES,
+	MT8196_MEMIF_MAX_LEN_16_BYTES,
+	MT8196_MEMIF_MAX_LEN_32_BYTES,
+	MT8196_MEMIF_MAX_LEN_64_BYTES,
+};
+
+enum {
+	MT8196_MEMIF_MIN_LEN_NOT_SUPPORT,
+	MT8196_MEMIF_MIN_LEN_16_BYTES,
+	MT8196_MEMIF_MIN_LEN_32_BYTES,
+	MT8196_MEMIF_MIN_LEN_64_BYTES,
+};
+
+/*****************************************************************************
+ * R E G I S T E R  D E F I N I T I O N
+ *****************************************************************************/
+/* AUDIO_TOP_CON0 */
+#define PDN_MTKAIFV4_SFT                                      25
+#define PDN_MTKAIFV4_MASK                                     0x1
+#define PDN_MTKAIFV4_MASK_SFT                                 (0x1 << 25)
+#define PDN_FM_I2S_SFT                                        24
+#define PDN_FM_I2S_MASK                                       0x1
+#define PDN_FM_I2S_MASK_SFT                                   (0x1 << 24)
+#define PDN_HW_GAIN01_SFT                                     21
+#define PDN_HW_GAIN01_MASK                                    0x1
+#define PDN_HW_GAIN01_MASK_SFT                                (0x1 << 21)
+#define PDN_HW_GAIN23_SFT                                     20
+#define PDN_HW_GAIN23_MASK                                    0x1
+#define PDN_HW_GAIN23_MASK_SFT                                (0x1 << 20)
+#define PDN_STF_SFT                                           19
+#define PDN_STF_MASK                                          0x1
+#define PDN_STF_MASK_SFT                                      (0x1 << 19)
+#define PDN_CM0_SFT                                           18
+#define PDN_CM0_MASK                                          0x1
+#define PDN_CM0_MASK_SFT                                      (0x1 << 18)
+#define PDN_CM1_SFT                                           17
+#define PDN_CM1_MASK                                          0x1
+#define PDN_CM1_MASK_SFT                                      (0x1 << 17)
+#define PDN_CM2_SFT                                           16
+#define PDN_CM2_MASK                                          0x1
+#define PDN_CM2_MASK_SFT                                      (0x1 << 16)
+#define PDN_PCM0_SFT                                          14
+#define PDN_PCM0_MASK                                         0x1
+#define PDN_PCM0_MASK_SFT                                     (0x1 << 14)
+#define PDN_PCM1_SFT                                          13
+#define PDN_PCM1_MASK                                         0x1
+#define PDN_PCM1_MASK_SFT                                     (0x1 << 13)
+
+/* AUDIO_TOP_CON1 */
+#define PDN_UL0_ADC_SFT                                       23
+#define PDN_UL0_ADC_MASK                                      0x1
+#define PDN_UL0_ADC_MASK_SFT                                  (0x1 << 23)
+#define PDN_UL0_TML_SFT                                       22
+#define PDN_UL0_TML_MASK                                      0x1
+#define PDN_UL0_TML_MASK_SFT                                  (0x1 << 22)
+#define PDN_UL0_ADC_HIRES_SFT                                 21
+#define PDN_UL0_ADC_HIRES_MASK                                0x1
+#define PDN_UL0_ADC_HIRES_MASK_SFT                            (0x1 << 21)
+#define PDN_UL0_ADC_HIRES_TML_SFT                             20
+#define PDN_UL0_ADC_HIRES_TML_MASK                            0x1
+#define PDN_UL0_ADC_HIRES_TML_MASK_SFT                        (0x1 << 20)
+#define PDN_UL1_ADC_SFT                                       19
+#define PDN_UL1_ADC_MASK                                      0x1
+#define PDN_UL1_ADC_MASK_SFT                                  (0x1 << 19)
+#define PDN_UL1_TML_SFT                                       18
+#define PDN_UL1_TML_MASK                                      0x1
+#define PDN_UL1_TML_MASK_SFT                                  (0x1 << 18)
+#define PDN_UL1_ADC_HIRES_SFT                                 17
+#define PDN_UL1_ADC_HIRES_MASK                                0x1
+#define PDN_UL1_ADC_HIRES_MASK_SFT                            (0x1 << 17)
+#define PDN_UL1_ADC_HIRES_TML_SFT                             16
+#define PDN_UL1_ADC_HIRES_TML_MASK                            0x1
+#define PDN_UL1_ADC_HIRES_TML_MASK_SFT                        (0x1 << 16)
+#define PDN_UL2_ADC_SFT                                       15
+#define PDN_UL2_ADC_MASK                                      0x1
+#define PDN_UL2_ADC_MASK_SFT                                  (0x1 << 15)
+#define PDN_UL2_TML_SFT                                       14
+#define PDN_UL2_TML_MASK                                      0x1
+#define PDN_UL2_TML_MASK_SFT                                  (0x1 << 14)
+#define PDN_UL2_ADC_HIRES_SFT                                 13
+#define PDN_UL2_ADC_HIRES_MASK                                0x1
+#define PDN_UL2_ADC_HIRES_MASK_SFT                            (0x1 << 13)
+#define PDN_UL2_ADC_HIRES_TML_SFT                             12
+#define PDN_UL2_ADC_HIRES_TML_MASK                            0x1
+#define PDN_UL2_ADC_HIRES_TML_MASK_SFT                        (0x1 << 12)
+
+/* AUDIO_TOP_CON2 */
+#define PDN_TDM_OUT_SFT                                       24
+#define PDN_TDM_OUT_MASK                                      0x1
+#define PDN_TDM_OUT_MASK_SFT                                  (0x1 << 24)
+#define PDN_ETDM_OUT0_SFT                                     21
+#define PDN_ETDM_OUT0_MASK                                    0x1
+#define PDN_ETDM_OUT0_MASK_SFT                                (0x1 << 21)
+#define PDN_ETDM_OUT1_SFT                                     20
+#define PDN_ETDM_OUT1_MASK                                    0x1
+#define PDN_ETDM_OUT1_MASK_SFT                                (0x1 << 20)
+#define PDN_ETDM_OUT2_SFT                                     19
+#define PDN_ETDM_OUT2_MASK                                    0x1
+#define PDN_ETDM_OUT2_MASK_SFT                                (0x1 << 19)
+#define PDN_ETDM_OUT3_SFT                                     18
+#define PDN_ETDM_OUT3_MASK                                    0x1
+#define PDN_ETDM_OUT3_MASK_SFT                                (0x1 << 18)
+#define PDN_ETDM_OUT4_SFT                                     17
+#define PDN_ETDM_OUT4_MASK                                    0x1
+#define PDN_ETDM_OUT4_MASK_SFT                                (0x1 << 17)
+#define PDN_ETDM_OUT5_SFT                                     16
+#define PDN_ETDM_OUT5_MASK                                    0x1
+#define PDN_ETDM_OUT5_MASK_SFT                                (0x1 << 16)
+#define PDN_ETDM_OUT6_SFT                                     15
+#define PDN_ETDM_OUT6_MASK                                    0x1
+#define PDN_ETDM_OUT6_MASK_SFT                                (0x1 << 15)
+#define PDN_ETDM_IN0_SFT                                      13
+#define PDN_ETDM_IN0_MASK                                     0x1
+#define PDN_ETDM_IN0_MASK_SFT                                 (0x1 << 13)
+#define PDN_ETDM_IN1_SFT                                      12
+#define PDN_ETDM_IN1_MASK                                     0x1
+#define PDN_ETDM_IN1_MASK_SFT                                 (0x1 << 12)
+#define PDN_ETDM_IN2_SFT                                      11
+#define PDN_ETDM_IN2_MASK                                     0x1
+#define PDN_ETDM_IN2_MASK_SFT                                 (0x1 << 11)
+#define PDN_ETDM_IN3_SFT                                      10
+#define PDN_ETDM_IN3_MASK                                     0x1
+#define PDN_ETDM_IN3_MASK_SFT                                 (0x1 << 10)
+#define PDN_ETDM_IN4_SFT                                      9
+#define PDN_ETDM_IN4_MASK                                     0x1
+#define PDN_ETDM_IN4_MASK_SFT                                 (0x1 << 9)
+#define PDN_ETDM_IN5_SFT                                      8
+#define PDN_ETDM_IN5_MASK                                     0x1
+#define PDN_ETDM_IN5_MASK_SFT                                 (0x1 << 8)
+#define PDN_ETDM_IN6_SFT                                      7
+#define PDN_ETDM_IN6_MASK                                     0x1
+#define PDN_ETDM_IN6_MASK_SFT                                 (0x1 << 7)
+
+/* AUDIO_TOP_CON3 */
+#define PDN_CONNSYS_I2S_ASRC_SFT                              25
+#define PDN_CONNSYS_I2S_ASRC_MASK                             0x1
+#define PDN_CONNSYS_I2S_ASRC_MASK_SFT                         (0x1 << 25)
+#define PDN_GENERAL0_ASRC_SFT                                 24
+#define PDN_GENERAL0_ASRC_MASK                                0x1
+#define PDN_GENERAL0_ASRC_MASK_SFT                            (0x1 << 24)
+#define PDN_GENERAL1_ASRC_SFT                                 23
+#define PDN_GENERAL1_ASRC_MASK                                0x1
+#define PDN_GENERAL1_ASRC_MASK_SFT                            (0x1 << 23)
+#define PDN_GENERAL2_ASRC_SFT                                 22
+#define PDN_GENERAL2_ASRC_MASK                                0x1
+#define PDN_GENERAL2_ASRC_MASK_SFT                            (0x1 << 22)
+#define PDN_GENERAL3_ASRC_SFT                                 21
+#define PDN_GENERAL3_ASRC_MASK                                0x1
+#define PDN_GENERAL3_ASRC_MASK_SFT                            (0x1 << 21)
+#define PDN_GENERAL4_ASRC_SFT                                 20
+#define PDN_GENERAL4_ASRC_MASK                                0x1
+#define PDN_GENERAL4_ASRC_MASK_SFT                            (0x1 << 20)
+#define PDN_GENERAL5_ASRC_SFT                                 19
+#define PDN_GENERAL5_ASRC_MASK                                0x1
+#define PDN_GENERAL5_ASRC_MASK_SFT                            (0x1 << 19)
+#define PDN_GENERAL6_ASRC_SFT                                 18
+#define PDN_GENERAL6_ASRC_MASK                                0x1
+#define PDN_GENERAL6_ASRC_MASK_SFT                            (0x1 << 18)
+#define PDN_GENERAL7_ASRC_SFT                                 17
+#define PDN_GENERAL7_ASRC_MASK                                0x1
+#define PDN_GENERAL7_ASRC_MASK_SFT                            (0x1 << 17)
+#define PDN_GENERAL8_ASRC_SFT                                 16
+#define PDN_GENERAL8_ASRC_MASK                                0x1
+#define PDN_GENERAL8_ASRC_MASK_SFT                            (0x1 << 16)
+#define PDN_GENERAL9_ASRC_SFT                                 15
+#define PDN_GENERAL9_ASRC_MASK                                0x1
+#define PDN_GENERAL9_ASRC_MASK_SFT                            (0x1 << 15)
+#define PDN_GENERAL10_ASRC_SFT                                14
+#define PDN_GENERAL10_ASRC_MASK                               0x1
+#define PDN_GENERAL10_ASRC_MASK_SFT                           (0x1 << 14)
+#define PDN_GENERAL11_ASRC_SFT                                13
+#define PDN_GENERAL11_ASRC_MASK                               0x1
+#define PDN_GENERAL11_ASRC_MASK_SFT                           (0x1 << 13)
+#define PDN_GENERAL12_ASRC_SFT                                12
+#define PDN_GENERAL12_ASRC_MASK                               0x1
+#define PDN_GENERAL12_ASRC_MASK_SFT                           (0x1 << 12)
+#define PDN_GENERAL13_ASRC_SFT                                11
+#define PDN_GENERAL13_ASRC_MASK                               0x1
+#define PDN_GENERAL13_ASRC_MASK_SFT                           (0x1 << 11)
+#define PDN_GENERAL14_ASRC_SFT                                10
+#define PDN_GENERAL14_ASRC_MASK                               0x1
+#define PDN_GENERAL14_ASRC_MASK_SFT                           (0x1 << 10)
+#define PDN_GENERAL15_ASRC_SFT                                9
+#define PDN_GENERAL15_ASRC_MASK                               0x1
+#define PDN_GENERAL15_ASRC_MASK_SFT                           (0x1 << 9)
+
+/* AUDIO_TOP_CON4 */
+#define PDN_APLL_TUNER1_SFT                                   13
+#define PDN_APLL_TUNER1_MASK                                  0x1
+#define PDN_APLL_TUNER1_MASK_SFT                              (0x1 << 13)
+#define PDN_APLL_TUNER2_SFT                                   12
+#define PDN_APLL_TUNER2_MASK                                  0x1
+#define PDN_APLL_TUNER2_MASK_SFT                              (0x1 << 12)
+#define CG_H208M_CK_SFT                                       4
+#define CG_H208M_CK_MASK                                      0x1
+#define CG_H208M_CK_MASK_SFT                                  (0x1 << 4)
+#define CG_APLL2_CK_SFT                                       3
+#define CG_APLL2_CK_MASK                                      0x1
+#define CG_APLL2_CK_MASK_SFT                                  (0x1 << 3)
+#define CG_APLL1_CK_SFT                                       2
+#define CG_APLL1_CK_MASK                                      0x1
+#define CG_APLL1_CK_MASK_SFT                                  (0x1 << 2)
+#define CG_AUDIO_F26M_CK_SFT                                  1
+#define CG_AUDIO_F26M_CK_MASK                                 0x1
+#define CG_AUDIO_F26M_CK_MASK_SFT                             (0x1 << 1)
+#define CG_AUDIO_HOPPING_CK_SFT                               0
+#define CG_AUDIO_HOPPING_CK_MASK                              0x1
+#define CG_AUDIO_HOPPING_CK_MASK_SFT                          (0x1 << 0)
+
+/* AUDIO_ENGEN_CON0 */
+/* AUDIO_ENGEN_CON0_USER1 */
+/* AUDIO_ENGEN_CON0_USER1 */
+#define MULTI_USER_BYPASS_SFT                                 17
+#define MULTI_USER_BYPASS_MASK                                0x1
+#define MULTI_USER_BYPASS_MASK_SFT                            (0x1 << 17)
+#define MULTI_USER_RST_SFT                                    16
+#define MULTI_USER_RST_MASK                                   0x1
+#define MULTI_USER_RST_MASK_SFT                               (0x1 << 16)
+#define AUDIO_F26M_EN_RST_SFT                                 8
+#define AUDIO_F26M_EN_RST_MASK                                0x1
+#define AUDIO_F26M_EN_RST_MASK_SFT                            (0x1 << 8)
+#define AUDIO_APLL2_EN_ON_SFT                                 3
+#define AUDIO_APLL2_EN_ON_MASK                                0x1
+#define AUDIO_APLL2_EN_ON_MASK_SFT                            (0x1 << 3)
+#define AUDIO_APLL1_EN_ON_SFT                                 2
+#define AUDIO_APLL1_EN_ON_MASK                                0x1
+#define AUDIO_APLL1_EN_ON_MASK_SFT                            (0x1 << 2)
+#define AUDIO_F3P25M_EN_ON_SFT                                1
+#define AUDIO_F3P25M_EN_ON_MASK                               0x1
+#define AUDIO_F3P25M_EN_ON_MASK_SFT                           (0x1 << 1)
+#define AUDIO_26M_EN_ON_SFT                                   0
+#define AUDIO_26M_EN_ON_MASK                                  0x1
+#define AUDIO_26M_EN_ON_MASK_SFT                              (0x1 << 0)
+
+/* AFE_SINEGEN_CON0 */
+#define DAC_EN_SFT                                            26
+#define DAC_EN_MASK                                           0x1
+#define DAC_EN_MASK_SFT                                       (0x1 << 26)
+#define TIE_SW_CH2_SFT                                        25
+#define TIE_SW_CH2_MASK                                       0x1
+#define TIE_SW_CH2_MASK_SFT                                   (0x1 << 25)
+#define TIE_SW_CH1_SFT                                        24
+#define TIE_SW_CH1_MASK                                       0x1
+#define TIE_SW_CH1_MASK_SFT                                   (0x1 << 24)
+#define AMP_DIV_CH2_SFT                                       20
+#define AMP_DIV_CH2_MASK                                      0xf
+#define AMP_DIV_CH2_MASK_SFT                                  (0xf << 20)
+#define FREQ_DIV_CH2_SFT                                      12
+#define FREQ_DIV_CH2_MASK                                     0x1f
+#define FREQ_DIV_CH2_MASK_SFT                                 (0x1f << 12)
+#define AMP_DIV_CH1_SFT                                       8
+#define AMP_DIV_CH1_MASK                                      0xf
+#define AMP_DIV_CH1_MASK_SFT                                  (0xf << 8)
+#define FREQ_DIV_CH1_SFT                                      0
+#define FREQ_DIV_CH1_MASK                                     0x1f
+#define FREQ_DIV_CH1_MASK_SFT                                 (0x1f << 0)
+
+/* AFE_SINEGEN_CON1 */
+#define SINE_DOMAIN_SFT                                       20
+#define SINE_DOMAIN_MASK                                      0x7
+#define SINE_DOMAIN_MASK_SFT                                  (0x7 << 20)
+#define SINE_MODE_SFT                                         12
+#define SINE_MODE_MASK                                        0x1f
+#define SINE_MODE_MASK_SFT                                    (0x1f << 12)
+#define INNER_LOOP_BACKI_SEL_SFT                              8
+#define INNER_LOOP_BACKI_SEL_MASK                             0x1
+#define INNER_LOOP_BACKI_SEL_MASK_SFT                         (0x1 << 8)
+#define INNER_LOOP_BACK_MODE_SFT                              0
+#define INNER_LOOP_BACK_MODE_MASK                             0xff
+#define INNER_LOOP_BACK_MODE_MASK_SFT                         (0xff << 0)
+
+/* AFE_SINEGEN_CON2 */
+#define TIE_CH1_CONSTANT_SFT                                  0
+#define TIE_CH1_CONSTANT_MASK                                 0xffffffff
+#define TIE_CH1_CONSTANT_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_SINEGEN_CON3 */
+#define TIE_CH2_CONSTANT_SFT                                  0
+#define TIE_CH2_CONSTANT_MASK                                 0xffffffff
+#define TIE_CH2_CONSTANT_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_APLL1_TUNER_CFG */
+/* AFE_APLL2_TUNER_CFG */
+#define UPPER_BOUND_SFT                                       8
+#define UPPER_BOUND_MASK                                      0xff
+#define UPPER_BOUND_MASK_SFT                                  (0xff << 8)
+#define APLL_DIV_SFT                                          4
+#define APLL_DIV_MASK                                         0xf
+#define APLL_DIV_MASK_SFT                                     (0xf << 4)
+#define XTAL_EN_128FS_SEL_SFT                                 1
+#define XTAL_EN_128FS_SEL_MASK                                0x3
+#define XTAL_EN_128FS_SEL_MASK_SFT                            (0x3 << 1)
+#define FREQ_TUNER_EN_SFT                                     0
+#define FREQ_TUNER_EN_MASK                                    0x1
+#define FREQ_TUNER_EN_MASK_SFT                                (0x1 << 0)
+
+/* AFE_APLL1_TUNER_MON0 */
+/* AFE_APLL2_TUNER_MON0 */
+#define TUNER_MON_SFT                                         0
+#define TUNER_MON_MASK                                        0xffffffff
+#define TUNER_MON_MASK_SFT                                    (0xffffffff << 0)
+
+/* AUDIO_TOP_RG0 */
+/* AUDIO_TOP_RG1 */
+/* AUDIO_TOP_RG2 */
+/* AUDIO_TOP_RG3 */
+/* AUDIO_TOP_RG4 */
+#define RESERVE_RG_SFT                                        0
+#define RESERVE_RG_MASK                                       0xffffffff
+#define RESERVE_RG_MASK_SFT                                   (0xffffffff << 0)
+
+/* AFE_SPM_CONTROL_REQ */
+#define AFE_DDREN_REQ_SFT                                     4
+#define AFE_DDREN_REQ_MASK                                    0x1
+#define AFE_DDREN_REQ_MASK_SFT                                (0x1 << 4)
+#define AFE_INFRA_REQ_SFT                                     3
+#define AFE_INFRA_REQ_MASK                                    0x1
+#define AFE_INFRA_REQ_MASK_SFT                                (0x1 << 3)
+#define AFE_VRF18_REQ_SFT                                     2
+#define AFE_VRF18_REQ_MASK                                    0x1
+#define AFE_VRF18_REQ_MASK_SFT                                (0x1 << 2)
+#define AFE_APSRC_REQ_SFT                                     1
+#define AFE_APSRC_REQ_MASK                                    0x1
+#define AFE_APSRC_REQ_MASK_SFT                                (0x1 << 1)
+#define AFE_SRCCLKENA_REQ_SFT                                 0
+#define AFE_SRCCLKENA_REQ_MASK                                0x1
+#define AFE_SRCCLKENA_REQ_MASK_SFT                            (0x1 << 0)
+
+/* AFE_SPM_CONTROL_ACK */
+#define SPM_RESOURCE_CONTROL_ACK_SFT                          0
+#define SPM_RESOURCE_CONTROL_ACK_MASK                         0xffffffff
+#define SPM_RESOURCE_CONTROL_ACK_MASK_SFT                     (0xffffffff << 0)
+
+/* AUD_TOP_CFG_VCORE_RG */
+#define AUD_TOP_CFG_SFT                                       0
+#define AUD_TOP_CFG_MASK                                      0xffffffff
+#define AUD_TOP_CFG_MASK_SFT                                  (0xffffffff << 0)
+
+/* AUDIO_TOP_IP_VERSION */
+#define AUDIO_TOP_IP_VERSION_SFT                              0
+#define AUDIO_TOP_IP_VERSION_MASK                             0xffffffff
+#define AUDIO_TOP_IP_VERSION_MASK_SFT                         (0xffffffff << 0)
+
+/* AUDIO_ENGEN_CON0_MON */
+#define AUDIO_ENGEN_MON_SFT                                   0
+#define AUDIO_ENGEN_MON_MASK                                  0xffffffff
+#define AUDIO_ENGEN_MON_MASK_SFT                              (0xffffffff << 0)
+
+/* AUD_TOP_CFG_VLP_RG */
+#define I2SIN1_DAT_SEL_SFT                                    31
+#define I2SIN1_DAT_SEL_MASK                                   0x1
+#define I2SIN1_DAT_SEL_MASK_SFT                               (0x1 << 31)
+#define FMI2S_IN_SEL_SFT                                      30
+#define FMI2S_IN_SEL_MASK                                     0x1
+#define FMI2S_IN_SEL_MASK_SFT                                 (0x1 << 30)
+#define RG_I2S4_IN_BCK_NEG_EG_LATCH_SFT                       21
+#define RG_I2S4_IN_BCK_NEG_EG_LATCH_MASK                      0x1
+#define RG_I2S4_IN_BCK_NEG_EG_LATCH_MASK_SFT                  (0x1 << 21)
+#define RG_I2S4_OUT_BCK_NEG_EG_LATCH_SFT                      20
+#define RG_I2S4_OUT_BCK_NEG_EG_LATCH_MASK                     0x1
+#define RG_I2S4_OUT_BCK_NEG_EG_LATCH_MASK_SFT                 (0x1 << 20)
+#define RG_I2S4_IN_SLV_LRCK_LATCH_EDGE_SFT                    19
+#define RG_I2S4_IN_SLV_LRCK_LATCH_EDGE_MASK                   0x1
+#define RG_I2S4_IN_SLV_LRCK_LATCH_EDGE_MASK_SFT               (0x1 << 19)
+#define RG_I2S4_IN_SLV_BCK_INV_SEL_SFT                        18
+#define RG_I2S4_IN_SLV_BCK_INV_SEL_MASK                       0x1
+#define RG_I2S4_IN_SLV_BCK_INV_SEL_MASK_SFT                   (0x1 << 18)
+#define RG_I2S4_OUT_SLV_LRCK_LATCH_EDGE_SFT                   17
+#define RG_I2S4_OUT_SLV_LRCK_LATCH_EDGE_MASK                  0x1
+#define RG_I2S4_OUT_SLV_LRCK_LATCH_EDGE_MASK_SFT              (0x1 << 17)
+#define RG_I2S4_OUT_SLV_BCK_INV_SEL_SFT                       16
+#define RG_I2S4_OUT_SLV_BCK_INV_SEL_MASK                      0x1
+#define RG_I2S4_OUT_SLV_BCK_INV_SEL_MASK_SFT                  (0x1 << 16)
+#define RG_I2S5_IN_BCK_NEG_EG_LATCH_SFT                       13
+#define RG_I2S5_IN_BCK_NEG_EG_LATCH_MASK                      0x1
+#define RG_I2S5_IN_BCK_NEG_EG_LATCH_MASK_SFT                  (0x1 << 13)
+#define RG_I2S5_OUT_BCK_NEG_EG_LATCH_SFT                      12
+#define RG_I2S5_OUT_BCK_NEG_EG_LATCH_MASK                     0x1
+#define RG_I2S5_OUT_BCK_NEG_EG_LATCH_MASK_SFT                 (0x1 << 12)
+#define RG_I2S5_IN_SLV_LRCK_LATCH_EDGE_SFT                    11
+#define RG_I2S5_IN_SLV_LRCK_LATCH_EDGE_MASK                   0x1
+#define RG_I2S5_IN_SLV_LRCK_LATCH_EDGE_MASK_SFT               (0x1 << 11)
+#define RG_I2S5_IN_SLV_BCK_INV_SEL_SFT                        10
+#define RG_I2S5_IN_SLV_BCK_INV_SEL_MASK                       0x1
+#define RG_I2S5_IN_SLV_BCK_INV_SEL_MASK_SFT                   (0x1 << 10)
+#define RG_I2S5_OUT_SLV_LRCK_LATCH_EDGE_SFT                   9
+#define RG_I2S5_OUT_SLV_LRCK_LATCH_EDGE_MASK                  0x1
+#define RG_I2S5_OUT_SLV_LRCK_LATCH_EDGE_MASK_SFT              (0x1 << 9)
+#define RG_I2S5_OUT_SLV_BCK_INV_SEL_SFT                       8
+#define RG_I2S5_OUT_SLV_BCK_INV_SEL_MASK                      0x1
+#define RG_I2S5_OUT_SLV_BCK_INV_SEL_MASK_SFT                  (0x1 << 8)
+#define RG_I2S4_PAD_TOP_CK_EN_SFT                             5
+#define RG_I2S4_PAD_TOP_CK_EN_MASK                            0x1
+#define RG_I2S4_PAD_TOP_CK_EN_MASK_SFT                        (0x1 << 5)
+#define RG_I2S5_PAD_TOP_CK_EN_SFT                             4
+#define RG_I2S5_PAD_TOP_CK_EN_MASK                            0x1
+#define RG_I2S5_PAD_TOP_CK_EN_MASK_SFT                        (0x1 << 4)
+#define RG_TEST_TYPE_SFT                                      2
+#define RG_TEST_TYPE_MASK                                     0x1
+#define RG_TEST_TYPE_MASK_SFT                                 (0x1 << 2)
+#define RG_SW_RESET_SFT                                       1
+#define RG_SW_RESET_MASK                                      0x1
+#define RG_SW_RESET_MASK_SFT                                  (0x1 << 1)
+#define RG_TEST_ON_SFT                                        0
+#define RG_TEST_ON_MASK                                       0x1
+#define RG_TEST_ON_MASK_SFT                                   (0x1 << 0)
+
+/* AUD_TOP_MON_RG */
+#define AUD_TOP_MON_SFT                                       0
+#define AUD_TOP_MON_MASK                                      0xffffffff
+#define AUD_TOP_MON_MASK_SFT                                  (0xffffffff << 0)
+
+/* AUDIO_USE_DEFAULT_DELSEL0 */
+#define USE_DEFAULT_DELSEL_RG_SFT                             0
+#define USE_DEFAULT_DELSEL_RG_MASK                            0xffffffff
+#define USE_DEFAULT_DELSEL_RG_MASK_SFT                        (0xffffffff << 0)
+
+/* AUDIO_USE_DEFAULT_DELSEL1 */
+#define USE_DEFAULT_DELSEL_RG_SFT                             0
+#define USE_DEFAULT_DELSEL_RG_MASK                            0xffffffff
+#define USE_DEFAULT_DELSEL_RG_MASK_SFT                        (0xffffffff << 0)
+
+/* AUDIO_USE_DEFAULT_DELSEL2 */
+#define USE_DEFAULT_DELSEL_RG_SFT                             0
+#define USE_DEFAULT_DELSEL_RG_MASK                            0xffffffff
+#define USE_DEFAULT_DELSEL_RG_MASK_SFT                        (0xffffffff << 0)
+
+/* AFE_CONNSYS_I2S_IPM_VER_MON */
+#define RG_CONNSYS_I2S_IPM_VER_MON_SFT                        0
+#define RG_CONNSYS_I2S_IPM_VER_MON_MASK                       0xffffffff
+#define RG_CONNSYS_I2S_IPM_VER_MON_MASK_SFT                   (0xffffffff << 0)
+
+/* AFE_CONNSYS_I2S_MON_SEL */
+#define RG_CONNSYS_I2S_MON_SEL_SFT                            0
+#define RG_CONNSYS_I2S_MON_SEL_MASK                           0xff
+#define RG_CONNSYS_I2S_MON_SEL_MASK_SFT                       (0xff << 0)
+
+/* AFE_CONNSYS_I2S_MON */
+#define RG_CONNSYS_I2S_MON_SFT                                0
+#define RG_CONNSYS_I2S_MON_MASK                               0xffffffff
+#define RG_CONNSYS_I2S_MON_MASK_SFT                           (0xffffffff << 0)
+
+/* AFE_CONNSYS_I2S_CON */
+#define I2S_SOFT_RST_SFT                                      31
+#define I2S_SOFT_RST_MASK                                     0x1
+#define I2S_SOFT_RST_MASK_SFT                                 (0x1 << 31)
+#define BCK_NEG_EG_LATCH_SFT                                  30
+#define BCK_NEG_EG_LATCH_MASK                                 0x1
+#define BCK_NEG_EG_LATCH_MASK_SFT                             (0x1 << 30)
+#define BCK_INV_SFT                                           29
+#define BCK_INV_MASK                                          0x1
+#define BCK_INV_MASK_SFT                                      (0x1 << 29)
+#define I2SIN_PAD_SEL_SFT                                     28
+#define I2SIN_PAD_SEL_MASK                                    0x1
+#define I2SIN_PAD_SEL_MASK_SFT                                (0x1 << 28)
+#define I2S_LOOPBACK_SFT                                      20
+#define I2S_LOOPBACK_MASK                                     0x1
+#define I2S_LOOPBACK_MASK_SFT                                 (0x1 << 20)
+#define I2S_HDEN_SFT                                          12
+#define I2S_HDEN_MASK                                         0x1
+#define I2S_HDEN_MASK_SFT                                     (0x1 << 12)
+#define I2S_MODE_SFT                                          8
+#define I2S_MODE_MASK                                         0xf
+#define I2S_MODE_MASK_SFT                                     (0xf << 8)
+#define I2S_BYPSRC_SFT                                        6
+#define I2S_BYPSRC_MASK                                       0x1
+#define I2S_BYPSRC_MASK_SFT                                   (0x1 << 6)
+#define INV_LRCK_SFT                                          5
+#define INV_LRCK_MASK                                         0x1
+#define INV_LRCK_MASK_SFT                                     (0x1 << 5)
+#define I2S_FMT_SFT                                           3
+#define I2S_FMT_MASK                                          0x1
+#define I2S_FMT_MASK_SFT                                      (0x1 << 3)
+#define I2S_SRC_SFT                                           2
+#define I2S_SRC_MASK                                          0x1
+#define I2S_SRC_MASK_SFT                                      (0x1 << 2)
+#define I2S_WLEN_SFT                                          1
+#define I2S_WLEN_MASK                                         0x1
+#define I2S_WLEN_MASK_SFT                                     (0x1 << 1)
+#define I2S_EN_SFT                                            0
+#define I2S_EN_MASK                                           0x1
+#define I2S_EN_MASK_SFT                                       (0x1 << 0)
+
+/* AFE_PCM0_INTF_CON0 */
+#define PCM0_HDEN_SFT                                         26
+#define PCM0_HDEN_MASK                                        0x1
+#define PCM0_HDEN_MASK_SFT                                    (0x1 << 26)
+#define PCM0_SYNC_DELSEL_SFT                                  25
+#define PCM0_SYNC_DELSEL_MASK                                 0x1
+#define PCM0_SYNC_DELSEL_MASK_SFT                             (0x1 << 25)
+#define PCM0_TX_LR_SWAP_SFT                                   24
+#define PCM0_TX_LR_SWAP_MASK                                  0x1
+#define PCM0_TX_LR_SWAP_MASK_SFT                              (0x1 << 24)
+#define PCM0_SYNC_OUT_INV_SFT                                 23
+#define PCM0_SYNC_OUT_INV_MASK                                0x1
+#define PCM0_SYNC_OUT_INV_MASK_SFT                            (0x1 << 23)
+#define PCM0_BCLK_OUT_INV_SFT                                 22
+#define PCM0_BCLK_OUT_INV_MASK                                0x1
+#define PCM0_BCLK_OUT_INV_MASK_SFT                            (0x1 << 22)
+#define PCM0_SYNC_IN_INV_SFT                                  21
+#define PCM0_SYNC_IN_INV_MASK                                 0x1
+#define PCM0_SYNC_IN_INV_MASK_SFT                             (0x1 << 21)
+#define PCM0_BCLK_IN_INV_SFT                                  20
+#define PCM0_BCLK_IN_INV_MASK                                 0x1
+#define PCM0_BCLK_IN_INV_MASK_SFT                             (0x1 << 20)
+#define PCM0_TX_LCH_RPT_SFT                                   19
+#define PCM0_TX_LCH_RPT_MASK                                  0x1
+#define PCM0_TX_LCH_RPT_MASK_SFT                              (0x1 << 19)
+#define PCM0_VBT_16K_MODE_SFT                                 18
+#define PCM0_VBT_16K_MODE_MASK                                0x1
+#define PCM0_VBT_16K_MODE_MASK_SFT                            (0x1 << 18)
+#define PCM0_BIT_LENGTH_SFT                                   16
+#define PCM0_BIT_LENGTH_MASK                                  0x3
+#define PCM0_BIT_LENGTH_MASK_SFT                              (0x3 << 16)
+#define PCM0_WLEN_SFT                                         14
+#define PCM0_WLEN_MASK                                        0x3
+#define PCM0_WLEN_MASK_SFT                                    (0x3 << 14)
+#define PCM0_SYNC_LENGTH_SFT                                  9
+#define PCM0_SYNC_LENGTH_MASK                                 0x1f
+#define PCM0_SYNC_LENGTH_MASK_SFT                             (0x1f << 9)
+#define PCM0_SYNC_TYPE_SFT                                    8
+#define PCM0_SYNC_TYPE_MASK                                   0x1
+#define PCM0_SYNC_TYPE_MASK_SFT                               (0x1 << 8)
+#define PCM0_BYP_ASRC_SFT                                     7
+#define PCM0_BYP_ASRC_MASK                                    0x1
+#define PCM0_BYP_ASRC_MASK_SFT                                (0x1 << 7)
+#define PCM0_SLAVE_SFT                                         6
+#define PCM0_SLAVE_MASK                                        0x1
+#define PCM0_SLAVE_MASK_SFT                                    (0x1 << 6)
+#define PCM0_MODE_SFT                                          3
+#define PCM0_MODE_MASK                                         0x7
+#define PCM0_MODE_MASK_SFT                                     (0x7 << 3)
+#define PCM0_FMT_SFT                                           1
+#define PCM0_FMT_MASK                                          0x3
+#define PCM0_FMT_MASK_SFT                                      (0x3 << 1)
+#define PCM0_EN_SFT                                            0
+#define PCM0_EN_MASK                                           0x1
+#define PCM0_EN_MASK_SFT                                       (0x1 << 0)
+
+/* AFE_PCM0_INTF_CON1 */
+#define PCM0_TX_RX_LOOPBACK_SFT                               31
+#define PCM0_TX_RX_LOOPBACK_MASK                              0x1
+#define PCM0_TX_RX_LOOPBACK_MASK_SFT                          (0x1 << 31)
+#define PCM0_BUFFER_LOOPBACK_SFT                              30
+#define PCM0_BUFFER_LOOPBACK_MASK                             0x1
+#define PCM0_BUFFER_LOOPBACK_MASK_SFT                         (0x1 << 30)
+#define PCM0_PARALLEL_LOOPBACK_SFT                            29
+#define PCM0_PARALLEL_LOOPBACK_MASK                           0x1
+#define PCM0_PARALLEL_LOOPBACK_MASK_SFT                       (0x1 << 29)
+#define PCM0_SERIAL_LOOPBACK_SFT                              28
+#define PCM0_SERIAL_LOOPBACK_MASK                             0x1
+#define PCM0_SERIAL_LOOPBACK_MASK_SFT                         (0x1 << 28)
+#define PCM0_DAI_LOOPBACK_SFT                                 27
+#define PCM0_DAI_LOOPBACK_MASK                                0x1
+#define PCM0_DAI_LOOPBACK_MASK_SFT                            (0x1 << 27)
+#define PCM0_I2S_LOOPBACK_SFT                                 26
+#define PCM0_I2S_LOOPBACK_MASK                                0x1
+#define PCM0_I2S_LOOPBACK_MASK_SFT                            (0x1 << 26)
+#define PCM0_1X_EN_DOMAIN_SFT                                 23
+#define PCM0_1X_EN_DOMAIN_MASK                                0x7
+#define PCM0_1X_EN_DOMAIN_MASK_SFT                            (0x7 << 23)
+#define PCM0_1X_EN_MODE_SFT                                   18
+#define PCM0_1X_EN_MODE_MASK                                  0x1f
+#define PCM0_1X_EN_MODE_MASK_SFT                              (0x1f << 18)
+#define PCM0_TX3_RCH_DBG_MODE_SFT                             17
+#define PCM0_TX3_RCH_DBG_MODE_MASK                            0x1
+#define PCM0_TX3_RCH_DBG_MODE_MASK_SFT                        (0x1 << 17)
+#define PCM0_PCM1_LOOPBACK_SFT                                16
+#define PCM0_PCM1_LOOPBACK_MASK                               0x1
+#define PCM0_PCM1_LOOPBACK_MASK_SFT                           (0x1 << 16)
+#define PCM0_LOOPBACK_CH_SEL_SFT                              12
+#define PCM0_LOOPBACK_CH_SEL_MASK                             0x3
+#define PCM0_LOOPBACK_CH_SEL_MASK_SFT                         (0x3 << 12)
+#define PCM0_BT_MODE_SFT                                      11
+#define PCM0_BT_MODE_MASK                                     0x1
+#define PCM0_BT_MODE_MASK_SFT                                 (0x1 << 11)
+#define PCM0_EXT_MODEM_SFT                                    10
+#define PCM0_EXT_MODEM_MASK                                   0x1
+#define PCM0_EXT_MODEM_MASK_SFT                               (0x1 << 10)
+#define PCM0_USE_MD3_SFT                                      9
+#define PCM0_USE_MD3_MASK                                     0x1
+#define PCM0_USE_MD3_MASK_SFT                                 (0x1 << 9)
+#define PCM0_FIX_VALUE_SEL_SFT                                8
+#define PCM0_FIX_VALUE_SEL_MASK                               0x1
+#define PCM0_FIX_VALUE_SEL_MASK_SFT                           (0x1 << 8)
+#define PCM0_TX_FIX_VALUE_SFT                                 0
+#define PCM0_TX_FIX_VALUE_MASK                                0xff
+#define PCM0_TX_FIX_VALUE_MASK_SFT                            (0xff << 0)
+
+/* AFE_PCM_INTF_MON */
+#define PCM0_TX_FIFO_OV_SFT                                   5
+#define PCM0_TX_FIFO_OV_MASK                                  0x1
+#define PCM0_TX_FIFO_OV_MASK_SFT                              (0x1 << 5)
+#define PCM0_RX_FIFO_OV_SFT                                   4
+#define PCM0_RX_FIFO_OV_MASK                                  0x1
+#define PCM0_RX_FIFO_OV_MASK_SFT                              (0x1 << 4)
+#define PCM1_TX_FIFO_OV_SFT                                   3
+#define PCM1_TX_FIFO_OV_MASK                                  0x1
+#define PCM1_TX_FIFO_OV_MASK_SFT                              (0x1 << 3)
+#define PCM1_RX_FIFO_OV_SFT                                   2
+#define PCM1_RX_FIFO_OV_MASK                                  0x1
+#define PCM1_RX_FIFO_OV_MASK_SFT                              (0x1 << 2)
+#define PCM0_SYNC_GLITCH_SFT                                  1
+#define PCM0_SYNC_GLITCH_MASK                                 0x1
+#define PCM0_SYNC_GLITCH_MASK_SFT                             (0x1 << 1)
+#define PCM1_SYNC_GLITCH_SFT                                  0
+#define PCM1_SYNC_GLITCH_MASK                                 0x1
+#define PCM1_SYNC_GLITCH_MASK_SFT                             (0x1 << 0)
+
+/* AFE_PCM1_INTF_CON0 */
+#define PCM1_TX_FIX_VALUE_SFT                                 24
+#define PCM1_TX_FIX_VALUE_MASK                                0xff
+#define PCM1_TX_FIX_VALUE_MASK_SFT                            (0xff << 24)
+#define PCM1_FIX_VALUE_SEL_SFT                                23
+#define PCM1_FIX_VALUE_SEL_MASK                               0x1
+#define PCM1_FIX_VALUE_SEL_MASK_SFT                           (0x1 << 23)
+#define PCM1_BUFFER_LOOPBACK_SFT                              22
+#define PCM1_BUFFER_LOOPBACK_MASK                             0x1
+#define PCM1_BUFFER_LOOPBACK_MASK_SFT                         (0x1 << 22)
+#define PCM1_PARALLEL_LOOPBACK_SFT                            21
+#define PCM1_PARALLEL_LOOPBACK_MASK                           0x1
+#define PCM1_PARALLEL_LOOPBACK_MASK_SFT                       (0x1 << 21)
+#define PCM1_SERIAL_LOOPBACK_SFT                              20
+#define PCM1_SERIAL_LOOPBACK_MASK                             0x1
+#define PCM1_SERIAL_LOOPBACK_MASK_SFT                         (0x1 << 20)
+#define PCM1_DAI_PCM1_LOOPBACK_SFT                            19
+#define PCM1_DAI_PCM1_LOOPBACK_MASK                           0x1
+#define PCM1_DAI_PCM1_LOOPBACK_MASK_SFT                       (0x1 << 19)
+#define PCM1_I2S_PCM1_LOOPBACK_SFT                            18
+#define PCM1_I2S_PCM1_LOOPBACK_MASK                           0x1
+#define PCM1_I2S_PCM1_LOOPBACK_MASK_SFT                       (0x1 << 18)
+#define PCM1_SYNC_DELSEL_SFT                                  17
+#define PCM1_SYNC_DELSEL_MASK                                 0x1
+#define PCM1_SYNC_DELSEL_MASK_SFT                             (0x1 << 17)
+#define PCM1_TX_LR_SWAP_SFT                                   16
+#define PCM1_TX_LR_SWAP_MASK                                  0x1
+#define PCM1_TX_LR_SWAP_MASK_SFT                              (0x1 << 16)
+#define PCM1_SYNC_IN_INV_SFT                                  15
+#define PCM1_SYNC_IN_INV_MASK                                 0x1
+#define PCM1_SYNC_IN_INV_MASK_SFT                             (0x1 << 15)
+#define PCM1_BCLK_IN_INV_SFT                                  14
+#define PCM1_BCLK_IN_INV_MASK                                 0x1
+#define PCM1_BCLK_IN_INV_MASK_SFT                             (0x1 << 14)
+#define PCM1_TX_LCH_RPT_SFT                                   13
+#define PCM1_TX_LCH_RPT_MASK                                  0x1
+#define PCM1_TX_LCH_RPT_MASK_SFT                              (0x1 << 13)
+#define PCM1_VBT_16K_MODE_SFT                                 12
+#define PCM1_VBT_16K_MODE_MASK                                0x1
+#define PCM1_VBT_16K_MODE_MASK_SFT                            (0x1 << 12)
+#define PCM1_LOOPBACK_CH_SEL_SFT                              10
+#define PCM1_LOOPBACK_CH_SEL_MASK                             0x3
+#define PCM1_LOOPBACK_CH_SEL_MASK_SFT                         (0x3 << 10)
+#define PCM1_TX2_BT_MODE_SFT                                  8
+#define PCM1_TX2_BT_MODE_MASK                                 0x1
+#define PCM1_TX2_BT_MODE_MASK_SFT                             (0x1 << 8)
+#define PCM1_BT_MODE_SFT                                      7
+#define PCM1_BT_MODE_MASK                                     0x1
+#define PCM1_BT_MODE_MASK_SFT                                 (0x1 << 7)
+#define PCM1_AFIFO_SFT                                        6
+#define PCM1_AFIFO_MASK                                       0x1
+#define PCM1_AFIFO_MASK_SFT                                   (0x1 << 6)
+#define PCM1_WLEN_SFT                                         5
+#define PCM1_WLEN_MASK                                        0x1
+#define PCM1_WLEN_MASK_SFT                                    (0x1 << 5)
+#define PCM1_MODE_SFT                                         3
+#define PCM1_MODE_MASK                                        0x3
+#define PCM1_MODE_MASK_SFT                                    (0x3 << 3)
+#define PCM1_FMT_SFT                                          1
+#define PCM1_FMT_MASK                                         0x3
+#define PCM1_FMT_MASK_SFT                                     (0x3 << 1)
+#define PCM1_EN_SFT                                           0
+#define PCM1_EN_MASK                                          0x1
+#define PCM1_EN_MASK_SFT                                      (0x1 << 0)
+
+/* AFE_PCM1_INTF_CON1 */
+#define PCM1_1X_EN_DOMAIN_SFT                                 23
+#define PCM1_1X_EN_DOMAIN_MASK                                0x7
+#define PCM1_1X_EN_DOMAIN_MASK_SFT                            (0x7 << 23)
+#define PCM1_1X_EN_MODE_SFT                                   18
+#define PCM1_1X_EN_MODE_MASK                                  0x1f
+#define PCM1_1X_EN_MODE_MASK_SFT                              (0x1f << 18)
+
+/* AFE_PCM_TOP_IP_VERSION */
+#define AFE_PCM_TOP_IP_VERSION_SFT                            0
+#define AFE_PCM_TOP_IP_VERSION_MASK                           0xffffffff
+#define AFE_PCM_TOP_IP_VERSION_MASK_SFT                       (0xffffffff << 0)
+
+/* AFE_IRQ_MCU_EN */
+#define AFE_IRQ_MCU_EN_SFT                                    0
+#define AFE_IRQ_MCU_EN_MASK                                   0xffffffff
+#define AFE_IRQ_MCU_EN_MASK_SFT                               (0xffffffff << 0)
+
+/* AFE_IRQ_MCU_DSP_EN */
+#define AFE_IRQ_DSP_EN_SFT                                    0
+#define AFE_IRQ_DSP_EN_MASK                                   0xffffffff
+#define AFE_IRQ_DSP_EN_MASK_SFT                               (0xffffffff << 0)
+
+/* AFE_IRQ_MCU_DSP2_EN */
+#define AFE_IRQ_DSP2_EN_SFT                                   0
+#define AFE_IRQ_DSP2_EN_MASK                                  0xffffffff
+#define AFE_IRQ_DSP2_EN_MASK_SFT                              (0xffffffff << 0)
+
+/* AFE_IRQ_MCU_SCP_EN */
+#define IRQ31_MCU_SCP_EN_SFT                                  31
+#define IRQ30_MCU_SCP_EN_SFT                                  30
+#define IRQ29_MCU_SCP_EN_SFT                                  29
+#define IRQ28_MCU_SCP_EN_SFT                                  28
+#define IRQ27_MCU_SCP_EN_SFT                                  27
+#define IRQ26_MCU_SCP_EN_SFT                                  26
+#define IRQ25_MCU_SCP_EN_SFT                                  25
+#define IRQ24_MCU_SCP_EN_SFT                                  24
+#define IRQ23_MCU_SCP_EN_SFT                                  23
+#define IRQ22_MCU_SCP_EN_SFT                                  22
+#define IRQ21_MCU_SCP_EN_SFT                                  21
+#define IRQ20_MCU_SCP_EN_SFT                                  20
+#define IRQ19_MCU_SCP_EN_SFT                                  19
+#define IRQ18_MCU_SCP_EN_SFT                                  18
+#define IRQ17_MCU_SCP_EN_SFT                                  17
+#define IRQ16_MCU_SCP_EN_SFT                                  16
+#define IRQ15_MCU_SCP_EN_SFT                                  15
+#define IRQ14_MCU_SCP_EN_SFT                                  14
+#define IRQ13_MCU_SCP_EN_SFT                                  13
+#define IRQ12_MCU_SCP_EN_SFT                                  12
+#define IRQ11_MCU_SCP_EN_SFT                                  11
+#define IRQ10_MCU_SCP_EN_SFT                                  10
+#define IRQ9_MCU_SCP_EN_SFT                                   9
+#define IRQ8_MCU_SCP_EN_SFT                                   8
+#define IRQ7_MCU_SCP_EN_SFT                                   7
+#define IRQ6_MCU_SCP_EN_SFT                                   6
+#define IRQ5_MCU_SCP_EN_SFT                                   5
+#define IRQ4_MCU_SCP_EN_SFT                                   4
+#define IRQ3_MCU_SCP_EN_SFT                                   3
+#define IRQ2_MCU_SCP_EN_SFT                                   2
+#define IRQ1_MCU_SCP_EN_SFT                                   1
+#define IRQ0_MCU_SCP_EN_SFT                                   0
+
+/* AFE_CUSTOM_IRQ_MCU_EN */
+#define AFE_CUSTOM_IRQ_MCU_EN_SFT                             0
+#define AFE_CUSTOM_IRQ_MCU_EN_MASK                            0xffffffff
+#define AFE_CUSTOM_IRQ_MCU_EN_MASK_SFT                        (0xffffffff << 0)
+
+/* AFE_CUSTOM_IRQ_MCU_DSP_EN */
+#define AFE_CUSTOM_IRQ_DSP_EN_SFT                             0
+#define AFE_CUSTOM_IRQ_DSP_EN_MASK                            0xffffffff
+#define AFE_CUSTOM_IRQ_DSP_EN_MASK_SFT                        (0xffffffff << 0)
+
+/* AFE_CUSTOM_IRQ_MCU_DSP2_EN */
+#define AFE_CUSTOM_IRQ_DSP2_EN_SFT                            0
+#define AFE_CUSTOM_IRQ_DSP2_EN_MASK                           0xffffffff
+#define AFE_CUSTOM_IRQ_DSP2_EN_MASK_SFT                       (0xffffffff << 0)
+
+/* AFE_CUSTOM_IRQ_MCU_SCP_EN */
+#define AFE_CUSTOM_IRQ_SCP_EN_SFT                             0
+#define AFE_CUSTOM_IRQ_SCP_EN_MASK                            0xffffffff
+#define AFE_CUSTOM_IRQ_SCP_EN_MASK_SFT                        (0xffffffff << 0)
+
+/* AFE_IRQ_MCU_STATUS */
+#define IRQ26_MCU_SFT                                         26
+#define IRQ26_MCU_MASK                                        0x1
+#define IRQ26_MCU_MASK_SFT                                    (0x1 << 26)
+#define IRQ25_MCU_SFT                                         25
+#define IRQ25_MCU_MASK                                        0x1
+#define IRQ25_MCU_MASK_SFT                                    (0x1 << 25)
+#define IRQ24_MCU_SFT                                         24
+#define IRQ24_MCU_MASK                                        0x1
+#define IRQ24_MCU_MASK_SFT                                    (0x1 << 24)
+#define IRQ23_MCU_SFT                                         23
+#define IRQ23_MCU_MASK                                        0x1
+#define IRQ23_MCU_MASK_SFT                                    (0x1 << 23)
+#define IRQ22_MCU_SFT                                         22
+#define IRQ22_MCU_MASK                                        0x1
+#define IRQ22_MCU_MASK_SFT                                    (0x1 << 22)
+#define IRQ21_MCU_SFT                                         21
+#define IRQ21_MCU_MASK                                        0x1
+#define IRQ21_MCU_MASK_SFT                                    (0x1 << 21)
+#define IRQ20_MCU_SFT                                         20
+#define IRQ20_MCU_MASK                                        0x1
+#define IRQ20_MCU_MASK_SFT                                    (0x1 << 20)
+#define IRQ19_MCU_SFT                                         19
+#define IRQ19_MCU_MASK                                        0x1
+#define IRQ19_MCU_MASK_SFT                                    (0x1 << 19)
+#define IRQ18_MCU_SFT                                         18
+#define IRQ18_MCU_MASK                                        0x1
+#define IRQ18_MCU_MASK_SFT                                    (0x1 << 18)
+#define IRQ17_MCU_SFT                                         17
+#define IRQ17_MCU_MASK                                        0x1
+#define IRQ17_MCU_MASK_SFT                                    (0x1 << 17)
+#define IRQ16_MCU_SFT                                         16
+#define IRQ16_MCU_MASK                                        0x1
+#define IRQ16_MCU_MASK_SFT                                    (0x1 << 16)
+#define IRQ15_MCU_SFT                                         15
+#define IRQ15_MCU_MASK                                        0x1
+#define IRQ15_MCU_MASK_SFT                                    (0x1 << 15)
+#define IRQ14_MCU_SFT                                         14
+#define IRQ14_MCU_MASK                                        0x1
+#define IRQ14_MCU_MASK_SFT                                    (0x1 << 14)
+#define IRQ13_MCU_SFT                                         13
+#define IRQ13_MCU_MASK                                        0x1
+#define IRQ13_MCU_MASK_SFT                                    (0x1 << 13)
+#define IRQ12_MCU_SFT                                         12
+#define IRQ12_MCU_MASK                                        0x1
+#define IRQ12_MCU_MASK_SFT                                    (0x1 << 12)
+#define IRQ11_MCU_SFT                                         11
+#define IRQ11_MCU_MASK                                        0x1
+#define IRQ11_MCU_MASK_SFT                                    (0x1 << 11)
+#define IRQ10_MCU_SFT                                         10
+#define IRQ10_MCU_MASK                                        0x1
+#define IRQ10_MCU_MASK_SFT                                    (0x1 << 10)
+#define IRQ9_MCU_SFT                                          9
+#define IRQ9_MCU_MASK                                         0x1
+#define IRQ9_MCU_MASK_SFT                                     (0x1 << 9)
+#define IRQ8_MCU_SFT                                          8
+#define IRQ8_MCU_MASK                                         0x1
+#define IRQ8_MCU_MASK_SFT                                     (0x1 << 8)
+#define IRQ7_MCU_SFT                                          7
+#define IRQ7_MCU_MASK                                         0x1
+#define IRQ7_MCU_MASK_SFT                                     (0x1 << 7)
+#define IRQ6_MCU_SFT                                          6
+#define IRQ6_MCU_MASK                                         0x1
+#define IRQ6_MCU_MASK_SFT                                     (0x1 << 6)
+#define IRQ5_MCU_SFT                                          5
+#define IRQ5_MCU_MASK                                         0x1
+#define IRQ5_MCU_MASK_SFT                                     (0x1 << 5)
+#define IRQ4_MCU_SFT                                          4
+#define IRQ4_MCU_MASK                                         0x1
+#define IRQ4_MCU_MASK_SFT                                     (0x1 << 4)
+#define IRQ3_MCU_SFT                                          3
+#define IRQ3_MCU_MASK                                         0x1
+#define IRQ3_MCU_MASK_SFT                                     (0x1 << 3)
+#define IRQ2_MCU_SFT                                          2
+#define IRQ2_MCU_MASK                                         0x1
+#define IRQ2_MCU_MASK_SFT                                     (0x1 << 2)
+#define IRQ1_MCU_SFT                                          1
+#define IRQ1_MCU_MASK                                         0x1
+#define IRQ1_MCU_MASK_SFT                                     (0x1 << 1)
+#define IRQ0_MCU_SFT                                          0
+#define IRQ0_MCU_MASK                                         0x1
+#define IRQ0_MCU_MASK_SFT                                     (0x1 << 0)
+
+/* AFE_CUSTOM_IRQ_MCU_STATUS */
+#define CUSTOM_IRQ21_MCU_SFT                                  21
+#define CUSTOM_IRQ21_MCU_MASK                                 0x1
+#define CUSTOM_IRQ21_MCU_MASK_SFT                             (0x1 << 21)
+#define CUSTOM_IRQ20_MCU_SFT                                  20
+#define CUSTOM_IRQ20_MCU_MASK                                 0x1
+#define CUSTOM_IRQ20_MCU_MASK_SFT                             (0x1 << 20)
+#define CUSTOM_IRQ19_MCU_SFT                                  19
+#define CUSTOM_IRQ19_MCU_MASK                                 0x1
+#define CUSTOM_IRQ19_MCU_MASK_SFT                             (0x1 << 19)
+#define CUSTOM_IRQ18_MCU_SFT                                  18
+#define CUSTOM_IRQ18_MCU_MASK                                 0x1
+#define CUSTOM_IRQ18_MCU_MASK_SFT                             (0x1 << 18)
+#define CUSTOM_IRQ17_MCU_SFT                                  17
+#define CUSTOM_IRQ17_MCU_MASK                                 0x1
+#define CUSTOM_IRQ17_MCU_MASK_SFT                             (0x1 << 17)
+#define CUSTOM_IRQ16_MCU_SFT                                  16
+#define CUSTOM_IRQ16_MCU_MASK                                 0x1
+#define CUSTOM_IRQ16_MCU_MASK_SFT                             (0x1 << 16)
+#define CUSTOM_IRQ9_MCU_SFT                                   9
+#define CUSTOM_IRQ9_MCU_MASK                                  0x1
+#define CUSTOM_IRQ9_MCU_MASK_SFT                              (0x1 << 9)
+#define CUSTOM_IRQ8_MCU_SFT                                   8
+#define CUSTOM_IRQ8_MCU_MASK                                  0x1
+#define CUSTOM_IRQ8_MCU_MASK_SFT                              (0x1 << 8)
+#define CUSTOM_IRQ7_MCU_SFT                                   7
+#define CUSTOM_IRQ7_MCU_MASK                                  0x1
+#define CUSTOM_IRQ7_MCU_MASK_SFT                              (0x1 << 7)
+#define CUSTOM_IRQ6_MCU_SFT                                   6
+#define CUSTOM_IRQ6_MCU_MASK                                  0x1
+#define CUSTOM_IRQ6_MCU_MASK_SFT                              (0x1 << 6)
+#define CUSTOM_IRQ5_MCU_SFT                                   5
+#define CUSTOM_IRQ5_MCU_MASK                                  0x1
+#define CUSTOM_IRQ5_MCU_MASK_SFT                              (0x1 << 5)
+#define CUSTOM_IRQ4_MCU_SFT                                   4
+#define CUSTOM_IRQ4_MCU_MASK                                  0x1
+#define CUSTOM_IRQ4_MCU_MASK_SFT                              (0x1 << 4)
+#define CUSTOM_IRQ3_MCU_SFT                                   3
+#define CUSTOM_IRQ3_MCU_MASK                                  0x1
+#define CUSTOM_IRQ3_MCU_MASK_SFT                              (0x1 << 3)
+#define CUSTOM_IRQ2_MCU_SFT                                   2
+#define CUSTOM_IRQ2_MCU_MASK                                  0x1
+#define CUSTOM_IRQ2_MCU_MASK_SFT                              (0x1 << 2)
+#define CUSTOM_IRQ1_MCU_SFT                                   1
+#define CUSTOM_IRQ1_MCU_MASK                                  0x1
+#define CUSTOM_IRQ1_MCU_MASK_SFT                              (0x1 << 1)
+#define CUSTOM_IRQ0_MCU_SFT                                   0
+#define CUSTOM_IRQ0_MCU_MASK                                  0x1
+#define CUSTOM_IRQ0_MCU_MASK_SFT                              (0x1 << 0)
+
+/* AFE_IRQ_MCU_CFG */
+#define AFE_IRQ_CLR_CFG_SFT                                   31
+#define AFE_IRQ_CLR_CFG_MASK                                  0x1
+#define AFE_IRQ_CLR_CFG_MASK_SFT                              (0x1 << 31)
+#define AFE_IRQ_MISS_FLAG_CLR_CFG_SFT                         30
+#define AFE_IRQ_MISS_FLAG_CLR_CFG_MASK                        0x1
+#define AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT                    (0x1 << 30)
+#define AFE_IRQ_MCU_CNT_SFT                                   0
+#define AFE_IRQ_MCU_CNT_MASK                                  0xffffff
+#define AFE_IRQ_MCU_CNT_MASK_SFT                              (0xffffff << 0)
+
+/* AFE_IRQ0_MCU_CFG0 */
+#define AFE_IRQ0_MCU_DOMAIN_SFT                               9
+#define AFE_IRQ0_MCU_DOMAIN_MASK                              0x7
+#define AFE_IRQ0_MCU_DOMAIN_MASK_SFT                          (0x7 << 9)
+#define AFE_IRQ0_MCU_FS_SFT                                   4
+#define AFE_IRQ0_MCU_FS_MASK                                  0x1f
+#define AFE_IRQ0_MCU_FS_MASK_SFT                              (0x1f << 4)
+#define AFE_IRQ0_MCU_ON_SFT                                   0
+#define AFE_IRQ0_MCU_ON_MASK                                  0x1
+#define AFE_IRQ0_MCU_ON_MASK_SFT                              (0x1 << 0)
+
+/* AFE_IRQ0_MCU_CFG1 */
+#define AFE_IRQ0_CLR_CFG_SFT                                  31
+#define AFE_IRQ0_CLR_CFG_MASK                                 0x1
+#define AFE_IRQ0_CLR_CFG_MASK_SFT                             (0x1 << 31)
+#define AFE_IRQ0_MISS_FLAG_CLR_CFG_SFT                        30
+#define AFE_IRQ0_MISS_FLAG_CLR_CFG_MASK                       0x1
+#define AFE_IRQ0_MISS_FLAG_CLR_CFG_MASK_SFT                   (0x1 << 30)
+#define AFE_IRQ0_MCU_CNT_SFT                                  0
+#define AFE_IRQ0_MCU_CNT_MASK                                 0xffffff
+#define AFE_IRQ0_MCU_CNT_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ1_MCU_CFG0 */
+#define AFE_IRQ1_MCU_DOMAIN_SFT                               9
+#define AFE_IRQ1_MCU_DOMAIN_MASK                              0x7
+#define AFE_IRQ1_MCU_DOMAIN_MASK_SFT                          (0x7 << 9)
+#define AFE_IRQ1_MCU_FS_SFT                                   4
+#define AFE_IRQ1_MCU_FS_MASK                                  0x1f
+#define AFE_IRQ1_MCU_FS_MASK_SFT                              (0x1f << 4)
+#define AFE_IRQ1_MCU_ON_SFT                                   0
+#define AFE_IRQ1_MCU_ON_MASK                                  0x1
+#define AFE_IRQ1_MCU_ON_MASK_SFT                              (0x1 << 0)
+
+/* AFE_IRQ1_MCU_CFG1 */
+#define AFE_IRQ1_CLR_CFG_SFT                                  31
+#define AFE_IRQ1_CLR_CFG_MASK                                 0x1
+#define AFE_IRQ1_CLR_CFG_MASK_SFT                             (0x1 << 31)
+#define AFE_IRQ1_MISS_FLAG_CLR_CFG_SFT                        30
+#define AFE_IRQ1_MISS_FLAG_CLR_CFG_MASK                       0x1
+#define AFE_IRQ1_MISS_FLAG_CLR_CFG_MASK_SFT                   (0x1 << 30)
+#define AFE_IRQ1_MCU_CNT_SFT                                  0
+#define AFE_IRQ1_MCU_CNT_MASK                                 0xffffff
+#define AFE_IRQ1_MCU_CNT_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ2_MCU_CFG0 */
+#define AFE_IRQ2_MCU_DOMAIN_SFT                               9
+#define AFE_IRQ2_MCU_DOMAIN_MASK                              0x7
+#define AFE_IRQ2_MCU_DOMAIN_MASK_SFT                          (0x7 << 9)
+#define AFE_IRQ2_MCU_FS_SFT                                   4
+#define AFE_IRQ2_MCU_FS_MASK                                  0x1f
+#define AFE_IRQ2_MCU_FS_MASK_SFT                              (0x1f << 4)
+#define AFE_IRQ2_MCU_ON_SFT                                   0
+#define AFE_IRQ2_MCU_ON_MASK                                  0x1
+#define AFE_IRQ2_MCU_ON_MASK_SFT                              (0x1 << 0)
+
+/* AFE_IRQ2_MCU_CFG1 */
+#define AFE_IRQ2_CLR_CFG_SFT                                  31
+#define AFE_IRQ2_CLR_CFG_MASK                                 0x1
+#define AFE_IRQ2_CLR_CFG_MASK_SFT                             (0x1 << 31)
+#define AFE_IRQ2_MISS_FLAG_CLR_CFG_SFT                        30
+#define AFE_IRQ2_MISS_FLAG_CLR_CFG_MASK                       0x1
+#define AFE_IRQ2_MISS_FLAG_CLR_CFG_MASK_SFT                   (0x1 << 30)
+#define AFE_IRQ2_MCU_CNT_SFT                                  0
+#define AFE_IRQ2_MCU_CNT_MASK                                 0xffffff
+#define AFE_IRQ2_MCU_CNT_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ3_MCU_CFG0 */
+#define AFE_IRQ3_MCU_DOMAIN_SFT                               9
+#define AFE_IRQ3_MCU_DOMAIN_MASK                              0x7
+#define AFE_IRQ3_MCU_DOMAIN_MASK_SFT                          (0x7 << 9)
+#define AFE_IRQ3_MCU_FS_SFT                                   4
+#define AFE_IRQ3_MCU_FS_MASK                                  0x1f
+#define AFE_IRQ3_MCU_FS_MASK_SFT                              (0x1f << 4)
+#define AFE_IRQ3_MCU_ON_SFT                                   0
+#define AFE_IRQ3_MCU_ON_MASK                                  0x1
+#define AFE_IRQ3_MCU_ON_MASK_SFT                              (0x1 << 0)
+
+/* AFE_IRQ3_MCU_CFG1 */
+#define AFE_IRQ3_CLR_CFG_SFT                                  31
+#define AFE_IRQ3_CLR_CFG_MASK                                 0x1
+#define AFE_IRQ3_CLR_CFG_MASK_SFT                             (0x1 << 31)
+#define AFE_IRQ3_MISS_FLAG_CLR_CFG_SFT                        30
+#define AFE_IRQ3_MISS_FLAG_CLR_CFG_MASK                       0x1
+#define AFE_IRQ3_MISS_FLAG_CLR_CFG_MASK_SFT                   (0x1 << 30)
+#define AFE_IRQ3_MCU_CNT_SFT                                  0
+#define AFE_IRQ3_MCU_CNT_MASK                                 0xffffff
+#define AFE_IRQ3_MCU_CNT_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ4_MCU_CFG0 */
+#define AFE_IRQ4_MCU_DOMAIN_SFT                               9
+#define AFE_IRQ4_MCU_DOMAIN_MASK                              0x7
+#define AFE_IRQ4_MCU_DOMAIN_MASK_SFT                          (0x7 << 9)
+#define AFE_IRQ4_MCU_FS_SFT                                   4
+#define AFE_IRQ4_MCU_FS_MASK                                  0x1f
+#define AFE_IRQ4_MCU_FS_MASK_SFT                              (0x1f << 4)
+#define AFE_IRQ4_MCU_ON_SFT                                   0
+#define AFE_IRQ4_MCU_ON_MASK                                  0x1
+#define AFE_IRQ4_MCU_ON_MASK_SFT                              (0x1 << 0)
+
+/* AFE_IRQ4_MCU_CFG1 */
+#define AFE_IRQ4_CLR_CFG_SFT                                  31
+#define AFE_IRQ4_CLR_CFG_MASK                                 0x1
+#define AFE_IRQ4_CLR_CFG_MASK_SFT                             (0x1 << 31)
+#define AFE_IRQ4_MISS_FLAG_CLR_CFG_SFT                        30
+#define AFE_IRQ4_MISS_FLAG_CLR_CFG_MASK                       0x1
+#define AFE_IRQ4_MISS_FLAG_CLR_CFG_MASK_SFT                   (0x1 << 30)
+#define AFE_IRQ4_MCU_CNT_SFT                                  0
+#define AFE_IRQ4_MCU_CNT_MASK                                 0xffffff
+#define AFE_IRQ4_MCU_CNT_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ5_MCU_CFG0 */
+#define AFE_IRQ5_MCU_DOMAIN_SFT                               9
+#define AFE_IRQ5_MCU_DOMAIN_MASK                              0x7
+#define AFE_IRQ5_MCU_DOMAIN_MASK_SFT                          (0x7 << 9)
+#define AFE_IRQ5_MCU_FS_SFT                                   4
+#define AFE_IRQ5_MCU_FS_MASK                                  0x1f
+#define AFE_IRQ5_MCU_FS_MASK_SFT                              (0x1f << 4)
+#define AFE_IRQ5_MCU_ON_SFT                                   0
+#define AFE_IRQ5_MCU_ON_MASK                                  0x1
+#define AFE_IRQ5_MCU_ON_MASK_SFT                              (0x1 << 0)
+
+/* AFE_IRQ5_MCU_CFG1 */
+#define AFE_IRQ5_CLR_CFG_SFT                                  31
+#define AFE_IRQ5_CLR_CFG_MASK                                 0x1
+#define AFE_IRQ5_CLR_CFG_MASK_SFT                             (0x1 << 31)
+#define AFE_IRQ5_MISS_FLAG_CLR_CFG_SFT                        30
+#define AFE_IRQ5_MISS_FLAG_CLR_CFG_MASK                       0x1
+#define AFE_IRQ5_MISS_FLAG_CLR_CFG_MASK_SFT                   (0x1 << 30)
+#define AFE_IRQ5_MCU_CNT_SFT                                  0
+#define AFE_IRQ5_MCU_CNT_MASK                                 0xffffff
+#define AFE_IRQ5_MCU_CNT_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ6_MCU_CFG0 */
+#define AFE_IRQ6_MCU_DOMAIN_SFT                               9
+#define AFE_IRQ6_MCU_DOMAIN_MASK                              0x7
+#define AFE_IRQ6_MCU_DOMAIN_MASK_SFT                          (0x7 << 9)
+#define AFE_IRQ6_MCU_FS_SFT                                   4
+#define AFE_IRQ6_MCU_FS_MASK                                  0x1f
+#define AFE_IRQ6_MCU_FS_MASK_SFT                              (0x1f << 4)
+#define AFE_IRQ6_MCU_ON_SFT                                   0
+#define AFE_IRQ6_MCU_ON_MASK                                  0x1
+#define AFE_IRQ6_MCU_ON_MASK_SFT                              (0x1 << 0)
+
+/* AFE_IRQ6_MCU_CFG1 */
+#define AFE_IRQ6_CLR_CFG_SFT                                  31
+#define AFE_IRQ6_CLR_CFG_MASK                                 0x1
+#define AFE_IRQ6_CLR_CFG_MASK_SFT                             (0x1 << 31)
+#define AFE_IRQ6_MISS_FLAG_CLR_CFG_SFT                        30
+#define AFE_IRQ6_MISS_FLAG_CLR_CFG_MASK                       0x1
+#define AFE_IRQ6_MISS_FLAG_CLR_CFG_MASK_SFT                   (0x1 << 30)
+#define AFE_IRQ6_MCU_CNT_SFT                                  0
+#define AFE_IRQ6_MCU_CNT_MASK                                 0xffffff
+#define AFE_IRQ6_MCU_CNT_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ7_MCU_CFG0 */
+#define AFE_IRQ7_MCU_DOMAIN_SFT                               9
+#define AFE_IRQ7_MCU_DOMAIN_MASK                              0x7
+#define AFE_IRQ7_MCU_DOMAIN_MASK_SFT                          (0x7 << 9)
+#define AFE_IRQ7_MCU_FS_SFT                                   4
+#define AFE_IRQ7_MCU_FS_MASK                                  0x1f
+#define AFE_IRQ7_MCU_FS_MASK_SFT                              (0x1f << 4)
+#define AFE_IRQ7_MCU_ON_SFT                                   0
+#define AFE_IRQ7_MCU_ON_MASK                                  0x1
+#define AFE_IRQ7_MCU_ON_MASK_SFT                              (0x1 << 0)
+
+/* AFE_IRQ7_MCU_CFG1 */
+#define AFE_IRQ7_CLR_CFG_SFT                                  31
+#define AFE_IRQ7_CLR_CFG_MASK                                 0x1
+#define AFE_IRQ7_CLR_CFG_MASK_SFT                             (0x1 << 31)
+#define AFE_IRQ7_MISS_FLAG_CLR_CFG_SFT                        30
+#define AFE_IRQ7_MISS_FLAG_CLR_CFG_MASK                       0x1
+#define AFE_IRQ7_MISS_FLAG_CLR_CFG_MASK_SFT                   (0x1 << 30)
+#define AFE_IRQ7_MCU_CNT_SFT                                  0
+#define AFE_IRQ7_MCU_CNT_MASK                                 0xffffff
+#define AFE_IRQ7_MCU_CNT_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ8_MCU_CFG0 */
+#define AFE_IRQ8_MCU_DOMAIN_SFT                               9
+#define AFE_IRQ8_MCU_DOMAIN_MASK                              0x7
+#define AFE_IRQ8_MCU_DOMAIN_MASK_SFT                          (0x7 << 9)
+#define AFE_IRQ8_MCU_FS_SFT                                   4
+#define AFE_IRQ8_MCU_FS_MASK                                  0x1f
+#define AFE_IRQ8_MCU_FS_MASK_SFT                              (0x1f << 4)
+#define AFE_IRQ8_MCU_ON_SFT                                   0
+#define AFE_IRQ8_MCU_ON_MASK                                  0x1
+#define AFE_IRQ8_MCU_ON_MASK_SFT                              (0x1 << 0)
+
+/* AFE_IRQ8_MCU_CFG1 */
+#define AFE_IRQ8_CLR_CFG_SFT                                  31
+#define AFE_IRQ8_CLR_CFG_MASK                                 0x1
+#define AFE_IRQ8_CLR_CFG_MASK_SFT                             (0x1 << 31)
+#define AFE_IRQ8_MISS_FLAG_CLR_CFG_SFT                        30
+#define AFE_IRQ8_MISS_FLAG_CLR_CFG_MASK                       0x1
+#define AFE_IRQ8_MISS_FLAG_CLR_CFG_MASK_SFT                   (0x1 << 30)
+#define AFE_IRQ8_MCU_CNT_SFT                                  0
+#define AFE_IRQ8_MCU_CNT_MASK                                 0xffffff
+#define AFE_IRQ8_MCU_CNT_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ9_MCU_CFG0 */
+#define AFE_IRQ9_MCU_DOMAIN_SFT                               9
+#define AFE_IRQ9_MCU_DOMAIN_MASK                              0x7
+#define AFE_IRQ9_MCU_DOMAIN_MASK_SFT                          (0x7 << 9)
+#define AFE_IRQ9_MCU_FS_SFT                                   4
+#define AFE_IRQ9_MCU_FS_MASK                                  0x1f
+#define AFE_IRQ9_MCU_FS_MASK_SFT                              (0x1f << 4)
+#define AFE_IRQ9_MCU_ON_SFT                                   0
+#define AFE_IRQ9_MCU_ON_MASK                                  0x1
+#define AFE_IRQ9_MCU_ON_MASK_SFT                              (0x1 << 0)
+
+/* AFE_IRQ9_MCU_CFG1 */
+#define AFE_IRQ9_CLR_CFG_SFT                                  31
+#define AFE_IRQ9_CLR_CFG_MASK                                 0x1
+#define AFE_IRQ9_CLR_CFG_MASK_SFT                             (0x1 << 31)
+#define AFE_IRQ9_MISS_FLAG_CLR_CFG_SFT                        30
+#define AFE_IRQ9_MISS_FLAG_CLR_CFG_MASK                       0x1
+#define AFE_IRQ9_MISS_FLAG_CLR_CFG_MASK_SFT                   (0x1 << 30)
+#define AFE_IRQ9_MCU_CNT_SFT                                  0
+#define AFE_IRQ9_MCU_CNT_MASK                                 0xffffff
+#define AFE_IRQ9_MCU_CNT_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ10_MCU_CFG0 */
+#define AFE_IRQ10_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ10_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ10_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ10_MCU_FS_SFT                                  4
+#define AFE_IRQ10_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ10_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ10_MCU_ON_SFT                                  0
+#define AFE_IRQ10_MCU_ON_MASK                                 0x1
+#define AFE_IRQ10_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ10_MCU_CFG1 */
+#define AFE_IRQ10_CLR_CFG_SFT                                 31
+#define AFE_IRQ10_CLR_CFG_MASK                                0x1
+#define AFE_IRQ10_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ10_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ10_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ10_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ10_MCU_CNT_SFT                                 0
+#define AFE_IRQ10_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ10_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ11_MCU_CFG0 */
+#define AFE_IRQ11_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ11_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ11_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ11_MCU_FS_SFT                                  4
+#define AFE_IRQ11_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ11_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ11_MCU_ON_SFT                                  0
+#define AFE_IRQ11_MCU_ON_MASK                                 0x1
+#define AFE_IRQ11_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ11_MCU_CFG1 */
+#define AFE_IRQ11_CLR_CFG_SFT                                 31
+#define AFE_IRQ11_CLR_CFG_MASK                                0x1
+#define AFE_IRQ11_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ11_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ11_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ11_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ11_MCU_CNT_SFT                                 0
+#define AFE_IRQ11_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ11_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ12_MCU_CFG0 */
+#define AFE_IRQ12_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ12_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ12_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ12_MCU_FS_SFT                                  4
+#define AFE_IRQ12_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ12_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ12_MCU_ON_SFT                                  0
+#define AFE_IRQ12_MCU_ON_MASK                                 0x1
+#define AFE_IRQ12_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ12_MCU_CFG1 */
+#define AFE_IRQ12_CLR_CFG_SFT                                 31
+#define AFE_IRQ12_CLR_CFG_MASK                                0x1
+#define AFE_IRQ12_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ12_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ12_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ12_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ12_MCU_CNT_SFT                                 0
+#define AFE_IRQ12_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ12_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ13_MCU_CFG0 */
+#define AFE_IRQ13_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ13_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ13_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ13_MCU_FS_SFT                                  4
+#define AFE_IRQ13_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ13_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ13_MCU_ON_SFT                                  0
+#define AFE_IRQ13_MCU_ON_MASK                                 0x1
+#define AFE_IRQ13_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ13_MCU_CFG1 */
+#define AFE_IRQ13_CLR_CFG_SFT                                 31
+#define AFE_IRQ13_CLR_CFG_MASK                                0x1
+#define AFE_IRQ13_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ13_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ13_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ13_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ13_MCU_CNT_SFT                                 0
+#define AFE_IRQ13_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ13_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ14_MCU_CFG0 */
+#define AFE_IRQ14_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ14_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ14_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ14_MCU_FS_SFT                                  4
+#define AFE_IRQ14_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ14_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ14_MCU_ON_SFT                                  0
+#define AFE_IRQ14_MCU_ON_MASK                                 0x1
+#define AFE_IRQ14_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ14_MCU_CFG1 */
+#define AFE_IRQ14_CLR_CFG_SFT                                 31
+#define AFE_IRQ14_CLR_CFG_MASK                                0x1
+#define AFE_IRQ14_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ14_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ14_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ14_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ14_MCU_CNT_SFT                                 0
+#define AFE_IRQ14_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ14_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ15_MCU_CFG0 */
+#define AFE_IRQ15_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ15_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ15_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ15_MCU_FS_SFT                                  4
+#define AFE_IRQ15_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ15_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ15_MCU_ON_SFT                                  0
+#define AFE_IRQ15_MCU_ON_MASK                                 0x1
+#define AFE_IRQ15_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ15_MCU_CFG1 */
+#define AFE_IRQ15_CLR_CFG_SFT                                 31
+#define AFE_IRQ15_CLR_CFG_MASK                                0x1
+#define AFE_IRQ15_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ15_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ15_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ15_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ15_MCU_CNT_SFT                                 0
+#define AFE_IRQ15_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ15_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ16_MCU_CFG0 */
+#define AFE_IRQ16_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ16_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ16_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ16_MCU_FS_SFT                                  4
+#define AFE_IRQ16_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ16_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ16_MCU_ON_SFT                                  0
+#define AFE_IRQ16_MCU_ON_MASK                                 0x1
+#define AFE_IRQ16_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ16_MCU_CFG1 */
+#define AFE_IRQ16_CLR_CFG_SFT                                 31
+#define AFE_IRQ16_CLR_CFG_MASK                                0x1
+#define AFE_IRQ16_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ16_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ16_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ16_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ16_MCU_CNT_SFT                                 0
+#define AFE_IRQ16_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ16_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ17_MCU_CFG0 */
+#define AFE_IRQ17_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ17_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ17_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ17_MCU_FS_SFT                                  4
+#define AFE_IRQ17_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ17_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ17_MCU_ON_SFT                                  0
+#define AFE_IRQ17_MCU_ON_MASK                                 0x1
+#define AFE_IRQ17_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ17_MCU_CFG1 */
+#define AFE_IRQ17_CLR_CFG_SFT                                 31
+#define AFE_IRQ17_CLR_CFG_MASK                                0x1
+#define AFE_IRQ17_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ17_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ17_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ17_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ17_MCU_CNT_SFT                                 0
+#define AFE_IRQ17_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ17_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ18_MCU_CFG0 */
+#define AFE_IRQ18_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ18_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ18_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ18_MCU_FS_SFT                                  4
+#define AFE_IRQ18_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ18_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ18_MCU_ON_SFT                                  0
+#define AFE_IRQ18_MCU_ON_MASK                                 0x1
+#define AFE_IRQ18_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ18_MCU_CFG1 */
+#define AFE_IRQ18_CLR_CFG_SFT                                 31
+#define AFE_IRQ18_CLR_CFG_MASK                                0x1
+#define AFE_IRQ18_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ18_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ18_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ18_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ18_MCU_CNT_SFT                                 0
+#define AFE_IRQ18_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ18_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ19_MCU_CFG0 */
+#define AFE_IRQ19_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ19_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ19_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ19_MCU_FS_SFT                                  4
+#define AFE_IRQ19_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ19_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ19_MCU_ON_SFT                                  0
+#define AFE_IRQ19_MCU_ON_MASK                                 0x1
+#define AFE_IRQ19_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ19_MCU_CFG1 */
+#define AFE_IRQ19_CLR_CFG_SFT                                 31
+#define AFE_IRQ19_CLR_CFG_MASK                                0x1
+#define AFE_IRQ19_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ19_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ19_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ19_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ19_MCU_CNT_SFT                                 0
+#define AFE_IRQ19_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ19_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ20_MCU_CFG0 */
+#define AFE_IRQ20_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ20_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ20_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ20_MCU_FS_SFT                                  4
+#define AFE_IRQ20_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ20_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ20_MCU_ON_SFT                                  0
+#define AFE_IRQ20_MCU_ON_MASK                                 0x1
+#define AFE_IRQ20_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ20_MCU_CFG1 */
+#define AFE_IRQ20_CLR_CFG_SFT                                 31
+#define AFE_IRQ20_CLR_CFG_MASK                                0x1
+#define AFE_IRQ20_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ20_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ20_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ20_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ20_MCU_CNT_SFT                                 0
+#define AFE_IRQ20_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ20_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ21_MCU_CFG0 */
+#define AFE_IRQ21_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ21_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ21_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ21_MCU_FS_SFT                                  4
+#define AFE_IRQ21_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ21_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ21_MCU_ON_SFT                                  0
+#define AFE_IRQ21_MCU_ON_MASK                                 0x1
+#define AFE_IRQ21_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ21_MCU_CFG1 */
+#define AFE_IRQ21_CLR_CFG_SFT                                 31
+#define AFE_IRQ21_CLR_CFG_MASK                                0x1
+#define AFE_IRQ21_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ21_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ21_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ21_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ21_MCU_CNT_SFT                                 0
+#define AFE_IRQ21_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ21_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ22_MCU_CFG0 */
+#define AFE_IRQ22_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ22_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ22_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ22_MCU_FS_SFT                                  4
+#define AFE_IRQ22_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ22_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ22_MCU_ON_SFT                                  0
+#define AFE_IRQ22_MCU_ON_MASK                                 0x1
+#define AFE_IRQ22_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ22_MCU_CFG1 */
+#define AFE_IRQ22_CLR_CFG_SFT                                 31
+#define AFE_IRQ22_CLR_CFG_MASK                                0x1
+#define AFE_IRQ22_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ22_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ22_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ22_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ22_MCU_CNT_SFT                                 0
+#define AFE_IRQ22_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ22_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ23_MCU_CFG0 */
+#define AFE_IRQ23_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ23_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ23_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ23_MCU_FS_SFT                                  4
+#define AFE_IRQ23_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ23_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ23_MCU_ON_SFT                                  0
+#define AFE_IRQ23_MCU_ON_MASK                                 0x1
+#define AFE_IRQ23_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ23_MCU_CFG1 */
+#define AFE_IRQ23_CLR_CFG_SFT                                 31
+#define AFE_IRQ23_CLR_CFG_MASK                                0x1
+#define AFE_IRQ23_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ23_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ23_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ23_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ23_MCU_CNT_SFT                                 0
+#define AFE_IRQ23_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ23_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ24_MCU_CFG0 */
+#define AFE_IRQ24_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ24_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ24_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ24_MCU_FS_SFT                                  4
+#define AFE_IRQ24_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ24_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ24_MCU_ON_SFT                                  0
+#define AFE_IRQ24_MCU_ON_MASK                                 0x1
+#define AFE_IRQ24_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ24_MCU_CFG1 */
+#define AFE_IRQ24_CLR_CFG_SFT                                 31
+#define AFE_IRQ24_CLR_CFG_MASK                                0x1
+#define AFE_IRQ24_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ24_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ24_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ24_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ24_MCU_CNT_SFT                                 0
+#define AFE_IRQ24_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ24_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ25_MCU_CFG0 */
+#define AFE_IRQ25_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ25_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ25_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ25_MCU_FS_SFT                                  4
+#define AFE_IRQ25_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ25_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ25_MCU_ON_SFT                                  0
+#define AFE_IRQ25_MCU_ON_MASK                                 0x1
+#define AFE_IRQ25_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ25_MCU_CFG1 */
+#define AFE_IRQ25_CLR_CFG_SFT                                 31
+#define AFE_IRQ25_CLR_CFG_MASK                                0x1
+#define AFE_IRQ25_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ25_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ25_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ25_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ25_MCU_CNT_SFT                                 0
+#define AFE_IRQ25_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ25_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ26_MCU_CFG0 */
+#define AFE_IRQ26_MCU_DOMAIN_SFT                              9
+#define AFE_IRQ26_MCU_DOMAIN_MASK                             0x7
+#define AFE_IRQ26_MCU_DOMAIN_MASK_SFT                         (0x7 << 9)
+#define AFE_IRQ26_MCU_FS_SFT                                  4
+#define AFE_IRQ26_MCU_FS_MASK                                 0x1f
+#define AFE_IRQ26_MCU_FS_MASK_SFT                             (0x1f << 4)
+#define AFE_IRQ26_MCU_ON_SFT                                  0
+#define AFE_IRQ26_MCU_ON_MASK                                 0x1
+#define AFE_IRQ26_MCU_ON_MASK_SFT                             (0x1 << 0)
+
+/* AFE_IRQ26_MCU_CFG1 */
+#define AFE_IRQ26_CLR_CFG_SFT                                 31
+#define AFE_IRQ26_CLR_CFG_MASK                                0x1
+#define AFE_IRQ26_CLR_CFG_MASK_SFT                            (0x1 << 31)
+#define AFE_IRQ26_MISS_FLAG_CLR_CFG_SFT                       30
+#define AFE_IRQ26_MISS_FLAG_CLR_CFG_MASK                      0x1
+#define AFE_IRQ26_MISS_FLAG_CLR_CFG_MASK_SFT                  (0x1 << 30)
+#define AFE_IRQ26_MCU_CNT_SFT                                 0
+#define AFE_IRQ26_MCU_CNT_MASK                                0xffffff
+#define AFE_IRQ26_MCU_CNT_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_CUSTOM_IRQ0_MCU_CFG0 */
+#define AFE_CUSTOM_IRQ0_MCU_ON_SFT                            0
+#define AFE_CUSTOM_IRQ0_MCU_ON_MASK                           0x1
+#define AFE_CUSTOM_IRQ0_MCU_ON_MASK_SFT                       (0x1 << 0)
+
+/* AFE_IRQ_MCU_MON0 */
+#define AFE_IRQ26_MISS_FLAG_SFT                               26
+#define AFE_IRQ26_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ26_MISS_FLAG_MASK_SFT                          (0x1 << 26)
+#define AFE_IRQ25_MISS_FLAG_SFT                               25
+#define AFE_IRQ25_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ25_MISS_FLAG_MASK_SFT                          (0x1 << 25)
+#define AFE_IRQ24_MISS_FLAG_SFT                               24
+#define AFE_IRQ24_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ24_MISS_FLAG_MASK_SFT                          (0x1 << 24)
+#define AFE_IRQ23_MISS_FLAG_SFT                               23
+#define AFE_IRQ23_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ23_MISS_FLAG_MASK_SFT                          (0x1 << 23)
+#define AFE_IRQ22_MISS_FLAG_SFT                               22
+#define AFE_IRQ22_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ22_MISS_FLAG_MASK_SFT                          (0x1 << 22)
+#define AFE_IRQ21_MISS_FLAG_SFT                               21
+#define AFE_IRQ21_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ21_MISS_FLAG_MASK_SFT                          (0x1 << 21)
+#define AFE_IRQ20_MISS_FLAG_SFT                               20
+#define AFE_IRQ20_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ20_MISS_FLAG_MASK_SFT                          (0x1 << 20)
+#define AFE_IRQ19_MISS_FLAG_SFT                               19
+#define AFE_IRQ19_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ19_MISS_FLAG_MASK_SFT                          (0x1 << 19)
+#define AFE_IRQ18_MISS_FLAG_SFT                               18
+#define AFE_IRQ18_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ18_MISS_FLAG_MASK_SFT                          (0x1 << 18)
+#define AFE_IRQ17_MISS_FLAG_SFT                               17
+#define AFE_IRQ17_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ17_MISS_FLAG_MASK_SFT                          (0x1 << 17)
+#define AFE_IRQ16_MISS_FLAG_SFT                               16
+#define AFE_IRQ16_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ16_MISS_FLAG_MASK_SFT                          (0x1 << 16)
+#define AFE_IRQ15_MISS_FLAG_SFT                               15
+#define AFE_IRQ15_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ15_MISS_FLAG_MASK_SFT                          (0x1 << 15)
+#define AFE_IRQ14_MISS_FLAG_SFT                               14
+#define AFE_IRQ14_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ14_MISS_FLAG_MASK_SFT                          (0x1 << 14)
+#define AFE_IRQ13_MISS_FLAG_SFT                               13
+#define AFE_IRQ13_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ13_MISS_FLAG_MASK_SFT                          (0x1 << 13)
+#define AFE_IRQ12_MISS_FLAG_SFT                               12
+#define AFE_IRQ12_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ12_MISS_FLAG_MASK_SFT                          (0x1 << 12)
+#define AFE_IRQ11_MISS_FLAG_SFT                               11
+#define AFE_IRQ11_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ11_MISS_FLAG_MASK_SFT                          (0x1 << 11)
+#define AFE_IRQ10_MISS_FLAG_SFT                               10
+#define AFE_IRQ10_MISS_FLAG_MASK                              0x1
+#define AFE_IRQ10_MISS_FLAG_MASK_SFT                          (0x1 << 10)
+#define AFE_IRQ9_MISS_FLAG_SFT                                9
+#define AFE_IRQ9_MISS_FLAG_MASK                               0x1
+#define AFE_IRQ9_MISS_FLAG_MASK_SFT                           (0x1 << 9)
+#define AFE_IRQ8_MISS_FLAG_SFT                                8
+#define AFE_IRQ8_MISS_FLAG_MASK                               0x1
+#define AFE_IRQ8_MISS_FLAG_MASK_SFT                           (0x1 << 8)
+#define AFE_IRQ7_MISS_FLAG_SFT                                7
+#define AFE_IRQ7_MISS_FLAG_MASK                               0x1
+#define AFE_IRQ7_MISS_FLAG_MASK_SFT                           (0x1 << 7)
+#define AFE_IRQ6_MISS_FLAG_SFT                                6
+#define AFE_IRQ6_MISS_FLAG_MASK                               0x1
+#define AFE_IRQ6_MISS_FLAG_MASK_SFT                           (0x1 << 6)
+#define AFE_IRQ5_MISS_FLAG_SFT                                5
+#define AFE_IRQ5_MISS_FLAG_MASK                               0x1
+#define AFE_IRQ5_MISS_FLAG_MASK_SFT                           (0x1 << 5)
+#define AFE_IRQ4_MISS_FLAG_SFT                                4
+#define AFE_IRQ4_MISS_FLAG_MASK                               0x1
+#define AFE_IRQ4_MISS_FLAG_MASK_SFT                           (0x1 << 4)
+#define AFE_IRQ3_MISS_FLAG_SFT                                3
+#define AFE_IRQ3_MISS_FLAG_MASK                               0x1
+#define AFE_IRQ3_MISS_FLAG_MASK_SFT                           (0x1 << 3)
+#define AFE_IRQ2_MISS_FLAG_SFT                                2
+#define AFE_IRQ2_MISS_FLAG_MASK                               0x1
+#define AFE_IRQ2_MISS_FLAG_MASK_SFT                           (0x1 << 2)
+#define AFE_IRQ1_MISS_FLAG_SFT                                1
+#define AFE_IRQ1_MISS_FLAG_MASK                               0x1
+#define AFE_IRQ1_MISS_FLAG_MASK_SFT                           (0x1 << 1)
+#define AFE_IRQ0_MISS_FLAG_SFT                                0
+#define AFE_IRQ0_MISS_FLAG_MASK                               0x1
+#define AFE_IRQ0_MISS_FLAG_MASK_SFT                           (0x1 << 0)
+
+/* AFE_IRQ_MCU_MON1 */
+#define AFE_CUSTOM_IRQ21_MISS_FLAG_SFT                        21
+#define AFE_CUSTOM_IRQ21_MISS_FLAG_MASK                       0x1
+#define AFE_CUSTOM_IRQ21_MISS_FLAG_MASK_SFT                   (0x1 << 21)
+#define AFE_CUSTOM_IRQ20_MISS_FLAG_SFT                        20
+#define AFE_CUSTOM_IRQ20_MISS_FLAG_MASK                       0x1
+#define AFE_CUSTOM_IRQ20_MISS_FLAG_MASK_SFT                   (0x1 << 20)
+#define AFE_CUSTOM_IRQ19_MISS_FLAG_SFT                        19
+#define AFE_CUSTOM_IRQ19_MISS_FLAG_MASK                       0x1
+#define AFE_CUSTOM_IRQ19_MISS_FLAG_MASK_SFT                   (0x1 << 19)
+#define AFE_CUSTOM_IRQ18_MISS_FLAG_SFT                        18
+#define AFE_CUSTOM_IRQ18_MISS_FLAG_MASK                       0x1
+#define AFE_CUSTOM_IRQ18_MISS_FLAG_MASK_SFT                   (0x1 << 18)
+#define AFE_CUSTOM_IRQ17_MISS_FLAG_SFT                        17
+#define AFE_CUSTOM_IRQ17_MISS_FLAG_MASK                       0x1
+#define AFE_CUSTOM_IRQ17_MISS_FLAG_MASK_SFT                   (0x1 << 17)
+#define AFE_CUSTOM_IRQ16_MISS_FLAG_SFT                        16
+#define AFE_CUSTOM_IRQ16_MISS_FLAG_MASK                       0x1
+#define AFE_CUSTOM_IRQ16_MISS_FLAG_MASK_SFT                   (0x1 << 16)
+#define AFE_CUSTOM_IRQ9_MISS_FLAG_SFT                         9
+#define AFE_CUSTOM_IRQ9_MISS_FLAG_MASK                        0x1
+#define AFE_CUSTOM_IRQ9_MISS_FLAG_MASK_SFT                    (0x1 << 9)
+#define AFE_CUSTOM_IRQ8_MISS_FLAG_SFT                         8
+#define AFE_CUSTOM_IRQ8_MISS_FLAG_MASK                        0x1
+#define AFE_CUSTOM_IRQ8_MISS_FLAG_MASK_SFT                    (0x1 << 8)
+#define AFE_CUSTOM_IRQ7_MISS_FLAG_SFT                         7
+#define AFE_CUSTOM_IRQ7_MISS_FLAG_MASK                        0x1
+#define AFE_CUSTOM_IRQ7_MISS_FLAG_MASK_SFT                    (0x1 << 7)
+#define AFE_CUSTOM_IRQ6_MISS_FLAG_SFT                         6
+#define AFE_CUSTOM_IRQ6_MISS_FLAG_MASK                        0x1
+#define AFE_CUSTOM_IRQ6_MISS_FLAG_MASK_SFT                    (0x1 << 6)
+#define AFE_CUSTOM_IRQ5_MISS_FLAG_SFT                         5
+#define AFE_CUSTOM_IRQ5_MISS_FLAG_MASK                        0x1
+#define AFE_CUSTOM_IRQ5_MISS_FLAG_MASK_SFT                    (0x1 << 5)
+#define AFE_CUSTOM_IRQ4_MISS_FLAG_SFT                         4
+#define AFE_CUSTOM_IRQ4_MISS_FLAG_MASK                        0x1
+#define AFE_CUSTOM_IRQ4_MISS_FLAG_MASK_SFT                    (0x1 << 4)
+#define AFE_CUSTOM_IRQ3_MISS_FLAG_SFT                         3
+#define AFE_CUSTOM_IRQ3_MISS_FLAG_MASK                        0x1
+#define AFE_CUSTOM_IRQ3_MISS_FLAG_MASK_SFT                    (0x1 << 3)
+#define AFE_CUSTOM_IRQ2_MISS_FLAG_SFT                         2
+#define AFE_CUSTOM_IRQ2_MISS_FLAG_MASK                        0x1
+#define AFE_CUSTOM_IRQ2_MISS_FLAG_MASK_SFT                    (0x1 << 2)
+#define AFE_CUSTOM_IRQ1_MISS_FLAG_SFT                         1
+#define AFE_CUSTOM_IRQ1_MISS_FLAG_MASK                        0x1
+#define AFE_CUSTOM_IRQ1_MISS_FLAG_MASK_SFT                    (0x1 << 1)
+#define AFE_CUSTOM_IRQ0_MISS_FLAG_SFT                         0
+#define AFE_CUSTOM_IRQ0_MISS_FLAG_MASK                        0x1
+#define AFE_CUSTOM_IRQ0_MISS_FLAG_MASK_SFT                    (0x1 << 0)
+
+/* AFE_IRQ_MCU_MON2 */
+#define AFE_IRQ_B_R_CNT_SFT                                   8
+#define AFE_IRQ_B_R_CNT_MASK                                  0xff
+#define AFE_IRQ_B_R_CNT_MASK_SFT                              (0xff << 8)
+#define AFE_IRQ_B_F_CNT_SFT                                   0
+#define AFE_IRQ_B_F_CNT_MASK                                  0xff
+#define AFE_IRQ_B_F_CNT_MASK_SFT                              (0xff << 0)
+
+/* AFE_IRQ0_CNT_MON */
+#define AFE_IRQ0_CNT_MON_SFT                                  0
+#define AFE_IRQ0_CNT_MON_MASK                                 0xffffff
+#define AFE_IRQ0_CNT_MON_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ1_CNT_MON */
+#define AFE_IRQ1_CNT_MON_SFT                                  0
+#define AFE_IRQ1_CNT_MON_MASK                                 0xffffff
+#define AFE_IRQ1_CNT_MON_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ2_CNT_MON */
+#define AFE_IRQ2_CNT_MON_SFT                                  0
+#define AFE_IRQ2_CNT_MON_MASK                                 0xffffff
+#define AFE_IRQ2_CNT_MON_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ3_CNT_MON */
+#define AFE_IRQ3_CNT_MON_SFT                                  0
+#define AFE_IRQ3_CNT_MON_MASK                                 0xffffff
+#define AFE_IRQ3_CNT_MON_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ4_CNT_MON */
+#define AFE_IRQ4_CNT_MON_SFT                                  0
+#define AFE_IRQ4_CNT_MON_MASK                                 0xffffff
+#define AFE_IRQ4_CNT_MON_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ5_CNT_MON */
+#define AFE_IRQ5_CNT_MON_SFT                                  0
+#define AFE_IRQ5_CNT_MON_MASK                                 0xffffff
+#define AFE_IRQ5_CNT_MON_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ6_CNT_MON */
+#define AFE_IRQ6_CNT_MON_SFT                                  0
+#define AFE_IRQ6_CNT_MON_MASK                                 0xffffff
+#define AFE_IRQ6_CNT_MON_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ7_CNT_MON */
+#define AFE_IRQ7_CNT_MON_SFT                                  0
+#define AFE_IRQ7_CNT_MON_MASK                                 0xffffff
+#define AFE_IRQ7_CNT_MON_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ8_CNT_MON */
+#define AFE_IRQ8_CNT_MON_SFT                                  0
+#define AFE_IRQ8_CNT_MON_MASK                                 0xffffff
+#define AFE_IRQ8_CNT_MON_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ9_CNT_MON */
+#define AFE_IRQ9_CNT_MON_SFT                                  0
+#define AFE_IRQ9_CNT_MON_MASK                                 0xffffff
+#define AFE_IRQ9_CNT_MON_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_IRQ10_CNT_MON */
+#define AFE_IRQ10_CNT_MON_SFT                                 0
+#define AFE_IRQ10_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ10_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ11_CNT_MON */
+#define AFE_IRQ11_CNT_MON_SFT                                 0
+#define AFE_IRQ11_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ11_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ12_CNT_MON */
+#define AFE_IRQ12_CNT_MON_SFT                                 0
+#define AFE_IRQ12_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ12_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ13_CNT_MON */
+#define AFE_IRQ13_CNT_MON_SFT                                 0
+#define AFE_IRQ13_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ13_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ14_CNT_MON */
+#define AFE_IRQ14_CNT_MON_SFT                                 0
+#define AFE_IRQ14_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ14_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ15_CNT_MON */
+#define AFE_IRQ15_CNT_MON_SFT                                 0
+#define AFE_IRQ15_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ15_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ16_CNT_MON */
+#define AFE_IRQ16_CNT_MON_SFT                                 0
+#define AFE_IRQ16_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ16_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ17_CNT_MON */
+#define AFE_IRQ17_CNT_MON_SFT                                 0
+#define AFE_IRQ17_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ17_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ18_CNT_MON */
+#define AFE_IRQ18_CNT_MON_SFT                                 0
+#define AFE_IRQ18_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ18_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ19_CNT_MON */
+#define AFE_IRQ19_CNT_MON_SFT                                 0
+#define AFE_IRQ19_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ19_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ20_CNT_MON */
+#define AFE_IRQ20_CNT_MON_SFT                                 0
+#define AFE_IRQ20_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ20_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ21_CNT_MON */
+#define AFE_IRQ21_CNT_MON_SFT                                 0
+#define AFE_IRQ21_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ21_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ22_CNT_MON */
+#define AFE_IRQ22_CNT_MON_SFT                                 0
+#define AFE_IRQ22_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ22_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ23_CNT_MON */
+#define AFE_IRQ23_CNT_MON_SFT                                 0
+#define AFE_IRQ23_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ23_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ24_CNT_MON */
+#define AFE_IRQ24_CNT_MON_SFT                                 0
+#define AFE_IRQ24_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ24_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ25_CNT_MON */
+#define AFE_IRQ25_CNT_MON_SFT                                 0
+#define AFE_IRQ25_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ25_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_IRQ26_CNT_MON */
+#define AFE_IRQ26_CNT_MON_SFT                                 0
+#define AFE_IRQ26_CNT_MON_MASK                                0xffffff
+#define AFE_IRQ26_CNT_MON_MASK_SFT                            (0xffffff << 0)
+
+/* AFE_CUSTOM_IRQ0_CNT_MON */
+#define AFE_CUSTOM_IRQ0_CNT_MON_SFT                           0
+#define AFE_CUSTOM_IRQ0_CNT_MON_MASK                          0xffffff
+#define AFE_CUSTOM_IRQ0_CNT_MON_MASK_SFT                      (0xffffff << 0)
+
+/* AFE_CUSTOM_IRQ0_MCU_CFG1 */
+#define AFE_CUSTOM_IRQ0_CLR_CFG_SFT                           31
+#define AFE_CUSTOM_IRQ0_CLR_CFG_MASK                          0x1
+#define AFE_CUSTOM_IRQ0_CLR_CFG_MASK_SFT                      (0x1 << 31)
+#define AFE_CUSTOM_IRQ0_MISS_FLAG_CLR_CFG_SFT                 30
+#define AFE_CUSTOM_IRQ0_MISS_FLAG_CLR_CFG_MASK                0x1
+#define AFE_CUSTOM_IRQ0_MISS_FLAG_CLR_CFG_MASK_SFT            (0x1 << 30)
+#define AFE_CUSTOM_IRQ0_MCU_CNT_SFT                           0
+#define AFE_CUSTOM_IRQ0_MCU_CNT_MASK                          0xffffff
+#define AFE_CUSTOM_IRQ0_MCU_CNT_MASK_SFT                      (0xffffff << 0)
+
+/* AFE_GAIN0_CON1_R */
+/* AFE_GAIN1_CON1_R */
+/* AFE_GAIN2_CON1_R */
+/* AFE_GAIN3_CON1_R */
+#define GAIN_TARGET_R_SFT                                    0
+#define GAIN_TARGET_R_MASK                                   0xffffffff
+#define GAIN_TARGET_R_MASK_SFT                               (0xffffffff << 0)
+
+/* AFE_GAIN0_CON1_L */
+/* AFE_GAIN1_CON1_L */
+/* AFE_GAIN2_CON1_L */
+/* AFE_GAIN3_CON1_L */
+#define GAIN_TARGET_L_SFT                                    0
+#define GAIN_TARGET_L_MASK                                   0xffffffff
+#define GAIN_TARGET_L_MASK_SFT                               (0xffffffff << 0)
+
+/* AFE_GAIN0_CON2 */
+#define GAIN0_DOWN_STEP_SFT                                   0
+#define GAIN0_DOWN_STEP_MASK                                  0x3fffff
+#define GAIN0_DOWN_STEP_MASK_SFT                              (0x3fffff << 0)
+
+/* AFE_GAIN0_CON3 */
+#define GAIN0_UP_STEP_SFT                                     0
+#define GAIN0_UP_STEP_MASK                                    0x3fffff
+#define GAIN0_UP_STEP_MASK_SFT                                (0x3fffff << 0)
+
+/* AFE_GAIN0_CUR_R */
+/* AFE_GAIN1_CUR_R */
+/* AFE_GAIN2_CUR_R */
+/* AFE_GAIN3_CUR_R */
+#define AFE_GAIN_CUR_R_SFT                                   0
+#define AFE_GAIN_CUR_R_MASK                                  0xffffffff
+#define AFE_GAIN_CUR_R_MASK_SFT                              (0xffffffff << 0)
+
+/* AFE_GAIN0_CUR_L */
+/* AFE_GAIN1_CUR_L */
+/* AFE_GAIN2_CUR_L */
+/* AFE_GAIN3_CUR_L */
+#define AFE_GAIN_CUR_L_SFT                                   0
+#define AFE_GAIN_CUR_L_MASK                                  0xffffffff
+#define AFE_GAIN_CUR_L_MASK_SFT                              (0xffffffff << 0)
+
+/* AFE_GAIN0_CON0 */
+/* AFE_GAIN1_CON0 */
+/* AFE_GAIN2_CON0 */
+/* AFE_GAIN3_CON0 */
+#define GAIN_TARGET_SYNC_ON_SFT                              24
+#define GAIN_TARGET_SYNC_ON_MASK                             0x1
+#define GAIN_TARGET_SYNC_ON_MASK_SFT                         (0x1 << 24)
+#define GAIN_TIMEOUT_SFT                                     18
+#define GAIN_TIMEOUT_MASK                                    0x3f
+#define GAIN_TIMEOUT_MASK_SFT                                (0x3f << 18)
+#define GAIN_TRIG_SFT                                        17
+#define GAIN_TRIG_MASK                                       0x1
+#define GAIN_TRIG_MASK_SFT                                   (0x1 << 17)
+#define GAIN_ON_SFT                                          16
+#define GAIN_ON_MASK                                         0x1
+#define GAIN_ON_MASK_SFT                                     (0x1 << 16)
+#define GAIN_SAMPLE_PER_STEP_SFT                             8
+#define GAIN_SAMPLE_PER_STEP_MASK                            0xff
+#define GAIN_SAMPLE_PER_STEP_MASK_SFT                        (0xff << 8)
+#define GAIN_SEL_DOMAIN_SFT                                  5
+#define GAIN_SEL_DOMAIN_MASK                                 0x7
+#define GAIN_SEL_DOMAIN_MASK_SFT                             (0x7 << 5)
+#define GAIN_SEL_FS_SFT                                      0
+#define GAIN_SEL_FS_MASK                                     0x1f
+#define GAIN_SEL_FS_MASK_SFT                                 (0x1f << 0)
+
+/* AFE_GAIN1_CON2 */
+#define GAIN1_DOWN_STEP_SFT                                   0
+#define GAIN1_DOWN_STEP_MASK                                  0x3fffff
+#define GAIN1_DOWN_STEP_MASK_SFT                              (0x3fffff << 0)
+
+/* AFE_GAIN1_CON3 */
+#define GAIN1_UP_STEP_SFT                                     0
+#define GAIN1_UP_STEP_MASK                                    0x3fffff
+#define GAIN1_UP_STEP_MASK_SFT                                (0x3fffff << 0)
+
+/* AFE_GAIN2_CON2 */
+#define GAIN2_DOWN_STEP_SFT                                   0
+#define GAIN2_DOWN_STEP_MASK                                  0x3fffff
+#define GAIN2_DOWN_STEP_MASK_SFT                              (0x3fffff << 0)
+
+/* AFE_GAIN2_CON3 */
+#define GAIN2_UP_STEP_SFT                                     0
+#define GAIN2_UP_STEP_MASK                                    0x3fffff
+#define GAIN2_UP_STEP_MASK_SFT                                (0x3fffff << 0)
+
+/* AFE_GAIN3_CON2 */
+#define GAIN3_DOWN_STEP_SFT                                   0
+#define GAIN3_DOWN_STEP_MASK                                  0x3fffff
+#define GAIN3_DOWN_STEP_MASK_SFT                              (0x3fffff << 0)
+
+/* AFE_GAIN3_CON3 */
+#define GAIN3_UP_STEP_SFT                                     0
+#define GAIN3_UP_STEP_MASK                                    0x3fffff
+#define GAIN3_UP_STEP_MASK_SFT                                (0x3fffff << 0)
+
+/* AFE_STF_CON0 */
+#define SLT_CNT_FLAG_RESET_SFT                                28
+#define SLT_CNT_FLAG_RESET_MASK                               0x1
+#define SLT_CNT_FLAG_RESET_MASK_SFT                           (0x1 << 28)
+#define SLT_CNT_THD_SFT                                       16
+#define SLT_CNT_THD_MASK                                      0xfff
+#define SLT_CNT_THD_MASK_SFT                                  (0xfff << 16)
+#define SIDE_TONE_HALF_TAP_NUM_SFT                            4
+#define SIDE_TONE_HALF_TAP_NUM_MASK                           0x7f
+#define SIDE_TONE_HALF_TAP_NUM_MASK_SFT                       (0x7f << 4)
+#define SIDE_TONE_ODD_MODE_SFT                                1
+#define SIDE_TONE_ODD_MODE_MASK                               0x1
+#define SIDE_TONE_ODD_MODE_MASK_SFT                           (0x1 << 1)
+#define SIDE_TONE_ON_SFT                                      0
+#define SIDE_TONE_ON_MASK                                     0x1
+#define SIDE_TONE_ON_MASK_SFT                                 (0x1 << 0)
+
+/* AFE_STF_CON1 */
+#define SIDE_TONE_IN_EN_SEL_DOMAIN_SFT                        5
+#define SIDE_TONE_IN_EN_SEL_DOMAIN_MASK                       0x7
+#define SIDE_TONE_IN_EN_SEL_DOMAIN_MASK_SFT                   (0x7 << 5)
+#define SIDE_TONE_IN_EN_SEL_FS_SFT                            0
+#define SIDE_TONE_IN_EN_SEL_FS_MASK                           0x1f
+#define SIDE_TONE_IN_EN_SEL_FS_MASK_SFT                       (0x1f << 0)
+
+/* AFE_STF_COEFF */
+#define SIDE_TONE_COEFFICIENT_R_W_SEL_SFT                     24
+#define SIDE_TONE_COEFFICIENT_R_W_SEL_MASK                    0x1
+#define SIDE_TONE_COEFFICIENT_R_W_SEL_MASK_SFT                (0x1 << 24)
+#define SIDE_TONE_COEFFICIENT_ADDR_SFT                        16
+#define SIDE_TONE_COEFFICIENT_ADDR_MASK                       0x1f
+#define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT                   (0x1f << 16)
+#define SIDE_TONE_COEFFICIENT_SFT                             0
+#define SIDE_TONE_COEFFICIENT_MASK                            0xffff
+#define SIDE_TONE_COEFFICIENT_MASK_SFT                        (0xffff << 0)
+
+/* AFE_STF_GAIN */
+#define SIDE_TONE_POSITIVE_GAIN_SFT                           16
+#define SIDE_TONE_POSITIVE_GAIN_MASK                          0x7
+#define SIDE_TONE_POSITIVE_GAIN_MASK_SFT                      (0x7 << 16)
+#define SIDE_TONE_GAIN_SFT                                    0
+#define SIDE_TONE_GAIN_MASK                                   0xffff
+#define SIDE_TONE_GAIN_MASK_SFT                               (0xffff << 0)
+
+/* AFE_STF_MON */
+#define SIDE_TONE_R_RDY_SFT                                   30
+#define SIDE_TONE_R_RDY_MASK                                  0x1
+#define SIDE_TONE_R_RDY_MASK_SFT                              (0x1 << 30)
+#define SIDE_TONE_W_RDY_SFT                                   29
+#define SIDE_TONE_W_RDY_MASK                                  0x1
+#define SIDE_TONE_W_RDY_MASK_SFT                              (0x1 << 29)
+#define SLT_CNT_FLAG_SFT                                      28
+#define SLT_CNT_FLAG_MASK                                     0x1
+#define SLT_CNT_FLAG_MASK_SFT                                 (0x1 << 28)
+#define SLT_CNT_SFT                                           16
+#define SLT_CNT_MASK                                          0xfff
+#define SLT_CNT_MASK_SFT                                      (0xfff << 16)
+#define SIDE_TONE_COEFF_SFT                                   0
+#define SIDE_TONE_COEFF_MASK                                  0xffff
+#define SIDE_TONE_COEFF_MASK_SFT                              (0xffff << 0)
+
+/* AFE_STF_IP_VERSION */
+#define SIDE_TONE_IP_VERSION_SFT                              0
+#define SIDE_TONE_IP_VERSION_MASK                             0xffffffff
+#define SIDE_TONE_IP_VERSION_MASK_SFT                         (0xffffffff << 0)
+
+/* AFE_CM_REG */
+#define AFE_CM_UPDATE_CNT_SFT                                 16
+#define AFE_CM_UPDATE_CNT_MASK                                0x7fff
+#define AFE_CM_UPDATE_CNT_MASK_SFT                            (0x7fff << 16)
+#define AFE_CM_1X_EN_SEL_FS_SFT                               8
+#define AFE_CM_1X_EN_SEL_FS_MASK                              0x1f
+#define AFE_CM_1X_EN_SEL_FS_MASK_SFT                          (0x1f << 8)
+#define AFE_CM_CH_NUM_SFT                                     2
+#define AFE_CM_CH_NUM_MASK                                    0x1f
+#define AFE_CM_CH_NUM_MASK_SFT                                (0x1f << 2)
+#define AFE_CM_BYTE_SWAP_SFT                                  1
+#define AFE_CM_BYTE_SWAP_MASK                                 0x1
+#define AFE_CM_BYTE_SWAP_MASK_SFT                             (0x1 << 1)
+#define AFE_CM_BYPASS_MODE_SFT                                31
+#define AFE_CM_BYPASS_MODE_MASK                               0x1
+#define AFE_CM_BYPASS_MODE_MASK_SFT                           (0x1 << 31)
+
+/* AFE_CM0_CON0 */
+#define AFE_CM0_BYPASS_MODE_SFT                               31
+#define AFE_CM0_BYPASS_MODE_MASK                              0x1
+#define AFE_CM0_BYPASS_MODE_MASK_SFT                          (0x1 << 31)
+#define AFE_CM0_UPDATE_CNT_SFT                                16
+#define AFE_CM0_UPDATE_CNT_MASK                               0x7fff
+#define AFE_CM0_UPDATE_CNT_MASK_SFT                           (0x7fff << 16)
+#define AFE_CM0_1X_EN_SEL_DOMAIN_SFT                          13
+#define AFE_CM0_1X_EN_SEL_DOMAIN_MASK                         0x7
+#define AFE_CM0_1X_EN_SEL_DOMAIN_MASK_SFT                     (0x7 << 13)
+#define AFE_CM0_1X_EN_SEL_FS_SFT                              8
+#define AFE_CM0_1X_EN_SEL_FS_MASK                             0x1f
+#define AFE_CM0_1X_EN_SEL_FS_MASK_SFT                         (0x1f << 8)
+#define AFE_CM0_OUTPUT_MUX_SFT                                7
+#define AFE_CM0_OUTPUT_MUX_MASK                               0x1
+#define AFE_CM0_OUTPUT_MUX_MASK_SFT                           (0x1 << 7)
+#define AFE_CM0_CH_NUM_SFT                                    2
+#define AFE_CM0_CH_NUM_MASK                                   0x1f
+#define AFE_CM0_CH_NUM_MASK_SFT                               (0x1f << 2)
+#define AFE_CM0_BYTE_SWAP_SFT                                 1
+#define AFE_CM0_BYTE_SWAP_MASK                                0x1
+#define AFE_CM0_BYTE_SWAP_MASK_SFT                            (0x1 << 1)
+#define AFE_CM0_ON_SFT                                        0
+#define AFE_CM0_ON_MASK                                       0x1
+#define AFE_CM0_ON_MASK_SFT                                   (0x1 << 0)
+
+/* AFE_CM0_MON */
+#define AFE_CM0_BYPASS_MODE_MON_SFT                           31
+#define AFE_CM0_BYPASS_MODE_MON_MASK                          0x1
+#define AFE_CM0_BYPASS_MODE_MON_MASK_SFT                      (0x1 << 31)
+#define AFE_CM0_OUTPUT_CNT_MON_SFT                            16
+#define AFE_CM0_OUTPUT_CNT_MON_MASK                           0x7fff
+#define AFE_CM0_OUTPUT_CNT_MON_MASK_SFT                       (0x7fff << 16)
+#define AFE_CM0_CUR_CHSET_MON_SFT                             5
+#define AFE_CM0_CUR_CHSET_MON_MASK                            0xf
+#define AFE_CM0_CUR_CHSET_MON_MASK_SFT                        (0xf << 5)
+#define AFE_CM0_ODD_FLAG_MON_SFT                              4
+#define AFE_CM0_ODD_FLAG_MON_MASK                             0x1
+#define AFE_CM0_ODD_FLAG_MON_MASK_SFT                         (0x1 << 4)
+#define AFE_CM0_BYTE_SWAP_MON_SFT                             1
+#define AFE_CM0_BYTE_SWAP_MON_MASK                            0x1
+#define AFE_CM0_BYTE_SWAP_MON_MASK_SFT                        (0x1 << 1)
+#define AFE_CM0_ON_MON_SFT                                    0
+#define AFE_CM0_ON_MON_MASK                                   0x1
+#define AFE_CM0_ON_MON_MASK_SFT                               (0x1 << 0)
+
+/* AFE_CM0_IP_VERSION */
+#define AFE_CM0_IP_VERSION_SFT                                0
+#define AFE_CM0_IP_VERSION_MASK                               0xffffffff
+#define AFE_CM0_IP_VERSION_MASK_SFT                           (0xffffffff << 0)
+
+/* AFE_CM1_CON0 */
+#define AFE_CM1_BYPASS_MODE_SFT                               31
+#define AFE_CM1_BYPASS_MODE_MASK                              0x1
+#define AFE_CM1_BYPASS_MODE_MASK_SFT                          (0x1 << 31)
+#define AFE_CM1_UPDATE_CNT_SFT                                16
+#define AFE_CM1_UPDATE_CNT_MASK                               0x7fff
+#define AFE_CM1_UPDATE_CNT_MASK_SFT                           (0x7fff << 16)
+#define AFE_CM1_1X_EN_SEL_DOMAIN_SFT                          13
+#define AFE_CM1_1X_EN_SEL_DOMAIN_MASK                         0x7
+#define AFE_CM1_1X_EN_SEL_DOMAIN_MASK_SFT                     (0x7 << 13)
+#define AFE_CM1_1X_EN_SEL_FS_SFT                              8
+#define AFE_CM1_1X_EN_SEL_FS_MASK                             0x1f
+#define AFE_CM1_1X_EN_SEL_FS_MASK_SFT                         (0x1f << 8)
+#define AFE_CM1_OUTPUT_MUX_SFT                                7
+#define AFE_CM1_OUTPUT_MUX_MASK                               0x1
+#define AFE_CM1_OUTPUT_MUX_MASK_SFT                           (0x1 << 7)
+#define AFE_CM1_CH_NUM_SFT                                    2
+#define AFE_CM1_CH_NUM_MASK                                   0x1f
+#define AFE_CM1_CH_NUM_MASK_SFT                               (0x1f << 2)
+#define AFE_CM1_BYTE_SWAP_SFT                                 1
+#define AFE_CM1_BYTE_SWAP_MASK                                0x1
+#define AFE_CM1_BYTE_SWAP_MASK_SFT                            (0x1 << 1)
+#define AFE_CM1_ON_SFT                                        0
+#define AFE_CM1_ON_MASK                                       0x1
+#define AFE_CM1_ON_MASK_SFT                                   (0x1 << 0)
+
+/* AFE_CM1_MON */
+#define AFE_CM1_BYPASS_MODE_MON_SFT                           31
+#define AFE_CM1_BYPASS_MODE_MON_MASK                          0x1
+#define AFE_CM1_BYPASS_MODE_MON_MASK_SFT                      (0x1 << 31)
+#define AFE_CM1_OUTPUT_CNT_MON_SFT                            16
+#define AFE_CM1_OUTPUT_CNT_MON_MASK                           0x7fff
+#define AFE_CM1_OUTPUT_CNT_MON_MASK_SFT                       (0x7fff << 16)
+#define AFE_CM1_CUR_CHSET_MON_SFT                             5
+#define AFE_CM1_CUR_CHSET_MON_MASK                            0xf
+#define AFE_CM1_CUR_CHSET_MON_MASK_SFT                        (0xf << 5)
+#define AFE_CM1_ODD_FLAG_MON_SFT                              4
+#define AFE_CM1_ODD_FLAG_MON_MASK                             0x1
+#define AFE_CM1_ODD_FLAG_MON_MASK_SFT                         (0x1 << 4)
+#define AFE_CM1_BYTE_SWAP_MON_SFT                             1
+#define AFE_CM1_BYTE_SWAP_MON_MASK                            0x1
+#define AFE_CM1_BYTE_SWAP_MON_MASK_SFT                        (0x1 << 1)
+#define AFE_CM1_ON_MON_SFT                                    0
+#define AFE_CM1_ON_MON_MASK                                   0x1
+#define AFE_CM1_ON_MON_MASK_SFT                               (0x1 << 0)
+
+/* AFE_CM1_IP_VERSION */
+#define AFE_CM1_IP_VERSION_SFT                                0
+#define AFE_CM1_IP_VERSION_MASK                               0xffffffff
+#define AFE_CM1_IP_VERSION_MASK_SFT                           (0xffffffff << 0)
+
+/* AFE_CM2_CON0 */
+#define AFE_CM2_BYPASS_MODE_SFT                               31
+#define AFE_CM2_BYPASS_MODE_MASK                              0x1
+#define AFE_CM2_BYPASS_MODE_MASK_SFT                          (0x1 << 31)
+#define AFE_CM2_UPDATE_CNT_SFT                                16
+#define AFE_CM2_UPDATE_CNT_MASK                               0x7fff
+#define AFE_CM2_UPDATE_CNT_MASK_SFT                           (0x7fff << 16)
+#define AFE_CM2_1X_EN_SEL_DOMAIN_SFT                          13
+#define AFE_CM2_1X_EN_SEL_DOMAIN_MASK                         0x7
+#define AFE_CM2_1X_EN_SEL_DOMAIN_MASK_SFT                     (0x7 << 13)
+#define AFE_CM2_1X_EN_SEL_FS_SFT                              8
+#define AFE_CM2_1X_EN_SEL_FS_MASK                             0x1f
+#define AFE_CM2_1X_EN_SEL_FS_MASK_SFT                         (0x1f << 8)
+#define AFE_CM2_OUTPUT_MUX_SFT                                7
+#define AFE_CM2_OUTPUT_MUX_MASK                               0x1
+#define AFE_CM2_OUTPUT_MUX_MASK_SFT                           (0x1 << 7)
+#define AFE_CM2_CH_NUM_SFT                                    2
+#define AFE_CM2_CH_NUM_MASK                                   0x1f
+#define AFE_CM2_CH_NUM_MASK_SFT                               (0x1f << 2)
+#define AFE_CM2_BYTE_SWAP_SFT                                 1
+#define AFE_CM2_BYTE_SWAP_MASK                                0x1
+#define AFE_CM2_BYTE_SWAP_MASK_SFT                            (0x1 << 1)
+#define AFE_CM2_ON_SFT                                        0
+#define AFE_CM2_ON_MASK                                       0x1
+#define AFE_CM2_ON_MASK_SFT                                   (0x1 << 0)
+
+/* AFE_CM2_MON */
+#define AFE_CM2_BYPASS_MODE_MON_SFT                           31
+#define AFE_CM2_BYPASS_MODE_MON_MASK                          0x1
+#define AFE_CM2_BYPASS_MODE_MON_MASK_SFT                      (0x1 << 31)
+#define AFE_CM2_OUTPUT_CNT_MON_SFT                            16
+#define AFE_CM2_OUTPUT_CNT_MON_MASK                           0x7fff
+#define AFE_CM2_OUTPUT_CNT_MON_MASK_SFT                       (0x7fff << 16)
+#define AFE_CM2_CUR_CHSET_MON_SFT                             5
+#define AFE_CM2_CUR_CHSET_MON_MASK                            0xf
+#define AFE_CM2_CUR_CHSET_MON_MASK_SFT                        (0xf << 5)
+#define AFE_CM2_ODD_FLAG_MON_SFT                              4
+#define AFE_CM2_ODD_FLAG_MON_MASK                             0x1
+#define AFE_CM2_ODD_FLAG_MON_MASK_SFT                         (0x1 << 4)
+#define AFE_CM2_BYTE_SWAP_MON_SFT                             1
+#define AFE_CM2_BYTE_SWAP_MON_MASK                            0x1
+#define AFE_CM2_BYTE_SWAP_MON_MASK_SFT                        (0x1 << 1)
+#define AFE_CM2_ON_MON_SFT                                    0
+#define AFE_CM2_ON_MON_MASK                                   0x1
+#define AFE_CM2_ON_MON_MASK_SFT                               (0x1 << 0)
+
+/* AFE_CM2_IP_VERSION */
+#define AFE_CM2_IP_VERSION_SFT                                0
+#define AFE_CM2_IP_VERSION_MASK                               0xffffffff
+#define AFE_CM2_IP_VERSION_MASK_SFT                           (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_SRC_CON0 */
+#define ULCF_CFG_EN_CTL_SFT                                   31
+#define ULCF_CFG_EN_CTL_MASK                                  0x1
+#define ULCF_CFG_EN_CTL_MASK_SFT                              (0x1 << 31)
+#define UL_DMIC_PHASE_SEL_CH1_SFT                             27
+#define UL_DMIC_PHASE_SEL_CH1_MASK                            0x7
+#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT                        (0x7 << 27)
+#define UL_DMIC_PHASE_SEL_CH2_SFT                             24
+#define UL_DMIC_PHASE_SEL_CH2_MASK                            0x7
+#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT                        (0x7 << 24)
+#define UL_DMIC_TWO_WIRE_CTL_SFT                              23
+#define UL_DMIC_TWO_WIRE_CTL_MASK                             0x1
+#define UL_DMIC_TWO_WIRE_CTL_MASK_SFT                         (0x1 << 23)
+#define UL_MODE_3P25M_CH2_CTL_SFT                             22
+#define UL_MODE_3P25M_CH2_CTL_MASK                            0x1
+#define UL_MODE_3P25M_CH2_CTL_MASK_SFT                        (0x1 << 22)
+#define UL_MODE_3P25M_CH1_CTL_SFT                             21
+#define UL_MODE_3P25M_CH1_CTL_MASK                            0x1
+#define UL_MODE_3P25M_CH1_CTL_MASK_SFT                        (0x1 << 21)
+#define UL_VOICE_MODE_CH1_CH2_CTL_SFT                         17
+#define UL_VOICE_MODE_CH1_CH2_CTL_MASK                        0x7
+#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT                    (0x7 << 17)
+#define UL_AP_DMIC_ON_SFT                                     16
+#define UL_AP_DMIC_ON_MASK                                    0x1
+#define UL_AP_DMIC_ON_MASK_SFT                                (0x1 << 16)
+#define DMIC_LOW_POWER_MODE_CTL_SFT                           14
+#define DMIC_LOW_POWER_MODE_CTL_MASK                          0x3
+#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT                      (0x3 << 14)
+#define UL_DISABLE_HW_CG_CTL_SFT                              12
+#define UL_DISABLE_HW_CG_CTL_MASK                             0x1
+#define UL_DISABLE_HW_CG_CTL_MASK_SFT                         (0x1 << 12)
+#define AMIC_26M_SEL_CTL_SFT                                  11
+#define AMIC_26M_SEL_CTL_MASK                                 0x1
+#define AMIC_26M_SEL_CTL_MASK_SFT                             (0x1 << 11)
+#define UL_IIR_ON_TMP_CTL_SFT                                 10
+#define UL_IIR_ON_TMP_CTL_MASK                                0x1
+#define UL_IIR_ON_TMP_CTL_MASK_SFT                            (0x1 << 10)
+#define UL_IIRMODE_CTL_SFT                                    7
+#define UL_IIRMODE_CTL_MASK                                   0x7
+#define UL_IIRMODE_CTL_MASK_SFT                               (0x7 << 7)
+#define DIGMIC_4P33M_SEL_SFT                                  6
+#define DIGMIC_4P33M_SEL_MASK                                 0x1
+#define DIGMIC_4P33M_SEL_MASK_SFT                             (0x1 << 6)
+#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT                       5
+#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK                      0x1
+#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT                  (0x1 << 5)
+#define AMIC_6P5M_SEL_CTL_SFT                                 4
+#define AMIC_6P5M_SEL_CTL_MASK                                0x1
+#define AMIC_6P5M_SEL_CTL_MASK_SFT                            (0x1 << 4)
+#define AMIC_1P625M_SEL_CTL_SFT                               3
+#define AMIC_1P625M_SEL_CTL_MASK                              0x1
+#define AMIC_1P625M_SEL_CTL_MASK_SFT                          (0x1 << 3)
+#define UL_LOOP_BACK_MODE_CTL_SFT                             2
+#define UL_LOOP_BACK_MODE_CTL_MASK                            0x1
+#define UL_LOOP_BACK_MODE_CTL_MASK_SFT                        (0x1 << 2)
+#define UL_SDM_3_LEVEL_CTL_SFT                                1
+#define UL_SDM_3_LEVEL_CTL_MASK                               0x1
+#define UL_SDM_3_LEVEL_CTL_MASK_SFT                           (0x1 << 1)
+#define UL_SRC_ON_TMP_CTL_SFT                                 0
+#define UL_SRC_ON_TMP_CTL_MASK                                0x1
+#define UL_SRC_ON_TMP_CTL_MASK_SFT                            (0x1 << 0)
+
+/* AFE_ADDA_UL0_SRC_CON1 */
+#define ADDA_UL_GAIN_VALUE_SFT                                16
+#define ADDA_UL_GAIN_VALUE_MASK                               0xffff
+#define ADDA_UL_GAIN_VALUE_MASK_SFT                           (0xffff << 16)
+#define ADDA_UL_POSTIVEGAIN_SFT                               12
+#define ADDA_UL_POSTIVEGAIN_MASK                              0x7
+#define ADDA_UL_POSTIVEGAIN_MASK_SFT                          (0x7 << 12)
+#define ADDA_UL_ODDTAP_MODE_SFT                               11
+#define ADDA_UL_ODDTAP_MODE_MASK                              0x1
+#define ADDA_UL_ODDTAP_MODE_MASK_SFT                          (0x1 << 11)
+#define ADDA_UL_HALF_TAP_NUM_SFT                              5
+#define ADDA_UL_HALF_TAP_NUM_MASK                             0x3f
+#define ADDA_UL_HALF_TAP_NUM_MASK_SFT                         (0x3f << 5)
+#define FIFO_SOFT_RST_SFT                                     4
+#define FIFO_SOFT_RST_MASK                                    0x1
+#define FIFO_SOFT_RST_MASK_SFT                                (0x1 << 4)
+#define FIFO_SOFT_RST_EN_SFT                                  3
+#define FIFO_SOFT_RST_EN_MASK                                 0x1
+#define FIFO_SOFT_RST_EN_MASK_SFT                             (0x1 << 3)
+#define LR_SWAP_SFT                                           2
+#define LR_SWAP_MASK                                          0x1
+#define LR_SWAP_MASK_SFT                                      (0x1 << 2)
+#define GAIN_MODE_SFT                                         0
+#define GAIN_MODE_MASK                                        0x3
+#define GAIN_MODE_MASK_SFT                                    (0x3 << 0)
+
+/* AFE_ADDA_UL0_SRC_CON2 */
+#define C_DAC_EN_CTL_SFT                                      27
+#define C_DAC_EN_CTL_MASK                                     0x1
+#define C_DAC_EN_CTL_MASK_SFT                                 (0x1 << 27)
+#define C_MUTE_SW_CTL_SFT                                     26
+#define C_MUTE_SW_CTL_MASK                                    0x1
+#define C_MUTE_SW_CTL_MASK_SFT                                (0x1 << 26)
+#define C_AMP_DIV_CH2_CTL_SFT                                 21
+#define C_AMP_DIV_CH2_CTL_MASK                                0x7
+#define C_AMP_DIV_CH2_CTL_MASK_SFT                            (0x7 << 21)
+#define C_FREQ_DIV_CH2_CTL_SFT                                16
+#define C_FREQ_DIV_CH2_CTL_MASK                               0x1f
+#define C_FREQ_DIV_CH2_CTL_MASK_SFT                           (0x1f << 16)
+#define C_SINE_MODE_CH2_CTL_SFT                               12
+#define C_SINE_MODE_CH2_CTL_MASK                              0xf
+#define C_SINE_MODE_CH2_CTL_MASK_SFT                          (0xf << 12)
+#define C_AMP_DIV_CH1_CTL_SFT                                 9
+#define C_AMP_DIV_CH1_CTL_MASK                                0x7
+#define C_AMP_DIV_CH1_CTL_MASK_SFT                            (0x7 << 9)
+#define C_FREQ_DIV_CH1_CTL_SFT                                4
+#define C_FREQ_DIV_CH1_CTL_MASK                               0x1f
+#define C_FREQ_DIV_CH1_CTL_MASK_SFT                           (0x1f << 4)
+#define C_SINE_MODE_CH1_CTL_SFT                               0
+#define C_SINE_MODE_CH1_CTL_MASK                              0xf
+#define C_SINE_MODE_CH1_CTL_MASK_SFT                          (0xf << 0)
+
+/* AFE_ADDA_UL0_SRC_DEBUG */
+#define UL_SLT_CNT_FLAG_RESET_CTL_SFT                         16
+#define UL_SLT_CNT_FLAG_RESET_CTL_MASK                        0x1
+#define UL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT                    (0x1 << 16)
+#define FIFO_DIGMIC_TESTIN_SFT                                12
+#define FIFO_DIGMIC_TESTIN_MASK                               0x3
+#define FIFO_DIGMIC_TESTIN_MASK_SFT                           (0x3 << 12)
+#define FIFO_DIGMIC_WDATA_TESTEN_SFT                          11
+#define FIFO_DIGMIC_WDATA_TESTEN_MASK                         0x1
+#define FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT                     (0x1 << 11)
+#define SLT_CNT_THD_CTL_SFT                                   0
+#define SLT_CNT_THD_CTL_MASK                                  0x7ff
+#define SLT_CNT_THD_CTL_MASK_SFT                              (0x7ff << 0)
+
+/* AFE_ADDA_UL0_SRC_DEBUG_MON0 */
+#define SLT_CNT_FLAG_CTL_SFT                                  16
+#define SLT_CNT_FLAG_CTL_MASK                                 0x1
+#define SLT_CNT_FLAG_CTL_MASK_SFT                             (0x1 << 16)
+#define SLT_COUNTER_CTL_SFT                                   0
+#define SLT_COUNTER_CTL_MASK                                  0x7ff
+#define SLT_COUNTER_CTL_MASK_SFT                              (0x7ff << 0)
+
+/* AFE_ADDA_UL0_IIR_COEF_02_01 */
+#define ADDA_IIR_COEF_02_01_SFT                               0
+#define ADDA_IIR_COEF_02_01_MASK                              0xffffffff
+#define ADDA_IIR_COEF_02_01_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_IIR_COEF_04_03 */
+#define ADDA_IIR_COEF_04_03_SFT                               0
+#define ADDA_IIR_COEF_04_03_MASK                              0xffffffff
+#define ADDA_IIR_COEF_04_03_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_IIR_COEF_06_05 */
+#define ADDA_IIR_COEF_06_05_SFT                               0
+#define ADDA_IIR_COEF_06_05_MASK                              0xffffffff
+#define ADDA_IIR_COEF_06_05_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_IIR_COEF_08_07 */
+#define ADDA_IIR_COEF_08_07_SFT                               0
+#define ADDA_IIR_COEF_08_07_MASK                              0xffffffff
+#define ADDA_IIR_COEF_08_07_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_IIR_COEF_10_09 */
+#define ADDA_IIR_COEF_10_09_SFT                               0
+#define ADDA_IIR_COEF_10_09_MASK                              0xffffffff
+#define ADDA_IIR_COEF_10_09_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_02_01 */
+#define ADDA_ULCF_CFG_02_01_SFT                               0
+#define ADDA_ULCF_CFG_02_01_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_02_01_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_04_03 */
+#define ADDA_ULCF_CFG_04_03_SFT                               0
+#define ADDA_ULCF_CFG_04_03_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_04_03_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_06_05 */
+#define ADDA_ULCF_CFG_06_05_SFT                               0
+#define ADDA_ULCF_CFG_06_05_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_06_05_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_08_07 */
+#define ADDA_ULCF_CFG_08_07_SFT                               0
+#define ADDA_ULCF_CFG_08_07_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_08_07_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_10_09 */
+#define ADDA_ULCF_CFG_10_09_SFT                               0
+#define ADDA_ULCF_CFG_10_09_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_10_09_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_12_11 */
+#define ADDA_ULCF_CFG_12_11_SFT                               0
+#define ADDA_ULCF_CFG_12_11_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_12_11_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_14_13 */
+#define ADDA_ULCF_CFG_14_13_SFT                               0
+#define ADDA_ULCF_CFG_14_13_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_14_13_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_16_15 */
+#define ADDA_ULCF_CFG_16_15_SFT                               0
+#define ADDA_ULCF_CFG_16_15_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_16_15_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_18_17 */
+#define ADDA_ULCF_CFG_18_17_SFT                               0
+#define ADDA_ULCF_CFG_18_17_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_18_17_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_20_19 */
+#define ADDA_ULCF_CFG_20_19_SFT                               0
+#define ADDA_ULCF_CFG_20_19_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_20_19_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_22_21 */
+#define ADDA_ULCF_CFG_22_21_SFT                               0
+#define ADDA_ULCF_CFG_22_21_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_22_21_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_24_23 */
+#define ADDA_ULCF_CFG_24_23_SFT                               0
+#define ADDA_ULCF_CFG_24_23_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_24_23_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_26_25 */
+#define ADDA_ULCF_CFG_26_25_SFT                               0
+#define ADDA_ULCF_CFG_26_25_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_26_25_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_28_27 */
+#define ADDA_ULCF_CFG_28_27_SFT                               0
+#define ADDA_ULCF_CFG_28_27_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_28_27_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_30_29 */
+#define ADDA_ULCF_CFG_30_29_SFT                               0
+#define ADDA_ULCF_CFG_30_29_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_30_29_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_32_31 */
+#define ADDA_ULCF_CFG_32_31_SFT                               0
+#define ADDA_ULCF_CFG_32_31_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_32_31_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_IP_VERSION */
+#define ADDA_ULCF_IP_VERSION_SFT                              0
+#define ADDA_ULCF_IP_VERSION_MASK                             0xffffffff
+#define ADDA_ULCF_IP_VERSION_MASK_SFT                         (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_SRC_CON0 */
+#define ULCF_CFG_EN_CTL_SFT                                   31
+#define ULCF_CFG_EN_CTL_MASK                                  0x1
+#define ULCF_CFG_EN_CTL_MASK_SFT                              (0x1 << 31)
+#define UL_DMIC_PHASE_SEL_CH1_SFT                             27
+#define UL_DMIC_PHASE_SEL_CH1_MASK                            0x7
+#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT                        (0x7 << 27)
+#define UL_DMIC_PHASE_SEL_CH2_SFT                             24
+#define UL_DMIC_PHASE_SEL_CH2_MASK                            0x7
+#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT                        (0x7 << 24)
+#define UL_DMIC_TWO_WIRE_CTL_SFT                              23
+#define UL_DMIC_TWO_WIRE_CTL_MASK                             0x1
+#define UL_DMIC_TWO_WIRE_CTL_MASK_SFT                         (0x1 << 23)
+#define UL_MODE_3P25M_CH2_CTL_SFT                             22
+#define UL_MODE_3P25M_CH2_CTL_MASK                            0x1
+#define UL_MODE_3P25M_CH2_CTL_MASK_SFT                        (0x1 << 22)
+#define UL_MODE_3P25M_CH1_CTL_SFT                             21
+#define UL_MODE_3P25M_CH1_CTL_MASK                            0x1
+#define UL_MODE_3P25M_CH1_CTL_MASK_SFT                        (0x1 << 21)
+#define UL_VOICE_MODE_CH1_CH2_CTL_SFT                         17
+#define UL_VOICE_MODE_CH1_CH2_CTL_MASK                        0x7
+#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT                    (0x7 << 17)
+#define UL_AP_DMIC_ON_SFT                                     16
+#define UL_AP_DMIC_ON_MASK                                    0x1
+#define UL_AP_DMIC_ON_MASK_SFT                                (0x1 << 16)
+#define DMIC_LOW_POWER_MODE_CTL_SFT                           14
+#define DMIC_LOW_POWER_MODE_CTL_MASK                          0x3
+#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT                      (0x3 << 14)
+#define UL_DISABLE_HW_CG_CTL_SFT                              12
+#define UL_DISABLE_HW_CG_CTL_MASK                             0x1
+#define UL_DISABLE_HW_CG_CTL_MASK_SFT                         (0x1 << 12)
+#define AMIC_26M_SEL_CTL_SFT                                  11
+#define AMIC_26M_SEL_CTL_MASK                                 0x1
+#define AMIC_26M_SEL_CTL_MASK_SFT                             (0x1 << 11)
+#define UL_IIR_ON_TMP_CTL_SFT                                 10
+#define UL_IIR_ON_TMP_CTL_MASK                                0x1
+#define UL_IIR_ON_TMP_CTL_MASK_SFT                            (0x1 << 10)
+#define UL_IIRMODE_CTL_SFT                                    7
+#define UL_IIRMODE_CTL_MASK                                   0x7
+#define UL_IIRMODE_CTL_MASK_SFT                               (0x7 << 7)
+#define DIGMIC_4P33M_SEL_SFT                                  6
+#define DIGMIC_4P33M_SEL_MASK                                 0x1
+#define DIGMIC_4P33M_SEL_MASK_SFT                             (0x1 << 6)
+#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT                       5
+#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK                      0x1
+#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT                  (0x1 << 5)
+#define AMIC_6P5M_SEL_CTL_SFT                                 4
+#define AMIC_6P5M_SEL_CTL_MASK                                0x1
+#define AMIC_6P5M_SEL_CTL_MASK_SFT                            (0x1 << 4)
+#define AMIC_1P625M_SEL_CTL_SFT                               3
+#define AMIC_1P625M_SEL_CTL_MASK                              0x1
+#define AMIC_1P625M_SEL_CTL_MASK_SFT                          (0x1 << 3)
+#define UL_LOOP_BACK_MODE_CTL_SFT                             2
+#define UL_LOOP_BACK_MODE_CTL_MASK                            0x1
+#define UL_LOOP_BACK_MODE_CTL_MASK_SFT                        (0x1 << 2)
+#define UL_SDM_3_LEVEL_CTL_SFT                                1
+#define UL_SDM_3_LEVEL_CTL_MASK                               0x1
+#define UL_SDM_3_LEVEL_CTL_MASK_SFT                           (0x1 << 1)
+#define UL_SRC_ON_TMP_CTL_SFT                                 0
+#define UL_SRC_ON_TMP_CTL_MASK                                0x1
+#define UL_SRC_ON_TMP_CTL_MASK_SFT                            (0x1 << 0)
+
+/* AFE_ADDA_UL1_SRC_CON1 */
+#define ADDA_UL_GAIN_VALUE_SFT                                16
+#define ADDA_UL_GAIN_VALUE_MASK                               0xffff
+#define ADDA_UL_GAIN_VALUE_MASK_SFT                           (0xffff << 16)
+#define ADDA_UL_POSTIVEGAIN_SFT                               12
+#define ADDA_UL_POSTIVEGAIN_MASK                              0x7
+#define ADDA_UL_POSTIVEGAIN_MASK_SFT                          (0x7 << 12)
+#define ADDA_UL_ODDTAP_MODE_SFT                               11
+#define ADDA_UL_ODDTAP_MODE_MASK                              0x1
+#define ADDA_UL_ODDTAP_MODE_MASK_SFT                          (0x1 << 11)
+#define ADDA_UL_HALF_TAP_NUM_SFT                              5
+#define ADDA_UL_HALF_TAP_NUM_MASK                             0x3f
+#define ADDA_UL_HALF_TAP_NUM_MASK_SFT                         (0x3f << 5)
+#define FIFO_SOFT_RST_SFT                                     4
+#define FIFO_SOFT_RST_MASK                                    0x1
+#define FIFO_SOFT_RST_MASK_SFT                                (0x1 << 4)
+#define FIFO_SOFT_RST_EN_SFT                                  3
+#define FIFO_SOFT_RST_EN_MASK                                 0x1
+#define FIFO_SOFT_RST_EN_MASK_SFT                             (0x1 << 3)
+#define LR_SWAP_SFT                                           2
+#define LR_SWAP_MASK                                          0x1
+#define LR_SWAP_MASK_SFT                                      (0x1 << 2)
+#define GAIN_MODE_SFT                                         0
+#define GAIN_MODE_MASK                                        0x3
+#define GAIN_MODE_MASK_SFT                                    (0x3 << 0)
+
+/* AFE_ADDA_UL1_SRC_CON2 */
+#define C_DAC_EN_CTL_SFT                                      27
+#define C_DAC_EN_CTL_MASK                                     0x1
+#define C_DAC_EN_CTL_MASK_SFT                                 (0x1 << 27)
+#define C_MUTE_SW_CTL_SFT                                     26
+#define C_MUTE_SW_CTL_MASK                                    0x1
+#define C_MUTE_SW_CTL_MASK_SFT                                (0x1 << 26)
+#define C_AMP_DIV_CH2_CTL_SFT                                 21
+#define C_AMP_DIV_CH2_CTL_MASK                                0x7
+#define C_AMP_DIV_CH2_CTL_MASK_SFT                            (0x7 << 21)
+#define C_FREQ_DIV_CH2_CTL_SFT                                16
+#define C_FREQ_DIV_CH2_CTL_MASK                               0x1f
+#define C_FREQ_DIV_CH2_CTL_MASK_SFT                           (0x1f << 16)
+#define C_SINE_MODE_CH2_CTL_SFT                               12
+#define C_SINE_MODE_CH2_CTL_MASK                              0xf
+#define C_SINE_MODE_CH2_CTL_MASK_SFT                          (0xf << 12)
+#define C_AMP_DIV_CH1_CTL_SFT                                 9
+#define C_AMP_DIV_CH1_CTL_MASK                                0x7
+#define C_AMP_DIV_CH1_CTL_MASK_SFT                            (0x7 << 9)
+#define C_FREQ_DIV_CH1_CTL_SFT                                4
+#define C_FREQ_DIV_CH1_CTL_MASK                               0x1f
+#define C_FREQ_DIV_CH1_CTL_MASK_SFT                           (0x1f << 4)
+#define C_SINE_MODE_CH1_CTL_SFT                               0
+#define C_SINE_MODE_CH1_CTL_MASK                              0xf
+#define C_SINE_MODE_CH1_CTL_MASK_SFT                          (0xf << 0)
+
+/* AFE_ADDA_UL1_SRC_DEBUG */
+#define UL_SLT_CNT_FLAG_RESET_CTL_SFT                         16
+#define UL_SLT_CNT_FLAG_RESET_CTL_MASK                        0x1
+#define UL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT                    (0x1 << 16)
+#define FIFO_DIGMIC_TESTIN_SFT                                12
+#define FIFO_DIGMIC_TESTIN_MASK                               0x3
+#define FIFO_DIGMIC_TESTIN_MASK_SFT                           (0x3 << 12)
+#define FIFO_DIGMIC_WDATA_TESTEN_SFT                          11
+#define FIFO_DIGMIC_WDATA_TESTEN_MASK                         0x1
+#define FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT                     (0x1 << 11)
+#define SLT_CNT_THD_CTL_SFT                                   0
+#define SLT_CNT_THD_CTL_MASK                                  0x7ff
+#define SLT_CNT_THD_CTL_MASK_SFT                              (0x7ff << 0)
+
+/* AFE_ADDA_UL1_SRC_DEBUG_MON0 */
+#define SLT_CNT_FLAG_CTL_SFT                                  16
+#define SLT_CNT_FLAG_CTL_MASK                                 0x1
+#define SLT_CNT_FLAG_CTL_MASK_SFT                             (0x1 << 16)
+#define SLT_COUNTER_CTL_SFT                                   0
+#define SLT_COUNTER_CTL_MASK                                  0x7ff
+#define SLT_COUNTER_CTL_MASK_SFT                              (0x7ff << 0)
+
+/* AFE_ADDA_UL1_IIR_COEF_02_01 */
+#define ADDA_IIR_COEF_02_01_SFT                               0
+#define ADDA_IIR_COEF_02_01_MASK                              0xffffffff
+#define ADDA_IIR_COEF_02_01_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_IIR_COEF_04_03 */
+#define ADDA_IIR_COEF_04_03_SFT                               0
+#define ADDA_IIR_COEF_04_03_MASK                              0xffffffff
+#define ADDA_IIR_COEF_04_03_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_IIR_COEF_06_05 */
+#define ADDA_IIR_COEF_06_05_SFT                               0
+#define ADDA_IIR_COEF_06_05_MASK                              0xffffffff
+#define ADDA_IIR_COEF_06_05_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_IIR_COEF_08_07 */
+#define ADDA_IIR_COEF_08_07_SFT                               0
+#define ADDA_IIR_COEF_08_07_MASK                              0xffffffff
+#define ADDA_IIR_COEF_08_07_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_IIR_COEF_10_09 */
+#define ADDA_IIR_COEF_10_09_SFT                               0
+#define ADDA_IIR_COEF_10_09_MASK                              0xffffffff
+#define ADDA_IIR_COEF_10_09_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_02_01 */
+#define ADDA_ULCF_CFG_02_01_SFT                               0
+#define ADDA_ULCF_CFG_02_01_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_02_01_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_04_03 */
+#define ADDA_ULCF_CFG_04_03_SFT                               0
+#define ADDA_ULCF_CFG_04_03_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_04_03_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_06_05 */
+#define ADDA_ULCF_CFG_06_05_SFT                               0
+#define ADDA_ULCF_CFG_06_05_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_06_05_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_08_07 */
+#define ADDA_ULCF_CFG_08_07_SFT                               0
+#define ADDA_ULCF_CFG_08_07_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_08_07_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_10_09 */
+#define ADDA_ULCF_CFG_10_09_SFT                               0
+#define ADDA_ULCF_CFG_10_09_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_10_09_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_12_11 */
+#define ADDA_ULCF_CFG_12_11_SFT                               0
+#define ADDA_ULCF_CFG_12_11_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_12_11_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_14_13 */
+#define ADDA_ULCF_CFG_14_13_SFT                               0
+#define ADDA_ULCF_CFG_14_13_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_14_13_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_16_15 */
+#define ADDA_ULCF_CFG_16_15_SFT                               0
+#define ADDA_ULCF_CFG_16_15_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_16_15_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_18_17 */
+#define ADDA_ULCF_CFG_18_17_SFT                               0
+#define ADDA_ULCF_CFG_18_17_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_18_17_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_20_19 */
+#define ADDA_ULCF_CFG_20_19_SFT                               0
+#define ADDA_ULCF_CFG_20_19_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_20_19_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_22_21 */
+#define ADDA_ULCF_CFG_22_21_SFT                               0
+#define ADDA_ULCF_CFG_22_21_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_22_21_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_24_23 */
+#define ADDA_ULCF_CFG_24_23_SFT                               0
+#define ADDA_ULCF_CFG_24_23_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_24_23_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_26_25 */
+#define ADDA_ULCF_CFG_26_25_SFT                               0
+#define ADDA_ULCF_CFG_26_25_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_26_25_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_28_27 */
+#define ADDA_ULCF_CFG_28_27_SFT                               0
+#define ADDA_ULCF_CFG_28_27_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_28_27_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_30_29 */
+#define ADDA_ULCF_CFG_30_29_SFT                               0
+#define ADDA_ULCF_CFG_30_29_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_30_29_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_32_31 */
+#define ADDA_ULCF_CFG_32_31_SFT                               0
+#define ADDA_ULCF_CFG_32_31_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_32_31_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_IP_VERSION */
+#define ADDA_ULCF_IP_VERSION_SFT                              0
+#define ADDA_ULCF_IP_VERSION_MASK                             0xffffffff
+#define ADDA_ULCF_IP_VERSION_MASK_SFT                         (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_SRC_CON0 */
+#define ULCF_CFG_EN_CTL_SFT                                   31
+#define ULCF_CFG_EN_CTL_MASK                                  0x1
+#define ULCF_CFG_EN_CTL_MASK_SFT                              (0x1 << 31)
+#define UL_DMIC_PHASE_SEL_CH1_SFT                             27
+#define UL_DMIC_PHASE_SEL_CH1_MASK                            0x7
+#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT                        (0x7 << 27)
+#define UL_DMIC_PHASE_SEL_CH2_SFT                             24
+#define UL_DMIC_PHASE_SEL_CH2_MASK                            0x7
+#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT                        (0x7 << 24)
+#define UL_DMIC_TWO_WIRE_CTL_SFT                              23
+#define UL_DMIC_TWO_WIRE_CTL_MASK                             0x1
+#define UL_DMIC_TWO_WIRE_CTL_MASK_SFT                         (0x1 << 23)
+#define UL_MODE_3P25M_CH2_CTL_SFT                             22
+#define UL_MODE_3P25M_CH2_CTL_MASK                            0x1
+#define UL_MODE_3P25M_CH2_CTL_MASK_SFT                        (0x1 << 22)
+#define UL_MODE_3P25M_CH1_CTL_SFT                             21
+#define UL_MODE_3P25M_CH1_CTL_MASK                            0x1
+#define UL_MODE_3P25M_CH1_CTL_MASK_SFT                        (0x1 << 21)
+#define UL_VOICE_MODE_CH1_CH2_CTL_SFT                         17
+#define UL_VOICE_MODE_CH1_CH2_CTL_MASK                        0x7
+#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT                    (0x7 << 17)
+#define UL_AP_DMIC_ON_SFT                                     16
+#define UL_AP_DMIC_ON_MASK                                    0x1
+#define UL_AP_DMIC_ON_MASK_SFT                                (0x1 << 16)
+#define DMIC_LOW_POWER_MODE_CTL_SFT                           14
+#define DMIC_LOW_POWER_MODE_CTL_MASK                          0x3
+#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT                      (0x3 << 14)
+#define UL_DISABLE_HW_CG_CTL_SFT                              12
+#define UL_DISABLE_HW_CG_CTL_MASK                             0x1
+#define UL_DISABLE_HW_CG_CTL_MASK_SFT                         (0x1 << 12)
+#define AMIC_26M_SEL_CTL_SFT                                  11
+#define AMIC_26M_SEL_CTL_MASK                                 0x1
+#define AMIC_26M_SEL_CTL_MASK_SFT                             (0x1 << 11)
+#define UL_IIR_ON_TMP_CTL_SFT                                 10
+#define UL_IIR_ON_TMP_CTL_MASK                                0x1
+#define UL_IIR_ON_TMP_CTL_MASK_SFT                            (0x1 << 10)
+#define UL_IIRMODE_CTL_SFT                                    7
+#define UL_IIRMODE_CTL_MASK                                   0x7
+#define UL_IIRMODE_CTL_MASK_SFT                               (0x7 << 7)
+#define DIGMIC_4P33M_SEL_SFT                                  6
+#define DIGMIC_4P33M_SEL_MASK                                 0x1
+#define DIGMIC_4P33M_SEL_MASK_SFT                             (0x1 << 6)
+#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT                       5
+#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK                      0x1
+#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT                  (0x1 << 5)
+#define AMIC_6P5M_SEL_CTL_SFT                                 4
+#define AMIC_6P5M_SEL_CTL_MASK                                0x1
+#define AMIC_6P5M_SEL_CTL_MASK_SFT                            (0x1 << 4)
+#define AMIC_1P625M_SEL_CTL_SFT                               3
+#define AMIC_1P625M_SEL_CTL_MASK                              0x1
+#define AMIC_1P625M_SEL_CTL_MASK_SFT                          (0x1 << 3)
+#define UL_LOOP_BACK_MODE_CTL_SFT                             2
+#define UL_LOOP_BACK_MODE_CTL_MASK                            0x1
+#define UL_LOOP_BACK_MODE_CTL_MASK_SFT                        (0x1 << 2)
+#define UL_SDM_3_LEVEL_CTL_SFT                                1
+#define UL_SDM_3_LEVEL_CTL_MASK                               0x1
+#define UL_SDM_3_LEVEL_CTL_MASK_SFT                           (0x1 << 1)
+#define UL_SRC_ON_TMP_CTL_SFT                                 0
+#define UL_SRC_ON_TMP_CTL_MASK                                0x1
+#define UL_SRC_ON_TMP_CTL_MASK_SFT                            (0x1 << 0)
+
+/* AFE_ADDA_UL2_SRC_CON1 */
+#define ADDA_UL_GAIN_VALUE_SFT                                16
+#define ADDA_UL_GAIN_VALUE_MASK                               0xffff
+#define ADDA_UL_GAIN_VALUE_MASK_SFT                           (0xffff << 16)
+#define ADDA_UL_POSTIVEGAIN_SFT                               12
+#define ADDA_UL_POSTIVEGAIN_MASK                              0x7
+#define ADDA_UL_POSTIVEGAIN_MASK_SFT                          (0x7 << 12)
+#define ADDA_UL_ODDTAP_MODE_SFT                               11
+#define ADDA_UL_ODDTAP_MODE_MASK                              0x1
+#define ADDA_UL_ODDTAP_MODE_MASK_SFT                          (0x1 << 11)
+#define ADDA_UL_HALF_TAP_NUM_SFT                              5
+#define ADDA_UL_HALF_TAP_NUM_MASK                             0x3f
+#define ADDA_UL_HALF_TAP_NUM_MASK_SFT                         (0x3f << 5)
+#define FIFO_SOFT_RST_SFT                                     4
+#define FIFO_SOFT_RST_MASK                                    0x1
+#define FIFO_SOFT_RST_MASK_SFT                                (0x1 << 4)
+#define FIFO_SOFT_RST_EN_SFT                                  3
+#define FIFO_SOFT_RST_EN_MASK                                 0x1
+#define FIFO_SOFT_RST_EN_MASK_SFT                             (0x1 << 3)
+#define LR_SWAP_SFT                                           2
+#define LR_SWAP_MASK                                          0x1
+#define LR_SWAP_MASK_SFT                                      (0x1 << 2)
+#define GAIN_MODE_SFT                                         0
+#define GAIN_MODE_MASK                                        0x3
+#define GAIN_MODE_MASK_SFT                                    (0x3 << 0)
+
+/* AFE_ADDA_UL2_SRC_CON2 */
+#define C_DAC_EN_CTL_SFT                                      27
+#define C_DAC_EN_CTL_MASK                                     0x1
+#define C_DAC_EN_CTL_MASK_SFT                                 (0x1 << 27)
+#define C_MUTE_SW_CTL_SFT                                     26
+#define C_MUTE_SW_CTL_MASK                                    0x1
+#define C_MUTE_SW_CTL_MASK_SFT                                (0x1 << 26)
+#define C_AMP_DIV_CH2_CTL_SFT                                 21
+#define C_AMP_DIV_CH2_CTL_MASK                                0x7
+#define C_AMP_DIV_CH2_CTL_MASK_SFT                            (0x7 << 21)
+#define C_FREQ_DIV_CH2_CTL_SFT                                16
+#define C_FREQ_DIV_CH2_CTL_MASK                               0x1f
+#define C_FREQ_DIV_CH2_CTL_MASK_SFT                           (0x1f << 16)
+#define C_SINE_MODE_CH2_CTL_SFT                               12
+#define C_SINE_MODE_CH2_CTL_MASK                              0xf
+#define C_SINE_MODE_CH2_CTL_MASK_SFT                          (0xf << 12)
+#define C_AMP_DIV_CH1_CTL_SFT                                 9
+#define C_AMP_DIV_CH1_CTL_MASK                                0x7
+#define C_AMP_DIV_CH1_CTL_MASK_SFT                            (0x7 << 9)
+#define C_FREQ_DIV_CH1_CTL_SFT                                4
+#define C_FREQ_DIV_CH1_CTL_MASK                               0x1f
+#define C_FREQ_DIV_CH1_CTL_MASK_SFT                           (0x1f << 4)
+#define C_SINE_MODE_CH1_CTL_SFT                               0
+#define C_SINE_MODE_CH1_CTL_MASK                              0xf
+#define C_SINE_MODE_CH1_CTL_MASK_SFT                          (0xf << 0)
+
+/* AFE_ADDA_UL2_SRC_DEBUG */
+#define UL_SLT_CNT_FLAG_RESET_CTL_SFT                         16
+#define UL_SLT_CNT_FLAG_RESET_CTL_MASK                        0x1
+#define UL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT                    (0x1 << 16)
+#define FIFO_DIGMIC_TESTIN_SFT                                12
+#define FIFO_DIGMIC_TESTIN_MASK                               0x3
+#define FIFO_DIGMIC_TESTIN_MASK_SFT                           (0x3 << 12)
+#define FIFO_DIGMIC_WDATA_TESTEN_SFT                          11
+#define FIFO_DIGMIC_WDATA_TESTEN_MASK                         0x1
+#define FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT                     (0x1 << 11)
+#define SLT_CNT_THD_CTL_SFT                                   0
+#define SLT_CNT_THD_CTL_MASK                                  0x7ff
+#define SLT_CNT_THD_CTL_MASK_SFT                              (0x7ff << 0)
+
+/* AFE_ADDA_UL2_SRC_DEBUG_MON0 */
+#define SLT_CNT_FLAG_CTL_SFT                                  16
+#define SLT_CNT_FLAG_CTL_MASK                                 0x1
+#define SLT_CNT_FLAG_CTL_MASK_SFT                             (0x1 << 16)
+#define SLT_COUNTER_CTL_SFT                                   0
+#define SLT_COUNTER_CTL_MASK                                  0x7ff
+#define SLT_COUNTER_CTL_MASK_SFT                              (0x7ff << 0)
+
+/* AFE_ADDA_UL2_IIR_COEF_02_01 */
+#define ADDA_IIR_COEF_02_01_SFT                               0
+#define ADDA_IIR_COEF_02_01_MASK                              0xffffffff
+#define ADDA_IIR_COEF_02_01_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_IIR_COEF_04_03 */
+#define ADDA_IIR_COEF_04_03_SFT                               0
+#define ADDA_IIR_COEF_04_03_MASK                              0xffffffff
+#define ADDA_IIR_COEF_04_03_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_IIR_COEF_06_05 */
+#define ADDA_IIR_COEF_06_05_SFT                               0
+#define ADDA_IIR_COEF_06_05_MASK                              0xffffffff
+#define ADDA_IIR_COEF_06_05_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_IIR_COEF_08_07 */
+#define ADDA_IIR_COEF_08_07_SFT                               0
+#define ADDA_IIR_COEF_08_07_MASK                              0xffffffff
+#define ADDA_IIR_COEF_08_07_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_IIR_COEF_10_09 */
+#define ADDA_IIR_COEF_10_09_SFT                               0
+#define ADDA_IIR_COEF_10_09_MASK                              0xffffffff
+#define ADDA_IIR_COEF_10_09_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_02_01 */
+#define ADDA_ULCF_CFG_02_01_SFT                               0
+#define ADDA_ULCF_CFG_02_01_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_02_01_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_04_03 */
+#define ADDA_ULCF_CFG_04_03_SFT                               0
+#define ADDA_ULCF_CFG_04_03_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_04_03_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_06_05 */
+#define ADDA_ULCF_CFG_06_05_SFT                               0
+#define ADDA_ULCF_CFG_06_05_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_06_05_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_08_07 */
+#define ADDA_ULCF_CFG_08_07_SFT                               0
+#define ADDA_ULCF_CFG_08_07_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_08_07_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_10_09 */
+#define ADDA_ULCF_CFG_10_09_SFT                               0
+#define ADDA_ULCF_CFG_10_09_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_10_09_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_12_11 */
+#define ADDA_ULCF_CFG_12_11_SFT                               0
+#define ADDA_ULCF_CFG_12_11_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_12_11_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_14_13 */
+#define ADDA_ULCF_CFG_14_13_SFT                               0
+#define ADDA_ULCF_CFG_14_13_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_14_13_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_16_15 */
+#define ADDA_ULCF_CFG_16_15_SFT                               0
+#define ADDA_ULCF_CFG_16_15_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_16_15_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_18_17 */
+#define ADDA_ULCF_CFG_18_17_SFT                               0
+#define ADDA_ULCF_CFG_18_17_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_18_17_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_20_19 */
+#define ADDA_ULCF_CFG_20_19_SFT                               0
+#define ADDA_ULCF_CFG_20_19_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_20_19_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_22_21 */
+#define ADDA_ULCF_CFG_22_21_SFT                               0
+#define ADDA_ULCF_CFG_22_21_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_22_21_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_24_23 */
+#define ADDA_ULCF_CFG_24_23_SFT                               0
+#define ADDA_ULCF_CFG_24_23_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_24_23_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_26_25 */
+#define ADDA_ULCF_CFG_26_25_SFT                               0
+#define ADDA_ULCF_CFG_26_25_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_26_25_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_28_27 */
+#define ADDA_ULCF_CFG_28_27_SFT                               0
+#define ADDA_ULCF_CFG_28_27_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_28_27_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_30_29 */
+#define ADDA_ULCF_CFG_30_29_SFT                               0
+#define ADDA_ULCF_CFG_30_29_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_30_29_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_ULCF_CFG_32_31 */
+#define ADDA_ULCF_CFG_32_31_SFT                               0
+#define ADDA_ULCF_CFG_32_31_MASK                              0xffffffff
+#define ADDA_ULCF_CFG_32_31_MASK_SFT                          (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_IP_VERSION */
+#define ADDA_ULCF_IP_VERSION_SFT                              0
+#define ADDA_ULCF_IP_VERSION_MASK                             0xffffffff
+#define ADDA_ULCF_IP_VERSION_MASK_SFT                         (0xffffffff << 0)
+
+/* AFE_ADDA_PROXIMITY_CON0 */
+#define PROXIMITY_CH1_ON_SFT                                  12
+#define PROXIMITY_CH1_ON_MASK                                 0x1
+#define PROXIMITY_CH1_ON_MASK_SFT                             (0x1 << 12)
+#define PROXIMITY_CH1_SEL_SFT                                 8
+#define PROXIMITY_CH1_SEL_MASK                                0xf
+#define PROXIMITY_CH1_SEL_MASK_SFT                            (0xf << 8)
+#define PROXIMITY_CH2_ON_SFT                                  4
+#define PROXIMITY_CH2_ON_MASK                                 0x1
+#define PROXIMITY_CH2_ON_MASK_SFT                             (0x1 << 4)
+#define PROXIMITY_CH2_SEL_SFT                                 0
+#define PROXIMITY_CH2_SEL_MASK                                0xf
+#define PROXIMITY_CH2_SEL_MASK_SFT                            (0xf << 0)
+
+/* AFE_ADDA_ULSRC_PHASE_CON0 */
+#define DMIC1_PHASE_FCLK_SEL_SFT                              30
+#define DMIC1_PHASE_FCLK_SEL_MASK                             0x3
+#define DMIC1_PHASE_FCLK_SEL_MASK_SFT                         (0x3 << 30)
+#define DMIC0_PHASE_FCLK_SEL_SFT                              28
+#define DMIC0_PHASE_FCLK_SEL_MASK                             0x3
+#define DMIC0_PHASE_FCLK_SEL_MASK_SFT                         (0x3 << 28)
+#define UL3_PHASE_FCLK_SEL_SFT                                26
+#define UL3_PHASE_FCLK_SEL_MASK                               0x3
+#define UL3_PHASE_FCLK_SEL_MASK_SFT                           (0x3 << 26)
+#define UL2_PHASE_FCLK_SEL_SFT                                24
+#define UL2_PHASE_FCLK_SEL_MASK                               0x3
+#define UL2_PHASE_FCLK_SEL_MASK_SFT                           (0x3 << 24)
+#define UL1_PHASE_FCLK_SEL_SFT                                22
+#define UL1_PHASE_FCLK_SEL_MASK                               0x3
+#define UL1_PHASE_FCLK_SEL_MASK_SFT                           (0x3 << 22)
+#define UL0_PHASE_FCLK_SEL_SFT                                20
+#define UL0_PHASE_FCLK_SEL_MASK                               0x3
+#define UL0_PHASE_FCLK_SEL_MASK_SFT                           (0x3 << 20)
+#define UL_PHASE_SYNC_FCLK_2_ON_SFT                           18
+#define UL_PHASE_SYNC_FCLK_2_ON_MASK                          0x1
+#define UL_PHASE_SYNC_FCLK_2_ON_MASK_SFT                      (0x1 << 18)
+#define UL_PHASE_SYNC_FCLK_1_ON_SFT                           17
+#define UL_PHASE_SYNC_FCLK_1_ON_MASK                          0x1
+#define UL_PHASE_SYNC_FCLK_1_ON_MASK_SFT                      (0x1 << 17)
+#define UL_PHASE_SYNC_FCLK_0_ON_SFT                           16
+#define UL_PHASE_SYNC_FCLK_0_ON_MASK                          0x1
+#define UL_PHASE_SYNC_FCLK_0_ON_MASK_SFT                      (0x1 << 16)
+#define DMIC1_PHASE_HCLK_SEL_SFT                              14
+#define DMIC1_PHASE_HCLK_SEL_MASK                             0x3
+#define DMIC1_PHASE_HCLK_SEL_MASK_SFT                         (0x3 << 14)
+#define DMIC0_PHASE_HCLK_SEL_SFT                              12
+#define DMIC0_PHASE_HCLK_SEL_MASK                             0x3
+#define DMIC0_PHASE_HCLK_SEL_MASK_SFT                         (0x3 << 12)
+#define UL3_PHASE_HCLK_SEL_SFT                                10
+#define UL3_PHASE_HCLK_SEL_MASK                               0x3
+#define UL3_PHASE_HCLK_SEL_MASK_SFT                           (0x3 << 10)
+#define UL2_PHASE_HCLK_SEL_SFT                                8
+#define UL2_PHASE_HCLK_SEL_MASK                               0x3
+#define UL2_PHASE_HCLK_SEL_MASK_SFT                           (0x3 << 8)
+#define UL1_PHASE_HCLK_SEL_SFT                                6
+#define UL1_PHASE_HCLK_SEL_MASK                               0x3
+#define UL1_PHASE_HCLK_SEL_MASK_SFT                           (0x3 << 6)
+#define UL0_PHASE_HCLK_SEL_SFT                                4
+#define UL0_PHASE_HCLK_SEL_MASK                               0x3
+#define UL0_PHASE_HCLK_SEL_MASK_SFT                           (0x3 << 4)
+#define UL_PHASE_SYNC_HCLK_2_ON_SFT                           2
+#define UL_PHASE_SYNC_HCLK_2_ON_MASK                          0x1
+#define UL_PHASE_SYNC_HCLK_2_ON_MASK_SFT                      (0x1 << 2)
+#define UL_PHASE_SYNC_HCLK_1_ON_SFT                           1
+#define UL_PHASE_SYNC_HCLK_1_ON_MASK                          0x1
+#define UL_PHASE_SYNC_HCLK_1_ON_MASK_SFT                      (0x1 << 1)
+#define UL_PHASE_SYNC_HCLK_0_ON_SFT                           0
+#define UL_PHASE_SYNC_HCLK_0_ON_MASK                          0x1
+#define UL_PHASE_SYNC_HCLK_0_ON_MASK_SFT                      (0x1 << 0)
+
+/* AFE_ADDA_ULSRC_PHASE_CON1 */
+#define DMIC_CLK_PHASE_SYNC_SET_SFT                           31
+#define DMIC_CLK_PHASE_SYNC_SET_MASK                          0x1
+#define DMIC_CLK_PHASE_SYNC_SET_MASK_SFT                      (0x1 << 31)
+#define DMIC1_PHASE_SYNC_FCLK_SET_SFT                         11
+#define DMIC1_PHASE_SYNC_FCLK_SET_MASK                        0x1
+#define DMIC1_PHASE_SYNC_FCLK_SET_MASK_SFT                    (0x1 << 11)
+#define DMIC1_PHASE_SYNC_HCLK_SET_SFT                         10
+#define DMIC1_PHASE_SYNC_HCLK_SET_MASK                        0x1
+#define DMIC1_PHASE_SYNC_HCLK_SET_MASK_SFT                    (0x1 << 10)
+#define DMIC0_PHASE_SYNC_FCLK_SET_SFT                         9
+#define DMIC0_PHASE_SYNC_FCLK_SET_MASK                        0x1
+#define DMIC0_PHASE_SYNC_FCLK_SET_MASK_SFT                    (0x1 << 9)
+#define DMIC0_PHASE_SYNC_HCLK_SET_SFT                         8
+#define DMIC0_PHASE_SYNC_HCLK_SET_MASK                        0x1
+#define DMIC0_PHASE_SYNC_HCLK_SET_MASK_SFT                    (0x1 << 8)
+#define UL3_PHASE_SYNC_FCLK_SET_SFT                           7
+#define UL3_PHASE_SYNC_FCLK_SET_MASK                          0x1
+#define UL3_PHASE_SYNC_FCLK_SET_MASK_SFT                      (0x1 << 7)
+#define UL3_PHASE_SYNC_HCLK_SET_SFT                           6
+#define UL3_PHASE_SYNC_HCLK_SET_MASK                          0x1
+#define UL3_PHASE_SYNC_HCLK_SET_MASK_SFT                      (0x1 << 6)
+#define UL2_PHASE_SYNC_FCLK_SET_SFT                           5
+#define UL2_PHASE_SYNC_FCLK_SET_MASK                          0x1
+#define UL2_PHASE_SYNC_FCLK_SET_MASK_SFT                      (0x1 << 5)
+#define UL2_PHASE_SYNC_HCLK_SET_SFT                           4
+#define UL2_PHASE_SYNC_HCLK_SET_MASK                          0x1
+#define UL2_PHASE_SYNC_HCLK_SET_MASK_SFT                      (0x1 << 4)
+#define UL1_PHASE_SYNC_FCLK_SET_SFT                           3
+#define UL1_PHASE_SYNC_FCLK_SET_MASK                          0x1
+#define UL1_PHASE_SYNC_FCLK_SET_MASK_SFT                      (0x1 << 3)
+#define UL1_PHASE_SYNC_HCLK_SET_SFT                           2
+#define UL1_PHASE_SYNC_HCLK_SET_MASK                          0x1
+#define UL1_PHASE_SYNC_HCLK_SET_MASK_SFT                      (0x1 << 2)
+#define UL0_PHASE_SYNC_FCLK_SET_SFT                           1
+#define UL0_PHASE_SYNC_FCLK_SET_MASK                          0x1
+#define UL0_PHASE_SYNC_FCLK_SET_MASK_SFT                      (0x1 << 1)
+#define UL0_PHASE_SYNC_HCLK_SET_SFT                           0
+#define UL0_PHASE_SYNC_HCLK_SET_MASK                          0x1
+#define UL0_PHASE_SYNC_HCLK_SET_MASK_SFT                      (0x1 << 0)
+
+/* AFE_ADDA_ULSRC_PHASE_CON2 */
+#define DMIC1_PHASE_SYNC_1X_EN_SEL_SFT                        26
+#define DMIC1_PHASE_SYNC_1X_EN_SEL_MASK                       0x3
+#define DMIC1_PHASE_SYNC_1X_EN_SEL_MASK_SFT                   (0x3 << 26)
+#define DMIC0_PHASE_SYNC_1X_EN_SEL_SFT                        24
+#define DMIC0_PHASE_SYNC_1X_EN_SEL_MASK                       0x3
+#define DMIC0_PHASE_SYNC_1X_EN_SEL_MASK_SFT                   (0x3 << 24)
+#define UL3_PHASE_SYNC_1X_EN_SEL_SFT                          22
+#define UL3_PHASE_SYNC_1X_EN_SEL_MASK                         0x3
+#define UL3_PHASE_SYNC_1X_EN_SEL_MASK_SFT                     (0x3 << 22)
+#define UL2_PHASE_SYNC_1X_EN_SEL_SFT                          20
+#define UL2_PHASE_SYNC_1X_EN_SEL_MASK                         0x3
+#define UL2_PHASE_SYNC_1X_EN_SEL_MASK_SFT                     (0x3 << 20)
+#define UL1_PHASE_SYNC_1X_EN_SEL_SFT                          18
+#define UL1_PHASE_SYNC_1X_EN_SEL_MASK                         0x3
+#define UL1_PHASE_SYNC_1X_EN_SEL_MASK_SFT                     (0x3 << 18)
+#define UL0_PHASE_SYNC_1X_EN_SEL_SFT                          16
+#define UL0_PHASE_SYNC_1X_EN_SEL_MASK                         0x3
+#define UL0_PHASE_SYNC_1X_EN_SEL_MASK_SFT                     (0x3 << 16)
+#define UL_PHASE_SYNC_FCLK_1X_EN_2_ON_SFT                     5
+#define UL_PHASE_SYNC_FCLK_1X_EN_2_ON_MASK                    0x1
+#define UL_PHASE_SYNC_FCLK_1X_EN_2_ON_MASK_SFT                (0x1 << 5)
+#define UL_PHASE_SYNC_FCLK_1X_EN_1_ON_SFT                     4
+#define UL_PHASE_SYNC_FCLK_1X_EN_1_ON_MASK                    0x1
+#define UL_PHASE_SYNC_FCLK_1X_EN_1_ON_MASK_SFT                (0x1 << 4)
+#define UL_PHASE_SYNC_FCLK_1X_EN_0_ON_SFT                     3
+#define UL_PHASE_SYNC_FCLK_1X_EN_0_ON_MASK                    0x1
+#define UL_PHASE_SYNC_FCLK_1X_EN_0_ON_MASK_SFT                (0x1 << 3)
+#define UL_PHASE_SYNC_HCLK_1X_EN_2_ON_SFT                     2
+#define UL_PHASE_SYNC_HCLK_1X_EN_2_ON_MASK                    0x1
+#define UL_PHASE_SYNC_HCLK_1X_EN_2_ON_MASK_SFT                (0x1 << 2)
+#define UL_PHASE_SYNC_HCLK_1X_EN_1_ON_SFT                     1
+#define UL_PHASE_SYNC_HCLK_1X_EN_1_ON_MASK                    0x1
+#define UL_PHASE_SYNC_HCLK_1X_EN_1_ON_MASK_SFT                (0x1 << 1)
+#define UL_PHASE_SYNC_HCLK_1X_EN_0_ON_SFT                     0
+#define UL_PHASE_SYNC_HCLK_1X_EN_0_ON_MASK                    0x1
+#define UL_PHASE_SYNC_HCLK_1X_EN_0_ON_MASK_SFT                (0x1 << 0)
+
+/* AFE_ADDA_ULSRC_PHASE_CON3 */
+#define DMIC1_PHASE_SYNC_SOFT_RST_SEL_SFT                     26
+#define DMIC1_PHASE_SYNC_SOFT_RST_SEL_MASK                    0x3
+#define DMIC1_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT                (0x3 << 26)
+#define DMIC0_PHASE_SYNC_SOFT_RST_SEL_SFT                     24
+#define DMIC0_PHASE_SYNC_SOFT_RST_SEL_MASK                    0x3
+#define DMIC0_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT                (0x3 << 24)
+#define UL3_PHASE_SYNC_SOFT_RST_SEL_SFT                       22
+#define UL3_PHASE_SYNC_SOFT_RST_SEL_MASK                      0x3
+#define UL3_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT                  (0x3 << 22)
+#define UL2_PHASE_SYNC_SOFT_RST_SEL_SFT                       20
+#define UL2_PHASE_SYNC_SOFT_RST_SEL_MASK                      0x3
+#define UL2_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT                  (0x3 << 20)
+#define UL1_PHASE_SYNC_SOFT_RST_SEL_SFT                       18
+#define UL1_PHASE_SYNC_SOFT_RST_SEL_MASK                      0x3
+#define UL1_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT                  (0x3 << 18)
+#define UL0_PHASE_SYNC_SOFT_RST_SEL_SFT                       16
+#define UL0_PHASE_SYNC_SOFT_RST_SEL_MASK                      0x3
+#define UL0_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT                  (0x3 << 16)
+#define DMIC1_PHASE_SYNC_CH1_FIFO_SEL_SFT                     13
+#define DMIC1_PHASE_SYNC_CH1_FIFO_SEL_MASK                    0x1
+#define DMIC1_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT                (0x1 << 13)
+#define DMIC0_PHASE_SYNC_CH1_FIFO_SEL_SFT                     12
+#define DMIC0_PHASE_SYNC_CH1_FIFO_SEL_MASK                    0x1
+#define DMIC0_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT                (0x1 << 12)
+#define UL3_PHASE_SYNC_CH1_FIFO_SEL_SFT                       11
+#define UL3_PHASE_SYNC_CH1_FIFO_SEL_MASK                      0x1
+#define UL3_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT                  (0x1 << 11)
+#define UL2_PHASE_SYNC_CH1_FIFO_SEL_SFT                       10
+#define UL2_PHASE_SYNC_CH1_FIFO_SEL_MASK                      0x1
+#define UL2_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT                  (0x1 << 10)
+#define UL1_PHASE_SYNC_CH1_FIFO_SEL_SFT                       9
+#define UL1_PHASE_SYNC_CH1_FIFO_SEL_MASK                      0x1
+#define UL1_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT                  (0x1 << 9)
+#define UL0_PHASE_SYNC_CH1_FIFO_SEL_SFT                       8
+#define UL0_PHASE_SYNC_CH1_FIFO_SEL_MASK                      0x1
+#define UL0_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT                  (0x1 << 8)
+#define UL_PHASE_SYNC_SOFT_RST_EN_2_ON_SFT                    5
+#define UL_PHASE_SYNC_SOFT_RST_EN_2_ON_MASK                   0x1
+#define UL_PHASE_SYNC_SOFT_RST_EN_2_ON_MASK_SFT               (0x1 << 5)
+#define UL_PHASE_SYNC_SOFT_RST_EN_1_ON_SFT                    4
+#define UL_PHASE_SYNC_SOFT_RST_EN_1_ON_MASK                   0x1
+#define UL_PHASE_SYNC_SOFT_RST_EN_1_ON_MASK_SFT               (0x1 << 4)
+#define UL_PHASE_SYNC_SOFT_RST_EN_0_ON_SFT                    3
+#define UL_PHASE_SYNC_SOFT_RST_EN_0_ON_MASK                   0x1
+#define UL_PHASE_SYNC_SOFT_RST_EN_0_ON_MASK_SFT               (0x1 << 3)
+#define UL_PHASE_SYNC_SOFT_RST_2_ON_SFT                       2
+#define UL_PHASE_SYNC_SOFT_RST_2_ON_MASK                      0x1
+#define UL_PHASE_SYNC_SOFT_RST_2_ON_MASK_SFT                  (0x1 << 2)
+#define UL_PHASE_SYNC_SOFT_RST_1_ON_SFT                       1
+#define UL_PHASE_SYNC_SOFT_RST_1_ON_MASK                      0x1
+#define UL_PHASE_SYNC_SOFT_RST_1_ON_MASK_SFT                  (0x1 << 1)
+#define UL_PHASE_SYNC_SOFT_RST_0_ON_SFT                       0
+#define UL_PHASE_SYNC_SOFT_RST_0_ON_MASK                      0x1
+#define UL_PHASE_SYNC_SOFT_RST_0_ON_MASK_SFT                  (0x1 << 0)
+
+/* AFE_MTKAIF_IPM_VER_MON */
+#define RG_MTKAIF_IPM_VER_MON_SFT                             0
+#define RG_MTKAIF_IPM_VER_MON_MASK                            0xffffffff
+#define RG_MTKAIF_IPM_VER_MON_MASK_SFT                        (0xffffffff << 0)
+
+/* AFE_MTKAIF_MON_SEL */
+#define RG_MTKAIF_MON_SEL_SFT                                 0
+#define RG_MTKAIF_MON_SEL_MASK                                0xff
+#define RG_MTKAIF_MON_SEL_MASK_SFT                            (0xff << 0)
+
+/* AFE_MTKAIF_MON */
+#define RG_MTKAIF_MON_SFT                                     0
+#define RG_MTKAIF_MON_MASK                                    0xffffffff
+#define RG_MTKAIF_MON_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_MTKAIF0_CFG0 */
+#define RG_MTKAIF0_RXIF_CLKINV_SFT                            31
+#define RG_MTKAIF0_RXIF_CLKINV_MASK                           0x1
+#define RG_MTKAIF0_RXIF_CLKINV_MASK_SFT                       (0x1 << 31)
+#define RG_MTKAIF0_RXIF_BYPASS_SRC_SFT                        17
+#define RG_MTKAIF0_RXIF_BYPASS_SRC_MASK                       0x1
+#define RG_MTKAIF0_RXIF_BYPASS_SRC_MASK_SFT                   (0x1 << 17)
+#define RG_MTKAIF0_RXIF_PROTOCOL2_SFT                         16
+#define RG_MTKAIF0_RXIF_PROTOCOL2_MASK                        0x1
+#define RG_MTKAIF0_RXIF_PROTOCOL2_MASK_SFT                    (0x1 << 16)
+#define RG_MTKAIF0_TXIF_NLE_DEBUG_SFT                         8
+#define RG_MTKAIF0_TXIF_NLE_DEBUG_MASK                        0x1
+#define RG_MTKAIF0_TXIF_NLE_DEBUG_MASK_SFT                    (0x1 << 8)
+#define RG_MTKAIF0_TXIF_BYPASS_SRC_SFT                        5
+#define RG_MTKAIF0_TXIF_BYPASS_SRC_MASK                       0x1
+#define RG_MTKAIF0_TXIF_BYPASS_SRC_MASK_SFT                   (0x1 << 5)
+#define RG_MTKAIF0_TXIF_PROTOCOL2_SFT                         4
+#define RG_MTKAIF0_TXIF_PROTOCOL2_MASK                        0x1
+#define RG_MTKAIF0_TXIF_PROTOCOL2_MASK_SFT                    (0x1 << 4)
+#define RG_MTKAIF0_TXIF_8TO5_SFT                              2
+#define RG_MTKAIF0_TXIF_8TO5_MASK                             0x1
+#define RG_MTKAIF0_TXIF_8TO5_MASK_SFT                         (0x1 << 2)
+#define RG_MTKAIF0_RXIF_8TO5_SFT                              1
+#define RG_MTKAIF0_RXIF_8TO5_MASK                             0x1
+#define RG_MTKAIF0_RXIF_8TO5_MASK_SFT                         (0x1 << 1)
+#define RG_MTKAIF0_TX2RX_LOOPBACK1_SFT                        0
+#define RG_MTKAIF0_TX2RX_LOOPBACK1_MASK                       0x1
+#define RG_MTKAIF0_TX2RX_LOOPBACK1_MASK_SFT                   (0x1 << 0)
+
+/* AFE_MTKAIF0_TX_CFG0 */
+#define RG_MTKAIF0_TXIF_NLE_FIFO_SWAP_SFT                     23
+#define RG_MTKAIF0_TXIF_NLE_FIFO_SWAP_MASK                    0x1
+#define RG_MTKAIF0_TXIF_NLE_FIFO_SWAP_MASK_SFT                (0x1 << 23)
+#define RG_MTKAIF0_TXIF_NLE_FIFO_RSP_SFT                      20
+#define RG_MTKAIF0_TXIF_NLE_FIFO_RSP_MASK                     0x7
+#define RG_MTKAIF0_TXIF_NLE_FIFO_RSP_MASK_SFT                 (0x7 << 20)
+#define RG_MTKAIF0_TXIF_FIFO_SWAP_SFT                         15
+#define RG_MTKAIF0_TXIF_FIFO_SWAP_MASK                        0x1
+#define RG_MTKAIF0_TXIF_FIFO_SWAP_MASK_SFT                    (0x1 << 15)
+#define RG_MTKAIF0_TXIF_FIFO_RSP_SFT                          12
+#define RG_MTKAIF0_TXIF_FIFO_RSP_MASK                         0x7
+#define RG_MTKAIF0_TXIF_FIFO_RSP_MASK_SFT                     (0x7 << 12)
+#define RG_MTKAIF0_TXIF_SYNC_WORD1_SFT                        4
+#define RG_MTKAIF0_TXIF_SYNC_WORD1_MASK                       0x7
+#define RG_MTKAIF0_TXIF_SYNC_WORD1_MASK_SFT                   (0x7 << 4)
+#define RG_MTKAIF0_TXIF_SYNC_WORD0_SFT                        0
+#define RG_MTKAIF0_TXIF_SYNC_WORD0_MASK                       0x7
+#define RG_MTKAIF0_TXIF_SYNC_WORD0_MASK_SFT                   (0x7 << 0)
+
+/* AFE_MTKAIF0_RX_CFG0 */
+#define RG_MTKAIF0_RXIF_VOICE_MODE_SFT                        20
+#define RG_MTKAIF0_RXIF_VOICE_MODE_MASK                       0xf
+#define RG_MTKAIF0_RXIF_VOICE_MODE_MASK_SFT                   (0xf << 20)
+#define RG_MTKAIF0_RXIF_DETECT_ON_SFT                         16
+#define RG_MTKAIF0_RXIF_DETECT_ON_MASK                        0x1
+#define RG_MTKAIF0_RXIF_DETECT_ON_MASK_SFT                    (0x1 << 16)
+#define RG_MTKAIF0_RXIF_DATA_BIT_SFT                          8
+#define RG_MTKAIF0_RXIF_DATA_BIT_MASK                         0x7
+#define RG_MTKAIF0_RXIF_DATA_BIT_MASK_SFT                     (0x7 << 8)
+#define RG_MTKAIF0_RXIF_FIFO_RSP_SFT                          4
+#define RG_MTKAIF0_RXIF_FIFO_RSP_MASK                         0x7
+#define RG_MTKAIF0_RXIF_FIFO_RSP_MASK_SFT                     (0x7 << 4)
+#define RG_MTKAIF0_RXIF_DATA_MODE_SFT                         0
+#define RG_MTKAIF0_RXIF_DATA_MODE_MASK                        0x1
+#define RG_MTKAIF0_RXIF_DATA_MODE_MASK_SFT                    (0x1 << 0)
+
+/* AFE_MTKAIF0_RX_CFG1 */
+#define RG_MTKAIF0_RXIF_CLEAR_SYNC_FAIL_SFT                   28
+#define RG_MTKAIF0_RXIF_CLEAR_SYNC_FAIL_MASK                  0x1
+#define RG_MTKAIF0_RXIF_CLEAR_SYNC_FAIL_MASK_SFT              (0x1 << 28)
+#define RG_MTKAIF0_RXIF_SYNC_CNT_TABLE_SFT                    16
+#define RG_MTKAIF0_RXIF_SYNC_CNT_TABLE_MASK                   0xfff
+#define RG_MTKAIF0_RXIF_SYNC_CNT_TABLE_MASK_SFT               (0xfff << 16)
+#define RG_MTKAIF0_RXIF_SYNC_SEARCH_TABLE_SFT                 12
+#define RG_MTKAIF0_RXIF_SYNC_SEARCH_TABLE_MASK                0xf
+#define RG_MTKAIF0_RXIF_SYNC_SEARCH_TABLE_MASK_SFT            (0xf << 12)
+#define RG_MTKAIF0_RXIF_INVALID_SYNC_CHECK_ROUND_SFT          8
+#define RG_MTKAIF0_RXIF_INVALID_SYNC_CHECK_ROUND_MASK         0xf
+#define RG_MTKAIF0_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT     (0xf << 8)
+#define RG_MTKAIF0_RXIF_SYNC_CHECK_ROUND_SFT                  4
+#define RG_MTKAIF0_RXIF_SYNC_CHECK_ROUND_MASK                 0xf
+#define RG_MTKAIF0_RXIF_SYNC_CHECK_ROUND_MASK_SFT             (0xf << 4)
+
+/* AFE_MTKAIF0_RX_CFG2 */
+#define RG_MTKAIF0_RXIF_SYNC_WORD1_DISABLE_SFT                27
+#define RG_MTKAIF0_RXIF_SYNC_WORD1_DISABLE_MASK               0x1
+#define RG_MTKAIF0_RXIF_SYNC_WORD1_DISABLE_MASK_SFT           (0x1 << 27)
+#define RG_MTKAIF0_RXIF_SYNC_WORD1_SFT                        24
+#define RG_MTKAIF0_RXIF_SYNC_WORD1_MASK                       0x7
+#define RG_MTKAIF0_RXIF_SYNC_WORD1_MASK_SFT                   (0x7 << 24)
+#define RG_MTKAIF0_RXIF_SYNC_WORD0_DISABLE_SFT                23
+#define RG_MTKAIF0_RXIF_SYNC_WORD0_DISABLE_MASK               0x1
+#define RG_MTKAIF0_RXIF_SYNC_WORD0_DISABLE_MASK_SFT           (0x1 << 23)
+#define RG_MTKAIF0_RXIF_SYNC_WORD0_SFT                        20
+#define RG_MTKAIF0_RXIF_SYNC_WORD0_MASK                       0x7
+#define RG_MTKAIF0_RXIF_SYNC_WORD0_MASK_SFT                   (0x7 << 20)
+#define RG_MTKAIF0_RXIF_DELAY_CYCLE_SFT                       12
+#define RG_MTKAIF0_RXIF_DELAY_CYCLE_MASK                      0xf
+#define RG_MTKAIF0_RXIF_DELAY_CYCLE_MASK_SFT                  (0xf << 12)
+#define RG_MTKAIF0_RXIF_DELAY_DATA_SFT                        8
+#define RG_MTKAIF0_RXIF_DELAY_DATA_MASK                       0x1
+#define RG_MTKAIF0_RXIF_DELAY_DATA_MASK_SFT                   (0x1 << 8)
+
+/* AFE_MTKAIF1_CFG0 */
+#define RG_MTKAIF1_RXIF_CLKINV_ADC_SFT                        31
+#define RG_MTKAIF1_RXIF_CLKINV_ADC_MASK                       0x1
+#define RG_MTKAIF1_RXIF_CLKINV_ADC_MASK_SFT                   (0x1 << 31)
+#define RG_MTKAIF1_RXIF_BYPASS_SRC_SFT                        17
+#define RG_MTKAIF1_RXIF_BYPASS_SRC_MASK                       0x1
+#define RG_MTKAIF1_RXIF_BYPASS_SRC_MASK_SFT                   (0x1 << 17)
+#define RG_MTKAIF1_RXIF_PROTOCOL2_SFT                         16
+#define RG_MTKAIF1_RXIF_PROTOCOL2_MASK                        0x1
+#define RG_MTKAIF1_RXIF_PROTOCOL2_MASK_SFT                    (0x1 << 16)
+#define RG_MTKAIF1_TXIF_NLE_DEBUG_SFT                         8
+#define RG_MTKAIF1_TXIF_NLE_DEBUG_MASK                        0x1
+#define RG_MTKAIF1_TXIF_NLE_DEBUG_MASK_SFT                    (0x1 << 8)
+#define RG_MTKAIF1_TXIF_BYPASS_SRC_SFT                        5
+#define RG_MTKAIF1_TXIF_BYPASS_SRC_MASK                       0x1
+#define RG_MTKAIF1_TXIF_BYPASS_SRC_MASK_SFT                   (0x1 << 5)
+#define RG_MTKAIF1_TXIF_PROTOCOL2_SFT                         4
+#define RG_MTKAIF1_TXIF_PROTOCOL2_MASK                        0x1
+#define RG_MTKAIF1_TXIF_PROTOCOL2_MASK_SFT                    (0x1 << 4)
+#define RG_MTKAIF1_TXIF_8TO5_SFT                              2
+#define RG_MTKAIF1_TXIF_8TO5_MASK                             0x1
+#define RG_MTKAIF1_TXIF_8TO5_MASK_SFT                         (0x1 << 2)
+#define RG_MTKAIF1_RXIF_8TO5_SFT                              1
+#define RG_MTKAIF1_RXIF_8TO5_MASK                             0x1
+#define RG_MTKAIF1_RXIF_8TO5_MASK_SFT                         (0x1 << 1)
+#define RG_MTKAIF1_IF_LOOPBACK1_SFT                           0
+#define RG_MTKAIF1_IF_LOOPBACK1_MASK                          0x1
+#define RG_MTKAIF1_IF_LOOPBACK1_MASK_SFT                      (0x1 << 0)
+
+/* AFE_MTKAIF1_TX_CFG0 */
+#define RG_MTKAIF1_TXIF_NLE_FIFO_SWAP_SFT                     23
+#define RG_MTKAIF1_TXIF_NLE_FIFO_SWAP_MASK                    0x1
+#define RG_MTKAIF1_TXIF_NLE_FIFO_SWAP_MASK_SFT                (0x1 << 23)
+#define RG_MTKAIF1_TXIF_NLE_FIFO_RSP_SFT                      20
+#define RG_MTKAIF1_TXIF_NLE_FIFO_RSP_MASK                     0x7
+#define RG_MTKAIF1_TXIF_NLE_FIFO_RSP_MASK_SFT                 (0x7 << 20)
+#define RG_MTKAIF1_TXIF_FIFO_SWAP_SFT                         15
+#define RG_MTKAIF1_TXIF_FIFO_SWAP_MASK                        0x1
+#define RG_MTKAIF1_TXIF_FIFO_SWAP_MASK_SFT                    (0x1 << 15)
+#define RG_MTKAIF1_TXIF_FIFO_RSP_SFT                          12
+#define RG_MTKAIF1_TXIF_FIFO_RSP_MASK                         0x7
+#define RG_MTKAIF1_TXIF_FIFO_RSP_MASK_SFT                     (0x7 << 12)
+#define RG_MTKAIF1_TXIF_SYNC_WORD1_SFT                        4
+#define RG_MTKAIF1_TXIF_SYNC_WORD1_MASK                       0x7
+#define RG_MTKAIF1_TXIF_SYNC_WORD1_MASK_SFT                   (0x7 << 4)
+#define RG_MTKAIF1_TXIF_SYNC_WORD0_SFT                        0
+#define RG_MTKAIF1_TXIF_SYNC_WORD0_MASK                       0x7
+#define RG_MTKAIF1_TXIF_SYNC_WORD0_MASK_SFT                   (0x7 << 0)
+
+/* AFE_MTKAIF1_RX_CFG0 */
+#define RG_MTKAIF1_RXIF_VOICE_MODE_SFT                        20
+#define RG_MTKAIF1_RXIF_VOICE_MODE_MASK                       0xf
+#define RG_MTKAIF1_RXIF_VOICE_MODE_MASK_SFT                   (0xf << 20)
+#define RG_MTKAIF1_RXIF_DETECT_ON_SFT                         16
+#define RG_MTKAIF1_RXIF_DETECT_ON_MASK                        0x1
+#define RG_MTKAIF1_RXIF_DETECT_ON_MASK_SFT                    (0x1 << 16)
+#define RG_MTKAIF1_RXIF_DATA_BIT_SFT                          8
+#define RG_MTKAIF1_RXIF_DATA_BIT_MASK                         0x7
+#define RG_MTKAIF1_RXIF_DATA_BIT_MASK_SFT                     (0x7 << 8)
+#define RG_MTKAIF1_RXIF_FIFO_RSP_SFT                          4
+#define RG_MTKAIF1_RXIF_FIFO_RSP_MASK                         0x7
+#define RG_MTKAIF1_RXIF_FIFO_RSP_MASK_SFT                     (0x7 << 4)
+#define RG_MTKAIF1_RXIF_DATA_MODE_SFT                         0
+#define RG_MTKAIF1_RXIF_DATA_MODE_MASK                        0x1
+#define RG_MTKAIF1_RXIF_DATA_MODE_MASK_SFT                    (0x1 << 0)
+
+/* AFE_MTKAIF1_RX_CFG1 */
+#define RG_MTKAIF1_RXIF_CLEAR_SYNC_FAIL_SFT                   28
+#define RG_MTKAIF1_RXIF_CLEAR_SYNC_FAIL_MASK                  0x1
+#define RG_MTKAIF1_RXIF_CLEAR_SYNC_FAIL_MASK_SFT              (0x1 << 28)
+#define RG_MTKAIF1_RXIF_SYNC_CNT_TABLE_SFT                    16
+#define RG_MTKAIF1_RXIF_SYNC_CNT_TABLE_MASK                   0xfff
+#define RG_MTKAIF1_RXIF_SYNC_CNT_TABLE_MASK_SFT               (0xfff << 16)
+#define RG_MTKAIF1_RXIF_SYNC_SEARCH_TABLE_SFT                 12
+#define RG_MTKAIF1_RXIF_SYNC_SEARCH_TABLE_MASK                0xf
+#define RG_MTKAIF1_RXIF_SYNC_SEARCH_TABLE_MASK_SFT            (0xf << 12)
+#define RG_MTKAIF1_RXIF_INVALID_SYNC_CHECK_ROUND_SFT          8
+#define RG_MTKAIF1_RXIF_INVALID_SYNC_CHECK_ROUND_MASK         0xf
+#define RG_MTKAIF1_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT     (0xf << 8)
+#define RG_MTKAIF1_RXIF_SYNC_CHECK_ROUND_SFT                  4
+#define RG_MTKAIF1_RXIF_SYNC_CHECK_ROUND_MASK                 0xf
+#define RG_MTKAIF1_RXIF_SYNC_CHECK_ROUND_MASK_SFT             (0xf << 4)
+
+/* AFE_MTKAIF1_RX_CFG2 */
+#define RG_MTKAIF1_RXIF_SYNC_WORD1_DISABLE_SFT                27
+#define RG_MTKAIF1_RXIF_SYNC_WORD1_DISABLE_MASK               0x1
+#define RG_MTKAIF1_RXIF_SYNC_WORD1_DISABLE_MASK_SFT           (0x1 << 27)
+#define RG_MTKAIF1_RXIF_SYNC_WORD1_SFT                        24
+#define RG_MTKAIF1_RXIF_SYNC_WORD1_MASK                       0x7
+#define RG_MTKAIF1_RXIF_SYNC_WORD1_MASK_SFT                   (0x7 << 24)
+#define RG_MTKAIF1_RXIF_SYNC_WORD0_DISABLE_SFT                23
+#define RG_MTKAIF1_RXIF_SYNC_WORD0_DISABLE_MASK               0x1
+#define RG_MTKAIF1_RXIF_SYNC_WORD0_DISABLE_MASK_SFT           (0x1 << 23)
+#define RG_MTKAIF1_RXIF_SYNC_WORD0_SFT                        20
+#define RG_MTKAIF1_RXIF_SYNC_WORD0_MASK                       0x7
+#define RG_MTKAIF1_RXIF_SYNC_WORD0_MASK_SFT                   (0x7 << 20)
+#define RG_MTKAIF1_RXIF_DELAY_CYCLE_SFT                       12
+#define RG_MTKAIF1_RXIF_DELAY_CYCLE_MASK                      0xf
+#define RG_MTKAIF1_RXIF_DELAY_CYCLE_MASK_SFT                  (0xf << 12)
+#define RG_MTKAIF1_RXIF_DELAY_DATA_SFT                        8
+#define RG_MTKAIF1_RXIF_DELAY_DATA_MASK                       0x1
+#define RG_MTKAIF1_RXIF_DELAY_DATA_MASK_SFT                   (0x1 << 8)
+
+/* AFE_AUD_PAD_TOP_CFG0 */
+#define AUD_PAD_TOP_FIFO_RSP_SFT                              4
+#define AUD_PAD_TOP_FIFO_RSP_MASK                             0xf
+#define AUD_PAD_TOP_FIFO_RSP_MASK_SFT                         (0xf << 4)
+#define RG_RX_PROTOCOL2_SFT                                   3
+#define RG_RX_PROTOCOL2_MASK                                  0x1
+#define RG_RX_PROTOCOL2_MASK_SFT                              (0x1 << 3)
+#define RG_RX_FIFO_ON_SFT                                     0
+#define RG_RX_FIFO_ON_MASK                                    0x1
+#define RG_RX_FIFO_ON_MASK_SFT                                (0x1 << 0)
+
+/* AFE_AUD_PAD_TOP_MON */
+#define AUD_PAD_TOP_MON_SFT                                   0
+#define AUD_PAD_TOP_MON_MASK                                  0xffff
+#define AUD_PAD_TOP_MON_MASK_SFT                              (0xffff << 0)
+
+/* AFE_ADDA_MTKAIFV4_TX_CFG0 */
+#define MTKAIFV4_TXIF_EN_SEL_SFT                              12
+#define MTKAIFV4_TXIF_EN_SEL_MASK                             0x1
+#define MTKAIFV4_TXIF_EN_SEL_MASK_SFT                         (0x1 << 12)
+#define MTKAIFV4_TXIF_V4_SFT                                  11
+#define MTKAIFV4_TXIF_V4_MASK                                 0x1
+#define MTKAIFV4_TXIF_V4_MASK_SFT                             (0x1 << 11)
+#define MTKAIFV4_ADDA6_OUT_EN_SEL_SFT                         10
+#define MTKAIFV4_ADDA6_OUT_EN_SEL_MASK                        0x1
+#define MTKAIFV4_ADDA6_OUT_EN_SEL_MASK_SFT                    (0x1 << 10)
+#define MTKAIFV4_ADDA_OUT_EN_SEL_SFT                          9
+#define MTKAIFV4_ADDA_OUT_EN_SEL_MASK                         0x1
+#define MTKAIFV4_ADDA_OUT_EN_SEL_MASK_SFT                     (0x1 << 9)
+#define MTKAIFV4_TXIF_INPUT_MODE_SFT                          4
+#define MTKAIFV4_TXIF_INPUT_MODE_MASK                         0x1f
+#define MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT                     (0x1f << 4)
+#define MTKAIFV4_TXIF_FOUR_CHANNEL_SFT                        1
+#define MTKAIFV4_TXIF_FOUR_CHANNEL_MASK                       0x1
+#define MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT                   (0x1 << 1)
+#define MTKAIFV4_TXIF_AFE_ON_SFT                              0
+#define MTKAIFV4_TXIF_AFE_ON_MASK                             0x1
+#define MTKAIFV4_TXIF_AFE_ON_MASK_SFT                         (0x1 << 0)
+
+/* AFE_ADDA6_MTKAIFV4_TX_CFG0 */
+#define ADDA6_MTKAIFV4_TXIF_EN_SEL_SFT                        12
+#define ADDA6_MTKAIFV4_TXIF_EN_SEL_MASK                       0x1
+#define ADDA6_MTKAIFV4_TXIF_EN_SEL_MASK_SFT                   (0x1 << 12)
+#define ADDA6_MTKAIFV4_TXIF_INPUT_MODE_SFT                    4
+#define ADDA6_MTKAIFV4_TXIF_INPUT_MODE_MASK                   0x1f
+#define ADDA6_MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT               (0x1f << 4)
+#define ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_SFT                  1
+#define ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_MASK                 0x1
+#define ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT             (0x1 << 1)
+#define ADDA6_MTKAIFV4_TXIF_AFE_ON_SFT                        0
+#define ADDA6_MTKAIFV4_TXIF_AFE_ON_MASK                       0x1
+#define ADDA6_MTKAIFV4_TXIF_AFE_ON_MASK_SFT                   (0x1 << 0)
+
+/* AFE_ADDA_MTKAIFV4_RX_CFG0 */
+#define MTKAIFV4_RXIF_CLKINV_SFT                              31
+#define MTKAIFV4_RXIF_CLKINV_MASK                             0x1
+#define MTKAIFV4_RXIF_CLKINV_MASK_SFT                         (0x1 << 31)
+#define MTKAIFV4_RXIF_LOOPBACK_MODE_SFT                       28
+#define MTKAIFV4_RXIF_LOOPBACK_MODE_MASK                      0x1
+#define MTKAIFV4_RXIF_LOOPBACK_MODE_MASK_SFT                  (0x1 << 28)
+#define MTKAIFV4_UL_CH7CH8_IN_EN_SEL_SFT                      19
+#define MTKAIFV4_UL_CH7CH8_IN_EN_SEL_MASK                     0x1
+#define MTKAIFV4_UL_CH7CH8_IN_EN_SEL_MASK_SFT                 (0x1 << 19)
+#define MTKAIFV4_UL_CH5CH6_IN_EN_SEL_SFT                      18
+#define MTKAIFV4_UL_CH5CH6_IN_EN_SEL_MASK                     0x1
+#define MTKAIFV4_UL_CH5CH6_IN_EN_SEL_MASK_SFT                 (0x1 << 18)
+#define MTKAIFV4_UL_CH3CH4_IN_EN_SEL_SFT                      17
+#define MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK                     0x1
+#define MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK_SFT                 (0x1 << 17)
+#define MTKAIFV4_UL_CH1CH2_IN_EN_SEL_SFT                      16
+#define MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK                     0x1
+#define MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK_SFT                 (0x1 << 16)
+#define MTKAIFV4_RXIF_EN_SEL_SFT                              12
+#define MTKAIFV4_RXIF_EN_SEL_MASK                             0x1
+#define MTKAIFV4_RXIF_EN_SEL_MASK_SFT                         (0x1 << 12)
+#define MTKAIFV4_RXIF_INPUT_MODE_SFT                          4
+#define MTKAIFV4_RXIF_INPUT_MODE_MASK                         0x1f
+#define MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT                     (0x1f << 4)
+#define MTKAIFV4_RXIF_FOUR_CHANNEL_SFT                        1
+#define MTKAIFV4_RXIF_FOUR_CHANNEL_MASK                       0x1
+#define MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT                   (0x1 << 1)
+#define MTKAIFV4_RXIF_AFE_ON_SFT                              0
+#define MTKAIFV4_RXIF_AFE_ON_MASK                             0x1
+#define MTKAIFV4_RXIF_AFE_ON_MASK_SFT                         (0x1 << 0)
+
+/* AFE_ADDA_MTKAIFV4_RX_CFG1 */
+#define MTKAIFV4_RXIF_SYNC_CNT_TABLE_SFT                      17
+#define MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK                     0xfff
+#define MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK_SFT                 (0xfff << 17)
+#define MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_SFT                   12
+#define MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK                  0x1f
+#define MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK_SFT              (0x1f << 12)
+#define MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_SFT            8
+#define MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK           0xf
+#define MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK_SFT       (0xf << 8)
+#define MTKAIFV4_RXIF_SYNC_CHECK_ROUND_SFT                    4
+#define MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK                   0xf
+#define MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK_SFT               (0xf << 4)
+#define MTKAIFV4_RXIF_FIFO_RSP_SFT                            1
+#define MTKAIFV4_RXIF_FIFO_RSP_MASK                           0x7
+#define MTKAIFV4_RXIF_FIFO_RSP_MASK_SFT                       (0x7 << 1)
+#define MTKAIFV4_RXIF_SELF_DEFINE_TABLE_SFT                   0
+#define MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK                  0x1
+#define MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK_SFT              (0x1 << 0)
+
+/* AFE_ADDA6_MTKAIFV4_RX_CFG0 */
+#define ADDA6_MTKAIFV4_RXIF_CLKINV_SFT                        31
+#define ADDA6_MTKAIFV4_RXIF_CLKINV_MASK                       0x1
+#define ADDA6_MTKAIFV4_RXIF_CLKINV_MASK_SFT                   (0x1 << 31)
+#define ADDA6_MTKAIFV4_RXIF_LOOPBACK_MODE_SFT                 28
+#define ADDA6_MTKAIFV4_RXIF_LOOPBACK_MODE_MASK                0x1
+#define ADDA6_MTKAIFV4_RXIF_LOOPBACK_MODE_MASK_SFT            (0x1 << 28)
+#define ADDA6_MTKAIFV4_RXIF_EN_SEL_SFT                        12
+#define ADDA6_MTKAIFV4_RXIF_EN_SEL_MASK                       0x1
+#define ADDA6_MTKAIFV4_RXIF_EN_SEL_MASK_SFT                   (0x1 << 12)
+#define ADDA6_MTKAIFV4_RXIF_INPUT_MODE_SFT                    4
+#define ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK                   0x1f
+#define ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT               (0x1f << 4)
+#define ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_SFT                  1
+#define ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_MASK                 0x1
+#define ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT             (0x1 << 1)
+#define ADDA6_MTKAIFV4_RXIF_AFE_ON_SFT                        0
+#define ADDA6_MTKAIFV4_RXIF_AFE_ON_MASK                       0x1
+#define ADDA6_MTKAIFV4_RXIF_AFE_ON_MASK_SFT                   (0x1 << 0)
+
+/* AFE_ADDA6_MTKAIFV4_RX_CFG1 */
+#define ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_SFT                17
+#define ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK               0xfff
+#define ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK_SFT           (0xfff << 17)
+#define ADDA6_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_SFT             12
+#define ADDA6_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK            0x1f
+#define ADDA6_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK_SFT        (0x1f << 12)
+#define ADDA6_MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_SFT      8
+#define ADDA6_MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK     0xf
+#define ADDA6_MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)
+#define ADDA6_MTKAIFV4_RXIF_SYNC_CHECK_ROUND_SFT              4
+#define ADDA6_MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK             0xf
+#define ADDA6_MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK_SFT         (0xf << 4)
+#define ADDA6_MTKAIFV4_RXIF_FIFO_RSP_SFT                      1
+#define ADDA6_MTKAIFV4_RXIF_FIFO_RSP_MASK                     0x7
+#define ADDA6_MTKAIFV4_RXIF_FIFO_RSP_MASK_SFT                 (0x7 << 1)
+#define ADDA6_MTKAIFV4_RXIF_SELF_DEFINE_TABLE_SFT             0
+#define ADDA6_MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK            0x1
+#define ADDA6_MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK_SFT        (0x1 << 0)
+
+/* AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG */
+#define ADDA6_MTKAIFV4_TXIF_SYNCWORD_SFT                      16
+#define ADDA6_MTKAIFV4_TXIF_SYNCWORD_MASK                     0xffff
+#define ADDA6_MTKAIFV4_TXIF_SYNCWORD_MASK_SFT                 (0xffff << 16)
+#define ADDA_MTKAIFV4_TXIF_SYNCWORD_SFT                       0
+#define ADDA_MTKAIFV4_TXIF_SYNCWORD_MASK                      0xffff
+#define ADDA_MTKAIFV4_TXIF_SYNCWORD_MASK_SFT                  (0xffff << 0)
+
+/* AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG */
+#define ADDA6_MTKAIFV4_RXIF_SYNCWORD_SFT                      16
+#define ADDA6_MTKAIFV4_RXIF_SYNCWORD_MASK                     0xffff
+#define ADDA6_MTKAIFV4_RXIF_SYNCWORD_MASK_SFT                 (0xffff << 16)
+#define ADDA_MTKAIFV4_RXIF_SYNCWORD_SFT                       0
+#define ADDA_MTKAIFV4_RXIF_SYNCWORD_MASK                      0xffff
+#define ADDA_MTKAIFV4_RXIF_SYNCWORD_MASK_SFT                  (0xffff << 0)
+
+/* AFE_ADDA_MTKAIFV4_MON0 */
+#define MTKAIFV4_TXIF_SDATA_OUT_SFT                           23
+#define MTKAIFV4_TXIF_SDATA_OUT_MASK                          0x1
+#define MTKAIFV4_TXIF_SDATA_OUT_MASK_SFT                      (0x1 << 23)
+#define MTKAIFV4_RXIF_SDATA_IN_SFT                            22
+#define MTKAIFV4_RXIF_SDATA_IN_MASK                           0x1
+#define MTKAIFV4_RXIF_SDATA_IN_MASK_SFT                       (0x1 << 22)
+#define MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_SFT                    21
+#define MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK                   0x1
+#define MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK_SFT               (0x1 << 21)
+#define MTKAIFV4_RXIF_ADC_FIFO_STATUS_SFT                     0
+#define MTKAIFV4_RXIF_ADC_FIFO_STATUS_MASK                    0xfff
+#define MTKAIFV4_RXIF_ADC_FIFO_STATUS_MASK_SFT                (0xfff << 0)
+
+/* AFE_ADDA_MTKAIFV4_MON1 */
+#define MTKAIFV4_RXIF_OUT_CH4_SFT                             24
+#define MTKAIFV4_RXIF_OUT_CH4_MASK                            0xff
+#define MTKAIFV4_RXIF_OUT_CH4_MASK_SFT                        (0xff << 24)
+#define MTKAIFV4_RXIF_OUT_CH3_SFT                             16
+#define MTKAIFV4_RXIF_OUT_CH3_MASK                            0xff
+#define MTKAIFV4_RXIF_OUT_CH3_MASK_SFT                        (0xff << 16)
+#define MTKAIFV4_RXIF_OUT_CH2_SFT                             8
+#define MTKAIFV4_RXIF_OUT_CH2_MASK                            0xff
+#define MTKAIFV4_RXIF_OUT_CH2_MASK_SFT                        (0xff << 8)
+#define MTKAIFV4_RXIF_OUT_CH1_SFT                             0
+#define MTKAIFV4_RXIF_OUT_CH1_MASK                            0xff
+#define MTKAIFV4_RXIF_OUT_CH1_MASK_SFT                        (0xff << 0)
+
+/* AFE_ADDA6_MTKAIFV4_MON0 */
+#define ADDA6_MTKAIFV4_TXIF_SDATA_OUT_SFT                     23
+#define ADDA6_MTKAIFV4_TXIF_SDATA_OUT_MASK                    0x1
+#define ADDA6_MTKAIFV4_TXIF_SDATA_OUT_MASK_SFT                (0x1 << 23)
+#define ADDA6_MTKAIFV4_RXIF_SDATA_IN_SFT                      22
+#define ADDA6_MTKAIFV4_RXIF_SDATA_IN_MASK                     0x1
+#define ADDA6_MTKAIFV4_RXIF_SDATA_IN_MASK_SFT                 (0x1 << 22)
+#define ADDA6_MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_SFT              21
+#define ADDA6_MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK             0x1
+#define ADDA6_MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK_SFT         (0x1 << 21)
+#define ADDA6_MTKAIFV3P3_RXIF_ADC_FIFO_STATUS_SFT             0
+#define ADDA6_MTKAIFV3P3_RXIF_ADC_FIFO_STATUS_MASK            0xfff
+#define ADDA6_MTKAIFV3P3_RXIF_ADC_FIFO_STATUS_MASK_SFT        (0xfff << 0)
+
+/* ETDM_IN0_CON0 */
+#define REG_ETDM_IN_EN_SFT                                    0
+#define REG_ETDM_IN_EN_MASK                                   0x1
+#define REG_ETDM_IN_EN_MASK_SFT                               (0x1 << 0)
+#define REG_SYNC_MODE_SFT                                     1
+#define REG_SYNC_MODE_MASK                                    0x1
+#define REG_SYNC_MODE_MASK_SFT                                (0x1 << 1)
+#define REG_LSB_FIRST_SFT                                     3
+#define REG_LSB_FIRST_MASK                                    0x1
+#define REG_LSB_FIRST_MASK_SFT                                (0x1 << 3)
+#define REG_SOFT_RST_SFT                                      4
+#define REG_SOFT_RST_MASK                                     0x1
+#define REG_SOFT_RST_MASK_SFT                                 (0x1 << 4)
+#define REG_SLAVE_MODE_SFT                                    5
+#define REG_SLAVE_MODE_MASK                                   0x1
+#define REG_SLAVE_MODE_MASK_SFT                               (0x1 << 5)
+#define REG_FMT_SFT                                           6
+#define REG_FMT_MASK                                          0x7
+#define REG_FMT_MASK_SFT                                      (0x7 << 6)
+#define REG_LRCK_EDGE_SEL_SFT                                 10
+#define REG_LRCK_EDGE_SEL_MASK                                0x1
+#define REG_LRCK_EDGE_SEL_MASK_SFT                            (0x1 << 10)
+#define REG_BIT_LENGTH_SFT                                    11
+#define REG_BIT_LENGTH_MASK                                   0x1f
+#define REG_BIT_LENGTH_MASK_SFT                               (0x1f << 11)
+#define REG_WORD_LENGTH_SFT                                   16
+#define REG_WORD_LENGTH_MASK                                  0x1f
+#define REG_WORD_LENGTH_MASK_SFT                              (0x1f << 16)
+#define REG_CH_NUM_SFT                                        23
+#define REG_CH_NUM_MASK                                       0x1f
+#define REG_CH_NUM_MASK_SFT                                   (0x1f << 23)
+#define REG_RELATCH_1X_EN_DOMAIN_SEL_SFT                      28
+#define REG_RELATCH_1X_EN_DOMAIN_SEL_MASK                     0x7
+#define REG_RELATCH_1X_EN_DOMAIN_SEL_MASK_SFT                 (0x7 << 28)
+#define REG_VALID_TOGETHER_SFT                                31
+#define REG_VALID_TOGETHER_MASK                               0x1
+#define REG_VALID_TOGETHER_MASK_SFT                           (0x1 << 31)
+
+/* ETDM_IN0_CON1 */
+/* ETDM_IN1_CON1 */
+/* ETDM_IN2_CON1 */
+/* ETDM_IN3_CON1 */
+/* ETDM_IN4_CON1 */
+/* ETDM_IN5_CON1 */
+/* ETDM_IN6_CON1 */
+#define REG_INITIAL_COUNT_SFT                                 0
+#define REG_INITIAL_COUNT_MASK                                0x1f
+#define REG_INITIAL_COUNT_MASK_SFT                            (0x1f << 0)
+#define REG_INITIAL_POINT_SFT                                 5
+#define REG_INITIAL_POINT_MASK                                0x1f
+#define REG_INITIAL_POINT_MASK_SFT                            (0x1f << 5)
+#define REG_LRCK_AUTO_OFF_SFT                                 10
+#define REG_LRCK_AUTO_OFF_MASK                                0x1
+#define REG_LRCK_AUTO_OFF_MASK_SFT                            (0x1 << 10)
+#define REG_BCK_AUTO_OFF_SFT                                  11
+#define REG_BCK_AUTO_OFF_MASK                                 0x1
+#define REG_BCK_AUTO_OFF_MASK_SFT                             (0x1 << 11)
+#define REG_INITIAL_LRCK_SFT                                  13
+#define REG_INITIAL_LRCK_MASK                                 0x1
+#define REG_INITIAL_LRCK_MASK_SFT                             (0x1 << 13)
+#define REG_NO_ALIGN_1X_EN_SFT                                14
+#define REG_NO_ALIGN_1X_EN_MASK                               0x1
+#define REG_NO_ALIGN_1X_EN_MASK_SFT                           (0x1 << 14)
+#define REG_LRCK_RESET_SFT                                    15
+#define REG_LRCK_RESET_MASK                                   0x1
+#define REG_LRCK_RESET_MASK_SFT                               (0x1 << 15)
+#define PINMUX_MCLK_CTRL_OE_SFT                               16
+#define PINMUX_MCLK_CTRL_OE_MASK                              0x1
+#define PINMUX_MCLK_CTRL_OE_MASK_SFT                          (0x1 << 16)
+#define REG_OUTPUT_CR_EN_SFT                                  18
+#define REG_OUTPUT_CR_EN_MASK                                 0x1
+#define REG_OUTPUT_CR_EN_MASK_SFT                             (0x1 << 18)
+#define REG_LR_ALIGN_SFT                                      19
+#define REG_LR_ALIGN_MASK                                     0x1
+#define REG_LR_ALIGN_MASK_SFT                                 (0x1 << 19)
+#define REG_LRCK_WIDTH_SFT                                    20
+#define REG_LRCK_WIDTH_MASK                                   0x3ff
+#define REG_LRCK_WIDTH_MASK_SFT                               (0x3ff << 20)
+#define REG_DIRECT_INPUT_MASTER_BCK_SFT                       30
+#define REG_DIRECT_INPUT_MASTER_BCK_MASK                      0x1
+#define REG_DIRECT_INPUT_MASTER_BCK_MASK_SFT                  (0x1 << 30)
+#define REG_LRCK_AUTO_MODE_SFT                                31
+#define REG_LRCK_AUTO_MODE_MASK                               0x1
+#define REG_LRCK_AUTO_MODE_MASK_SFT                           (0x1 << 31)
+
+/* ETDM_IN0_CON2 */
+/* ETDM_IN1_CON2 */
+/* ETDM_IN2_CON2 */
+/* ETDM_IN3_CON2 */
+/* ETDM_IN4_CON2 */
+/* ETDM_IN5_CON2 */
+/* ETDM_IN6_CON2 */
+#define REG_UPDATE_POINT_SFT                                  0
+#define REG_UPDATE_POINT_MASK                                 0x1f
+#define REG_UPDATE_POINT_MASK_SFT                             (0x1f << 0)
+#define REG_UPDATE_GAP_SFT                                    5
+#define REG_UPDATE_GAP_MASK                                   0x1f
+#define REG_UPDATE_GAP_MASK_SFT                               (0x1f << 5)
+#define REG_CLOCK_SOURCE_SEL_SFT                              10
+#define REG_CLOCK_SOURCE_SEL_MASK                             0x7
+#define REG_CLOCK_SOURCE_SEL_MASK_SFT                         (0x7 << 10)
+#define REG_CK_EN_SEL_AUTO_SFT                                14
+#define REG_CK_EN_SEL_AUTO_MASK                               0x1
+#define REG_CK_EN_SEL_AUTO_MASK_SFT                           (0x1 << 14)
+#define REG_MULTI_IP_TOTAL_CHNUM_SFT                          15
+#define REG_MULTI_IP_TOTAL_CHNUM_MASK                         0x1f
+#define REG_MULTI_IP_TOTAL_CHNUM_MASK_SFT                     (0x1f << 15)
+#define REG_MASK_AUTO_SFT                                     20
+#define REG_MASK_AUTO_MASK                                    0x1
+#define REG_MASK_AUTO_MASK_SFT                                (0x1 << 20)
+#define REG_MASK_NUM_SFT                                      21
+#define REG_MASK_NUM_MASK                                     0x1f
+#define REG_MASK_NUM_MASK_SFT                                 (0x1f << 21)
+#define REG_UPDATE_POINT_AUTO_SFT                             26
+#define REG_UPDATE_POINT_AUTO_MASK                            0x1
+#define REG_UPDATE_POINT_AUTO_MASK_SFT                        (0x1 << 26)
+#define REG_SDATA_DELAY_0P5T_EN_SFT                           27
+#define REG_SDATA_DELAY_0P5T_EN_MASK                          0x1
+#define REG_SDATA_DELAY_0P5T_EN_MASK_SFT                      (0x1 << 27)
+#define REG_SDATA_DELAY_BCK_INV_SFT                           28
+#define REG_SDATA_DELAY_BCK_INV_MASK                          0x1
+#define REG_SDATA_DELAY_BCK_INV_MASK_SFT                      (0x1 << 28)
+#define REG_LRCK_DELAY_0P5T_EN_SFT                            29
+#define REG_LRCK_DELAY_0P5T_EN_MASK                           0x1
+#define REG_LRCK_DELAY_0P5T_EN_MASK_SFT                       (0x1 << 29)
+#define REG_LRCK_DELAY_BCK_INV_SFT                            30
+#define REG_LRCK_DELAY_BCK_INV_MASK                           0x1
+#define REG_LRCK_DELAY_BCK_INV_MASK_SFT                       (0x1 << 30)
+#define REG_MULTI_IP_MODE_SFT                                 31
+#define REG_MULTI_IP_MODE_MASK                                0x1
+#define REG_MULTI_IP_MODE_MASK_SFT                            (0x1 << 31)
+
+/* ETDM_IN0_CON3 */
+/* ETDM_IN1_CON3 */
+/* ETDM_IN2_CON3 */
+/* ETDM_IN3_CON3 */
+/* ETDM_IN4_CON3 */
+/* ETDM_IN5_CON3 */
+/* ETDM_IN6_CON3 */
+#define REG_DISABLE_OUT_SFT                                   0
+#define REG_DISABLE_OUT_MASK                                  0xffff
+#define REG_DISABLE_OUT_MASK_SFT                              (0xffff << 0)
+#define REG_RJ_DATA_RIGHT_ALIGN_SFT                           16
+#define REG_RJ_DATA_RIGHT_ALIGN_MASK                          0x1
+#define REG_RJ_DATA_RIGHT_ALIGN_MASK_SFT                      (0x1 << 16)
+#define REG_MONITOR_SEL_SFT                                   17
+#define REG_MONITOR_SEL_MASK                                  0x3
+#define REG_MONITOR_SEL_MASK_SFT                              (0x3 << 17)
+#define REG_CNT_UPPER_LIMIT_SFT                               19
+#define REG_CNT_UPPER_LIMIT_MASK                              0x3f
+#define REG_CNT_UPPER_LIMIT_MASK_SFT                          (0x3f << 19)
+#define REG_COMPACT_SAMPLE_END_DIS_SFT                        25
+#define REG_COMPACT_SAMPLE_END_DIS_MASK                       0x1
+#define REG_COMPACT_SAMPLE_END_DIS_MASK_SFT                   (0x1 << 25)
+#define REG_FS_TIMING_SEL_SFT                                 26
+#define REG_FS_TIMING_SEL_MASK                                0x1f
+#define REG_FS_TIMING_SEL_MASK_SFT                            (0x1f << 26)
+#define REG_SAMPLE_END_MODE_SFT                               31
+#define REG_SAMPLE_END_MODE_MASK                              0x1
+#define REG_SAMPLE_END_MODE_MASK_SFT                          (0x1 << 31)
+
+/* ETDM_IN0_CON4 */
+/* ETDM_IN1_CON4 */
+/* ETDM_IN2_CON4 */
+/* ETDM_IN3_CON4 */
+/* ETDM_IN4_CON4 */
+/* ETDM_IN5_CON4 */
+/* ETDM_IN6_CON4 */
+#define REG_ALWAYS_OPEN_1X_EN_SFT                             31
+#define REG_ALWAYS_OPEN_1X_EN_MASK                            0x1
+#define REG_ALWAYS_OPEN_1X_EN_MASK_SFT                        (0x1 << 31)
+#define REG_WAIT_LAST_SAMPLE_SFT                              30
+#define REG_WAIT_LAST_SAMPLE_MASK                             0x1
+#define REG_WAIT_LAST_SAMPLE_MASK_SFT                         (0x1 << 30)
+#define REG_SAMPLE_END_POINT_SFT                              25
+#define REG_SAMPLE_END_POINT_MASK                             0x1f
+#define REG_SAMPLE_END_POINT_MASK_SFT                         (0x1f << 25)
+#define REG_RELATCH_1X_EN_SEL_SFT                             20
+#define REG_RELATCH_1X_EN_SEL_MASK                            0x1f
+#define REG_RELATCH_1X_EN_SEL_MASK_SFT                        (0x1f << 20)
+#define REG_MASTER_WS_INV_SFT                                 19
+#define REG_MASTER_WS_INV_MASK                                0x1
+#define REG_MASTER_WS_INV_MASK_SFT                            (0x1 << 19)
+#define REG_MASTER_BCK_INV_SFT                                18
+#define REG_MASTER_BCK_INV_MASK                               0x1
+#define REG_MASTER_BCK_INV_MASK_SFT                           (0x1 << 18)
+#define REG_SLAVE_LRCK_INV_SFT                                17
+#define REG_SLAVE_LRCK_INV_MASK                               0x1
+#define REG_SLAVE_LRCK_INV_MASK_SFT                           (0x1 << 17)
+#define REG_SLAVE_BCK_INV_SFT                                 16
+#define REG_SLAVE_BCK_INV_MASK                                0x1
+#define REG_SLAVE_BCK_INV_MASK_SFT                            (0x1 << 16)
+#define REG_REPACK_CHNUM_SFT                                  12
+#define REG_REPACK_CHNUM_MASK                                 0xf
+#define REG_REPACK_CHNUM_MASK_SFT                             (0xf << 12)
+#define REG_ASYNC_RESET_SFT                                   11
+#define REG_ASYNC_RESET_MASK                                  0x1
+#define REG_ASYNC_RESET_MASK_SFT                              (0x1 << 11)
+#define REG_REPACK_WORD_LENGTH_SFT                            9
+#define REG_REPACK_WORD_LENGTH_MASK                           0x3
+#define REG_REPACK_WORD_LENGTH_MASK_SFT                       (0x3 << 9)
+#define REG_REPACK_AUTO_MODE_SFT                              8
+#define REG_REPACK_AUTO_MODE_MASK                             0x1
+#define REG_REPACK_AUTO_MODE_MASK_SFT                         (0x1 << 8)
+#define REG_REPACK_MODE_SFT                                   0
+#define REG_REPACK_MODE_MASK                                  0x3f
+#define REG_REPACK_MODE_MASK_SFT                              (0x3f << 0)
+
+/* ETDM_IN0_CON5 */
+/* ETDM_IN1_CON5 */
+/* ETDM_IN2_CON5 */
+/* ETDM_IN3_CON5 */
+/* ETDM_IN4_CON5 */
+/* ETDM_IN5_CON5 */
+/* ETDM_IN6_CON5 */
+#define REG_LR_SWAP_SFT                                       16
+#define REG_LR_SWAP_MASK                                      0xffff
+#define REG_LR_SWAP_MASK_SFT                                  (0xffff << 16)
+#define REG_ODD_FLAG_EN_SFT                                   0
+#define REG_ODD_FLAG_EN_MASK                                  0xffff
+#define REG_ODD_FLAG_EN_MASK_SFT                              (0xffff << 0)
+
+/* ETDM_IN0_CON6 */
+/* ETDM_IN1_CON6 */
+/* ETDM_IN2_CON6 */
+/* ETDM_IN3_CON6 */
+/* ETDM_IN4_CON6 */
+/* ETDM_IN5_CON6 */
+/* ETDM_IN6_CON6 */
+#define LCH_DATA_REG_SFT                                      0
+#define LCH_DATA_REG_MASK                                     0xffffffff
+#define LCH_DATA_REG_MASK_SFT                                 (0xffffffff << 0)
+
+/* ETDM_IN0_CON7 */
+/* ETDM_IN1_CON7 */
+/* ETDM_IN2_CON7 */
+/* ETDM_IN3_CON7 */
+/* ETDM_IN4_CON7 */
+/* ETDM_IN5_CON7 */
+/* ETDM_IN6_CON7 */
+#define RCH_DATA_REG_SFT                                      0
+#define RCH_DATA_REG_MASK                                     0xffffffff
+#define RCH_DATA_REG_MASK_SFT                                 (0xffffffff << 0)
+
+/* ETDM_IN0_CON8 */
+/* ETDM_IN1_CON8 */
+/* ETDM_IN2_CON8 */
+/* ETDM_IN3_CON8 */
+/* ETDM_IN4_CON8 */
+/* ETDM_IN5_CON8 */
+/* ETDM_IN6_CON8 */
+#define REG_AFIFO_THRESHOLD_SFT                               29
+#define REG_AFIFO_THRESHOLD_MASK                              0x3
+#define REG_AFIFO_THRESHOLD_MASK_SFT                          (0x3 << 29)
+#define REG_CK_EN_SEL_MANUAL_SFT                              16
+#define REG_CK_EN_SEL_MANUAL_MASK                             0x3ff
+#define REG_CK_EN_SEL_MANUAL_MASK_SFT                         (0x3ff << 16)
+#define REG_AFIFO_SW_RESET_SFT                                15
+#define REG_AFIFO_SW_RESET_MASK                               0x1
+#define REG_AFIFO_SW_RESET_MASK_SFT                           (0x1 << 15)
+#define REG_AFIFO_RESET_SEL_SFT                               14
+#define REG_AFIFO_RESET_SEL_MASK                              0x1
+#define REG_AFIFO_RESET_SEL_MASK_SFT                          (0x1 << 14)
+#define REG_AFIFO_AUTO_RESET_DIS_SFT                          9
+#define REG_AFIFO_AUTO_RESET_DIS_MASK                         0x1
+#define REG_AFIFO_AUTO_RESET_DIS_MASK_SFT                     (0x1 << 9)
+#define REG_ETDM_USE_AFIFO_SFT                                8
+#define REG_ETDM_USE_AFIFO_MASK                               0x1
+#define REG_ETDM_USE_AFIFO_MASK_SFT                           (0x1 << 8)
+#define REG_AFIFO_CLOCK_DOMAIN_SEL_SFT                        5
+#define REG_AFIFO_CLOCK_DOMAIN_SEL_MASK                       0x7
+#define REG_AFIFO_CLOCK_DOMAIN_SEL_MASK_SFT                   (0x7 << 5)
+#define REG_AFIFO_MODE_SFT                                    0
+#define REG_AFIFO_MODE_MASK                                   0x1f
+#define REG_AFIFO_MODE_MASK_SFT                               (0x1f << 0)
+
+/* ETDM_IN0_CON9 */
+/* ETDM_IN1_CON9 */
+/* ETDM_IN2_CON9 */
+/* ETDM_IN3_CON9 */
+/* ETDM_IN4_CON9 */
+/* ETDM_IN5_CON9 */
+/* ETDM_IN6_CON9 */
+#define REG_OUT2LATCH_TIME_SFT                                10
+#define REG_OUT2LATCH_TIME_MASK                               0x1f
+#define REG_OUT2LATCH_TIME_MASK_SFT                           (0x1f << 10)
+#define REG_ALMOST_END_BIT_COUNT_SFT                          5
+#define REG_ALMOST_END_BIT_COUNT_MASK                         0x1f
+#define REG_ALMOST_END_BIT_COUNT_MASK_SFT                     (0x1f << 5)
+#define REG_ALMOST_END_CH_COUNT_SFT                           0
+#define REG_ALMOST_END_CH_COUNT_MASK                          0x1f
+#define REG_ALMOST_END_CH_COUNT_MASK_SFT                      (0x1f << 0)
+
+/* ETDM_IN0_MON */
+/* ETDM_IN1_MON */
+/* ETDM_IN2_MON */
+/* ETDM_IN3_MON */
+/* ETDM_IN4_MON */
+/* ETDM_IN5_MON */
+/* ETDM_IN6_MON */
+#define LRCK_INV_SFT                                          30
+#define LRCK_INV_MASK                                         0x1
+#define LRCK_INV_MASK_SFT                                     (0x1 << 30)
+#define EN_SYNC_OUT_SFT                                       29
+#define EN_SYNC_OUT_MASK                                      0x1
+#define EN_SYNC_OUT_MASK_SFT                                  (0x1 << 29)
+#define HOPPING_EN_SYNC_OUT_PRE_SFT                           28
+#define HOPPING_EN_SYNC_OUT_PRE_MASK                          0x1
+#define HOPPING_EN_SYNC_OUT_PRE_MASK_SFT                      (0x1 << 28)
+#define WFULL_SFT                                             27
+#define WFULL_MASK                                            0x1
+#define WFULL_MASK_SFT                                        (0x1 << 27)
+#define REMPTY_SFT                                            26
+#define REMPTY_MASK                                           0x1
+#define REMPTY_MASK_SFT                                       (0x1 << 26)
+#define ETDM_2X_CK_EN_SFT                                     25
+#define ETDM_2X_CK_EN_MASK                                    0x1
+#define ETDM_2X_CK_EN_MASK_SFT                                (0x1 << 25)
+#define ETDM_1X_CK_EN_SFT                                     24
+#define ETDM_1X_CK_EN_MASK                                    0x1
+#define ETDM_1X_CK_EN_MASK_SFT                                (0x1 << 24)
+#define SDATA0_SFT                                            23
+#define SDATA0_MASK                                           0x1
+#define SDATA0_MASK_SFT                                       (0x1 << 23)
+#define CURRENT_STATUS_SFT                                    21
+#define CURRENT_STATUS_MASK                                   0x3
+#define CURRENT_STATUS_MASK_SFT                               (0x3 << 21)
+#define BIT_POINT_SFT                                         16
+#define BIT_POINT_MASK                                        0x1f
+#define BIT_POINT_MASK_SFT                                    (0x1f << 16)
+#define BIT_CH_COUNT_SFT                                      10
+#define BIT_CH_COUNT_MASK                                     0x3f
+#define BIT_CH_COUNT_MASK_SFT                                 (0x3f << 10)
+#define BIT_COUNT_SFT                                         5
+#define BIT_COUNT_MASK                                        0x1f
+#define BIT_COUNT_MASK_SFT                                    (0x1f << 5)
+#define CH_COUNT_SFT                                          0
+#define CH_COUNT_MASK                                         0x1f
+#define CH_COUNT_MASK_SFT                                     (0x1f << 0)
+
+/* ETDM_OUT0_CON0 */
+/* ETDM_OUT1_CON0 */
+/* ETDM_OUT2_CON0 */
+/* ETDM_OUT3_CON0 */
+/* ETDM_OUT4_CON0 */
+/* ETDM_OUT5_CON0 */
+/* ETDM_OUT6_CON0 */
+#define OUT_REG_ETDM_OUT_EN_SFT                                   0
+#define OUT_REG_ETDM_OUT_EN_MASK                                  0x1
+#define OUT_REG_ETDM_OUT_EN_MASK_SFT                              (0x1 << 0)
+#define OUT_REG_SYNC_MODE_SFT                                     1
+#define OUT_REG_SYNC_MODE_MASK                                    0x1
+#define OUT_REG_SYNC_MODE_MASK_SFT                                (0x1 << 1)
+#define OUT_REG_LSB_FIRST_SFT                                     3
+#define OUT_REG_LSB_FIRST_MASK                                    0x1
+#define OUT_REG_LSB_FIRST_MASK_SFT                                (0x1 << 3)
+#define OUT_REG_SOFT_RST_SFT                                      4
+#define OUT_REG_SOFT_RST_MASK                                     0x1
+#define OUT_REG_SOFT_RST_MASK_SFT                                 (0x1 << 4)
+#define OUT_REG_SLAVE_MODE_SFT                                    5
+#define OUT_REG_SLAVE_MODE_MASK                                   0x1
+#define OUT_REG_SLAVE_MODE_MASK_SFT                               (0x1 << 5)
+#define OUT_REG_FMT_SFT                                           6
+#define OUT_REG_FMT_MASK                                          0x7
+#define OUT_REG_FMT_MASK_SFT                                      (0x7 << 6)
+#define OUT_REG_LRCK_EDGE_SEL_SFT                                 10
+#define OUT_REG_LRCK_EDGE_SEL_MASK                                0x1
+#define OUT_REG_LRCK_EDGE_SEL_MASK_SFT                            (0x1 << 10)
+#define OUT_REG_BIT_LENGTH_SFT                                    11
+#define OUT_REG_BIT_LENGTH_MASK                                   0x1f
+#define OUT_REG_BIT_LENGTH_MASK_SFT                               (0x1f << 11)
+#define OUT_REG_WORD_LENGTH_SFT                                   16
+#define OUT_REG_WORD_LENGTH_MASK                                  0x1f
+#define OUT_REG_WORD_LENGTH_MASK_SFT                              (0x1f << 16)
+#define OUT_REG_CH_NUM_SFT                                        23
+#define OUT_REG_CH_NUM_MASK                                       0x1f
+#define OUT_REG_CH_NUM_MASK_SFT                                   (0x1f << 23)
+#define OUT_REG_RELATCH_DOMAIN_SEL_SFT                            28
+#define OUT_REG_RELATCH_DOMAIN_SEL_MASK                           0x7
+#define OUT_REG_RELATCH_DOMAIN_SEL_MASK_SFT                       (0x7 << 28)
+#define OUT_REG_VALID_TOGETHER_SFT                                31
+#define OUT_REG_VALID_TOGETHER_MASK                               0x1
+#define OUT_REG_VALID_TOGETHER_MASK_SFT                           (0x1 << 31)
+
+/* ETDM_OUT0_CON1 */
+/* ETDM_OUT1_CON1 */
+/* ETDM_OUT2_CON1 */
+/* ETDM_OUT3_CON1 */
+/* ETDM_OUT4_CON1 */
+/* ETDM_OUT5_CON1 */
+/* ETDM_OUT6_CON1 */
+#define OUT_REG_INITIAL_COUNT_SFT                                 0
+#define OUT_REG_INITIAL_COUNT_MASK                                0x1f
+#define OUT_REG_INITIAL_COUNT_MASK_SFT                            (0x1f << 0)
+#define OUT_REG_INITIAL_POINT_SFT                                 5
+#define OUT_REG_INITIAL_POINT_MASK                                0x1f
+#define OUT_REG_INITIAL_POINT_MASK_SFT                            (0x1f << 5)
+#define OUT_REG_LRCK_AUTO_OFF_SFT                                 10
+#define OUT_REG_LRCK_AUTO_OFF_MASK                                0x1
+#define OUT_REG_LRCK_AUTO_OFF_MASK_SFT                            (0x1 << 10)
+#define OUT_REG_BCK_AUTO_OFF_SFT                                  11
+#define OUT_REG_BCK_AUTO_OFF_MASK                                 0x1
+#define OUT_REG_BCK_AUTO_OFF_MASK_SFT                             (0x1 << 11)
+#define OUT_REG_INITIAL_LRCK_SFT                                  13
+#define OUT_REG_INITIAL_LRCK_MASK                                 0x1
+#define OUT_REG_INITIAL_LRCK_MASK_SFT                             (0x1 << 13)
+#define OUT_REG_NO_ALIGN_1X_EN_SFT                                14
+#define OUT_REG_NO_ALIGN_1X_EN_MASK                               0x1
+#define OUT_REG_NO_ALIGN_1X_EN_MASK_SFT                           (0x1 << 14)
+#define OUT_REG_LRCK_RESET_SFT                                    15
+#define OUT_REG_LRCK_RESET_MASK                                   0x1
+#define OUT_REG_LRCK_RESET_MASK_SFT                               (0x1 << 15)
+#define OUT_PINMUX_MCLK_CTRL_OE_SFT                               16
+#define OUT_PINMUX_MCLK_CTRL_OE_MASK                              0x1
+#define OUT_PINMUX_MCLK_CTRL_OE_MASK_SFT                          (0x1 << 16)
+#define OUT_REG_OUTPUT_CR_EN_SFT                                  18
+#define OUT_REG_OUTPUT_CR_EN_MASK                                 0x1
+#define OUT_REG_OUTPUT_CR_EN_MASK_SFT                             (0x1 << 18)
+#define OUT_REG_LRCK_WIDTH_SFT                                    19
+#define OUT_REG_LRCK_WIDTH_MASK                                   0x3ff
+#define OUT_REG_LRCK_WIDTH_MASK_SFT                               (0x3ff << 19)
+#define OUT_REG_LRCK_AUTO_MODE_SFT                                29
+#define OUT_REG_LRCK_AUTO_MODE_MASK                               0x1
+#define OUT_REG_LRCK_AUTO_MODE_MASK_SFT                           (0x1 << 29)
+#define OUT_REG_DIRECT_INPUT_MASTER_BCK_SFT                       30
+#define OUT_REG_DIRECT_INPUT_MASTER_BCK_MASK                      0x1
+#define OUT_REG_DIRECT_INPUT_MASTER_BCK_MASK_SFT                  (0x1 << 30)
+#define OUT_REG_16B_COMPACT_MODE_SFT                              31
+#define OUT_REG_16B_COMPACT_MODE_MASK                             0x1
+#define OUT_REG_16B_COMPACT_MODE_MASK_SFT                         (0x1 << 31)
+
+/* ETDM_OUT0_CON2 */
+/* ETDM_OUT1_CON2 */
+/* ETDM_OUT2_CON2 */
+/* ETDM_OUT3_CON2 */
+/* ETDM_OUT4_CON2 */
+/* ETDM_OUT5_CON2 */
+/* ETDM_OUT6_CON2 */
+#define OUT_REG_IN2LATCH_TIME_SFT                                 0
+#define OUT_REG_IN2LATCH_TIME_MASK                                0x1f
+#define OUT_REG_IN2LATCH_TIME_MASK_SFT                            (0x1f << 0)
+#define OUT_REG_MASK_NUM_SFT                                      5
+#define OUT_REG_MASK_NUM_MASK                                     0x1f
+#define OUT_REG_MASK_NUM_MASK_SFT                                 (0x1f << 5)
+#define OUT_REG_MASK_AUTO_SFT                                     10
+#define OUT_REG_MASK_AUTO_MASK                                    0x1
+#define OUT_REG_MASK_AUTO_MASK_SFT                                (0x1 << 10)
+#define OUT_REG_SDATA_SHIFT_SFT                                   11
+#define OUT_REG_SDATA_SHIFT_MASK                                  0x3
+#define OUT_REG_SDATA_SHIFT_MASK_SFT                              (0x3 << 11)
+#define OUT_REG_ALMOST_END_BIT_COUNT_SFT                          13
+#define OUT_REG_ALMOST_END_BIT_COUNT_MASK                         0x1f
+#define OUT_REG_ALMOST_END_BIT_COUNT_MASK_SFT                     (0x1f << 13)
+#define OUT_REG_SDATA_CON_SFT                                     18
+#define OUT_REG_SDATA_CON_MASK                                    0x3
+#define OUT_REG_SDATA_CON_MASK_SFT                                (0x3 << 18)
+#define OUT_REG_REDUNDANT_0_SFT                                   20
+#define OUT_REG_REDUNDANT_0_MASK                                  0x1
+#define OUT_REG_REDUNDANT_0_MASK_SFT                              (0x1 << 20)
+#define OUT_REG_SDATA_AUTO_OFF_SFT                                21
+#define OUT_REG_SDATA_AUTO_OFF_MASK                               0x1
+#define OUT_REG_SDATA_AUTO_OFF_MASK_SFT                           (0x1 << 21)
+#define OUT_REG_BCK_OFF_TIME_SFT                                  22
+#define OUT_REG_BCK_OFF_TIME_MASK                                 0x3
+#define OUT_REG_BCK_OFF_TIME_MASK_SFT                             (0x3 << 22)
+#define OUT_REG_MONITOR_SEL_SFT                                   24
+#define OUT_REG_MONITOR_SEL_MASK                                  0x3
+#define OUT_REG_MONITOR_SEL_MASK_SFT                              (0x3 << 24)
+#define OUT_REG_SHIFT_AUTO_SFT                                    26
+#define OUT_REG_SHIFT_AUTO_MASK                                   0x1
+#define OUT_REG_SHIFT_AUTO_MASK_SFT                               (0x1 << 26)
+#define OUT_REG_SDATA_DELAY_0P5T_EN_SFT                           27
+#define OUT_REG_SDATA_DELAY_0P5T_EN_MASK                          0x1
+#define OUT_REG_SDATA_DELAY_0P5T_EN_MASK_SFT                      (0x1 << 27)
+#define OUT_REG_SDATA_DELAY_BCK_INV_SFT                           28
+#define OUT_REG_SDATA_DELAY_BCK_INV_MASK                          0x1
+#define OUT_REG_SDATA_DELAY_BCK_INV_MASK_SFT                      (0x1 << 28)
+#define OUT_REG_LRCK_DELAY_0P5T_EN_SFT                            29
+#define OUT_REG_LRCK_DELAY_0P5T_EN_MASK                           0x1
+#define OUT_REG_LRCK_DELAY_0P5T_EN_MASK_SFT                       (0x1 << 29)
+#define OUT_REG_LRCK_DELAY_BCK_INV_SFT                            30
+#define OUT_REG_LRCK_DELAY_BCK_INV_MASK                           0x1
+#define OUT_REG_LRCK_DELAY_BCK_INV_MASK_SFT                       (0x1 << 30)
+#define OUT_REG_OFF_CR_EN_SFT                                     31
+#define OUT_REG_OFF_CR_EN_MASK                                    0x1
+#define OUT_REG_OFF_CR_EN_MASK_SFT                                (0x1 << 31)
+
+/* ETDM_OUT0_CON3 */
+/* ETDM_OUT1_CON3 */
+/* ETDM_OUT2_CON3 */
+/* ETDM_OUT3_CON3 */
+/* ETDM_OUT4_CON3 */
+/* ETDM_OUT5_CON3 */
+/* ETDM_OUT6_CON3 */
+#define OUT_REG_START_CH_PAIR0_SFT                                0
+#define OUT_REG_START_CH_PAIR0_MASK                               0xf
+#define OUT_REG_START_CH_PAIR0_MASK_SFT                           (0xf << 0)
+#define OUT_REG_START_CH_PAIR1_SFT                                4
+#define OUT_REG_START_CH_PAIR1_MASK                               0xf
+#define OUT_REG_START_CH_PAIR1_MASK_SFT                           (0xf << 4)
+#define OUT_REG_START_CH_PAIR2_SFT                                8
+#define OUT_REG_START_CH_PAIR2_MASK                               0xf
+#define OUT_REG_START_CH_PAIR2_MASK_SFT                           (0xf << 8)
+#define OUT_REG_START_CH_PAIR3_SFT                                12
+#define OUT_REG_START_CH_PAIR3_MASK                               0xf
+#define OUT_REG_START_CH_PAIR3_MASK_SFT                           (0xf << 12)
+#define OUT_REG_START_CH_PAIR4_SFT                                16
+#define OUT_REG_START_CH_PAIR4_MASK                               0xf
+#define OUT_REG_START_CH_PAIR4_MASK_SFT                           (0xf << 16)
+#define OUT_REG_START_CH_PAIR5_SFT                                20
+#define OUT_REG_START_CH_PAIR5_MASK                               0xf
+#define OUT_REG_START_CH_PAIR5_MASK_SFT                           (0xf << 20)
+#define OUT_REG_START_CH_PAIR6_SFT                                24
+#define OUT_REG_START_CH_PAIR6_MASK                               0xf
+#define OUT_REG_START_CH_PAIR6_MASK_SFT                           (0xf << 24)
+#define OUT_REG_START_CH_PAIR7_SFT                                28
+#define OUT_REG_START_CH_PAIR7_MASK                               0xf
+#define OUT_REG_START_CH_PAIR7_MASK_SFT                           (0xf << 28)
+
+/* ETDM_OUT0_CON4 */
+/* ETDM_OUT1_CON4 */
+/* ETDM_OUT2_CON4 */
+/* ETDM_OUT3_CON4 */
+/* ETDM_OUT4_CON4 */
+/* ETDM_OUT5_CON4 */
+/* ETDM_OUT6_CON4 */
+#define OUT_REG_FS_TIMING_SEL_SFT                                 0
+#define OUT_REG_FS_TIMING_SEL_MASK                                0x1f
+#define OUT_REG_FS_TIMING_SEL_MASK_SFT                            (0x1f << 0)
+#define OUT_REG_CLOCK_SOURCE_SEL_SFT                              6
+#define OUT_REG_CLOCK_SOURCE_SEL_MASK                             0x7
+#define OUT_REG_CLOCK_SOURCE_SEL_MASK_SFT                         (0x7 << 6)
+#define OUT_REG_CK_EN_SEL_AUTO_SFT                                10
+#define OUT_REG_CK_EN_SEL_AUTO_MASK                               0x1
+#define OUT_REG_CK_EN_SEL_AUTO_MASK_SFT                           (0x1 << 10)
+#define OUT_REG_ASYNC_RESET_SFT                                   11
+#define OUT_REG_ASYNC_RESET_MASK                                  0x1
+#define OUT_REG_ASYNC_RESET_MASK_SFT                              (0x1 << 11)
+#define OUT_REG_CK_EN_SEL_MANUAL_SFT                              14
+#define OUT_REG_CK_EN_SEL_MANUAL_MASK                             0x3ff
+#define OUT_REG_CK_EN_SEL_MANUAL_MASK_SFT                         (0x3ff << 14)
+#define OUT_REG_RELATCH_EN_SEL_SFT                                24
+#define OUT_REG_RELATCH_EN_SEL_MASK                               0x1f
+#define OUT_REG_RELATCH_EN_SEL_MASK_SFT                           (0x1f << 24)
+#define OUT_REG_WAIT_LAST_SAMPLE_SFT                              30
+#define OUT_REG_WAIT_LAST_SAMPLE_MASK                             0x1
+#define OUT_REG_WAIT_LAST_SAMPLE_MASK_SFT                         (0x1 << 30)
+#define OUT_REG_ALWAYS_OPEN_1X_EN_SFT                             31
+#define OUT_REG_ALWAYS_OPEN_1X_EN_MASK                            0x1
+#define OUT_REG_ALWAYS_OPEN_1X_EN_MASK_SFT                        (0x1 << 31)
+
+/* ETDM_OUT0_CON5 */
+/* ETDM_OUT1_CON5 */
+/* ETDM_OUT2_CON5 */
+/* ETDM_OUT3_CON5 */
+/* ETDM_OUT4_CON5 */
+/* ETDM_OUT5_CON5 */
+/* ETDM_OUT6_CON5 */
+#define OUT_REG_REPACK_BITNUM_SFT                                 0
+#define OUT_REG_REPACK_BITNUM_MASK                                0x3
+#define OUT_REG_REPACK_BITNUM_MASK_SFT                            (0x3 << 0)
+#define OUT_REG_REPACK_CHNUM_SFT                                  2
+#define OUT_REG_REPACK_CHNUM_MASK                                 0xf
+#define OUT_REG_REPACK_CHNUM_MASK_SFT                             (0xf << 2)
+#define OUT_REG_SLAVE_BCK_INV_SFT                                 7
+#define OUT_REG_SLAVE_BCK_INV_MASK                                0x1
+#define OUT_REG_SLAVE_BCK_INV_MASK_SFT                            (0x1 << 7)
+#define OUT_REG_SLAVE_LRCK_INV_SFT                                8
+#define OUT_REG_SLAVE_LRCK_INV_MASK                               0x1
+#define OUT_REG_SLAVE_LRCK_INV_MASK_SFT                           (0x1 << 8)
+#define OUT_REG_MASTER_BCK_INV_SFT                                9
+#define OUT_REG_MASTER_BCK_INV_MASK                               0x1
+#define OUT_REG_MASTER_BCK_INV_MASK_SFT                           (0x1 << 9)
+#define OUT_REG_MASTER_WS_INV_SFT                                 10
+#define OUT_REG_MASTER_WS_INV_MASK                                0x1
+#define OUT_REG_MASTER_WS_INV_MASK_SFT                            (0x1 << 10)
+#define OUT_REG_REPACK_24B_MSB_ALIGN_SFT                          11
+#define OUT_REG_REPACK_24B_MSB_ALIGN_MASK                         0x1
+#define OUT_REG_REPACK_24B_MSB_ALIGN_MASK_SFT                     (0x1 << 11)
+#define OUT_REG_LR_SWAP_SFT                                       16
+#define OUT_REG_LR_SWAP_MASK                                      0xffff
+#define OUT_REG_LR_SWAP_MASK_SFT                                  (0xffff << 16)
+
+/* ETDM_OUT0_CON6 */
+/* ETDM_OUT1_CON6 */
+/* ETDM_OUT2_CON6 */
+/* ETDM_OUT3_CON6 */
+/* ETDM_OUT4_CON6 */
+/* ETDM_OUT5_CON6 */
+/* ETDM_OUT6_CON6 */
+#define OUT_LCH_DATA_REG_SFT                                      0
+#define OUT_LCH_DATA_REG_MASK                                     0xffffffff
+#define OUT_LCH_DATA_REG_MASK_SFT                                 (0xffffffff << 0)
+
+/* ETDM_OUT0_CON7 */
+/* ETDM_OUT1_CON7 */
+/* ETDM_OUT2_CON7 */
+/* ETDM_OUT3_CON7 */
+/* ETDM_OUT4_CON7 */
+/* ETDM_OUT5_CON7 */
+/* ETDM_OUT6_CON7 */
+#define OUT_RCH_DATA_REG_SFT                                      0
+#define OUT_RCH_DATA_REG_MASK                                     0xffffffff
+#define OUT_RCH_DATA_REG_MASK_SFT                                 (0xffffffff << 0)
+
+/* ETDM_OUT0_CON8 */
+/* ETDM_OUT1_CON8 */
+/* ETDM_OUT2_CON8 */
+/* ETDM_OUT3_CON8 */
+/* ETDM_OUT4_CON8 */
+/* ETDM_OUT5_CON8 */
+/* ETDM_OUT6_CON8 */
+#define OUT_REG_START_CH_PAIR8_SFT                                0
+#define OUT_REG_START_CH_PAIR8_MASK                               0xf
+#define OUT_REG_START_CH_PAIR8_MASK_SFT                           (0xf << 0)
+#define OUT_REG_START_CH_PAIR9_SFT                                4
+#define OUT_REG_START_CH_PAIR9_MASK                               0xf
+#define OUT_REG_START_CH_PAIR9_MASK_SFT                           (0xf << 4)
+#define OUT_REG_START_CH_PAIR10_SFT                               8
+#define OUT_REG_START_CH_PAIR10_MASK                              0xf
+#define OUT_REG_START_CH_PAIR10_MASK_SFT                          (0xf << 8)
+#define OUT_REG_START_CH_PAIR11_SFT                               12
+#define OUT_REG_START_CH_PAIR11_MASK                              0xf
+#define OUT_REG_START_CH_PAIR11_MASK_SFT                          (0xf << 12)
+#define OUT_REG_START_CH_PAIR12_SFT                               16
+#define OUT_REG_START_CH_PAIR12_MASK                              0xf
+#define OUT_REG_START_CH_PAIR12_MASK_SFT                          (0xf << 16)
+#define OUT_REG_START_CH_PAIR13_SFT                               20
+#define OUT_REG_START_CH_PAIR13_MASK                              0xf
+#define OUT_REG_START_CH_PAIR13_MASK_SFT                          (0xf << 20)
+#define OUT_REG_START_CH_PAIR14_SFT                               24
+#define OUT_REG_START_CH_PAIR14_MASK                              0xf
+#define OUT_REG_START_CH_PAIR14_MASK_SFT                          (0xf << 24)
+#define OUT_REG_START_CH_PAIR15_SFT                               28
+#define OUT_REG_START_CH_PAIR15_MASK                              0xf
+#define OUT_REG_START_CH_PAIR15_MASK_SFT                          (0xf << 28)
+
+/* ETDM_OUT0_CON9 */
+/* ETDM_OUT1_CON9 */
+/* ETDM_OUT2_CON9 */
+/* ETDM_OUT3_CON9 */
+/* ETDM_OUT4_CON9 */
+/* ETDM_OUT5_CON9 */
+/* ETDM_OUT6_CON9 */
+#define OUT_REG_AFIFO_THRESHOLD_SFT                               29
+#define OUT_REG_AFIFO_THRESHOLD_MASK                              0x3
+#define OUT_REG_AFIFO_THRESHOLD_MASK_SFT                          (0x3 << 29)
+#define OUT_REG_AFIFO_SW_RESET_SFT                                15
+#define OUT_REG_AFIFO_SW_RESET_MASK                               0x1
+#define OUT_REG_AFIFO_SW_RESET_MASK_SFT                           (0x1 << 15)
+#define OUT_REG_AFIFO_RESET_SEL_SFT                               14
+#define OUT_REG_AFIFO_RESET_SEL_MASK                              0x1
+#define OUT_REG_AFIFO_RESET_SEL_MASK_SFT                          (0x1 << 14)
+#define OUT_REG_AFIFO_AUTO_RESET_DIS_SFT                          9
+#define OUT_REG_AFIFO_AUTO_RESET_DIS_MASK                         0x1
+#define OUT_REG_AFIFO_AUTO_RESET_DIS_MASK_SFT                     (0x1 << 9)
+#define OUT_REG_ETDM_USE_AFIFO_SFT                                8
+#define OUT_REG_ETDM_USE_AFIFO_MASK                               0x1
+#define OUT_REG_ETDM_USE_AFIFO_MASK_SFT                           (0x1 << 8)
+#define OUT_REG_AFIFO_CLOCK_DOMAIN_SEL_SFT                        5
+#define OUT_REG_AFIFO_CLOCK_DOMAIN_SEL_MASK                       0x7
+#define OUT_REG_AFIFO_CLOCK_DOMAIN_SEL_MASK_SFT                   (0x7 << 5)
+#define OUT_REG_AFIFO_MODE_SFT                                    0
+#define OUT_REG_AFIFO_MODE_MASK                                   0x1f
+#define OUT_REG_AFIFO_MODE_MASK_SFT                               (0x1f << 0)
+
+/* ETDM_OUT0_MON */
+/* ETDM_OUT1_MON */
+/* ETDM_OUT2_MON */
+/* ETDM_OUT3_MON */
+/* ETDM_OUT4_MON */
+/* ETDM_OUT5_MON */
+/* ETDM_OUT6_MON */
+#define LRCK_INV_SFT                                          30
+#define LRCK_INV_MASK                                         0x1
+#define LRCK_INV_MASK_SFT                                     (0x1 << 30)
+#define EN_SYNC_OUT_SFT                                       29
+#define EN_SYNC_OUT_MASK                                      0x1
+#define EN_SYNC_OUT_MASK_SFT                                  (0x1 << 29)
+#define HOPPING_EN_SYNC_OUT_PRE_SFT                           28
+#define HOPPING_EN_SYNC_OUT_PRE_MASK                          0x1
+#define HOPPING_EN_SYNC_OUT_PRE_MASK_SFT                      (0x1 << 28)
+#define ETDM_2X_CK_EN_SFT                                     25
+#define ETDM_2X_CK_EN_MASK                                    0x1
+#define ETDM_2X_CK_EN_MASK_SFT                                (0x1 << 25)
+#define ETDM_1X_CK_EN_SFT                                     24
+#define ETDM_1X_CK_EN_MASK                                    0x1
+#define ETDM_1X_CK_EN_MASK_SFT                                (0x1 << 24)
+#define SDATA0_SFT                                            23
+#define SDATA0_MASK                                           0x1
+#define SDATA0_MASK_SFT                                       (0x1 << 23)
+#define CURRENT_STATUS_SFT                                    21
+#define CURRENT_STATUS_MASK                                   0x3
+#define CURRENT_STATUS_MASK_SFT                               (0x3 << 21)
+#define BIT_POINT_SFT                                         16
+#define BIT_POINT_MASK                                        0x1f
+#define BIT_POINT_MASK_SFT                                    (0x1f << 16)
+#define BIT_CH_COUNT_SFT                                      10
+#define BIT_CH_COUNT_MASK                                     0x3f
+#define BIT_CH_COUNT_MASK_SFT                                 (0x3f << 10)
+#define BIT_COUNT_SFT                                         5
+#define BIT_COUNT_MASK                                        0x1f
+#define BIT_COUNT_MASK_SFT                                    (0x1f << 5)
+#define CH_COUNT_SFT                                          0
+#define CH_COUNT_MASK                                         0x1f
+#define CH_COUNT_MASK_SFT                                     (0x1f << 0)
+
+/* ETDM_0_3_COWORK_CON0 */
+#define ETDM_OUT0_DATA_SEL_SFT                                0
+#define ETDM_OUT0_DATA_SEL_MASK                               0xf
+#define ETDM_OUT0_DATA_SEL_MASK_SFT                           (0xf << 0)
+#define ETDM_OUT0_SYNC_SEL_SFT                                4
+#define ETDM_OUT0_SYNC_SEL_MASK                               0xf
+#define ETDM_OUT0_SYNC_SEL_MASK_SFT                           (0xf << 4)
+#define ETDM_OUT0_SLAVE_SEL_SFT                               8
+#define ETDM_OUT0_SLAVE_SEL_MASK                              0xf
+#define ETDM_OUT0_SLAVE_SEL_MASK_SFT                          (0xf << 8)
+#define ETDM_OUT1_DATA_SEL_SFT                                12
+#define ETDM_OUT1_DATA_SEL_MASK                               0xf
+#define ETDM_OUT1_DATA_SEL_MASK_SFT                           (0xf << 12)
+#define ETDM_OUT1_SYNC_SEL_SFT                                16
+#define ETDM_OUT1_SYNC_SEL_MASK                               0xf
+#define ETDM_OUT1_SYNC_SEL_MASK_SFT                           (0xf << 16)
+#define ETDM_OUT1_SLAVE_SEL_SFT                               20
+#define ETDM_OUT1_SLAVE_SEL_MASK                              0xf
+#define ETDM_OUT1_SLAVE_SEL_MASK_SFT                          (0xf << 20)
+#define ETDM_IN0_SLAVE_SEL_SFT                                24
+#define ETDM_IN0_SLAVE_SEL_MASK                               0xf
+#define ETDM_IN0_SLAVE_SEL_MASK_SFT                           (0xf << 24)
+#define ETDM_IN0_SYNC_SEL_SFT                                 28
+#define ETDM_IN0_SYNC_SEL_MASK                                0xf
+#define ETDM_IN0_SYNC_SEL_MASK_SFT                            (0xf << 28)
+
+/* ETDM_0_3_COWORK_CON1 */
+#define ETDM_IN0_SDATA0_SEL_SFT                               0
+#define ETDM_IN0_SDATA0_SEL_MASK                              0xf
+#define ETDM_IN0_SDATA0_SEL_MASK_SFT                          (0xf << 0)
+#define ETDM_IN0_SDATA1_15_SEL_SFT                            4
+#define ETDM_IN0_SDATA1_15_SEL_MASK                           0xf
+#define ETDM_IN0_SDATA1_15_SEL_MASK_SFT                       (0xf << 4)
+#define ETDM_IN1_SLAVE_SEL_SFT                                8
+#define ETDM_IN1_SLAVE_SEL_MASK                               0xf
+#define ETDM_IN1_SLAVE_SEL_MASK_SFT                           (0xf << 8)
+#define ETDM_IN1_SYNC_SEL_SFT                                 12
+#define ETDM_IN1_SYNC_SEL_MASK                                0xf
+#define ETDM_IN1_SYNC_SEL_MASK_SFT                            (0xf << 12)
+#define ETDM_IN1_SDATA0_SEL_SFT                               16
+#define ETDM_IN1_SDATA0_SEL_MASK                              0xf
+#define ETDM_IN1_SDATA0_SEL_MASK_SFT                          (0xf << 16)
+#define ETDM_IN1_SDATA1_15_SEL_SFT                            20
+#define ETDM_IN1_SDATA1_15_SEL_MASK                           0xf
+#define ETDM_IN1_SDATA1_15_SEL_MASK_SFT                       (0xf << 20)
+
+/* ETDM_0_3_COWORK_CON2 */
+#define ETDM_OUT2_DATA_SEL_SFT                                0
+#define ETDM_OUT2_DATA_SEL_MASK                               0xf
+#define ETDM_OUT2_DATA_SEL_MASK_SFT                           (0xf << 0)
+#define ETDM_OUT2_SYNC_SEL_SFT                                4
+#define ETDM_OUT2_SYNC_SEL_MASK                               0xf
+#define ETDM_OUT2_SYNC_SEL_MASK_SFT                           (0xf << 4)
+#define ETDM_OUT2_SLAVE_SEL_SFT                               8
+#define ETDM_OUT2_SLAVE_SEL_MASK                              0xf
+#define ETDM_OUT2_SLAVE_SEL_MASK_SFT                          (0xf << 8)
+#define ETDM_OUT3_DATA_SEL_SFT                                12
+#define ETDM_OUT3_DATA_SEL_MASK                               0xf
+#define ETDM_OUT3_DATA_SEL_MASK_SFT                           (0xf << 12)
+#define ETDM_OUT3_SYNC_SEL_SFT                                16
+#define ETDM_OUT3_SYNC_SEL_MASK                               0xf
+#define ETDM_OUT3_SYNC_SEL_MASK_SFT                           (0xf << 16)
+#define ETDM_OUT3_SLAVE_SEL_SFT                               20
+#define ETDM_OUT3_SLAVE_SEL_MASK                              0xf
+#define ETDM_OUT3_SLAVE_SEL_MASK_SFT                          (0xf << 20)
+#define ETDM_IN2_SLAVE_SEL_SFT                                24
+#define ETDM_IN2_SLAVE_SEL_MASK                               0xf
+#define ETDM_IN2_SLAVE_SEL_MASK_SFT                           (0xf << 24)
+#define ETDM_IN2_SYNC_SEL_SFT                                 28
+#define ETDM_IN2_SYNC_SEL_MASK                                0xf
+#define ETDM_IN2_SYNC_SEL_MASK_SFT                            (0xf << 28)
+
+/* ETDM_0_3_COWORK_CON3 */
+#define ETDM_IN2_SDATA0_SEL_SFT                               0
+#define ETDM_IN2_SDATA0_SEL_MASK                              0xf
+#define ETDM_IN2_SDATA0_SEL_MASK_SFT                          (0xf << 0)
+#define ETDM_IN2_SDATA1_15_SEL_SFT                            4
+#define ETDM_IN2_SDATA1_15_SEL_MASK                           0xf
+#define ETDM_IN2_SDATA1_15_SEL_MASK_SFT                       (0xf << 4)
+#define ETDM_IN3_SLAVE_SEL_SFT                                8
+#define ETDM_IN3_SLAVE_SEL_MASK                               0xf
+#define ETDM_IN3_SLAVE_SEL_MASK_SFT                           (0xf << 8)
+#define ETDM_IN3_SYNC_SEL_SFT                                 12
+#define ETDM_IN3_SYNC_SEL_MASK                                0xf
+#define ETDM_IN3_SYNC_SEL_MASK_SFT                            (0xf << 12)
+#define ETDM_IN3_SDATA0_SEL_SFT                               16
+#define ETDM_IN3_SDATA0_SEL_MASK                              0xf
+#define ETDM_IN3_SDATA0_SEL_MASK_SFT                          (0xf << 16)
+#define ETDM_IN3_SDATA1_15_SEL_SFT                            20
+#define ETDM_IN3_SDATA1_15_SEL_MASK                           0xf
+#define ETDM_IN3_SDATA1_15_SEL_MASK_SFT                       (0xf << 20)
+
+/* ETDM_4_7_COWORK_CON0 */
+#define ETDM_OUT4_DATA_SEL_SFT                                0
+#define ETDM_OUT4_DATA_SEL_MASK                               0xf
+#define ETDM_OUT4_DATA_SEL_MASK_SFT                           (0xf << 0)
+#define ETDM_OUT4_SYNC_SEL_SFT                                4
+#define ETDM_OUT4_SYNC_SEL_MASK                               0xf
+#define ETDM_OUT4_SYNC_SEL_MASK_SFT                           (0xf << 4)
+#define ETDM_OUT4_SLAVE_SEL_SFT                               8
+#define ETDM_OUT4_SLAVE_SEL_MASK                              0xf
+#define ETDM_OUT4_SLAVE_SEL_MASK_SFT                          (0xf << 8)
+#define ETDM_OUT5_DATA_SEL_SFT                                12
+#define ETDM_OUT5_DATA_SEL_MASK                               0xf
+#define ETDM_OUT5_DATA_SEL_MASK_SFT                           (0xf << 12)
+#define ETDM_OUT5_SYNC_SEL_SFT                                16
+#define ETDM_OUT5_SYNC_SEL_MASK                               0xf
+#define ETDM_OUT5_SYNC_SEL_MASK_SFT                           (0xf << 16)
+#define ETDM_OUT5_SLAVE_SEL_SFT                               20
+#define ETDM_OUT5_SLAVE_SEL_MASK                              0xf
+#define ETDM_OUT5_SLAVE_SEL_MASK_SFT                          (0xf << 20)
+#define ETDM_IN4_SLAVE_SEL_SFT                                24
+#define ETDM_IN4_SLAVE_SEL_MASK                               0xf
+#define ETDM_IN4_SLAVE_SEL_MASK_SFT                           (0xf << 24)
+#define ETDM_IN4_SYNC_SEL_SFT                                 28
+#define ETDM_IN4_SYNC_SEL_MASK                                0xf
+#define ETDM_IN4_SYNC_SEL_MASK_SFT                            (0xf << 28)
+
+/* ETDM_4_7_COWORK_CON1 */
+#define ETDM_IN4_SDATA0_SEL_SFT                               0
+#define ETDM_IN4_SDATA0_SEL_MASK                              0xf
+#define ETDM_IN4_SDATA0_SEL_MASK_SFT                          (0xf << 0)
+#define ETDM_IN4_SDATA1_15_SEL_SFT                            4
+#define ETDM_IN4_SDATA1_15_SEL_MASK                           0xf
+#define ETDM_IN4_SDATA1_15_SEL_MASK_SFT                       (0xf << 4)
+#define ETDM_IN5_SLAVE_SEL_SFT                                8
+#define ETDM_IN5_SLAVE_SEL_MASK                               0xf
+#define ETDM_IN5_SLAVE_SEL_MASK_SFT                           (0xf << 8)
+#define ETDM_IN5_SYNC_SEL_SFT                                 12
+#define ETDM_IN5_SYNC_SEL_MASK                                0xf
+#define ETDM_IN5_SYNC_SEL_MASK_SFT                            (0xf << 12)
+#define ETDM_IN5_SDATA0_SEL_SFT                               16
+#define ETDM_IN5_SDATA0_SEL_MASK                              0xf
+#define ETDM_IN5_SDATA0_SEL_MASK_SFT                          (0xf << 16)
+#define ETDM_IN5_SDATA1_15_SEL_SFT                            20
+#define ETDM_IN5_SDATA1_15_SEL_MASK                           0xf
+#define ETDM_IN5_SDATA1_15_SEL_MASK_SFT                       (0xf << 20)
+
+/* ETDM_4_7_COWORK_CON2 */
+#define ETDM_OUT6_DATA_SEL_SFT                                0
+#define ETDM_OUT6_DATA_SEL_MASK                               0xf
+#define ETDM_OUT6_DATA_SEL_MASK_SFT                           (0xf << 0)
+#define ETDM_OUT6_SYNC_SEL_SFT                                4
+#define ETDM_OUT6_SYNC_SEL_MASK                               0xf
+#define ETDM_OUT6_SYNC_SEL_MASK_SFT                           (0xf << 4)
+#define ETDM_OUT6_SLAVE_SEL_SFT                               8
+#define ETDM_OUT6_SLAVE_SEL_MASK                              0xf
+#define ETDM_OUT6_SLAVE_SEL_MASK_SFT                          (0xf << 8)
+#define ETDM_OUT7_DATA_SEL_SFT                                12
+#define ETDM_OUT7_DATA_SEL_MASK                               0xf
+#define ETDM_OUT7_DATA_SEL_MASK_SFT                           (0xf << 12)
+#define ETDM_OUT7_SYNC_SEL_SFT                                16
+#define ETDM_OUT7_SYNC_SEL_MASK                               0xf
+#define ETDM_OUT7_SYNC_SEL_MASK_SFT                           (0xf << 16)
+#define ETDM_OUT7_SLAVE_SEL_SFT                               20
+#define ETDM_OUT7_SLAVE_SEL_MASK                              0xf
+#define ETDM_OUT7_SLAVE_SEL_MASK_SFT                          (0xf << 20)
+#define ETDM_IN6_SLAVE_SEL_SFT                                24
+#define ETDM_IN6_SLAVE_SEL_MASK                               0xf
+#define ETDM_IN6_SLAVE_SEL_MASK_SFT                           (0xf << 24)
+#define ETDM_IN6_SYNC_SEL_SFT                                 28
+#define ETDM_IN6_SYNC_SEL_MASK                                0xf
+#define ETDM_IN6_SYNC_SEL_MASK_SFT                            (0xf << 28)
+
+/* ETDM_4_7_COWORK_CON3 */
+#define ETDM_IN6_SDATA0_SEL_SFT                               0
+#define ETDM_IN6_SDATA0_SEL_MASK                              0xf
+#define ETDM_IN6_SDATA0_SEL_MASK_SFT                          (0xf << 0)
+#define ETDM_IN6_SDATA1_15_SEL_SFT                            4
+#define ETDM_IN6_SDATA1_15_SEL_MASK                           0xf
+#define ETDM_IN6_SDATA1_15_SEL_MASK_SFT                       (0xf << 4)
+#define ETDM_IN7_SLAVE_SEL_SFT                                8
+#define ETDM_IN7_SLAVE_SEL_MASK                               0xf
+#define ETDM_IN7_SLAVE_SEL_MASK_SFT                           (0xf << 8)
+#define ETDM_IN7_SYNC_SEL_SFT                                 12
+#define ETDM_IN7_SYNC_SEL_MASK                                0xf
+#define ETDM_IN7_SYNC_SEL_MASK_SFT                            (0xf << 12)
+#define ETDM_IN7_SDATA0_SEL_SFT                               16
+#define ETDM_IN7_SDATA0_SEL_MASK                              0xf
+#define ETDM_IN7_SDATA0_SEL_MASK_SFT                          (0xf << 16)
+#define ETDM_IN7_SDATA1_15_SEL_SFT                            20
+#define ETDM_IN7_SDATA1_15_SEL_MASK                           0xf
+#define ETDM_IN7_SDATA1_15_SEL_MASK_SFT                       (0xf << 20)
+
+/* AFE_DPTX_CON */
+#define DPTX_CHANNEL_ENABLE_SFT                               8
+#define DPTX_CHANNEL_ENABLE_MASK                              0xff
+#define DPTX_CHANNEL_ENABLE_MASK_SFT                          (0xff << 8)
+#define DPTX_REGISTER_MONITOR_SELECT_SFT                      3
+#define DPTX_REGISTER_MONITOR_SELECT_MASK                     0xf
+#define DPTX_REGISTER_MONITOR_SELECT_MASK_SFT                 (0xf << 3)
+#define DPTX_16BIT_SFT                                        2
+#define DPTX_16BIT_MASK                                       0x1
+#define DPTX_16BIT_MASK_SFT                                   (0x1 << 2)
+#define DPTX_CHANNEL_NUMBER_SFT                               1
+#define DPTX_CHANNEL_NUMBER_MASK                              0x1
+#define DPTX_CHANNEL_NUMBER_MASK_SFT                          (0x1 << 1)
+#define DPTX_ON_SFT                                           0
+#define DPTX_ON_MASK                                          0x1
+#define DPTX_ON_MASK_SFT                                      (0x1 << 0)
+
+/* AFE_DPTX_MON */
+#define AFE_DPTX_MON0_SFT                                     0
+#define AFE_DPTX_MON0_MASK                                    0xffffffff
+#define AFE_DPTX_MON0_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_TDM_CON1 */
+#define TDM_EN_SFT                                            0
+#define TDM_EN_MASK                                           0x1
+#define TDM_EN_MASK_SFT                                       (0x1 << 0)
+#define BCK_INVERSE_SFT                                       1
+#define BCK_INVERSE_MASK                                      0x1
+#define BCK_INVERSE_MASK_SFT                                  (0x1 << 1)
+#define LRCK_INVERSE_SFT                                      2
+#define LRCK_INVERSE_MASK                                     0x1
+#define LRCK_INVERSE_MASK_SFT                                 (0x1 << 2)
+#define DELAY_DATA_SFT                                        3
+#define DELAY_DATA_MASK                                       0x1
+#define DELAY_DATA_MASK_SFT                                   (0x1 << 3)
+#define LEFT_ALIGN_SFT                                        4
+#define LEFT_ALIGN_MASK                                       0x1
+#define LEFT_ALIGN_MASK_SFT                                   (0x1 << 4)
+#define TDM_LRCK_D0P5T_SFT                                    5
+#define TDM_LRCK_D0P5T_MASK                                   0x1
+#define TDM_LRCK_D0P5T_MASK_SFT                               (0x1 << 5)
+#define TDM_SDATA_D0P5T_SFT                                   6
+#define TDM_SDATA_D0P5T_MASK                                  0x1
+#define TDM_SDATA_D0P5T_MASK_SFT                              (0x1 << 6)
+#define WLEN_SFT                                              8
+#define WLEN_MASK                                             0x3
+#define WLEN_MASK_SFT                                         (0x3 << 8)
+#define CHANNEL_NUM_SFT                                       10
+#define CHANNEL_NUM_MASK                                      0x3
+#define CHANNEL_NUM_MASK_SFT                                  (0x3 << 10)
+#define CHANNEL_BCK_CYCLES_SFT                                12
+#define CHANNEL_BCK_CYCLES_MASK                               0x3
+#define CHANNEL_BCK_CYCLES_MASK_SFT                           (0x3 << 12)
+#define HDMI_CLK_INV_SEL_SFT                                  15
+#define HDMI_CLK_INV_SEL_MASK                                 0x1
+#define HDMI_CLK_INV_SEL_MASK_SFT                             (0x1 << 15)
+#define DAC_BIT_NUM_SFT                                       16
+#define DAC_BIT_NUM_MASK                                      0x1f
+#define DAC_BIT_NUM_MASK_SFT                                  (0x1f << 16)
+#define LRCK_TDM_WIDTH_SFT                                    24
+#define LRCK_TDM_WIDTH_MASK                                   0xff
+#define LRCK_TDM_WIDTH_MASK_SFT                               (0xff << 24)
+
+/* AFE_TDM_CON2 */
+#define ST_CH_PAIR_SOUT0_SFT                                  0
+#define ST_CH_PAIR_SOUT0_MASK                                 0x7
+#define ST_CH_PAIR_SOUT0_MASK_SFT                             (0x7 << 0)
+#define ST_CH_PAIR_SOUT1_SFT                                  4
+#define ST_CH_PAIR_SOUT1_MASK                                 0x7
+#define ST_CH_PAIR_SOUT1_MASK_SFT                             (0x7 << 4)
+#define ST_CH_PAIR_SOUT2_SFT                                  8
+#define ST_CH_PAIR_SOUT2_MASK                                 0x7
+#define ST_CH_PAIR_SOUT2_MASK_SFT                             (0x7 << 8)
+#define ST_CH_PAIR_SOUT3_SFT                                  12
+#define ST_CH_PAIR_SOUT3_MASK                                 0x7
+#define ST_CH_PAIR_SOUT3_MASK_SFT                             (0x7 << 12)
+#define TDM_FIX_VALUE_SEL_SFT                                 16
+#define TDM_FIX_VALUE_SEL_MASK                                0x1
+#define TDM_FIX_VALUE_SEL_MASK_SFT                            (0x1 << 16)
+#define TDM_I2S_LOOPBACK_SFT                                  20
+#define TDM_I2S_LOOPBACK_MASK                                 0x1
+#define TDM_I2S_LOOPBACK_MASK_SFT                             (0x1 << 20)
+#define TDM_I2S_LOOPBACK_CH_SFT                               21
+#define TDM_I2S_LOOPBACK_CH_MASK                              0x3
+#define TDM_I2S_LOOPBACK_CH_MASK_SFT                          (0x3 << 21)
+#define TDM_USE_SINEGEN_INPUT_SFT                             23
+#define TDM_USE_SINEGEN_INPUT_MASK                            0x1
+#define TDM_USE_SINEGEN_INPUT_MASK_SFT                        (0x1 << 23)
+#define TDM_FIX_VALUE_SFT                                     24
+#define TDM_FIX_VALUE_MASK                                    0xff
+#define TDM_FIX_VALUE_MASK_SFT                                (0xff << 24)
+
+/* AFE_TDM_CON3 */
+#define TDM_OUT_SEL_DOMAIN_SFT                                29
+#define TDM_OUT_SEL_DOMAIN_MASK                               0x7
+#define TDM_OUT_SEL_DOMAIN_MASK_SFT                           (0x7 << 29)
+#define TDM_OUT_SEL_FS_SFT                                    24
+#define TDM_OUT_SEL_FS_MASK                                   0x1f
+#define TDM_OUT_SEL_FS_MASK_SFT                               (0x1f << 24)
+#define TDM_OUT_MON_SEL_SFT                                   3
+#define TDM_OUT_MON_SEL_MASK                                  0x1
+#define TDM_OUT_MON_SEL_MASK_SFT                              (0x1 << 3)
+#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_EN_SFT                 2
+#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_EN_MASK                0x1
+#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT            (0x1 << 2)
+#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_SFT                    1
+#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_MASK                   0x1
+#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_MASK_SFT               (0x1 << 1)
+#define TDM_UPDATE_EN_SEL_SFT                                 0
+#define TDM_UPDATE_EN_SEL_MASK                                0x1
+#define TDM_UPDATE_EN_SEL_MASK_SFT                            (0x1 << 0)
+
+/* AFE_TDM_OUT_MON */
+#define AFE_TDM_OUT_MON_SFT                                   0
+#define AFE_TDM_OUT_MON_MASK                                  0xffffffff
+#define AFE_TDM_OUT_MON_MASK_SFT                              (0xffffffff << 0)
+
+/* AFE_HDMI_CONN0 */
+#define HDMI_O_7_SFT                                          21
+#define HDMI_O_7_MASK                                         0x7
+#define HDMI_O_7_MASK_SFT                                     (0x7 << 21)
+#define HDMI_O_6_SFT                                          18
+#define HDMI_O_6_MASK                                         0x7
+#define HDMI_O_6_MASK_SFT                                     (0x7 << 18)
+#define HDMI_O_5_SFT                                          15
+#define HDMI_O_5_MASK                                         0x7
+#define HDMI_O_5_MASK_SFT                                     (0x7 << 15)
+#define HDMI_O_4_SFT                                          12
+#define HDMI_O_4_MASK                                         0x7
+#define HDMI_O_4_MASK_SFT                                     (0x7 << 12)
+#define HDMI_O_3_SFT                                          9
+#define HDMI_O_3_MASK                                         0x7
+#define HDMI_O_3_MASK_SFT                                     (0x7 << 9)
+#define HDMI_O_2_SFT                                          6
+#define HDMI_O_2_MASK                                         0x7
+#define HDMI_O_2_MASK_SFT                                     (0x7 << 6)
+#define HDMI_O_1_SFT                                          3
+#define HDMI_O_1_MASK                                         0x7
+#define HDMI_O_1_MASK_SFT                                     (0x7 << 3)
+#define HDMI_O_0_SFT                                          0
+#define HDMI_O_0_MASK                                         0x7
+#define HDMI_O_0_MASK_SFT                                     (0x7 << 0)
+
+/* AFE_TDM_TOP_IP_VERSION */
+#define AFE_TDM_TOP_IP_VERSION_SFT                            0
+#define AFE_TDM_TOP_IP_VERSION_MASK                           0xffffffff
+#define AFE_TDM_TOP_IP_VERSION_MASK_SFT                       (0xffffffff << 0)
+
+/* AFE_CBIP_CFG0 */
+#define CBIP_TOP_SLV_MUX_WAY_EN_SFT                           16
+#define CBIP_TOP_SLV_MUX_WAY_EN_MASK                          0xffff
+#define CBIP_TOP_SLV_MUX_WAY_EN_MASK_SFT                      (0xffff << 16)
+#define RESERVED_04_SFT                                       15
+#define RESERVED_04_MASK                                      0x1
+#define RESERVED_04_MASK_SFT                                  (0x1 << 15)
+#define CBIP_ASYNC_MST_RG_FIFO_THRE_SFT                       13
+#define CBIP_ASYNC_MST_RG_FIFO_THRE_MASK                      0x3
+#define CBIP_ASYNC_MST_RG_FIFO_THRE_MASK_SFT                  (0x3 << 13)
+#define CBIP_ASYNC_MST_POSTWRITE_DIS_SFT                      12
+#define CBIP_ASYNC_MST_POSTWRITE_DIS_MASK                     0x1
+#define CBIP_ASYNC_MST_POSTWRITE_DIS_MASK_SFT                 (0x1 << 12)
+#define RESERVED_03_SFT                                       11
+#define RESERVED_03_MASK                                      0x1
+#define RESERVED_03_MASK_SFT                                  (0x1 << 11)
+#define CBIP_ASYNC_SLV_RG_FIFO_THRE_SFT                       9
+#define CBIP_ASYNC_SLV_RG_FIFO_THRE_MASK                      0x3
+#define CBIP_ASYNC_SLV_RG_FIFO_THRE_MASK_SFT                  (0x3 << 9)
+#define CBIP_ASYNC_SLV_POSTWRITE_DIS_SFT                      8
+#define CBIP_ASYNC_SLV_POSTWRITE_DIS_MASK                     0x1
+#define CBIP_ASYNC_SLV_POSTWRITE_DIS_MASK_SFT                 (0x1 << 8)
+#define AUDIOSYS_BUSY_SFT                                     7
+#define AUDIOSYS_BUSY_MASK                                    0x1
+#define AUDIOSYS_BUSY_MASK_SFT                                (0x1 << 7)
+#define CBIP_SLV_DECODER_ERR_FLAG_EN_SFT                      6
+#define CBIP_SLV_DECODER_ERR_FLAG_EN_MASK                     0x1
+#define CBIP_SLV_DECODER_ERR_FLAG_EN_MASK_SFT                 (0x1 << 6)
+#define CBIP_SLV_DECODER_SLAVE_WAY_EN_SFT                     5
+#define CBIP_SLV_DECODER_SLAVE_WAY_EN_MASK                    0x1
+#define CBIP_SLV_DECODER_SLAVE_WAY_EN_MASK_SFT                (0x1 << 5)
+#define APB_R2T_SFT                                           3
+#define APB_R2T_MASK                                          0x1
+#define APB_R2T_MASK_SFT                                      (0x1 << 3)
+#define APB_W2T_SFT                                           2
+#define APB_W2T_MASK                                          0x1
+#define APB_W2T_MASK_SFT                                      (0x1 << 2)
+#define AHB_IDLE_EN_INT_SFT                                   1
+#define AHB_IDLE_EN_INT_MASK                                  0x1
+#define AHB_IDLE_EN_INT_MASK_SFT                              (0x1 << 1)
+#define AHB_IDLE_EN_EXT_SFT                                   0
+#define AHB_IDLE_EN_EXT_MASK                                  0x1
+#define AHB_IDLE_EN_EXT_MASK_SFT                              (0x1 << 0)
+
+/* AFE_CBIP_SLV_DECODER_MON0 */
+#define CBIP_SLV_DECODER_ERR_DOMAIN_SFT                       4
+#define CBIP_SLV_DECODER_ERR_DOMAIN_MASK                      0x1
+#define CBIP_SLV_DECODER_ERR_DOMAIN_MASK_SFT                  (0x1 << 4)
+#define CBIP_SLV_DECODER_ERR_ID_SFT                           3
+#define CBIP_SLV_DECODER_ERR_ID_MASK                          0x1
+#define CBIP_SLV_DECODER_ERR_ID_MASK_SFT                      (0x1 << 3)
+#define CBIP_SLV_DECODER_ERR_RW_SFT                           2
+#define CBIP_SLV_DECODER_ERR_RW_MASK                          0x1
+#define CBIP_SLV_DECODER_ERR_RW_MASK_SFT                      (0x1 << 2)
+#define CBIP_SLV_DECODER_ERR_DECERR_SFT                       1
+#define CBIP_SLV_DECODER_ERR_DECERR_MASK                      0x1
+#define CBIP_SLV_DECODER_ERR_DECERR_MASK_SFT                  (0x1 << 1)
+#define CBIP_SLV_DECODER_CTRL_UPDATE_STATUS_SFT               0
+#define CBIP_SLV_DECODER_CTRL_UPDATE_STATUS_MASK              0x1
+#define CBIP_SLV_DECODER_CTRL_UPDATE_STATUS_MASK_SFT          (0x1 << 0)
+
+/* AFE_CBIP_SLV_DECODER_MON1 */
+#define CBIP_SLV_DECODER_ERR_ADDR_SFT                         0
+#define CBIP_SLV_DECODER_ERR_ADDR_MASK                        0xffffffff
+#define CBIP_SLV_DECODER_ERR_ADDR_MASK_SFT                    (0xffffffff << 0)
+
+/* AFE_CBIP_SLV_MUX_MON_CFG */
+#define CBIP_SLV_MUX_ERR_FLAG_EN_SFT                          3
+#define CBIP_SLV_MUX_ERR_FLAG_EN_MASK                         0x1
+#define CBIP_SLV_MUX_ERR_FLAG_EN_MASK_SFT                     (0x1 << 3)
+#define CBIP_SLV_MUX_REG_SLAVE_WAY_EN_SFT                     2
+#define CBIP_SLV_MUX_REG_SLAVE_WAY_EN_MASK                    0x1
+#define CBIP_SLV_MUX_REG_SLAVE_WAY_EN_MASK_SFT                (0x1 << 2)
+#define CBIP_SLV_MUX_REG_LAYER_WAY_EN_SFT                     0
+#define CBIP_SLV_MUX_REG_LAYER_WAY_EN_MASK                    0x3
+#define CBIP_SLV_MUX_REG_LAYER_WAY_EN_MASK_SFT                (0x3 << 0)
+
+/* AFE_CBIP_SLV_MUX_MON0 */
+#define CBIP_SLV_MUX_ERR_DOMAIN_SFT                           8
+#define CBIP_SLV_MUX_ERR_DOMAIN_MASK                          0x1
+#define CBIP_SLV_MUX_ERR_DOMAIN_MASK_SFT                      (0x1 << 8)
+#define CBIP_SLV_MUX_ERR_ID_SFT                               7
+#define CBIP_SLV_MUX_ERR_ID_MASK                              0x1
+#define CBIP_SLV_MUX_ERR_ID_MASK_SFT                          (0x1 << 7)
+#define CBIP_SLV_MUX_ERR_RD_SFT                               6
+#define CBIP_SLV_MUX_ERR_RD_MASK                              0x1
+#define CBIP_SLV_MUX_ERR_RD_MASK_SFT                          (0x1 << 6)
+#define CBIP_SLV_MUX_ERR_WR_SFT                               5
+#define CBIP_SLV_MUX_ERR_WR_MASK                              0x1
+#define CBIP_SLV_MUX_ERR_WR_MASK_SFT                          (0x1 << 5)
+#define CBIP_SLV_MUX_ERR_EN_SLV_SFT                           4
+#define CBIP_SLV_MUX_ERR_EN_SLV_MASK                          0x1
+#define CBIP_SLV_MUX_ERR_EN_SLV_MASK_SFT                      (0x1 << 4)
+#define CBIP_SLV_MUX_ERR_EN_MST_SFT                           2
+#define CBIP_SLV_MUX_ERR_EN_MST_MASK                          0x3
+#define CBIP_SLV_MUX_ERR_EN_MST_MASK_SFT                      (0x3 << 2)
+#define CBIP_SLV_MUX_CTRL_UPDATE_STATUS_SFT                   0
+#define CBIP_SLV_MUX_CTRL_UPDATE_STATUS_MASK                  0x3
+#define CBIP_SLV_MUX_CTRL_UPDATE_STATUS_MASK_SFT              (0x3 << 0)
+
+/* AFE_CBIP_SLV_MUX_MON1 */
+#define CBIP_SLV_MUX_ERR_ADDR_SFT                             0
+#define CBIP_SLV_MUX_ERR_ADDR_MASK                            0xffffffff
+#define CBIP_SLV_MUX_ERR_ADDR_MASK_SFT                        (0xffffffff << 0)
+
+/* AFE_MEMIF_CON0 */
+#define CPU_COMPACT_MODE_SFT                                  2
+#define CPU_COMPACT_MODE_MASK                                 0x1
+#define CPU_COMPACT_MODE_MASK_SFT                             (0x1 << 2)
+#define CPU_HD_ALIGN_SFT                                      1
+#define CPU_HD_ALIGN_MASK                                     0x1
+#define CPU_HD_ALIGN_MASK_SFT                                 (0x1 << 1)
+#define SYSRAM_SIGN_SFT                                       0
+#define SYSRAM_SIGN_MASK                                      0x1
+#define SYSRAM_SIGN_MASK_SFT                                  (0x1 << 0)
+
+/* AFE_MEMIF_ONE_HEART */
+#define DL_ONE_HEART_ON_2_SFT                                 2
+#define DL_ONE_HEART_ON_2_MASK                                0x1
+#define DL_ONE_HEART_ON_2_MASK_SFT                            (0x1 << 2)
+#define DL_ONE_HEART_ON_1_SFT                                 1
+#define DL_ONE_HEART_ON_1_MASK                                0x1
+#define DL_ONE_HEART_ON_1_MASK_SFT                            (0x1 << 1)
+#define DL_ONE_HEART_ON_0_SFT                                 0
+#define DL_ONE_HEART_ON_0_MASK                                0x1
+#define DL_ONE_HEART_ON_0_MASK_SFT                            (0x1 << 0)
+
+/* AFE_DL0_BASE_MSB */
+#define DL0_BASE_ADDR_MSB_SFT                                 0
+#define DL0_BASE_ADDR_MSB_MASK                                0x1ff
+#define DL0_BASE_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_DL0_BASE */
+#define DL0_BASE_ADDR_SFT                                     4
+#define DL0_BASE_ADDR_MASK                                    0xfffffff
+#define DL0_BASE_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_DL0_CUR_MSB */
+#define DL0_CUR_PTR_MSB_SFT                                   0
+#define DL0_CUR_PTR_MSB_MASK                                  0x1ff
+#define DL0_CUR_PTR_MSB_MASK_SFT                              (0x1ff << 0)
+
+/* AFE_DL0_CUR */
+#define DL0_CUR_PTR_SFT                                       0
+#define DL0_CUR_PTR_MASK                                      0xffffffff
+#define DL0_CUR_PTR_MASK_SFT                                  (0xffffffff << 0)
+
+/* AFE_DL0_END_MSB */
+#define DL0_END_ADDR_MSB_SFT                                  0
+#define DL0_END_ADDR_MSB_MASK                                 0x1ff
+#define DL0_END_ADDR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_DL0_END */
+#define DL0_END_ADDR_SFT                                      4
+#define DL0_END_ADDR_MASK                                     0xfffffff
+#define DL0_END_ADDR_MASK_SFT                                 (0xfffffff << 4)
+
+/* AFE_DL0_RCH_MON */
+#define DL0_RCH_DATA_SFT                                      0
+#define DL0_RCH_DATA_MASK                                     0xffffffff
+#define DL0_RCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL0_LCH_MON */
+#define DL0_LCH_DATA_SFT                                      0
+#define DL0_LCH_DATA_MASK                                     0xffffffff
+#define DL0_LCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL0_CON0 */
+#define DL0_ON_SFT                                            28
+#define DL0_ON_MASK                                           0x1
+#define DL0_ON_MASK_SFT                                       (0x1 << 28)
+#define DL0_ONE_HEART_SEL_SFT                                 22
+#define DL0_ONE_HEART_SEL_MASK                                0x3
+#define DL0_ONE_HEART_SEL_MASK_SFT                            (0x3 << 22)
+#define DL0_MINLEN_SFT                                        20
+#define DL0_MINLEN_MASK                                       0x3
+#define DL0_MINLEN_MASK_SFT                                   (0x3 << 20)
+#define DL0_MAXLEN_SFT                                        16
+#define DL0_MAXLEN_MASK                                       0x3
+#define DL0_MAXLEN_MASK_SFT                                   (0x3 << 16)
+#define DL0_SEL_DOMAIN_SFT                                    13
+#define DL0_SEL_DOMAIN_MASK                                   0x7
+#define DL0_SEL_DOMAIN_MASK_SFT                               (0x7 << 13)
+#define DL0_SEL_FS_SFT                                        8
+#define DL0_SEL_FS_MASK                                       0x1f
+#define DL0_SEL_FS_MASK_SFT                                   (0x1f << 8)
+#define DL0_SW_CLEAR_BUF_EMPTY_SFT                            7
+#define DL0_SW_CLEAR_BUF_EMPTY_MASK                           0x1
+#define DL0_SW_CLEAR_BUF_EMPTY_MASK_SFT                       (0x1 << 7)
+#define DL0_PBUF_SIZE_SFT                                     5
+#define DL0_PBUF_SIZE_MASK                                    0x3
+#define DL0_PBUF_SIZE_MASK_SFT                                (0x3 << 5)
+#define DL0_MONO_SFT                                          4
+#define DL0_MONO_MASK                                         0x1
+#define DL0_MONO_MASK_SFT                                     (0x1 << 4)
+#define DL0_NORMAL_MODE_SFT                                   3
+#define DL0_NORMAL_MODE_MASK                                  0x1
+#define DL0_NORMAL_MODE_MASK_SFT                              (0x1 << 3)
+#define DL0_HALIGN_SFT                                        2
+#define DL0_HALIGN_MASK                                       0x1
+#define DL0_HALIGN_MASK_SFT                                   (0x1 << 2)
+#define DL0_HD_MODE_SFT                                       0
+#define DL0_HD_MODE_MASK                                      0x3
+#define DL0_HD_MODE_MASK_SFT                                  (0x3 << 0)
+
+/* AFE_DL1_BASE_MSB */
+#define DL1_BASE_ADDR_MSB_SFT                                 0
+#define DL1_BASE_ADDR_MSB_MASK                                0x1ff
+#define DL1_BASE_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_DL1_BASE */
+#define DL1_BASE_ADDR_SFT                                     4
+#define DL1_BASE_ADDR_MASK                                    0xfffffff
+#define DL1_BASE_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_DL1_CUR_MSB */
+#define DL1_CUR_PTR_MSB_SFT                                   0
+#define DL1_CUR_PTR_MSB_MASK                                  0x1ff
+#define DL1_CUR_PTR_MSB_MASK_SFT                              (0x1ff << 0)
+
+/* AFE_DL1_CUR */
+#define DL1_CUR_PTR_SFT                                       0
+#define DL1_CUR_PTR_MASK                                      0xffffffff
+#define DL1_CUR_PTR_MASK_SFT                                  (0xffffffff << 0)
+
+/* AFE_DL1_END_MSB */
+#define DL1_END_ADDR_MSB_SFT                                  0
+#define DL1_END_ADDR_MSB_MASK                                 0x1ff
+#define DL1_END_ADDR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_DL1_END */
+#define DL1_END_ADDR_SFT                                      4
+#define DL1_END_ADDR_MASK                                     0xfffffff
+#define DL1_END_ADDR_MASK_SFT                                 (0xfffffff << 4)
+
+/* AFE_DL1_RCH_MON */
+#define DL1_RCH_DATA_SFT                                      0
+#define DL1_RCH_DATA_MASK                                     0xffffffff
+#define DL1_RCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL1_LCH_MON */
+#define DL1_LCH_DATA_SFT                                      0
+#define DL1_LCH_DATA_MASK                                     0xffffffff
+#define DL1_LCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL1_CON0 */
+#define DL1_ON_SFT                                            28
+#define DL1_ON_MASK                                           0x1
+#define DL1_ON_MASK_SFT                                       (0x1 << 28)
+#define DL1_ONE_HEART_SEL_SFT                                 22
+#define DL1_ONE_HEART_SEL_MASK                                0x3
+#define DL1_ONE_HEART_SEL_MASK_SFT                            (0x3 << 22)
+#define DL1_MINLEN_SFT                                        20
+#define DL1_MINLEN_MASK                                       0x3
+#define DL1_MINLEN_MASK_SFT                                   (0x3 << 20)
+#define DL1_MAXLEN_SFT                                        16
+#define DL1_MAXLEN_MASK                                       0x3
+#define DL1_MAXLEN_MASK_SFT                                   (0x3 << 16)
+#define DL1_SEL_DOMAIN_SFT                                    13
+#define DL1_SEL_DOMAIN_MASK                                   0x7
+#define DL1_SEL_DOMAIN_MASK_SFT                               (0x7 << 13)
+#define DL1_SEL_FS_SFT                                        8
+#define DL1_SEL_FS_MASK                                       0x1f
+#define DL1_SEL_FS_MASK_SFT                                   (0x1f << 8)
+#define DL1_SW_CLEAR_BUF_EMPTY_SFT                            7
+#define DL1_SW_CLEAR_BUF_EMPTY_MASK                           0x1
+#define DL1_SW_CLEAR_BUF_EMPTY_MASK_SFT                       (0x1 << 7)
+#define DL1_PBUF_SIZE_SFT                                     5
+#define DL1_PBUF_SIZE_MASK                                    0x3
+#define DL1_PBUF_SIZE_MASK_SFT                                (0x3 << 5)
+#define DL1_MONO_SFT                                          4
+#define DL1_MONO_MASK                                         0x1
+#define DL1_MONO_MASK_SFT                                     (0x1 << 4)
+#define DL1_NORMAL_MODE_SFT                                   3
+#define DL1_NORMAL_MODE_MASK                                  0x1
+#define DL1_NORMAL_MODE_MASK_SFT                              (0x1 << 3)
+#define DL1_HALIGN_SFT                                        2
+#define DL1_HALIGN_MASK                                       0x1
+#define DL1_HALIGN_MASK_SFT                                   (0x1 << 2)
+#define DL1_HD_MODE_SFT                                       0
+#define DL1_HD_MODE_MASK                                      0x3
+#define DL1_HD_MODE_MASK_SFT                                  (0x3 << 0)
+
+/* AFE_DL2_BASE_MSB */
+#define DL2_BASE__ADDR_MSB_SFT                                0
+#define DL2_BASE__ADDR_MSB_MASK                               0x1ff
+#define DL2_BASE__ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_DL2_BASE */
+#define DL2_BASE_ADDR_SFT                                     4
+#define DL2_BASE_ADDR_MASK                                    0xfffffff
+#define DL2_BASE_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_DL2_CUR_MSB */
+#define DL2_CUR_PTR_MSB_SFT                                   0
+#define DL2_CUR_PTR_MSB_MASK                                  0x1ff
+#define DL2_CUR_PTR_MSB_MASK_SFT                              (0x1ff << 0)
+
+/* AFE_DL2_CUR */
+#define DL2_CUR_PTR_SFT                                       0
+#define DL2_CUR_PTR_MASK                                      0xffffffff
+#define DL2_CUR_PTR_MASK_SFT                                  (0xffffffff << 0)
+
+/* AFE_DL2_END_MSB */
+#define DL2_END_ADDR_MSB_SFT                                  0
+#define DL2_END_ADDR_MSB_MASK                                 0x1ff
+#define DL2_END_ADDR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_DL2_END */
+#define DL2_END_ADDR_SFT                                      4
+#define DL2_END_ADDR_MASK                                     0xfffffff
+#define DL2_END_ADDR_MASK_SFT                                 (0xfffffff << 4)
+
+/* AFE_DL2_RCH_MON */
+#define DL2_RCH_DATA_SFT                                      0
+#define DL2_RCH_DATA_MASK                                     0xffffffff
+#define DL2_RCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL2_LCH_MON */
+#define DL2_LCH_DATA_SFT                                      0
+#define DL2_LCH_DATA_MASK                                     0xffffffff
+#define DL2_LCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL2_CON0 */
+#define DL2_ON_SFT                                            28
+#define DL2_ON_MASK                                           0x1
+#define DL2_ON_MASK_SFT                                       (0x1 << 28)
+#define DL2_ONE_HEART_SEL_SFT                                 22
+#define DL2_ONE_HEART_SEL_MASK                                0x3
+#define DL2_ONE_HEART_SEL_MASK_SFT                            (0x3 << 22)
+#define DL2_MINLEN_SFT                                        20
+#define DL2_MINLEN_MASK                                       0x3
+#define DL2_MINLEN_MASK_SFT                                   (0x3 << 20)
+#define DL2_MAXLEN_SFT                                        16
+#define DL2_MAXLEN_MASK                                       0x3
+#define DL2_MAXLEN_MASK_SFT                                   (0x3 << 16)
+#define DL2_SEL_DOMAIN_SFT                                    13
+#define DL2_SEL_DOMAIN_MASK                                   0x7
+#define DL2_SEL_DOMAIN_MASK_SFT                               (0x7 << 13)
+#define DL2_SEL_FS_SFT                                        8
+#define DL2_SEL_FS_MASK                                       0x1f
+#define DL2_SEL_FS_MASK_SFT                                   (0x1f << 8)
+#define DL2_SW_CLEAR_BUF_EMPTY_SFT                            7
+#define DL2_SW_CLEAR_BUF_EMPTY_MASK                           0x1
+#define DL2_SW_CLEAR_BUF_EMPTY_MASK_SFT                       (0x1 << 7)
+#define DL2_PBUF_SIZE_SFT                                     5
+#define DL2_PBUF_SIZE_MASK                                    0x3
+#define DL2_PBUF_SIZE_MASK_SFT                                (0x3 << 5)
+#define DL2_MONO_SFT                                          4
+#define DL2_MONO_MASK                                         0x1
+#define DL2_MONO_MASK_SFT                                     (0x1 << 4)
+#define DL2_NORMAL_MODE_SFT                                   3
+#define DL2_NORMAL_MODE_MASK                                  0x1
+#define DL2_NORMAL_MODE_MASK_SFT                              (0x1 << 3)
+#define DL2_HALIGN_SFT                                        2
+#define DL2_HALIGN_MASK                                       0x1
+#define DL2_HALIGN_MASK_SFT                                   (0x1 << 2)
+#define DL2_HD_MODE_SFT                                       0
+#define DL2_HD_MODE_MASK                                      0x3
+#define DL2_HD_MODE_MASK_SFT                                  (0x3 << 0)
+
+/* AFE_DL3_BASE_MSB */
+#define DL3_BASE__ADDR_MSB_SFT                                0
+#define DL3_BASE__ADDR_MSB_MASK                               0x1ff
+#define DL3_BASE__ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_DL3_BASE */
+#define DL3_BASE_ADDR_SFT                                     4
+#define DL3_BASE_ADDR_MASK                                    0xfffffff
+#define DL3_BASE_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_DL3_CUR_MSB */
+#define DL3_CUR_PTR_MSB_SFT                                   0
+#define DL3_CUR_PTR_MSB_MASK                                  0x1ff
+#define DL3_CUR_PTR_MSB_MASK_SFT                              (0x1ff << 0)
+
+/* AFE_DL3_CUR */
+#define DL3_CUR_PTR_SFT                                       0
+#define DL3_CUR_PTR_MASK                                      0xffffffff
+#define DL3_CUR_PTR_MASK_SFT                                  (0xffffffff << 0)
+
+/* AFE_DL3_END_MSB */
+#define DL3_END_ADDR_MSB_SFT                                  0
+#define DL3_END_ADDR_MSB_MASK                                 0x1ff
+#define DL3_END_ADDR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_DL3_END */
+#define DL3_END_ADDR_SFT                                      4
+#define DL3_END_ADDR_MASK                                     0xfffffff
+#define DL3_END_ADDR_MASK_SFT                                 (0xfffffff << 4)
+
+/* AFE_DL3_RCH_MON */
+#define DL3_RCH_DATA_SFT                                      0
+#define DL3_RCH_DATA_MASK                                     0xffffffff
+#define DL3_RCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL3_LCH_MON */
+#define DL3_LCH_DATA_SFT                                      0
+#define DL3_LCH_DATA_MASK                                     0xffffffff
+#define DL3_LCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL3_CON0 */
+#define DL3_ON_SFT                                            28
+#define DL3_ON_MASK                                           0x1
+#define DL3_ON_MASK_SFT                                       (0x1 << 28)
+#define DL3_ONE_HEART_SEL_SFT                                 22
+#define DL3_ONE_HEART_SEL_MASK                                0x3
+#define DL3_ONE_HEART_SEL_MASK_SFT                            (0x3 << 22)
+#define DL3_MINLEN_SFT                                        20
+#define DL3_MINLEN_MASK                                       0x3
+#define DL3_MINLEN_MASK_SFT                                   (0x3 << 20)
+#define DL3_MAXLEN_SFT                                        16
+#define DL3_MAXLEN_MASK                                       0x3
+#define DL3_MAXLEN_MASK_SFT                                   (0x3 << 16)
+#define DL3_SEL_DOMAIN_SFT                                    13
+#define DL3_SEL_DOMAIN_MASK                                   0x7
+#define DL3_SEL_DOMAIN_MASK_SFT                               (0x7 << 13)
+#define DL3_SEL_FS_SFT                                        8
+#define DL3_SEL_FS_MASK                                       0x1f
+#define DL3_SEL_FS_MASK_SFT                                   (0x1f << 8)
+#define DL3_SW_CLEAR_BUF_EMPTY_SFT                            7
+#define DL3_SW_CLEAR_BUF_EMPTY_MASK                           0x1
+#define DL3_SW_CLEAR_BUF_EMPTY_MASK_SFT                       (0x1 << 7)
+#define DL3_PBUF_SIZE_SFT                                     5
+#define DL3_PBUF_SIZE_MASK                                    0x3
+#define DL3_PBUF_SIZE_MASK_SFT                                (0x3 << 5)
+#define DL3_MONO_SFT                                          4
+#define DL3_MONO_MASK                                         0x1
+#define DL3_MONO_MASK_SFT                                     (0x1 << 4)
+#define DL3_NORMAL_MODE_SFT                                   3
+#define DL3_NORMAL_MODE_MASK                                  0x1
+#define DL3_NORMAL_MODE_MASK_SFT                              (0x1 << 3)
+#define DL3_HALIGN_SFT                                        2
+#define DL3_HALIGN_MASK                                       0x1
+#define DL3_HALIGN_MASK_SFT                                   (0x1 << 2)
+#define DL3_HD_MODE_SFT                                       0
+#define DL3_HD_MODE_MASK                                      0x3
+#define DL3_HD_MODE_MASK_SFT                                  (0x3 << 0)
+
+/* AFE_DL4_BASE_MSB */
+#define DL4_BASE__ADDR_MSB_SFT                                0
+#define DL4_BASE__ADDR_MSB_MASK                               0x1ff
+#define DL4_BASE__ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_DL4_BASE */
+#define DL4_BASE_ADDR_SFT                                     4
+#define DL4_BASE_ADDR_MASK                                    0xfffffff
+#define DL4_BASE_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_DL4_CUR_MSB */
+#define DL4_CUR_PTR_MSB_SFT                                   0
+#define DL4_CUR_PTR_MSB_MASK                                  0x1ff
+#define DL4_CUR_PTR_MSB_MASK_SFT                              (0x1ff << 0)
+
+/* AFE_DL4_CUR */
+#define DL4_CUR_PTR_SFT                                       0
+#define DL4_CUR_PTR_MASK                                      0xffffffff
+#define DL4_CUR_PTR_MASK_SFT                                  (0xffffffff << 0)
+
+/* AFE_DL4_END_MSB */
+#define DL4_END_ADDR_MSB_SFT                                  0
+#define DL4_END_ADDR_MSB_MASK                                 0x1ff
+#define DL4_END_ADDR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_DL4_END */
+#define DL4_END_ADDR_SFT                                      4
+#define DL4_END_ADDR_MASK                                     0xfffffff
+#define DL4_END_ADDR_MASK_SFT                                 (0xfffffff << 4)
+
+/* AFE_DL4_RCH_MON */
+#define DL4_RCH_DATA_SFT                                      0
+#define DL4_RCH_DATA_MASK                                     0xffffffff
+#define DL4_RCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL4_LCH_MON */
+#define DL4_LCH_DATA_SFT                                      0
+#define DL4_LCH_DATA_MASK                                     0xffffffff
+#define DL4_LCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL4_CON0 */
+#define DL4_ON_SFT                                            28
+#define DL4_ON_MASK                                           0x1
+#define DL4_ON_MASK_SFT                                       (0x1 << 28)
+#define DL4_ONE_HEART_SEL_SFT                                 22
+#define DL4_ONE_HEART_SEL_MASK                                0x3
+#define DL4_ONE_HEART_SEL_MASK_SFT                            (0x3 << 22)
+#define DL4_MINLEN_SFT                                        20
+#define DL4_MINLEN_MASK                                       0x3
+#define DL4_MINLEN_MASK_SFT                                   (0x3 << 20)
+#define DL4_MAXLEN_SFT                                        16
+#define DL4_MAXLEN_MASK                                       0x3
+#define DL4_MAXLEN_MASK_SFT                                   (0x3 << 16)
+#define DL4_SEL_DOMAIN_SFT                                    13
+#define DL4_SEL_DOMAIN_MASK                                   0x7
+#define DL4_SEL_DOMAIN_MASK_SFT                               (0x7 << 13)
+#define DL4_SEL_FS_SFT                                        8
+#define DL4_SEL_FS_MASK                                       0x1f
+#define DL4_SEL_FS_MASK_SFT                                   (0x1f << 8)
+#define DL4_SW_CLEAR_BUF_EMPTY_SFT                            7
+#define DL4_SW_CLEAR_BUF_EMPTY_MASK                           0x1
+#define DL4_SW_CLEAR_BUF_EMPTY_MASK_SFT                       (0x1 << 7)
+#define DL4_PBUF_SIZE_SFT                                     5
+#define DL4_PBUF_SIZE_MASK                                    0x3
+#define DL4_PBUF_SIZE_MASK_SFT                                (0x3 << 5)
+#define DL4_MONO_SFT                                          4
+#define DL4_MONO_MASK                                         0x1
+#define DL4_MONO_MASK_SFT                                     (0x1 << 4)
+#define DL4_NORMAL_MODE_SFT                                   3
+#define DL4_NORMAL_MODE_MASK                                  0x1
+#define DL4_NORMAL_MODE_MASK_SFT                              (0x1 << 3)
+#define DL4_HALIGN_SFT                                        2
+#define DL4_HALIGN_MASK                                       0x1
+#define DL4_HALIGN_MASK_SFT                                   (0x1 << 2)
+#define DL4_HD_MODE_SFT                                       0
+#define DL4_HD_MODE_MASK                                      0x3
+#define DL4_HD_MODE_MASK_SFT                                  (0x3 << 0)
+
+/* AFE_DL5_BASE_MSB */
+#define DL5_BASE__ADDR_MSB_SFT                                0
+#define DL5_BASE__ADDR_MSB_MASK                               0x1ff
+#define DL5_BASE__ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_DL5_BASE */
+#define DL5_BASE_ADDR_SFT                                     4
+#define DL5_BASE_ADDR_MASK                                    0xfffffff
+#define DL5_BASE_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_DL5_CUR_MSB */
+#define DL5_CUR_PTR_MSB_SFT                                   0
+#define DL5_CUR_PTR_MSB_MASK                                  0x1ff
+#define DL5_CUR_PTR_MSB_MASK_SFT                              (0x1ff << 0)
+
+/* AFE_DL5_CUR */
+#define DL5_CUR_PTR_SFT                                       0
+#define DL5_CUR_PTR_MASK                                      0xffffffff
+#define DL5_CUR_PTR_MASK_SFT                                  (0xffffffff << 0)
+
+/* AFE_DL5_END_MSB */
+#define DL5_END_ADDR_MSB_SFT                                  0
+#define DL5_END_ADDR_MSB_MASK                                 0x1ff
+#define DL5_END_ADDR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_DL5_END */
+#define DL5_END_ADDR_SFT                                      4
+#define DL5_END_ADDR_MASK                                     0xfffffff
+#define DL5_END_ADDR_MASK_SFT                                 (0xfffffff << 4)
+
+/* AFE_DL5_RCH_MON */
+#define DL5_RCH_DATA_SFT                                      0
+#define DL5_RCH_DATA_MASK                                     0xffffffff
+#define DL5_RCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL5_LCH_MON */
+#define DL5_LCH_DATA_SFT                                      0
+#define DL5_LCH_DATA_MASK                                     0xffffffff
+#define DL5_LCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL5_CON0 */
+#define DL5_ON_SFT                                            28
+#define DL5_ON_MASK                                           0x1
+#define DL5_ON_MASK_SFT                                       (0x1 << 28)
+#define DL5_ONE_HEART_SEL_SFT                                 22
+#define DL5_ONE_HEART_SEL_MASK                                0x3
+#define DL5_ONE_HEART_SEL_MASK_SFT                            (0x3 << 22)
+#define DL5_MINLEN_SFT                                        20
+#define DL5_MINLEN_MASK                                       0x3
+#define DL5_MINLEN_MASK_SFT                                   (0x3 << 20)
+#define DL5_MAXLEN_SFT                                        16
+#define DL5_MAXLEN_MASK                                       0x3
+#define DL5_MAXLEN_MASK_SFT                                   (0x3 << 16)
+#define DL5_SEL_DOMAIN_SFT                                    13
+#define DL5_SEL_DOMAIN_MASK                                   0x7
+#define DL5_SEL_DOMAIN_MASK_SFT                               (0x7 << 13)
+#define DL5_SEL_FS_SFT                                        8
+#define DL5_SEL_FS_MASK                                       0x1f
+#define DL5_SEL_FS_MASK_SFT                                   (0x1f << 8)
+#define DL5_SW_CLEAR_BUF_EMPTY_SFT                            7
+#define DL5_SW_CLEAR_BUF_EMPTY_MASK                           0x1
+#define DL5_SW_CLEAR_BUF_EMPTY_MASK_SFT                       (0x1 << 7)
+#define DL5_PBUF_SIZE_SFT                                     5
+#define DL5_PBUF_SIZE_MASK                                    0x3
+#define DL5_PBUF_SIZE_MASK_SFT                                (0x3 << 5)
+#define DL5_MONO_SFT                                          4
+#define DL5_MONO_MASK                                         0x1
+#define DL5_MONO_MASK_SFT                                     (0x1 << 4)
+#define DL5_NORMAL_MODE_SFT                                   3
+#define DL5_NORMAL_MODE_MASK                                  0x1
+#define DL5_NORMAL_MODE_MASK_SFT                              (0x1 << 3)
+#define DL5_HALIGN_SFT                                        2
+#define DL5_HALIGN_MASK                                       0x1
+#define DL5_HALIGN_MASK_SFT                                   (0x1 << 2)
+#define DL5_HD_MODE_SFT                                       0
+#define DL5_HD_MODE_MASK                                      0x3
+#define DL5_HD_MODE_MASK_SFT                                  (0x3 << 0)
+
+/* AFE_DL6_BASE_MSB */
+#define DL6_BASE__ADDR_MSB_SFT                                0
+#define DL6_BASE__ADDR_MSB_MASK                               0x1ff
+#define DL6_BASE__ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_DL6_BASE */
+#define DL6_BASE_ADDR_SFT                                     4
+#define DL6_BASE_ADDR_MASK                                    0xfffffff
+#define DL6_BASE_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_DL6_CUR_MSB */
+#define DL6_CUR_PTR_MSB_SFT                                   0
+#define DL6_CUR_PTR_MSB_MASK                                  0x1ff
+#define DL6_CUR_PTR_MSB_MASK_SFT                              (0x1ff << 0)
+
+/* AFE_DL6_CUR */
+#define DL6_CUR_PTR_SFT                                       0
+#define DL6_CUR_PTR_MASK                                      0xffffffff
+#define DL6_CUR_PTR_MASK_SFT                                  (0xffffffff << 0)
+
+/* AFE_DL6_END_MSB */
+#define DL6_END_ADDR_MSB_SFT                                  0
+#define DL6_END_ADDR_MSB_MASK                                 0x1ff
+#define DL6_END_ADDR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_DL6_END */
+#define DL6_END_ADDR_SFT                                      4
+#define DL6_END_ADDR_MASK                                     0xfffffff
+#define DL6_END_ADDR_MASK_SFT                                 (0xfffffff << 4)
+
+/* AFE_DL6_RCH_MON */
+#define DL6_RCH_DATA_SFT                                      0
+#define DL6_RCH_DATA_MASK                                     0xffffffff
+#define DL6_RCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL6_LCH_MON */
+#define DL6_LCH_DATA_SFT                                      0
+#define DL6_LCH_DATA_MASK                                     0xffffffff
+#define DL6_LCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL6_CON0 */
+#define DL6_ON_SFT                                            28
+#define DL6_ON_MASK                                           0x1
+#define DL6_ON_MASK_SFT                                       (0x1 << 28)
+#define DL6_ONE_HEART_SEL_SFT                                 22
+#define DL6_ONE_HEART_SEL_MASK                                0x3
+#define DL6_ONE_HEART_SEL_MASK_SFT                            (0x3 << 22)
+#define DL6_MINLEN_SFT                                        20
+#define DL6_MINLEN_MASK                                       0x3
+#define DL6_MINLEN_MASK_SFT                                   (0x3 << 20)
+#define DL6_MAXLEN_SFT                                        16
+#define DL6_MAXLEN_MASK                                       0x3
+#define DL6_MAXLEN_MASK_SFT                                   (0x3 << 16)
+#define DL6_SEL_DOMAIN_SFT                                    13
+#define DL6_SEL_DOMAIN_MASK                                   0x7
+#define DL6_SEL_DOMAIN_MASK_SFT                               (0x7 << 13)
+#define DL6_SEL_FS_SFT                                        8
+#define DL6_SEL_FS_MASK                                       0x1f
+#define DL6_SEL_FS_MASK_SFT                                   (0x1f << 8)
+#define DL6_SW_CLEAR_BUF_EMPTY_SFT                            7
+#define DL6_SW_CLEAR_BUF_EMPTY_MASK                           0x1
+#define DL6_SW_CLEAR_BUF_EMPTY_MASK_SFT                       (0x1 << 7)
+#define DL6_PBUF_SIZE_SFT                                     5
+#define DL6_PBUF_SIZE_MASK                                    0x3
+#define DL6_PBUF_SIZE_MASK_SFT                                (0x3 << 5)
+#define DL6_MONO_SFT                                          4
+#define DL6_MONO_MASK                                         0x1
+#define DL6_MONO_MASK_SFT                                     (0x1 << 4)
+#define DL6_NORMAL_MODE_SFT                                   3
+#define DL6_NORMAL_MODE_MASK                                  0x1
+#define DL6_NORMAL_MODE_MASK_SFT                              (0x1 << 3)
+#define DL6_HALIGN_SFT                                        2
+#define DL6_HALIGN_MASK                                       0x1
+#define DL6_HALIGN_MASK_SFT                                   (0x1 << 2)
+#define DL6_HD_MODE_SFT                                       0
+#define DL6_HD_MODE_MASK                                      0x3
+#define DL6_HD_MODE_MASK_SFT                                  (0x3 << 0)
+
+/* AFE_DL7_BASE_MSB */
+#define DL7_BASE__ADDR_MSB_SFT                                0
+#define DL7_BASE__ADDR_MSB_MASK                               0x1ff
+#define DL7_BASE__ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_DL7_BASE */
+#define DL7_BASE_ADDR_SFT                                     4
+#define DL7_BASE_ADDR_MASK                                    0xfffffff
+#define DL7_BASE_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_DL7_CUR_MSB */
+#define DL7_CUR_PTR_MSB_SFT                                   0
+#define DL7_CUR_PTR_MSB_MASK                                  0x1ff
+#define DL7_CUR_PTR_MSB_MASK_SFT                              (0x1ff << 0)
+
+/* AFE_DL7_CUR */
+#define DL7_CUR_PTR_SFT                                       0
+#define DL7_CUR_PTR_MASK                                      0xffffffff
+#define DL7_CUR_PTR_MASK_SFT                                  (0xffffffff << 0)
+
+/* AFE_DL7_END_MSB */
+#define DL7_END_ADDR_MSB_SFT                                  0
+#define DL7_END_ADDR_MSB_MASK                                 0x1ff
+#define DL7_END_ADDR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_DL7_END */
+#define DL7_END_ADDR_SFT                                      4
+#define DL7_END_ADDR_MASK                                     0xfffffff
+#define DL7_END_ADDR_MASK_SFT                                 (0xfffffff << 4)
+
+/* AFE_DL7_RCH_MON */
+#define DL7_RCH_DATA_SFT                                      0
+#define DL7_RCH_DATA_MASK                                     0xffffffff
+#define DL7_RCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL7_LCH_MON */
+#define DL7_LCH_DATA_SFT                                      0
+#define DL7_LCH_DATA_MASK                                     0xffffffff
+#define DL7_LCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL7_CON0 */
+#define DL7_ON_SFT                                            28
+#define DL7_ON_MASK                                           0x1
+#define DL7_ON_MASK_SFT                                       (0x1 << 28)
+#define DL7_ONE_HEART_SEL_SFT                                 22
+#define DL7_ONE_HEART_SEL_MASK                                0x3
+#define DL7_ONE_HEART_SEL_MASK_SFT                            (0x3 << 22)
+#define DL7_MINLEN_SFT                                        20
+#define DL7_MINLEN_MASK                                       0x3
+#define DL7_MINLEN_MASK_SFT                                   (0x3 << 20)
+#define DL7_MAXLEN_SFT                                        16
+#define DL7_MAXLEN_MASK                                       0x3
+#define DL7_MAXLEN_MASK_SFT                                   (0x3 << 16)
+#define DL7_SEL_DOMAIN_SFT                                    13
+#define DL7_SEL_DOMAIN_MASK                                   0x7
+#define DL7_SEL_DOMAIN_MASK_SFT                               (0x7 << 13)
+#define DL7_SEL_FS_SFT                                        8
+#define DL7_SEL_FS_MASK                                       0x1f
+#define DL7_SEL_FS_MASK_SFT                                   (0x1f << 8)
+#define DL7_SW_CLEAR_BUF_EMPTY_SFT                            7
+#define DL7_SW_CLEAR_BUF_EMPTY_MASK                           0x1
+#define DL7_SW_CLEAR_BUF_EMPTY_MASK_SFT                       (0x1 << 7)
+#define DL7_PBUF_SIZE_SFT                                     5
+#define DL7_PBUF_SIZE_MASK                                    0x3
+#define DL7_PBUF_SIZE_MASK_SFT                                (0x3 << 5)
+#define DL7_MONO_SFT                                          4
+#define DL7_MONO_MASK                                         0x1
+#define DL7_MONO_MASK_SFT                                     (0x1 << 4)
+#define DL7_NORMAL_MODE_SFT                                   3
+#define DL7_NORMAL_MODE_MASK                                  0x1
+#define DL7_NORMAL_MODE_MASK_SFT                              (0x1 << 3)
+#define DL7_HALIGN_SFT                                        2
+#define DL7_HALIGN_MASK                                       0x1
+#define DL7_HALIGN_MASK_SFT                                   (0x1 << 2)
+#define DL7_HD_MODE_SFT                                       0
+#define DL7_HD_MODE_MASK                                      0x3
+#define DL7_HD_MODE_MASK_SFT                                  (0x3 << 0)
+
+/* AFE_DL8_BASE_MSB */
+#define DL8_BASE__ADDR_MSB_SFT                                0
+#define DL8_BASE__ADDR_MSB_MASK                               0x1ff
+#define DL8_BASE__ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_DL8_BASE */
+#define DL8_BASE_ADDR_SFT                                     4
+#define DL8_BASE_ADDR_MASK                                    0xfffffff
+#define DL8_BASE_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_DL8_CUR_MSB */
+#define DL8_CUR_PTR_MSB_SFT                                   0
+#define DL8_CUR_PTR_MSB_MASK                                  0x1ff
+#define DL8_CUR_PTR_MSB_MASK_SFT                              (0x1ff << 0)
+
+/* AFE_DL8_CUR */
+#define DL8_CUR_PTR_SFT                                       0
+#define DL8_CUR_PTR_MASK                                      0xffffffff
+#define DL8_CUR_PTR_MASK_SFT                                  (0xffffffff << 0)
+
+/* AFE_DL8_END_MSB */
+#define DL8_END_ADDR_MSB_SFT                                  0
+#define DL8_END_ADDR_MSB_MASK                                 0x1ff
+#define DL8_END_ADDR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_DL8_END */
+#define DL8_END_ADDR_SFT                                      4
+#define DL8_END_ADDR_MASK                                     0xfffffff
+#define DL8_END_ADDR_MASK_SFT                                 (0xfffffff << 4)
+
+/* AFE_DL8_RCH_MON */
+#define DL8_RCH_DATA_SFT                                      0
+#define DL8_RCH_DATA_MASK                                     0xffffffff
+#define DL8_RCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL8_LCH_MON */
+#define DL8_LCH_DATA_SFT                                      0
+#define DL8_LCH_DATA_MASK                                     0xffffffff
+#define DL8_LCH_DATA_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL8_CON0 */
+#define DL8_ON_SFT                                            28
+#define DL8_ON_MASK                                           0x1
+#define DL8_ON_MASK_SFT                                       (0x1 << 28)
+#define DL8_ONE_HEART_SEL_SFT                                 22
+#define DL8_ONE_HEART_SEL_MASK                                0x3
+#define DL8_ONE_HEART_SEL_MASK_SFT                            (0x3 << 22)
+#define DL8_MINLEN_SFT                                        20
+#define DL8_MINLEN_MASK                                       0x3
+#define DL8_MINLEN_MASK_SFT                                   (0x3 << 20)
+#define DL8_MAXLEN_SFT                                        16
+#define DL8_MAXLEN_MASK                                       0x3
+#define DL8_MAXLEN_MASK_SFT                                   (0x3 << 16)
+#define DL8_SEL_DOMAIN_SFT                                    13
+#define DL8_SEL_DOMAIN_MASK                                   0x7
+#define DL8_SEL_DOMAIN_MASK_SFT                               (0x7 << 13)
+#define DL8_SEL_FS_SFT                                        8
+#define DL8_SEL_FS_MASK                                       0x1f
+#define DL8_SEL_FS_MASK_SFT                                   (0x1f << 8)
+#define DL8_SW_CLEAR_BUF_EMPTY_SFT                            7
+#define DL8_SW_CLEAR_BUF_EMPTY_MASK                           0x1
+#define DL8_SW_CLEAR_BUF_EMPTY_MASK_SFT                       (0x1 << 7)
+#define DL8_PBUF_SIZE_SFT                                     5
+#define DL8_PBUF_SIZE_MASK                                    0x3
+#define DL8_PBUF_SIZE_MASK_SFT                                (0x3 << 5)
+#define DL8_MONO_SFT                                          4
+#define DL8_MONO_MASK                                         0x1
+#define DL8_MONO_MASK_SFT                                     (0x1 << 4)
+#define DL8_NORMAL_MODE_SFT                                   3
+#define DL8_NORMAL_MODE_MASK                                  0x1
+#define DL8_NORMAL_MODE_MASK_SFT                              (0x1 << 3)
+#define DL8_HALIGN_SFT                                        2
+#define DL8_HALIGN_MASK                                       0x1
+#define DL8_HALIGN_MASK_SFT                                   (0x1 << 2)
+#define DL8_HD_MODE_SFT                                       0
+#define DL8_HD_MODE_MASK                                      0x3
+#define DL8_HD_MODE_MASK_SFT                                  (0x3 << 0)
+
+/* AFE_DL_4CH_BASE_MSB */
+#define DL_4CH_BASE__ADDR_MSB_SFT                             0
+#define DL_4CH_BASE__ADDR_MSB_MASK                            0x1ff
+#define DL_4CH_BASE__ADDR_MSB_MASK_SFT                        (0x1ff << 0)
+
+/* AFE_DL_4CH_BASE */
+#define DL_4CH_BASE_ADDR_SFT                                  4
+#define DL_4CH_BASE_ADDR_MASK                                 0xfffffff
+#define DL_4CH_BASE_ADDR_MASK_SFT                             (0xfffffff << 4)
+
+/* AFE_DL_4CH_CUR_MSB */
+#define DL_4CH_CUR_PTR_MSB_SFT                                0
+#define DL_4CH_CUR_PTR_MSB_MASK                               0x1ff
+#define DL_4CH_CUR_PTR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_DL_4CH_CUR */
+#define DL_4CH_CUR_PTR_SFT                                    0
+#define DL_4CH_CUR_PTR_MASK                                   0xffffffff
+#define DL_4CH_CUR_PTR_MASK_SFT                               (0xffffffff << 0)
+
+/* AFE_DL_4CH_END_MSB */
+#define DL_4CH_END_ADDR_MSB_SFT                               0
+#define DL_4CH_END_ADDR_MSB_MASK                              0x1ff
+#define DL_4CH_END_ADDR_MSB_MASK_SFT                          (0x1ff << 0)
+
+/* AFE_DL_4CH_END */
+#define DL_4CH_END_ADDR_SFT                                   4
+#define DL_4CH_END_ADDR_MASK                                  0xfffffff
+#define DL_4CH_END_ADDR_MASK_SFT                              (0xfffffff << 4)
+
+/* AFE_DL_4CH_CON0 */
+#define DL_4CH_ON_SFT                                         31
+#define DL_4CH_ON_MASK                                        0x1
+#define DL_4CH_ON_MASK_SFT                                    (0x1 << 31)
+#define DL_4CH_NUM_SFT                                        24
+#define DL_4CH_NUM_MASK                                       0x1f
+#define DL_4CH_NUM_MASK_SFT                                   (0x1f << 24)
+#define DL_4CH_ONE_HEART_SEL_SFT                              22
+#define DL_4CH_ONE_HEART_SEL_MASK                             0x3
+#define DL_4CH_ONE_HEART_SEL_MASK_SFT                         (0x3 << 22)
+#define DL_4CH_MINLEN_SFT                                     20
+#define DL_4CH_MINLEN_MASK                                    0x3
+#define DL_4CH_MINLEN_MASK_SFT                                (0x3 << 20)
+#define DL_4CH_MAXLEN_SFT                                     16
+#define DL_4CH_MAXLEN_MASK                                    0x3
+#define DL_4CH_MAXLEN_MASK_SFT                                (0x3 << 16)
+#define DL_4CH_SEL_DOMAIN_SFT                                 13
+#define DL_4CH_SEL_DOMAIN_MASK                                0x7
+#define DL_4CH_SEL_DOMAIN_MASK_SFT                            (0x7 << 13)
+#define DL_4CH_SEL_FS_SFT                                     8
+#define DL_4CH_SEL_FS_MASK                                    0x1f
+#define DL_4CH_SEL_FS_MASK_SFT                                (0x1f << 8)
+#define DL_4CH_BUF_EMPTY_CLR_SFT                              7
+#define DL_4CH_BUF_EMPTY_CLR_MASK                             0x1
+#define DL_4CH_BUF_EMPTY_CLR_MASK_SFT                         (0x1 << 7)
+#define DL_4CH_PBUF_SIZE_SFT                                  5
+#define DL_4CH_PBUF_SIZE_MASK                                 0x3
+#define DL_4CH_PBUF_SIZE_MASK_SFT                             (0x3 << 5)
+#define DL_4CH_HANG_CLR_SFT                                   4
+#define DL_4CH_HANG_CLR_MASK                                  0x1
+#define DL_4CH_HANG_CLR_MASK_SFT                              (0x1 << 4)
+#define DL_4CH_NORMAL_MODE_SFT                                3
+#define DL_4CH_NORMAL_MODE_MASK                               0x1
+#define DL_4CH_NORMAL_MODE_MASK_SFT                           (0x1 << 3)
+#define DL_4CH_HALIGN_SFT                                     2
+#define DL_4CH_HALIGN_MASK                                    0x1
+#define DL_4CH_HALIGN_MASK_SFT                                (0x1 << 2)
+#define DL_4CH_HD_MODE_SFT                                    0
+#define DL_4CH_HD_MODE_MASK                                   0x3
+#define DL_4CH_HD_MODE_MASK_SFT                               (0x3 << 0)
+
+/* AFE_DL_24CH_BASE_MSB */
+#define DL_24CH_BASE__ADDR_MSB_SFT                            0
+#define DL_24CH_BASE__ADDR_MSB_MASK                           0x1ff
+#define DL_24CH_BASE__ADDR_MSB_MASK_SFT                       (0x1ff << 0)
+
+/* AFE_DL_24CH_BASE */
+#define DL_24CH_BASE_ADDR_SFT                                 4
+#define DL_24CH_BASE_ADDR_MASK                                0xfffffff
+#define DL_24CH_BASE_ADDR_MASK_SFT                            (0xfffffff << 4)
+
+/* AFE_DL_24CH_CUR_MSB */
+#define DL_24CH_CUR_PTR_MSB_SFT                               0
+#define DL_24CH_CUR_PTR_MSB_MASK                              0x1ff
+#define DL_24CH_CUR_PTR_MSB_MASK_SFT                          (0x1ff << 0)
+
+/* AFE_DL_24CH_CUR */
+#define DL_24CH_CUR_PTR_SFT                                   0
+#define DL_24CH_CUR_PTR_MASK                                  0xffffffff
+#define DL_24CH_CUR_PTR_MASK_SFT                              (0xffffffff << 0)
+
+/* AFE_DL_24CH_END_MSB */
+#define DL_24CH_END_ADDR_MSB_SFT                              0
+#define DL_24CH_END_ADDR_MSB_MASK                             0x1ff
+#define DL_24CH_END_ADDR_MSB_MASK_SFT                         (0x1ff << 0)
+
+/* AFE_DL_24CH_END */
+#define DL_24CH_END_ADDR_SFT                                  4
+#define DL_24CH_END_ADDR_MASK                                 0xfffffff
+#define DL_24CH_END_ADDR_MASK_SFT                             (0xfffffff << 4)
+
+/* AFE_DL_24CH_CON0 */
+#define DL_24CH_ON_SFT                                        31
+#define DL_24CH_ON_MASK                                       0x1
+#define DL_24CH_ON_MASK_SFT                                   (0x1 << 31)
+#define DL_24CH_NUM_SFT                                       24
+#define DL_24CH_NUM_MASK                                      0x3f
+#define DL_24CH_NUM_MASK_SFT                                  (0x3f << 24)
+#define DL_24CH_ONE_HEART_SEL_SFT                             22
+#define DL_24CH_ONE_HEART_SEL_MASK                            0x3
+#define DL_24CH_ONE_HEART_SEL_MASK_SFT                        (0x3 << 22)
+#define DL_24CH_MINLEN_SFT                                    20
+#define DL_24CH_MINLEN_MASK                                   0x3
+#define DL_24CH_MINLEN_MASK_SFT                               (0x3 << 20)
+#define DL_24CH_MAXLEN_SFT                                    16
+#define DL_24CH_MAXLEN_MASK                                   0x3
+#define DL_24CH_MAXLEN_MASK_SFT                               (0x3 << 16)
+#define DL_24CH_SEL_DOMAIN_SFT                                13
+#define DL_24CH_SEL_DOMAIN_MASK                               0x7
+#define DL_24CH_SEL_DOMAIN_MASK_SFT                           (0x7 << 13)
+#define DL_24CH_SEL_FS_SFT                                    8
+#define DL_24CH_SEL_FS_MASK                                   0x1f
+#define DL_24CH_SEL_FS_MASK_SFT                               (0x1f << 8)
+#define DL_24CH_BUF_EMPTY_CLR_SFT                             7
+#define DL_24CH_BUF_EMPTY_CLR_MASK                            0x1
+#define DL_24CH_BUF_EMPTY_CLR_MASK_SFT                        (0x1 << 7)
+#define DL_24CH_PBUF_SIZE_SFT                                 5
+#define DL_24CH_PBUF_SIZE_MASK                                0x3
+#define DL_24CH_PBUF_SIZE_MASK_SFT                            (0x3 << 5)
+#define DL_24CH_HANG_CLR_SFT                                  4
+#define DL_24CH_HANG_CLR_MASK                                 0x1
+#define DL_24CH_HANG_CLR_MASK_SFT                             (0x1 << 4)
+#define DL_24CH_NORMAL_MODE_SFT                               3
+#define DL_24CH_NORMAL_MODE_MASK                              0x1
+#define DL_24CH_NORMAL_MODE_MASK_SFT                          (0x1 << 3)
+#define DL_24CH_HALIGN_SFT                                    2
+#define DL_24CH_HALIGN_MASK                                   0x1
+#define DL_24CH_HALIGN_MASK_SFT                               (0x1 << 2)
+#define DL_24CH_HD_MODE_SFT                                   0
+#define DL_24CH_HD_MODE_MASK                                  0x3
+#define DL_24CH_HD_MODE_MASK_SFT                              (0x3 << 0)
+
+/* AFE_DL23_BASE_MSB */
+#define DL23_BASE__ADDR_MSB_SFT                               0
+#define DL23_BASE__ADDR_MSB_MASK                              0x1ff
+#define DL23_BASE__ADDR_MSB_MASK_SFT                          (0x1ff << 0)
+
+/* AFE_DL23_BASE */
+#define DL23_BASE_ADDR_SFT                                    4
+#define DL23_BASE_ADDR_MASK                                   0xfffffff
+#define DL23_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_DL23_CUR_MSB */
+#define DL23_CUR_PTR_MSB_SFT                                  0
+#define DL23_CUR_PTR_MSB_MASK                                 0x1ff
+#define DL23_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_DL23_CUR */
+#define DL23_CUR_PTR_SFT                                      0
+#define DL23_CUR_PTR_MASK                                     0xffffffff
+#define DL23_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL23_END_MSB */
+#define DL23_END_ADDR_MSB_SFT                                 0
+#define DL23_END_ADDR_MSB_MASK                                0x1ff
+#define DL23_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_DL23_END */
+#define DL23_END_ADDR_SFT                                     4
+#define DL23_END_ADDR_MASK                                    0xfffffff
+#define DL23_END_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_DL23_RCH_MON */
+#define DL23_RCH_DATA_SFT                                     0
+#define DL23_RCH_DATA_MASK                                    0xffffffff
+#define DL23_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_DL23_LCH_MON */
+#define DL23_LCH_DATA_SFT                                     0
+#define DL23_LCH_DATA_MASK                                    0xffffffff
+#define DL23_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_DL23_CON0 */
+#define DL23_ON_SFT                                           28
+#define DL23_ON_MASK                                          0x1
+#define DL23_ON_MASK_SFT                                      (0x1 << 28)
+#define DL23_ONE_HEART_SEL_SFT                                22
+#define DL23_ONE_HEART_SEL_MASK                               0x3
+#define DL23_ONE_HEART_SEL_MASK_SFT                           (0x3 << 22)
+#define DL23_MINLEN_SFT                                       20
+#define DL23_MINLEN_MASK                                      0x3
+#define DL23_MINLEN_MASK_SFT                                  (0x3 << 20)
+#define DL23_MAXLEN_SFT                                       16
+#define DL23_MAXLEN_MASK                                      0x3
+#define DL23_MAXLEN_MASK_SFT                                  (0x3 << 16)
+#define DL23_SEL_DOMAIN_SFT                                   13
+#define DL23_SEL_DOMAIN_MASK                                  0x7
+#define DL23_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
+#define DL23_SEL_FS_SFT                                       8
+#define DL23_SEL_FS_MASK                                      0x1f
+#define DL23_SEL_FS_MASK_SFT                                  (0x1f << 8)
+#define DL23_SW_CLEAR_BUF_EMPTY_SFT                           7
+#define DL23_SW_CLEAR_BUF_EMPTY_MASK                          0x1
+#define DL23_SW_CLEAR_BUF_EMPTY_MASK_SFT                      (0x1 << 7)
+#define DL23_PBUF_SIZE_SFT                                    5
+#define DL23_PBUF_SIZE_MASK                                   0x3
+#define DL23_PBUF_SIZE_MASK_SFT                               (0x3 << 5)
+#define DL23_MONO_SFT                                         4
+#define DL23_MONO_MASK                                        0x1
+#define DL23_MONO_MASK_SFT                                    (0x1 << 4)
+#define DL23_NORMAL_MODE_SFT                                  3
+#define DL23_NORMAL_MODE_MASK                                 0x1
+#define DL23_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
+#define DL23_HALIGN_SFT                                       2
+#define DL23_HALIGN_MASK                                      0x1
+#define DL23_HALIGN_MASK_SFT                                  (0x1 << 2)
+#define DL23_HD_MODE_SFT                                      0
+#define DL23_HD_MODE_MASK                                     0x3
+#define DL23_HD_MODE_MASK_SFT                                 (0x3 << 0)
+
+/* AFE_DL24_BASE_MSB */
+#define DL24_BASE__ADDR_MSB_SFT                               0
+#define DL24_BASE__ADDR_MSB_MASK                              0x1ff
+#define DL24_BASE__ADDR_MSB_MASK_SFT                          (0x1ff << 0)
+
+/* AFE_DL24_BASE */
+#define DL24_BASE_ADDR_SFT                                    4
+#define DL24_BASE_ADDR_MASK                                   0xfffffff
+#define DL24_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_DL24_CUR_MSB */
+#define DL24_CUR_PTR_MSB_SFT                                  0
+#define DL24_CUR_PTR_MSB_MASK                                 0x1ff
+#define DL24_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_DL24_CUR */
+#define DL24_CUR_PTR_SFT                                      0
+#define DL24_CUR_PTR_MASK                                     0xffffffff
+#define DL24_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL24_END_MSB */
+#define DL24_END_ADDR_MSB_SFT                                 0
+#define DL24_END_ADDR_MSB_MASK                                0x1ff
+#define DL24_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_DL24_END */
+#define DL24_END_ADDR_SFT                                     4
+#define DL24_END_ADDR_MASK                                    0xfffffff
+#define DL24_END_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_DL24_RCH_MON */
+#define DL24_RCH_DATA_SFT                                     0
+#define DL24_RCH_DATA_MASK                                    0xffffffff
+#define DL24_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_DL24_LCH_MON */
+#define DL24_LCH_DATA_SFT                                     0
+#define DL24_LCH_DATA_MASK                                    0xffffffff
+#define DL24_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_DL24_CON0 */
+#define DL24_ON_SFT                                           28
+#define DL24_ON_MASK                                          0x1
+#define DL24_ON_MASK_SFT                                      (0x1 << 28)
+#define DL24_ONE_HEART_SEL_SFT                                22
+#define DL24_ONE_HEART_SEL_MASK                               0x3
+#define DL24_ONE_HEART_SEL_MASK_SFT                           (0x3 << 22)
+#define DL24_MINLEN_SFT                                       20
+#define DL24_MINLEN_MASK                                      0x3
+#define DL24_MINLEN_MASK_SFT                                  (0x3 << 20)
+#define DL24_MAXLEN_SFT                                       16
+#define DL24_MAXLEN_MASK                                      0x3
+#define DL24_MAXLEN_MASK_SFT                                  (0x3 << 16)
+#define DL24_SEL_DOMAIN_SFT                                   13
+#define DL24_SEL_DOMAIN_MASK                                  0x7
+#define DL24_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
+#define DL24_SEL_FS_SFT                                       8
+#define DL24_SEL_FS_MASK                                      0x1f
+#define DL24_SEL_FS_MASK_SFT                                  (0x1f << 8)
+#define DL24_SW_CLEAR_BUF_EMPTY_SFT                           7
+#define DL24_SW_CLEAR_BUF_EMPTY_MASK                          0x1
+#define DL24_SW_CLEAR_BUF_EMPTY_MASK_SFT                      (0x1 << 7)
+#define DL24_PBUF_SIZE_SFT                                    5
+#define DL24_PBUF_SIZE_MASK                                   0x3
+#define DL24_PBUF_SIZE_MASK_SFT                               (0x3 << 5)
+#define DL24_MONO_SFT                                         4
+#define DL24_MONO_MASK                                        0x1
+#define DL24_MONO_MASK_SFT                                    (0x1 << 4)
+#define DL24_NORMAL_MODE_SFT                                  3
+#define DL24_NORMAL_MODE_MASK                                 0x1
+#define DL24_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
+#define DL24_HALIGN_SFT                                       2
+#define DL24_HALIGN_MASK                                      0x1
+#define DL24_HALIGN_MASK_SFT                                  (0x1 << 2)
+#define DL24_HD_MODE_SFT                                      0
+#define DL24_HD_MODE_MASK                                     0x3
+#define DL24_HD_MODE_MASK_SFT                                 (0x3 << 0)
+
+/* AFE_DL25_BASE_MSB */
+#define DL25_BASE__ADDR_MSB_SFT                               0
+#define DL25_BASE__ADDR_MSB_MASK                              0x1ff
+#define DL25_BASE__ADDR_MSB_MASK_SFT                          (0x1ff << 0)
+
+/* AFE_DL25_BASE */
+#define DL25_BASE_ADDR_SFT                                    4
+#define DL25_BASE_ADDR_MASK                                   0xfffffff
+#define DL25_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_DL25_CUR_MSB */
+#define DL25_CUR_PTR_MSB_SFT                                  0
+#define DL25_CUR_PTR_MSB_MASK                                 0x1ff
+#define DL25_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_DL25_CUR */
+#define DL25_CUR_PTR_SFT                                      0
+#define DL25_CUR_PTR_MASK                                     0xffffffff
+#define DL25_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL25_END_MSB */
+#define DL25_END_ADDR_MSB_SFT                                 0
+#define DL25_END_ADDR_MSB_MASK                                0x1ff
+#define DL25_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_DL25_END */
+#define DL25_END_ADDR_SFT                                     4
+#define DL25_END_ADDR_MASK                                    0xfffffff
+#define DL25_END_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_DL25_RCH_MON */
+#define DL25_RCH_DATA_SFT                                     0
+#define DL25_RCH_DATA_MASK                                    0xffffffff
+#define DL25_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_DL25_LCH_MON */
+#define DL25_LCH_DATA_SFT                                     0
+#define DL25_LCH_DATA_MASK                                    0xffffffff
+#define DL25_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_DL25_CON0 */
+#define DL25_ON_SFT                                           28
+#define DL25_ON_MASK                                          0x1
+#define DL25_ON_MASK_SFT                                      (0x1 << 28)
+#define DL25_ONE_HEART_SEL_SFT                                22
+#define DL25_ONE_HEART_SEL_MASK                               0x3
+#define DL25_ONE_HEART_SEL_MASK_SFT                           (0x3 << 22)
+#define DL25_MINLEN_SFT                                       20
+#define DL25_MINLEN_MASK                                      0x3
+#define DL25_MINLEN_MASK_SFT                                  (0x3 << 20)
+#define DL25_MAXLEN_SFT                                       16
+#define DL25_MAXLEN_MASK                                      0x3
+#define DL25_MAXLEN_MASK_SFT                                  (0x3 << 16)
+#define DL25_SEL_DOMAIN_SFT                                   13
+#define DL25_SEL_DOMAIN_MASK                                  0x7
+#define DL25_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
+#define DL25_SEL_FS_SFT                                       8
+#define DL25_SEL_FS_MASK                                      0x1f
+#define DL25_SEL_FS_MASK_SFT                                  (0x1f << 8)
+#define DL25_SW_CLEAR_BUF_EMPTY_SFT                           7
+#define DL25_SW_CLEAR_BUF_EMPTY_MASK                          0x1
+#define DL25_SW_CLEAR_BUF_EMPTY_MASK_SFT                      (0x1 << 7)
+#define DL25_PBUF_SIZE_SFT                                    5
+#define DL25_PBUF_SIZE_MASK                                   0x3
+#define DL25_PBUF_SIZE_MASK_SFT                               (0x3 << 5)
+#define DL25_MONO_SFT                                         4
+#define DL25_MONO_MASK                                        0x1
+#define DL25_MONO_MASK_SFT                                    (0x1 << 4)
+#define DL25_NORMAL_MODE_SFT                                  3
+#define DL25_NORMAL_MODE_MASK                                 0x1
+#define DL25_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
+#define DL25_HALIGN_SFT                                       2
+#define DL25_HALIGN_MASK                                      0x1
+#define DL25_HALIGN_MASK_SFT                                  (0x1 << 2)
+#define DL25_HD_MODE_SFT                                      0
+#define DL25_HD_MODE_MASK                                     0x3
+#define DL25_HD_MODE_MASK_SFT                                 (0x3 << 0)
+
+/* AFE_DL26_BASE_MSB */
+#define DL26_BASE__ADDR_MSB_SFT                               0
+#define DL26_BASE__ADDR_MSB_MASK                              0x1ff
+#define DL26_BASE__ADDR_MSB_MASK_SFT                          (0x1ff << 0)
+
+/* AFE_DL26_BASE */
+#define DL26_BASE_ADDR_SFT                                    4
+#define DL26_BASE_ADDR_MASK                                   0xfffffff
+#define DL26_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_DL26_CUR_MSB */
+#define DL26_CUR_PTR_MSB_SFT                                  0
+#define DL26_CUR_PTR_MSB_MASK                                 0x1ff
+#define DL26_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_DL26_CUR */
+#define DL26_CUR_PTR_SFT                                      0
+#define DL26_CUR_PTR_MASK                                     0xffffffff
+#define DL26_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_DL26_END_MSB */
+#define DL26_END_ADDR_MSB_SFT                                 0
+#define DL26_END_ADDR_MSB_MASK                                0x1ff
+#define DL26_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_DL26_END */
+#define DL26_END_ADDR_SFT                                     4
+#define DL26_END_ADDR_MASK                                    0xfffffff
+#define DL26_END_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_DL26_RCH_MON */
+#define DL26_RCH_DATA_SFT                                     0
+#define DL26_RCH_DATA_MASK                                    0xffffffff
+#define DL26_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_DL26_LCH_MON */
+#define DL26_LCH_DATA_SFT                                     0
+#define DL26_LCH_DATA_MASK                                    0xffffffff
+#define DL26_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_DL26_CON0 */
+#define DL26_ON_SFT                                           28
+#define DL26_ON_MASK                                          0x1
+#define DL26_ON_MASK_SFT                                      (0x1 << 28)
+#define DL26_ONE_HEART_SEL_SFT                                22
+#define DL26_ONE_HEART_SEL_MASK                               0x3
+#define DL26_ONE_HEART_SEL_MASK_SFT                           (0x3 << 22)
+#define DL26_MINLEN_SFT                                       20
+#define DL26_MINLEN_MASK                                      0x3
+#define DL26_MINLEN_MASK_SFT                                  (0x3 << 20)
+#define DL26_MAXLEN_SFT                                       16
+#define DL26_MAXLEN_MASK                                      0x3
+#define DL26_MAXLEN_MASK_SFT                                  (0x3 << 16)
+#define DL26_SEL_DOMAIN_SFT                                   13
+#define DL26_SEL_DOMAIN_MASK                                  0x7
+#define DL26_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
+#define DL26_SEL_FS_SFT                                       8
+#define DL26_SEL_FS_MASK                                      0x1f
+#define DL26_SEL_FS_MASK_SFT                                  (0x1f << 8)
+#define DL26_SW_CLEAR_BUF_EMPTY_SFT                           7
+#define DL26_SW_CLEAR_BUF_EMPTY_MASK                          0x1
+#define DL26_SW_CLEAR_BUF_EMPTY_MASK_SFT                      (0x1 << 7)
+#define DL26_PBUF_SIZE_SFT                                    5
+#define DL26_PBUF_SIZE_MASK                                   0x3
+#define DL26_PBUF_SIZE_MASK_SFT                               (0x3 << 5)
+#define DL26_MONO_SFT                                         4
+#define DL26_MONO_MASK                                        0x1
+#define DL26_MONO_MASK_SFT                                    (0x1 << 4)
+#define DL26_NORMAL_MODE_SFT                                  3
+#define DL26_NORMAL_MODE_MASK                                 0x1
+#define DL26_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
+#define DL26_HALIGN_SFT                                       2
+#define DL26_HALIGN_MASK                                      0x1
+#define DL26_HALIGN_MASK_SFT                                  (0x1 << 2)
+#define DL26_HD_MODE_SFT                                      0
+#define DL26_HD_MODE_MASK                                     0x3
+#define DL26_HD_MODE_MASK_SFT                                 (0x3 << 0)
+
+/* AFE_VUL0_BASE_MSB */
+#define VUL0_BASE_ADDR_MSB_SFT                                0
+#define VUL0_BASE_ADDR_MSB_MASK                               0x1ff
+#define VUL0_BASE_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_VUL0_BASE */
+#define VUL0_BASE_ADDR_SFT                                    4
+#define VUL0_BASE_ADDR_MASK                                   0xfffffff
+#define VUL0_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_VUL0_CUR_MSB */
+#define VUL0_CUR_PTR_MSB_SFT                                  0
+#define VUL0_CUR_PTR_MSB_MASK                                 0x1ff
+#define VUL0_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_VUL0_CUR */
+#define VUL0_CUR_PTR_SFT                                      0
+#define VUL0_CUR_PTR_MASK                                     0xffffffff
+#define VUL0_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_VUL0_END_MSB */
+#define VUL0_END_ADDR_MSB_SFT                                 0
+#define VUL0_END_ADDR_MSB_MASK                                0x1ff
+#define VUL0_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_VUL0_END */
+#define VUL0_END_ADDR_SFT                                     4
+#define VUL0_END_ADDR_MASK                                    0xfffffff
+#define VUL0_END_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_VUL0_RCH_MON */
+#define VUL0_RCH_DATA_SFT                                     0
+#define VUL0_RCH_DATA_MASK                                    0xffffffff
+#define VUL0_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL0_LCH_MON */
+#define VUL0_LCH_DATA_SFT                                     0
+#define VUL0_LCH_DATA_MASK                                    0xffffffff
+#define VUL0_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL0_CON0 */
+#define VUL0_ON_SFT                                           28
+#define VUL0_ON_MASK                                          0x1
+#define VUL0_ON_MASK_SFT                                      (0x1 << 28)
+#define VUL0_MINLEN_SFT                                       20
+#define VUL0_MINLEN_MASK                                      0x3
+#define VUL0_MINLEN_MASK_SFT                                  (0x3 << 20)
+#define VUL0_MAXLEN_SFT                                       16
+#define VUL0_MAXLEN_MASK                                      0x3
+#define VUL0_MAXLEN_MASK_SFT                                  (0x3 << 16)
+#define VUL0_SEL_DOMAIN_SFT                                   13
+#define VUL0_SEL_DOMAIN_MASK                                  0x7
+#define VUL0_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
+#define VUL0_SEL_FS_SFT                                       8
+#define VUL0_SEL_FS_MASK                                      0x1f
+#define VUL0_SEL_FS_MASK_SFT                                  (0x1f << 8)
+#define VUL0_SW_CLEAR_BUF_FULL_SFT                            7
+#define VUL0_SW_CLEAR_BUF_FULL_MASK                           0x1
+#define VUL0_SW_CLEAR_BUF_FULL_MASK_SFT                       (0x1 << 7)
+#define VUL0_WR_SIGN_SFT                                      6
+#define VUL0_WR_SIGN_MASK                                     0x1
+#define VUL0_WR_SIGN_MASK_SFT                                 (0x1 << 6)
+#define VUL0_R_MONO_SFT                                       5
+#define VUL0_R_MONO_MASK                                      0x1
+#define VUL0_R_MONO_MASK_SFT                                  (0x1 << 5)
+#define VUL0_MONO_SFT                                         4
+#define VUL0_MONO_MASK                                        0x1
+#define VUL0_MONO_MASK_SFT                                    (0x1 << 4)
+#define VUL0_NORMAL_MODE_SFT                                  3
+#define VUL0_NORMAL_MODE_MASK                                 0x1
+#define VUL0_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
+#define VUL0_HALIGN_SFT                                       2
+#define VUL0_HALIGN_MASK                                      0x1
+#define VUL0_HALIGN_MASK_SFT                                  (0x1 << 2)
+#define VUL0_HD_MODE_SFT                                      0
+#define VUL0_HD_MODE_MASK                                     0x3
+#define VUL0_HD_MODE_MASK_SFT                                 (0x3 << 0)
+
+/* AFE_VUL1_BASE_MSB */
+#define VUL1_BASE_ADDR_MSB_SFT                                0
+#define VUL1_BASE_ADDR_MSB_MASK                               0x1ff
+#define VUL1_BASE_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_VUL1_BASE */
+#define VUL1_BASE_ADDR_SFT                                    4
+#define VUL1_BASE_ADDR_MASK                                   0xfffffff
+#define VUL1_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_VUL1_CUR_MSB */
+#define VUL1_CUR_PTR_MSB_SFT                                  0
+#define VUL1_CUR_PTR_MSB_MASK                                 0x1ff
+#define VUL1_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_VUL1_CUR */
+#define VUL1_CUR_PTR_SFT                                      0
+#define VUL1_CUR_PTR_MASK                                     0xffffffff
+#define VUL1_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_VUL1_END_MSB */
+#define VUL1_END_ADDR_MSB_SFT                                 0
+#define VUL1_END_ADDR_MSB_MASK                                0x1ff
+#define VUL1_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_VUL1_END */
+#define VUL1_END_ADDR_SFT                                     4
+#define VUL1_END_ADDR_MASK                                    0xfffffff
+#define VUL1_END_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_VUL1_RCH_MON */
+#define VUL1_RCH_DATA_SFT                                     0
+#define VUL1_RCH_DATA_MASK                                    0xffffffff
+#define VUL1_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL1_LCH_MON */
+#define VUL1_LCH_DATA_SFT                                     0
+#define VUL1_LCH_DATA_MASK                                    0xffffffff
+#define VUL1_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL1_CON0 */
+#define VUL1_ON_SFT                                           28
+#define VUL1_ON_MASK                                          0x1
+#define VUL1_ON_MASK_SFT                                      (0x1 << 28)
+#define VUL1_MINLEN_SFT                                       20
+#define VUL1_MINLEN_MASK                                      0x3
+#define VUL1_MINLEN_MASK_SFT                                  (0x3 << 20)
+#define VUL1_MAXLEN_SFT                                       16
+#define VUL1_MAXLEN_MASK                                      0x3
+#define VUL1_MAXLEN_MASK_SFT                                  (0x3 << 16)
+#define VUL1_SEL_DOMAIN_SFT                                   13
+#define VUL1_SEL_DOMAIN_MASK                                  0x7
+#define VUL1_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
+#define VUL1_SEL_FS_SFT                                       8
+#define VUL1_SEL_FS_MASK                                      0x1f
+#define VUL1_SEL_FS_MASK_SFT                                  (0x1f << 8)
+#define VUL1_SW_CLEAR_BUF_FULL_SFT                            7
+#define VUL1_SW_CLEAR_BUF_FULL_MASK                           0x1
+#define VUL1_SW_CLEAR_BUF_FULL_MASK_SFT                       (0x1 << 7)
+#define VUL1_WR_SIGN_SFT                                      6
+#define VUL1_WR_SIGN_MASK                                     0x1
+#define VUL1_WR_SIGN_MASK_SFT                                 (0x1 << 6)
+#define VUL1_R_MONO_SFT                                       5
+#define VUL1_R_MONO_MASK                                      0x1
+#define VUL1_R_MONO_MASK_SFT                                  (0x1 << 5)
+#define VUL1_MONO_SFT                                         4
+#define VUL1_MONO_MASK                                        0x1
+#define VUL1_MONO_MASK_SFT                                    (0x1 << 4)
+#define VUL1_NORMAL_MODE_SFT                                  3
+#define VUL1_NORMAL_MODE_MASK                                 0x1
+#define VUL1_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
+#define VUL1_HALIGN_SFT                                       2
+#define VUL1_HALIGN_MASK                                      0x1
+#define VUL1_HALIGN_MASK_SFT                                  (0x1 << 2)
+#define VUL1_HD_MODE_SFT                                      0
+#define VUL1_HD_MODE_MASK                                     0x3
+#define VUL1_HD_MODE_MASK_SFT                                 (0x3 << 0)
+
+/* AFE_VUL2_BASE_MSB */
+#define VUL2_BASE_ADDR_MSB_SFT                                0
+#define VUL2_BASE_ADDR_MSB_MASK                               0x1ff
+#define VUL2_BASE_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_VUL2_BASE */
+#define VUL2_BASE_ADDR_SFT                                    4
+#define VUL2_BASE_ADDR_MASK                                   0xfffffff
+#define VUL2_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_VUL2_CUR_MSB */
+#define VUL2_CUR_PTR_MSB_SFT                                  0
+#define VUL2_CUR_PTR_MSB_MASK                                 0x1ff
+#define VUL2_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_VUL2_CUR */
+#define VUL2_CUR_PTR_SFT                                      0
+#define VUL2_CUR_PTR_MASK                                     0xffffffff
+#define VUL2_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_VUL2_END_MSB */
+#define VUL2_END_ADDR_MSB_SFT                                 0
+#define VUL2_END_ADDR_MSB_MASK                                0x1ff
+#define VUL2_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_VUL2_END */
+#define VUL2_END_ADDR_SFT                                     4
+#define VUL2_END_ADDR_MASK                                    0xfffffff
+#define VUL2_END_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_VUL2_RCH_MON */
+#define VUL2_RCH_DATA_SFT                                     0
+#define VUL2_RCH_DATA_MASK                                    0xffffffff
+#define VUL2_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL2_LCH_MON */
+#define VUL2_LCH_DATA_SFT                                     0
+#define VUL2_LCH_DATA_MASK                                    0xffffffff
+#define VUL2_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL2_CON0 */
+#define VUL2_ON_SFT                                           28
+#define VUL2_ON_MASK                                          0x1
+#define VUL2_ON_MASK_SFT                                      (0x1 << 28)
+#define VUL2_MINLEN_SFT                                       20
+#define VUL2_MINLEN_MASK                                      0x3
+#define VUL2_MINLEN_MASK_SFT                                  (0x3 << 20)
+#define VUL2_MAXLEN_SFT                                       16
+#define VUL2_MAXLEN_MASK                                      0x3
+#define VUL2_MAXLEN_MASK_SFT                                  (0x3 << 16)
+#define VUL2_SEL_DOMAIN_SFT                                   13
+#define VUL2_SEL_DOMAIN_MASK                                  0x7
+#define VUL2_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
+#define VUL2_SEL_FS_SFT                                       8
+#define VUL2_SEL_FS_MASK                                      0x1f
+#define VUL2_SEL_FS_MASK_SFT                                  (0x1f << 8)
+#define VUL2_SW_CLEAR_BUF_FULL_SFT                            7
+#define VUL2_SW_CLEAR_BUF_FULL_MASK                           0x1
+#define VUL2_SW_CLEAR_BUF_FULL_MASK_SFT                       (0x1 << 7)
+#define VUL2_WR_SIGN_SFT                                      6
+#define VUL2_WR_SIGN_MASK                                     0x1
+#define VUL2_WR_SIGN_MASK_SFT                                 (0x1 << 6)
+#define VUL2_R_MONO_SFT                                       5
+#define VUL2_R_MONO_MASK                                      0x1
+#define VUL2_R_MONO_MASK_SFT                                  (0x1 << 5)
+#define VUL2_MONO_SFT                                         4
+#define VUL2_MONO_MASK                                        0x1
+#define VUL2_MONO_MASK_SFT                                    (0x1 << 4)
+#define VUL2_NORMAL_MODE_SFT                                  3
+#define VUL2_NORMAL_MODE_MASK                                 0x1
+#define VUL2_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
+#define VUL2_HALIGN_SFT                                       2
+#define VUL2_HALIGN_MASK                                      0x1
+#define VUL2_HALIGN_MASK_SFT                                  (0x1 << 2)
+#define VUL2_HD_MODE_SFT                                      0
+#define VUL2_HD_MODE_MASK                                     0x3
+#define VUL2_HD_MODE_MASK_SFT                                 (0x3 << 0)
+
+/* AFE_VUL3_BASE_MSB */
+#define VUL3_BASE_ADDR_MSB_SFT                                0
+#define VUL3_BASE_ADDR_MSB_MASK                               0x1ff
+#define VUL3_BASE_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_VUL3_BASE */
+#define VUL3_BASE_ADDR_SFT                                    4
+#define VUL3_BASE_ADDR_MASK                                   0xfffffff
+#define VUL3_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_VUL3_CUR_MSB */
+#define VUL3_CUR_PTR_MSB_SFT                                  0
+#define VUL3_CUR_PTR_MSB_MASK                                 0x1ff
+#define VUL3_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_VUL3_CUR */
+#define VUL3_CUR_PTR_SFT                                      0
+#define VUL3_CUR_PTR_MASK                                     0xffffffff
+#define VUL3_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_VUL3_END_MSB */
+#define VUL3_END_ADDR_MSB_SFT                                 0
+#define VUL3_END_ADDR_MSB_MASK                                0x1ff
+#define VUL3_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_VUL3_END */
+#define VUL3_END_ADDR_SFT                                     4
+#define VUL3_END_ADDR_MASK                                    0xfffffff
+#define VUL3_END_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_VUL3_RCH_MON */
+#define VUL3_RCH_DATA_SFT                                     0
+#define VUL3_RCH_DATA_MASK                                    0xffffffff
+#define VUL3_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL3_LCH_MON */
+#define VUL3_LCH_DATA_SFT                                     0
+#define VUL3_LCH_DATA_MASK                                    0xffffffff
+#define VUL3_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL3_CON0 */
+#define VUL3_ON_SFT                                           28
+#define VUL3_ON_MASK                                          0x1
+#define VUL3_ON_MASK_SFT                                      (0x1 << 28)
+#define VUL3_MINLEN_SFT                                       20
+#define VUL3_MINLEN_MASK                                      0x3
+#define VUL3_MINLEN_MASK_SFT                                  (0x3 << 20)
+#define VUL3_MAXLEN_SFT                                       16
+#define VUL3_MAXLEN_MASK                                      0x3
+#define VUL3_MAXLEN_MASK_SFT                                  (0x3 << 16)
+#define VUL3_SEL_DOMAIN_SFT                                   13
+#define VUL3_SEL_DOMAIN_MASK                                  0x7
+#define VUL3_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
+#define VUL3_SEL_FS_SFT                                       8
+#define VUL3_SEL_FS_MASK                                      0x1f
+#define VUL3_SEL_FS_MASK_SFT                                  (0x1f << 8)
+#define VUL3_SW_CLEAR_BUF_FULL_SFT                            7
+#define VUL3_SW_CLEAR_BUF_FULL_MASK                           0x1
+#define VUL3_SW_CLEAR_BUF_FULL_MASK_SFT                       (0x1 << 7)
+#define VUL3_WR_SIGN_SFT                                      6
+#define VUL3_WR_SIGN_MASK                                     0x1
+#define VUL3_WR_SIGN_MASK_SFT                                 (0x1 << 6)
+#define VUL3_R_MONO_SFT                                       5
+#define VUL3_R_MONO_MASK                                      0x1
+#define VUL3_R_MONO_MASK_SFT                                  (0x1 << 5)
+#define VUL3_MONO_SFT                                         4
+#define VUL3_MONO_MASK                                        0x1
+#define VUL3_MONO_MASK_SFT                                    (0x1 << 4)
+#define VUL3_NORMAL_MODE_SFT                                  3
+#define VUL3_NORMAL_MODE_MASK                                 0x1
+#define VUL3_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
+#define VUL3_HALIGN_SFT                                       2
+#define VUL3_HALIGN_MASK                                      0x1
+#define VUL3_HALIGN_MASK_SFT                                  (0x1 << 2)
+#define VUL3_HD_MODE_SFT                                      0
+#define VUL3_HD_MODE_MASK                                     0x3
+#define VUL3_HD_MODE_MASK_SFT                                 (0x3 << 0)
+
+/* AFE_VUL4_BASE_MSB */
+#define VUL4_BASE_ADDR_MSB_SFT                                0
+#define VUL4_BASE_ADDR_MSB_MASK                               0x1ff
+#define VUL4_BASE_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_VUL4_BASE */
+#define VUL4_BASE_ADDR_SFT                                    4
+#define VUL4_BASE_ADDR_MASK                                   0xfffffff
+#define VUL4_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_VUL4_CUR_MSB */
+#define VUL4_CUR_PTR_MSB_SFT                                  0
+#define VUL4_CUR_PTR_MSB_MASK                                 0x1ff
+#define VUL4_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_VUL4_CUR */
+#define VUL4_CUR_PTR_SFT                                      0
+#define VUL4_CUR_PTR_MASK                                     0xffffffff
+#define VUL4_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_VUL4_END_MSB */
+#define VUL4_END_ADDR_MSB_SFT                                 0
+#define VUL4_END_ADDR_MSB_MASK                                0x1ff
+#define VUL4_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_VUL4_END */
+#define VUL4_END_ADDR_SFT                                     4
+#define VUL4_END_ADDR_MASK                                    0xfffffff
+#define VUL4_END_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_VUL4_RCH_MON */
+#define VUL4_RCH_DATA_SFT                                     0
+#define VUL4_RCH_DATA_MASK                                    0xffffffff
+#define VUL4_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL4_LCH_MON */
+#define VUL4_LCH_DATA_SFT                                     0
+#define VUL4_LCH_DATA_MASK                                    0xffffffff
+#define VUL4_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL4_CON0 */
+#define VUL4_ON_SFT                                           28
+#define VUL4_ON_MASK                                          0x1
+#define VUL4_ON_MASK_SFT                                      (0x1 << 28)
+#define VUL4_MINLEN_SFT                                       20
+#define VUL4_MINLEN_MASK                                      0x3
+#define VUL4_MINLEN_MASK_SFT                                  (0x3 << 20)
+#define VUL4_MAXLEN_SFT                                       16
+#define VUL4_MAXLEN_MASK                                      0x3
+#define VUL4_MAXLEN_MASK_SFT                                  (0x3 << 16)
+#define VUL4_SEL_DOMAIN_SFT                                   13
+#define VUL4_SEL_DOMAIN_MASK                                  0x7
+#define VUL4_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
+#define VUL4_SEL_FS_SFT                                       8
+#define VUL4_SEL_FS_MASK                                      0x1f
+#define VUL4_SEL_FS_MASK_SFT                                  (0x1f << 8)
+#define VUL4_SW_CLEAR_BUF_FULL_SFT                            7
+#define VUL4_SW_CLEAR_BUF_FULL_MASK                           0x1
+#define VUL4_SW_CLEAR_BUF_FULL_MASK_SFT                       (0x1 << 7)
+#define VUL4_WR_SIGN_SFT                                      6
+#define VUL4_WR_SIGN_MASK                                     0x1
+#define VUL4_WR_SIGN_MASK_SFT                                 (0x1 << 6)
+#define VUL4_R_MONO_SFT                                       5
+#define VUL4_R_MONO_MASK                                      0x1
+#define VUL4_R_MONO_MASK_SFT                                  (0x1 << 5)
+#define VUL4_MONO_SFT                                         4
+#define VUL4_MONO_MASK                                        0x1
+#define VUL4_MONO_MASK_SFT                                    (0x1 << 4)
+#define VUL4_NORMAL_MODE_SFT                                  3
+#define VUL4_NORMAL_MODE_MASK                                 0x1
+#define VUL4_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
+#define VUL4_HALIGN_SFT                                       2
+#define VUL4_HALIGN_MASK                                      0x1
+#define VUL4_HALIGN_MASK_SFT                                  (0x1 << 2)
+#define VUL4_HD_MODE_SFT                                      0
+#define VUL4_HD_MODE_MASK                                     0x3
+#define VUL4_HD_MODE_MASK_SFT                                 (0x3 << 0)
+
+/* AFE_VUL5_BASE_MSB */
+#define VUL5_BASE_ADDR_MSB_SFT                                0
+#define VUL5_BASE_ADDR_MSB_MASK                               0x1ff
+#define VUL5_BASE_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_VUL5_BASE */
+#define VUL5_BASE_ADDR_SFT                                    4
+#define VUL5_BASE_ADDR_MASK                                   0xfffffff
+#define VUL5_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_VUL5_CUR_MSB */
+#define VUL5_CUR_PTR_MSB_SFT                                  0
+#define VUL5_CUR_PTR_MSB_MASK                                 0x1ff
+#define VUL5_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_VUL5_CUR */
+#define VUL5_CUR_PTR_SFT                                      0
+#define VUL5_CUR_PTR_MASK                                     0xffffffff
+#define VUL5_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_VUL5_END_MSB */
+#define VUL5_END_ADDR_MSB_SFT                                 0
+#define VUL5_END_ADDR_MSB_MASK                                0x1ff
+#define VUL5_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_VUL5_END */
+#define VUL5_END_ADDR_SFT                                     4
+#define VUL5_END_ADDR_MASK                                    0xfffffff
+#define VUL5_END_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_VUL5_RCH_MON */
+#define VUL5_RCH_DATA_SFT                                     0
+#define VUL5_RCH_DATA_MASK                                    0xffffffff
+#define VUL5_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL5_LCH_MON */
+#define VUL5_LCH_DATA_SFT                                     0
+#define VUL5_LCH_DATA_MASK                                    0xffffffff
+#define VUL5_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL5_CON0 */
+#define VUL5_ON_SFT                                           28
+#define VUL5_ON_MASK                                          0x1
+#define VUL5_ON_MASK_SFT                                      (0x1 << 28)
+#define VUL5_MINLEN_SFT                                       20
+#define VUL5_MINLEN_MASK                                      0x3
+#define VUL5_MINLEN_MASK_SFT                                  (0x3 << 20)
+#define VUL5_MAXLEN_SFT                                       16
+#define VUL5_MAXLEN_MASK                                      0x3
+#define VUL5_MAXLEN_MASK_SFT                                  (0x3 << 16)
+#define VUL5_SEL_DOMAIN_SFT                                   13
+#define VUL5_SEL_DOMAIN_MASK                                  0x7
+#define VUL5_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
+#define VUL5_SEL_FS_SFT                                       8
+#define VUL5_SEL_FS_MASK                                      0x1f
+#define VUL5_SEL_FS_MASK_SFT                                  (0x1f << 8)
+#define VUL5_SW_CLEAR_BUF_FULL_SFT                            7
+#define VUL5_SW_CLEAR_BUF_FULL_MASK                           0x1
+#define VUL5_SW_CLEAR_BUF_FULL_MASK_SFT                       (0x1 << 7)
+#define VUL5_WR_SIGN_SFT                                      6
+#define VUL5_WR_SIGN_MASK                                     0x1
+#define VUL5_WR_SIGN_MASK_SFT                                 (0x1 << 6)
+#define VUL5_R_MONO_SFT                                       5
+#define VUL5_R_MONO_MASK                                      0x1
+#define VUL5_R_MONO_MASK_SFT                                  (0x1 << 5)
+#define VUL5_MONO_SFT                                         4
+#define VUL5_MONO_MASK                                        0x1
+#define VUL5_MONO_MASK_SFT                                    (0x1 << 4)
+#define VUL5_NORMAL_MODE_SFT                                  3
+#define VUL5_NORMAL_MODE_MASK                                 0x1
+#define VUL5_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
+#define VUL5_HALIGN_SFT                                       2
+#define VUL5_HALIGN_MASK                                      0x1
+#define VUL5_HALIGN_MASK_SFT                                  (0x1 << 2)
+#define VUL5_HD_MODE_SFT                                      0
+#define VUL5_HD_MODE_MASK                                     0x3
+#define VUL5_HD_MODE_MASK_SFT                                 (0x3 << 0)
+
+/* AFE_VUL6_BASE_MSB */
+#define VUL6_BASE_ADDR_MSB_SFT                                0
+#define VUL6_BASE_ADDR_MSB_MASK                               0x1ff
+#define VUL6_BASE_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_VUL6_BASE */
+#define VUL6_BASE_ADDR_SFT                                    4
+#define VUL6_BASE_ADDR_MASK                                   0xfffffff
+#define VUL6_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_VUL6_CUR_MSB */
+#define VUL6_CUR_PTR_MSB_SFT                                  0
+#define VUL6_CUR_PTR_MSB_MASK                                 0x1ff
+#define VUL6_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_VUL6_CUR */
+#define VUL6_CUR_PTR_SFT                                      0
+#define VUL6_CUR_PTR_MASK                                     0xffffffff
+#define VUL6_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_VUL6_END_MSB */
+#define VUL6_END_ADDR_MSB_SFT                                 0
+#define VUL6_END_ADDR_MSB_MASK                                0x1ff
+#define VUL6_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_VUL6_END */
+#define VUL6_END_ADDR_SFT                                     4
+#define VUL6_END_ADDR_MASK                                    0xfffffff
+#define VUL6_END_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_VUL6_RCH_MON */
+#define VUL6_RCH_DATA_SFT                                     0
+#define VUL6_RCH_DATA_MASK                                    0xffffffff
+#define VUL6_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL6_LCH_MON */
+#define VUL6_LCH_DATA_SFT                                     0
+#define VUL6_LCH_DATA_MASK                                    0xffffffff
+#define VUL6_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL6_CON0 */
+#define VUL6_ON_SFT                                           28
+#define VUL6_ON_MASK                                          0x1
+#define VUL6_ON_MASK_SFT                                      (0x1 << 28)
+#define VUL6_MINLEN_SFT                                       20
+#define VUL6_MINLEN_MASK                                      0x3
+#define VUL6_MINLEN_MASK_SFT                                  (0x3 << 20)
+#define VUL6_MAXLEN_SFT                                       16
+#define VUL6_MAXLEN_MASK                                      0x3
+#define VUL6_MAXLEN_MASK_SFT                                  (0x3 << 16)
+#define VUL6_SEL_DOMAIN_SFT                                   13
+#define VUL6_SEL_DOMAIN_MASK                                  0x7
+#define VUL6_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
+#define VUL6_SEL_FS_SFT                                       8
+#define VUL6_SEL_FS_MASK                                      0x1f
+#define VUL6_SEL_FS_MASK_SFT                                  (0x1f << 8)
+#define VUL6_SW_CLEAR_BUF_FULL_SFT                            7
+#define VUL6_SW_CLEAR_BUF_FULL_MASK                           0x1
+#define VUL6_SW_CLEAR_BUF_FULL_MASK_SFT                       (0x1 << 7)
+#define VUL6_WR_SIGN_SFT                                      6
+#define VUL6_WR_SIGN_MASK                                     0x1
+#define VUL6_WR_SIGN_MASK_SFT                                 (0x1 << 6)
+#define VUL6_R_MONO_SFT                                       5
+#define VUL6_R_MONO_MASK                                      0x1
+#define VUL6_R_MONO_MASK_SFT                                  (0x1 << 5)
+#define VUL6_MONO_SFT                                         4
+#define VUL6_MONO_MASK                                        0x1
+#define VUL6_MONO_MASK_SFT                                    (0x1 << 4)
+#define VUL6_NORMAL_MODE_SFT                                  3
+#define VUL6_NORMAL_MODE_MASK                                 0x1
+#define VUL6_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
+#define VUL6_HALIGN_SFT                                       2
+#define VUL6_HALIGN_MASK                                      0x1
+#define VUL6_HALIGN_MASK_SFT                                  (0x1 << 2)
+#define VUL6_HD_MODE_SFT                                      0
+#define VUL6_HD_MODE_MASK                                     0x3
+#define VUL6_HD_MODE_MASK_SFT                                 (0x3 << 0)
+
+/* AFE_VUL7_BASE_MSB */
+#define VUL7_BASE_ADDR_MSB_SFT                                0
+#define VUL7_BASE_ADDR_MSB_MASK                               0x1ff
+#define VUL7_BASE_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_VUL7_BASE */
+#define VUL7_BASE_ADDR_SFT                                    4
+#define VUL7_BASE_ADDR_MASK                                   0xfffffff
+#define VUL7_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_VUL7_CUR_MSB */
+#define VUL7_CUR_PTR_MSB_SFT                                  0
+#define VUL7_CUR_PTR_MSB_MASK                                 0x1ff
+#define VUL7_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_VUL7_CUR */
+#define VUL7_CUR_PTR_SFT                                      0
+#define VUL7_CUR_PTR_MASK                                     0xffffffff
+#define VUL7_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_VUL7_END_MSB */
+#define VUL7_END_ADDR_MSB_SFT                                 0
+#define VUL7_END_ADDR_MSB_MASK                                0x1ff
+#define VUL7_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_VUL7_END */
+#define VUL7_END_ADDR_SFT                                     4
+#define VUL7_END_ADDR_MASK                                    0xfffffff
+#define VUL7_END_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_VUL7_RCH_MON */
+#define VUL7_RCH_DATA_SFT                                     0
+#define VUL7_RCH_DATA_MASK                                    0xffffffff
+#define VUL7_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL7_LCH_MON */
+#define VUL7_LCH_DATA_SFT                                     0
+#define VUL7_LCH_DATA_MASK                                    0xffffffff
+#define VUL7_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL7_CON0 */
+#define VUL7_ON_SFT                                           28
+#define VUL7_ON_MASK                                          0x1
+#define VUL7_ON_MASK_SFT                                      (0x1 << 28)
+#define VUL7_MINLEN_SFT                                       20
+#define VUL7_MINLEN_MASK                                      0x3
+#define VUL7_MINLEN_MASK_SFT                                  (0x3 << 20)
+#define VUL7_MAXLEN_SFT                                       16
+#define VUL7_MAXLEN_MASK                                      0x3
+#define VUL7_MAXLEN_MASK_SFT                                  (0x3 << 16)
+#define VUL7_SEL_DOMAIN_SFT                                   13
+#define VUL7_SEL_DOMAIN_MASK                                  0x7
+#define VUL7_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
+#define VUL7_SEL_FS_SFT                                       8
+#define VUL7_SEL_FS_MASK                                      0x1f
+#define VUL7_SEL_FS_MASK_SFT                                  (0x1f << 8)
+#define VUL7_SW_CLEAR_BUF_FULL_SFT                            7
+#define VUL7_SW_CLEAR_BUF_FULL_MASK                           0x1
+#define VUL7_SW_CLEAR_BUF_FULL_MASK_SFT                       (0x1 << 7)
+#define VUL7_WR_SIGN_SFT                                      6
+#define VUL7_WR_SIGN_MASK                                     0x1
+#define VUL7_WR_SIGN_MASK_SFT                                 (0x1 << 6)
+#define VUL7_R_MONO_SFT                                       5
+#define VUL7_R_MONO_MASK                                      0x1
+#define VUL7_R_MONO_MASK_SFT                                  (0x1 << 5)
+#define VUL7_MONO_SFT                                         4
+#define VUL7_MONO_MASK                                        0x1
+#define VUL7_MONO_MASK_SFT                                    (0x1 << 4)
+#define VUL7_NORMAL_MODE_SFT                                  3
+#define VUL7_NORMAL_MODE_MASK                                 0x1
+#define VUL7_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
+#define VUL7_HALIGN_SFT                                       2
+#define VUL7_HALIGN_MASK                                      0x1
+#define VUL7_HALIGN_MASK_SFT                                  (0x1 << 2)
+#define VUL7_HD_MODE_SFT                                      0
+#define VUL7_HD_MODE_MASK                                     0x3
+#define VUL7_HD_MODE_MASK_SFT                                 (0x3 << 0)
+
+/* AFE_VUL8_BASE_MSB */
+#define VUL8_BASE_ADDR_MSB_SFT                                0
+#define VUL8_BASE_ADDR_MSB_MASK                               0x1ff
+#define VUL8_BASE_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_VUL8_BASE */
+#define VUL8_BASE_ADDR_SFT                                    4
+#define VUL8_BASE_ADDR_MASK                                   0xfffffff
+#define VUL8_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_VUL8_CUR_MSB */
+#define VUL8_CUR_PTR_MSB_SFT                                  0
+#define VUL8_CUR_PTR_MSB_MASK                                 0x1ff
+#define VUL8_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_VUL8_CUR */
+#define VUL8_CUR_PTR_SFT                                      0
+#define VUL8_CUR_PTR_MASK                                     0xffffffff
+#define VUL8_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_VUL8_END_MSB */
+#define VUL8_END_ADDR_MSB_SFT                                 0
+#define VUL8_END_ADDR_MSB_MASK                                0x1ff
+#define VUL8_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_VUL8_END */
+#define VUL8_END_ADDR_SFT                                     4
+#define VUL8_END_ADDR_MASK                                    0xfffffff
+#define VUL8_END_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_VUL8_RCH_MON */
+#define VUL8_RCH_DATA_SFT                                     0
+#define VUL8_RCH_DATA_MASK                                    0xffffffff
+#define VUL8_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL8_LCH_MON */
+#define VUL8_LCH_DATA_SFT                                     0
+#define VUL8_LCH_DATA_MASK                                    0xffffffff
+#define VUL8_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL8_CON0 */
+#define VUL8_ON_SFT                                           28
+#define VUL8_ON_MASK                                          0x1
+#define VUL8_ON_MASK_SFT                                      (0x1 << 28)
+#define VUL8_MINLEN_SFT                                       20
+#define VUL8_MINLEN_MASK                                      0x3
+#define VUL8_MINLEN_MASK_SFT                                  (0x3 << 20)
+#define VUL8_MAXLEN_SFT                                       16
+#define VUL8_MAXLEN_MASK                                      0x3
+#define VUL8_MAXLEN_MASK_SFT                                  (0x3 << 16)
+#define VUL8_SEL_DOMAIN_SFT                                   13
+#define VUL8_SEL_DOMAIN_MASK                                  0x7
+#define VUL8_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
+#define VUL8_SEL_FS_SFT                                       8
+#define VUL8_SEL_FS_MASK                                      0x1f
+#define VUL8_SEL_FS_MASK_SFT                                  (0x1f << 8)
+#define VUL8_SW_CLEAR_BUF_FULL_SFT                            7
+#define VUL8_SW_CLEAR_BUF_FULL_MASK                           0x1
+#define VUL8_SW_CLEAR_BUF_FULL_MASK_SFT                       (0x1 << 7)
+#define VUL8_WR_SIGN_SFT                                      6
+#define VUL8_WR_SIGN_MASK                                     0x1
+#define VUL8_WR_SIGN_MASK_SFT                                 (0x1 << 6)
+#define VUL8_R_MONO_SFT                                       5
+#define VUL8_R_MONO_MASK                                      0x1
+#define VUL8_R_MONO_MASK_SFT                                  (0x1 << 5)
+#define VUL8_MONO_SFT                                         4
+#define VUL8_MONO_MASK                                        0x1
+#define VUL8_MONO_MASK_SFT                                    (0x1 << 4)
+#define VUL8_NORMAL_MODE_SFT                                  3
+#define VUL8_NORMAL_MODE_MASK                                 0x1
+#define VUL8_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
+#define VUL8_HALIGN_SFT                                       2
+#define VUL8_HALIGN_MASK                                      0x1
+#define VUL8_HALIGN_MASK_SFT                                  (0x1 << 2)
+#define VUL8_HD_MODE_SFT                                      0
+#define VUL8_HD_MODE_MASK                                     0x3
+#define VUL8_HD_MODE_MASK_SFT                                 (0x3 << 0)
+
+/* AFE_VUL9_BASE_MSB */
+#define VUL9_BASE_ADDR_MSB_SFT                                0
+#define VUL9_BASE_ADDR_MSB_MASK                               0x1ff
+#define VUL9_BASE_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_VUL9_BASE */
+#define VUL9_BASE_ADDR_SFT                                    4
+#define VUL9_BASE_ADDR_MASK                                   0xfffffff
+#define VUL9_BASE_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_VUL9_CUR_MSB */
+#define VUL9_CUR_PTR_MSB_SFT                                  0
+#define VUL9_CUR_PTR_MSB_MASK                                 0x1ff
+#define VUL9_CUR_PTR_MSB_MASK_SFT                             (0x1ff << 0)
+
+/* AFE_VUL9_CUR */
+#define VUL9_CUR_PTR_SFT                                      0
+#define VUL9_CUR_PTR_MASK                                     0xffffffff
+#define VUL9_CUR_PTR_MASK_SFT                                 (0xffffffff << 0)
+
+/* AFE_VUL9_END_MSB */
+#define VUL9_END_ADDR_MSB_SFT                                 0
+#define VUL9_END_ADDR_MSB_MASK                                0x1ff
+#define VUL9_END_ADDR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_VUL9_END */
+#define VUL9_END_ADDR_SFT                                     4
+#define VUL9_END_ADDR_MASK                                    0xfffffff
+#define VUL9_END_ADDR_MASK_SFT                                (0xfffffff << 4)
+
+/* AFE_VUL9_RCH_MON */
+#define VUL9_RCH_DATA_SFT                                     0
+#define VUL9_RCH_DATA_MASK                                    0xffffffff
+#define VUL9_RCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL9_LCH_MON */
+#define VUL9_LCH_DATA_SFT                                     0
+#define VUL9_LCH_DATA_MASK                                    0xffffffff
+#define VUL9_LCH_DATA_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL9_CON0 */
+#define VUL9_ON_SFT                                           28
+#define VUL9_ON_MASK                                          0x1
+#define VUL9_ON_MASK_SFT                                      (0x1 << 28)
+#define VUL9_MINLEN_SFT                                       20
+#define VUL9_MINLEN_MASK                                      0x3
+#define VUL9_MINLEN_MASK_SFT                                  (0x3 << 20)
+#define VUL9_MAXLEN_SFT                                       16
+#define VUL9_MAXLEN_MASK                                      0x3
+#define VUL9_MAXLEN_MASK_SFT                                  (0x3 << 16)
+#define VUL9_SEL_DOMAIN_SFT                                   13
+#define VUL9_SEL_DOMAIN_MASK                                  0x7
+#define VUL9_SEL_DOMAIN_MASK_SFT                              (0x7 << 13)
+#define VUL9_SEL_FS_SFT                                       8
+#define VUL9_SEL_FS_MASK                                      0x1f
+#define VUL9_SEL_FS_MASK_SFT                                  (0x1f << 8)
+#define VUL9_SW_CLEAR_BUF_FULL_SFT                            7
+#define VUL9_SW_CLEAR_BUF_FULL_MASK                           0x1
+#define VUL9_SW_CLEAR_BUF_FULL_MASK_SFT                       (0x1 << 7)
+#define VUL9_WR_SIGN_SFT                                      6
+#define VUL9_WR_SIGN_MASK                                     0x1
+#define VUL9_WR_SIGN_MASK_SFT                                 (0x1 << 6)
+#define VUL9_R_MONO_SFT                                       5
+#define VUL9_R_MONO_MASK                                      0x1
+#define VUL9_R_MONO_MASK_SFT                                  (0x1 << 5)
+#define VUL9_MONO_SFT                                         4
+#define VUL9_MONO_MASK                                        0x1
+#define VUL9_MONO_MASK_SFT                                    (0x1 << 4)
+#define VUL9_NORMAL_MODE_SFT                                  3
+#define VUL9_NORMAL_MODE_MASK                                 0x1
+#define VUL9_NORMAL_MODE_MASK_SFT                             (0x1 << 3)
+#define VUL9_HALIGN_SFT                                       2
+#define VUL9_HALIGN_MASK                                      0x1
+#define VUL9_HALIGN_MASK_SFT                                  (0x1 << 2)
+#define VUL9_HD_MODE_SFT                                      0
+#define VUL9_HD_MODE_MASK                                     0x3
+#define VUL9_HD_MODE_MASK_SFT                                 (0x3 << 0)
+
+/* AFE_VUL10_BASE_MSB */
+#define VUL10_BASE_ADDR_MSB_SFT                               0
+#define VUL10_BASE_ADDR_MSB_MASK                              0x1ff
+#define VUL10_BASE_ADDR_MSB_MASK_SFT                          (0x1ff << 0)
+
+/* AFE_VUL10_BASE */
+#define VUL10_BASE_ADDR_SFT                                   4
+#define VUL10_BASE_ADDR_MASK                                  0xfffffff
+#define VUL10_BASE_ADDR_MASK_SFT                              (0xfffffff << 4)
+
+/* AFE_VUL10_CUR_MSB */
+#define VUL10_CUR_PTR_MSB_SFT                                 0
+#define VUL10_CUR_PTR_MSB_MASK                                0x1ff
+#define VUL10_CUR_PTR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_VUL10_CUR */
+#define VUL10_CUR_PTR_SFT                                     0
+#define VUL10_CUR_PTR_MASK                                    0xffffffff
+#define VUL10_CUR_PTR_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL10_END_MSB */
+#define VUL10_END_ADDR_MSB_SFT                                0
+#define VUL10_END_ADDR_MSB_MASK                               0x1ff
+#define VUL10_END_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_VUL10_END */
+#define VUL10_END_ADDR_SFT                                    4
+#define VUL10_END_ADDR_MASK                                   0xfffffff
+#define VUL10_END_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_VUL10_RCH_MON */
+#define VUL10_RCH_DATA_SFT                                    0
+#define VUL10_RCH_DATA_MASK                                   0xffffffff
+#define VUL10_RCH_DATA_MASK_SFT                               (0xffffffff << 0)
+
+/* AFE_VUL10_LCH_MON */
+#define VUL10_LCH_DATA_SFT                                    0
+#define VUL10_LCH_DATA_MASK                                   0xffffffff
+#define VUL10_LCH_DATA_MASK_SFT                               (0xffffffff << 0)
+
+/* AFE_VUL10_CON0 */
+#define VUL10_ON_SFT                                          28
+#define VUL10_ON_MASK                                         0x1
+#define VUL10_ON_MASK_SFT                                     (0x1 << 28)
+#define VUL10_MINLEN_SFT                                      20
+#define VUL10_MINLEN_MASK                                     0x3
+#define VUL10_MINLEN_MASK_SFT                                 (0x3 << 20)
+#define VUL10_MAXLEN_SFT                                      16
+#define VUL10_MAXLEN_MASK                                     0x3
+#define VUL10_MAXLEN_MASK_SFT                                 (0x3 << 16)
+#define VUL10_SEL_DOMAIN_SFT                                  13
+#define VUL10_SEL_DOMAIN_MASK                                 0x7
+#define VUL10_SEL_DOMAIN_MASK_SFT                             (0x7 << 13)
+#define VUL10_SEL_FS_SFT                                      8
+#define VUL10_SEL_FS_MASK                                     0x1f
+#define VUL10_SEL_FS_MASK_SFT                                 (0x1f << 8)
+#define VUL10_SW_CLEAR_BUF_FULL_SFT                           7
+#define VUL10_SW_CLEAR_BUF_FULL_MASK                          0x1
+#define VUL10_SW_CLEAR_BUF_FULL_MASK_SFT                      (0x1 << 7)
+#define VUL10_WR_SIGN_SFT                                     6
+#define VUL10_WR_SIGN_MASK                                    0x1
+#define VUL10_WR_SIGN_MASK_SFT                                (0x1 << 6)
+#define VUL10_R_MONO_SFT                                      5
+#define VUL10_R_MONO_MASK                                     0x1
+#define VUL10_R_MONO_MASK_SFT                                 (0x1 << 5)
+#define VUL10_MONO_SFT                                        4
+#define VUL10_MONO_MASK                                       0x1
+#define VUL10_MONO_MASK_SFT                                   (0x1 << 4)
+#define VUL10_NORMAL_MODE_SFT                                 3
+#define VUL10_NORMAL_MODE_MASK                                0x1
+#define VUL10_NORMAL_MODE_MASK_SFT                            (0x1 << 3)
+#define VUL10_HALIGN_SFT                                      2
+#define VUL10_HALIGN_MASK                                     0x1
+#define VUL10_HALIGN_MASK_SFT                                 (0x1 << 2)
+#define VUL10_HD_MODE_SFT                                     0
+#define VUL10_HD_MODE_MASK                                    0x3
+#define VUL10_HD_MODE_MASK_SFT                                (0x3 << 0)
+
+/* AFE_VUL24_BASE_MSB */
+#define VUL24_BASE_ADDR_MSB_SFT                               0
+#define VUL24_BASE_ADDR_MSB_MASK                              0x1ff
+#define VUL24_BASE_ADDR_MSB_MASK_SFT                          (0x1ff << 0)
+
+/* AFE_VUL24_BASE */
+#define VUL24_BASE_ADDR_SFT                                   4
+#define VUL24_BASE_ADDR_MASK                                  0xfffffff
+#define VUL24_BASE_ADDR_MASK_SFT                              (0xfffffff << 4)
+
+/* AFE_VUL24_CUR_MSB */
+#define VUL24_CUR_PTR_MSB_SFT                                 0
+#define VUL24_CUR_PTR_MSB_MASK                                0x1ff
+#define VUL24_CUR_PTR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_VUL24_CUR */
+#define VUL24_CUR_PTR_SFT                                     0
+#define VUL24_CUR_PTR_MASK                                    0xffffffff
+#define VUL24_CUR_PTR_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL24_END_MSB */
+#define VUL24_END_ADDR_MSB_SFT                                0
+#define VUL24_END_ADDR_MSB_MASK                               0x1ff
+#define VUL24_END_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_VUL24_END */
+#define VUL24_END_ADDR_SFT                                    4
+#define VUL24_END_ADDR_MASK                                   0xfffffff
+#define VUL24_END_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_VUL24_CON0 */
+#define OUT_ON_USE_VUL24_SFT                                  29
+#define OUT_ON_USE_VUL24_MASK                                 0x1
+#define OUT_ON_USE_VUL24_MASK_SFT                             (0x1 << 29)
+#define VUL24_ON_SFT                                          28
+#define VUL24_ON_MASK                                         0x1
+#define VUL24_ON_MASK_SFT                                     (0x1 << 28)
+#define VUL24_MINLEN_SFT                                      20
+#define VUL24_MINLEN_MASK                                     0x3
+#define VUL24_MINLEN_MASK_SFT                                 (0x3 << 20)
+#define VUL24_MAXLEN_SFT                                      16
+#define VUL24_MAXLEN_MASK                                     0x3
+#define VUL24_MAXLEN_MASK_SFT                                 (0x3 << 16)
+#define VUL24_SEL_DOMAIN_SFT                                  13
+#define VUL24_SEL_DOMAIN_MASK                                 0x7
+#define VUL24_SEL_DOMAIN_MASK_SFT                             (0x7 << 13)
+#define VUL24_SEL_FS_SFT                                      8
+#define VUL24_SEL_FS_MASK                                     0x1f
+#define VUL24_SEL_FS_MASK_SFT                                 (0x1f << 8)
+#define VUL24_SW_CLEAR_BUF_FULL_SFT                           7
+#define VUL24_SW_CLEAR_BUF_FULL_MASK                          0x1
+#define VUL24_SW_CLEAR_BUF_FULL_MASK_SFT                      (0x1 << 7)
+#define VUL24_WR_SIGN_SFT                                     6
+#define VUL24_WR_SIGN_MASK                                    0x1
+#define VUL24_WR_SIGN_MASK_SFT                                (0x1 << 6)
+#define VUL24_R_MONO_SFT                                      5
+#define VUL24_R_MONO_MASK                                     0x1
+#define VUL24_R_MONO_MASK_SFT                                 (0x1 << 5)
+#define VUL24_MONO_SFT                                        4
+#define VUL24_MONO_MASK                                       0x1
+#define VUL24_MONO_MASK_SFT                                   (0x1 << 4)
+#define VUL24_NORMAL_MODE_SFT                                 3
+#define VUL24_NORMAL_MODE_MASK                                0x1
+#define VUL24_NORMAL_MODE_MASK_SFT                            (0x1 << 3)
+#define VUL24_HALIGN_SFT                                      2
+#define VUL24_HALIGN_MASK                                     0x1
+#define VUL24_HALIGN_MASK_SFT                                 (0x1 << 2)
+#define VUL24_HD_MODE_SFT                                     0
+#define VUL24_HD_MODE_MASK                                    0x3
+#define VUL24_HD_MODE_MASK_SFT                                (0x3 << 0)
+
+/* AFE_VUL25_BASE_MSB */
+#define VUL25_BASE_ADDR_MSB_SFT                               0
+#define VUL25_BASE_ADDR_MSB_MASK                              0x1ff
+#define VUL25_BASE_ADDR_MSB_MASK_SFT                          (0x1ff << 0)
+
+/* AFE_VUL25_BASE */
+#define VUL25_BASE_ADDR_SFT                                   4
+#define VUL25_BASE_ADDR_MASK                                  0xfffffff
+#define VUL25_BASE_ADDR_MASK_SFT                              (0xfffffff << 4)
+
+/* AFE_VUL25_CUR_MSB */
+#define VUL25_CUR_PTR_MSB_SFT                                 0
+#define VUL25_CUR_PTR_MSB_MASK                                0x1ff
+#define VUL25_CUR_PTR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_VUL25_CUR */
+#define VUL25_CUR_PTR_SFT                                     0
+#define VUL25_CUR_PTR_MASK                                    0xffffffff
+#define VUL25_CUR_PTR_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL25_END_MSB */
+#define VUL25_END_ADDR_MSB_SFT                                0
+#define VUL25_END_ADDR_MSB_MASK                               0x1ff
+#define VUL25_END_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_VUL25_END */
+#define VUL25_END_ADDR_SFT                                    4
+#define VUL25_END_ADDR_MASK                                   0xfffffff
+#define VUL25_END_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_VUL25_CON0 */
+#define OUT_ON_USE_VUL25_SFT                                  29
+#define OUT_ON_USE_VUL25_MASK                                 0x1
+#define OUT_ON_USE_VUL25_MASK_SFT                             (0x1 << 29)
+#define VUL25_ON_SFT                                          28
+#define VUL25_ON_MASK                                         0x1
+#define VUL25_ON_MASK_SFT                                     (0x1 << 28)
+#define VUL25_MINLEN_SFT                                      20
+#define VUL25_MINLEN_MASK                                     0x3
+#define VUL25_MINLEN_MASK_SFT                                 (0x3 << 20)
+#define VUL25_MAXLEN_SFT                                      16
+#define VUL25_MAXLEN_MASK                                     0x3
+#define VUL25_MAXLEN_MASK_SFT                                 (0x3 << 16)
+#define VUL25_SEL_DOMAIN_SFT                                  13
+#define VUL25_SEL_DOMAIN_MASK                                 0x7
+#define VUL25_SEL_DOMAIN_MASK_SFT                             (0x7 << 13)
+#define VUL25_SEL_FS_SFT                                      8
+#define VUL25_SEL_FS_MASK                                     0x1f
+#define VUL25_SEL_FS_MASK_SFT                                 (0x1f << 8)
+#define VUL25_SW_CLEAR_BUF_FULL_SFT                           7
+#define VUL25_SW_CLEAR_BUF_FULL_MASK                          0x1
+#define VUL25_SW_CLEAR_BUF_FULL_MASK_SFT                      (0x1 << 7)
+#define VUL25_WR_SIGN_SFT                                     6
+#define VUL25_WR_SIGN_MASK                                    0x1
+#define VUL25_WR_SIGN_MASK_SFT                                (0x1 << 6)
+#define VUL25_R_MONO_SFT                                      5
+#define VUL25_R_MONO_MASK                                     0x1
+#define VUL25_R_MONO_MASK_SFT                                 (0x1 << 5)
+#define VUL25_MONO_SFT                                        4
+#define VUL25_MONO_MASK                                       0x1
+#define VUL25_MONO_MASK_SFT                                   (0x1 << 4)
+#define VUL25_NORMAL_MODE_SFT                                 3
+#define VUL25_NORMAL_MODE_MASK                                0x1
+#define VUL25_NORMAL_MODE_MASK_SFT                            (0x1 << 3)
+#define VUL25_HALIGN_SFT                                      2
+#define VUL25_HALIGN_MASK                                     0x1
+#define VUL25_HALIGN_MASK_SFT                                 (0x1 << 2)
+#define VUL25_HD_MODE_SFT                                     0
+#define VUL25_HD_MODE_MASK                                    0x3
+#define VUL25_HD_MODE_MASK_SFT                                (0x3 << 0)
+
+/* AFE_VUL26_BASE_MSB */
+#define VUL26_BASE_ADDR_MSB_SFT                               0
+#define VUL26_BASE_ADDR_MSB_MASK                              0x1ff
+#define VUL26_BASE_ADDR_MSB_MASK_SFT                          (0x1ff << 0)
+
+/* AFE_VUL26_BASE */
+#define VUL26_BASE_ADDR_SFT                                   4
+#define VUL26_BASE_ADDR_MASK                                  0xfffffff
+#define VUL26_BASE_ADDR_MASK_SFT                              (0xfffffff << 4)
+
+/* AFE_VUL26_CUR_MSB */
+#define VUL26_CUR_PTR_MSB_SFT                                 0
+#define VUL26_CUR_PTR_MSB_MASK                                0x1ff
+#define VUL26_CUR_PTR_MSB_MASK_SFT                            (0x1ff << 0)
+
+/* AFE_VUL26_CUR */
+#define VUL26_CUR_PTR_SFT                                     0
+#define VUL26_CUR_PTR_MASK                                    0xffffffff
+#define VUL26_CUR_PTR_MASK_SFT                                (0xffffffff << 0)
+
+/* AFE_VUL26_END_MSB */
+#define VUL26_END_ADDR_MSB_SFT                                0
+#define VUL26_END_ADDR_MSB_MASK                               0x1ff
+#define VUL26_END_ADDR_MSB_MASK_SFT                           (0x1ff << 0)
+
+/* AFE_VUL26_END */
+#define VUL26_END_ADDR_SFT                                    4
+#define VUL26_END_ADDR_MASK                                   0xfffffff
+#define VUL26_END_ADDR_MASK_SFT                               (0xfffffff << 4)
+
+/* AFE_VUL26_CON0 */
+#define OUT_ON_USE_VUL26_SFT                                  29
+#define OUT_ON_USE_VUL26_MASK                                 0x1
+#define OUT_ON_USE_VUL26_MASK_SFT                             (0x1 << 29)
+#define VUL26_ON_SFT                                          28
+#define VUL26_ON_MASK                                         0x1
+#define VUL26_ON_MASK_SFT                                     (0x1 << 28)
+#define VUL26_MINLEN_SFT                                      20
+#define VUL26_MINLEN_MASK                                     0x3
+#define VUL26_MINLEN_MASK_SFT                                 (0x3 << 20)
+#define VUL26_MAXLEN_SFT                                      16
+#define VUL26_MAXLEN_MASK                                     0x3
+#define VUL26_MAXLEN_MASK_SFT                                 (0x3 << 16)
+#define VUL26_SEL_DOMAIN_SFT                                  13
+#define VUL26_SEL_DOMAIN_MASK                                 0x7
+#define VUL26_SEL_DOMAIN_MASK_SFT                             (0x7 << 13)
+#define VUL26_SEL_FS_SFT                                      8
+#define VUL26_SEL_FS_MASK                                     0x1f
+#define VUL26_SEL_FS_MASK_SFT                                 (0x1f << 8)
+#define VUL26_SW_CLEAR_BUF_FULL_SFT                           7
+#define VUL26_SW_CLEAR_BUF_FULL_MASK                          0x1
+#define VUL26_SW_CLEAR_BUF_FULL_MASK_SFT                      (0x1 << 7)
+#define VUL26_WR_SIGN_SFT                                     6
+#define VUL26_WR_SIGN_MASK                                    0x1
+#define VUL26_WR_SIGN_MASK_SFT                                (0x1 << 6)
+#define VUL26_R_MONO_SFT                                      5
+#define VUL26_R_MONO_MASK                                     0x1
+#define VUL26_R_MONO_MASK_SFT                                 (0x1 << 5)
+#define VUL26_MONO_SFT                                        4
+#define VUL26_MONO_MASK                                       0x1
+#define VUL26_MONO_MASK_SFT                                   (0x1 << 4)
+#define VUL26_NORMAL_MODE_SFT                                 3
+#define VUL26_NORMAL_MODE_MASK                                0x1
+#define VUL26_NORMAL_MODE_MASK_SFT                            (0x1 << 3)
+#define VUL26_HALIGN_SFT                                      2
+#define VUL26_HALIGN_MASK                                     0x1
+#define VUL26_HALIGN_MASK_SFT                                 (0x1 << 2)
+#define VUL26_HD_MODE_SFT                                     0
+#define VUL26_HD_MODE_MASK                                    0x3
+#define VUL26_HD_MODE_MASK_SFT                                (0x3 << 0)
+
+/* AFE_VUL_CM0_BASE_MSB */
+#define VUL_CM0_BASE_ADDR_MSB_SFT                             0
+#define VUL_CM0_BASE_ADDR_MSB_MASK                            0x1ff
+#define VUL_CM0_BASE_ADDR_MSB_MASK_SFT                        (0x1ff << 0)
+
+/* AFE_VUL_CM0_BASE */
+#define VUL_CM0_BASE_ADDR_SFT                                 4
+#define VUL_CM0_BASE_ADDR_MASK                                0xfffffff
+#define VUL_CM0_BASE_ADDR_MASK_SFT                            (0xfffffff << 4)
+
+/* AFE_VUL_CM0_CUR_MSB */
+#define VUL_CM0_CUR_PTR_MSB_SFT                               0
+#define VUL_CM0_CUR_PTR_MSB_MASK                              0x1ff
+#define VUL_CM0_CUR_PTR_MSB_MASK_SFT                          (0x1ff << 0)
+
+/* AFE_VUL_CM0_CUR */
+#define VUL_CM0_CUR_PTR_SFT                                   0
+#define VUL_CM0_CUR_PTR_MASK                                  0xffffffff
+#define VUL_CM0_CUR_PTR_MASK_SFT                              (0xffffffff << 0)
+
+/* AFE_VUL_CM0_END_MSB */
+#define VUL_CM0_END_ADDR_MSB_SFT                              0
+#define VUL_CM0_END_ADDR_MSB_MASK                             0x1ff
+#define VUL_CM0_END_ADDR_MSB_MASK_SFT                         (0x1ff << 0)
+
+/* AFE_VUL_CM0_END */
+#define VUL_CM0_END_ADDR_SFT                                  4
+#define VUL_CM0_END_ADDR_MASK                                 0xfffffff
+#define VUL_CM0_END_ADDR_MASK_SFT                             (0xfffffff << 4)
+
+/* AFE_VUL_CM0_CON0 */
+#define VUL_CM0_ON_SFT                                        28
+#define VUL_CM0_ON_MASK                                       0x1
+#define VUL_CM0_ON_MASK_SFT                                   (0x1 << 28)
+#define VUL_CM0_REG_CH_SHIFT_MODE_SFT                         26
+#define VUL_CM0_REG_CH_SHIFT_MODE_MASK                        0x1
+#define VUL_CM0_REG_CH_SHIFT_MODE_MASK_SFT                    (0x1 << 26)
+#define VUL_CM0_RG_FORCE_NO_MASK_EXTRA_SFT                    25
+#define VUL_CM0_RG_FORCE_NO_MASK_EXTRA_MASK                   0x1
+#define VUL_CM0_RG_FORCE_NO_MASK_EXTRA_MASK_SFT               (0x1 << 25)
+#define VUL_CM0_SW_CLEAR_BUF_FULL_SFT                         24
+#define VUL_CM0_SW_CLEAR_BUF_FULL_MASK                        0x1
+#define VUL_CM0_SW_CLEAR_BUF_FULL_MASK_SFT                    (0x1 << 24)
+#define VUL_CM0_ULTRA_TH_SFT                                  20
+#define VUL_CM0_ULTRA_TH_MASK                                 0xf
+#define VUL_CM0_ULTRA_TH_MASK_SFT                             (0xf << 20)
+#define VUL_CM0_NORMAL_MODE_SFT                               17
+#define VUL_CM0_NORMAL_MODE_MASK                              0x1
+#define VUL_CM0_NORMAL_MODE_MASK_SFT                          (0x1 << 17)
+#define VUL_CM0_ODD_USE_EVEN_SFT                              16
+#define VUL_CM0_ODD_USE_EVEN_MASK                             0x1
+#define VUL_CM0_ODD_USE_EVEN_MASK_SFT                         (0x1 << 16)
+#define VUL_CM0_AXI_REQ_MAXLEN_SFT                            12
+#define VUL_CM0_AXI_REQ_MAXLEN_MASK                           0x3
+#define VUL_CM0_AXI_REQ_MAXLEN_MASK_SFT                       (0x3 << 12)
+#define VUL_CM0_AXI_REQ_MINLEN_SFT                            8
+#define VUL_CM0_AXI_REQ_MINLEN_MASK                           0x3
+#define VUL_CM0_AXI_REQ_MINLEN_MASK_SFT                       (0x3 << 8)
+#define VUL_CM0_HALIGN_SFT                                    7
+#define VUL_CM0_HALIGN_MASK                                   0x1
+#define VUL_CM0_HALIGN_MASK_SFT                               (0x1 << 7)
+#define VUL_CM0_SIGN_EXT_SFT                                  6
+#define VUL_CM0_SIGN_EXT_MASK                                 0x1
+#define VUL_CM0_SIGN_EXT_MASK_SFT                             (0x1 << 6)
+#define VUL_CM0_HD_MODE_SFT                                   4
+#define VUL_CM0_HD_MODE_MASK                                  0x3
+#define VUL_CM0_HD_MODE_MASK_SFT                              (0x3 << 4)
+#define VUL_CM0_MAKE_EXTRA_UPDATE_SFT                         3
+#define VUL_CM0_MAKE_EXTRA_UPDATE_MASK                        0x1
+#define VUL_CM0_MAKE_EXTRA_UPDATE_MASK_SFT                    (0x1 << 3)
+#define VUL_CM0_AGENT_FREE_RUN_SFT                            2
+#define VUL_CM0_AGENT_FREE_RUN_MASK                           0x1
+#define VUL_CM0_AGENT_FREE_RUN_MASK_SFT                       (0x1 << 2)
+#define VUL_CM0_USE_INT_ODD_SFT                               1
+#define VUL_CM0_USE_INT_ODD_MASK                              0x1
+#define VUL_CM0_USE_INT_ODD_MASK_SFT                          (0x1 << 1)
+#define VUL_CM0_INT_ODD_FLAG_SFT                              0
+#define VUL_CM0_INT_ODD_FLAG_MASK                             0x1
+#define VUL_CM0_INT_ODD_FLAG_MASK_SFT                         (0x1 << 0)
+
+/* AFE_VUL_CM1_BASE_MSB */
+#define VUL_CM1_BASE_ADDR_MSB_SFT                             0
+#define VUL_CM1_BASE_ADDR_MSB_MASK                            0x1ff
+#define VUL_CM1_BASE_ADDR_MSB_MASK_SFT                        (0x1ff << 0)
+
+/* AFE_VUL_CM1_BASE */
+#define VUL_CM1_BASE_ADDR_SFT                                 4
+#define VUL_CM1_BASE_ADDR_MASK                                0xfffffff
+#define VUL_CM1_BASE_ADDR_MASK_SFT                            (0xfffffff << 4)
+
+/* AFE_VUL_CM1_CUR_MSB */
+#define VUL_CM1_CUR_PTR_MSB_SFT                               0
+#define VUL_CM1_CUR_PTR_MSB_MASK                              0x1ff
+#define VUL_CM1_CUR_PTR_MSB_MASK_SFT                          (0x1ff << 0)
+
+/* AFE_VUL_CM1_CUR */
+#define VUL_CM1_CUR_PTR_SFT                                   0
+#define VUL_CM1_CUR_PTR_MASK                                  0xffffffff
+#define VUL_CM1_CUR_PTR_MASK_SFT                              (0xffffffff << 0)
+
+/* AFE_VUL_CM1_END_MSB */
+#define VUL_CM1_END_ADDR_MSB_SFT                              0
+#define VUL_CM1_END_ADDR_MSB_MASK                             0x1ff
+#define VUL_CM1_END_ADDR_MSB_MASK_SFT                         (0x1ff << 0)
+
+/* AFE_VUL_CM1_END */
+#define VUL_CM1_END_ADDR_SFT                                  4
+#define VUL_CM1_END_ADDR_MASK                                 0xfffffff
+#define VUL_CM1_END_ADDR_MASK_SFT                             (0xfffffff << 4)
+
+/* AFE_VUL_CM1_CON0 */
+#define VUL_CM1_ON_SFT                                        28
+#define VUL_CM1_ON_MASK                                       0x1
+#define VUL_CM1_ON_MASK_SFT                                   (0x1 << 28)
+#define VUL_CM1_REG_CH_SHIFT_MODE_SFT                         26
+#define VUL_CM1_REG_CH_SHIFT_MODE_MASK                        0x1
+#define VUL_CM1_REG_CH_SHIFT_MODE_MASK_SFT                    (0x1 << 26)
+#define VUL_CM1_RG_FORCE_NO_MASK_EXTRA_SFT                    25
+#define VUL_CM1_RG_FORCE_NO_MASK_EXTRA_MASK                   0x1
+#define VUL_CM1_RG_FORCE_NO_MASK_EXTRA_MASK_SFT               (0x1 << 25)
+#define VUL_CM1_SW_CLEAR_BUF_FULL_SFT                         24
+#define VUL_CM1_SW_CLEAR_BUF_FULL_MASK                        0x1
+#define VUL_CM1_SW_CLEAR_BUF_FULL_MASK_SFT                    (0x1 << 24)
+#define VUL_CM1_ULTRA_TH_SFT                                  20
+#define VUL_CM1_ULTRA_TH_MASK                                 0xf
+#define VUL_CM1_ULTRA_TH_MASK_SFT                             (0xf << 20)
+#define VUL_CM1_NORMAL_MODE_SFT                               17
+#define VUL_CM1_NORMAL_MODE_MASK                              0x1
+#define VUL_CM1_NORMAL_MODE_MASK_SFT                          (0x1 << 17)
+#define VUL_CM1_ODD_USE_EVEN_SFT                              16
+#define VUL_CM1_ODD_USE_EVEN_MASK                             0x1
+#define VUL_CM1_ODD_USE_EVEN_MASK_SFT                         (0x1 << 16)
+#define VUL_CM1_AXI_REQ_MAXLEN_SFT                            12
+#define VUL_CM1_AXI_REQ_MAXLEN_MASK                           0x3
+#define VUL_CM1_AXI_REQ_MAXLEN_MASK_SFT                       (0x3 << 12)
+#define VUL_CM1_AXI_REQ_MINLEN_SFT                            8
+#define VUL_CM1_AXI_REQ_MINLEN_MASK                           0x3
+#define VUL_CM1_AXI_REQ_MINLEN_MASK_SFT                       (0x3 << 8)
+#define VUL_CM1_HALIGN_SFT                                    7
+#define VUL_CM1_HALIGN_MASK                                   0x1
+#define VUL_CM1_HALIGN_MASK_SFT                               (0x1 << 7)
+#define VUL_CM1_SIGN_EXT_SFT                                  6
+#define VUL_CM1_SIGN_EXT_MASK                                 0x1
+#define VUL_CM1_SIGN_EXT_MASK_SFT                             (0x1 << 6)
+#define VUL_CM1_HD_MODE_SFT                                   4
+#define VUL_CM1_HD_MODE_MASK                                  0x3
+#define VUL_CM1_HD_MODE_MASK_SFT                              (0x3 << 4)
+#define VUL_CM1_MAKE_EXTRA_UPDATE_SFT                         3
+#define VUL_CM1_MAKE_EXTRA_UPDATE_MASK                        0x1
+#define VUL_CM1_MAKE_EXTRA_UPDATE_MASK_SFT                    (0x1 << 3)
+#define VUL_CM1_AGENT_FREE_RUN_SFT                            2
+#define VUL_CM1_AGENT_FREE_RUN_MASK                           0x1
+#define VUL_CM1_AGENT_FREE_RUN_MASK_SFT                       (0x1 << 2)
+#define VUL_CM1_USE_INT_ODD_SFT                               1
+#define VUL_CM1_USE_INT_ODD_MASK                              0x1
+#define VUL_CM1_USE_INT_ODD_MASK_SFT                          (0x1 << 1)
+#define VUL_CM1_INT_ODD_FLAG_SFT                              0
+#define VUL_CM1_INT_ODD_FLAG_MASK                             0x1
+#define VUL_CM1_INT_ODD_FLAG_MASK_SFT                         (0x1 << 0)
+
+/* AFE_VUL_CM2_BASE_MSB */
+#define VUL_CM2_BASE_ADDR_MSB_SFT                             0
+#define VUL_CM2_BASE_ADDR_MSB_MASK                            0x1ff
+#define VUL_CM2_BASE_ADDR_MSB_MASK_SFT                        (0x1ff << 0)
+
+/* AFE_VUL_CM2_BASE */
+#define VUL_CM2_BASE_ADDR_SFT                                 4
+#define VUL_CM2_BASE_ADDR_MASK                                0xfffffff
+#define VUL_CM2_BASE_ADDR_MASK_SFT                            (0xfffffff << 4)
+
+/* AFE_VUL_CM2_CUR_MSB */
+#define VUL_CM2_CUR_PTR_MSB_SFT                               0
+#define VUL_CM2_CUR_PTR_MSB_MASK                              0x1ff
+#define VUL_CM2_CUR_PTR_MSB_MASK_SFT                          (0x1ff << 0)
+
+/* AFE_VUL_CM2_CUR */
+#define VUL_CM2_CUR_PTR_SFT                                   0
+#define VUL_CM2_CUR_PTR_MASK                                  0xffffffff
+#define VUL_CM2_CUR_PTR_MASK_SFT                              (0xffffffff << 0)
+
+/* AFE_VUL_CM2_END_MSB */
+#define VUL_CM2_END_ADDR_MSB_SFT                              0
+#define VUL_CM2_END_ADDR_MSB_MASK                             0x1ff
+#define VUL_CM2_END_ADDR_MSB_MASK_SFT                         (0x1ff << 0)
+
+/* AFE_VUL_CM2_END */
+#define VUL_CM2_END_ADDR_SFT                                  4
+#define VUL_CM2_END_ADDR_MASK                                 0xfffffff
+#define VUL_CM2_END_ADDR_MASK_SFT                             (0xfffffff << 4)
+
+/* AFE_VUL_CM2_CON0 */
+#define VUL_CM2_ON_SFT                                        28
+#define VUL_CM2_ON_MASK                                       0x1
+#define VUL_CM2_ON_MASK_SFT                                   (0x1 << 28)
+#define VUL_CM2_REG_CH_SHIFT_MODE_SFT                         26
+#define VUL_CM2_REG_CH_SHIFT_MODE_MASK                        0x1
+#define VUL_CM2_REG_CH_SHIFT_MODE_MASK_SFT                    (0x1 << 26)
+#define VUL_CM2_RG_FORCE_NO_MASK_EXTRA_SFT                    25
+#define VUL_CM2_RG_FORCE_NO_MASK_EXTRA_MASK                   0x1
+#define VUL_CM2_RG_FORCE_NO_MASK_EXTRA_MASK_SFT               (0x1 << 25)
+#define VUL_CM2_SW_CLEAR_BUF_FULL_SFT                         24
+#define VUL_CM2_SW_CLEAR_BUF_FULL_MASK                        0x1
+#define VUL_CM2_SW_CLEAR_BUF_FULL_MASK_SFT                    (0x1 << 24)
+#define VUL_CM2_ULTRA_TH_SFT                                  20
+#define VUL_CM2_ULTRA_TH_MASK                                 0xf
+#define VUL_CM2_ULTRA_TH_MASK_SFT                             (0xf << 20)
+#define VUL_CM2_NORMAL_MODE_SFT                               17
+#define VUL_CM2_NORMAL_MODE_MASK                              0x1
+#define VUL_CM2_NORMAL_MODE_MASK_SFT                          (0x1 << 17)
+#define VUL_CM2_ODD_USE_EVEN_SFT                              16
+#define VUL_CM2_ODD_USE_EVEN_MASK                             0x1
+#define VUL_CM2_ODD_USE_EVEN_MASK_SFT                         (0x1 << 16)
+#define VUL_CM2_AXI_REQ_MAXLEN_SFT                            12
+#define VUL_CM2_AXI_REQ_MAXLEN_MASK                           0x3
+#define VUL_CM2_AXI_REQ_MAXLEN_MASK_SFT                       (0x3 << 12)
+#define VUL_CM2_AXI_REQ_MINLEN_SFT                            8
+#define VUL_CM2_AXI_REQ_MINLEN_MASK                           0x3
+#define VUL_CM2_AXI_REQ_MINLEN_MASK_SFT                       (0x3 << 8)
+#define VUL_CM2_HALIGN_SFT                                    7
+#define VUL_CM2_HALIGN_MASK                                   0x1
+#define VUL_CM2_HALIGN_MASK_SFT                               (0x1 << 7)
+#define VUL_CM2_SIGN_EXT_SFT                                  6
+#define VUL_CM2_SIGN_EXT_MASK                                 0x1
+#define VUL_CM2_SIGN_EXT_MASK_SFT                             (0x1 << 6)
+#define VUL_CM2_HD_MODE_SFT                                   4
+#define VUL_CM2_HD_MODE_MASK                                  0x3
+#define VUL_CM2_HD_MODE_MASK_SFT                              (0x3 << 4)
+#define VUL_CM2_MAKE_EXTRA_UPDATE_SFT                         3
+#define VUL_CM2_MAKE_EXTRA_UPDATE_MASK                        0x1
+#define VUL_CM2_MAKE_EXTRA_UPDATE_MASK_SFT                    (0x1 << 3)
+#define VUL_CM2_AGENT_FREE_RUN_SFT                            2
+#define VUL_CM2_AGENT_FREE_RUN_MASK                           0x1
+#define VUL_CM2_AGENT_FREE_RUN_MASK_SFT                       (0x1 << 2)
+#define VUL_CM2_USE_INT_ODD_SFT                               1
+#define VUL_CM2_USE_INT_ODD_MASK                              0x1
+#define VUL_CM2_USE_INT_ODD_MASK_SFT                          (0x1 << 1)
+#define VUL_CM2_INT_ODD_FLAG_SFT                              0
+#define VUL_CM2_INT_ODD_FLAG_MASK                             0x1
+#define VUL_CM2_INT_ODD_FLAG_MASK_SFT                         (0x1 << 0)
+
+/* AFE_ETDM_IN0_BASE_MSB */
+#define ETDM_IN0_BASE_ADDR_MSB_SFT                            0
+#define ETDM_IN0_BASE_ADDR_MSB_MASK                           0x1ff
+#define ETDM_IN0_BASE_ADDR_MSB_MASK_SFT                       (0x1ff << 0)
+
+/* AFE_ETDM_IN0_BASE */
+#define ETDM_IN0_BASE_ADDR_SFT                                4
+#define ETDM_IN0_BASE_ADDR_MASK                               0xfffffff
+#define ETDM_IN0_BASE_ADDR_MASK_SFT                           (0xfffffff << 4)
+
+/* AFE_ETDM_IN0_CUR_MSB */
+#define ETDM_IN0_CUR_PTR_MSB_SFT                              0
+#define ETDM_IN0_CUR_PTR_MSB_MASK                             0x1ff
+#define ETDM_IN0_CUR_PTR_MSB_MASK_SFT                         (0x1ff << 0)
+
+/* AFE_ETDM_IN0_CUR */
+#define ETDM_IN0_CUR_PTR_SFT                                  0
+#define ETDM_IN0_CUR_PTR_MASK                                 0xffffffff
+#define ETDM_IN0_CUR_PTR_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_ETDM_IN0_END_MSB */
+#define ETDM_IN0_END_ADDR_MSB_SFT                             0
+#define ETDM_IN0_END_ADDR_MSB_MASK                            0x1ff
+#define ETDM_IN0_END_ADDR_MSB_MASK_SFT                        (0x1ff << 0)
+
+/* AFE_ETDM_IN0_END */
+#define ETDM_IN0_END_ADDR_SFT                                 4
+#define ETDM_IN0_END_ADDR_MASK                                0xfffffff
+#define ETDM_IN0_END_ADDR_MASK_SFT                            (0xfffffff << 4)
+
+/* AFE_ETDM_IN0_CON0 */
+#define ETDM_IN0_CH_NUM_SFT                                   28
+#define ETDM_IN0_CH_NUM_MASK                                  0xf
+#define ETDM_IN0_CH_NUM_MASK_SFT                              (0xf << 28)
+#define ETDM_IN0_ON_SFT                                       27
+#define ETDM_IN0_ON_MASK                                      0x1
+#define ETDM_IN0_ON_MASK_SFT                                  (0x1 << 27)
+#define ETDM_IN0_REG_CH_SHIFT_MODE_SFT                        26
+#define ETDM_IN0_REG_CH_SHIFT_MODE_MASK                       0x1
+#define ETDM_IN0_REG_CH_SHIFT_MODE_MASK_SFT                   (0x1 << 26)
+#define ETDM_IN0_RG_FORCE_NO_MASK_EXTRA_SFT                   25
+#define ETDM_IN0_RG_FORCE_NO_MASK_EXTRA_MASK                  0x1
+#define ETDM_IN0_RG_FORCE_NO_MASK_EXTRA_MASK_SFT              (0x1 << 25)
+#define ETDM_IN0_SW_CLEAR_BUF_FULL_SFT                        24
+#define ETDM_IN0_SW_CLEAR_BUF_FULL_MASK                       0x1
+#define ETDM_IN0_SW_CLEAR_BUF_FULL_MASK_SFT                   (0x1 << 24)
+#define ETDM_IN0_ULTRA_TH_SFT                                 20
+#define ETDM_IN0_ULTRA_TH_MASK                                0xf
+#define ETDM_IN0_ULTRA_TH_MASK_SFT                            (0xf << 20)
+#define ETDM_IN0_NORMAL_MODE_SFT                              17
+#define ETDM_IN0_NORMAL_MODE_MASK                             0x1
+#define ETDM_IN0_NORMAL_MODE_MASK_SFT                         (0x1 << 17)
+#define ETDM_IN0_ODD_USE_EVEN_SFT                             16
+#define ETDM_IN0_ODD_USE_EVEN_MASK                            0x1
+#define ETDM_IN0_ODD_USE_EVEN_MASK_SFT                        (0x1 << 16)
+#define ETDM_IN0_AXI_REQ_MAXLEN_SFT                           12
+#define ETDM_IN0_AXI_REQ_MAXLEN_MASK                          0x3
+#define ETDM_IN0_AXI_REQ_MAXLEN_MASK_SFT                      (0x3 << 12)
+#define ETDM_IN0_AXI_REQ_MINLEN_SFT                           8
+#define ETDM_IN0_AXI_REQ_MINLEN_MASK                          0x3
+#define ETDM_IN0_AXI_REQ_MINLEN_MASK_SFT                      (0x3 << 8)
+#define ETDM_IN0_HALIGN_SFT                                   7
+#define ETDM_IN0_HALIGN_MASK                                  0x1
+#define ETDM_IN0_HALIGN_MASK_SFT                              (0x1 << 7)
+#define ETDM_IN0_SIGN_EXT_SFT                                 6
+#define ETDM_IN0_SIGN_EXT_MASK                                0x1
+#define ETDM_IN0_SIGN_EXT_MASK_SFT                            (0x1 << 6)
+#define ETDM_IN0_HD_MODE_SFT                                  4
+#define ETDM_IN0_HD_MODE_MASK                                 0x3
+#define ETDM_IN0_HD_MODE_MASK_SFT                             (0x3 << 4)
+#define ETDM_IN0_MAKE_EXTRA_UPDATE_SFT                        3
+#define ETDM_IN0_MAKE_EXTRA_UPDATE_MASK                       0x1
+#define ETDM_IN0_MAKE_EXTRA_UPDATE_MASK_SFT                   (0x1 << 3)
+#define ETDM_IN0_AGENT_FREE_RUN_SFT                           2
+#define ETDM_IN0_AGENT_FREE_RUN_MASK                          0x1
+#define ETDM_IN0_AGENT_FREE_RUN_MASK_SFT                      (0x1 << 2)
+#define ETDM_IN0_USE_INT_ODD_SFT                              1
+#define ETDM_IN0_USE_INT_ODD_MASK                             0x1
+#define ETDM_IN0_USE_INT_ODD_MASK_SFT                         (0x1 << 1)
+#define ETDM_IN0_INT_ODD_FLAG_SFT                             0
+#define ETDM_IN0_INT_ODD_FLAG_MASK                            0x1
+#define ETDM_IN0_INT_ODD_FLAG_MASK_SFT                        (0x1 << 0)
+
+/* AFE_ETDM_IN1_BASE_MSB */
+#define ETDM_IN1_BASE_ADDR_MSB_SFT                            0
+#define ETDM_IN1_BASE_ADDR_MSB_MASK                           0x1ff
+#define ETDM_IN1_BASE_ADDR_MSB_MASK_SFT                       (0x1ff << 0)
+
+/* AFE_ETDM_IN1_BASE */
+#define ETDM_IN1_BASE_ADDR_SFT                                4
+#define ETDM_IN1_BASE_ADDR_MASK                               0xfffffff
+#define ETDM_IN1_BASE_ADDR_MASK_SFT                           (0xfffffff << 4)
+
+/* AFE_ETDM_IN1_CUR_MSB */
+#define ETDM_IN1_CUR_PTR_MSB_SFT                              0
+#define ETDM_IN1_CUR_PTR_MSB_MASK                             0x1ff
+#define ETDM_IN1_CUR_PTR_MSB_MASK_SFT                         (0x1ff << 0)
+
+/* AFE_ETDM_IN1_CUR */
+#define ETDM_IN1_CUR_PTR_SFT                                  0
+#define ETDM_IN1_CUR_PTR_MASK                                 0xffffffff
+#define ETDM_IN1_CUR_PTR_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_ETDM_IN1_END_MSB */
+#define ETDM_IN1_END_ADDR_MSB_SFT                             0
+#define ETDM_IN1_END_ADDR_MSB_MASK                            0x1ff
+#define ETDM_IN1_END_ADDR_MSB_MASK_SFT                        (0x1ff << 0)
+
+/* AFE_ETDM_IN1_END */
+#define ETDM_IN1_END_ADDR_SFT                                 4
+#define ETDM_IN1_END_ADDR_MASK                                0xfffffff
+#define ETDM_IN1_END_ADDR_MASK_SFT                            (0xfffffff << 4)
+
+/* AFE_ETDM_IN1_CON0 */
+#define ETDM_IN1_CH_NUM_SFT                                   28
+#define ETDM_IN1_CH_NUM_MASK                                  0xf
+#define ETDM_IN1_CH_NUM_MASK_SFT                              (0xf << 28)
+#define ETDM_IN1_ON_SFT                                       27
+#define ETDM_IN1_ON_MASK                                      0x1
+#define ETDM_IN1_ON_MASK_SFT                                  (0x1 << 27)
+#define ETDM_IN1_REG_CH_SHIFT_MODE_SFT                        26
+#define ETDM_IN1_REG_CH_SHIFT_MODE_MASK                       0x1
+#define ETDM_IN1_REG_CH_SHIFT_MODE_MASK_SFT                   (0x1 << 26)
+#define ETDM_IN1_RG_FORCE_NO_MASK_EXTRA_SFT                   25
+#define ETDM_IN1_RG_FORCE_NO_MASK_EXTRA_MASK                  0x1
+#define ETDM_IN1_RG_FORCE_NO_MASK_EXTRA_MASK_SFT              (0x1 << 25)
+#define ETDM_IN1_SW_CLEAR_BUF_FULL_SFT                        24
+#define ETDM_IN1_SW_CLEAR_BUF_FULL_MASK                       0x1
+#define ETDM_IN1_SW_CLEAR_BUF_FULL_MASK_SFT                   (0x1 << 24)
+#define ETDM_IN1_ULTRA_TH_SFT                                 20
+#define ETDM_IN1_ULTRA_TH_MASK                                0xf
+#define ETDM_IN1_ULTRA_TH_MASK_SFT                            (0xf << 20)
+#define ETDM_IN1_NORMAL_MODE_SFT                              17
+#define ETDM_IN1_NORMAL_MODE_MASK                             0x1
+#define ETDM_IN1_NORMAL_MODE_MASK_SFT                         (0x1 << 17)
+#define ETDM_IN1_ODD_USE_EVEN_SFT                             16
+#define ETDM_IN1_ODD_USE_EVEN_MASK                            0x1
+#define ETDM_IN1_ODD_USE_EVEN_MASK_SFT                        (0x1 << 16)
+#define ETDM_IN1_AXI_REQ_MAXLEN_SFT                           12
+#define ETDM_IN1_AXI_REQ_MAXLEN_MASK                          0x3
+#define ETDM_IN1_AXI_REQ_MAXLEN_MASK_SFT                      (0x3 << 12)
+#define ETDM_IN1_AXI_REQ_MINLEN_SFT                           8
+#define ETDM_IN1_AXI_REQ_MINLEN_MASK                          0x3
+#define ETDM_IN1_AXI_REQ_MINLEN_MASK_SFT                      (0x3 << 8)
+#define ETDM_IN1_HALIGN_SFT                                   7
+#define ETDM_IN1_HALIGN_MASK                                  0x1
+#define ETDM_IN1_HALIGN_MASK_SFT                              (0x1 << 7)
+#define ETDM_IN1_SIGN_EXT_SFT                                 6
+#define ETDM_IN1_SIGN_EXT_MASK                                0x1
+#define ETDM_IN1_SIGN_EXT_MASK_SFT                            (0x1 << 6)
+#define ETDM_IN1_HD_MODE_SFT                                  4
+#define ETDM_IN1_HD_MODE_MASK                                 0x3
+#define ETDM_IN1_HD_MODE_MASK_SFT                             (0x3 << 4)
+#define ETDM_IN1_MAKE_EXTRA_UPDATE_SFT                        3
+#define ETDM_IN1_MAKE_EXTRA_UPDATE_MASK                       0x1
+#define ETDM_IN1_MAKE_EXTRA_UPDATE_MASK_SFT                   (0x1 << 3)
+#define ETDM_IN1_AGENT_FREE_RUN_SFT                           2
+#define ETDM_IN1_AGENT_FREE_RUN_MASK                          0x1
+#define ETDM_IN1_AGENT_FREE_RUN_MASK_SFT                      (0x1 << 2)
+#define ETDM_IN1_USE_INT_ODD_SFT                              1
+#define ETDM_IN1_USE_INT_ODD_MASK                             0x1
+#define ETDM_IN1_USE_INT_ODD_MASK_SFT                         (0x1 << 1)
+#define ETDM_IN1_INT_ODD_FLAG_SFT                             0
+#define ETDM_IN1_INT_ODD_FLAG_MASK                            0x1
+#define ETDM_IN1_INT_ODD_FLAG_MASK_SFT                        (0x1 << 0)
+
+/* AFE_ETDM_IN2_BASE_MSB */
+#define ETDM_IN2_BASE_ADDR_MSB_SFT                            0
+#define ETDM_IN2_BASE_ADDR_MSB_MASK                           0x1ff
+#define ETDM_IN2_BASE_ADDR_MSB_MASK_SFT                       (0x1ff << 0)
+
+/* AFE_ETDM_IN2_BASE */
+#define ETDM_IN2_BASE_ADDR_SFT                                4
+#define ETDM_IN2_BASE_ADDR_MASK                               0xfffffff
+#define ETDM_IN2_BASE_ADDR_MASK_SFT                           (0xfffffff << 4)
+
+/* AFE_ETDM_IN2_CUR_MSB */
+#define ETDM_IN2_CUR_PTR_MSB_SFT                              0
+#define ETDM_IN2_CUR_PTR_MSB_MASK                             0x1ff
+#define ETDM_IN2_CUR_PTR_MSB_MASK_SFT                         (0x1ff << 0)
+
+/* AFE_ETDM_IN2_CUR */
+#define ETDM_IN2_CUR_PTR_SFT                                  0
+#define ETDM_IN2_CUR_PTR_MASK                                 0xffffffff
+#define ETDM_IN2_CUR_PTR_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_ETDM_IN2_END_MSB */
+#define ETDM_IN2_END_ADDR_MSB_SFT                             0
+#define ETDM_IN2_END_ADDR_MSB_MASK                            0x1ff
+#define ETDM_IN2_END_ADDR_MSB_MASK_SFT                        (0x1ff << 0)
+
+/* AFE_ETDM_IN2_END */
+#define ETDM_IN2_END_ADDR_SFT                                 4
+#define ETDM_IN2_END_ADDR_MASK                                0xfffffff
+#define ETDM_IN2_END_ADDR_MASK_SFT                            (0xfffffff << 4)
+
+/* AFE_ETDM_IN2_CON0 */
+#define ETDM_IN2_CH_NUM_SFT                                   28
+#define ETDM_IN2_CH_NUM_MASK                                  0xf
+#define ETDM_IN2_CH_NUM_MASK_SFT                              (0xf << 28)
+#define ETDM_IN2_ON_SFT                                       27
+#define ETDM_IN2_ON_MASK                                      0x1
+#define ETDM_IN2_ON_MASK_SFT                                  (0x1 << 27)
+#define ETDM_IN2_REG_CH_SHIFT_MODE_SFT                        26
+#define ETDM_IN2_REG_CH_SHIFT_MODE_MASK                       0x1
+#define ETDM_IN2_REG_CH_SHIFT_MODE_MASK_SFT                   (0x1 << 26)
+#define ETDM_IN2_RG_FORCE_NO_MASK_EXTRA_SFT                   25
+#define ETDM_IN2_RG_FORCE_NO_MASK_EXTRA_MASK                  0x1
+#define ETDM_IN2_RG_FORCE_NO_MASK_EXTRA_MASK_SFT              (0x1 << 25)
+#define ETDM_IN2_SW_CLEAR_BUF_FULL_SFT                        24
+#define ETDM_IN2_SW_CLEAR_BUF_FULL_MASK                       0x1
+#define ETDM_IN2_SW_CLEAR_BUF_FULL_MASK_SFT                   (0x1 << 24)
+#define ETDM_IN2_ULTRA_TH_SFT                                 20
+#define ETDM_IN2_ULTRA_TH_MASK                                0xf
+#define ETDM_IN2_ULTRA_TH_MASK_SFT                            (0xf << 20)
+#define ETDM_IN2_NORMAL_MODE_SFT                              17
+#define ETDM_IN2_NORMAL_MODE_MASK                             0x1
+#define ETDM_IN2_NORMAL_MODE_MASK_SFT                         (0x1 << 17)
+#define ETDM_IN2_ODD_USE_EVEN_SFT                             16
+#define ETDM_IN2_ODD_USE_EVEN_MASK                            0x1
+#define ETDM_IN2_ODD_USE_EVEN_MASK_SFT                        (0x1 << 16)
+#define ETDM_IN2_AXI_REQ_MAXLEN_SFT                           12
+#define ETDM_IN2_AXI_REQ_MAXLEN_MASK                          0x3
+#define ETDM_IN2_AXI_REQ_MAXLEN_MASK_SFT                      (0x3 << 12)
+#define ETDM_IN2_AXI_REQ_MINLEN_SFT                           8
+#define ETDM_IN2_AXI_REQ_MINLEN_MASK                          0x3
+#define ETDM_IN2_AXI_REQ_MINLEN_MASK_SFT                      (0x3 << 8)
+#define ETDM_IN2_HALIGN_SFT                                   7
+#define ETDM_IN2_HALIGN_MASK                                  0x1
+#define ETDM_IN2_HALIGN_MASK_SFT                              (0x1 << 7)
+#define ETDM_IN2_SIGN_EXT_SFT                                 6
+#define ETDM_IN2_SIGN_EXT_MASK                                0x1
+#define ETDM_IN2_SIGN_EXT_MASK_SFT                            (0x1 << 6)
+#define ETDM_IN2_HD_MODE_SFT                                  4
+#define ETDM_IN2_HD_MODE_MASK                                 0x3
+#define ETDM_IN2_HD_MODE_MASK_SFT                             (0x3 << 4)
+#define ETDM_IN2_MAKE_EXTRA_UPDATE_SFT                        3
+#define ETDM_IN2_MAKE_EXTRA_UPDATE_MASK                       0x1
+#define ETDM_IN2_MAKE_EXTRA_UPDATE_MASK_SFT                   (0x1 << 3)
+#define ETDM_IN2_AGENT_FREE_RUN_SFT                           2
+#define ETDM_IN2_AGENT_FREE_RUN_MASK                          0x1
+#define ETDM_IN2_AGENT_FREE_RUN_MASK_SFT                      (0x1 << 2)
+#define ETDM_IN2_USE_INT_ODD_SFT                              1
+#define ETDM_IN2_USE_INT_ODD_MASK                             0x1
+#define ETDM_IN2_USE_INT_ODD_MASK_SFT                         (0x1 << 1)
+#define ETDM_IN2_INT_ODD_FLAG_SFT                             0
+#define ETDM_IN2_INT_ODD_FLAG_MASK                            0x1
+#define ETDM_IN2_INT_ODD_FLAG_MASK_SFT                        (0x1 << 0)
+
+/* AFE_ETDM_IN3_BASE_MSB */
+#define ETDM_IN3_BASE_ADDR_MSB_SFT                            0
+#define ETDM_IN3_BASE_ADDR_MSB_MASK                           0x1ff
+#define ETDM_IN3_BASE_ADDR_MSB_MASK_SFT                       (0x1ff << 0)
+
+/* AFE_ETDM_IN3_BASE */
+#define ETDM_IN3_BASE_ADDR_SFT                                4
+#define ETDM_IN3_BASE_ADDR_MASK                               0xfffffff
+#define ETDM_IN3_BASE_ADDR_MASK_SFT                           (0xfffffff << 4)
+
+/* AFE_ETDM_IN3_CUR_MSB */
+#define ETDM_IN3_CUR_PTR_MSB_SFT                              0
+#define ETDM_IN3_CUR_PTR_MSB_MASK                             0x1ff
+#define ETDM_IN3_CUR_PTR_MSB_MASK_SFT                         (0x1ff << 0)
+
+/* AFE_ETDM_IN3_CUR */
+#define ETDM_IN3_CUR_PTR_SFT                                  0
+#define ETDM_IN3_CUR_PTR_MASK                                 0xffffffff
+#define ETDM_IN3_CUR_PTR_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_ETDM_IN3_END_MSB */
+#define ETDM_IN3_END_ADDR_MSB_SFT                             0
+#define ETDM_IN3_END_ADDR_MSB_MASK                            0x1ff
+#define ETDM_IN3_END_ADDR_MSB_MASK_SFT                        (0x1ff << 0)
+
+/* AFE_ETDM_IN3_END */
+#define ETDM_IN3_END_ADDR_SFT                                 4
+#define ETDM_IN3_END_ADDR_MASK                                0xfffffff
+#define ETDM_IN3_END_ADDR_MASK_SFT                            (0xfffffff << 4)
+
+/* AFE_ETDM_IN3_CON0 */
+#define ETDM_IN3_CH_NUM_SFT                                   28
+#define ETDM_IN3_CH_NUM_MASK                                  0xf
+#define ETDM_IN3_CH_NUM_MASK_SFT                              (0xf << 28)
+#define ETDM_IN3_ON_SFT                                       27
+#define ETDM_IN3_ON_MASK                                      0x1
+#define ETDM_IN3_ON_MASK_SFT                                  (0x1 << 27)
+#define ETDM_IN3_REG_CH_SHIFT_MODE_SFT                        26
+#define ETDM_IN3_REG_CH_SHIFT_MODE_MASK                       0x1
+#define ETDM_IN3_REG_CH_SHIFT_MODE_MASK_SFT                   (0x1 << 26)
+#define ETDM_IN3_RG_FORCE_NO_MASK_EXTRA_SFT                   25
+#define ETDM_IN3_RG_FORCE_NO_MASK_EXTRA_MASK                  0x1
+#define ETDM_IN3_RG_FORCE_NO_MASK_EXTRA_MASK_SFT              (0x1 << 25)
+#define ETDM_IN3_SW_CLEAR_BUF_FULL_SFT                        24
+#define ETDM_IN3_SW_CLEAR_BUF_FULL_MASK                       0x1
+#define ETDM_IN3_SW_CLEAR_BUF_FULL_MASK_SFT                   (0x1 << 24)
+#define ETDM_IN3_ULTRA_TH_SFT                                 20
+#define ETDM_IN3_ULTRA_TH_MASK                                0xf
+#define ETDM_IN3_ULTRA_TH_MASK_SFT                            (0xf << 20)
+#define ETDM_IN3_NORMAL_MODE_SFT                              17
+#define ETDM_IN3_NORMAL_MODE_MASK                             0x1
+#define ETDM_IN3_NORMAL_MODE_MASK_SFT                         (0x1 << 17)
+#define ETDM_IN3_ODD_USE_EVEN_SFT                             16
+#define ETDM_IN3_ODD_USE_EVEN_MASK                            0x1
+#define ETDM_IN3_ODD_USE_EVEN_MASK_SFT                        (0x1 << 16)
+#define ETDM_IN3_AXI_REQ_MAXLEN_SFT                           12
+#define ETDM_IN3_AXI_REQ_MAXLEN_MASK                          0x3
+#define ETDM_IN3_AXI_REQ_MAXLEN_MASK_SFT                      (0x3 << 12)
+#define ETDM_IN3_AXI_REQ_MINLEN_SFT                           8
+#define ETDM_IN3_AXI_REQ_MINLEN_MASK                          0x3
+#define ETDM_IN3_AXI_REQ_MINLEN_MASK_SFT                      (0x3 << 8)
+#define ETDM_IN3_HALIGN_SFT                                   7
+#define ETDM_IN3_HALIGN_MASK                                  0x1
+#define ETDM_IN3_HALIGN_MASK_SFT                              (0x1 << 7)
+#define ETDM_IN3_SIGN_EXT_SFT                                 6
+#define ETDM_IN3_SIGN_EXT_MASK                                0x1
+#define ETDM_IN3_SIGN_EXT_MASK_SFT                            (0x1 << 6)
+#define ETDM_IN3_HD_MODE_SFT                                  4
+#define ETDM_IN3_HD_MODE_MASK                                 0x3
+#define ETDM_IN3_HD_MODE_MASK_SFT                             (0x3 << 4)
+#define ETDM_IN3_MAKE_EXTRA_UPDATE_SFT                        3
+#define ETDM_IN3_MAKE_EXTRA_UPDATE_MASK                       0x1
+#define ETDM_IN3_MAKE_EXTRA_UPDATE_MASK_SFT                   (0x1 << 3)
+#define ETDM_IN3_AGENT_FREE_RUN_SFT                           2
+#define ETDM_IN3_AGENT_FREE_RUN_MASK                          0x1
+#define ETDM_IN3_AGENT_FREE_RUN_MASK_SFT                      (0x1 << 2)
+#define ETDM_IN3_USE_INT_ODD_SFT                              1
+#define ETDM_IN3_USE_INT_ODD_MASK                             0x1
+#define ETDM_IN3_USE_INT_ODD_MASK_SFT                         (0x1 << 1)
+#define ETDM_IN3_INT_ODD_FLAG_SFT                             0
+#define ETDM_IN3_INT_ODD_FLAG_MASK                            0x1
+#define ETDM_IN3_INT_ODD_FLAG_MASK_SFT                        (0x1 << 0)
+
+/* AFE_ETDM_IN4_BASE_MSB */
+#define ETDM_IN4_BASE_ADDR_MSB_SFT                            0
+#define ETDM_IN4_BASE_ADDR_MSB_MASK                           0x1ff
+#define ETDM_IN4_BASE_ADDR_MSB_MASK_SFT                       (0x1ff << 0)
+
+/* AFE_ETDM_IN4_BASE */
+#define ETDM_IN4_BASE_ADDR_SFT                                4
+#define ETDM_IN4_BASE_ADDR_MASK                               0xfffffff
+#define ETDM_IN4_BASE_ADDR_MASK_SFT                           (0xfffffff << 4)
+
+/* AFE_ETDM_IN4_CUR_MSB */
+#define ETDM_IN4_CUR_PTR_MSB_SFT                              0
+#define ETDM_IN4_CUR_PTR_MSB_MASK                             0x1ff
+#define ETDM_IN4_CUR_PTR_MSB_MASK_SFT                         (0x1ff << 0)
+
+/* AFE_ETDM_IN4_CUR */
+#define ETDM_IN4_CUR_PTR_SFT                                  0
+#define ETDM_IN4_CUR_PTR_MASK                                 0xffffffff
+#define ETDM_IN4_CUR_PTR_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_ETDM_IN4_END_MSB */
+#define ETDM_IN4_END_ADDR_MSB_SFT                             0
+#define ETDM_IN4_END_ADDR_MSB_MASK                            0x1ff
+#define ETDM_IN4_END_ADDR_MSB_MASK_SFT                        (0x1ff << 0)
+
+/* AFE_ETDM_IN4_END */
+#define ETDM_IN4_END_ADDR_SFT                                 4
+#define ETDM_IN4_END_ADDR_MASK                                0xfffffff
+#define ETDM_IN4_END_ADDR_MASK_SFT                            (0xfffffff << 4)
+
+/* AFE_ETDM_IN4_CON0 */
+#define ETDM_IN4_CH_NUM_SFT                                   28
+#define ETDM_IN4_CH_NUM_MASK                                  0xf
+#define ETDM_IN4_CH_NUM_MASK_SFT                              (0xf << 28)
+#define ETDM_IN4_ON_SFT                                       27
+#define ETDM_IN4_ON_MASK                                      0x1
+#define ETDM_IN4_ON_MASK_SFT                                  (0x1 << 27)
+#define ETDM_IN4_REG_CH_SHIFT_MODE_SFT                        26
+#define ETDM_IN4_REG_CH_SHIFT_MODE_MASK                       0x1
+#define ETDM_IN4_REG_CH_SHIFT_MODE_MASK_SFT                   (0x1 << 26)
+#define ETDM_IN4_RG_FORCE_NO_MASK_EXTRA_SFT                   25
+#define ETDM_IN4_RG_FORCE_NO_MASK_EXTRA_MASK                  0x1
+#define ETDM_IN4_RG_FORCE_NO_MASK_EXTRA_MASK_SFT              (0x1 << 25)
+#define ETDM_IN4_SW_CLEAR_BUF_FULL_SFT                        24
+#define ETDM_IN4_SW_CLEAR_BUF_FULL_MASK                       0x1
+#define ETDM_IN4_SW_CLEAR_BUF_FULL_MASK_SFT                   (0x1 << 24)
+#define ETDM_IN4_ULTRA_TH_SFT                                 20
+#define ETDM_IN4_ULTRA_TH_MASK                                0xf
+#define ETDM_IN4_ULTRA_TH_MASK_SFT                            (0xf << 20)
+#define ETDM_IN4_NORMAL_MODE_SFT                              17
+#define ETDM_IN4_NORMAL_MODE_MASK                             0x1
+#define ETDM_IN4_NORMAL_MODE_MASK_SFT                         (0x1 << 17)
+#define ETDM_IN4_ODD_USE_EVEN_SFT                             16
+#define ETDM_IN4_ODD_USE_EVEN_MASK                            0x1
+#define ETDM_IN4_ODD_USE_EVEN_MASK_SFT                        (0x1 << 16)
+#define ETDM_IN4_AXI_REQ_MAXLEN_SFT                           12
+#define ETDM_IN4_AXI_REQ_MAXLEN_MASK                          0x3
+#define ETDM_IN4_AXI_REQ_MAXLEN_MASK_SFT                      (0x3 << 12)
+#define ETDM_IN4_AXI_REQ_MINLEN_SFT                           8
+#define ETDM_IN4_AXI_REQ_MINLEN_MASK                          0x3
+#define ETDM_IN4_AXI_REQ_MINLEN_MASK_SFT                      (0x3 << 8)
+#define ETDM_IN4_HALIGN_SFT                                   7
+#define ETDM_IN4_HALIGN_MASK                                  0x1
+#define ETDM_IN4_HALIGN_MASK_SFT                              (0x1 << 7)
+#define ETDM_IN4_SIGN_EXT_SFT                                 6
+#define ETDM_IN4_SIGN_EXT_MASK                                0x1
+#define ETDM_IN4_SIGN_EXT_MASK_SFT                            (0x1 << 6)
+#define ETDM_IN4_HD_MODE_SFT                                  4
+#define ETDM_IN4_HD_MODE_MASK                                 0x3
+#define ETDM_IN4_HD_MODE_MASK_SFT                             (0x3 << 4)
+#define ETDM_IN4_MAKE_EXTRA_UPDATE_SFT                        3
+#define ETDM_IN4_MAKE_EXTRA_UPDATE_MASK                       0x1
+#define ETDM_IN4_MAKE_EXTRA_UPDATE_MASK_SFT                   (0x1 << 3)
+#define ETDM_IN4_AGENT_FREE_RUN_SFT                           2
+#define ETDM_IN4_AGENT_FREE_RUN_MASK                          0x1
+#define ETDM_IN4_AGENT_FREE_RUN_MASK_SFT                      (0x1 << 2)
+#define ETDM_IN4_USE_INT_ODD_SFT                              1
+#define ETDM_IN4_USE_INT_ODD_MASK                             0x1
+#define ETDM_IN4_USE_INT_ODD_MASK_SFT                         (0x1 << 1)
+#define ETDM_IN4_INT_ODD_FLAG_SFT                             0
+#define ETDM_IN4_INT_ODD_FLAG_MASK                            0x1
+#define ETDM_IN4_INT_ODD_FLAG_MASK_SFT                        (0x1 << 0)
+
+/* AFE_ETDM_IN5_BASE_MSB */
+#define ETDM_IN5_BASE_ADDR_MSB_SFT                            0
+#define ETDM_IN5_BASE_ADDR_MSB_MASK                           0x1ff
+#define ETDM_IN5_BASE_ADDR_MSB_MASK_SFT                       (0x1ff << 0)
+
+/* AFE_ETDM_IN5_BASE */
+#define ETDM_IN5_BASE_ADDR_SFT                                4
+#define ETDM_IN5_BASE_ADDR_MASK                               0xfffffff
+#define ETDM_IN5_BASE_ADDR_MASK_SFT                           (0xfffffff << 4)
+
+/* AFE_ETDM_IN5_CUR_MSB */
+#define ETDM_IN5_CUR_PTR_MSB_SFT                              0
+#define ETDM_IN5_CUR_PTR_MSB_MASK                             0x1ff
+#define ETDM_IN5_CUR_PTR_MSB_MASK_SFT                         (0x1ff << 0)
+
+/* AFE_ETDM_IN5_CUR */
+#define ETDM_IN5_CUR_PTR_SFT                                  0
+#define ETDM_IN5_CUR_PTR_MASK                                 0xffffffff
+#define ETDM_IN5_CUR_PTR_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_ETDM_IN5_END_MSB */
+#define ETDM_IN5_END_ADDR_MSB_SFT                             0
+#define ETDM_IN5_END_ADDR_MSB_MASK                            0x1ff
+#define ETDM_IN5_END_ADDR_MSB_MASK_SFT                        (0x1ff << 0)
+
+/* AFE_ETDM_IN5_END */
+#define ETDM_IN5_END_ADDR_SFT                                 4
+#define ETDM_IN5_END_ADDR_MASK                                0xfffffff
+#define ETDM_IN5_END_ADDR_MASK_SFT                            (0xfffffff << 4)
+
+/* AFE_ETDM_IN5_CON0 */
+#define ETDM_IN5_CH_NUM_SFT                                   28
+#define ETDM_IN5_CH_NUM_MASK                                  0xf
+#define ETDM_IN5_CH_NUM_MASK_SFT                              (0xf << 28)
+#define ETDM_IN5_ON_SFT                                       27
+#define ETDM_IN5_ON_MASK                                      0x1
+#define ETDM_IN5_ON_MASK_SFT                                  (0x1 << 27)
+#define ETDM_IN5_REG_CH_SHIFT_MODE_SFT                        26
+#define ETDM_IN5_REG_CH_SHIFT_MODE_MASK                       0x1
+#define ETDM_IN5_REG_CH_SHIFT_MODE_MASK_SFT                   (0x1 << 26)
+#define ETDM_IN5_RG_FORCE_NO_MASK_EXTRA_SFT                   25
+#define ETDM_IN5_RG_FORCE_NO_MASK_EXTRA_MASK                  0x1
+#define ETDM_IN5_RG_FORCE_NO_MASK_EXTRA_MASK_SFT              (0x1 << 25)
+#define ETDM_IN5_SW_CLEAR_BUF_FULL_SFT                        24
+#define ETDM_IN5_SW_CLEAR_BUF_FULL_MASK                       0x1
+#define ETDM_IN5_SW_CLEAR_BUF_FULL_MASK_SFT                   (0x1 << 24)
+#define ETDM_IN5_ULTRA_TH_SFT                                 20
+#define ETDM_IN5_ULTRA_TH_MASK                                0xf
+#define ETDM_IN5_ULTRA_TH_MASK_SFT                            (0xf << 20)
+#define ETDM_IN5_NORMAL_MODE_SFT                              17
+#define ETDM_IN5_NORMAL_MODE_MASK                             0x1
+#define ETDM_IN5_NORMAL_MODE_MASK_SFT                         (0x1 << 17)
+#define ETDM_IN5_ODD_USE_EVEN_SFT                             16
+#define ETDM_IN5_ODD_USE_EVEN_MASK                            0x1
+#define ETDM_IN5_ODD_USE_EVEN_MASK_SFT                        (0x1 << 16)
+#define ETDM_IN5_AXI_REQ_MAXLEN_SFT                           12
+#define ETDM_IN5_AXI_REQ_MAXLEN_MASK                          0x3
+#define ETDM_IN5_AXI_REQ_MAXLEN_MASK_SFT                      (0x3 << 12)
+#define ETDM_IN5_AXI_REQ_MINLEN_SFT                           8
+#define ETDM_IN5_AXI_REQ_MINLEN_MASK                          0x3
+#define ETDM_IN5_AXI_REQ_MINLEN_MASK_SFT                      (0x3 << 8)
+#define ETDM_IN5_HALIGN_SFT                                   7
+#define ETDM_IN5_HALIGN_MASK                                  0x1
+#define ETDM_IN5_HALIGN_MASK_SFT                              (0x1 << 7)
+#define ETDM_IN5_SIGN_EXT_SFT                                 6
+#define ETDM_IN5_SIGN_EXT_MASK                                0x1
+#define ETDM_IN5_SIGN_EXT_MASK_SFT                            (0x1 << 6)
+#define ETDM_IN5_HD_MODE_SFT                                  4
+#define ETDM_IN5_HD_MODE_MASK                                 0x3
+#define ETDM_IN5_HD_MODE_MASK_SFT                             (0x3 << 4)
+#define ETDM_IN5_MAKE_EXTRA_UPDATE_SFT                        3
+#define ETDM_IN5_MAKE_EXTRA_UPDATE_MASK                       0x1
+#define ETDM_IN5_MAKE_EXTRA_UPDATE_MASK_SFT                   (0x1 << 3)
+#define ETDM_IN5_AGENT_FREE_RUN_SFT                           2
+#define ETDM_IN5_AGENT_FREE_RUN_MASK                          0x1
+#define ETDM_IN5_AGENT_FREE_RUN_MASK_SFT                      (0x1 << 2)
+#define ETDM_IN5_USE_INT_ODD_SFT                              1
+#define ETDM_IN5_USE_INT_ODD_MASK                             0x1
+#define ETDM_IN5_USE_INT_ODD_MASK_SFT                         (0x1 << 1)
+#define ETDM_IN5_INT_ODD_FLAG_SFT                             0
+#define ETDM_IN5_INT_ODD_FLAG_MASK                            0x1
+#define ETDM_IN5_INT_ODD_FLAG_MASK_SFT                        (0x1 << 0)
+
+/* AFE_ETDM_IN6_BASE_MSB */
+#define ETDM_IN6_BASE_ADDR_MSB_SFT                            0
+#define ETDM_IN6_BASE_ADDR_MSB_MASK                           0x1ff
+#define ETDM_IN6_BASE_ADDR_MSB_MASK_SFT                       (0x1ff << 0)
+
+/* AFE_ETDM_IN6_BASE */
+#define ETDM_IN6_BASE_ADDR_SFT                                4
+#define ETDM_IN6_BASE_ADDR_MASK                               0xfffffff
+#define ETDM_IN6_BASE_ADDR_MASK_SFT                           (0xfffffff << 4)
+
+/* AFE_ETDM_IN6_CUR_MSB */
+#define ETDM_IN6_CUR_PTR_MSB_SFT                              0
+#define ETDM_IN6_CUR_PTR_MSB_MASK                             0x1ff
+#define ETDM_IN6_CUR_PTR_MSB_MASK_SFT                         (0x1ff << 0)
+
+/* AFE_ETDM_IN6_CUR */
+#define ETDM_IN6_CUR_PTR_SFT                                  0
+#define ETDM_IN6_CUR_PTR_MASK                                 0xffffffff
+#define ETDM_IN6_CUR_PTR_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_ETDM_IN6_END_MSB */
+#define ETDM_IN6_END_ADDR_MSB_SFT                             0
+#define ETDM_IN6_END_ADDR_MSB_MASK                            0x1ff
+#define ETDM_IN6_END_ADDR_MSB_MASK_SFT                        (0x1ff << 0)
+
+/* AFE_ETDM_IN6_END */
+#define ETDM_IN6_END_ADDR_SFT                                 4
+#define ETDM_IN6_END_ADDR_MASK                                0xfffffff
+#define ETDM_IN6_END_ADDR_MASK_SFT                            (0xfffffff << 4)
+
+/* AFE_ETDM_IN6_CON0 */
+#define ETDM_IN6_CH_NUM_SFT                                   28
+#define ETDM_IN6_CH_NUM_MASK                                  0xf
+#define ETDM_IN6_CH_NUM_MASK_SFT                              (0xf << 28)
+#define ETDM_IN6_ON_SFT                                       27
+#define ETDM_IN6_ON_MASK                                      0x1
+#define ETDM_IN6_ON_MASK_SFT                                  (0x1 << 27)
+#define ETDM_IN6_REG_CH_SHIFT_MODE_SFT                        26
+#define ETDM_IN6_REG_CH_SHIFT_MODE_MASK                       0x1
+#define ETDM_IN6_REG_CH_SHIFT_MODE_MASK_SFT                   (0x1 << 26)
+#define ETDM_IN6_RG_FORCE_NO_MASK_EXTRA_SFT                   25
+#define ETDM_IN6_RG_FORCE_NO_MASK_EXTRA_MASK                  0x1
+#define ETDM_IN6_RG_FORCE_NO_MASK_EXTRA_MASK_SFT              (0x1 << 25)
+#define ETDM_IN6_SW_CLEAR_BUF_FULL_SFT                        24
+#define ETDM_IN6_SW_CLEAR_BUF_FULL_MASK                       0x1
+#define ETDM_IN6_SW_CLEAR_BUF_FULL_MASK_SFT                   (0x1 << 24)
+#define ETDM_IN6_ULTRA_TH_SFT                                 20
+#define ETDM_IN6_ULTRA_TH_MASK                                0xf
+#define ETDM_IN6_ULTRA_TH_MASK_SFT                            (0xf << 20)
+#define ETDM_IN6_NORMAL_MODE_SFT                              17
+#define ETDM_IN6_NORMAL_MODE_MASK                             0x1
+#define ETDM_IN6_NORMAL_MODE_MASK_SFT                         (0x1 << 17)
+#define ETDM_IN6_ODD_USE_EVEN_SFT                             16
+#define ETDM_IN6_ODD_USE_EVEN_MASK                            0x1
+#define ETDM_IN6_ODD_USE_EVEN_MASK_SFT                        (0x1 << 16)
+#define ETDM_IN6_AXI_REQ_MAXLEN_SFT                           12
+#define ETDM_IN6_AXI_REQ_MAXLEN_MASK                          0x3
+#define ETDM_IN6_AXI_REQ_MAXLEN_MASK_SFT                      (0x3 << 12)
+#define ETDM_IN6_AXI_REQ_MINLEN_SFT                           8
+#define ETDM_IN6_AXI_REQ_MINLEN_MASK                          0x3
+#define ETDM_IN6_AXI_REQ_MINLEN_MASK_SFT                      (0x3 << 8)
+#define ETDM_IN6_HALIGN_SFT                                   7
+#define ETDM_IN6_HALIGN_MASK                                  0x1
+#define ETDM_IN6_HALIGN_MASK_SFT                              (0x1 << 7)
+#define ETDM_IN6_SIGN_EXT_SFT                                 6
+#define ETDM_IN6_SIGN_EXT_MASK                                0x1
+#define ETDM_IN6_SIGN_EXT_MASK_SFT                            (0x1 << 6)
+#define ETDM_IN6_HD_MODE_SFT                                  4
+#define ETDM_IN6_HD_MODE_MASK                                 0x3
+#define ETDM_IN6_HD_MODE_MASK_SFT                             (0x3 << 4)
+#define ETDM_IN6_MAKE_EXTRA_UPDATE_SFT                        3
+#define ETDM_IN6_MAKE_EXTRA_UPDATE_MASK                       0x1
+#define ETDM_IN6_MAKE_EXTRA_UPDATE_MASK_SFT                   (0x1 << 3)
+#define ETDM_IN6_AGENT_FREE_RUN_SFT                           2
+#define ETDM_IN6_AGENT_FREE_RUN_MASK                          0x1
+#define ETDM_IN6_AGENT_FREE_RUN_MASK_SFT                      (0x1 << 2)
+#define ETDM_IN6_USE_INT_ODD_SFT                              1
+#define ETDM_IN6_USE_INT_ODD_MASK                             0x1
+#define ETDM_IN6_USE_INT_ODD_MASK_SFT                         (0x1 << 1)
+#define ETDM_IN6_INT_ODD_FLAG_SFT                             0
+#define ETDM_IN6_INT_ODD_FLAG_MASK                            0x1
+#define ETDM_IN6_INT_ODD_FLAG_MASK_SFT                        (0x1 << 0)
+
+/* AFE_HDMI_OUT_BASE_MSB */
+#define AFE_HDMI_OUT_BASE_MSB_SFT                             0
+#define AFE_HDMI_OUT_BASE_MSB_MASK                            0x1ff
+#define AFE_HDMI_OUT_BASE_MSB_MASK_SFT                        (0x1ff << 0)
+
+/* AFE_HDMI_OUT_BASE */
+#define AFE_HDMI_OUT_BASE_SFT                                 4
+#define AFE_HDMI_OUT_BASE_MASK                                0xfffffff
+#define AFE_HDMI_OUT_BASE_MASK_SFT                            (0xfffffff << 4)
+
+/* AFE_HDMI_OUT_CUR_MSB */
+#define AFE_HDMI_OUT_CUR_MSB_SFT                              0
+#define AFE_HDMI_OUT_CUR_MSB_MASK                             0x1ff
+#define AFE_HDMI_OUT_CUR_MSB_MASK_SFT                         (0x1ff << 0)
+
+/* AFE_HDMI_OUT_CUR */
+#define AFE_HDMI_OUT_CUR_SFT                                  0
+#define AFE_HDMI_OUT_CUR_MASK                                 0xffffffff
+#define AFE_HDMI_OUT_CUR_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_HDMI_OUT_END_MSB */
+#define AFE_HDMI_OUT_END_MSB_SFT                              0
+#define AFE_HDMI_OUT_END_MSB_MASK                             0x1ff
+#define AFE_HDMI_OUT_END_MSB_MASK_SFT                         (0x1ff << 0)
+
+/* AFE_HDMI_OUT_END */
+#define AFE_HDMI_OUT_END_SFT                                  4
+#define AFE_HDMI_OUT_END_MASK                                 0xfffffff
+#define AFE_HDMI_OUT_END_MASK_SFT                             (0xfffffff << 4)
+#define AFE_HDMI_OUT_END_LSB_SFT                              0
+#define AFE_HDMI_OUT_END_LSB_MASK                             0xf
+#define AFE_HDMI_OUT_END_LSB_MASK_SFT                         (0xf << 0)
+
+/* AFE_HDMI_OUT_CON0 */
+#define HDMI_OUT_ON_SFT                                       28
+#define HDMI_OUT_ON_MASK                                      0x1
+#define HDMI_OUT_ON_MASK_SFT                                  (0x1 << 28)
+#define HDMI_CH_NUM_SFT                                       24
+#define HDMI_CH_NUM_MASK                                      0xf
+#define HDMI_CH_NUM_MASK_SFT                                  (0xf << 24)
+#define HDMI_OUT_ONE_HEART_SEL_SFT                            22
+#define HDMI_OUT_ONE_HEART_SEL_MASK                           0x3
+#define HDMI_OUT_ONE_HEART_SEL_MASK_SFT                       (0x3 << 22)
+#define HDMI_OUT_MINLEN_SFT                                   20
+#define HDMI_OUT_MINLEN_MASK                                  0x3
+#define HDMI_OUT_MINLEN_MASK_SFT                              (0x3 << 20)
+#define HDMI_OUT_MAXLEN_SFT                                   16
+#define HDMI_OUT_MAXLEN_MASK                                  0x3
+#define HDMI_OUT_MAXLEN_MASK_SFT                              (0x3 << 16)
+#define HDMI_OUT_SW_CLEAR_BUF_EMPTY_SFT                       15
+#define HDMI_OUT_SW_CLEAR_BUF_EMPTY_MASK                      0x1
+#define HDMI_OUT_SW_CLEAR_BUF_EMPTY_MASK_SFT                  (0x1 << 15)
+#define HDMI_OUT_PBUF_SIZE_SFT                                12
+#define HDMI_OUT_PBUF_SIZE_MASK                               0x3
+#define HDMI_OUT_PBUF_SIZE_MASK_SFT                           (0x3 << 12)
+#define HDMI_OUT_SW_CLEAR_HDMI_BUF_EMPTY_SFT                  7
+#define HDMI_OUT_SW_CLEAR_HDMI_BUF_EMPTY_MASK                 0x1
+#define HDMI_OUT_SW_CLEAR_HDMI_BUF_EMPTY_MASK_SFT             (0x1 << 7)
+#define HDMI_OUT_NORMAL_MODE_SFT                              5
+#define HDMI_OUT_NORMAL_MODE_MASK                             0x1
+#define HDMI_OUT_NORMAL_MODE_MASK_SFT                         (0x1 << 5)
+#define HDMI_OUT_HALIGN_SFT                                   4
+#define HDMI_OUT_HALIGN_MASK                                  0x1
+#define HDMI_OUT_HALIGN_MASK_SFT                              (0x1 << 4)
+#define HDMI_OUT_HD_MODE_SFT                                  0
+#define HDMI_OUT_HD_MODE_MASK                                 0x3
+#define HDMI_OUT_HD_MODE_MASK_SFT                             (0x3 << 0)
+
+/* AFE_VUL24_RCH_MON */
+#define VUL24_RCH_DATA_SFT                                    0
+#define VUL24_RCH_DATA_MASK                                   0xffffffff
+#define VUL24_RCH_DATA_MASK_SFT                               (0xffffffff << 0)
+
+/* AFE_VUL24_LCH_MON */
+#define VUL24_LCH_DATA_SFT                                    0
+#define VUL24_LCH_DATA_MASK                                   0xffffffff
+#define VUL24_LCH_DATA_MASK_SFT                               (0xffffffff << 0)
+
+/* AFE_VUL25_RCH_MON */
+#define VUL25_RCH_DATA_SFT                                    0
+#define VUL25_RCH_DATA_MASK                                   0xffffffff
+#define VUL25_RCH_DATA_MASK_SFT                               (0xffffffff << 0)
+
+/* AFE_VUL25_LCH_MON */
+#define VUL25_LCH_DATA_SFT                                    0
+#define VUL25_LCH_DATA_MASK                                   0xffffffff
+#define VUL25_LCH_DATA_MASK_SFT                               (0xffffffff << 0)
+
+/* AFE_VUL26_RCH_MON */
+#define VUL26_RCH_DATA_SFT                                    0
+#define VUL26_RCH_DATA_MASK                                   0xffffffff
+#define VUL26_RCH_DATA_MASK_SFT                               (0xffffffff << 0)
+
+/* AFE_VUL26_LCH_MON */
+#define VUL26_LCH_DATA_SFT                                    0
+#define VUL26_LCH_DATA_MASK                                   0xffffffff
+#define VUL26_LCH_DATA_MASK_SFT                               (0xffffffff << 0)
+
+/* AFE_VUL_CM0_RCH_MON */
+#define VUL_CM0_RCH_DATA_SFT                                  0
+#define VUL_CM0_RCH_DATA_MASK                                 0xffffffff
+#define VUL_CM0_RCH_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_VUL_CM0_LCH_MON */
+#define VUL_CM0_LCH_DATA_SFT                                  0
+#define VUL_CM0_LCH_DATA_MASK                                 0xffffffff
+#define VUL_CM0_LCH_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_VUL_CM1_RCH_MON */
+#define VUL_CM1_RCH_DATA_SFT                                  0
+#define VUL_CM1_RCH_DATA_MASK                                 0xffffffff
+#define VUL_CM1_RCH_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_VUL_CM1_LCH_MON */
+#define VUL_CM1_LCH_DATA_SFT                                  0
+#define VUL_CM1_LCH_DATA_MASK                                 0xffffffff
+#define VUL_CM1_LCH_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_VUL_CM2_RCH_MON */
+#define VUL_CM2_RCH_DATA_SFT                                  0
+#define VUL_CM2_RCH_DATA_MASK                                 0xffffffff
+#define VUL_CM2_RCH_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_VUL_CM2_LCH_MON */
+#define VUL_CM2_LCH_DATA_SFT                                  0
+#define VUL_CM2_LCH_DATA_MASK                                 0xffffffff
+#define VUL_CM2_LCH_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_DL_4CH_CH0_MON */
+#define DL_4CH_CH0_DATA_SFT                                   0
+#define DL_4CH_CH0_DATA_MASK                                  0xffffffff
+#define DL_4CH_CH0_DATA_MASK_SFT                              (0xffffffff << 0)
+
+/* AFE_DL_4CH_CH1_MON */
+#define DL_4CH_CH1_DATA_SFT                                   0
+#define DL_4CH_CH1_DATA_MASK                                  0xffffffff
+#define DL_4CH_CH1_DATA_MASK_SFT                              (0xffffffff << 0)
+
+/* AFE_DL_4CH_CH2_MON */
+#define DL_4CH_CH2_DATA_SFT                                   0
+#define DL_4CH_CH2_DATA_MASK                                  0xffffffff
+#define DL_4CH_CH2_DATA_MASK_SFT                              (0xffffffff << 0)
+
+/* AFE_DL_4CH_CH3_MON */
+#define DL_4CH_CH3_DATA_SFT                                   0
+#define DL_4CH_CH3_DATA_MASK                                  0xffffffff
+#define DL_4CH_CH3_DATA_MASK_SFT                              (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH0_MON */
+#define DL_24CH_CH0_DATA_SFT                                  0
+#define DL_24CH_CH0_DATA_MASK                                 0xffffffff
+#define DL_24CH_CH0_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH1_MON */
+#define DL_24CH_CH1_DATA_SFT                                  0
+#define DL_24CH_CH1_DATA_MASK                                 0xffffffff
+#define DL_24CH_CH1_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH2_MON */
+#define DL_24CH_CH2_DATA_SFT                                  0
+#define DL_24CH_CH2_DATA_MASK                                 0xffffffff
+#define DL_24CH_CH2_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH3_MON */
+#define DL_24CH_CH3_DATA_SFT                                  0
+#define DL_24CH_CH3_DATA_MASK                                 0xffffffff
+#define DL_24CH_CH3_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH4_MON */
+#define DL_24CH_CH4_DATA_SFT                                  0
+#define DL_24CH_CH4_DATA_MASK                                 0xffffffff
+#define DL_24CH_CH4_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH5_MON */
+#define DL_24CH_CH5_DATA_SFT                                  0
+#define DL_24CH_CH5_DATA_MASK                                 0xffffffff
+#define DL_24CH_CH5_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH6_MON */
+#define DL_24CH_CH6_DATA_SFT                                  0
+#define DL_24CH_CH6_DATA_MASK                                 0xffffffff
+#define DL_24CH_CH6_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH7_MON */
+#define DL_24CH_CH7_DATA_SFT                                  0
+#define DL_24CH_CH7_DATA_MASK                                 0xffffffff
+#define DL_24CH_CH7_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH8_MON */
+#define DL_24CH_CH8_DATA_SFT                                  0
+#define DL_24CH_CH8_DATA_MASK                                 0xffffffff
+#define DL_24CH_CH8_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH9_MON */
+#define DL_24CH_CH9_DATA_SFT                                  0
+#define DL_24CH_CH9_DATA_MASK                                 0xffffffff
+#define DL_24CH_CH9_DATA_MASK_SFT                             (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH10_MON */
+#define DL_24CH_CH10_DATA_SFT                                 0
+#define DL_24CH_CH10_DATA_MASK                                0xffffffff
+#define DL_24CH_CH10_DATA_MASK_SFT                            (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH11_MON */
+#define DL_24CH_CH11_DATA_SFT                                 0
+#define DL_24CH_CH11_DATA_MASK                                0xffffffff
+#define DL_24CH_CH11_DATA_MASK_SFT                            (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH12_MON */
+#define DL_24CH_CH12_DATA_SFT                                 0
+#define DL_24CH_CH12_DATA_MASK                                0xffffffff
+#define DL_24CH_CH12_DATA_MASK_SFT                            (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH13_MON */
+#define DL_24CH_CH13_DATA_SFT                                 0
+#define DL_24CH_CH13_DATA_MASK                                0xffffffff
+#define DL_24CH_CH13_DATA_MASK_SFT                            (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH14_MON */
+#define DL_24CH_CH14_DATA_SFT                                 0
+#define DL_24CH_CH14_DATA_MASK                                0xffffffff
+#define DL_24CH_CH14_DATA_MASK_SFT                            (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH15_MON */
+#define DL_24CH_CH15_DATA_SFT                                 0
+#define DL_24CH_CH15_DATA_MASK                                0xffffffff
+#define DL_24CH_CH15_DATA_MASK_SFT                            (0xffffffff << 0)
+
+/* AFE_SRAM_BOUND */
+#define SECURE_BIT_SFT                                        19
+#define SECURE_BIT_MASK                                       0x1
+#define SECURE_BIT_MASK_SFT                                   (0x1 << 19)
+#define SECURE_SRAM_BOUND_SFT                                 0
+#define SECURE_SRAM_BOUND_MASK                                0x7ffff
+#define SECURE_SRAM_BOUND_MASK_SFT                            (0x7ffff << 0)
+
+/* AFE_SECURE_CON0 */
+#define READ_EN15_NS_SFT                                      31
+#define READ_EN15_NS_MASK                                     0x1
+#define READ_EN15_NS_MASK_SFT                                 (0x1 << 31)
+#define WRITE_EN15_NS_SFT                                     30
+#define WRITE_EN15_NS_MASK                                    0x1
+#define WRITE_EN15_NS_MASK_SFT                                (0x1 << 30)
+#define READ_EN14_NS_SFT                                      29
+#define READ_EN14_NS_MASK                                     0x1
+#define READ_EN14_NS_MASK_SFT                                 (0x1 << 29)
+#define WRITE_EN14_NS_SFT                                     28
+#define WRITE_EN14_NS_MASK                                    0x1
+#define WRITE_EN14_NS_MASK_SFT                                (0x1 << 28)
+#define READ_EN13_NS_SFT                                      27
+#define READ_EN13_NS_MASK                                     0x1
+#define READ_EN13_NS_MASK_SFT                                 (0x1 << 27)
+#define WRITE_EN13_NS_SFT                                     26
+#define WRITE_EN13_NS_MASK                                    0x1
+#define WRITE_EN13_NS_MASK_SFT                                (0x1 << 26)
+#define READ_EN12_NS_SFT                                      25
+#define READ_EN12_NS_MASK                                     0x1
+#define READ_EN12_NS_MASK_SFT                                 (0x1 << 25)
+#define WRITE_EN12_NS_SFT                                     24
+#define WRITE_EN12_NS_MASK                                    0x1
+#define WRITE_EN12_NS_MASK_SFT                                (0x1 << 24)
+#define READ_EN11_NS_SFT                                      23
+#define READ_EN11_NS_MASK                                     0x1
+#define READ_EN11_NS_MASK_SFT                                 (0x1 << 23)
+#define WRITE_EN11_NS_SFT                                     22
+#define WRITE_EN11_NS_MASK                                    0x1
+#define WRITE_EN11_NS_MASK_SFT                                (0x1 << 22)
+#define READ_EN10_NS_SFT                                      21
+#define READ_EN10_NS_MASK                                     0x1
+#define READ_EN10_NS_MASK_SFT                                 (0x1 << 21)
+#define WRITE_EN10_NS_SFT                                     20
+#define WRITE_EN10_NS_MASK                                    0x1
+#define WRITE_EN10_NS_MASK_SFT                                (0x1 << 20)
+#define READ_EN9_NS_SFT                                       19
+#define READ_EN9_NS_MASK                                      0x1
+#define READ_EN9_NS_MASK_SFT                                  (0x1 << 19)
+#define WRITE_EN9_NS_SFT                                      18
+#define WRITE_EN9_NS_MASK                                     0x1
+#define WRITE_EN9_NS_MASK_SFT                                 (0x1 << 18)
+#define READ_EN8_NS_SFT                                       17
+#define READ_EN8_NS_MASK                                      0x1
+#define READ_EN8_NS_MASK_SFT                                  (0x1 << 17)
+#define WRITE_EN8_NS_SFT                                      16
+#define WRITE_EN8_NS_MASK                                     0x1
+#define WRITE_EN8_NS_MASK_SFT                                 (0x1 << 16)
+#define READ_EN7_NS_SFT                                       15
+#define READ_EN7_NS_MASK                                      0x1
+#define READ_EN7_NS_MASK_SFT                                  (0x1 << 15)
+#define WRITE_EN7_NS_SFT                                      14
+#define WRITE_EN7_NS_MASK                                     0x1
+#define WRITE_EN7_NS_MASK_SFT                                 (0x1 << 14)
+#define READ_EN6_NS_SFT                                       13
+#define READ_EN6_NS_MASK                                      0x1
+#define READ_EN6_NS_MASK_SFT                                  (0x1 << 13)
+#define WRITE_EN6_NS_SFT                                      12
+#define WRITE_EN6_NS_MASK                                     0x1
+#define WRITE_EN6_NS_MASK_SFT                                 (0x1 << 12)
+#define READ_EN5_NS_SFT                                       11
+#define READ_EN5_NS_MASK                                      0x1
+#define READ_EN5_NS_MASK_SFT                                  (0x1 << 11)
+#define WRITE_EN5_NS_SFT                                      10
+#define WRITE_EN5_NS_MASK                                     0x1
+#define WRITE_EN5_NS_MASK_SFT                                 (0x1 << 10)
+#define READ_EN4_NS_SFT                                       9
+#define READ_EN4_NS_MASK                                      0x1
+#define READ_EN4_NS_MASK_SFT                                  (0x1 << 9)
+#define WRITE_EN4_NS_SFT                                      8
+#define WRITE_EN4_NS_MASK                                     0x1
+#define WRITE_EN4_NS_MASK_SFT                                 (0x1 << 8)
+#define READ_EN3_NS_SFT                                       7
+#define READ_EN3_NS_MASK                                      0x1
+#define READ_EN3_NS_MASK_SFT                                  (0x1 << 7)
+#define WRITE_EN3_NS_SFT                                      6
+#define WRITE_EN3_NS_MASK                                     0x1
+#define WRITE_EN3_NS_MASK_SFT                                 (0x1 << 6)
+#define READ_EN2_NS_SFT                                       5
+#define READ_EN2_NS_MASK                                      0x1
+#define READ_EN2_NS_MASK_SFT                                  (0x1 << 5)
+#define WRITE_EN2_NS_SFT                                      4
+#define WRITE_EN2_NS_MASK                                     0x1
+#define WRITE_EN2_NS_MASK_SFT                                 (0x1 << 4)
+#define READ_EN1_NS_SFT                                       3
+#define READ_EN1_NS_MASK                                      0x1
+#define READ_EN1_NS_MASK_SFT                                  (0x1 << 3)
+#define WRITE_EN1_NS_SFT                                      2
+#define WRITE_EN1_NS_MASK                                     0x1
+#define WRITE_EN1_NS_MASK_SFT                                 (0x1 << 2)
+#define READ_EN0_NS_SFT                                       1
+#define READ_EN0_NS_MASK                                      0x1
+#define READ_EN0_NS_MASK_SFT                                  (0x1 << 1)
+#define WRITE_EN0_NS_SFT                                      0
+#define WRITE_EN0_NS_MASK                                     0x1
+#define WRITE_EN0_NS_MASK_SFT                                 (0x1 << 0)
+
+/* AFE_SECURE_CON1 */
+#define READ_EN15_S_SFT                                       31
+#define READ_EN15_S_MASK                                      0x1
+#define READ_EN15_S_MASK_SFT                                  (0x1 << 31)
+#define WRITE_EN15_S_SFT                                      30
+#define WRITE_EN15_S_MASK                                     0x1
+#define WRITE_EN15_S_MASK_SFT                                 (0x1 << 30)
+#define READ_EN14_S_SFT                                       29
+#define READ_EN14_S_MASK                                      0x1
+#define READ_EN14_S_MASK_SFT                                  (0x1 << 29)
+#define WRITE_EN14_S_SFT                                      28
+#define WRITE_EN14_S_MASK                                     0x1
+#define WRITE_EN14_S_MASK_SFT                                 (0x1 << 28)
+#define READ_EN13_S_SFT                                       27
+#define READ_EN13_S_MASK                                      0x1
+#define READ_EN13_S_MASK_SFT                                  (0x1 << 27)
+#define WRITE_EN13_S_SFT                                      26
+#define WRITE_EN13_S_MASK                                     0x1
+#define WRITE_EN13_S_MASK_SFT                                 (0x1 << 26)
+#define READ_EN12_S_SFT                                       25
+#define READ_EN12_S_MASK                                      0x1
+#define READ_EN12_S_MASK_SFT                                  (0x1 << 25)
+#define WRITE_EN12_S_SFT                                      24
+#define WRITE_EN12_S_MASK                                     0x1
+#define WRITE_EN12_S_MASK_SFT                                 (0x1 << 24)
+#define READ_EN11_S_SFT                                       23
+#define READ_EN11_S_MASK                                      0x1
+#define READ_EN11_S_MASK_SFT                                  (0x1 << 23)
+#define WRITE_EN11_S_SFT                                      22
+#define WRITE_EN11_S_MASK                                     0x1
+#define WRITE_EN11_S_MASK_SFT                                 (0x1 << 22)
+#define READ_EN10_S_SFT                                       21
+#define READ_EN10_S_MASK                                      0x1
+#define READ_EN10_S_MASK_SFT                                  (0x1 << 21)
+#define WRITE_EN10_S_SFT                                      20
+#define WRITE_EN10_S_MASK                                     0x1
+#define WRITE_EN10_S_MASK_SFT                                 (0x1 << 20)
+#define READ_EN9_S_SFT                                        19
+#define READ_EN9_S_MASK                                       0x1
+#define READ_EN9_S_MASK_SFT                                   (0x1 << 19)
+#define WRITE_EN9_S_SFT                                       18
+#define WRITE_EN9_S_MASK                                      0x1
+#define WRITE_EN9_S_MASK_SFT                                  (0x1 << 18)
+#define READ_EN8_S_SFT                                        17
+#define READ_EN8_S_MASK                                       0x1
+#define READ_EN8_S_MASK_SFT                                   (0x1 << 17)
+#define WRITE_EN8_S_SFT                                       16
+#define WRITE_EN8_S_MASK                                      0x1
+#define WRITE_EN8_S_MASK_SFT                                  (0x1 << 16)
+#define READ_EN7_S_SFT                                        15
+#define READ_EN7_S_MASK                                       0x1
+#define READ_EN7_S_MASK_SFT                                   (0x1 << 15)
+#define WRITE_EN7_S_SFT                                       14
+#define WRITE_EN7_S_MASK                                      0x1
+#define WRITE_EN7_S_MASK_SFT                                  (0x1 << 14)
+#define READ_EN6_S_SFT                                        13
+#define READ_EN6_S_MASK                                       0x1
+#define READ_EN6_S_MASK_SFT                                   (0x1 << 13)
+#define WRITE_EN6_S_SFT                                       12
+#define WRITE_EN6_S_MASK                                      0x1
+#define WRITE_EN6_S_MASK_SFT                                  (0x1 << 12)
+#define READ_EN5_S_SFT                                        11
+#define READ_EN5_S_MASK                                       0x1
+#define READ_EN5_S_MASK_SFT                                   (0x1 << 11)
+#define WRITE_EN5_S_SFT                                       10
+#define WRITE_EN5_S_MASK                                      0x1
+#define WRITE_EN5_S_MASK_SFT                                  (0x1 << 10)
+#define READ_EN4_S_SFT                                        9
+#define READ_EN4_S_MASK                                       0x1
+#define READ_EN4_S_MASK_SFT                                   (0x1 << 9)
+#define WRITE_EN4_S_SFT                                       8
+#define WRITE_EN4_S_MASK                                      0x1
+#define WRITE_EN4_S_MASK_SFT                                  (0x1 << 8)
+#define READ_EN3_S_SFT                                        7
+#define READ_EN3_S_MASK                                       0x1
+#define READ_EN3_S_MASK_SFT                                   (0x1 << 7)
+#define WRITE_EN3_S_SFT                                       6
+#define WRITE_EN3_S_MASK                                      0x1
+#define WRITE_EN3_S_MASK_SFT                                  (0x1 << 6)
+#define READ_EN2_S_SFT                                        5
+#define READ_EN2_S_MASK                                       0x1
+#define READ_EN2_S_MASK_SFT                                   (0x1 << 5)
+#define WRITE_EN2_S_SFT                                       4
+#define WRITE_EN2_S_MASK                                      0x1
+#define WRITE_EN2_S_MASK_SFT                                  (0x1 << 4)
+#define READ_EN1_S_SFT                                        3
+#define READ_EN1_S_MASK                                       0x1
+#define READ_EN1_S_MASK_SFT                                   (0x1 << 3)
+#define WRITE_EN1_S_SFT                                       2
+#define WRITE_EN1_S_MASK                                      0x1
+#define WRITE_EN1_S_MASK_SFT                                  (0x1 << 2)
+#define READ_EN0_S_SFT                                        1
+#define READ_EN0_S_MASK                                       0x1
+#define READ_EN0_S_MASK_SFT                                   (0x1 << 1)
+#define WRITE_EN0_S_SFT                                       0
+#define WRITE_EN0_S_MASK                                      0x1
+#define WRITE_EN0_S_MASK_SFT                                  (0x1 << 0)
+
+/* AFE_SE_SECURE_CON0 */
+#define AFE_HDMI_SE_SECURE_BIT_SFT                            11
+#define AFE_HDMI_SE_SECURE_BIT_MASK                           0x1
+#define AFE_HDMI_SE_SECURE_BIT_MASK_SFT                       (0x1 << 11)
+#define AFE_SPDIF2_OUT_SE_SECURE_BIT_SFT                      10
+#define AFE_SPDIF2_OUT_SE_SECURE_BIT_MASK                     0x1
+#define AFE_SPDIF2_OUT_SE_SECURE_BIT_MASK_SFT                 (0x1 << 10)
+#define AFE_SPDIF_OUT_SE_SECURE_BIT_SFT                       9
+#define AFE_SPDIF_OUT_SE_SECURE_BIT_MASK                      0x1
+#define AFE_SPDIF_OUT_SE_SECURE_BIT_MASK_SFT                  (0x1 << 9)
+#define AFE_DL8_SE_SECURE_BIT_SFT                             8
+#define AFE_DL8_SE_SECURE_BIT_MASK                            0x1
+#define AFE_DL8_SE_SECURE_BIT_MASK_SFT                        (0x1 << 8)
+#define AFE_DL7_SE_SECURE_BIT_SFT                             7
+#define AFE_DL7_SE_SECURE_BIT_MASK                            0x1
+#define AFE_DL7_SE_SECURE_BIT_MASK_SFT                        (0x1 << 7)
+#define AFE_DL6_SE_SECURE_BIT_SFT                             6
+#define AFE_DL6_SE_SECURE_BIT_MASK                            0x1
+#define AFE_DL6_SE_SECURE_BIT_MASK_SFT                        (0x1 << 6)
+#define AFE_DL5_SE_SECURE_BIT_SFT                             5
+#define AFE_DL5_SE_SECURE_BIT_MASK                            0x1
+#define AFE_DL5_SE_SECURE_BIT_MASK_SFT                        (0x1 << 5)
+#define AFE_DL4_SE_SECURE_BIT_SFT                             4
+#define AFE_DL4_SE_SECURE_BIT_MASK                            0x1
+#define AFE_DL4_SE_SECURE_BIT_MASK_SFT                        (0x1 << 4)
+#define AFE_DL3_SE_SECURE_BIT_SFT                             3
+#define AFE_DL3_SE_SECURE_BIT_MASK                            0x1
+#define AFE_DL3_SE_SECURE_BIT_MASK_SFT                        (0x1 << 3)
+#define AFE_DL2_SE_SECURE_BIT_SFT                             2
+#define AFE_DL2_SE_SECURE_BIT_MASK                            0x1
+#define AFE_DL2_SE_SECURE_BIT_MASK_SFT                        (0x1 << 2)
+#define AFE_DL1_SE_SECURE_BIT_SFT                             1
+#define AFE_DL1_SE_SECURE_BIT_MASK                            0x1
+#define AFE_DL1_SE_SECURE_BIT_MASK_SFT                        (0x1 << 1)
+#define AFE_DL0_SE_SECURE_BIT_SFT                             0
+#define AFE_DL0_SE_SECURE_BIT_MASK                            0x1
+#define AFE_DL0_SE_SECURE_BIT_MASK_SFT                        (0x1 << 0)
+
+/* AFE_SE_SECURE_CON1 */
+#define AFE_DL46_SE_SECURE_BIT_SFT                            26
+#define AFE_DL46_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL46_SE_SECURE_BIT_MASK_SFT                       (0x1 << 26)
+#define AFE_DL45_SE_SECURE_BIT_SFT                            25
+#define AFE_DL45_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL45_SE_SECURE_BIT_MASK_SFT                       (0x1 << 25)
+#define AFE_DL44_SE_SECURE_BIT_SFT                            24
+#define AFE_DL44_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL44_SE_SECURE_BIT_MASK_SFT                       (0x1 << 24)
+#define AFE_DL43_SE_SECURE_BIT_SFT                            23
+#define AFE_DL43_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL43_SE_SECURE_BIT_MASK_SFT                       (0x1 << 23)
+#define AFE_DL42_SE_SECURE_BIT_SFT                            22
+#define AFE_DL42_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL42_SE_SECURE_BIT_MASK_SFT                       (0x1 << 22)
+#define AFE_DL41_SE_SECURE_BIT_SFT                            21
+#define AFE_DL41_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL41_SE_SECURE_BIT_MASK_SFT                       (0x1 << 21)
+#define AFE_DL40_SE_SECURE_BIT_SFT                            20
+#define AFE_DL40_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL40_SE_SECURE_BIT_MASK_SFT                       (0x1 << 20)
+#define AFE_DL39_SE_SECURE_BIT_SFT                            19
+#define AFE_DL39_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL39_SE_SECURE_BIT_MASK_SFT                       (0x1 << 19)
+#define AFE_DL38_SE_SECURE_BIT_SFT                            18
+#define AFE_DL38_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL38_SE_SECURE_BIT_MASK_SFT                       (0x1 << 18)
+#define AFE_DL37_SE_SECURE_BIT_SFT                            17
+#define AFE_DL37_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL37_SE_SECURE_BIT_MASK_SFT                       (0x1 << 17)
+#define AFE_DL36_SE_SECURE_BIT_SFT                            16
+#define AFE_DL36_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL36_SE_SECURE_BIT_MASK_SFT                       (0x1 << 16)
+#define AFE_DL35_SE_SECURE_BIT_SFT                            15
+#define AFE_DL35_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL35_SE_SECURE_BIT_MASK_SFT                       (0x1 << 15)
+#define AFE_DL34_SE_SECURE_BIT_SFT                            14
+#define AFE_DL34_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL34_SE_SECURE_BIT_MASK_SFT                       (0x1 << 14)
+#define AFE_DL33_SE_SECURE_BIT_SFT                            13
+#define AFE_DL33_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL33_SE_SECURE_BIT_MASK_SFT                       (0x1 << 13)
+#define AFE_DL32_SE_SECURE_BIT_SFT                            12
+#define AFE_DL32_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL32_SE_SECURE_BIT_MASK_SFT                       (0x1 << 12)
+#define AFE_DL31_SE_SECURE_BIT_SFT                            11
+#define AFE_DL31_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL31_SE_SECURE_BIT_MASK_SFT                       (0x1 << 11)
+#define AFE_DL30_SE_SECURE_BIT_SFT                            10
+#define AFE_DL30_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL30_SE_SECURE_BIT_MASK_SFT                       (0x1 << 10)
+#define AFE_DL29_SE_SECURE_BIT_SFT                            9
+#define AFE_DL29_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL29_SE_SECURE_BIT_MASK_SFT                       (0x1 << 9)
+#define AFE_DL28_SE_SECURE_BIT_SFT                            8
+#define AFE_DL28_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL28_SE_SECURE_BIT_MASK_SFT                       (0x1 << 8)
+#define AFE_DL27_SE_SECURE_BIT_SFT                            7
+#define AFE_DL27_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL27_SE_SECURE_BIT_MASK_SFT                       (0x1 << 7)
+#define AFE_DL26_SE_SECURE_BIT_SFT                            6
+#define AFE_DL26_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL26_SE_SECURE_BIT_MASK_SFT                       (0x1 << 6)
+#define AFE_DL25_SE_SECURE_BIT_SFT                            5
+#define AFE_DL25_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL25_SE_SECURE_BIT_MASK_SFT                       (0x1 << 5)
+#define AFE_DL24_SE_SECURE_BIT_SFT                            4
+#define AFE_DL24_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL24_SE_SECURE_BIT_MASK_SFT                       (0x1 << 4)
+#define AFE_DL23_SE_SECURE_BIT_SFT                            3
+#define AFE_DL23_SE_SECURE_BIT_MASK                           0x1
+#define AFE_DL23_SE_SECURE_BIT_MASK_SFT                       (0x1 << 3)
+#define AFE_DL_48CH_SE_SECURE_BIT_SFT                         2
+#define AFE_DL_48CH_SE_SECURE_BIT_MASK                        0x1
+#define AFE_DL_48CH_SE_SECURE_BIT_MASK_SFT                    (0x1 << 2)
+#define AFE_DL_24CH_SE_SECURE_BIT_SFT                         1
+#define AFE_DL_24CH_SE_SECURE_BIT_MASK                        0x1
+#define AFE_DL_24CH_SE_SECURE_BIT_MASK_SFT                    (0x1 << 1)
+#define AFE_DL_4CH_SE_SECURE_BIT_SFT                          0
+#define AFE_DL_4CH_SE_SECURE_BIT_MASK                         0x1
+#define AFE_DL_4CH_SE_SECURE_BIT_MASK_SFT                     (0x1 << 0)
+
+/* AFE_SE_SECURE_CON2 */
+#define AFE_VUL38_SE_SECURE_BIT_SFT                           28
+#define AFE_VUL38_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL38_SE_SECURE_BIT_MASK_SFT                      (0x1 << 28)
+#define AFE_VUL37_SE_SECURE_BIT_SFT                           27
+#define AFE_VUL37_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL37_SE_SECURE_BIT_MASK_SFT                      (0x1 << 27)
+#define AFE_VUL36_SE_SECURE_BIT_SFT                           26
+#define AFE_VUL36_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL36_SE_SECURE_BIT_MASK_SFT                      (0x1 << 26)
+#define AFE_VUL35_SE_SECURE_BIT_SFT                           25
+#define AFE_VUL35_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL35_SE_SECURE_BIT_MASK_SFT                      (0x1 << 25)
+#define AFE_VUL34_SE_SECURE_BIT_SFT                           24
+#define AFE_VUL34_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL34_SE_SECURE_BIT_MASK_SFT                      (0x1 << 24)
+#define AFE_VUL33_SE_SECURE_BIT_SFT                           23
+#define AFE_VUL33_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL33_SE_SECURE_BIT_MASK_SFT                      (0x1 << 23)
+#define AFE_VUL32_SE_SECURE_BIT_SFT                           22
+#define AFE_VUL32_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL32_SE_SECURE_BIT_MASK_SFT                      (0x1 << 22)
+#define AFE_VUL31_SE_SECURE_BIT_SFT                           21
+#define AFE_VUL31_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL31_SE_SECURE_BIT_MASK_SFT                      (0x1 << 21)
+#define AFE_VUL30_SE_SECURE_BIT_SFT                           20
+#define AFE_VUL30_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL30_SE_SECURE_BIT_MASK_SFT                      (0x1 << 20)
+#define AFE_VUL29_SE_SECURE_BIT_SFT                           19
+#define AFE_VUL29_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL29_SE_SECURE_BIT_MASK_SFT                      (0x1 << 19)
+#define AFE_VUL28_SE_SECURE_BIT_SFT                           18
+#define AFE_VUL28_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL28_SE_SECURE_BIT_MASK_SFT                      (0x1 << 18)
+#define AFE_VUL27_SE_SECURE_BIT_SFT                           17
+#define AFE_VUL27_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL27_SE_SECURE_BIT_MASK_SFT                      (0x1 << 17)
+#define AFE_VUL26_SE_SECURE_BIT_SFT                           16
+#define AFE_VUL26_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL26_SE_SECURE_BIT_MASK_SFT                      (0x1 << 16)
+#define AFE_VUL25_SE_SECURE_BIT_SFT                           15
+#define AFE_VUL25_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL25_SE_SECURE_BIT_MASK_SFT                      (0x1 << 15)
+#define AFE_VUL24_SE_SECURE_BIT_SFT                           14
+#define AFE_VUL24_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL24_SE_SECURE_BIT_MASK_SFT                      (0x1 << 14)
+#define AFE_VUL_CM2_SE_SECURE_BIT_SFT                         13
+#define AFE_VUL_CM2_SE_SECURE_BIT_MASK                        0x1
+#define AFE_VUL_CM2_SE_SECURE_BIT_MASK_SFT                    (0x1 << 13)
+#define AFE_VUL_CM1_SE_SECURE_BIT_SFT                         12
+#define AFE_VUL_CM1_SE_SECURE_BIT_MASK                        0x1
+#define AFE_VUL_CM1_SE_SECURE_BIT_MASK_SFT                    (0x1 << 12)
+#define AFE_VUL_CM0_SE_SECURE_BIT_SFT                         11
+#define AFE_VUL_CM0_SE_SECURE_BIT_MASK                        0x1
+#define AFE_VUL_CM0_SE_SECURE_BIT_MASK_SFT                    (0x1 << 11)
+#define AFE_VUL10_SE_SECURE_BIT_SFT                           10
+#define AFE_VUL10_SE_SECURE_BIT_MASK                          0x1
+#define AFE_VUL10_SE_SECURE_BIT_MASK_SFT                      (0x1 << 10)
+#define AFE_VUL9_SE_SECURE_BIT_SFT                            9
+#define AFE_VUL9_SE_SECURE_BIT_MASK                           0x1
+#define AFE_VUL9_SE_SECURE_BIT_MASK_SFT                       (0x1 << 9)
+#define AFE_VUL8_SE_SECURE_BIT_SFT                            8
+#define AFE_VUL8_SE_SECURE_BIT_MASK                           0x1
+#define AFE_VUL8_SE_SECURE_BIT_MASK_SFT                       (0x1 << 8)
+#define AFE_VUL7_SE_SECURE_BIT_SFT                            7
+#define AFE_VUL7_SE_SECURE_BIT_MASK                           0x1
+#define AFE_VUL7_SE_SECURE_BIT_MASK_SFT                       (0x1 << 7)
+#define AFE_VUL6_SE_SECURE_BIT_SFT                            6
+#define AFE_VUL6_SE_SECURE_BIT_MASK                           0x1
+#define AFE_VUL6_SE_SECURE_BIT_MASK_SFT                       (0x1 << 6)
+#define AFE_VUL5_SE_SECURE_BIT_SFT                            5
+#define AFE_VUL5_SE_SECURE_BIT_MASK                           0x1
+#define AFE_VUL5_SE_SECURE_BIT_MASK_SFT                       (0x1 << 5)
+#define AFE_VUL4_SE_SECURE_BIT_SFT                            4
+#define AFE_VUL4_SE_SECURE_BIT_MASK                           0x1
+#define AFE_VUL4_SE_SECURE_BIT_MASK_SFT                       (0x1 << 4)
+#define AFE_VUL3_SE_SECURE_BIT_SFT                            3
+#define AFE_VUL3_SE_SECURE_BIT_MASK                           0x1
+#define AFE_VUL3_SE_SECURE_BIT_MASK_SFT                       (0x1 << 3)
+#define AFE_VUL2_SE_SECURE_BIT_SFT                            2
+#define AFE_VUL2_SE_SECURE_BIT_MASK                           0x1
+#define AFE_VUL2_SE_SECURE_BIT_MASK_SFT                       (0x1 << 2)
+#define AFE_VUL1_SE_SECURE_BIT_SFT                            1
+#define AFE_VUL1_SE_SECURE_BIT_MASK                           0x1
+#define AFE_VUL1_SE_SECURE_BIT_MASK_SFT                       (0x1 << 1)
+#define AFE_VUL0_SE_SECURE_BIT_SFT                            0
+#define AFE_VUL0_SE_SECURE_BIT_MASK                           0x1
+#define AFE_VUL0_SE_SECURE_BIT_MASK_SFT                       (0x1 << 0)
+
+/* AFE_SE_SECURE_CON3 */
+#define AFE_SPDIFIN_SE_SECURE_BIT_SFT                         10
+#define AFE_SPDIFIN_SE_SECURE_BIT_MASK                        0x1
+#define AFE_SPDIFIN_SE_SECURE_BIT_MASK_SFT                    (0x1 << 10)
+#define AFE_TDM_IN_SE_SECURE_BIT_SFT                          9
+#define AFE_TDM_IN_SE_SECURE_BIT_MASK                         0x1
+#define AFE_TDM_IN_SE_SECURE_BIT_MASK_SFT                     (0x1 << 9)
+#define AFE_MPHONE_EARC_SE_SECURE_BIT_SFT                     8
+#define AFE_MPHONE_EARC_SE_SECURE_BIT_MASK                    0x1
+#define AFE_MPHONE_EARC_SE_SECURE_BIT_MASK_SFT                (0x1 << 8)
+#define AFE_MPHONE_SPDIF_SE_SECURE_BIT_SFT                    7
+#define AFE_MPHONE_SPDIF_SE_SECURE_BIT_MASK                   0x1
+#define AFE_MPHONE_SPDIF_SE_SECURE_BIT_MASK_SFT               (0x1 << 7)
+#define AFE_ETDM_IN6_SE_SECURE_BIT_SFT                        6
+#define AFE_ETDM_IN6_SE_SECURE_BIT_MASK                       0x1
+#define AFE_ETDM_IN6_SE_SECURE_BIT_MASK_SFT                   (0x1 << 6)
+#define AFE_ETDM_IN5_SE_SECURE_BIT_SFT                        5
+#define AFE_ETDM_IN5_SE_SECURE_BIT_MASK                       0x1
+#define AFE_ETDM_IN5_SE_SECURE_BIT_MASK_SFT                   (0x1 << 5)
+#define AFE_ETDM_IN4_SE_SECURE_BIT_SFT                        4
+#define AFE_ETDM_IN4_SE_SECURE_BIT_MASK                       0x1
+#define AFE_ETDM_IN4_SE_SECURE_BIT_MASK_SFT                   (0x1 << 4)
+#define AFE_ETDM_IN3_SE_SECURE_BIT_SFT                        3
+#define AFE_ETDM_IN3_SE_SECURE_BIT_MASK                       0x1
+#define AFE_ETDM_IN3_SE_SECURE_BIT_MASK_SFT                   (0x1 << 3)
+#define AFE_ETDM_IN2_SE_SECURE_BIT_SFT                        2
+#define AFE_ETDM_IN2_SE_SECURE_BIT_MASK                       0x1
+#define AFE_ETDM_IN2_SE_SECURE_BIT_MASK_SFT                   (0x1 << 2)
+#define AFE_ETDM_IN1_SE_SECURE_BIT_SFT                        1
+#define AFE_ETDM_IN1_SE_SECURE_BIT_MASK                       0x1
+#define AFE_ETDM_IN1_SE_SECURE_BIT_MASK_SFT                   (0x1 << 1)
+#define AFE_ETDM_IN0_SE_SECURE_BIT_SFT                        0
+#define AFE_ETDM_IN0_SE_SECURE_BIT_MASK                       0x1
+#define AFE_ETDM_IN0_SE_SECURE_BIT_MASK_SFT                   (0x1 << 0)
+
+/* AFE_SE_PROT_SIDEBAND0 */
+#define HDMI_HPROT_SFT                                        11
+#define HDMI_HPROT_MASK                                       0x1
+#define HDMI_HPROT_MASK_SFT                                   (0x1 << 11)
+#define SPDIF2_OUT_HPROT_SFT                                  10
+#define SPDIF2_OUT_HPROT_MASK                                 0x1
+#define SPDIF2_OUT_HPROT_MASK_SFT                             (0x1 << 10)
+#define SPDIF_OUT_HPROT_SFT                                   9
+#define SPDIF_OUT_HPROT_MASK                                  0x1
+#define SPDIF_OUT_HPROT_MASK_SFT                              (0x1 << 9)
+#define DL8_HPROT_SFT                                         8
+#define DL8_HPROT_MASK                                        0x1
+#define DL8_HPROT_MASK_SFT                                    (0x1 << 8)
+#define DL7_HPROT_SFT                                         7
+#define DL7_HPROT_MASK                                        0x1
+#define DL7_HPROT_MASK_SFT                                    (0x1 << 7)
+#define DL6_HPROT_SFT                                         6
+#define DL6_HPROT_MASK                                        0x1
+#define DL6_HPROT_MASK_SFT                                    (0x1 << 6)
+#define DL5_HPROT_SFT                                         5
+#define DL5_HPROT_MASK                                        0x1
+#define DL5_HPROT_MASK_SFT                                    (0x1 << 5)
+#define DL4_HPROT_SFT                                         4
+#define DL4_HPROT_MASK                                        0x1
+#define DL4_HPROT_MASK_SFT                                    (0x1 << 4)
+#define DL3_HPROT_SFT                                         3
+#define DL3_HPROT_MASK                                        0x1
+#define DL3_HPROT_MASK_SFT                                    (0x1 << 3)
+#define DL2_HPROT_SFT                                         2
+#define DL2_HPROT_MASK                                        0x1
+#define DL2_HPROT_MASK_SFT                                    (0x1 << 2)
+#define DL1_HPROT_SFT                                         1
+#define DL1_HPROT_MASK                                        0x1
+#define DL1_HPROT_MASK_SFT                                    (0x1 << 1)
+#define DL0_HPROT_SFT                                         0
+#define DL0_HPROT_MASK                                        0x1
+#define DL0_HPROT_MASK_SFT                                    (0x1 << 0)
+
+/* AFE_SE_PROT_SIDEBAND1 */
+#define DL46_HPROT_SFT                                        26
+#define DL46_HPROT_MASK                                       0x1
+#define DL46_HPROT_MASK_SFT                                   (0x1 << 26)
+#define DL45_HPROT_SFT                                        25
+#define DL45_HPROT_MASK                                       0x1
+#define DL45_HPROT_MASK_SFT                                   (0x1 << 25)
+#define DL44_HPROT_SFT                                        24
+#define DL44_HPROT_MASK                                       0x1
+#define DL44_HPROT_MASK_SFT                                   (0x1 << 24)
+#define DL43_HPROT_SFT                                        23
+#define DL43_HPROT_MASK                                       0x1
+#define DL43_HPROT_MASK_SFT                                   (0x1 << 23)
+#define DL42_HPROT_SFT                                        22
+#define DL42_HPROT_MASK                                       0x1
+#define DL42_HPROT_MASK_SFT                                   (0x1 << 22)
+#define DL41_HPROT_SFT                                        21
+#define DL41_HPROT_MASK                                       0x1
+#define DL41_HPROT_MASK_SFT                                   (0x1 << 21)
+#define DL40_HPROT_SFT                                        20
+#define DL40_HPROT_MASK                                       0x1
+#define DL40_HPROT_MASK_SFT                                   (0x1 << 20)
+#define DL39_HPROT_SFT                                        19
+#define DL39_HPROT_MASK                                       0x1
+#define DL39_HPROT_MASK_SFT                                   (0x1 << 19)
+#define DL38_HPROT_SFT                                        18
+#define DL38_HPROT_MASK                                       0x1
+#define DL38_HPROT_MASK_SFT                                   (0x1 << 18)
+#define DL37_HPROT_SFT                                        17
+#define DL37_HPROT_MASK                                       0x1
+#define DL37_HPROT_MASK_SFT                                   (0x1 << 17)
+#define DL36_HPROT_SFT                                        16
+#define DL36_HPROT_MASK                                       0x1
+#define DL36_HPROT_MASK_SFT                                   (0x1 << 16)
+#define DL35_HPROT_SFT                                        15
+#define DL35_HPROT_MASK                                       0x1
+#define DL35_HPROT_MASK_SFT                                   (0x1 << 15)
+#define DL34_HPROT_SFT                                        14
+#define DL34_HPROT_MASK                                       0x1
+#define DL34_HPROT_MASK_SFT                                   (0x1 << 14)
+#define DL33_HPROT_SFT                                        13
+#define DL33_HPROT_MASK                                       0x1
+#define DL33_HPROT_MASK_SFT                                   (0x1 << 13)
+#define DL32_HPROT_SFT                                        12
+#define DL32_HPROT_MASK                                       0x1
+#define DL32_HPROT_MASK_SFT                                   (0x1 << 12)
+#define DL31_HPROT_SFT                                        11
+#define DL31_HPROT_MASK                                       0x1
+#define DL31_HPROT_MASK_SFT                                   (0x1 << 11)
+#define DL30_HPROT_SFT                                        10
+#define DL30_HPROT_MASK                                       0x1
+#define DL30_HPROT_MASK_SFT                                   (0x1 << 10)
+#define DL29_HPROT_SFT                                        9
+#define DL29_HPROT_MASK                                       0x1
+#define DL29_HPROT_MASK_SFT                                   (0x1 << 9)
+#define DL28_HPROT_SFT                                        8
+#define DL28_HPROT_MASK                                       0x1
+#define DL28_HPROT_MASK_SFT                                   (0x1 << 8)
+#define DL27_HPROT_SFT                                        7
+#define DL27_HPROT_MASK                                       0x1
+#define DL27_HPROT_MASK_SFT                                   (0x1 << 7)
+#define DL26_HPROT_SFT                                        6
+#define DL26_HPROT_MASK                                       0x1
+#define DL26_HPROT_MASK_SFT                                   (0x1 << 6)
+#define DL25_HPROT_SFT                                        5
+#define DL25_HPROT_MASK                                       0x1
+#define DL25_HPROT_MASK_SFT                                   (0x1 << 5)
+#define DL24_HPROT_SFT                                        4
+#define DL24_HPROT_MASK                                       0x1
+#define DL24_HPROT_MASK_SFT                                   (0x1 << 4)
+#define DL23_HPROT_SFT                                        3
+#define DL23_HPROT_MASK                                       0x1
+#define DL23_HPROT_MASK_SFT                                   (0x1 << 3)
+#define DL_48CH_PROT_SFT                                      2
+#define DL_48CH_PROT_MASK                                     0x1
+#define DL_48CH_PROT_MASK_SFT                                 (0x1 << 2)
+#define DL_24CH_PROT_SFT                                      1
+#define DL_24CH_PROT_MASK                                     0x1
+#define DL_24CH_PROT_MASK_SFT                                 (0x1 << 1)
+#define DL_4CH_PROT_SFT                                       0
+#define DL_4CH_PROT_MASK                                      0x1
+#define DL_4CH_PROT_MASK_SFT                                  (0x1 << 0)
+
+/* AFE_SE_PROT_SIDEBAND2 */
+#define VUL38_HPROT_SFT                                       28
+#define VUL38_HPROT_MASK                                      0x1
+#define VUL38_HPROT_MASK_SFT                                  (0x1 << 28)
+#define VUL37_HPROT_SFT                                       27
+#define VUL37_HPROT_MASK                                      0x1
+#define VUL37_HPROT_MASK_SFT                                  (0x1 << 27)
+#define VUL36_HPROT_SFT                                       26
+#define VUL36_HPROT_MASK                                      0x1
+#define VUL36_HPROT_MASK_SFT                                  (0x1 << 26)
+#define VUL35_HPROT_SFT                                       25
+#define VUL35_HPROT_MASK                                      0x1
+#define VUL35_HPROT_MASK_SFT                                  (0x1 << 25)
+#define VUL34_HPROT_SFT                                       24
+#define VUL34_HPROT_MASK                                      0x1
+#define VUL34_HPROT_MASK_SFT                                  (0x1 << 24)
+#define VUL33_HPROT_SFT                                       23
+#define VUL33_HPROT_MASK                                      0x1
+#define VUL33_HPROT_MASK_SFT                                  (0x1 << 23)
+#define VUL32_HPROT_SFT                                       22
+#define VUL32_HPROT_MASK                                      0x1
+#define VUL32_HPROT_MASK_SFT                                  (0x1 << 22)
+#define VUL31_HPROT_SFT                                       21
+#define VUL31_HPROT_MASK                                      0x1
+#define VUL31_HPROT_MASK_SFT                                  (0x1 << 21)
+#define VUL30_HPROT_SFT                                       20
+#define VUL30_HPROT_MASK                                      0x1
+#define VUL30_HPROT_MASK_SFT                                  (0x1 << 20)
+#define VUL29_HPROT_SFT                                       19
+#define VUL29_HPROT_MASK                                      0x1
+#define VUL29_HPROT_MASK_SFT                                  (0x1 << 19)
+#define VUL28_HPROT_SFT                                       18
+#define VUL28_HPROT_MASK                                      0x1
+#define VUL28_HPROT_MASK_SFT                                  (0x1 << 18)
+#define VUL27_HPROT_SFT                                       17
+#define VUL27_HPROT_MASK                                      0x1
+#define VUL27_HPROT_MASK_SFT                                  (0x1 << 17)
+#define VUL26_HPROT_SFT                                       16
+#define VUL26_HPROT_MASK                                      0x1
+#define VUL26_HPROT_MASK_SFT                                  (0x1 << 16)
+#define VUL25_HPROT_SFT                                       15
+#define VUL25_HPROT_MASK                                      0x1
+#define VUL25_HPROT_MASK_SFT                                  (0x1 << 15)
+#define VUL24_HPROT_SFT                                       14
+#define VUL24_HPROT_MASK                                      0x1
+#define VUL24_HPROT_MASK_SFT                                  (0x1 << 14)
+#define VUL_CM2_HPROT_SFT                                     13
+#define VUL_CM2_HPROT_MASK                                    0x1
+#define VUL_CM2_HPROT_MASK_SFT                                (0x1 << 13)
+#define VUL_CM1_HPROT_SFT                                     12
+#define VUL_CM1_HPROT_MASK                                    0x1
+#define VUL_CM1_HPROT_MASK_SFT                                (0x1 << 12)
+#define VUL_CM0_HPROT_SFT                                     11
+#define VUL_CM0_HPROT_MASK                                    0x1
+#define VUL_CM0_HPROT_MASK_SFT                                (0x1 << 11)
+#define VUL10_HPROT_SFT                                       10
+#define VUL10_HPROT_MASK                                      0x1
+#define VUL10_HPROT_MASK_SFT                                  (0x1 << 10)
+#define VUL9_HPROT_SFT                                        9
+#define VUL9_HPROT_MASK                                       0x1
+#define VUL9_HPROT_MASK_SFT                                   (0x1 << 9)
+#define VUL8_HPROT_SFT                                        8
+#define VUL8_HPROT_MASK                                       0x1
+#define VUL8_HPROT_MASK_SFT                                   (0x1 << 8)
+#define VUL7_HPROT_SFT                                        7
+#define VUL7_HPROT_MASK                                       0x1
+#define VUL7_HPROT_MASK_SFT                                   (0x1 << 7)
+#define VUL6_HPROT_SFT                                        6
+#define VUL6_HPROT_MASK                                       0x1
+#define VUL6_HPROT_MASK_SFT                                   (0x1 << 6)
+#define VUL5_HPROT_SFT                                        5
+#define VUL5_HPROT_MASK                                       0x1
+#define VUL5_HPROT_MASK_SFT                                   (0x1 << 5)
+#define VUL4_HPROT_SFT                                        4
+#define VUL4_HPROT_MASK                                       0x1
+#define VUL4_HPROT_MASK_SFT                                   (0x1 << 4)
+#define VUL3_HPROT_SFT                                        3
+#define VUL3_HPROT_MASK                                       0x1
+#define VUL3_HPROT_MASK_SFT                                   (0x1 << 3)
+#define VUL2_HPROT_SFT                                        2
+#define VUL2_HPROT_MASK                                       0x1
+#define VUL2_HPROT_MASK_SFT                                   (0x1 << 2)
+#define VUL1_HPROT_SFT                                        1
+#define VUL1_HPROT_MASK                                       0x1
+#define VUL1_HPROT_MASK_SFT                                   (0x1 << 1)
+#define VUL0_HPROT_SFT                                        0
+#define VUL0_HPROT_MASK                                       0x1
+#define VUL0_HPROT_MASK_SFT                                   (0x1 << 0)
+
+/* AFE_SE_PROT_SIDEBAND3 */
+#define MPHONE_EARC_HPROT_SFT                                 10
+#define MPHONE_EARC_HPROT_MASK                                0x1
+#define MPHONE_EARC_HPROT_MASK_SFT                            (0x1 << 10)
+#define MPHONE_SPDIF_HPROT_SFT                                9
+#define MPHONE_SPDIF_HPROT_MASK                               0x1
+#define MPHONE_SPDIF_HPROT_MASK_SFT                           (0x1 << 9)
+#define SPDIFIN_HPROT_SFT                                     8
+#define SPDIFIN_HPROT_MASK                                    0x1
+#define SPDIFIN_HPROT_MASK_SFT                                (0x1 << 8)
+#define TDMIN_HPROT_SFT                                       7
+#define TDMIN_HPROT_MASK                                      0x1
+#define TDMIN_HPROT_MASK_SFT                                  (0x1 << 7)
+#define ETDM_IN6_HPROT_SFT                                    6
+#define ETDM_IN6_HPROT_MASK                                   0x1
+#define ETDM_IN6_HPROT_MASK_SFT                               (0x1 << 6)
+#define ETDM_IN5_HPROT_SFT                                    5
+#define ETDM_IN5_HPROT_MASK                                   0x1
+#define ETDM_IN5_HPROT_MASK_SFT                               (0x1 << 5)
+#define ETDM_IN4_HPROT_SFT                                    4
+#define ETDM_IN4_HPROT_MASK                                   0x1
+#define ETDM_IN4_HPROT_MASK_SFT                               (0x1 << 4)
+#define ETDM_IN3_HPROT_SFT                                    3
+#define ETDM_IN3_HPROT_MASK                                   0x1
+#define ETDM_IN3_HPROT_MASK_SFT                               (0x1 << 3)
+#define ETDM_IN2_HPROT_SFT                                    2
+#define ETDM_IN2_HPROT_MASK                                   0x1
+#define ETDM_IN2_HPROT_MASK_SFT                               (0x1 << 2)
+#define ETDM_IN1_HPROT_SFT                                    1
+#define ETDM_IN1_HPROT_MASK                                   0x1
+#define ETDM_IN1_HPROT_MASK_SFT                               (0x1 << 1)
+#define ETDM_IN0_HPROT_SFT                                    0
+#define ETDM_IN0_HPROT_MASK                                   0x1
+#define ETDM_IN0_HPROT_MASK_SFT                               (0x1 << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND0 */
+#define DL7_HDOMAIN_SFT                                       28
+#define DL7_HDOMAIN_MASK                                      0xf
+#define DL7_HDOMAIN_MASK_SFT                                  (0xf << 28)
+#define DL6_HDOMAIN_SFT                                       24
+#define DL6_HDOMAIN_MASK                                      0xf
+#define DL6_HDOMAIN_MASK_SFT                                  (0xf << 24)
+#define DL5_HDOMAIN_SFT                                       20
+#define DL5_HDOMAIN_MASK                                      0xf
+#define DL5_HDOMAIN_MASK_SFT                                  (0xf << 20)
+#define DL4_HDOMAIN_SFT                                       16
+#define DL4_HDOMAIN_MASK                                      0xf
+#define DL4_HDOMAIN_MASK_SFT                                  (0xf << 16)
+#define DL3_HDOMAIN_SFT                                       12
+#define DL3_HDOMAIN_MASK                                      0xf
+#define DL3_HDOMAIN_MASK_SFT                                  (0xf << 12)
+#define DL2_HDOMAIN_SFT                                       8
+#define DL2_HDOMAIN_MASK                                      0xf
+#define DL2_HDOMAIN_MASK_SFT                                  (0xf << 8)
+#define DL1_HDOMAIN_SFT                                       4
+#define DL1_HDOMAIN_MASK                                      0xf
+#define DL1_HDOMAIN_MASK_SFT                                  (0xf << 4)
+#define DL0_HDOMAIN_SFT                                       0
+#define DL0_HDOMAIN_MASK                                      0xf
+#define DL0_HDOMAIN_MASK_SFT                                  (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND1 */
+#define DL_48CH_HDOMAIN_SFT                                   24
+#define DL_48CH_HDOMAIN_MASK                                  0xf
+#define DL_48CH_HDOMAIN_MASK_SFT                              (0xf << 24)
+#define DL_24CH_HDOMAIN_SFT                                   20
+#define DL_24CH_HDOMAIN_MASK                                  0xf
+#define DL_24CH_HDOMAIN_MASK_SFT                              (0xf << 20)
+#define DL_4CH_HDOMAIN_SFT                                    16
+#define DL_4CH_HDOMAIN_MASK                                   0xf
+#define DL_4CH_HDOMAIN_MASK_SFT                               (0xf << 16)
+#define HDMI_HDOMAIN_SFT                                      12
+#define HDMI_HDOMAIN_MASK                                     0xf
+#define HDMI_HDOMAIN_MASK_SFT                                 (0xf << 12)
+#define SPDIF2_OUT_HDOMAIN_SFT                                8
+#define SPDIF2_OUT_HDOMAIN_MASK                               0xf
+#define SPDIF2_OUT_HDOMAIN_MASK_SFT                           (0xf << 8)
+#define SPDIF_OUT_HDOMAIN_SFT                                 4
+#define SPDIF_OUT_HDOMAIN_MASK                                0xf
+#define SPDIF_OUT_HDOMAIN_MASK_SFT                            (0xf << 4)
+#define DL8_HDOMAIN_SFT                                       0
+#define DL8_HDOMAIN_MASK                                      0xf
+#define DL8_HDOMAIN_MASK_SFT                                  (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND2 */
+#define DL30_HDOMAIN_SFT                                      28
+#define DL30_HDOMAIN_MASK                                     0xf
+#define DL30_HDOMAIN_MASK_SFT                                 (0xf << 28)
+#define DL29_HDOMAIN_SFT                                      24
+#define DL29_HDOMAIN_MASK                                     0xf
+#define DL29_HDOMAIN_MASK_SFT                                 (0xf << 24)
+#define DL28_HDOMAIN_SFT                                      20
+#define DL28_HDOMAIN_MASK                                     0xf
+#define DL28_HDOMAIN_MASK_SFT                                 (0xf << 20)
+#define DL27_HDOMAIN_SFT                                      16
+#define DL27_HDOMAIN_MASK                                     0xf
+#define DL27_HDOMAIN_MASK_SFT                                 (0xf << 16)
+#define DL26_HDOMAIN_SFT                                      12
+#define DL26_HDOMAIN_MASK                                     0xf
+#define DL26_HDOMAIN_MASK_SFT                                 (0xf << 12)
+#define DL25_HDOMAIN_SFT                                      8
+#define DL25_HDOMAIN_MASK                                     0xf
+#define DL25_HDOMAIN_MASK_SFT                                 (0xf << 8)
+#define DL24_HDOMAIN_SFT                                      4
+#define DL24_HDOMAIN_MASK                                     0xf
+#define DL24_HDOMAIN_MASK_SFT                                 (0xf << 4)
+#define DL23_HDOMAIN_SFT                                      0
+#define DL23_HDOMAIN_MASK                                     0xf
+#define DL23_HDOMAIN_MASK_SFT                                 (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND3 */
+#define DL38_HDOMAIN_SFT                                      28
+#define DL38_HDOMAIN_MASK                                     0xf
+#define DL38_HDOMAIN_MASK_SFT                                 (0xf << 28)
+#define DL37_HDOMAIN_SFT                                      24
+#define DL37_HDOMAIN_MASK                                     0xf
+#define DL37_HDOMAIN_MASK_SFT                                 (0xf << 24)
+#define DL36_HDOMAIN_SFT                                      20
+#define DL36_HDOMAIN_MASK                                     0xf
+#define DL36_HDOMAIN_MASK_SFT                                 (0xf << 20)
+#define DL35_HDOMAIN_SFT                                      16
+#define DL35_HDOMAIN_MASK                                     0xf
+#define DL35_HDOMAIN_MASK_SFT                                 (0xf << 16)
+#define DL34_HDOMAIN_SFT                                      12
+#define DL34_HDOMAIN_MASK                                     0xf
+#define DL34_HDOMAIN_MASK_SFT                                 (0xf << 12)
+#define DL33_HDOMAIN_SFT                                      8
+#define DL33_HDOMAIN_MASK                                     0xf
+#define DL33_HDOMAIN_MASK_SFT                                 (0xf << 8)
+#define DL32_HDOMAIN_SFT                                      4
+#define DL32_HDOMAIN_MASK                                     0xf
+#define DL32_HDOMAIN_MASK_SFT                                 (0xf << 4)
+#define DL31_HDOMAIN_SFT                                      0
+#define DL31_HDOMAIN_MASK                                     0xf
+#define DL31_HDOMAIN_MASK_SFT                                 (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND4 */
+#define DL46_HDOMAIN_SFT                                      28
+#define DL46_HDOMAIN_MASK                                     0xf
+#define DL46_HDOMAIN_MASK_SFT                                 (0xf << 28)
+#define DL45_HDOMAIN_SFT                                      24
+#define DL45_HDOMAIN_MASK                                     0xf
+#define DL45_HDOMAIN_MASK_SFT                                 (0xf << 24)
+#define DL44_HDOMAIN_SFT                                      20
+#define DL44_HDOMAIN_MASK                                     0xf
+#define DL44_HDOMAIN_MASK_SFT                                 (0xf << 20)
+#define DL43_HDOMAIN_SFT                                      16
+#define DL43_HDOMAIN_MASK                                     0xf
+#define DL43_HDOMAIN_MASK_SFT                                 (0xf << 16)
+#define DL42_HDOMAIN_SFT                                      12
+#define DL42_HDOMAIN_MASK                                     0xf
+#define DL42_HDOMAIN_MASK_SFT                                 (0xf << 12)
+#define DL41_HDOMAIN_SFT                                      8
+#define DL41_HDOMAIN_MASK                                     0xf
+#define DL41_HDOMAIN_MASK_SFT                                 (0xf << 8)
+#define DL40_HDOMAIN_SFT                                      4
+#define DL40_HDOMAIN_MASK                                     0xf
+#define DL40_HDOMAIN_MASK_SFT                                 (0xf << 4)
+#define DL39_HDOMAIN_SFT                                      0
+#define DL39_HDOMAIN_MASK                                     0xf
+#define DL39_HDOMAIN_MASK_SFT                                 (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND5 */
+#define VUL7_HDOMAIN_SFT                                      28
+#define VUL7_HDOMAIN_MASK                                     0xf
+#define VUL7_HDOMAIN_MASK_SFT                                 (0xf << 28)
+#define VUL6_HDOMAIN_SFT                                      24
+#define VUL6_HDOMAIN_MASK                                     0xf
+#define VUL6_HDOMAIN_MASK_SFT                                 (0xf << 24)
+#define VUL5_HDOMAIN_SFT                                      20
+#define VUL5_HDOMAIN_MASK                                     0xf
+#define VUL5_HDOMAIN_MASK_SFT                                 (0xf << 20)
+#define VUL4_HDOMAIN_SFT                                      16
+#define VUL4_HDOMAIN_MASK                                     0xf
+#define VUL4_HDOMAIN_MASK_SFT                                 (0xf << 16)
+#define VUL3_HDOMAIN_SFT                                      12
+#define VUL3_HDOMAIN_MASK                                     0xf
+#define VUL3_HDOMAIN_MASK_SFT                                 (0xf << 12)
+#define VUL2_HDOMAIN_SFT                                      8
+#define VUL2_HDOMAIN_MASK                                     0xf
+#define VUL2_HDOMAIN_MASK_SFT                                 (0xf << 8)
+#define VUL1_HDOMAIN_SFT                                      4
+#define VUL1_HDOMAIN_MASK                                     0xf
+#define VUL1_HDOMAIN_MASK_SFT                                 (0xf << 4)
+#define VUL0_HDOMAIN_SFT                                      0
+#define VUL0_HDOMAIN_MASK                                     0xf
+#define VUL0_HDOMAIN_MASK_SFT                                 (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND6 */
+#define VU25_HDOMAIN_SFT                                      28
+#define VU25_HDOMAIN_MASK                                     0xf
+#define VU25_HDOMAIN_MASK_SFT                                 (0xf << 28)
+#define VUL24_HDOMAIN_SFT                                     24
+#define VUL24_HDOMAIN_MASK                                    0xf
+#define VUL24_HDOMAIN_MASK_SFT                                (0xf << 24)
+#define VUL_CM2_HDOMAIN_SFT                                   20
+#define VUL_CM2_HDOMAIN_MASK                                  0xf
+#define VUL_CM2_HDOMAIN_MASK_SFT                              (0xf << 20)
+#define VUL_CM1_HDOMAIN_SFT                                   16
+#define VUL_CM1_HDOMAIN_MASK                                  0xf
+#define VUL_CM1_HDOMAIN_MASK_SFT                              (0xf << 16)
+#define VUL_CM0_HDOMAIN_SFT                                   12
+#define VUL_CM0_HDOMAIN_MASK                                  0xf
+#define VUL_CM0_HDOMAIN_MASK_SFT                              (0xf << 12)
+#define VUL10_HDOMAIN_SFT                                     8
+#define VUL10_HDOMAIN_MASK                                    0xf
+#define VUL10_HDOMAIN_MASK_SFT                                (0xf << 8)
+#define VUL9_HDOMAIN_SFT                                      4
+#define VUL9_HDOMAIN_MASK                                     0xf
+#define VUL9_HDOMAIN_MASK_SFT                                 (0xf << 4)
+#define VUL8_HDOMAIN_SFT                                      0
+#define VUL8_HDOMAIN_MASK                                     0xf
+#define VUL8_HDOMAIN_MASK_SFT                                 (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND7 */
+#define VUL33_HDOMAIN_SFT                                     28
+#define VUL33_HDOMAIN_MASK                                    0xf
+#define VUL33_HDOMAIN_MASK_SFT                                (0xf << 28)
+#define VUL32_HDOMAIN_SFT                                     24
+#define VUL32_HDOMAIN_MASK                                    0xf
+#define VUL32_HDOMAIN_MASK_SFT                                (0xf << 24)
+#define VUL31_HDOMAIN_SFT                                     20
+#define VUL31_HDOMAIN_MASK                                    0xf
+#define VUL31_HDOMAIN_MASK_SFT                                (0xf << 20)
+#define VUL30_HDOMAIN_SFT                                     16
+#define VUL30_HDOMAIN_MASK                                    0xf
+#define VUL30_HDOMAIN_MASK_SFT                                (0xf << 16)
+#define VUL29_HDOMAIN_SFT                                     12
+#define VUL29_HDOMAIN_MASK                                    0xf
+#define VUL29_HDOMAIN_MASK_SFT                                (0xf << 12)
+#define VUL28_HDOMAIN_SFT                                     8
+#define VUL28_HDOMAIN_MASK                                    0xf
+#define VUL28_HDOMAIN_MASK_SFT                                (0xf << 8)
+#define VUL27_HDOMAIN_SFT                                     4
+#define VUL27_HDOMAIN_MASK                                    0xf
+#define VUL27_HDOMAIN_MASK_SFT                                (0xf << 4)
+#define VUL26_HDOMAIN_SFT                                     0
+#define VUL26_HDOMAIN_MASK                                    0xf
+#define VUL26_HDOMAIN_MASK_SFT                                (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND8 */
+#define ETDM_IN2_HDOMAIN_SFT                                  28
+#define ETDM_IN2_HDOMAIN_MASK                                 0xf
+#define ETDM_IN2_HDOMAIN_MASK_SFT                             (0xf << 28)
+#define ETDM_IN1_HDOMAIN_SFT                                  24
+#define ETDM_IN1_HDOMAIN_MASK                                 0xf
+#define ETDM_IN1_HDOMAIN_MASK_SFT                             (0xf << 24)
+#define ETDM_IN0_HDOMAIN_SFT                                  20
+#define ETDM_IN0_HDOMAIN_MASK                                 0xf
+#define ETDM_IN0_HDOMAIN_MASK_SFT                             (0xf << 20)
+#define VUL38_HDOMAIN_SFT                                     16
+#define VUL38_HDOMAIN_MASK                                    0xf
+#define VUL38_HDOMAIN_MASK_SFT                                (0xf << 16)
+#define VUL37_HDOMAIN_SFT                                     12
+#define VUL37_HDOMAIN_MASK                                    0xf
+#define VUL37_HDOMAIN_MASK_SFT                                (0xf << 12)
+#define VUL36_HDOMAIN_SFT                                     8
+#define VUL36_HDOMAIN_MASK                                    0xf
+#define VUL36_HDOMAIN_MASK_SFT                                (0xf << 8)
+#define VUL35_HDOMAIN_SFT                                     4
+#define VUL35_HDOMAIN_MASK                                    0xf
+#define VUL35_HDOMAIN_MASK_SFT                                (0xf << 4)
+#define VUL34_HDOMAIN_SFT                                     0
+#define VUL34_HDOMAIN_MASK                                    0xf
+#define VUL34_HDOMAIN_MASK_SFT                                (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND9 */
+#define MPHONE_EARC_HDOMAIN_SFT                               28
+#define MPHONE_EARC_HDOMAIN_MASK                              0xf
+#define MPHONE_EARC_HDOMAIN_MASK_SFT                          (0xf << 28)
+#define MPHONE_SPDIF_HDOMAIN_SFT                              24
+#define MPHONE_SPDIF_HDOMAIN_MASK                             0xf
+#define MPHONE_SPDIF_HDOMAIN_MASK_SFT                         (0xf << 24)
+#define SPDIFIN_HDOMAIN_SFT                                   20
+#define SPDIFIN_HDOMAIN_MASK                                  0xf
+#define SPDIFIN_HDOMAIN_MASK_SFT                              (0xf << 20)
+#define TDMIN_HDOMAIN_SFT                                     16
+#define TDMIN_HDOMAIN_MASK                                    0xf
+#define TDMIN_HDOMAIN_MASK_SFT                                (0xf << 16)
+#define ETDM_IN6_HDOMAIN_SFT                                  12
+#define ETDM_IN6_HDOMAIN_MASK                                 0xf
+#define ETDM_IN6_HDOMAIN_MASK_SFT                             (0xf << 12)
+#define ETDM_IN5_HDOMAIN_SFT                                  8
+#define ETDM_IN5_HDOMAIN_MASK                                 0xf
+#define ETDM_IN5_HDOMAIN_MASK_SFT                             (0xf << 8)
+#define ETDM_IN4_HDOMAIN_SFT                                  4
+#define ETDM_IN4_HDOMAIN_MASK                                 0xf
+#define ETDM_IN4_HDOMAIN_MASK_SFT                             (0xf << 4)
+#define ETDM_IN3_HDOMAIN_SFT                                  0
+#define ETDM_IN3_HDOMAIN_MASK                                 0xf
+#define ETDM_IN3_HDOMAIN_MASK_SFT                             (0xf << 0)
+
+/* AFE_PROT_SIDEBAND0_MON */
+#define AFE_DOMAIN_SIDEBAN0_MON_SFT                           0
+#define AFE_DOMAIN_SIDEBAN0_MON_MASK                          0xffffffff
+#define AFE_DOMAIN_SIDEBAN0_MON_MASK_SFT                      (0xffffffff << 0)
+
+/* AFE_PROT_SIDEBAND1_MON */
+#define AFE_DOMAIN_SIDEBAN1_MON_SFT                           0
+#define AFE_DOMAIN_SIDEBAN1_MON_MASK                          0xffffffff
+#define AFE_DOMAIN_SIDEBAN1_MON_MASK_SFT                      (0xffffffff << 0)
+
+/* AFE_PROT_SIDEBAND2_MON */
+#define AFE_DOMAIN_SIDEBAN2_MON_SFT                           0
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK                          0xffffffff
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT                      (0xffffffff << 0)
+
+/* AFE_PROT_SIDEBAND3_MON */
+#define AFE_DOMAIN_SIDEBAN3_MON_SFT                           0
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK                          0xffffffff
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT                      (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND0_MON */
+#define AFE_DOMAIN_SIDEBAN0_MON_SFT                           0
+#define AFE_DOMAIN_SIDEBAN0_MON_MASK                          0xffffffff
+#define AFE_DOMAIN_SIDEBAN0_MON_MASK_SFT                      (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND1_MON */
+#define AFE_DOMAIN_SIDEBAN1_MON_SFT                           0
+#define AFE_DOMAIN_SIDEBAN1_MON_MASK                          0xffffffff
+#define AFE_DOMAIN_SIDEBAN1_MON_MASK_SFT                      (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND2_MON */
+#define AFE_DOMAIN_SIDEBAN2_MON_SFT                           0
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK                          0xffffffff
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT                      (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND3_MON */
+#define AFE_DOMAIN_SIDEBAN3_MON_SFT                           0
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK                          0xffffffff
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT                      (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND4_MON */
+#define AFE_DOMAIN_SIDEBAN0_MON_SFT                           0
+#define AFE_DOMAIN_SIDEBAN0_MON_MASK                          0xffffffff
+#define AFE_DOMAIN_SIDEBAN0_MON_MASK_SFT                      (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND5_MON */
+#define AFE_DOMAIN_SIDEBAN1_MON_SFT                           0
+#define AFE_DOMAIN_SIDEBAN1_MON_MASK                          0xffffffff
+#define AFE_DOMAIN_SIDEBAN1_MON_MASK_SFT                      (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND6_MON */
+#define AFE_DOMAIN_SIDEBAN2_MON_SFT                           0
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK                          0xffffffff
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT                      (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND7_MON */
+#define AFE_DOMAIN_SIDEBAN3_MON_SFT                           0
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK                          0xffffffff
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT                      (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND8_MON */
+#define AFE_DOMAIN_SIDEBAN2_MON_SFT                           0
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK                          0xffffffff
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT                      (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND9_MON */
+#define AFE_DOMAIN_SIDEBAN3_MON_SFT                           0
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK                          0xffffffff
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT                      (0xffffffff << 0)
+
+/* AFE_SECURE_CONN0 */
+#define AFE_SPDIFIN_LPBK_CON_MASK_S_SFT                       26
+#define AFE_SPDIFIN_LPBK_CON_MASK_S_MASK                      0x3
+#define AFE_SPDIFIN_LPBK_CON_MASK_S_MASK_SFT                  (0x3 << 26)
+#define AFE_ADDA_DMIC1_SRC_CON0_MASK_S_SFT                    25
+#define AFE_ADDA_DMIC1_SRC_CON0_MASK_S_MASK                   0x1
+#define AFE_ADDA_DMIC1_SRC_CON0_MASK_S_MASK_SFT               (0x1 << 25)
+#define AFE_ADDA_DMIC0_SRC_CON0_MASK_S_SFT                    24
+#define AFE_ADDA_DMIC0_SRC_CON0_MASK_S_MASK                   0x1
+#define AFE_ADDA_DMIC0_SRC_CON0_MASK_S_MASK_SFT               (0x1 << 24)
+#define AFE_ADDA_UL3_SRC_CON0_MASK_S_SFT                      23
+#define AFE_ADDA_UL3_SRC_CON0_MASK_S_MASK                     0x1
+#define AFE_ADDA_UL3_SRC_CON0_MASK_S_MASK_SFT                 (0x1 << 23)
+#define AFE_ADDA_UL2_SRC_CON0_MASK_S_SFT                      22
+#define AFE_ADDA_UL2_SRC_CON0_MASK_S_MASK                     0x1
+#define AFE_ADDA_UL2_SRC_CON0_MASK_S_MASK_SFT                 (0x1 << 22)
+#define AFE_ADDA_UL1_SRC_CON0_MASK_S_SFT                      21
+#define AFE_ADDA_UL1_SRC_CON0_MASK_S_MASK                     0x1
+#define AFE_ADDA_UL1_SRC_CON0_MASK_S_MASK_SFT                 (0x1 << 21)
+#define AFE_ADDA_UL0_SRC_CON0_MASK_S_SFT                      20
+#define AFE_ADDA_UL0_SRC_CON0_MASK_S_MASK                     0x1
+#define AFE_ADDA_UL0_SRC_CON0_MASK_S_MASK_SFT                 (0x1 << 20)
+#define AFE_MRKAIF1_CFG0_MASK_S_SFT                           19
+#define AFE_MRKAIF1_CFG0_MASK_S_MASK                          0x1
+#define AFE_MRKAIF1_CFG0_MASK_S_MASK_SFT                      (0x1 << 19)
+#define AFE_MRKAIF0_CFG0_MASK_S_SFT                           18
+#define AFE_MRKAIF0_CFG0_MASK_S_MASK                          0x1
+#define AFE_MRKAIF0_CFG0_MASK_S_MASK_SFT                      (0x1 << 18)
+#define AFE_TDMIN_CON1_MASK_S_SFT                             17
+#define AFE_TDMIN_CON1_MASK_S_MASK                            0x1
+#define AFE_TDMIN_CON1_MASK_S_MASK_SFT                        (0x1 << 17)
+#define AFE_TDM_CON2_MASK_S_SFT                               16
+#define AFE_TDM_CON2_MASK_S_MASK                              0x1
+#define AFE_TDM_CON2_MASK_S_MASK_SFT                          (0x1 << 16)
+#define AFE_DAIBT_CON_MASK_S_SFT                              14
+#define AFE_DAIBT_CON_MASK_S_MASK                             0x3
+#define AFE_DAIBT_CON_MASK_S_MASK_SFT                         (0x3 << 14)
+#define AFE_MRGIF_CON_MASK_S_SFT                              12
+#define AFE_MRGIF_CON_MASK_S_MASK                             0x3
+#define AFE_MRGIF_CON_MASK_S_MASK_SFT                         (0x3 << 12)
+#define AFE_CONNSYS_I2S_CON_MASK_S_SFT                        11
+#define AFE_CONNSYS_I2S_CON_MASK_S_MASK                       0x1
+#define AFE_CONNSYS_I2S_CON_MASK_S_MASK_SFT                   (0x1 << 11)
+#define AFE_PCM1_INFT_CON0_MASK_S_SFT                         6
+#define AFE_PCM1_INFT_CON0_MASK_S_MASK                        0x1f
+#define AFE_PCM1_INFT_CON0_MASK_S_MASK_SFT                    (0x1f << 6)
+#define AFE_PCM0_INTF_CON1_MASK_S_SFT                         0
+#define AFE_PCM0_INTF_CON1_MASK_S_MASK                        0x3f
+#define AFE_PCM0_INTF_CON1_MASK_S_MASK_SFT                    (0x3f << 0)
+
+/* AFE_SECURE_CONN_ETDM0 */
+#define ETDM_0_3_COWORK_CON2_OUT3_DATA_SEL_SFT                28
+#define ETDM_0_3_COWORK_CON2_OUT3_DATA_SEL_MASK               0xf
+#define ETDM_0_3_COWORK_CON2_OUT3_DATA_SEL_MASK_SFT           (0xf << 28)
+#define ETDM_0_3_COWORK_CON2_OUT2_DATA_SEL_SFT                24
+#define ETDM_0_3_COWORK_CON2_OUT2_DATA_SEL_MASK               0xf
+#define ETDM_0_3_COWORK_CON2_OUT2_DATA_SEL_MASK_SFT           (0xf << 24)
+#define ETDM_0_3_COWORK_CON2_IN1_SDATA1_15_SEL_SFT            20
+#define ETDM_0_3_COWORK_CON2_IN1_SDATA1_15_SEL_MASK           0xf
+#define ETDM_0_3_COWORK_CON2_IN1_SDATA1_15_SEL_MASK_SFT       (0xf << 20)
+#define ETDM_0_3_COWORK_CON2_IN1_SDATA0_SEL_SFT               16
+#define ETDM_0_3_COWORK_CON2_IN1_SDATA0_SEL_MASK              0xf
+#define ETDM_0_3_COWORK_CON2_IN1_SDATA0_SEL_MASK_SFT          (0xf << 16)
+#define ETDM_0_3_COWORK_CON2_IN0_SDATA1_15_SEL_SFT            12
+#define ETDM_0_3_COWORK_CON2_IN0_SDATA1_15_SEL_MASK           0xf
+#define ETDM_0_3_COWORK_CON2_IN0_SDATA1_15_SEL_MASK_SFT       (0xf << 12)
+#define ETDM_0_3_COWORK_CON2_IN0_SDATA0_SEL_SFT               8
+#define ETDM_0_3_COWORK_CON2_IN0_SDATA0_SEL_MASK              0xf
+#define ETDM_0_3_COWORK_CON2_IN0_SDATA0_SEL_MASK_SFT          (0xf << 8)
+#define ETDM_0_3_COWORK_CON2_OUT1_DATA_SEL_SFT                4
+#define ETDM_0_3_COWORK_CON2_OUT1_DATA_SEL_MASK               0xf
+#define ETDM_0_3_COWORK_CON2_OUT1_DATA_SEL_MASK_SFT           (0xf << 4)
+#define ETDM_0_3_COWORK_CON2_OUT0_DATA_SEL_SFT                0
+#define ETDM_0_3_COWORK_CON2_OUT0_DATA_SEL_MASK               0xf
+#define ETDM_0_3_COWORK_CON2_OUT0_DATA_SEL_MASK_SFT           (0xf << 0)
+
+/* AFE_SECURE_CONN_ETDM1 */
+#define ETDM_4_7_COWORK_CON1_IN4_SDATA1_15_SEL_SFT            28
+#define ETDM_4_7_COWORK_CON1_IN4_SDATA1_15_SEL_MASK           0xf
+#define ETDM_4_7_COWORK_CON1_IN4_SDATA1_15_SEL_MASK_SFT       (0xf << 28)
+#define ETDM_4_7_COWORK_CON1_IN4_SDATA0_SEL_SFT               24
+#define ETDM_4_7_COWORK_CON1_IN4_SDATA0_SEL_MASK              0xf
+#define ETDM_4_7_COWORK_CON1_IN4_SDATA0_SEL_MASK_SFT          (0xf << 24)
+#define ETDM_4_7_COWORK_CON1_OUT5_DATA_SEL_SFT                20
+#define ETDM_4_7_COWORK_CON1_OUT5_DATA_SEL_MASK               0xf
+#define ETDM_4_7_COWORK_CON1_OUT5_DATA_SEL_MASK_SFT           (0xf << 20)
+#define ETDM_4_7_COWORK_CON1_OUT4_DATA_SEL_SFT                16
+#define ETDM_4_7_COWORK_CON1_OUT4_DATA_SEL_MASK               0xf
+#define ETDM_4_7_COWORK_CON1_OUT4_DATA_SEL_MASK_SFT           (0xf << 16)
+#define ETDM_4_7_COWORK_CON1_IN3_SDATA1_15_SEL_SFT            12
+#define ETDM_4_7_COWORK_CON1_IN3_SDATA1_15_SEL_MASK           0xf
+#define ETDM_4_7_COWORK_CON1_IN3_SDATA1_15_SEL_MASK_SFT       (0xf << 12)
+#define ETDM_4_7_COWORK_CON1_IN3_SDATA0_SEL_SFT               8
+#define ETDM_4_7_COWORK_CON1_IN3_SDATA0_SEL_MASK              0xf
+#define ETDM_4_7_COWORK_CON1_IN3_SDATA0_SEL_MASK_SFT          (0xf << 8)
+#define ETDM_4_7_COWORK_CON1_IN2_SDATA1_15_SEL_SFT            4
+#define ETDM_4_7_COWORK_CON1_IN2_SDATA1_15_SEL_MASK           0xf
+#define ETDM_4_7_COWORK_CON1_IN2_SDATA1_15_SEL_MASK_SFT       (0xf << 4)
+#define ETDM_4_7_COWORK_CON1_IN2_SDATA0_SEL_SFT               0
+#define ETDM_4_7_COWORK_CON1_IN2_SDATA0_SEL_MASK              0xf
+#define ETDM_4_7_COWORK_CON1_IN2_SDATA0_SEL_MASK_SFT          (0xf << 0)
+
+/* AFE_SECURE_CONN_ETDM2 */
+#define ETDM_4_7_COWORK_CON3_IN7_SDATA1_15_SEL_SFT                            28
+#define ETDM_4_7_COWORK_CON3_IN7_SDATA1_15_SEL_MASK                           0xf
+#define ETDM_4_7_COWORK_CON3_IN7_SDATA1_15_SEL_MASK_SFT                       (0xf << 28)
+#define ETDM_4_7_COWORK_CON3_IN7_SDATA0_SEL_SFT                               24
+#define ETDM_4_7_COWORK_CON3_IN7_SDATA0_SEL_MASK                              0xf
+#define ETDM_4_7_COWORK_CON3_IN7_SDATA0_SEL_MASK_SFT                          (0xf << 24)
+#define ETDM_4_7_COWORK_CON3_IN6_SDATA1_15_SEL_SFT                            20
+#define ETDM_4_7_COWORK_CON3_IN6_SDATA1_15_SEL_MASK                           0xf
+#define ETDM_4_7_COWORK_CON3_IN6_SDATA1_15_SEL_MASK_SFT                       (0xf << 20)
+#define ETDM_4_7_COWORK_CON3_IN6_SDATA0_SEL_SFT                               16
+#define ETDM_4_7_COWORK_CON3_IN6_SDATA0_SEL_MASK                              0xf
+#define ETDM_4_7_COWORK_CON3_IN6_SDATA0_SEL_MASK_SFT                          (0xf << 16)
+#define ETDM_4_7_COWORK_CON3_OUT7_DATA_SEL_SFT                                12
+#define ETDM_4_7_COWORK_CON3_OUT7_DATA_SEL_MASK                               0xf
+#define ETDM_4_7_COWORK_CON3_OUT7_DATA_SEL_MASK_SFT                           (0xf << 12)
+#define ETDM_4_7_COWORK_CON3_OUT6_DATA_SEL_SFT                                8
+#define ETDM_4_7_COWORK_CON3_OUT6_DATA_SEL_MASK                               0xf
+#define ETDM_4_7_COWORK_CON3_OUT6_DATA_SEL_MASK_SFT                           (0xf << 8)
+#define ETDM_4_7_COWORK_CON3_IN5_SDATA1_15_SEL_SFT                            4
+#define ETDM_4_7_COWORK_CON3_IN5_SDATA1_15_SEL_MASK                           0xf
+#define ETDM_4_7_COWORK_CON3_IN5_SDATA1_15_SEL_MASK_SFT                       (0xf << 4)
+#define ETDM_4_7_COWORK_CON3_IN5_SDATA0_SEL_SFT                               0
+#define ETDM_4_7_COWORK_CON3_IN5_SDATA0_SEL_MASK                              0xf
+#define ETDM_4_7_COWORK_CON3_IN5_SDATA0_SEL_MASK_SFT                          (0xf << 0)
+
+/* AFE_SECURE_SRAM_CON0 */
+#define SRAM_READ_EN15_NS_SFT                                 31
+#define SRAM_READ_EN15_NS_MASK                                0x1
+#define SRAM_READ_EN15_NS_MASK_SFT                            (0x1 << 31)
+#define SRAM_WRITE_EN15_NS_SFT                                30
+#define SRAM_WRITE_EN15_NS_MASK                               0x1
+#define SRAM_WRITE_EN15_NS_MASK_SFT                           (0x1 << 30)
+#define SRAM_READ_EN14_NS_SFT                                 29
+#define SRAM_READ_EN14_NS_MASK                                0x1
+#define SRAM_READ_EN14_NS_MASK_SFT                            (0x1 << 29)
+#define SRAM_WRITE_EN14_NS_SFT                                28
+#define SRAM_WRITE_EN14_NS_MASK                               0x1
+#define SRAM_WRITE_EN14_NS_MASK_SFT                           (0x1 << 28)
+#define SRAM_READ_EN13_NS_SFT                                 27
+#define SRAM_READ_EN13_NS_MASK                                0x1
+#define SRAM_READ_EN13_NS_MASK_SFT                            (0x1 << 27)
+#define SRAM_WRITE_EN13_NS_SFT                                26
+#define SRAM_WRITE_EN13_NS_MASK                               0x1
+#define SRAM_WRITE_EN13_NS_MASK_SFT                           (0x1 << 26)
+#define SRAM_READ_EN12_NS_SFT                                 25
+#define SRAM_READ_EN12_NS_MASK                                0x1
+#define SRAM_READ_EN12_NS_MASK_SFT                            (0x1 << 25)
+#define SRAM_WRITE_EN12_NS_SFT                                24
+#define SRAM_WRITE_EN12_NS_MASK                               0x1
+#define SRAM_WRITE_EN12_NS_MASK_SFT                           (0x1 << 24)
+#define SRAM_READ_EN11_NS_SFT                                 23
+#define SRAM_READ_EN11_NS_MASK                                0x1
+#define SRAM_READ_EN11_NS_MASK_SFT                            (0x1 << 23)
+#define SRAM_WRITE_EN11_NS_SFT                                22
+#define SRAM_WRITE_EN11_NS_MASK                               0x1
+#define SRAM_WRITE_EN11_NS_MASK_SFT                           (0x1 << 22)
+#define SRAM_READ_EN10_NS_SFT                                 21
+#define SRAM_READ_EN10_NS_MASK                                0x1
+#define SRAM_READ_EN10_NS_MASK_SFT                            (0x1 << 21)
+#define SRAM_WRITE_EN10_NS_SFT                                20
+#define SRAM_WRITE_EN10_NS_MASK                               0x1
+#define SRAM_WRITE_EN10_NS_MASK_SFT                           (0x1 << 20)
+#define SRAM_READ_EN9_NS_SFT                                  19
+#define SRAM_READ_EN9_NS_MASK                                 0x1
+#define SRAM_READ_EN9_NS_MASK_SFT                             (0x1 << 19)
+#define SRAM_WRITE_EN9_NS_SFT                                 18
+#define SRAM_WRITE_EN9_NS_MASK                                0x1
+#define SRAM_WRITE_EN9_NS_MASK_SFT                            (0x1 << 18)
+#define SRAM_READ_EN8_NS_SFT                                  17
+#define SRAM_READ_EN8_NS_MASK                                 0x1
+#define SRAM_READ_EN8_NS_MASK_SFT                             (0x1 << 17)
+#define SRAM_WRITE_EN8_NS_SFT                                 16
+#define SRAM_WRITE_EN8_NS_MASK                                0x1
+#define SRAM_WRITE_EN8_NS_MASK_SFT                            (0x1 << 16)
+#define SRAM_READ_EN7_NS_SFT                                  15
+#define SRAM_READ_EN7_NS_MASK                                 0x1
+#define SRAM_READ_EN7_NS_MASK_SFT                             (0x1 << 15)
+#define SRAM_WRITE_EN7_NS_SFT                                 14
+#define SRAM_WRITE_EN7_NS_MASK                                0x1
+#define SRAM_WRITE_EN7_NS_MASK_SFT                            (0x1 << 14)
+#define SRAM_READ_EN6_NS_SFT                                  13
+#define SRAM_READ_EN6_NS_MASK                                 0x1
+#define SRAM_READ_EN6_NS_MASK_SFT                             (0x1 << 13)
+#define SRAM_WRITE_EN6_NS_SFT                                 12
+#define SRAM_WRITE_EN6_NS_MASK                                0x1
+#define SRAM_WRITE_EN6_NS_MASK_SFT                            (0x1 << 12)
+#define SRAM_READ_EN5_NS_SFT                                  11
+#define SRAM_READ_EN5_NS_MASK                                 0x1
+#define SRAM_READ_EN5_NS_MASK_SFT                             (0x1 << 11)
+#define SRAM_WRITE_EN5_NS_SFT                                 10
+#define SRAM_WRITE_EN5_NS_MASK                                0x1
+#define SRAM_WRITE_EN5_NS_MASK_SFT                            (0x1 << 10)
+#define SRAM_READ_EN4_NS_SFT                                  9
+#define SRAM_READ_EN4_NS_MASK                                 0x1
+#define SRAM_READ_EN4_NS_MASK_SFT                             (0x1 << 9)
+#define SRAM_WRITE_EN4_NS_SFT                                 8
+#define SRAM_WRITE_EN4_NS_MASK                                0x1
+#define SRAM_WRITE_EN4_NS_MASK_SFT                            (0x1 << 8)
+#define SRAM_READ_EN3_NS_SFT                                  7
+#define SRAM_READ_EN3_NS_MASK                                 0x1
+#define SRAM_READ_EN3_NS_MASK_SFT                             (0x1 << 7)
+#define SRAM_WRITE_EN3_NS_SFT                                 6
+#define SRAM_WRITE_EN3_NS_MASK                                0x1
+#define SRAM_WRITE_EN3_NS_MASK_SFT                            (0x1 << 6)
+#define SRAM_READ_EN2_NS_SFT                                  5
+#define SRAM_READ_EN2_NS_MASK                                 0x1
+#define SRAM_READ_EN2_NS_MASK_SFT                             (0x1 << 5)
+#define SRAM_WRITE_EN2_NS_SFT                                 4
+#define SRAM_WRITE_EN2_NS_MASK                                0x1
+#define SRAM_WRITE_EN2_NS_MASK_SFT                            (0x1 << 4)
+#define SRAM_READ_EN1_NS_SFT                                  3
+#define SRAM_READ_EN1_NS_MASK                                 0x1
+#define SRAM_READ_EN1_NS_MASK_SFT                             (0x1 << 3)
+#define SRAM_WRITE_EN1_NS_SFT                                 2
+#define SRAM_WRITE_EN1_NS_MASK                                0x1
+#define SRAM_WRITE_EN1_NS_MASK_SFT                            (0x1 << 2)
+#define SRAM_READ_EN0_NS_SFT                                  1
+#define SRAM_READ_EN0_NS_MASK                                 0x1
+#define SRAM_READ_EN0_NS_MASK_SFT                             (0x1 << 1)
+#define SRAM_WRITE_EN0_NS_SFT                                 0
+#define SRAM_WRITE_EN0_NS_MASK                                0x1
+#define SRAM_WRITE_EN0_NS_MASK_SFT                            (0x1 << 0)
+
+/* AFE_SECURE_SRAM_CON1 */
+#define SRAM_READ_EN15_S_SFT                                  31
+#define SRAM_READ_EN15_S_MASK                                 0x1
+#define SRAM_READ_EN15_S_MASK_SFT                             (0x1 << 31)
+#define SRAM_WRITE_EN15_S_SFT                                 30
+#define SRAM_WRITE_EN15_S_MASK                                0x1
+#define SRAM_WRITE_EN15_S_MASK_SFT                            (0x1 << 30)
+#define SRAM_READ_EN14_S_SFT                                  29
+#define SRAM_READ_EN14_S_MASK                                 0x1
+#define SRAM_READ_EN14_S_MASK_SFT                             (0x1 << 29)
+#define SRAM_WRITE_EN14_S_SFT                                 28
+#define SRAM_WRITE_EN14_S_MASK                                0x1
+#define SRAM_WRITE_EN14_S_MASK_SFT                            (0x1 << 28)
+#define SRAM_READ_EN13_S_SFT                                  27
+#define SRAM_READ_EN13_S_MASK                                 0x1
+#define SRAM_READ_EN13_S_MASK_SFT                             (0x1 << 27)
+#define SRAM_WRITE_EN13_S_SFT                                 26
+#define SRAM_WRITE_EN13_S_MASK                                0x1
+#define SRAM_WRITE_EN13_S_MASK_SFT                            (0x1 << 26)
+#define SRAM_READ_EN12_S_SFT                                  25
+#define SRAM_READ_EN12_S_MASK                                 0x1
+#define SRAM_READ_EN12_S_MASK_SFT                             (0x1 << 25)
+#define SRAM_WRITE_EN12_S_SFT                                 24
+#define SRAM_WRITE_EN12_S_MASK                                0x1
+#define SRAM_WRITE_EN12_S_MASK_SFT                            (0x1 << 24)
+#define SRAM_READ_EN11_S_SFT                                  23
+#define SRAM_READ_EN11_S_MASK                                 0x1
+#define SRAM_READ_EN11_S_MASK_SFT                             (0x1 << 23)
+#define SRAM_WRITE_EN11_S_SFT                                 22
+#define SRAM_WRITE_EN11_S_MASK                                0x1
+#define SRAM_WRITE_EN11_S_MASK_SFT                            (0x1 << 22)
+#define SRAM_READ_EN10_S_SFT                                  21
+#define SRAM_READ_EN10_S_MASK                                 0x1
+#define SRAM_READ_EN10_S_MASK_SFT                             (0x1 << 21)
+#define SRAM_WRITE_EN10_S_SFT                                 20
+#define SRAM_WRITE_EN10_S_MASK                                0x1
+#define SRAM_WRITE_EN10_S_MASK_SFT                            (0x1 << 20)
+#define SRAM_READ_EN9_S_SFT                                   19
+#define SRAM_READ_EN9_S_MASK                                  0x1
+#define SRAM_READ_EN9_S_MASK_SFT                              (0x1 << 19)
+#define SRAM_WRITE_EN9_S_SFT                                  18
+#define SRAM_WRITE_EN9_S_MASK                                 0x1
+#define SRAM_WRITE_EN9_S_MASK_SFT                             (0x1 << 18)
+#define SRAM_READ_EN8_S_SFT                                   17
+#define SRAM_READ_EN8_S_MASK                                  0x1
+#define SRAM_READ_EN8_S_MASK_SFT                              (0x1 << 17)
+#define SRAM_WRITE_EN8_S_SFT                                  16
+#define SRAM_WRITE_EN8_S_MASK                                 0x1
+#define SRAM_WRITE_EN8_S_MASK_SFT                             (0x1 << 16)
+#define SRAM_READ_EN7_S_SFT                                   15
+#define SRAM_READ_EN7_S_MASK                                  0x1
+#define SRAM_READ_EN7_S_MASK_SFT                              (0x1 << 15)
+#define SRAM_WRITE_EN7_S_SFT                                  14
+#define SRAM_WRITE_EN7_S_MASK                                 0x1
+#define SRAM_WRITE_EN7_S_MASK_SFT                             (0x1 << 14)
+#define SRAM_READ_EN6_S_SFT                                   13
+#define SRAM_READ_EN6_S_MASK                                  0x1
+#define SRAM_READ_EN6_S_MASK_SFT                              (0x1 << 13)
+#define SRAM_WRITE_EN6_S_SFT                                  12
+#define SRAM_WRITE_EN6_S_MASK                                 0x1
+#define SRAM_WRITE_EN6_S_MASK_SFT                             (0x1 << 12)
+#define SRAM_READ_EN5_S_SFT                                   11
+#define SRAM_READ_EN5_S_MASK                                  0x1
+#define SRAM_READ_EN5_S_MASK_SFT                              (0x1 << 11)
+#define SRAM_WRITE_EN5_S_SFT                                  10
+#define SRAM_WRITE_EN5_S_MASK                                 0x1
+#define SRAM_WRITE_EN5_S_MASK_SFT                             (0x1 << 10)
+#define SRAM_READ_EN4_S_SFT                                   9
+#define SRAM_READ_EN4_S_MASK                                  0x1
+#define SRAM_READ_EN4_S_MASK_SFT                              (0x1 << 9)
+#define SRAM_WRITE_EN4_S_SFT                                  8
+#define SRAM_WRITE_EN4_S_MASK                                 0x1
+#define SRAM_WRITE_EN4_S_MASK_SFT                             (0x1 << 8)
+#define SRAM_READ_EN3_S_SFT                                   7
+#define SRAM_READ_EN3_S_MASK                                  0x1
+#define SRAM_READ_EN3_S_MASK_SFT                              (0x1 << 7)
+#define SRAM_WRITE_EN3_S_SFT                                  6
+#define SRAM_WRITE_EN3_S_MASK                                 0x1
+#define SRAM_WRITE_EN3_S_MASK_SFT                             (0x1 << 6)
+#define SRAM_READ_EN2_S_SFT                                   5
+#define SRAM_READ_EN2_S_MASK                                  0x1
+#define SRAM_READ_EN2_S_MASK_SFT                              (0x1 << 5)
+#define SRAM_WRITE_EN2_S_SFT                                  4
+#define SRAM_WRITE_EN2_S_MASK                                 0x1
+#define SRAM_WRITE_EN2_S_MASK_SFT                             (0x1 << 4)
+#define SRAM_READ_EN1_S_SFT                                   3
+#define SRAM_READ_EN1_S_MASK                                  0x1
+#define SRAM_READ_EN1_S_MASK_SFT                              (0x1 << 3)
+#define SRAM_WRITE_EN1_S_SFT                                  2
+#define SRAM_WRITE_EN1_S_MASK                                 0x1
+#define SRAM_WRITE_EN1_S_MASK_SFT                             (0x1 << 2)
+#define SRAM_READ_EN0_S_SFT                                   1
+#define SRAM_READ_EN0_S_MASK                                  0x1
+#define SRAM_READ_EN0_S_MASK_SFT                              (0x1 << 1)
+#define SRAM_WRITE_EN0_S_SFT                                  0
+#define SRAM_WRITE_EN0_S_MASK                                 0x1
+#define SRAM_WRITE_EN0_S_MASK_SFT                             (0x1 << 0)
+
+/* AFE_SE_CONN_INPUT_MASK0 */
+#define SECURE_INTRCONN_I0_I31_S_SFT                          0
+#define SECURE_INTRCONN_I0_I31_S_MASK                         0xffffffff
+#define SECURE_INTRCONN_I0_I31_S_MASK_SFT                     (0xffffffff << 0)
+
+/* AFE_SE_CONN_INPUT_MASK1 */
+#define SECURE_INTRCONN_I32_I63_S_SFT                         0
+#define SECURE_INTRCONN_I32_I63_S_MASK                        0xffffffff
+#define SECURE_INTRCONN_I32_I63_S_MASK_SFT                    (0xffffffff << 0)
+
+/* AFE_SE_CONN_INPUT_MASK2 */
+#define SECURE_INTRCONN_I64_I95_S_SFT                         0
+#define SECURE_INTRCONN_I64_I95_S_MASK                        0xffffffff
+#define SECURE_INTRCONN_I64_I95_S_MASK_SFT                    (0xffffffff << 0)
+
+/* AFE_SE_CONN_INPUT_MASK3 */
+#define SECURE_INTRCONN_I96_I127_S_SFT                        0
+#define SECURE_INTRCONN_I96_I127_S_MASK                       0xffffffff
+#define SECURE_INTRCONN_I96_I127_S_MASK_SFT                   (0xffffffff << 0)
+
+/* AFE_SE_CONN_INPUT_MASK4 */
+#define SECURE_INTRCONN_I128_I159_S_SFT                       0
+#define SECURE_INTRCONN_I128_I159_S_MASK                      0xffffffff
+#define SECURE_INTRCONN_I128_I159_S_MASK_SFT                  (0xffffffff << 0)
+
+/* AFE_SE_CONN_INPUT_MASK5 */
+#define SECURE_INTRCONN_I160_I191_S_SFT                       0
+#define SECURE_INTRCONN_I160_I191_S_MASK                      0xffffffff
+#define SECURE_INTRCONN_I160_I191_S_MASK_SFT                  (0xffffffff << 0)
+
+/* AFE_SE_CONN_INPUT_MASK6 */
+#define SECURE_INTRCONN_I192_I223_S_SFT                       0
+#define SECURE_INTRCONN_I192_I223_S_MASK                      0xffffffff
+#define SECURE_INTRCONN_I192_I223_S_MASK_SFT                  (0xffffffff << 0)
+
+/* AFE_SE_CONN_INPUT_MASK7 */
+#define SECURE_INTRCONN_I224_I256_S_SFT                       0
+#define SECURE_INTRCONN_I224_I256_S_MASK                      0xffffffff
+#define SECURE_INTRCONN_I224_I256_S_MASK_SFT                  (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK0 */
+#define NORMAL_INTRCONN_I0_I31_S_SFT                          0
+#define NORMAL_INTRCONN_I0_I31_S_MASK                         0xffffffff
+#define NORMAL_INTRCONN_I0_I31_S_MASK_SFT                     (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK1 */
+#define NORMAL_INTRCONN_I32_I63_S_SFT                         0
+#define NORMAL_INTRCONN_I32_I63_S_MASK                        0xffffffff
+#define NORMAL_INTRCONN_I32_I63_S_MASK_SFT                    (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK2 */
+#define NORMAL_INTRCONN_I64_I95_S_SFT                         0
+#define NORMAL_INTRCONN_I64_I95_S_MASK                        0xffffffff
+#define NORMAL_INTRCONN_I64_I95_S_MASK_SFT                    (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK3 */
+#define NORMAL_INTRCONN_I96_I127_S_SFT                        0
+#define NORMAL_INTRCONN_I96_I127_S_MASK                       0xffffffff
+#define NORMAL_INTRCONN_I96_I127_S_MASK_SFT                   (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK4 */
+#define NORMAL_INTRCONN_I128_I159_S_SFT                       0
+#define NORMAL_INTRCONN_I128_I159_S_MASK                      0xffffffff
+#define NORMAL_INTRCONN_I128_I159_S_MASK_SFT                  (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK5 */
+#define NORMAL_INTRCONN_I160_I191_S_SFT                       0
+#define NORMAL_INTRCONN_I160_I191_S_MASK                      0xffffffff
+#define NORMAL_INTRCONN_I160_I191_S_MASK_SFT                  (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK6 */
+#define NORMAL_INTRCONN_I192_I223_S_SFT                       0
+#define NORMAL_INTRCONN_I192_I223_S_MASK                      0xffffffff
+#define NORMAL_INTRCONN_I192_I223_S_MASK_SFT                  (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK7 */
+#define NORMAL_INTRCONN_I224_I256_S_SFT                       0
+#define NORMAL_INTRCONN_I224_I256_S_MASK                      0xffffffff
+#define NORMAL_INTRCONN_I224_I256_S_MASK_SFT                  (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL0 */
+#define SECURE_INTRCONN_O0_O31_S_SFT                          0
+#define SECURE_INTRCONN_O0_O31_S_MASK                         0xffffffff
+#define SECURE_INTRCONN_O0_O31_S_MASK_SFT                     (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL1 */
+#define SECURE_INTRCONN_O32_O63_S_SFT                         0
+#define SECURE_INTRCONN_O32_O63_S_MASK                        0xffffffff
+#define SECURE_INTRCONN_O32_O63_S_MASK_SFT                    (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL2 */
+#define SECURE_INTRCONN_O64_O95_S_SFT                         0
+#define SECURE_INTRCONN_O64_O95_S_MASK                        0xffffffff
+#define SECURE_INTRCONN_O64_O95_S_MASK_SFT                    (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL3 */
+#define SECURE_INTRCONN_O96_O127_S_SFT                        0
+#define SECURE_INTRCONN_O96_O127_S_MASK                       0xffffffff
+#define SECURE_INTRCONN_O96_O127_S_MASK_SFT                   (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL4 */
+#define SECURE_INTRCONN_O128_O159_S_SFT                       0
+#define SECURE_INTRCONN_O128_O159_S_MASK                      0xffffffff
+#define SECURE_INTRCONN_O128_O159_S_MASK_SFT                  (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL5 */
+#define SECURE_INTRCONN_O160_O191_S_SFT                       0
+#define SECURE_INTRCONN_O160_O191_S_MASK                      0xffffffff
+#define SECURE_INTRCONN_O160_O191_S_MASK_SFT                  (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL6 */
+#define SECURE_INTRCONN_O192_O223_S_SFT                       0
+#define SECURE_INTRCONN_O192_O223_S_MASK                      0xffffffff
+#define SECURE_INTRCONN_O192_O223_S_MASK_SFT                  (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL7 */
+#define SECURE_INTRCONN_O224_O256_S_SFT                       0
+#define SECURE_INTRCONN_O224_O256_S_MASK                      0xffffffff
+#define SECURE_INTRCONN_O224_O256_S_MASK_SFT                  (0xffffffff << 0)
+
+/* AFE_PCM0_INTF_CON1_MASK_MON */
+#define AFE_PCM0_INTF_CON1_MASK_MON_SFT                       0
+#define AFE_PCM0_INTF_CON1_MASK_MON_MASK                      0xffffffff
+#define AFE_PCM0_INTF_CON1_MASK_MON_MASK_SFT                  (0xffffffff << 0)
+
+/* AFE_PCM0_INTF_CON0_MASK_MON */
+#define AFE_PCM0_INTF_CON0_MASK_MON_SFT                       0
+#define AFE_PCM0_INTF_CON0_MASK_MON_MASK                      0xffffffff
+#define AFE_PCM0_INTF_CON0_MASK_MON_MASK_SFT                  (0xffffffff << 0)
+
+/* AFE_CONNSYS_I2S_CON_MASK_MON */
+#define AFE_CONNSYS_I2S_CON_MASK_MON_SFT                      0
+#define AFE_CONNSYS_I2S_CON_MASK_MON_MASK                     0xffffffff
+#define AFE_CONNSYS_I2S_CON_MASK_MON_MASK_SFT                 (0xffffffff << 0)
+
+/* AFE_TDM_CON2_MASK_MON */
+#define AFE_TDM_CON2_MASK_MON_SFT                             0
+#define AFE_TDM_CON2_MASK_MON_MASK                            0xffffffff
+#define AFE_TDM_CON2_MASK_MON_MASK_SFT                        (0xffffffff << 0)
+
+/* AFE_MTKAIF0_CFG0_MASK_MON */
+#define AFE_MTKAIF0_CFG0_MASK_MON_SFT                         0
+#define AFE_MTKAIF0_CFG0_MASK_MON_MASK                        0xffffffff
+#define AFE_MTKAIF0_CFG0_MASK_MON_MASK_SFT                    (0xffffffff << 0)
+
+/* AFE_MTKAIF1_CFG0_MASK_MON */
+#define AFE_MTKAIF1_CFG0_MASK_MON_SFT                         0
+#define AFE_MTKAIF1_CFG0_MASK_MON_MASK                        0xffffffff
+#define AFE_MTKAIF1_CFG0_MASK_MON_MASK_SFT                    (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_SRC_CON0_MASK_MON */
+#define AFE_ADDA_UL0_SRC_CON0_MASK_MON_SFT                    0
+#define AFE_ADDA_UL0_SRC_CON0_MASK_MON_MASK                   0xffffffff
+#define AFE_ADDA_UL0_SRC_CON0_MASK_MON_MASK_SFT               (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_SRC_CON0_MASK_MON */
+#define AFE_ADDA_UL1_SRC_CON0_MASK_MON_SFT                    0
+#define AFE_ADDA_UL1_SRC_CON0_MASK_MON_MASK                   0xffffffff
+#define AFE_ADDA_UL1_SRC_CON0_MASK_MON_MASK_SFT               (0xffffffff << 0)
+
+/* AFE_ADDA_UL2_SRC_CON0_MASK_MON */
+#define AFE_ADDA_UL2_SRC_CON0_MASK_MON_SFT                    0
+#define AFE_ADDA_UL2_SRC_CON0_MASK_MON_MASK                   0xffffffff
+#define AFE_ADDA_UL2_SRC_CON0_MASK_MON_MASK_SFT               (0xffffffff << 0)
+
+/* AFE_ASRC_NEW_CON0 */
+#define ONE_HEART_SFT                                         31
+#define ONE_HEART_MASK                                        0x1
+#define ONE_HEART_MASK_SFT                                    (0x1 << 31)
+#define CHSET0_OFS_ONE_HEART_DISABLE_SFT                      30
+#define CHSET0_OFS_ONE_HEART_DISABLE_MASK                     0x1
+#define CHSET0_OFS_ONE_HEART_DISABLE_MASK_SFT                 (0x1 << 30)
+#define USE_SHORT_DELAY_COEFF_SFT                             29
+#define USE_SHORT_DELAY_COEFF_MASK                            0x1
+#define USE_SHORT_DELAY_COEFF_MASK_SFT                        (0x1 << 29)
+#define CHSET0_O16BIT_SFT                                     19
+#define CHSET0_O16BIT_MASK                                    0x1
+#define CHSET0_O16BIT_MASK_SFT                                (0x1 << 19)
+#define CHSET0_CLR_IIR_HISTORY_SFT                            17
+#define CHSET0_CLR_IIR_HISTORY_MASK                           0x1
+#define CHSET0_CLR_IIR_HISTORY_MASK_SFT                       (0x1 << 17)
+#define CHSET0_IS_MONO_SFT                                    16
+#define CHSET0_IS_MONO_MASK                                   0x1
+#define CHSET0_IS_MONO_MASK_SFT                               (0x1 << 16)
+#define CHSET0_OFS_SEL_SFT                                    14
+#define CHSET0_OFS_SEL_MASK                                   0x3
+#define CHSET0_OFS_SEL_MASK_SFT                               (0x3 << 14)
+#define CHSET0_IFS_SEL_SFT                                    12
+#define CHSET0_IFS_SEL_MASK                                   0x3
+#define CHSET0_IFS_SEL_MASK_SFT                               (0x3 << 12)
+#define CHSET0_IIR_EN_SFT                                     11
+#define CHSET0_IIR_EN_MASK                                    0x1
+#define CHSET0_IIR_EN_MASK_SFT                                (0x1 << 11)
+#define CHSET0_IIR_STAGE_SFT                                  8
+#define CHSET0_IIR_STAGE_MASK                                 0x7
+#define CHSET0_IIR_STAGE_MASK_SFT                             (0x7 << 8)
+#define ASM_ON_MOD_SFT                                        7
+#define ASM_ON_MOD_MASK                                       0x1
+#define ASM_ON_MOD_MASK_SFT                                   (0x1 << 7)
+#define CHSET_STR_CLR_SFT                                     4
+#define CHSET_STR_CLR_MASK                                    0x1
+#define CHSET_STR_CLR_MASK_SFT                                (0x1 << 4)
+#define CHSET_ON_SFT                                          2
+#define CHSET_ON_MASK                                         0x1
+#define CHSET_ON_MASK_SFT                                     (0x1 << 2)
+#define COEFF_SRAM_CTRL_SFT                                   1
+#define COEFF_SRAM_CTRL_MASK                                  0x1
+#define COEFF_SRAM_CTRL_MASK_SFT                              (0x1 << 1)
+#define ASM_ON_SFT                                            0
+#define ASM_ON_MASK                                           0x1
+#define ASM_ON_MASK_SFT                                       (0x1 << 0)
+
+/* AFE_ASRC_NEW_CON1 */
+#define ASM_FREQ_0_SFT                                        0
+#define ASM_FREQ_0_MASK                                       0xffffff
+#define ASM_FREQ_0_MASK_SFT                                   (0xffffff << 0)
+
+/* AFE_ASRC_NEW_CON2 */
+#define ASM_FREQ_1_SFT                                        0
+#define ASM_FREQ_1_MASK                                       0xffffff
+#define ASM_FREQ_1_MASK_SFT                                   (0xffffff << 0)
+
+/* AFE_ASRC_NEW_CON3 */
+#define ASM_FREQ_2_SFT                                        0
+#define ASM_FREQ_2_MASK                                       0xffffff
+#define ASM_FREQ_2_MASK_SFT                                   (0xffffff << 0)
+
+/* AFE_ASRC_NEW_CON4 */
+#define ASM_FREQ_3_SFT                                        0
+#define ASM_FREQ_3_MASK                                       0xffffff
+#define ASM_FREQ_3_MASK_SFT                                   (0xffffff << 0)
+
+/* AFE_ASRC_NEW_CON5 */
+#define OUT_EN_SEL_DOMAIN_SFT                                 29
+#define OUT_EN_SEL_DOMAIN_MASK                                0x7
+#define OUT_EN_SEL_DOMAIN_MASK_SFT                            (0x7 << 29)
+#define OUT_EN_SEL_FS_SFT                                     24
+#define OUT_EN_SEL_FS_MASK                                    0x1f
+#define OUT_EN_SEL_FS_MASK_SFT                                (0x1f << 24)
+#define IN_EN_SEL_DOMAIN_SFT                                  21
+#define IN_EN_SEL_DOMAIN_MASK                                 0x7
+#define IN_EN_SEL_DOMAIN_MASK_SFT                             (0x7 << 21)
+#define IN_EN_SEL_FS_SFT                                      16
+#define IN_EN_SEL_FS_MASK                                     0x1f
+#define IN_EN_SEL_FS_MASK_SFT                                 (0x1f << 16)
+#define RESULT_SEL_SFT                                        8
+#define RESULT_SEL_MASK                                       0x7
+#define RESULT_SEL_MASK_SFT                                   (0x7 << 8)
+#define CALI_CK_SEL_SFT                                       4
+#define CALI_CK_SEL_MASK                                      0x7
+#define CALI_CK_SEL_MASK_SFT                                  (0x7 << 4)
+#define CALI_LRCK_SEL_SFT                                     1
+#define CALI_LRCK_SEL_MASK                                    0x7
+#define CALI_LRCK_SEL_MASK_SFT                                (0x7 << 1)
+#define SOFT_RESET_SFT                                        0
+#define SOFT_RESET_MASK                                       0x1
+#define SOFT_RESET_MASK_SFT                                   (0x1 << 0)
+
+/* AFE_ASRC_NEW_CON6 */
+#define FREQ_CALI_CYCLE_SFT                                   16
+#define FREQ_CALI_CYCLE_MASK                                  0xffff
+#define FREQ_CALI_CYCLE_MASK_SFT                              (0xffff << 16)
+#define FREQ_CALI_AUTORST_EN_SFT                              15
+#define FREQ_CALI_AUTORST_EN_MASK                             0x1
+#define FREQ_CALI_AUTORST_EN_MASK_SFT                         (0x1 << 15)
+#define CALI_AUTORST_DETECT_SFT                               14
+#define CALI_AUTORST_DETECT_MASK                              0x1
+#define CALI_AUTORST_DETECT_MASK_SFT                          (0x1 << 14)
+#define FREQ_CALC_RUNNING_SFT                                 13
+#define FREQ_CALC_RUNNING_MASK                                0x1
+#define FREQ_CALC_RUNNING_MASK_SFT                            (0x1 << 13)
+#define AUTO_TUNE_FREQ3_SFT                                   12
+#define AUTO_TUNE_FREQ3_MASK                                  0x1
+#define AUTO_TUNE_FREQ3_MASK_SFT                              (0x1 << 12)
+#define COMP_FREQ_RES_EN_SFT                                  11
+#define COMP_FREQ_RES_EN_MASK                                 0x1
+#define COMP_FREQ_RES_EN_MASK_SFT                             (0x1 << 11)
+#define FREQ_CALI_SEL_SFT                                     8
+#define FREQ_CALI_SEL_MASK                                    0x3
+#define FREQ_CALI_SEL_MASK_SFT                                (0x3 << 8)
+#define FREQ_CALI_BP_DGL_SFT                                  7
+#define FREQ_CALI_BP_DGL_MASK                                 0x1
+#define FREQ_CALI_BP_DGL_MASK_SFT                             (0x1 << 7)
+#define FREQ_CALI_MAX_GWIDTH_SFT                              4
+#define FREQ_CALI_MAX_GWIDTH_MASK                             0x7
+#define FREQ_CALI_MAX_GWIDTH_MASK_SFT                         (0x7 << 4)
+#define AUTO_TUNE_FREQ2_SFT                                   3
+#define AUTO_TUNE_FREQ2_MASK                                  0x1
+#define AUTO_TUNE_FREQ2_MASK_SFT                              (0x1 << 3)
+#define FREQ_CALI_AUTO_RESTART_SFT                            2
+#define FREQ_CALI_AUTO_RESTART_MASK                           0x1
+#define FREQ_CALI_AUTO_RESTART_MASK_SFT                       (0x1 << 2)
+#define CALI_USE_FREQ_OUT_SFT                                 1
+#define CALI_USE_FREQ_OUT_MASK                                0x1
+#define CALI_USE_FREQ_OUT_MASK_SFT                            (0x1 << 1)
+#define CALI_EN_SFT                                           0
+#define CALI_EN_MASK                                          0x1
+#define CALI_EN_MASK_SFT                                      (0x1 << 0)
+
+/* AFE_ASRC_NEW_CON7 */
+#define FREQ_CALC_DENOMINATOR_SFT                             0
+#define FREQ_CALC_DENOMINATOR_MASK                            0xffffff
+#define FREQ_CALC_DENOMINATOR_MASK_SFT                        (0xffffff << 0)
+
+/* AFE_ASRC_NEW_CON8 */
+#define PRD_CALI_RESULT_RECORD_SFT                            0
+#define PRD_CALI_RESULT_RECORD_MASK                           0xffffff
+#define PRD_CALI_RESULT_RECORD_MASK_SFT                       (0xffffff << 0)
+
+/* AFE_ASRC_NEW_CON9 */
+#define FREQ_CALI_RESULT_SFT                                  0
+#define FREQ_CALI_RESULT_MASK                                 0xffffff
+#define FREQ_CALI_RESULT_MASK_SFT                             (0xffffff << 0)
+
+/* AFE_ASRC_NEW_CON10 */
+#define COEFF_SRAM_DATA_SFT                                   0
+#define COEFF_SRAM_DATA_MASK                                  0xffffffff
+#define COEFF_SRAM_DATA_MASK_SFT                              (0xffffffff << 0)
+
+/* AFE_ASRC_NEW_CON11 */
+#define COEFF_SRAM_ADR_SFT                                    0
+#define COEFF_SRAM_ADR_MASK                                   0x3f
+#define COEFF_SRAM_ADR_MASK_SFT                               (0x3f << 0)
+
+/* AFE_ASRC_NEW_CON12 */
+#define RING_DBG_RD_SFT                                       0
+#define RING_DBG_RD_MASK                                      0x3ffffff
+#define RING_DBG_RD_MASK_SFT                                  (0x3ffffff << 0)
+
+/* AFE_ASRC_NEW_CON13 */
+#define FREQ_CALI_AUTORST_TH_HIGH_SFT                         0
+#define FREQ_CALI_AUTORST_TH_HIGH_MASK                        0xffffff
+#define FREQ_CALI_AUTORST_TH_HIGH_MASK_SFT                    (0xffffff << 0)
+
+/* AFE_ASRC_NEW_CON14 */
+#define FREQ_CALI_AUTORST_TH_LOW_SFT                          0
+#define FREQ_CALI_AUTORST_TH_LOW_MASK                         0xffffff
+#define FREQ_CALI_AUTORST_TH_LOW_MASK_SFT                     (0xffffff << 0)
+
+/* AFE_ASRC_NEW_IP_VERSION */
+#define IP_VERSION_SFT                                        0
+#define IP_VERSION_MASK                                       0xffffffff
+#define IP_VERSION_MASK_SFT                                   (0xffffffff << 0)
+
+#define AUDIO_TOP_CON0                       0x0
+#define AUDIO_TOP_CON1                       0x4
+#define AUDIO_TOP_CON2                       0x8
+#define AUDIO_TOP_CON3                       0xc
+#define AUDIO_TOP_CON4                       0x10
+#define AUDIO_ENGEN_CON0                     0x14
+#define AUDIO_ENGEN_CON0_USER1               0x18
+#define AUDIO_ENGEN_CON0_USER2               0x1c
+#define AFE_SINEGEN_CON0                     0x20
+#define AFE_SINEGEN_CON1                     0x24
+#define AFE_SINEGEN_CON2                     0x28
+#define AFE_SINEGEN_CON3                     0x2c
+#define AFE_APLL1_TUNER_CFG                  0x30
+#define AFE_APLL1_TUNER_MON0                 0x34
+#define AFE_APLL2_TUNER_CFG                  0x38
+#define AFE_APLL2_TUNER_MON0                 0x3c
+#define AUDIO_TOP_RG0                        0x4c
+#define AUDIO_TOP_RG1                        0x50
+#define AUDIO_TOP_RG2                        0x54
+#define AUDIO_TOP_RG3                        0x58
+#define AUDIO_TOP_RG4                        0x5c
+#define AFE_SPM_CONTROL_REQ                  0x60
+#define AFE_SPM_CONTROL_ACK                  0x64
+#define AUD_TOP_CFG_VCORE_RG                 0x68
+#define AUDIO_TOP_IP_VERSION                 0x6c
+#define AUDIO_ENGEN_CON0_MON                 0x7c
+#define AUD_TOP_CFG_VLP_RG                   0x98
+#define AUD_TOP_MON_RG                       0x9c
+#define AUDIO_USE_DEFAULT_DELSEL0            0xa0
+#define AUDIO_USE_DEFAULT_DELSEL1            0xa4
+#define AUDIO_USE_DEFAULT_DELSEL2            0xa8
+#define AFE_CONNSYS_I2S_IPM_VER_MON          0xb0
+#define AFE_CONNSYS_I2S_MON_SEL              0xb4
+#define AFE_CONNSYS_I2S_MON                  0xb8
+#define AFE_CONNSYS_I2S_CON                  0xbc
+#define AFE_PCM0_INTF_CON0                   0xc0
+#define AFE_PCM0_INTF_CON1                   0xc4
+#define AFE_PCM_INTF_MON                     0xc8
+#define AFE_PCM1_INTF_CON0                   0xd0
+#define AFE_PCM1_INTF_CON1                   0xd4
+#define AFE_PCM_TOP_IP_VERSION               0xe8
+#define AFE_IRQ_MCU_EN                       0x100
+#define AFE_IRQ_MCU_DSP_EN                   0x104
+#define AFE_IRQ_MCU_DSP2_EN                  0x108
+#define AFE_IRQ_MCU_SCP_EN                   0x10c
+#define AFE_CUSTOM_IRQ_MCU_EN                0x110
+#define AFE_CUSTOM_IRQ_MCU_DSP_EN            0x114
+#define AFE_CUSTOM_IRQ_MCU_DSP2_EN           0x118
+#define AFE_CUSTOM_IRQ_MCU_SCP_EN            0x11c
+#define AFE_IRQ_MCU_STATUS                   0x120
+#define AFE_CUSTOM_IRQ_MCU_STATUS            0x124
+#define AFE_IRQ0_MCU_CFG0                    0x140
+#define AFE_IRQ0_MCU_CFG1                    0x144
+#define AFE_IRQ1_MCU_CFG0                    0x148
+#define AFE_IRQ1_MCU_CFG1                    0x14c
+#define AFE_IRQ2_MCU_CFG0                    0x150
+#define AFE_IRQ2_MCU_CFG1                    0x154
+#define AFE_IRQ3_MCU_CFG0                    0x158
+#define AFE_IRQ3_MCU_CFG1                    0x15c
+#define AFE_IRQ4_MCU_CFG0                    0x160
+#define AFE_IRQ4_MCU_CFG1                    0x164
+#define AFE_IRQ5_MCU_CFG0                    0x168
+#define AFE_IRQ5_MCU_CFG1                    0x16c
+#define AFE_IRQ6_MCU_CFG0                    0x170
+#define AFE_IRQ6_MCU_CFG1                    0x174
+#define AFE_IRQ7_MCU_CFG0                    0x178
+#define AFE_IRQ7_MCU_CFG1                    0x17c
+#define AFE_IRQ8_MCU_CFG0                    0x180
+#define AFE_IRQ8_MCU_CFG1                    0x184
+#define AFE_IRQ9_MCU_CFG0                    0x188
+#define AFE_IRQ9_MCU_CFG1                    0x18c
+#define AFE_IRQ10_MCU_CFG0                   0x190
+#define AFE_IRQ10_MCU_CFG1                   0x194
+#define AFE_IRQ11_MCU_CFG0                   0x198
+#define AFE_IRQ11_MCU_CFG1                   0x19c
+#define AFE_IRQ12_MCU_CFG0                   0x1a0
+#define AFE_IRQ12_MCU_CFG1                   0x1a4
+#define AFE_IRQ13_MCU_CFG0                   0x1a8
+#define AFE_IRQ13_MCU_CFG1                   0x1ac
+#define AFE_IRQ14_MCU_CFG0                   0x1b0
+#define AFE_IRQ14_MCU_CFG1                   0x1b4
+#define AFE_IRQ15_MCU_CFG0                   0x1b8
+#define AFE_IRQ15_MCU_CFG1                   0x1bc
+#define AFE_IRQ16_MCU_CFG0                   0x1c0
+#define AFE_IRQ16_MCU_CFG1                   0x1c4
+#define AFE_IRQ17_MCU_CFG0                   0x1c8
+#define AFE_IRQ17_MCU_CFG1                   0x1cc
+#define AFE_IRQ18_MCU_CFG0                   0x1d0
+#define AFE_IRQ18_MCU_CFG1                   0x1d4
+#define AFE_IRQ19_MCU_CFG0                   0x1d8
+#define AFE_IRQ19_MCU_CFG1                   0x1dc
+#define AFE_IRQ20_MCU_CFG0                   0x1e0
+#define AFE_IRQ20_MCU_CFG1                   0x1e4
+#define AFE_IRQ21_MCU_CFG0                   0x1e8
+#define AFE_IRQ21_MCU_CFG1                   0x1ec
+#define AFE_IRQ22_MCU_CFG0                   0x1f0
+#define AFE_IRQ22_MCU_CFG1                   0x1f4
+#define AFE_IRQ23_MCU_CFG0                   0x1f8
+#define AFE_IRQ23_MCU_CFG1                   0x1fc
+#define AFE_IRQ24_MCU_CFG0                   0x200
+#define AFE_IRQ24_MCU_CFG1                   0x204
+#define AFE_IRQ25_MCU_CFG0                   0x208
+#define AFE_IRQ25_MCU_CFG1                   0x20c
+#define AFE_IRQ26_MCU_CFG0                   0x210
+#define AFE_IRQ26_MCU_CFG1                   0x214
+#define AFE_CUSTOM_IRQ0_MCU_CFG0             0x268
+#define AFE_IRQ_MCU_MON0                     0x300
+#define AFE_IRQ_MCU_MON1                     0x304
+#define AFE_IRQ_MCU_MON2                     0x308
+#define AFE_IRQ0_CNT_MON                     0x310
+#define AFE_IRQ1_CNT_MON                     0x314
+#define AFE_IRQ2_CNT_MON                     0x318
+#define AFE_IRQ3_CNT_MON                     0x31c
+#define AFE_IRQ4_CNT_MON                     0x320
+#define AFE_IRQ5_CNT_MON                     0x324
+#define AFE_IRQ6_CNT_MON                     0x328
+#define AFE_IRQ7_CNT_MON                     0x32c
+#define AFE_IRQ8_CNT_MON                     0x330
+#define AFE_IRQ9_CNT_MON                     0x334
+#define AFE_IRQ10_CNT_MON                    0x338
+#define AFE_IRQ11_CNT_MON                    0x33c
+#define AFE_IRQ12_CNT_MON                    0x340
+#define AFE_IRQ13_CNT_MON                    0x344
+#define AFE_IRQ14_CNT_MON                    0x348
+#define AFE_IRQ15_CNT_MON                    0x34c
+#define AFE_IRQ16_CNT_MON                    0x350
+#define AFE_IRQ17_CNT_MON                    0x354
+#define AFE_IRQ18_CNT_MON                    0x358
+#define AFE_IRQ19_CNT_MON                    0x35c
+#define AFE_IRQ20_CNT_MON                    0x360
+#define AFE_IRQ21_CNT_MON                    0x364
+#define AFE_IRQ22_CNT_MON                    0x368
+#define AFE_IRQ23_CNT_MON                    0x36c
+#define AFE_IRQ24_CNT_MON                    0x370
+#define AFE_IRQ25_CNT_MON                    0x374
+#define AFE_IRQ26_CNT_MON                    0x378
+#define AFE_CUSTOM_IRQ0_CNT_MON              0x390
+#define AFE_CUSTOM_IRQ0_MCU_CFG1             0x3dc
+#define AFE_GAIN0_CON0                       0x400
+#define AFE_GAIN0_CON1_R                     0x404
+#define AFE_GAIN0_CON1_L                     0x408
+#define AFE_GAIN0_CON2                       0x40c
+#define AFE_GAIN0_CON3                       0x410
+#define AFE_GAIN0_CUR_R                      0x414
+#define AFE_GAIN0_CUR_L                      0x418
+#define AFE_GAIN1_CON0                       0x41c
+#define AFE_GAIN1_CON1_R                     0x420
+#define AFE_GAIN1_CON1_L                     0x424
+#define AFE_GAIN1_CON2                       0x428
+#define AFE_GAIN1_CON3                       0x42c
+#define AFE_GAIN1_CUR_R                      0x430
+#define AFE_GAIN1_CUR_L                      0x434
+#define AFE_GAIN2_CON0                       0x438
+#define AFE_GAIN2_CON1_R                     0x43c
+#define AFE_GAIN2_CON1_L                     0x440
+#define AFE_GAIN2_CON2                       0x444
+#define AFE_GAIN2_CON3                       0x448
+#define AFE_GAIN2_CUR_R                      0x44c
+#define AFE_GAIN2_CUR_L                      0x450
+#define AFE_GAIN3_CON0                       0x454
+#define AFE_GAIN3_CON1_R                     0x458
+#define AFE_GAIN3_CON1_L                     0x45c
+#define AFE_GAIN3_CON2                       0x460
+#define AFE_GAIN3_CON3                       0x464
+#define AFE_GAIN3_CUR_R                      0x468
+#define AFE_GAIN3_CUR_L                      0x46c
+#define AFE_STF_CON0                         0xb80
+#define AFE_STF_CON1                         0xb84
+#define AFE_STF_COEFF                        0xb88
+#define AFE_STF_GAIN                         0xb8c
+#define AFE_STF_MON                          0xb90
+#define AFE_STF_IP_VERSION                   0xb94
+#define AFE_CM0_CON0                         0xba0
+#define AFE_CM0_MON                          0xba4
+#define AFE_CM0_IP_VERSION                   0xba8
+#define AFE_CM1_CON0                         0xbb0
+#define AFE_CM1_MON                          0xbb4
+#define AFE_CM1_IP_VERSION                   0xbb8
+#define AFE_CM2_CON0                         0xbc0
+#define AFE_CM2_MON                          0xbc4
+#define AFE_CM2_IP_VERSION                   0xbc8
+#define AFE_ADDA_UL0_SRC_CON0                0xbd0
+#define AFE_ADDA_UL0_SRC_CON1                0xbd4
+#define AFE_ADDA_UL0_SRC_CON2                0xbd8
+#define AFE_ADDA_UL0_SRC_DEBUG               0xbdc
+#define AFE_ADDA_UL0_SRC_DEBUG_MON0          0xbe0
+#define AFE_ADDA_UL0_SRC_MON0                0xbe4
+#define AFE_ADDA_UL0_SRC_MON1                0xbe8
+#define AFE_ADDA_UL0_IIR_COEF_02_01          0xbec
+#define AFE_ADDA_UL0_IIR_COEF_04_03          0xbf0
+#define AFE_ADDA_UL0_IIR_COEF_06_05          0xbf4
+#define AFE_ADDA_UL0_IIR_COEF_08_07          0xbf8
+#define AFE_ADDA_UL0_IIR_COEF_10_09          0xbfc
+#define AFE_ADDA_UL0_ULCF_CFG_02_01          0xc00
+#define AFE_ADDA_UL0_ULCF_CFG_04_03          0xc04
+#define AFE_ADDA_UL0_ULCF_CFG_06_05          0xc08
+#define AFE_ADDA_UL0_ULCF_CFG_08_07          0xc0c
+#define AFE_ADDA_UL0_ULCF_CFG_10_09          0xc10
+#define AFE_ADDA_UL0_ULCF_CFG_12_11          0xc14
+#define AFE_ADDA_UL0_ULCF_CFG_14_13          0xc18
+#define AFE_ADDA_UL0_ULCF_CFG_16_15          0xc1c
+#define AFE_ADDA_UL0_ULCF_CFG_18_17          0xc20
+#define AFE_ADDA_UL0_ULCF_CFG_20_19          0xc24
+#define AFE_ADDA_UL0_ULCF_CFG_22_21          0xc28
+#define AFE_ADDA_UL0_ULCF_CFG_24_23          0xc2c
+#define AFE_ADDA_UL0_ULCF_CFG_26_25          0xc30
+#define AFE_ADDA_UL0_ULCF_CFG_28_27          0xc34
+#define AFE_ADDA_UL0_ULCF_CFG_30_29          0xc38
+#define AFE_ADDA_UL0_ULCF_CFG_32_31          0xc3c
+#define AFE_ADDA_UL0_IP_VERSION              0xc4c
+#define AFE_ADDA_UL1_SRC_CON0                0xc50
+#define AFE_ADDA_UL1_SRC_CON1                0xc54
+#define AFE_ADDA_UL1_SRC_CON2                0xc58
+#define AFE_ADDA_UL1_SRC_DEBUG               0xc5c
+#define AFE_ADDA_UL1_SRC_DEBUG_MON0          0xc60
+#define AFE_ADDA_UL1_SRC_MON0                0xc64
+#define AFE_ADDA_UL1_SRC_MON1                0xc68
+#define AFE_ADDA_UL1_IIR_COEF_02_01          0xc6c
+#define AFE_ADDA_UL1_IIR_COEF_04_03          0xc70
+#define AFE_ADDA_UL1_IIR_COEF_06_05          0xc74
+#define AFE_ADDA_UL1_IIR_COEF_08_07          0xc78
+#define AFE_ADDA_UL1_IIR_COEF_10_09          0xc7c
+#define AFE_ADDA_UL1_ULCF_CFG_02_01          0xc80
+#define AFE_ADDA_UL1_ULCF_CFG_04_03          0xc84
+#define AFE_ADDA_UL1_ULCF_CFG_06_05          0xc88
+#define AFE_ADDA_UL1_ULCF_CFG_08_07          0xc8c
+#define AFE_ADDA_UL1_ULCF_CFG_10_09          0xc90
+#define AFE_ADDA_UL1_ULCF_CFG_12_11          0xc94
+#define AFE_ADDA_UL1_ULCF_CFG_14_13          0xc98
+#define AFE_ADDA_UL1_ULCF_CFG_16_15          0xc9c
+#define AFE_ADDA_UL1_ULCF_CFG_18_17          0xca0
+#define AFE_ADDA_UL1_ULCF_CFG_20_19          0xca4
+#define AFE_ADDA_UL1_ULCF_CFG_22_21          0xca8
+#define AFE_ADDA_UL1_ULCF_CFG_24_23          0xcac
+#define AFE_ADDA_UL1_ULCF_CFG_26_25          0xcb0
+#define AFE_ADDA_UL1_ULCF_CFG_28_27          0xcb4
+#define AFE_ADDA_UL1_ULCF_CFG_30_29          0xcb8
+#define AFE_ADDA_UL1_ULCF_CFG_32_31          0xcbc
+#define AFE_ADDA_UL1_IP_VERSION              0xccc
+#define AFE_ADDA_UL2_SRC_CON0                0xcd0
+#define AFE_ADDA_UL2_SRC_CON1                0xcd4
+#define AFE_ADDA_UL2_SRC_CON2                0xcd8
+#define AFE_ADDA_UL2_SRC_DEBUG               0xcdc
+#define AFE_ADDA_UL2_SRC_DEBUG_MON0          0xce0
+#define AFE_ADDA_UL2_SRC_MON0                0xce4
+#define AFE_ADDA_UL2_SRC_MON1                0xce8
+#define AFE_ADDA_UL2_IIR_COEF_02_01          0xcec
+#define AFE_ADDA_UL2_IIR_COEF_04_03          0xcf0
+#define AFE_ADDA_UL2_IIR_COEF_06_05          0xcf4
+#define AFE_ADDA_UL2_IIR_COEF_08_07          0xcf8
+#define AFE_ADDA_UL2_IIR_COEF_10_09          0xcfc
+#define AFE_ADDA_UL2_ULCF_CFG_02_01          0xd00
+#define AFE_ADDA_UL2_ULCF_CFG_04_03          0xd04
+#define AFE_ADDA_UL2_ULCF_CFG_06_05          0xd08
+#define AFE_ADDA_UL2_ULCF_CFG_08_07          0xd0c
+#define AFE_ADDA_UL2_ULCF_CFG_10_09          0xd10
+#define AFE_ADDA_UL2_ULCF_CFG_12_11          0xd14
+#define AFE_ADDA_UL2_ULCF_CFG_14_13          0xd18
+#define AFE_ADDA_UL2_ULCF_CFG_16_15          0xd1c
+#define AFE_ADDA_UL2_ULCF_CFG_18_17          0xd20
+#define AFE_ADDA_UL2_ULCF_CFG_20_19          0xd24
+#define AFE_ADDA_UL2_ULCF_CFG_22_21          0xd28
+#define AFE_ADDA_UL2_ULCF_CFG_24_23          0xd2c
+#define AFE_ADDA_UL2_ULCF_CFG_26_25          0xd30
+#define AFE_ADDA_UL2_ULCF_CFG_28_27          0xd34
+#define AFE_ADDA_UL2_ULCF_CFG_30_29          0xd38
+#define AFE_ADDA_UL2_ULCF_CFG_32_31          0xd3c
+#define AFE_ADDA_UL2_IP_VERSION              0xd4c
+#define AFE_ADDA_PROXIMITY_CON0              0xed0
+#define AFE_ADDA_ULSRC_PHASE_CON0            0xf00
+#define AFE_ADDA_ULSRC_PHASE_CON1            0xf04
+#define AFE_ADDA_ULSRC_PHASE_CON2            0xf08
+#define AFE_ADDA_ULSRC_PHASE_CON3            0xf0c
+#define AFE_MTKAIF_IPM_VER_MON               0x1180
+#define AFE_MTKAIF_MON_SEL                   0x1184
+#define AFE_MTKAIF_MON                       0x1188
+#define AFE_MTKAIF0_CFG0                     0x1190
+#define AFE_MTKAIF0_TX_CFG0                  0x1194
+#define AFE_MTKAIF0_RX_CFG0                  0x1198
+#define AFE_MTKAIF0_RX_CFG1                  0x119c
+#define AFE_MTKAIF0_RX_CFG2                  0x11a0
+#define AFE_MTKAIF1_CFG0                     0x11f0
+#define AFE_MTKAIF1_TX_CFG0                  0x11f4
+#define AFE_MTKAIF1_RX_CFG0                  0x11f8
+#define AFE_MTKAIF1_RX_CFG1                  0x11fc
+#define AFE_MTKAIF1_RX_CFG2                  0x1200
+#define AFE_AUD_PAD_TOP_CFG0                 0x1204
+#define AFE_AUD_PAD_TOP_MON                  0x1208
+#define AFE_ADDA_MTKAIFV4_TX_CFG0            0x1280
+#define AFE_ADDA6_MTKAIFV4_TX_CFG0           0x1284
+#define AFE_ADDA_MTKAIFV4_RX_CFG0            0x1288
+#define AFE_ADDA_MTKAIFV4_RX_CFG1            0x128c
+#define AFE_ADDA6_MTKAIFV4_RX_CFG0           0x1290
+#define AFE_ADDA6_MTKAIFV4_RX_CFG1           0x1294
+#define AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG    0x1298
+#define AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG    0x129c
+#define AFE_ADDA_MTKAIFV4_MON0               0x12a0
+#define AFE_ADDA_MTKAIFV4_MON1               0x12a4
+#define AFE_ADDA6_MTKAIFV4_MON0              0x12a8
+#define ETDM_IN0_CON0                        0x1300
+#define ETDM_IN0_CON1                        0x1304
+#define ETDM_IN0_CON2                        0x1308
+#define ETDM_IN0_CON3                        0x130c
+#define ETDM_IN0_CON4                        0x1310
+#define ETDM_IN0_CON5                        0x1314
+#define ETDM_IN0_CON6                        0x1318
+#define ETDM_IN0_CON7                        0x131c
+#define ETDM_IN0_CON8                        0x1320
+#define ETDM_IN0_CON9                        0x1324
+#define ETDM_IN0_MON                         0x1328
+#define ETDM_IN1_CON0                        0x1330
+#define ETDM_IN1_CON1                        0x1334
+#define ETDM_IN1_CON2                        0x1338
+#define ETDM_IN1_CON3                        0x133c
+#define ETDM_IN1_CON4                        0x1340
+#define ETDM_IN1_CON5                        0x1344
+#define ETDM_IN1_CON6                        0x1348
+#define ETDM_IN1_CON7                        0x134c
+#define ETDM_IN1_CON8                        0x1350
+#define ETDM_IN1_CON9                        0x1354
+#define ETDM_IN1_MON                         0x1358
+#define ETDM_IN2_CON0                        0x1360
+#define ETDM_IN2_CON1                        0x1364
+#define ETDM_IN2_CON2                        0x1368
+#define ETDM_IN2_CON3                        0x136c
+#define ETDM_IN2_CON4                        0x1370
+#define ETDM_IN2_CON5                        0x1374
+#define ETDM_IN2_CON6                        0x1378
+#define ETDM_IN2_CON7                        0x137c
+#define ETDM_IN2_CON8                        0x1380
+#define ETDM_IN2_CON9                        0x1384
+#define ETDM_IN2_MON                         0x1388
+#define ETDM_IN3_CON0                        0x1390
+#define ETDM_IN3_CON1                        0x1394
+#define ETDM_IN3_CON2                        0x1398
+#define ETDM_IN3_CON3                        0x139c
+#define ETDM_IN3_CON4                        0x13a0
+#define ETDM_IN3_CON5                        0x13a4
+#define ETDM_IN3_CON6                        0x13a8
+#define ETDM_IN3_CON7                        0x13ac
+#define ETDM_IN3_CON8                        0x13b0
+#define ETDM_IN3_CON9                        0x13b4
+#define ETDM_IN3_MON                         0x13b8
+#define ETDM_IN4_CON0                        0x13c0
+#define ETDM_IN4_CON1                        0x13c4
+#define ETDM_IN4_CON2                        0x13c8
+#define ETDM_IN4_CON3                        0x13cc
+#define ETDM_IN4_CON4                        0x13d0
+#define ETDM_IN4_CON5                        0x13d4
+#define ETDM_IN4_CON6                        0x13d8
+#define ETDM_IN4_CON7                        0x13dc
+#define ETDM_IN4_CON8                        0x13e0
+#define ETDM_IN4_CON9                        0x13e4
+#define ETDM_IN4_MON                         0x13e8
+#define ETDM_IN5_CON0                        0x13f0
+#define ETDM_IN5_CON1                        0x13f4
+#define ETDM_IN5_CON2                        0x13f8
+#define ETDM_IN5_CON3                        0x13fc
+#define ETDM_IN5_CON4                        0x1400
+#define ETDM_IN5_CON5                        0x1404
+#define ETDM_IN5_CON6                        0x1408
+#define ETDM_IN5_CON7                        0x140c
+#define ETDM_IN5_CON8                        0x1410
+#define ETDM_IN5_CON9                        0x1414
+#define ETDM_IN5_MON                         0x1418
+#define ETDM_IN6_CON0                        0x1420
+#define ETDM_IN6_CON1                        0x1424
+#define ETDM_IN6_CON2                        0x1428
+#define ETDM_IN6_CON3                        0x142c
+#define ETDM_IN6_CON4                        0x1430
+#define ETDM_IN6_CON5                        0x1434
+#define ETDM_IN6_CON6                        0x1438
+#define ETDM_IN6_CON7                        0x143c
+#define ETDM_IN6_CON8                        0x1440
+#define ETDM_IN6_CON9                        0x1444
+#define ETDM_IN6_MON                         0x1448
+#define ETDM_OUT0_CON0                       0x1480
+#define ETDM_OUT0_CON1                       0x1484
+#define ETDM_OUT0_CON2                       0x1488
+#define ETDM_OUT0_CON3                       0x148c
+#define ETDM_OUT0_CON4                       0x1490
+#define ETDM_OUT0_CON5                       0x1494
+#define ETDM_OUT0_CON6                       0x1498
+#define ETDM_OUT0_CON7                       0x149c
+#define ETDM_OUT0_CON8                       0x14a0
+#define ETDM_OUT0_CON9                       0x14a4
+#define ETDM_OUT0_MON                        0x14a8
+#define ETDM_OUT1_CON0                       0x14c0
+#define ETDM_OUT1_CON1                       0x14c4
+#define ETDM_OUT1_CON2                       0x14c8
+#define ETDM_OUT1_CON3                       0x14cc
+#define ETDM_OUT1_CON4                       0x14d0
+#define ETDM_OUT1_CON5                       0x14d4
+#define ETDM_OUT1_CON6                       0x14d8
+#define ETDM_OUT1_CON7                       0x14dc
+#define ETDM_OUT1_CON8                       0x14e0
+#define ETDM_OUT1_CON9                       0x14e4
+#define ETDM_OUT1_MON                        0x14e8
+#define ETDM_OUT2_CON0                       0x1500
+#define ETDM_OUT2_CON1                       0x1504
+#define ETDM_OUT2_CON2                       0x1508
+#define ETDM_OUT2_CON3                       0x150c
+#define ETDM_OUT2_CON4                       0x1510
+#define ETDM_OUT2_CON5                       0x1514
+#define ETDM_OUT2_CON6                       0x1518
+#define ETDM_OUT2_CON7                       0x151c
+#define ETDM_OUT2_CON8                       0x1520
+#define ETDM_OUT2_CON9                       0x1524
+#define ETDM_OUT2_MON                        0x1528
+#define ETDM_OUT3_CON0                       0x1540
+#define ETDM_OUT3_CON1                       0x1544
+#define ETDM_OUT3_CON2                       0x1548
+#define ETDM_OUT3_CON3                       0x154c
+#define ETDM_OUT3_CON4                       0x1550
+#define ETDM_OUT3_CON5                       0x1554
+#define ETDM_OUT3_CON6                       0x1558
+#define ETDM_OUT3_CON7                       0x155c
+#define ETDM_OUT3_CON8                       0x1560
+#define ETDM_OUT3_CON9                       0x1564
+#define ETDM_OUT3_MON                        0x1568
+#define ETDM_OUT4_CON0                       0x1580
+#define ETDM_OUT4_CON1                       0x1584
+#define ETDM_OUT4_CON2                       0x1588
+#define ETDM_OUT4_CON3                       0x158c
+#define ETDM_OUT4_CON4                       0x1590
+#define ETDM_OUT4_CON5                       0x1594
+#define ETDM_OUT4_CON6                       0x1598
+#define ETDM_OUT4_CON7                       0x159c
+#define ETDM_OUT4_CON8                       0x15a0
+#define ETDM_OUT4_CON9                       0x15a4
+#define ETDM_OUT4_MON                        0x15a8
+#define ETDM_OUT5_CON0                       0x15c0
+#define ETDM_OUT5_CON1                       0x15c4
+#define ETDM_OUT5_CON2                       0x15c8
+#define ETDM_OUT5_CON3                       0x15cc
+#define ETDM_OUT5_CON4                       0x15d0
+#define ETDM_OUT5_CON5                       0x15d4
+#define ETDM_OUT5_CON6                       0x15d8
+#define ETDM_OUT5_CON7                       0x15dc
+#define ETDM_OUT5_CON8                       0x15e0
+#define ETDM_OUT5_CON9                       0x15e4
+#define ETDM_OUT5_MON                        0x15e8
+#define ETDM_OUT6_CON0                       0x1600
+#define ETDM_OUT6_CON1                       0x1604
+#define ETDM_OUT6_CON2                       0x1608
+#define ETDM_OUT6_CON3                       0x160c
+#define ETDM_OUT6_CON4                       0x1610
+#define ETDM_OUT6_CON5                       0x1614
+#define ETDM_OUT6_CON6                       0x1618
+#define ETDM_OUT6_CON7                       0x161c
+#define ETDM_OUT6_CON8                       0x1620
+#define ETDM_OUT6_CON9                       0x1624
+#define ETDM_OUT6_MON                        0x1628
+#define ETDM_0_3_COWORK_CON0                 0x1680
+#define ETDM_0_3_COWORK_CON1                 0x1684
+#define ETDM_0_3_COWORK_CON2                 0x1688
+#define ETDM_0_3_COWORK_CON3                 0x168c
+#define ETDM_4_7_COWORK_CON0                 0x1690
+#define ETDM_4_7_COWORK_CON1                 0x1694
+#define ETDM_4_7_COWORK_CON2                 0x1698
+#define ETDM_4_7_COWORK_CON3                 0x169c
+#define AFE_DPTX_CON                         0x2040
+#define AFE_DPTX_MON                         0x2044
+#define AFE_TDM_CON1                         0x2048
+#define AFE_TDM_CON2                         0x204c
+#define AFE_TDM_CON3                         0x2050
+#define AFE_TDM_OUT_MON                      0x2054
+#define AFE_HDMI_CONN0                       0x2078
+#define AFE_TDM_TOP_IP_VERSION               0x207c
+#define AFE_CONN004_0                        0x2100
+#define AFE_CONN004_1                        0x2104
+#define AFE_CONN004_2                        0x2108
+#define AFE_CONN004_4                        0x2110
+#define AFE_CONN004_5                        0x2114
+#define AFE_CONN004_6                        0x2118
+#define AFE_CONN004_7                        0x211c
+#define AFE_CONN005_0                        0x2120
+#define AFE_CONN005_1                        0x2124
+#define AFE_CONN005_2                        0x2128
+#define AFE_CONN005_4                        0x2130
+#define AFE_CONN005_5                        0x2134
+#define AFE_CONN005_6                        0x2138
+#define AFE_CONN005_7                        0x213c
+#define AFE_CONN006_0                        0x2140
+#define AFE_CONN006_1                        0x2144
+#define AFE_CONN006_2                        0x2148
+#define AFE_CONN006_4                        0x2150
+#define AFE_CONN006_5                        0x2154
+#define AFE_CONN006_6                        0x2158
+#define AFE_CONN006_7                        0x215c
+#define AFE_CONN007_0                        0x2160
+#define AFE_CONN007_1                        0x2164
+#define AFE_CONN007_2                        0x2168
+#define AFE_CONN007_4                        0x2170
+#define AFE_CONN007_5                        0x2174
+#define AFE_CONN007_6                        0x2178
+#define AFE_CONN007_7                        0x217c
+#define AFE_CONN008_0                        0x2180
+#define AFE_CONN008_1                        0x2184
+#define AFE_CONN008_2                        0x2188
+#define AFE_CONN008_4                        0x2190
+#define AFE_CONN008_5                        0x2194
+#define AFE_CONN008_6                        0x2198
+#define AFE_CONN008_7                        0x219c
+#define AFE_CONN009_0                        0x21a0
+#define AFE_CONN009_1                        0x21a4
+#define AFE_CONN009_2                        0x21a8
+#define AFE_CONN009_4                        0x21b0
+#define AFE_CONN009_5                        0x21b4
+#define AFE_CONN009_6                        0x21b8
+#define AFE_CONN009_7                        0x21bc
+#define AFE_CONN010_0                        0x21c0
+#define AFE_CONN010_1                        0x21c4
+#define AFE_CONN010_2                        0x21c8
+#define AFE_CONN010_4                        0x21d0
+#define AFE_CONN010_5                        0x21d4
+#define AFE_CONN010_6                        0x21d8
+#define AFE_CONN010_7                        0x21dc
+#define AFE_CONN011_0                        0x21e0
+#define AFE_CONN011_1                        0x21e4
+#define AFE_CONN011_2                        0x21e8
+#define AFE_CONN011_4                        0x21f0
+#define AFE_CONN011_5                        0x21f4
+#define AFE_CONN011_6                        0x21f8
+#define AFE_CONN011_7                        0x21fc
+#define AFE_CONN012_0                        0x2200
+#define AFE_CONN012_1                        0x2204
+#define AFE_CONN012_2                        0x2208
+#define AFE_CONN012_4                        0x2210
+#define AFE_CONN012_5                        0x2214
+#define AFE_CONN012_6                        0x2218
+#define AFE_CONN012_7                        0x221c
+#define AFE_CONN014_0                        0x2240
+#define AFE_CONN014_1                        0x2244
+#define AFE_CONN014_2                        0x2248
+#define AFE_CONN014_4                        0x2250
+#define AFE_CONN014_5                        0x2254
+#define AFE_CONN014_6                        0x2258
+#define AFE_CONN014_7                        0x225c
+#define AFE_CONN015_0                        0x2260
+#define AFE_CONN015_1                        0x2264
+#define AFE_CONN015_2                        0x2268
+#define AFE_CONN015_4                        0x2270
+#define AFE_CONN015_5                        0x2274
+#define AFE_CONN015_6                        0x2278
+#define AFE_CONN015_7                        0x227c
+#define AFE_CONN016_0                        0x2280
+#define AFE_CONN016_1                        0x2284
+#define AFE_CONN016_2                        0x2288
+#define AFE_CONN016_4                        0x2290
+#define AFE_CONN016_5                        0x2294
+#define AFE_CONN016_6                        0x2298
+#define AFE_CONN016_7                        0x229c
+#define AFE_CONN017_0                        0x22a0
+#define AFE_CONN017_1                        0x22a4
+#define AFE_CONN017_2                        0x22a8
+#define AFE_CONN017_4                        0x22b0
+#define AFE_CONN017_5                        0x22b4
+#define AFE_CONN017_6                        0x22b8
+#define AFE_CONN017_7                        0x22bc
+#define AFE_CONN018_0                        0x22c0
+#define AFE_CONN018_1                        0x22c4
+#define AFE_CONN018_2                        0x22c8
+#define AFE_CONN018_4                        0x22d0
+#define AFE_CONN018_5                        0x22d4
+#define AFE_CONN018_6                        0x22d8
+#define AFE_CONN018_7                        0x22dc
+#define AFE_CONN019_0                        0x22e0
+#define AFE_CONN019_1                        0x22e4
+#define AFE_CONN019_2                        0x22e8
+#define AFE_CONN019_4                        0x22f0
+#define AFE_CONN019_5                        0x22f4
+#define AFE_CONN019_6                        0x22f8
+#define AFE_CONN019_7                        0x22fc
+#define AFE_CONN020_0                        0x2300
+#define AFE_CONN020_1                        0x2304
+#define AFE_CONN020_2                        0x2308
+#define AFE_CONN020_4                        0x2310
+#define AFE_CONN020_5                        0x2314
+#define AFE_CONN020_6                        0x2318
+#define AFE_CONN020_7                        0x231c
+#define AFE_CONN021_0                        0x2320
+#define AFE_CONN021_1                        0x2324
+#define AFE_CONN021_2                        0x2328
+#define AFE_CONN021_4                        0x2330
+#define AFE_CONN021_5                        0x2334
+#define AFE_CONN021_6                        0x2338
+#define AFE_CONN021_7                        0x233c
+#define AFE_CONN022_0                        0x2340
+#define AFE_CONN022_1                        0x2344
+#define AFE_CONN022_2                        0x2348
+#define AFE_CONN022_4                        0x2350
+#define AFE_CONN022_5                        0x2354
+#define AFE_CONN022_6                        0x2358
+#define AFE_CONN022_7                        0x235c
+#define AFE_CONN023_0                        0x2360
+#define AFE_CONN023_1                        0x2364
+#define AFE_CONN023_2                        0x2368
+#define AFE_CONN023_4                        0x2370
+#define AFE_CONN023_5                        0x2374
+#define AFE_CONN023_6                        0x2378
+#define AFE_CONN023_7                        0x237c
+#define AFE_CONN024_0                        0x2380
+#define AFE_CONN024_1                        0x2384
+#define AFE_CONN024_2                        0x2388
+#define AFE_CONN024_4                        0x2390
+#define AFE_CONN024_5                        0x2394
+#define AFE_CONN024_6                        0x2398
+#define AFE_CONN024_7                        0x239c
+#define AFE_CONN025_0                        0x23a0
+#define AFE_CONN025_1                        0x23a4
+#define AFE_CONN025_2                        0x23a8
+#define AFE_CONN025_4                        0x23b0
+#define AFE_CONN025_5                        0x23b4
+#define AFE_CONN025_6                        0x23b8
+#define AFE_CONN025_7                        0x23bc
+#define AFE_CONN026_0                        0x23c0
+#define AFE_CONN026_1                        0x23c4
+#define AFE_CONN026_2                        0x23c8
+#define AFE_CONN026_4                        0x23d0
+#define AFE_CONN026_5                        0x23d4
+#define AFE_CONN026_6                        0x23d8
+#define AFE_CONN026_7                        0x23dc
+#define AFE_CONN027_0                        0x23e0
+#define AFE_CONN027_1                        0x23e4
+#define AFE_CONN027_2                        0x23e8
+#define AFE_CONN027_4                        0x23f0
+#define AFE_CONN027_5                        0x23f4
+#define AFE_CONN027_6                        0x23f8
+#define AFE_CONN027_7                        0x23fc
+#define AFE_CONN028_0                        0x2400
+#define AFE_CONN028_1                        0x2404
+#define AFE_CONN028_2                        0x2408
+#define AFE_CONN028_4                        0x2410
+#define AFE_CONN028_5                        0x2414
+#define AFE_CONN028_6                        0x2418
+#define AFE_CONN028_7                        0x241c
+#define AFE_CONN029_0                        0x2420
+#define AFE_CONN029_1                        0x2424
+#define AFE_CONN029_2                        0x2428
+#define AFE_CONN029_4                        0x2430
+#define AFE_CONN029_5                        0x2434
+#define AFE_CONN029_6                        0x2438
+#define AFE_CONN029_7                        0x243c
+#define AFE_CONN030_0                        0x2440
+#define AFE_CONN030_1                        0x2444
+#define AFE_CONN030_2                        0x2448
+#define AFE_CONN030_4                        0x2450
+#define AFE_CONN030_5                        0x2454
+#define AFE_CONN030_6                        0x2458
+#define AFE_CONN030_7                        0x245c
+#define AFE_CONN031_0                        0x2460
+#define AFE_CONN031_1                        0x2464
+#define AFE_CONN031_2                        0x2468
+#define AFE_CONN031_4                        0x2470
+#define AFE_CONN031_5                        0x2474
+#define AFE_CONN031_6                        0x2478
+#define AFE_CONN031_7                        0x247c
+#define AFE_CONN032_0                        0x2480
+#define AFE_CONN032_1                        0x2484
+#define AFE_CONN032_2                        0x2488
+#define AFE_CONN032_4                        0x2490
+#define AFE_CONN032_5                        0x2494
+#define AFE_CONN032_6                        0x2498
+#define AFE_CONN032_7                        0x249c
+#define AFE_CONN033_0                        0x24a0
+#define AFE_CONN033_1                        0x24a4
+#define AFE_CONN033_2                        0x24a8
+#define AFE_CONN033_4                        0x24b0
+#define AFE_CONN033_5                        0x24b4
+#define AFE_CONN033_6                        0x24b8
+#define AFE_CONN033_7                        0x24bc
+#define AFE_CONN034_0                        0x24c0
+#define AFE_CONN034_1                        0x24c4
+#define AFE_CONN034_2                        0x24c8
+#define AFE_CONN034_4                        0x24d0
+#define AFE_CONN034_5                        0x24d4
+#define AFE_CONN034_6                        0x24d8
+#define AFE_CONN034_7                        0x24dc
+#define AFE_CONN035_0                        0x24e0
+#define AFE_CONN035_1                        0x24e4
+#define AFE_CONN035_2                        0x24e8
+#define AFE_CONN035_4                        0x24f0
+#define AFE_CONN035_5                        0x24f4
+#define AFE_CONN035_6                        0x24f8
+#define AFE_CONN035_7                        0x24fc
+#define AFE_CONN036_0                        0x2500
+#define AFE_CONN036_1                        0x2504
+#define AFE_CONN036_2                        0x2508
+#define AFE_CONN036_4                        0x2510
+#define AFE_CONN036_5                        0x2514
+#define AFE_CONN036_6                        0x2518
+#define AFE_CONN036_7                        0x251c
+#define AFE_CONN037_0                        0x2520
+#define AFE_CONN037_1                        0x2524
+#define AFE_CONN037_2                        0x2528
+#define AFE_CONN037_4                        0x2530
+#define AFE_CONN037_5                        0x2534
+#define AFE_CONN037_6                        0x2538
+#define AFE_CONN037_7                        0x253c
+#define AFE_CONN038_0                        0x2540
+#define AFE_CONN038_1                        0x2544
+#define AFE_CONN038_2                        0x2548
+#define AFE_CONN038_4                        0x2550
+#define AFE_CONN038_5                        0x2554
+#define AFE_CONN038_6                        0x2558
+#define AFE_CONN038_7                        0x255c
+#define AFE_CONN039_0                        0x2560
+#define AFE_CONN039_1                        0x2564
+#define AFE_CONN039_2                        0x2568
+#define AFE_CONN039_4                        0x2570
+#define AFE_CONN039_5                        0x2574
+#define AFE_CONN039_6                        0x2578
+#define AFE_CONN039_7                        0x257c
+#define AFE_CONN040_0                        0x2580
+#define AFE_CONN040_1                        0x2584
+#define AFE_CONN040_2                        0x2588
+#define AFE_CONN040_4                        0x2590
+#define AFE_CONN040_5                        0x2594
+#define AFE_CONN040_6                        0x2598
+#define AFE_CONN040_7                        0x259c
+#define AFE_CONN041_0                        0x25a0
+#define AFE_CONN041_1                        0x25a4
+#define AFE_CONN041_2                        0x25a8
+#define AFE_CONN041_4                        0x25b0
+#define AFE_CONN041_5                        0x25b4
+#define AFE_CONN041_6                        0x25b8
+#define AFE_CONN041_7                        0x25bc
+#define AFE_CONN042_0                        0x25c0
+#define AFE_CONN042_1                        0x25c4
+#define AFE_CONN042_2                        0x25c8
+#define AFE_CONN042_4                        0x25d0
+#define AFE_CONN042_5                        0x25d4
+#define AFE_CONN042_6                        0x25d8
+#define AFE_CONN042_7                        0x25dc
+#define AFE_CONN043_0                        0x25e0
+#define AFE_CONN043_1                        0x25e4
+#define AFE_CONN043_2                        0x25e8
+#define AFE_CONN043_4                        0x25f0
+#define AFE_CONN043_5                        0x25f4
+#define AFE_CONN043_6                        0x25f8
+#define AFE_CONN043_7                        0x25fc
+#define AFE_CONN044_0                        0x2600
+#define AFE_CONN044_1                        0x2604
+#define AFE_CONN044_2                        0x2608
+#define AFE_CONN044_4                        0x2610
+#define AFE_CONN044_5                        0x2614
+#define AFE_CONN044_6                        0x2618
+#define AFE_CONN044_7                        0x261c
+#define AFE_CONN045_0                        0x2620
+#define AFE_CONN045_1                        0x2624
+#define AFE_CONN045_2                        0x2628
+#define AFE_CONN045_4                        0x2630
+#define AFE_CONN045_5                        0x2634
+#define AFE_CONN045_6                        0x2638
+#define AFE_CONN045_7                        0x263c
+#define AFE_CONN046_0                        0x2640
+#define AFE_CONN046_1                        0x2644
+#define AFE_CONN046_2                        0x2648
+#define AFE_CONN046_4                        0x2650
+#define AFE_CONN046_5                        0x2654
+#define AFE_CONN046_6                        0x2658
+#define AFE_CONN046_7                        0x265c
+#define AFE_CONN047_0                        0x2660
+#define AFE_CONN047_1                        0x2664
+#define AFE_CONN047_2                        0x2668
+#define AFE_CONN047_4                        0x2670
+#define AFE_CONN047_5                        0x2674
+#define AFE_CONN047_6                        0x2678
+#define AFE_CONN047_7                        0x267c
+#define AFE_CONN048_0                        0x2680
+#define AFE_CONN048_1                        0x2684
+#define AFE_CONN048_2                        0x2688
+#define AFE_CONN048_4                        0x2690
+#define AFE_CONN048_5                        0x2694
+#define AFE_CONN048_6                        0x2698
+#define AFE_CONN048_7                        0x269c
+#define AFE_CONN049_0                        0x26a0
+#define AFE_CONN049_1                        0x26a4
+#define AFE_CONN049_2                        0x26a8
+#define AFE_CONN049_4                        0x26b0
+#define AFE_CONN049_5                        0x26b4
+#define AFE_CONN049_6                        0x26b8
+#define AFE_CONN049_7                        0x26bc
+#define AFE_CONN050_0                        0x26c0
+#define AFE_CONN050_1                        0x26c4
+#define AFE_CONN050_2                        0x26c8
+#define AFE_CONN050_4                        0x26d0
+#define AFE_CONN050_5                        0x26d4
+#define AFE_CONN050_6                        0x26d8
+#define AFE_CONN050_7                        0x26dc
+#define AFE_CONN051_0                        0x26e0
+#define AFE_CONN051_1                        0x26e4
+#define AFE_CONN051_2                        0x26e8
+#define AFE_CONN051_4                        0x26f0
+#define AFE_CONN051_5                        0x26f4
+#define AFE_CONN051_6                        0x26f8
+#define AFE_CONN051_7                        0x26fc
+#define AFE_CONN052_0                        0x2700
+#define AFE_CONN052_1                        0x2704
+#define AFE_CONN052_2                        0x2708
+#define AFE_CONN052_4                        0x2710
+#define AFE_CONN052_5                        0x2714
+#define AFE_CONN052_6                        0x2718
+#define AFE_CONN052_7                        0x271c
+#define AFE_CONN053_0                        0x2720
+#define AFE_CONN053_1                        0x2724
+#define AFE_CONN053_2                        0x2728
+#define AFE_CONN053_4                        0x2730
+#define AFE_CONN053_5                        0x2734
+#define AFE_CONN053_6                        0x2738
+#define AFE_CONN053_7                        0x273c
+#define AFE_CONN054_0                        0x2740
+#define AFE_CONN054_1                        0x2744
+#define AFE_CONN054_2                        0x2748
+#define AFE_CONN054_4                        0x2750
+#define AFE_CONN054_5                        0x2754
+#define AFE_CONN054_6                        0x2758
+#define AFE_CONN054_7                        0x275c
+#define AFE_CONN055_0                        0x2760
+#define AFE_CONN055_1                        0x2764
+#define AFE_CONN055_2                        0x2768
+#define AFE_CONN055_4                        0x2770
+#define AFE_CONN055_5                        0x2774
+#define AFE_CONN055_6                        0x2778
+#define AFE_CONN055_7                        0x277c
+#define AFE_CONN056_0                        0x2780
+#define AFE_CONN056_1                        0x2784
+#define AFE_CONN056_2                        0x2788
+#define AFE_CONN056_4                        0x2790
+#define AFE_CONN056_5                        0x2794
+#define AFE_CONN056_6                        0x2798
+#define AFE_CONN056_7                        0x279c
+#define AFE_CONN057_0                        0x27a0
+#define AFE_CONN057_1                        0x27a4
+#define AFE_CONN057_2                        0x27a8
+#define AFE_CONN057_4                        0x27b0
+#define AFE_CONN057_5                        0x27b4
+#define AFE_CONN057_6                        0x27b8
+#define AFE_CONN057_7                        0x27bc
+#define AFE_CONN058_0                        0x27c0
+#define AFE_CONN058_1                        0x27c4
+#define AFE_CONN058_2                        0x27c8
+#define AFE_CONN058_4                        0x27d0
+#define AFE_CONN058_5                        0x27d4
+#define AFE_CONN058_6                        0x27d8
+#define AFE_CONN058_7                        0x27dc
+#define AFE_CONN059_0                        0x27e0
+#define AFE_CONN059_1                        0x27e4
+#define AFE_CONN059_2                        0x27e8
+#define AFE_CONN059_4                        0x27f0
+#define AFE_CONN059_5                        0x27f4
+#define AFE_CONN059_6                        0x27f8
+#define AFE_CONN059_7                        0x27fc
+#define AFE_CONN060_0                        0x2800
+#define AFE_CONN060_1                        0x2804
+#define AFE_CONN060_2                        0x2808
+#define AFE_CONN060_4                        0x2810
+#define AFE_CONN060_5                        0x2814
+#define AFE_CONN060_6                        0x2818
+#define AFE_CONN060_7                        0x281c
+#define AFE_CONN061_0                        0x2820
+#define AFE_CONN061_1                        0x2824
+#define AFE_CONN061_2                        0x2828
+#define AFE_CONN061_4                        0x2830
+#define AFE_CONN061_5                        0x2834
+#define AFE_CONN061_6                        0x2838
+#define AFE_CONN061_7                        0x283c
+#define AFE_CONN062_0                        0x2840
+#define AFE_CONN062_1                        0x2844
+#define AFE_CONN062_2                        0x2848
+#define AFE_CONN062_4                        0x2850
+#define AFE_CONN062_5                        0x2854
+#define AFE_CONN062_6                        0x2858
+#define AFE_CONN062_7                        0x285c
+#define AFE_CONN063_0                        0x2860
+#define AFE_CONN063_1                        0x2864
+#define AFE_CONN063_2                        0x2868
+#define AFE_CONN063_4                        0x2870
+#define AFE_CONN063_5                        0x2874
+#define AFE_CONN063_6                        0x2878
+#define AFE_CONN063_7                        0x287c
+#define AFE_CONN064_0                        0x2880
+#define AFE_CONN064_1                        0x2884
+#define AFE_CONN064_2                        0x2888
+#define AFE_CONN064_4                        0x2890
+#define AFE_CONN064_5                        0x2894
+#define AFE_CONN064_6                        0x2898
+#define AFE_CONN064_7                        0x289c
+#define AFE_CONN065_0                        0x28a0
+#define AFE_CONN065_1                        0x28a4
+#define AFE_CONN065_2                        0x28a8
+#define AFE_CONN065_4                        0x28b0
+#define AFE_CONN065_5                        0x28b4
+#define AFE_CONN065_6                        0x28b8
+#define AFE_CONN065_7                        0x28bc
+#define AFE_CONN066_0                        0x28c0
+#define AFE_CONN066_1                        0x28c4
+#define AFE_CONN066_2                        0x28c8
+#define AFE_CONN066_4                        0x28d0
+#define AFE_CONN066_5                        0x28d4
+#define AFE_CONN066_6                        0x28d8
+#define AFE_CONN066_7                        0x28dc
+#define AFE_CONN067_0                        0x28e0
+#define AFE_CONN067_1                        0x28e4
+#define AFE_CONN067_2                        0x28e8
+#define AFE_CONN067_4                        0x28f0
+#define AFE_CONN067_5                        0x28f4
+#define AFE_CONN067_6                        0x28f8
+#define AFE_CONN067_7                        0x28fc
+#define AFE_CONN068_0                        0x2900
+#define AFE_CONN068_1                        0x2904
+#define AFE_CONN068_2                        0x2908
+#define AFE_CONN068_4                        0x2910
+#define AFE_CONN068_5                        0x2914
+#define AFE_CONN068_6                        0x2918
+#define AFE_CONN068_7                        0x291c
+#define AFE_CONN069_0                        0x2920
+#define AFE_CONN069_1                        0x2924
+#define AFE_CONN069_2                        0x2928
+#define AFE_CONN069_4                        0x2930
+#define AFE_CONN069_5                        0x2934
+#define AFE_CONN069_6                        0x2938
+#define AFE_CONN069_7                        0x293c
+#define AFE_CONN070_0                        0x2940
+#define AFE_CONN070_1                        0x2944
+#define AFE_CONN070_2                        0x2948
+#define AFE_CONN070_4                        0x2950
+#define AFE_CONN070_5                        0x2954
+#define AFE_CONN070_6                        0x2958
+#define AFE_CONN070_7                        0x295c
+#define AFE_CONN071_0                        0x2960
+#define AFE_CONN071_1                        0x2964
+#define AFE_CONN071_2                        0x2968
+#define AFE_CONN071_4                        0x2970
+#define AFE_CONN071_5                        0x2974
+#define AFE_CONN071_6                        0x2978
+#define AFE_CONN071_7                        0x297c
+#define AFE_CONN072_0                        0x2980
+#define AFE_CONN072_1                        0x2984
+#define AFE_CONN072_2                        0x2988
+#define AFE_CONN072_4                        0x2990
+#define AFE_CONN072_5                        0x2994
+#define AFE_CONN072_6                        0x2998
+#define AFE_CONN072_7                        0x299c
+#define AFE_CONN073_0                        0x29a0
+#define AFE_CONN073_1                        0x29a4
+#define AFE_CONN073_2                        0x29a8
+#define AFE_CONN073_4                        0x29b0
+#define AFE_CONN073_5                        0x29b4
+#define AFE_CONN073_6                        0x29b8
+#define AFE_CONN073_7                        0x29bc
+#define AFE_CONN074_0                        0x29c0
+#define AFE_CONN074_1                        0x29c4
+#define AFE_CONN074_2                        0x29c8
+#define AFE_CONN074_4                        0x29d0
+#define AFE_CONN074_5                        0x29d4
+#define AFE_CONN074_6                        0x29d8
+#define AFE_CONN074_7                        0x29dc
+#define AFE_CONN075_0                        0x29e0
+#define AFE_CONN075_1                        0x29e4
+#define AFE_CONN075_2                        0x29e8
+#define AFE_CONN075_4                        0x29f0
+#define AFE_CONN075_5                        0x29f4
+#define AFE_CONN075_6                        0x29f8
+#define AFE_CONN075_7                        0x29fc
+#define AFE_CONN076_0                        0x2a00
+#define AFE_CONN076_1                        0x2a04
+#define AFE_CONN076_2                        0x2a08
+#define AFE_CONN076_4                        0x2a10
+#define AFE_CONN076_5                        0x2a14
+#define AFE_CONN076_6                        0x2a18
+#define AFE_CONN076_7                        0x2a1c
+#define AFE_CONN077_0                        0x2a20
+#define AFE_CONN077_1                        0x2a24
+#define AFE_CONN077_2                        0x2a28
+#define AFE_CONN077_4                        0x2a30
+#define AFE_CONN077_5                        0x2a34
+#define AFE_CONN077_6                        0x2a38
+#define AFE_CONN077_7                        0x2a3c
+#define AFE_CONN078_0                        0x2a40
+#define AFE_CONN078_1                        0x2a44
+#define AFE_CONN078_2                        0x2a48
+#define AFE_CONN078_4                        0x2a50
+#define AFE_CONN078_5                        0x2a54
+#define AFE_CONN078_6                        0x2a58
+#define AFE_CONN078_7                        0x2a5c
+#define AFE_CONN079_0                        0x2a60
+#define AFE_CONN079_1                        0x2a64
+#define AFE_CONN079_2                        0x2a68
+#define AFE_CONN079_4                        0x2a70
+#define AFE_CONN079_5                        0x2a74
+#define AFE_CONN079_6                        0x2a78
+#define AFE_CONN079_7                        0x2a7c
+#define AFE_CONN080_0                        0x2a80
+#define AFE_CONN080_1                        0x2a84
+#define AFE_CONN080_2                        0x2a88
+#define AFE_CONN080_4                        0x2a90
+#define AFE_CONN080_5                        0x2a94
+#define AFE_CONN080_6                        0x2a98
+#define AFE_CONN080_7                        0x2a9c
+#define AFE_CONN081_0                        0x2aa0
+#define AFE_CONN081_1                        0x2aa4
+#define AFE_CONN081_2                        0x2aa8
+#define AFE_CONN081_4                        0x2ab0
+#define AFE_CONN081_5                        0x2ab4
+#define AFE_CONN081_6                        0x2ab8
+#define AFE_CONN081_7                        0x2abc
+#define AFE_CONN082_0                        0x2ac0
+#define AFE_CONN082_1                        0x2ac4
+#define AFE_CONN082_2                        0x2ac8
+#define AFE_CONN082_4                        0x2ad0
+#define AFE_CONN082_5                        0x2ad4
+#define AFE_CONN082_6                        0x2ad8
+#define AFE_CONN082_7                        0x2adc
+#define AFE_CONN083_0                        0x2ae0
+#define AFE_CONN083_1                        0x2ae4
+#define AFE_CONN083_2                        0x2ae8
+#define AFE_CONN083_4                        0x2af0
+#define AFE_CONN083_5                        0x2af4
+#define AFE_CONN083_6                        0x2af8
+#define AFE_CONN083_7                        0x2afc
+#define AFE_CONN084_0                        0x2b00
+#define AFE_CONN084_1                        0x2b04
+#define AFE_CONN084_2                        0x2b08
+#define AFE_CONN084_4                        0x2b10
+#define AFE_CONN084_5                        0x2b14
+#define AFE_CONN084_6                        0x2b18
+#define AFE_CONN084_7                        0x2b1c
+#define AFE_CONN085_0                        0x2b20
+#define AFE_CONN085_1                        0x2b24
+#define AFE_CONN085_2                        0x2b28
+#define AFE_CONN085_4                        0x2b30
+#define AFE_CONN085_5                        0x2b34
+#define AFE_CONN085_6                        0x2b38
+#define AFE_CONN085_7                        0x2b3c
+#define AFE_CONN086_0                        0x2b40
+#define AFE_CONN086_1                        0x2b44
+#define AFE_CONN086_2                        0x2b48
+#define AFE_CONN086_4                        0x2b50
+#define AFE_CONN086_5                        0x2b54
+#define AFE_CONN086_6                        0x2b58
+#define AFE_CONN086_7                        0x2b5c
+#define AFE_CONN087_0                        0x2b60
+#define AFE_CONN087_1                        0x2b64
+#define AFE_CONN087_2                        0x2b68
+#define AFE_CONN087_4                        0x2b70
+#define AFE_CONN087_5                        0x2b74
+#define AFE_CONN087_6                        0x2b78
+#define AFE_CONN087_7                        0x2b7c
+#define AFE_CONN088_0                        0x2b80
+#define AFE_CONN088_1                        0x2b84
+#define AFE_CONN088_2                        0x2b88
+#define AFE_CONN088_4                        0x2b90
+#define AFE_CONN088_5                        0x2b94
+#define AFE_CONN088_6                        0x2b98
+#define AFE_CONN088_7                        0x2b9c
+#define AFE_CONN089_0                        0x2ba0
+#define AFE_CONN089_1                        0x2ba4
+#define AFE_CONN089_2                        0x2ba8
+#define AFE_CONN089_4                        0x2bb0
+#define AFE_CONN089_5                        0x2bb4
+#define AFE_CONN089_6                        0x2bb8
+#define AFE_CONN089_7                        0x2bbc
+#define AFE_CONN090_0                        0x2bc0
+#define AFE_CONN090_1                        0x2bc4
+#define AFE_CONN090_2                        0x2bc8
+#define AFE_CONN090_4                        0x2bd0
+#define AFE_CONN090_5                        0x2bd4
+#define AFE_CONN090_6                        0x2bd8
+#define AFE_CONN090_7                        0x2bdc
+#define AFE_CONN091_0                        0x2be0
+#define AFE_CONN091_1                        0x2be4
+#define AFE_CONN091_2                        0x2be8
+#define AFE_CONN091_4                        0x2bf0
+#define AFE_CONN091_5                        0x2bf4
+#define AFE_CONN091_6                        0x2bf8
+#define AFE_CONN091_7                        0x2bfc
+#define AFE_CONN092_0                        0x2c00
+#define AFE_CONN092_1                        0x2c04
+#define AFE_CONN092_2                        0x2c08
+#define AFE_CONN092_4                        0x2c10
+#define AFE_CONN092_5                        0x2c14
+#define AFE_CONN092_6                        0x2c18
+#define AFE_CONN092_7                        0x2c1c
+#define AFE_CONN093_0                        0x2c20
+#define AFE_CONN093_1                        0x2c24
+#define AFE_CONN093_2                        0x2c28
+#define AFE_CONN093_4                        0x2c30
+#define AFE_CONN093_5                        0x2c34
+#define AFE_CONN093_6                        0x2c38
+#define AFE_CONN093_7                        0x2c3c
+#define AFE_CONN094_0                        0x2c40
+#define AFE_CONN094_1                        0x2c44
+#define AFE_CONN094_2                        0x2c48
+#define AFE_CONN094_4                        0x2c50
+#define AFE_CONN094_5                        0x2c54
+#define AFE_CONN094_6                        0x2c58
+#define AFE_CONN094_7                        0x2c5c
+#define AFE_CONN095_0                        0x2c60
+#define AFE_CONN095_1                        0x2c64
+#define AFE_CONN095_2                        0x2c68
+#define AFE_CONN095_4                        0x2c70
+#define AFE_CONN095_5                        0x2c74
+#define AFE_CONN095_6                        0x2c78
+#define AFE_CONN095_7                        0x2c7c
+#define AFE_CONN096_0                        0x2c80
+#define AFE_CONN096_1                        0x2c84
+#define AFE_CONN096_2                        0x2c88
+#define AFE_CONN096_4                        0x2c90
+#define AFE_CONN096_5                        0x2c94
+#define AFE_CONN096_6                        0x2c98
+#define AFE_CONN096_7                        0x2c9c
+#define AFE_CONN097_0                        0x2ca0
+#define AFE_CONN097_1                        0x2ca4
+#define AFE_CONN097_2                        0x2ca8
+#define AFE_CONN097_4                        0x2cb0
+#define AFE_CONN097_5                        0x2cb4
+#define AFE_CONN097_6                        0x2cb8
+#define AFE_CONN097_7                        0x2cbc
+#define AFE_CONN098_0                        0x2cc0
+#define AFE_CONN098_1                        0x2cc4
+#define AFE_CONN098_2                        0x2cc8
+#define AFE_CONN098_4                        0x2cd0
+#define AFE_CONN098_5                        0x2cd4
+#define AFE_CONN098_6                        0x2cd8
+#define AFE_CONN098_7                        0x2cdc
+#define AFE_CONN099_0                        0x2ce0
+#define AFE_CONN099_1                        0x2ce4
+#define AFE_CONN099_2                        0x2ce8
+#define AFE_CONN099_4                        0x2cf0
+#define AFE_CONN099_5                        0x2cf4
+#define AFE_CONN099_6                        0x2cf8
+#define AFE_CONN099_7                        0x2cfc
+#define AFE_CONN100_0                        0x2d00
+#define AFE_CONN100_1                        0x2d04
+#define AFE_CONN100_2                        0x2d08
+#define AFE_CONN100_4                        0x2d10
+#define AFE_CONN100_5                        0x2d14
+#define AFE_CONN100_6                        0x2d18
+#define AFE_CONN100_7                        0x2d1c
+#define AFE_CONN102_0                        0x2d40
+#define AFE_CONN102_1                        0x2d44
+#define AFE_CONN102_2                        0x2d48
+#define AFE_CONN102_4                        0x2d50
+#define AFE_CONN102_5                        0x2d54
+#define AFE_CONN102_6                        0x2d58
+#define AFE_CONN102_7                        0x2d5c
+#define AFE_CONN103_0                        0x2d60
+#define AFE_CONN103_1                        0x2d64
+#define AFE_CONN103_2                        0x2d68
+#define AFE_CONN103_4                        0x2d70
+#define AFE_CONN103_5                        0x2d74
+#define AFE_CONN103_6                        0x2d78
+#define AFE_CONN103_7                        0x2d7c
+#define AFE_CONN104_0                        0x2d80
+#define AFE_CONN104_1                        0x2d84
+#define AFE_CONN104_2                        0x2d88
+#define AFE_CONN104_4                        0x2d90
+#define AFE_CONN104_5                        0x2d94
+#define AFE_CONN104_6                        0x2d98
+#define AFE_CONN104_7                        0x2d9c
+#define AFE_CONN105_0                        0x2da0
+#define AFE_CONN105_1                        0x2da4
+#define AFE_CONN105_2                        0x2da8
+#define AFE_CONN105_4                        0x2db0
+#define AFE_CONN105_5                        0x2db4
+#define AFE_CONN105_6                        0x2db8
+#define AFE_CONN105_7                        0x2dbc
+#define AFE_CONN106_0                        0x2dc0
+#define AFE_CONN106_1                        0x2dc4
+#define AFE_CONN106_2                        0x2dc8
+#define AFE_CONN106_4                        0x2dd0
+#define AFE_CONN106_5                        0x2dd4
+#define AFE_CONN106_6                        0x2dd8
+#define AFE_CONN106_7                        0x2ddc
+#define AFE_CONN108_0                        0x2e00
+#define AFE_CONN108_1                        0x2e04
+#define AFE_CONN108_2                        0x2e08
+#define AFE_CONN108_4                        0x2e10
+#define AFE_CONN108_5                        0x2e14
+#define AFE_CONN108_6                        0x2e18
+#define AFE_CONN108_7                        0x2e1c
+#define AFE_CONN109_0                        0x2e20
+#define AFE_CONN109_1                        0x2e24
+#define AFE_CONN109_2                        0x2e28
+#define AFE_CONN109_4                        0x2e30
+#define AFE_CONN109_5                        0x2e34
+#define AFE_CONN109_6                        0x2e38
+#define AFE_CONN109_7                        0x2e3c
+#define AFE_CONN110_0                        0x2e40
+#define AFE_CONN110_1                        0x2e44
+#define AFE_CONN110_2                        0x2e48
+#define AFE_CONN110_4                        0x2e50
+#define AFE_CONN110_5                        0x2e54
+#define AFE_CONN110_6                        0x2e58
+#define AFE_CONN110_7                        0x2e5c
+#define AFE_CONN111_0                        0x2e60
+#define AFE_CONN111_1                        0x2e64
+#define AFE_CONN111_2                        0x2e68
+#define AFE_CONN111_4                        0x2e70
+#define AFE_CONN111_5                        0x2e74
+#define AFE_CONN111_6                        0x2e78
+#define AFE_CONN111_7                        0x2e7c
+#define AFE_CONN112_0                        0x2e80
+#define AFE_CONN112_1                        0x2e84
+#define AFE_CONN112_2                        0x2e88
+#define AFE_CONN112_4                        0x2e90
+#define AFE_CONN112_5                        0x2e94
+#define AFE_CONN112_6                        0x2e98
+#define AFE_CONN112_7                        0x2e9c
+#define AFE_CONN113_0                        0x2ea0
+#define AFE_CONN113_1                        0x2ea4
+#define AFE_CONN113_2                        0x2ea8
+#define AFE_CONN113_4                        0x2eb0
+#define AFE_CONN113_5                        0x2eb4
+#define AFE_CONN113_6                        0x2eb8
+#define AFE_CONN113_7                        0x2ebc
+#define AFE_CONN114_0                        0x2ec0
+#define AFE_CONN114_1                        0x2ec4
+#define AFE_CONN114_2                        0x2ec8
+#define AFE_CONN114_4                        0x2ed0
+#define AFE_CONN114_5                        0x2ed4
+#define AFE_CONN114_6                        0x2ed8
+#define AFE_CONN114_7                        0x2edc
+#define AFE_CONN115_0                        0x2ee0
+#define AFE_CONN115_1                        0x2ee4
+#define AFE_CONN115_2                        0x2ee8
+#define AFE_CONN115_4                        0x2ef0
+#define AFE_CONN115_5                        0x2ef4
+#define AFE_CONN115_6                        0x2ef8
+#define AFE_CONN115_7                        0x2efc
+#define AFE_CONN116_0                        0x2f00
+#define AFE_CONN116_1                        0x2f04
+#define AFE_CONN116_2                        0x2f08
+#define AFE_CONN116_4                        0x2f10
+#define AFE_CONN116_5                        0x2f14
+#define AFE_CONN116_6                        0x2f18
+#define AFE_CONN116_7                        0x2f1c
+#define AFE_CONN117_0                        0x2f20
+#define AFE_CONN117_1                        0x2f24
+#define AFE_CONN117_2                        0x2f28
+#define AFE_CONN117_4                        0x2f30
+#define AFE_CONN117_5                        0x2f34
+#define AFE_CONN117_6                        0x2f38
+#define AFE_CONN117_7                        0x2f3c
+#define AFE_CONN118_0                        0x2f40
+#define AFE_CONN118_1                        0x2f44
+#define AFE_CONN118_2                        0x2f48
+#define AFE_CONN118_4                        0x2f50
+#define AFE_CONN118_5                        0x2f54
+#define AFE_CONN118_6                        0x2f58
+#define AFE_CONN118_7                        0x2f5c
+#define AFE_CONN119_0                        0x2f60
+#define AFE_CONN119_1                        0x2f64
+#define AFE_CONN119_2                        0x2f68
+#define AFE_CONN119_4                        0x2f70
+#define AFE_CONN119_5                        0x2f74
+#define AFE_CONN119_6                        0x2f78
+#define AFE_CONN119_7                        0x2f7c
+#define AFE_CONN120_0                        0x2f80
+#define AFE_CONN120_1                        0x2f84
+#define AFE_CONN120_2                        0x2f88
+#define AFE_CONN120_4                        0x2f90
+#define AFE_CONN120_5                        0x2f94
+#define AFE_CONN120_6                        0x2f98
+#define AFE_CONN120_7                        0x2f9c
+#define AFE_CONN121_0                        0x2fa0
+#define AFE_CONN121_1                        0x2fa4
+#define AFE_CONN121_2                        0x2fa8
+#define AFE_CONN121_4                        0x2fb0
+#define AFE_CONN121_5                        0x2fb4
+#define AFE_CONN121_6                        0x2fb8
+#define AFE_CONN121_7                        0x2fbc
+#define AFE_CONN122_0                        0x2fc0
+#define AFE_CONN122_1                        0x2fc4
+#define AFE_CONN122_2                        0x2fc8
+#define AFE_CONN122_4                        0x2fd0
+#define AFE_CONN122_5                        0x2fd4
+#define AFE_CONN122_6                        0x2fd8
+#define AFE_CONN122_7                        0x2fdc
+#define AFE_CONN123_0                        0x2fe0
+#define AFE_CONN123_1                        0x2fe4
+#define AFE_CONN123_2                        0x2fe8
+#define AFE_CONN123_4                        0x2ff0
+#define AFE_CONN123_5                        0x2ff4
+#define AFE_CONN123_6                        0x2ff8
+#define AFE_CONN123_7                        0x2ffc
+#define AFE_CONN124_0                        0x3000
+#define AFE_CONN124_1                        0x3004
+#define AFE_CONN124_2                        0x3008
+#define AFE_CONN124_4                        0x3010
+#define AFE_CONN124_5                        0x3014
+#define AFE_CONN124_6                        0x3018
+#define AFE_CONN124_7                        0x301c
+#define AFE_CONN125_0                        0x3020
+#define AFE_CONN125_1                        0x3024
+#define AFE_CONN125_2                        0x3028
+#define AFE_CONN125_4                        0x3030
+#define AFE_CONN125_5                        0x3034
+#define AFE_CONN125_6                        0x3038
+#define AFE_CONN125_7                        0x303c
+#define AFE_CONN126_0                        0x3040
+#define AFE_CONN126_1                        0x3044
+#define AFE_CONN126_2                        0x3048
+#define AFE_CONN126_4                        0x3050
+#define AFE_CONN126_5                        0x3054
+#define AFE_CONN126_6                        0x3058
+#define AFE_CONN126_7                        0x305c
+#define AFE_CONN127_0                        0x3060
+#define AFE_CONN127_1                        0x3064
+#define AFE_CONN127_2                        0x3068
+#define AFE_CONN127_4                        0x3070
+#define AFE_CONN127_5                        0x3074
+#define AFE_CONN127_6                        0x3078
+#define AFE_CONN127_7                        0x307c
+#define AFE_CONN128_0                        0x3080
+#define AFE_CONN128_1                        0x3084
+#define AFE_CONN128_2                        0x3088
+#define AFE_CONN128_4                        0x3090
+#define AFE_CONN128_5                        0x3094
+#define AFE_CONN128_6                        0x3098
+#define AFE_CONN128_7                        0x309c
+#define AFE_CONN129_0                        0x30a0
+#define AFE_CONN129_1                        0x30a4
+#define AFE_CONN129_2                        0x30a8
+#define AFE_CONN129_4                        0x30b0
+#define AFE_CONN129_5                        0x30b4
+#define AFE_CONN129_6                        0x30b8
+#define AFE_CONN129_7                        0x30bc
+#define AFE_CONN130_0                        0x30c0
+#define AFE_CONN130_1                        0x30c4
+#define AFE_CONN130_2                        0x30c8
+#define AFE_CONN130_4                        0x30d0
+#define AFE_CONN130_5                        0x30d4
+#define AFE_CONN130_6                        0x30d8
+#define AFE_CONN130_7                        0x30dc
+#define AFE_CONN131_0                        0x30e0
+#define AFE_CONN131_1                        0x30e4
+#define AFE_CONN131_2                        0x30e8
+#define AFE_CONN131_4                        0x30f0
+#define AFE_CONN131_5                        0x30f4
+#define AFE_CONN131_6                        0x30f8
+#define AFE_CONN131_7                        0x30fc
+#define AFE_CONN132_0                        0x3100
+#define AFE_CONN132_1                        0x3104
+#define AFE_CONN132_2                        0x3108
+#define AFE_CONN132_4                        0x3110
+#define AFE_CONN132_5                        0x3114
+#define AFE_CONN132_6                        0x3118
+#define AFE_CONN132_7                        0x311c
+#define AFE_CONN133_0                        0x3120
+#define AFE_CONN133_1                        0x3124
+#define AFE_CONN133_2                        0x3128
+#define AFE_CONN133_4                        0x3130
+#define AFE_CONN133_5                        0x3134
+#define AFE_CONN133_6                        0x3138
+#define AFE_CONN133_7                        0x313c
+#define AFE_CONN134_0                        0x3140
+#define AFE_CONN134_1                        0x3144
+#define AFE_CONN134_2                        0x3148
+#define AFE_CONN134_4                        0x3150
+#define AFE_CONN134_5                        0x3154
+#define AFE_CONN134_6                        0x3158
+#define AFE_CONN134_7                        0x315c
+#define AFE_CONN135_0                        0x3160
+#define AFE_CONN135_1                        0x3164
+#define AFE_CONN135_2                        0x3168
+#define AFE_CONN135_4                        0x3170
+#define AFE_CONN135_5                        0x3174
+#define AFE_CONN135_6                        0x3178
+#define AFE_CONN135_7                        0x317c
+#define AFE_CONN136_0                        0x3180
+#define AFE_CONN136_1                        0x3184
+#define AFE_CONN136_2                        0x3188
+#define AFE_CONN136_4                        0x3190
+#define AFE_CONN136_5                        0x3194
+#define AFE_CONN136_6                        0x3198
+#define AFE_CONN136_7                        0x319c
+#define AFE_CONN137_0                        0x31a0
+#define AFE_CONN137_1                        0x31a4
+#define AFE_CONN137_2                        0x31a8
+#define AFE_CONN137_4                        0x31b0
+#define AFE_CONN137_5                        0x31b4
+#define AFE_CONN137_6                        0x31b8
+#define AFE_CONN137_7                        0x31bc
+#define AFE_CONN138_0                        0x31c0
+#define AFE_CONN138_1                        0x31c4
+#define AFE_CONN138_2                        0x31c8
+#define AFE_CONN138_4                        0x31d0
+#define AFE_CONN138_5                        0x31d4
+#define AFE_CONN138_6                        0x31d8
+#define AFE_CONN138_7                        0x31dc
+#define AFE_CONN139_0                        0x31e0
+#define AFE_CONN139_1                        0x31e4
+#define AFE_CONN139_2                        0x31e8
+#define AFE_CONN139_4                        0x31f0
+#define AFE_CONN139_5                        0x31f4
+#define AFE_CONN139_6                        0x31f8
+#define AFE_CONN139_7                        0x31fc
+#define AFE_CONN148_0                        0x3300
+#define AFE_CONN148_1                        0x3304
+#define AFE_CONN148_2                        0x3308
+#define AFE_CONN148_4                        0x3310
+#define AFE_CONN148_5                        0x3314
+#define AFE_CONN148_6                        0x3318
+#define AFE_CONN148_7                        0x331c
+#define AFE_CONN149_0                        0x3320
+#define AFE_CONN149_1                        0x3324
+#define AFE_CONN149_2                        0x3328
+#define AFE_CONN149_4                        0x3330
+#define AFE_CONN149_5                        0x3334
+#define AFE_CONN149_6                        0x3338
+#define AFE_CONN149_7                        0x333c
+#define AFE_CONN180_0                        0x3700
+#define AFE_CONN180_1                        0x3704
+#define AFE_CONN180_2                        0x3708
+#define AFE_CONN180_4                        0x3710
+#define AFE_CONN180_5                        0x3714
+#define AFE_CONN180_6                        0x3718
+#define AFE_CONN180_7                        0x371c
+#define AFE_CONN181_0                        0x3720
+#define AFE_CONN181_1                        0x3724
+#define AFE_CONN181_2                        0x3728
+#define AFE_CONN181_4                        0x3730
+#define AFE_CONN181_5                        0x3734
+#define AFE_CONN181_6                        0x3738
+#define AFE_CONN181_7                        0x373c
+#define AFE_CONN182_0                        0x3740
+#define AFE_CONN182_1                        0x3744
+#define AFE_CONN182_2                        0x3748
+#define AFE_CONN182_4                        0x3750
+#define AFE_CONN182_5                        0x3754
+#define AFE_CONN182_6                        0x3758
+#define AFE_CONN182_7                        0x375c
+#define AFE_CONN183_0                        0x3760
+#define AFE_CONN183_1                        0x3764
+#define AFE_CONN183_2                        0x3768
+#define AFE_CONN183_4                        0x3770
+#define AFE_CONN183_5                        0x3774
+#define AFE_CONN183_6                        0x3778
+#define AFE_CONN183_7                        0x377c
+#define AFE_CONN184_0                        0x3780
+#define AFE_CONN184_1                        0x3784
+#define AFE_CONN184_2                        0x3788
+#define AFE_CONN184_4                        0x3790
+#define AFE_CONN184_5                        0x3794
+#define AFE_CONN184_6                        0x3798
+#define AFE_CONN184_7                        0x379c
+#define AFE_CONN185_0                        0x37a0
+#define AFE_CONN185_1                        0x37a4
+#define AFE_CONN185_2                        0x37a8
+#define AFE_CONN185_4                        0x37b0
+#define AFE_CONN185_5                        0x37b4
+#define AFE_CONN185_6                        0x37b8
+#define AFE_CONN185_7                        0x37bc
+#define AFE_CONN186_0                        0x37c0
+#define AFE_CONN186_1                        0x37c4
+#define AFE_CONN186_2                        0x37c8
+#define AFE_CONN186_4                        0x37d0
+#define AFE_CONN186_5                        0x37d4
+#define AFE_CONN186_6                        0x37d8
+#define AFE_CONN186_7                        0x37dc
+#define AFE_CONN187_0                        0x37e0
+#define AFE_CONN187_1                        0x37e4
+#define AFE_CONN187_2                        0x37e8
+#define AFE_CONN187_4                        0x37f0
+#define AFE_CONN187_5                        0x37f4
+#define AFE_CONN187_6                        0x37f8
+#define AFE_CONN187_7                        0x37fc
+#define AFE_CONN188_0                        0x3800
+#define AFE_CONN188_1                        0x3804
+#define AFE_CONN188_2                        0x3808
+#define AFE_CONN188_4                        0x3810
+#define AFE_CONN188_5                        0x3814
+#define AFE_CONN188_6                        0x3818
+#define AFE_CONN188_7                        0x381c
+#define AFE_CONN189_0                        0x3820
+#define AFE_CONN189_1                        0x3824
+#define AFE_CONN189_2                        0x3828
+#define AFE_CONN189_4                        0x3830
+#define AFE_CONN189_5                        0x3834
+#define AFE_CONN189_6                        0x3838
+#define AFE_CONN189_7                        0x383c
+#define AFE_CONN190_0                        0x3840
+#define AFE_CONN190_1                        0x3844
+#define AFE_CONN190_2                        0x3848
+#define AFE_CONN190_4                        0x3850
+#define AFE_CONN190_5                        0x3854
+#define AFE_CONN190_6                        0x3858
+#define AFE_CONN190_7                        0x385c
+#define AFE_CONN191_0                        0x3860
+#define AFE_CONN191_1                        0x3864
+#define AFE_CONN191_2                        0x3868
+#define AFE_CONN191_4                        0x3870
+#define AFE_CONN191_5                        0x3874
+#define AFE_CONN191_6                        0x3878
+#define AFE_CONN191_7                        0x387c
+#define AFE_CONN192_0                        0x3880
+#define AFE_CONN192_1                        0x3884
+#define AFE_CONN192_2                        0x3888
+#define AFE_CONN192_4                        0x3890
+#define AFE_CONN192_5                        0x3894
+#define AFE_CONN192_6                        0x3898
+#define AFE_CONN192_7                        0x389c
+#define AFE_CONN193_0                        0x38a0
+#define AFE_CONN193_1                        0x38a4
+#define AFE_CONN193_2                        0x38a8
+#define AFE_CONN193_4                        0x38b0
+#define AFE_CONN193_5                        0x38b4
+#define AFE_CONN193_6                        0x38b8
+#define AFE_CONN193_7                        0x38bc
+#define AFE_CONN194_0                        0x38c0
+#define AFE_CONN194_1                        0x38c4
+#define AFE_CONN194_2                        0x38c8
+#define AFE_CONN194_4                        0x38d0
+#define AFE_CONN194_5                        0x38d4
+#define AFE_CONN194_6                        0x38d8
+#define AFE_CONN194_7                        0x38dc
+#define AFE_CONN195_0                        0x38e0
+#define AFE_CONN195_1                        0x38e4
+#define AFE_CONN195_2                        0x38e8
+#define AFE_CONN195_4                        0x38f0
+#define AFE_CONN195_5                        0x38f4
+#define AFE_CONN195_6                        0x38f8
+#define AFE_CONN195_7                        0x38fc
+#define AFE_CONN196_0                        0x3900
+#define AFE_CONN196_1                        0x3904
+#define AFE_CONN196_2                        0x3908
+#define AFE_CONN196_4                        0x3910
+#define AFE_CONN196_5                        0x3914
+#define AFE_CONN196_6                        0x3918
+#define AFE_CONN196_7                        0x391c
+#define AFE_CONN197_0                        0x3920
+#define AFE_CONN197_1                        0x3924
+#define AFE_CONN197_2                        0x3928
+#define AFE_CONN197_4                        0x3930
+#define AFE_CONN197_5                        0x3934
+#define AFE_CONN197_6                        0x3938
+#define AFE_CONN197_7                        0x393c
+#define AFE_CONN198_0                        0x3940
+#define AFE_CONN198_1                        0x3944
+#define AFE_CONN198_2                        0x3948
+#define AFE_CONN198_4                        0x3950
+#define AFE_CONN198_5                        0x3954
+#define AFE_CONN198_6                        0x3958
+#define AFE_CONN198_7                        0x395c
+#define AFE_CONN199_0                        0x3960
+#define AFE_CONN199_1                        0x3964
+#define AFE_CONN199_2                        0x3968
+#define AFE_CONN199_4                        0x3970
+#define AFE_CONN199_5                        0x3974
+#define AFE_CONN199_6                        0x3978
+#define AFE_CONN199_7                        0x397c
+#define AFE_CONN200_0                        0x3980
+#define AFE_CONN200_1                        0x3984
+#define AFE_CONN200_2                        0x3988
+#define AFE_CONN200_4                        0x3990
+#define AFE_CONN200_5                        0x3994
+#define AFE_CONN200_6                        0x3998
+#define AFE_CONN200_7                        0x399c
+#define AFE_CONN201_0                        0x39a0
+#define AFE_CONN201_1                        0x39a4
+#define AFE_CONN201_2                        0x39a8
+#define AFE_CONN201_4                        0x39b0
+#define AFE_CONN201_5                        0x39b4
+#define AFE_CONN201_6                        0x39b8
+#define AFE_CONN201_7                        0x39bc
+#define AFE_CONN202_0                        0x39c0
+#define AFE_CONN202_1                        0x39c4
+#define AFE_CONN202_2                        0x39c8
+#define AFE_CONN202_4                        0x39d0
+#define AFE_CONN202_5                        0x39d4
+#define AFE_CONN202_6                        0x39d8
+#define AFE_CONN202_7                        0x39dc
+#define AFE_CONN203_0                        0x39e0
+#define AFE_CONN203_1                        0x39e4
+#define AFE_CONN203_2                        0x39e8
+#define AFE_CONN203_4                        0x39f0
+#define AFE_CONN203_5                        0x39f4
+#define AFE_CONN203_6                        0x39f8
+#define AFE_CONN203_7                        0x39fc
+#define AFE_CONN204_0                        0x3a00
+#define AFE_CONN204_1                        0x3a04
+#define AFE_CONN204_2                        0x3a08
+#define AFE_CONN204_4                        0x3a10
+#define AFE_CONN204_5                        0x3a14
+#define AFE_CONN204_6                        0x3a18
+#define AFE_CONN204_7                        0x3a1c
+#define AFE_CONN205_0                        0x3a20
+#define AFE_CONN205_1                        0x3a24
+#define AFE_CONN205_2                        0x3a28
+#define AFE_CONN205_4                        0x3a30
+#define AFE_CONN205_5                        0x3a34
+#define AFE_CONN205_6                        0x3a38
+#define AFE_CONN205_7                        0x3a3c
+#define AFE_CONN206_0                        0x3a40
+#define AFE_CONN206_1                        0x3a44
+#define AFE_CONN206_2                        0x3a48
+#define AFE_CONN206_4                        0x3a50
+#define AFE_CONN206_5                        0x3a54
+#define AFE_CONN206_6                        0x3a58
+#define AFE_CONN206_7                        0x3a5c
+#define AFE_CONN207_0                        0x3a60
+#define AFE_CONN207_1                        0x3a64
+#define AFE_CONN207_2                        0x3a68
+#define AFE_CONN207_4                        0x3a70
+#define AFE_CONN207_5                        0x3a74
+#define AFE_CONN207_6                        0x3a78
+#define AFE_CONN207_7                        0x3a7c
+#define AFE_CONN208_0                        0x3a80
+#define AFE_CONN208_1                        0x3a84
+#define AFE_CONN208_2                        0x3a88
+#define AFE_CONN208_4                        0x3a90
+#define AFE_CONN208_5                        0x3a94
+#define AFE_CONN208_6                        0x3a98
+#define AFE_CONN208_7                        0x3a9c
+#define AFE_CONN209_0                        0x3aa0
+#define AFE_CONN209_1                        0x3aa4
+#define AFE_CONN209_2                        0x3aa8
+#define AFE_CONN209_4                        0x3ab0
+#define AFE_CONN209_5                        0x3ab4
+#define AFE_CONN209_6                        0x3ab8
+#define AFE_CONN209_7                        0x3abc
+#define AFE_CONN210_0                        0x3ac0
+#define AFE_CONN210_1                        0x3ac4
+#define AFE_CONN210_2                        0x3ac8
+#define AFE_CONN210_4                        0x3ad0
+#define AFE_CONN210_5                        0x3ad4
+#define AFE_CONN210_6                        0x3ad8
+#define AFE_CONN210_7                        0x3adc
+#define AFE_CONN211_0                        0x3ae0
+#define AFE_CONN211_1                        0x3ae4
+#define AFE_CONN211_2                        0x3ae8
+#define AFE_CONN211_4                        0x3af0
+#define AFE_CONN211_5                        0x3af4
+#define AFE_CONN211_6                        0x3af8
+#define AFE_CONN211_7                        0x3afc
+#define AFE_CONN_MON_CFG                     0x4080
+#define AFE_CONN_MON0                        0x4084
+#define AFE_CONN_MON1                        0x4088
+#define AFE_CONN_MON2                        0x408c
+#define AFE_CONN_MON3                        0x4090
+#define AFE_CONN_MON4                        0x4094
+#define AFE_CONN_MON5                        0x4098
+#define AFE_CONN_RS_0                        0x40a0
+#define AFE_CONN_RS_1                        0x40a4
+#define AFE_CONN_RS_2                        0x40a8
+#define AFE_CONN_RS_3                        0x40ac
+#define AFE_CONN_RS_4                        0x40b0
+#define AFE_CONN_RS_5                        0x40b4
+#define AFE_CONN_RS_6                        0x40b8
+#define AFE_CONN_DI_0                        0x40c0
+#define AFE_CONN_DI_1                        0x40c4
+#define AFE_CONN_DI_2                        0x40c8
+#define AFE_CONN_DI_3                        0x40cc
+#define AFE_CONN_DI_4                        0x40d0
+#define AFE_CONN_DI_5                        0x40d4
+#define AFE_CONN_DI_6                        0x40d8
+#define AFE_CONN_16BIT_0                     0x40e0
+#define AFE_CONN_16BIT_1                     0x40e4
+#define AFE_CONN_16BIT_2                     0x40e8
+#define AFE_CONN_16BIT_3                     0x40ec
+#define AFE_CONN_16BIT_4                     0x40f0
+#define AFE_CONN_16BIT_5                     0x40f4
+#define AFE_CONN_16BIT_6                     0x40f8
+#define AFE_CONN_24BIT_0                     0x4100
+#define AFE_CONN_24BIT_1                     0x4104
+#define AFE_CONN_24BIT_2                     0x4108
+#define AFE_CONN_24BIT_3                     0x410c
+#define AFE_CONN_24BIT_4                     0x4110
+#define AFE_CONN_24BIT_5                     0x4114
+#define AFE_CONN_24BIT_6                     0x4118
+#define AFE_CBIP_CFG0                        0x4380
+#define AFE_CBIP_SLV_DECODER_MON0            0x4384
+#define AFE_CBIP_SLV_DECODER_MON1            0x4388
+#define AFE_CBIP_SLV_MUX_MON_CFG             0x438c
+#define AFE_CBIP_SLV_MUX_MON0                0x4390
+#define AFE_CBIP_SLV_MUX_MON1                0x4394
+#define AFE_MEMIF_CON0                       0x4400
+#define AFE_MEMIF_ONE_HEART                  0x4420
+#define AFE_DL0_BASE_MSB                     0x4440
+#define AFE_DL0_BASE                         0x4444
+#define AFE_DL0_CUR_MSB                      0x4448
+#define AFE_DL0_CUR                          0x444c
+#define AFE_DL0_END_MSB                      0x4450
+#define AFE_DL0_END                          0x4454
+#define AFE_DL0_RCH_MON                      0x4458
+#define AFE_DL0_LCH_MON                      0x445c
+#define AFE_DL0_CON0                         0x4460
+#define AFE_DL0_MON0                         0x4464
+#define AFE_DL1_BASE_MSB                     0x4470
+#define AFE_DL1_BASE                         0x4474
+#define AFE_DL1_CUR_MSB                      0x4478
+#define AFE_DL1_CUR                          0x447c
+#define AFE_DL1_END_MSB                      0x4480
+#define AFE_DL1_END                          0x4484
+#define AFE_DL1_RCH_MON                      0x4488
+#define AFE_DL1_LCH_MON                      0x448c
+#define AFE_DL1_CON0                         0x4490
+#define AFE_DL1_MON0                         0x4494
+#define AFE_DL2_BASE_MSB                     0x44a0
+#define AFE_DL2_BASE                         0x44a4
+#define AFE_DL2_CUR_MSB                      0x44a8
+#define AFE_DL2_CUR                          0x44ac
+#define AFE_DL2_END_MSB                      0x44b0
+#define AFE_DL2_END                          0x44b4
+#define AFE_DL2_RCH_MON                      0x44b8
+#define AFE_DL2_LCH_MON                      0x44bc
+#define AFE_DL2_CON0                         0x44c0
+#define AFE_DL2_MON0                         0x44c4
+#define AFE_DL3_BASE_MSB                     0x44d0
+#define AFE_DL3_BASE                         0x44d4
+#define AFE_DL3_CUR_MSB                      0x44d8
+#define AFE_DL3_CUR                          0x44dc
+#define AFE_DL3_END_MSB                      0x44e0
+#define AFE_DL3_END                          0x44e4
+#define AFE_DL3_RCH_MON                      0x44e8
+#define AFE_DL3_LCH_MON                      0x44ec
+#define AFE_DL3_CON0                         0x44f0
+#define AFE_DL3_MON0                         0x44f4
+#define AFE_DL4_BASE_MSB                     0x4500
+#define AFE_DL4_BASE                         0x4504
+#define AFE_DL4_CUR_MSB                      0x4508
+#define AFE_DL4_CUR                          0x450c
+#define AFE_DL4_END_MSB                      0x4510
+#define AFE_DL4_END                          0x4514
+#define AFE_DL4_RCH_MON                      0x4518
+#define AFE_DL4_LCH_MON                      0x451c
+#define AFE_DL4_CON0                         0x4520
+#define AFE_DL4_MON0                         0x4524
+#define AFE_DL5_BASE_MSB                     0x4530
+#define AFE_DL5_BASE                         0x4534
+#define AFE_DL5_CUR_MSB                      0x4538
+#define AFE_DL5_CUR                          0x453c
+#define AFE_DL5_END_MSB                      0x4540
+#define AFE_DL5_END                          0x4544
+#define AFE_DL5_RCH_MON                      0x4548
+#define AFE_DL5_LCH_MON                      0x454c
+#define AFE_DL5_CON0                         0x4550
+#define AFE_DL5_MON0                         0x4554
+#define AFE_DL6_BASE_MSB                     0x4560
+#define AFE_DL6_BASE                         0x4564
+#define AFE_DL6_CUR_MSB                      0x4568
+#define AFE_DL6_CUR                          0x456c
+#define AFE_DL6_END_MSB                      0x4570
+#define AFE_DL6_END                          0x4574
+#define AFE_DL6_RCH_MON                      0x4578
+#define AFE_DL6_LCH_MON                      0x457c
+#define AFE_DL6_CON0                         0x4580
+#define AFE_DL6_MON0                         0x4584
+#define AFE_DL7_BASE_MSB                     0x4590
+#define AFE_DL7_BASE                         0x4594
+#define AFE_DL7_CUR_MSB                      0x4598
+#define AFE_DL7_CUR                          0x459c
+#define AFE_DL7_END_MSB                      0x45a0
+#define AFE_DL7_END                          0x45a4
+#define AFE_DL7_RCH_MON                      0x45a8
+#define AFE_DL7_LCH_MON                      0x45ac
+#define AFE_DL7_CON0                         0x45b0
+#define AFE_DL7_MON0                         0x45b4
+#define AFE_DL8_BASE_MSB                     0x45c0
+#define AFE_DL8_BASE                         0x45c4
+#define AFE_DL8_CUR_MSB                      0x45c8
+#define AFE_DL8_CUR                          0x45cc
+#define AFE_DL8_END_MSB                      0x45d0
+#define AFE_DL8_END                          0x45d4
+#define AFE_DL8_RCH_MON                      0x45d8
+#define AFE_DL8_LCH_MON                      0x45dc
+#define AFE_DL8_CON0                         0x45e0
+#define AFE_DL8_MON0                         0x45e4
+#define AFE_DL_4CH_BASE_MSB                  0x45f0
+#define AFE_DL_4CH_BASE                      0x45f4
+#define AFE_DL_4CH_CUR_MSB                   0x45f8
+#define AFE_DL_4CH_CUR                       0x45fc
+#define AFE_DL_4CH_END_MSB                   0x4600
+#define AFE_DL_4CH_END                       0x4604
+#define AFE_DL_4CH_CON0                      0x4610
+#define AFE_DL_4CH_MON0                      0x4618
+#define AFE_DL_24CH_BASE_MSB                 0x4620
+#define AFE_DL_24CH_BASE                     0x4624
+#define AFE_DL_24CH_CUR_MSB                  0x4628
+#define AFE_DL_24CH_CUR                      0x462c
+#define AFE_DL_24CH_END_MSB                  0x4630
+#define AFE_DL_24CH_END                      0x4634
+#define AFE_DL_24CH_CON0                     0x4640
+#define AFE_DL_24CH_MON0                     0x4648
+#define AFE_DL23_BASE_MSB                    0x4680
+#define AFE_DL23_BASE                        0x4684
+#define AFE_DL23_CUR_MSB                     0x4688
+#define AFE_DL23_CUR                         0x468c
+#define AFE_DL23_END_MSB                     0x4690
+#define AFE_DL23_END                         0x4694
+#define AFE_DL23_RCH_MON                     0x4698
+#define AFE_DL23_LCH_MON                     0x469c
+#define AFE_DL23_CON0                        0x46a0
+#define AFE_DL23_MON0                        0x46a4
+#define AFE_DL24_BASE_MSB                    0x46b0
+#define AFE_DL24_BASE                        0x46b4
+#define AFE_DL24_CUR_MSB                     0x46b8
+#define AFE_DL24_CUR                         0x46bc
+#define AFE_DL24_END_MSB                     0x46c0
+#define AFE_DL24_END                         0x46c4
+#define AFE_DL24_RCH_MON                     0x46c8
+#define AFE_DL24_LCH_MON                     0x46cc
+#define AFE_DL24_CON0                        0x46d0
+#define AFE_DL24_MON0                        0x46d4
+#define AFE_DL25_BASE_MSB                    0x46e0
+#define AFE_DL25_BASE                        0x46e4
+#define AFE_DL25_CUR_MSB                     0x46e8
+#define AFE_DL25_CUR                         0x46ec
+#define AFE_DL25_END_MSB                     0x46f0
+#define AFE_DL25_END                         0x46f4
+#define AFE_DL25_RCH_MON                     0x46f8
+#define AFE_DL25_LCH_MON                     0x46fc
+#define AFE_DL25_CON0                        0x4700
+#define AFE_DL25_MON0                        0x4704
+#define AFE_DL26_BASE_MSB                    0x4710
+#define AFE_DL26_BASE                        0x4714
+#define AFE_DL26_CUR_MSB                     0x4718
+#define AFE_DL26_CUR                         0x471c
+#define AFE_DL26_END_MSB                     0x4720
+#define AFE_DL26_END                         0x4724
+#define AFE_DL26_RCH_MON                     0x4728
+#define AFE_DL26_LCH_MON                     0x472c
+#define AFE_DL26_CON0                        0x4730
+#define AFE_DL26_MON0                        0x4734
+#define AFE_VUL0_BASE_MSB                    0x4d60
+#define AFE_VUL0_BASE                        0x4d64
+#define AFE_VUL0_CUR_MSB                     0x4d68
+#define AFE_VUL0_CUR                         0x4d6c
+#define AFE_VUL0_END_MSB                     0x4d70
+#define AFE_VUL0_END                         0x4d74
+#define AFE_VUL0_RCH_MON                     0x4d78
+#define AFE_VUL0_LCH_MON                     0x4d7c
+#define AFE_VUL0_CON0                        0x4d80
+#define AFE_VUL0_MON0                        0x4d84
+#define AFE_VUL1_BASE_MSB                    0x4d90
+#define AFE_VUL1_BASE                        0x4d94
+#define AFE_VUL1_CUR_MSB                     0x4d98
+#define AFE_VUL1_CUR                         0x4d9c
+#define AFE_VUL1_END_MSB                     0x4da0
+#define AFE_VUL1_END                         0x4da4
+#define AFE_VUL1_RCH_MON                     0x4da8
+#define AFE_VUL1_LCH_MON                     0x4dac
+#define AFE_VUL1_CON0                        0x4db0
+#define AFE_VUL1_MON0                        0x4db4
+#define AFE_VUL2_BASE_MSB                    0x4dc0
+#define AFE_VUL2_BASE                        0x4dc4
+#define AFE_VUL2_CUR_MSB                     0x4dc8
+#define AFE_VUL2_CUR                         0x4dcc
+#define AFE_VUL2_END_MSB                     0x4dd0
+#define AFE_VUL2_END                         0x4dd4
+#define AFE_VUL2_RCH_MON                     0x4dd8
+#define AFE_VUL2_LCH_MON                     0x4ddc
+#define AFE_VUL2_CON0                        0x4de0
+#define AFE_VUL2_MON0                        0x4de4
+#define AFE_VUL3_BASE_MSB                    0x4df0
+#define AFE_VUL3_BASE                        0x4df4
+#define AFE_VUL3_CUR_MSB                     0x4df8
+#define AFE_VUL3_CUR                         0x4dfc
+#define AFE_VUL3_END_MSB                     0x4e00
+#define AFE_VUL3_END                         0x4e04
+#define AFE_VUL3_RCH_MON                     0x4e08
+#define AFE_VUL3_LCH_MON                     0x4e0c
+#define AFE_VUL3_CON0                        0x4e10
+#define AFE_VUL3_MON0                        0x4e14
+#define AFE_VUL4_BASE_MSB                    0x4e20
+#define AFE_VUL4_BASE                        0x4e24
+#define AFE_VUL4_CUR_MSB                     0x4e28
+#define AFE_VUL4_CUR                         0x4e2c
+#define AFE_VUL4_END_MSB                     0x4e30
+#define AFE_VUL4_END                         0x4e34
+#define AFE_VUL4_RCH_MON                     0x4e38
+#define AFE_VUL4_LCH_MON                     0x4e3c
+#define AFE_VUL4_CON0                        0x4e40
+#define AFE_VUL4_MON0                        0x4e44
+#define AFE_VUL5_BASE_MSB                    0x4e50
+#define AFE_VUL5_BASE                        0x4e54
+#define AFE_VUL5_CUR_MSB                     0x4e58
+#define AFE_VUL5_CUR                         0x4e5c
+#define AFE_VUL5_END_MSB                     0x4e60
+#define AFE_VUL5_END                         0x4e64
+#define AFE_VUL5_RCH_MON                     0x4e68
+#define AFE_VUL5_LCH_MON                     0x4e6c
+#define AFE_VUL5_CON0                        0x4e70
+#define AFE_VUL5_MON0                        0x4e74
+#define AFE_VUL6_BASE_MSB                    0x4e80
+#define AFE_VUL6_BASE                        0x4e84
+#define AFE_VUL6_CUR_MSB                     0x4e88
+#define AFE_VUL6_CUR                         0x4e8c
+#define AFE_VUL6_END_MSB                     0x4e90
+#define AFE_VUL6_END                         0x4e94
+#define AFE_VUL6_RCH_MON                     0x4e98
+#define AFE_VUL6_LCH_MON                     0x4e9c
+#define AFE_VUL6_CON0                        0x4ea0
+#define AFE_VUL6_MON0                        0x4ea4
+#define AFE_VUL7_BASE_MSB                    0x4eb0
+#define AFE_VUL7_BASE                        0x4eb4
+#define AFE_VUL7_CUR_MSB                     0x4eb8
+#define AFE_VUL7_CUR                         0x4ebc
+#define AFE_VUL7_END_MSB                     0x4ec0
+#define AFE_VUL7_END                         0x4ec4
+#define AFE_VUL7_RCH_MON                     0x4ec8
+#define AFE_VUL7_LCH_MON                     0x4ecc
+#define AFE_VUL7_CON0                        0x4ed0
+#define AFE_VUL7_MON0                        0x4ed4
+#define AFE_VUL8_BASE_MSB                    0x4ee0
+#define AFE_VUL8_BASE                        0x4ee4
+#define AFE_VUL8_CUR_MSB                     0x4ee8
+#define AFE_VUL8_CUR                         0x4eec
+#define AFE_VUL8_END_MSB                     0x4ef0
+#define AFE_VUL8_END                         0x4ef4
+#define AFE_VUL8_RCH_MON                     0x4ef8
+#define AFE_VUL8_LCH_MON                     0x4efc
+#define AFE_VUL8_CON0                        0x4f00
+#define AFE_VUL8_MON0                        0x4f04
+#define AFE_VUL9_BASE_MSB                    0x4f10
+#define AFE_VUL9_BASE                        0x4f14
+#define AFE_VUL9_CUR_MSB                     0x4f18
+#define AFE_VUL9_CUR                         0x4f1c
+#define AFE_VUL9_END_MSB                     0x4f20
+#define AFE_VUL9_END                         0x4f24
+#define AFE_VUL9_RCH_MON                     0x4f28
+#define AFE_VUL9_LCH_MON                     0x4f2c
+#define AFE_VUL9_CON0                        0x4f30
+#define AFE_VUL9_MON0                        0x4f34
+#define AFE_VUL10_BASE_MSB                   0x4f40
+#define AFE_VUL10_BASE                       0x4f44
+#define AFE_VUL10_CUR_MSB                    0x4f48
+#define AFE_VUL10_CUR                        0x4f4c
+#define AFE_VUL10_END_MSB                    0x4f50
+#define AFE_VUL10_END                        0x4f54
+#define AFE_VUL10_RCH_MON                    0x4f58
+#define AFE_VUL10_LCH_MON                    0x4f5c
+#define AFE_VUL10_CON0                       0x4f60
+#define AFE_VUL10_MON0                       0x4f64
+#define AFE_VUL24_BASE_MSB                   0x4fa0
+#define AFE_VUL24_BASE                       0x4fa4
+#define AFE_VUL24_CUR_MSB                    0x4fa8
+#define AFE_VUL24_CUR                        0x4fac
+#define AFE_VUL24_END_MSB                    0x4fb0
+#define AFE_VUL24_END                        0x4fb4
+#define AFE_VUL24_CON0                       0x4fb8
+#define AFE_VUL24_MON0                       0x4fbc
+#define AFE_VUL25_BASE_MSB                   0x4fc0
+#define AFE_VUL25_BASE                       0x4fc4
+#define AFE_VUL25_CUR_MSB                    0x4fc8
+#define AFE_VUL25_CUR                        0x4fcc
+#define AFE_VUL25_END_MSB                    0x4fd0
+#define AFE_VUL25_END                        0x4fd4
+#define AFE_VUL25_CON0                       0x4fd8
+#define AFE_VUL25_MON0                       0x4fdc
+#define AFE_VUL26_BASE_MSB                   0x4fe0
+#define AFE_VUL26_BASE                       0x4fe4
+#define AFE_VUL26_CUR_MSB                    0x4fe8
+#define AFE_VUL26_CUR                        0x4fec
+#define AFE_VUL26_END_MSB                    0x4ff0
+#define AFE_VUL26_END                        0x4ff4
+#define AFE_VUL26_CON0                       0x4ff8
+#define AFE_VUL26_MON0                       0x4ffc
+#define AFE_VUL_CM0_BASE_MSB                 0x51c0
+#define AFE_VUL_CM0_BASE                     0x51c4
+#define AFE_VUL_CM0_CUR_MSB                  0x51c8
+#define AFE_VUL_CM0_CUR                      0x51cc
+#define AFE_VUL_CM0_END_MSB                  0x51d0
+#define AFE_VUL_CM0_END                      0x51d4
+#define AFE_VUL_CM0_CON0                     0x51d8
+#define AFE_VUL_CM1_BASE_MSB                 0x51e0
+#define AFE_VUL_CM1_BASE                     0x51e4
+#define AFE_VUL_CM1_CUR_MSB                  0x51e8
+#define AFE_VUL_CM1_CUR                      0x51ec
+#define AFE_VUL_CM1_END_MSB                  0x51f0
+#define AFE_VUL_CM1_END                      0x51f4
+#define AFE_VUL_CM1_CON0                     0x51f8
+#define AFE_VUL_CM2_BASE_MSB                 0x5200
+#define AFE_VUL_CM2_BASE                     0x5204
+#define AFE_VUL_CM2_CUR_MSB                  0x5208
+#define AFE_VUL_CM2_CUR                      0x520c
+#define AFE_VUL_CM2_END_MSB                  0x5210
+#define AFE_VUL_CM2_END                      0x5214
+#define AFE_VUL_CM2_CON0                     0x5218
+#define AFE_ETDM_IN0_BASE_MSB                0x5220
+#define AFE_ETDM_IN0_BASE                    0x5224
+#define AFE_ETDM_IN0_CUR_MSB                 0x5228
+#define AFE_ETDM_IN0_CUR                     0x522c
+#define AFE_ETDM_IN0_END_MSB                 0x5230
+#define AFE_ETDM_IN0_END                     0x5234
+#define AFE_ETDM_IN0_CON0                    0x5238
+#define AFE_ETDM_IN1_BASE_MSB                0x5240
+#define AFE_ETDM_IN1_BASE                    0x5244
+#define AFE_ETDM_IN1_CUR_MSB                 0x5248
+#define AFE_ETDM_IN1_CUR                     0x524c
+#define AFE_ETDM_IN1_END_MSB                 0x5250
+#define AFE_ETDM_IN1_END                     0x5254
+#define AFE_ETDM_IN1_CON0                    0x5258
+#define AFE_ETDM_IN2_BASE_MSB                0x5260
+#define AFE_ETDM_IN2_BASE                    0x5264
+#define AFE_ETDM_IN2_CUR_MSB                 0x5268
+#define AFE_ETDM_IN2_CUR                     0x526c
+#define AFE_ETDM_IN2_END_MSB                 0x5270
+#define AFE_ETDM_IN2_END                     0x5274
+#define AFE_ETDM_IN2_CON0                    0x5278
+#define AFE_ETDM_IN3_BASE_MSB                0x5280
+#define AFE_ETDM_IN3_BASE                    0x5284
+#define AFE_ETDM_IN3_CUR_MSB                 0x5288
+#define AFE_ETDM_IN3_CUR                     0x528c
+#define AFE_ETDM_IN3_END_MSB                 0x5290
+#define AFE_ETDM_IN3_END                     0x5294
+#define AFE_ETDM_IN3_CON0                    0x5298
+#define AFE_ETDM_IN4_BASE_MSB                0x52a0
+#define AFE_ETDM_IN4_BASE                    0x52a4
+#define AFE_ETDM_IN4_CUR_MSB                 0x52a8
+#define AFE_ETDM_IN4_CUR                     0x52ac
+#define AFE_ETDM_IN4_END_MSB                 0x52b0
+#define AFE_ETDM_IN4_END                     0x52b4
+#define AFE_ETDM_IN4_CON0                    0x52b8
+#define AFE_ETDM_IN5_BASE_MSB                0x52c0
+#define AFE_ETDM_IN5_BASE                    0x52c4
+#define AFE_ETDM_IN5_CUR_MSB                 0x52c8
+#define AFE_ETDM_IN5_CUR                     0x52cc
+#define AFE_ETDM_IN5_END_MSB                 0x52d0
+#define AFE_ETDM_IN5_END                     0x52d4
+#define AFE_ETDM_IN5_CON0                    0x52d8
+#define AFE_ETDM_IN6_BASE_MSB                0x52e0
+#define AFE_ETDM_IN6_BASE                    0x52e4
+#define AFE_ETDM_IN6_CUR_MSB                 0x52e8
+#define AFE_ETDM_IN6_CUR                     0x52ec
+#define AFE_ETDM_IN6_END_MSB                 0x52f0
+#define AFE_ETDM_IN6_END                     0x52f4
+#define AFE_ETDM_IN6_CON0                    0x52f8
+#define AFE_HDMI_OUT_BASE_MSB                0x5360
+#define AFE_HDMI_OUT_BASE                    0x5364
+#define AFE_HDMI_OUT_CUR_MSB                 0x5368
+#define AFE_HDMI_OUT_CUR                     0x536c
+#define AFE_HDMI_OUT_END_MSB                 0x5370
+#define AFE_HDMI_OUT_END                     0x5374
+#define AFE_HDMI_OUT_CON0                    0x5378
+#define AFE_VUL24_RCH_MON                    0x53e0
+#define AFE_VUL24_LCH_MON                    0x53e4
+#define AFE_VUL25_RCH_MON                    0x53e8
+#define AFE_VUL25_LCH_MON                    0x53ec
+#define AFE_VUL26_RCH_MON                    0x53f0
+#define AFE_VUL26_LCH_MON                    0x53f4
+#define AFE_VUL_CM0_RCH_MON                  0x5458
+#define AFE_VUL_CM0_LCH_MON                  0x545c
+#define AFE_VUL_CM1_RCH_MON                  0x5460
+#define AFE_VUL_CM1_LCH_MON                  0x5464
+#define AFE_VUL_CM2_RCH_MON                  0x5468
+#define AFE_VUL_CM2_LCH_MON                  0x546c
+#define AFE_DL_4CH_CH0_MON                   0x54f4
+#define AFE_DL_4CH_CH1_MON                   0x54f8
+#define AFE_DL_4CH_CH2_MON                   0x54fc
+#define AFE_DL_4CH_CH3_MON                   0x5500
+#define AFE_DL_24CH_CH0_MON                  0x5504
+#define AFE_DL_24CH_CH1_MON                  0x5508
+#define AFE_DL_24CH_CH2_MON                  0x550c
+#define AFE_DL_24CH_CH3_MON                  0x5510
+#define AFE_DL_24CH_CH4_MON                  0x5514
+#define AFE_DL_24CH_CH5_MON                  0x5518
+#define AFE_DL_24CH_CH6_MON                  0x551c
+#define AFE_DL_24CH_CH7_MON                  0x5520
+#define AFE_DL_24CH_CH8_MON                  0x5524
+#define AFE_DL_24CH_CH9_MON                  0x5528
+#define AFE_DL_24CH_CH10_MON                 0x552c
+#define AFE_DL_24CH_CH11_MON                 0x5530
+#define AFE_DL_24CH_CH12_MON                 0x5534
+#define AFE_DL_24CH_CH13_MON                 0x5538
+#define AFE_DL_24CH_CH14_MON                 0x553c
+#define AFE_DL_24CH_CH15_MON                 0x5540
+#define AFE_SRAM_BOUND                       0x5620
+#define AFE_SECURE_CON0                      0x5624
+#define AFE_SECURE_CON1                      0x5628
+#define AFE_SE_SECURE_CON0                   0x5630
+#define AFE_SE_SECURE_CON1                   0x5634
+#define AFE_SE_SECURE_CON2                   0x5638
+#define AFE_SE_SECURE_CON3                   0x563c
+#define AFE_SE_PROT_SIDEBAND0                0x5640
+#define AFE_SE_PROT_SIDEBAND1                0x5644
+#define AFE_SE_PROT_SIDEBAND2                0x5648
+#define AFE_SE_PROT_SIDEBAND3                0x564c
+#define AFE_SE_DOMAIN_SIDEBAND0              0x5650
+#define AFE_SE_DOMAIN_SIDEBAND1              0x5654
+#define AFE_SE_DOMAIN_SIDEBAND2              0x5658
+#define AFE_SE_DOMAIN_SIDEBAND3              0x565c
+#define AFE_SE_DOMAIN_SIDEBAND4              0x5660
+#define AFE_SE_DOMAIN_SIDEBAND5              0x5664
+#define AFE_SE_DOMAIN_SIDEBAND6              0x5668
+#define AFE_SE_DOMAIN_SIDEBAND7              0x566c
+#define AFE_SE_DOMAIN_SIDEBAND8              0x5670
+#define AFE_SE_DOMAIN_SIDEBAND9              0x5674
+#define AFE_PROT_SIDEBAND0_MON               0x5678
+#define AFE_PROT_SIDEBAND1_MON               0x567c
+#define AFE_PROT_SIDEBAND2_MON               0x5680
+#define AFE_PROT_SIDEBAND3_MON               0x5684
+#define AFE_DOMAIN_SIDEBAND0_MON             0x5688
+#define AFE_DOMAIN_SIDEBAND1_MON             0x568c
+#define AFE_DOMAIN_SIDEBAND2_MON             0x5690
+#define AFE_DOMAIN_SIDEBAND3_MON             0x5694
+#define AFE_DOMAIN_SIDEBAND4_MON             0x5698
+#define AFE_DOMAIN_SIDEBAND5_MON             0x569c
+#define AFE_DOMAIN_SIDEBAND6_MON             0x56a0
+#define AFE_DOMAIN_SIDEBAND7_MON             0x56a4
+#define AFE_DOMAIN_SIDEBAND8_MON             0x56a8
+#define AFE_DOMAIN_SIDEBAND9_MON             0x56ac
+#define AFE_SECURE_CONN0                     0x56b0
+#define AFE_SECURE_CONN_ETDM0                0x56b4
+#define AFE_SECURE_CONN_ETDM1                0x56b8
+#define AFE_SECURE_CONN_ETDM2                0x56bc
+#define AFE_SECURE_SRAM_CON0                 0x56c0
+#define AFE_SECURE_SRAM_CON1                 0x56c4
+#define AFE_SE_CONN_INPUT_MASK0              0x56d0
+#define AFE_SE_CONN_INPUT_MASK1              0x56d4
+#define AFE_SE_CONN_INPUT_MASK2              0x56d8
+#define AFE_SE_CONN_INPUT_MASK3              0x56dc
+#define AFE_SE_CONN_INPUT_MASK4              0x56e0
+#define AFE_SE_CONN_INPUT_MASK5              0x56e4
+#define AFE_SE_CONN_INPUT_MASK6              0x56e8
+#define AFE_SE_CONN_INPUT_MASK7              0x56ec
+#define AFE_NON_SE_CONN_INPUT_MASK0          0x56f0
+#define AFE_NON_SE_CONN_INPUT_MASK1          0x56f4
+#define AFE_NON_SE_CONN_INPUT_MASK2          0x56f8
+#define AFE_NON_SE_CONN_INPUT_MASK3          0x56fc
+#define AFE_NON_SE_CONN_INPUT_MASK4          0x5700
+#define AFE_NON_SE_CONN_INPUT_MASK5          0x5704
+#define AFE_NON_SE_CONN_INPUT_MASK6          0x5708
+#define AFE_NON_SE_CONN_INPUT_MASK7          0x570c
+#define AFE_SE_CONN_OUTPUT_SEL0              0x5710
+#define AFE_SE_CONN_OUTPUT_SEL1              0x5714
+#define AFE_SE_CONN_OUTPUT_SEL2              0x5718
+#define AFE_SE_CONN_OUTPUT_SEL3              0x571c
+#define AFE_SE_CONN_OUTPUT_SEL4              0x5720
+#define AFE_SE_CONN_OUTPUT_SEL5              0x5724
+#define AFE_SE_CONN_OUTPUT_SEL6              0x5728
+#define AFE_SE_CONN_OUTPUT_SEL7              0x572c
+#define AFE_PCM0_INTF_CON1_MASK_MON          0x5730
+#define AFE_PCM0_INTF_CON0_MASK_MON          0x5734
+#define AFE_CONNSYS_I2S_CON_MASK_MON         0x5738
+#define AFE_TDM_CON2_MASK_MON                0x5744
+#define AFE_MTKAIF0_CFG0_MASK_MON            0x574c
+#define AFE_MTKAIF1_CFG0_MASK_MON            0x5750
+#define AFE_ADDA_UL0_SRC_CON0_MASK_MON       0x5754
+#define AFE_ADDA_UL1_SRC_CON0_MASK_MON       0x5758
+#define AFE_ADDA_UL2_SRC_CON0_MASK_MON       0x575c
+#define AFE_ASRC_NEW_CON0                    0x7800
+#define AFE_ASRC_NEW_CON1                    0x7804
+#define AFE_ASRC_NEW_CON2                    0x7808
+#define AFE_ASRC_NEW_CON3                    0x780c
+#define AFE_ASRC_NEW_CON4                    0x7810
+#define AFE_ASRC_NEW_CON5                    0x7814
+#define AFE_ASRC_NEW_CON6                    0x7818
+#define AFE_ASRC_NEW_CON7                    0x781c
+#define AFE_ASRC_NEW_CON8                    0x7820
+#define AFE_ASRC_NEW_CON9                    0x7824
+#define AFE_ASRC_NEW_CON10                   0x7828
+#define AFE_ASRC_NEW_CON11                   0x782c
+#define AFE_ASRC_NEW_CON12                   0x7830
+#define AFE_ASRC_NEW_CON13                   0x7834
+#define AFE_ASRC_NEW_CON14                   0x7838
+#define AFE_ASRC_NEW_IP_VERSION              0x783c
+#define AFE_GASRC0_NEW_CON0                  0x7840
+#define AFE_GASRC0_NEW_CON1                  0x7844
+#define AFE_GASRC0_NEW_CON2                  0x7848
+#define AFE_GASRC0_NEW_CON3                  0x784c
+#define AFE_GASRC0_NEW_CON4                  0x7850
+#define AFE_GASRC0_NEW_CON5                  0x7854
+#define AFE_GASRC0_NEW_CON6                  0x7858
+#define AFE_GASRC0_NEW_CON7                  0x785c
+#define AFE_GASRC0_NEW_CON8                  0x7860
+#define AFE_GASRC0_NEW_CON9                  0x7864
+#define AFE_GASRC0_NEW_CON10                 0x7868
+#define AFE_GASRC0_NEW_CON11                 0x786c
+#define AFE_GASRC0_NEW_CON12                 0x7870
+#define AFE_GASRC0_NEW_CON13                 0x7874
+#define AFE_GASRC0_NEW_CON14                 0x7878
+#define AFE_GASRC0_NEW_IP_VERSION            0x787c
+#define AFE_GASRC1_NEW_CON0                  0x7880
+#define AFE_GASRC1_NEW_CON1                  0x7884
+#define AFE_GASRC1_NEW_CON2                  0x7888
+#define AFE_GASRC1_NEW_CON3                  0x788c
+#define AFE_GASRC1_NEW_CON4                  0x7890
+#define AFE_GASRC1_NEW_CON5                  0x7894
+#define AFE_GASRC1_NEW_CON6                  0x7898
+#define AFE_GASRC1_NEW_CON7                  0x789c
+#define AFE_GASRC1_NEW_CON8                  0x78a0
+#define AFE_GASRC1_NEW_CON9                  0x78a4
+#define AFE_GASRC1_NEW_CON10                 0x78a8
+#define AFE_GASRC1_NEW_CON11                 0x78ac
+#define AFE_GASRC1_NEW_CON12                 0x78b0
+#define AFE_GASRC1_NEW_CON13                 0x78b4
+#define AFE_GASRC1_NEW_CON14                 0x78b8
+#define AFE_GASRC1_NEW_IP_VERSION            0x78bc
+#define AFE_GASRC2_NEW_CON0                  0x78c0
+#define AFE_GASRC2_NEW_CON1                  0x78c4
+#define AFE_GASRC2_NEW_CON2                  0x78c8
+#define AFE_GASRC2_NEW_CON3                  0x78cc
+#define AFE_GASRC2_NEW_CON4                  0x78d0
+#define AFE_GASRC2_NEW_CON5                  0x78d4
+#define AFE_GASRC2_NEW_CON6                  0x78d8
+#define AFE_GASRC2_NEW_CON7                  0x78dc
+#define AFE_GASRC2_NEW_CON8                  0x78e0
+#define AFE_GASRC2_NEW_CON9                  0x78e4
+#define AFE_GASRC2_NEW_CON10                 0x78e8
+#define AFE_GASRC2_NEW_CON11                 0x78ec
+#define AFE_GASRC2_NEW_CON12                 0x78f0
+#define AFE_GASRC2_NEW_CON13                 0x78f4
+#define AFE_GASRC2_NEW_CON14                 0x78f8
+#define AFE_GASRC2_NEW_IP_VERSION            0x78fc
+#define AFE_GASRC3_NEW_CON0                  0x7900
+#define AFE_GASRC3_NEW_CON1                  0x7904
+#define AFE_GASRC3_NEW_CON2                  0x7908
+#define AFE_GASRC3_NEW_CON3                  0x790c
+#define AFE_GASRC3_NEW_CON4                  0x7910
+#define AFE_GASRC3_NEW_CON5                  0x7914
+#define AFE_GASRC3_NEW_CON6                  0x7918
+#define AFE_GASRC3_NEW_CON7                  0x791c
+#define AFE_GASRC3_NEW_CON8                  0x7920
+#define AFE_GASRC3_NEW_CON9                  0x7924
+#define AFE_GASRC3_NEW_CON10                 0x7928
+#define AFE_GASRC3_NEW_CON11                 0x792c
+#define AFE_GASRC3_NEW_CON12                 0x7930
+#define AFE_GASRC3_NEW_CON13                 0x7934
+#define AFE_GASRC3_NEW_CON14                 0x7938
+#define AFE_GASRC3_NEW_IP_VERSION            0x793c
+#define AFE_GASRC4_NEW_CON0                  0x7940
+#define AFE_GASRC4_NEW_CON1                  0x7944
+#define AFE_GASRC4_NEW_CON2                  0x7948
+#define AFE_GASRC4_NEW_CON3                  0x794c
+#define AFE_GASRC4_NEW_CON4                  0x7950
+#define AFE_GASRC4_NEW_CON5                  0x7954
+#define AFE_GASRC4_NEW_CON6                  0x7958
+#define AFE_GASRC4_NEW_CON7                  0x795c
+#define AFE_GASRC4_NEW_CON8                  0x7960
+#define AFE_GASRC4_NEW_CON9                  0x7964
+#define AFE_GASRC4_NEW_CON10                 0x7968
+#define AFE_GASRC4_NEW_CON11                 0x796c
+#define AFE_GASRC4_NEW_CON12                 0x7970
+#define AFE_GASRC4_NEW_CON13                 0x7974
+#define AFE_GASRC4_NEW_CON14                 0x7978
+#define AFE_GASRC4_NEW_IP_VERSION            0x797c
+#define AFE_GASRC5_NEW_CON0                  0x7980
+#define AFE_GASRC5_NEW_CON1                  0x7984
+#define AFE_GASRC5_NEW_CON2                  0x7988
+#define AFE_GASRC5_NEW_CON3                  0x798c
+#define AFE_GASRC5_NEW_CON4                  0x7990
+#define AFE_GASRC5_NEW_CON5                  0x7994
+#define AFE_GASRC5_NEW_CON6                  0x7998
+#define AFE_GASRC5_NEW_CON7                  0x799c
+#define AFE_GASRC5_NEW_CON8                  0x79a0
+#define AFE_GASRC5_NEW_CON9                  0x79a4
+#define AFE_GASRC5_NEW_CON10                 0x79a8
+#define AFE_GASRC5_NEW_CON11                 0x79ac
+#define AFE_GASRC5_NEW_CON12                 0x79b0
+#define AFE_GASRC5_NEW_CON13                 0x79b4
+#define AFE_GASRC5_NEW_CON14                 0x79b8
+#define AFE_GASRC5_NEW_IP_VERSION            0x79bc
+#define AFE_GASRC6_NEW_CON0                  0x79c0
+#define AFE_GASRC6_NEW_CON1                  0x79c4
+#define AFE_GASRC6_NEW_CON2                  0x79c8
+#define AFE_GASRC6_NEW_CON3                  0x79cc
+#define AFE_GASRC6_NEW_CON4                  0x79d0
+#define AFE_GASRC6_NEW_CON5                  0x79d4
+#define AFE_GASRC6_NEW_CON6                  0x79d8
+#define AFE_GASRC6_NEW_CON7                  0x79dc
+#define AFE_GASRC6_NEW_CON8                  0x79e0
+#define AFE_GASRC6_NEW_CON9                  0x79e4
+#define AFE_GASRC6_NEW_CON10                 0x79e8
+#define AFE_GASRC6_NEW_CON11                 0x79ec
+#define AFE_GASRC6_NEW_CON12                 0x79f0
+#define AFE_GASRC6_NEW_CON13                 0x79f4
+#define AFE_GASRC6_NEW_CON14                 0x79f8
+#define AFE_GASRC6_NEW_IP_VERSION            0x79fc
+#define AFE_GASRC7_NEW_CON0                  0x7a00
+#define AFE_GASRC7_NEW_CON1                  0x7a04
+#define AFE_GASRC7_NEW_CON2                  0x7a08
+#define AFE_GASRC7_NEW_CON3                  0x7a0c
+#define AFE_GASRC7_NEW_CON4                  0x7a10
+#define AFE_GASRC7_NEW_CON5                  0x7a14
+#define AFE_GASRC7_NEW_CON6                  0x7a18
+#define AFE_GASRC7_NEW_CON7                  0x7a1c
+#define AFE_GASRC7_NEW_CON8                  0x7a20
+#define AFE_GASRC7_NEW_CON9                  0x7a24
+#define AFE_GASRC7_NEW_CON10                 0x7a28
+#define AFE_GASRC7_NEW_CON11                 0x7a2c
+#define AFE_GASRC7_NEW_CON12                 0x7a30
+#define AFE_GASRC7_NEW_CON13                 0x7a34
+#define AFE_GASRC7_NEW_CON14                 0x7a38
+#define AFE_GASRC7_NEW_IP_VERSION            0x7a3c
+#define AFE_GASRC8_NEW_CON0                  0x7a40
+#define AFE_GASRC8_NEW_CON1                  0x7a44
+#define AFE_GASRC8_NEW_CON2                  0x7a48
+#define AFE_GASRC8_NEW_CON3                  0x7a4c
+#define AFE_GASRC8_NEW_CON4                  0x7a50
+#define AFE_GASRC8_NEW_CON5                  0x7a54
+#define AFE_GASRC8_NEW_CON6                  0x7a58
+#define AFE_GASRC8_NEW_CON7                  0x7a5c
+#define AFE_GASRC8_NEW_CON8                  0x7a60
+#define AFE_GASRC8_NEW_CON9                  0x7a64
+#define AFE_GASRC8_NEW_CON10                 0x7a68
+#define AFE_GASRC8_NEW_CON11                 0x7a6c
+#define AFE_GASRC8_NEW_CON12                 0x7a70
+#define AFE_GASRC8_NEW_CON13                 0x7a74
+#define AFE_GASRC8_NEW_CON14                 0x7a78
+#define AFE_GASRC8_NEW_IP_VERSION            0x7a7c
+#define AFE_GASRC9_NEW_CON0                  0x7a80
+#define AFE_GASRC9_NEW_CON1                  0x7a84
+#define AFE_GASRC9_NEW_CON2                  0x7a88
+#define AFE_GASRC9_NEW_CON3                  0x7a8c
+#define AFE_GASRC9_NEW_CON4                  0x7a90
+#define AFE_GASRC9_NEW_CON5                  0x7a94
+#define AFE_GASRC9_NEW_CON6                  0x7a98
+#define AFE_GASRC9_NEW_CON7                  0x7a9c
+#define AFE_GASRC9_NEW_CON8                  0x7aa0
+#define AFE_GASRC9_NEW_CON9                  0x7aa4
+#define AFE_GASRC9_NEW_CON10                 0x7aa8
+#define AFE_GASRC9_NEW_CON11                 0x7aac
+#define AFE_GASRC9_NEW_CON12                 0x7ab0
+#define AFE_GASRC9_NEW_CON13                 0x7ab4
+#define AFE_GASRC9_NEW_CON14                 0x7ab8
+#define AFE_GASRC9_NEW_IP_VERSION            0x7abc
+#define AFE_GASRC10_NEW_CON0                 0x7ac0
+#define AFE_GASRC10_NEW_CON1                 0x7ac4
+#define AFE_GASRC10_NEW_CON2                 0x7ac8
+#define AFE_GASRC10_NEW_CON3                 0x7acc
+#define AFE_GASRC10_NEW_CON4                 0x7ad0
+#define AFE_GASRC10_NEW_CON5                 0x7ad4
+#define AFE_GASRC10_NEW_CON6                 0x7ad8
+#define AFE_GASRC10_NEW_CON7                 0x7adc
+#define AFE_GASRC10_NEW_CON8                 0x7ae0
+#define AFE_GASRC10_NEW_CON9                 0x7ae4
+#define AFE_GASRC10_NEW_CON10                0x7ae8
+#define AFE_GASRC10_NEW_CON11                0x7aec
+#define AFE_GASRC10_NEW_CON12                0x7af0
+#define AFE_GASRC10_NEW_CON13                0x7af4
+#define AFE_GASRC10_NEW_CON14                0x7af8
+#define AFE_GASRC10_NEW_IP_VERSION           0x7afc
+#define AFE_GASRC11_NEW_CON0                 0x7b00
+#define AFE_GASRC11_NEW_CON1                 0x7b04
+#define AFE_GASRC11_NEW_CON2                 0x7b08
+#define AFE_GASRC11_NEW_CON3                 0x7b0c
+#define AFE_GASRC11_NEW_CON4                 0x7b10
+#define AFE_GASRC11_NEW_CON5                 0x7b14
+#define AFE_GASRC11_NEW_CON6                 0x7b18
+#define AFE_GASRC11_NEW_CON7                 0x7b1c
+#define AFE_GASRC11_NEW_CON8                 0x7b20
+#define AFE_GASRC11_NEW_CON9                 0x7b24
+#define AFE_GASRC11_NEW_CON10                0x7b28
+#define AFE_GASRC11_NEW_CON11                0x7b2c
+#define AFE_GASRC11_NEW_CON12                0x7b30
+#define AFE_GASRC11_NEW_CON13                0x7b34
+#define AFE_GASRC11_NEW_CON14                0x7b38
+#define AFE_GASRC11_NEW_IP_VERSION           0x7b3c
+#define AFE_GASRC12_NEW_CON0                 0x7b40
+#define AFE_GASRC12_NEW_CON1                 0x7b44
+#define AFE_GASRC12_NEW_CON2                 0x7b48
+#define AFE_GASRC12_NEW_CON3                 0x7b4c
+#define AFE_GASRC12_NEW_CON4                 0x7b50
+#define AFE_GASRC12_NEW_CON5                 0x7b54
+#define AFE_GASRC12_NEW_CON6                 0x7b58
+#define AFE_GASRC12_NEW_CON7                 0x7b5c
+#define AFE_GASRC12_NEW_CON8                 0x7b60
+#define AFE_GASRC12_NEW_CON9                 0x7b64
+#define AFE_GASRC12_NEW_CON10                0x7b68
+#define AFE_GASRC12_NEW_CON11                0x7b6c
+#define AFE_GASRC12_NEW_CON12                0x7b70
+#define AFE_GASRC12_NEW_CON13                0x7b74
+#define AFE_GASRC12_NEW_CON14                0x7b78
+#define AFE_GASRC12_NEW_IP_VERSION           0x7b7c
+#define AFE_GASRC13_NEW_CON0                 0x7b80
+#define AFE_GASRC13_NEW_CON1                 0x7b84
+#define AFE_GASRC13_NEW_CON2                 0x7b88
+#define AFE_GASRC13_NEW_CON3                 0x7b8c
+#define AFE_GASRC13_NEW_CON4                 0x7b90
+#define AFE_GASRC13_NEW_CON5                 0x7b94
+#define AFE_GASRC13_NEW_CON6                 0x7b98
+#define AFE_GASRC13_NEW_CON7                 0x7b9c
+#define AFE_GASRC13_NEW_CON8                 0x7ba0
+#define AFE_GASRC13_NEW_CON9                 0x7ba4
+#define AFE_GASRC13_NEW_CON10                0x7ba8
+#define AFE_GASRC13_NEW_CON11                0x7bac
+#define AFE_GASRC13_NEW_CON12                0x7bb0
+#define AFE_GASRC13_NEW_CON13                0x7bb4
+#define AFE_GASRC13_NEW_CON14                0x7bb8
+#define AFE_GASRC13_NEW_IP_VERSION           0x7bbc
+#define AFE_GASRC14_NEW_CON0                 0x7bc0
+#define AFE_GASRC14_NEW_CON1                 0x7bc4
+#define AFE_GASRC14_NEW_CON2                 0x7bc8
+#define AFE_GASRC14_NEW_CON3                 0x7bcc
+#define AFE_GASRC14_NEW_CON4                 0x7bd0
+#define AFE_GASRC14_NEW_CON5                 0x7bd4
+#define AFE_GASRC14_NEW_CON6                 0x7bd8
+#define AFE_GASRC14_NEW_CON7                 0x7bdc
+#define AFE_GASRC14_NEW_CON8                 0x7be0
+#define AFE_GASRC14_NEW_CON9                 0x7be4
+#define AFE_GASRC14_NEW_CON10                0x7be8
+#define AFE_GASRC14_NEW_CON11                0x7bec
+#define AFE_GASRC14_NEW_CON12                0x7bf0
+#define AFE_GASRC14_NEW_CON13                0x7bf4
+#define AFE_GASRC14_NEW_CON14                0x7bf8
+#define AFE_GASRC14_NEW_IP_VERSION           0x7bfc
+#define AFE_GASRC15_NEW_CON0                 0x7c00
+#define AFE_GASRC15_NEW_CON1                 0x7c04
+#define AFE_GASRC15_NEW_CON2                 0x7c08
+#define AFE_GASRC15_NEW_CON3                 0x7c0c
+#define AFE_GASRC15_NEW_CON4                 0x7c10
+#define AFE_GASRC15_NEW_CON5                 0x7c14
+#define AFE_GASRC15_NEW_CON6                 0x7c18
+#define AFE_GASRC15_NEW_CON7                 0x7c1c
+#define AFE_GASRC15_NEW_CON8                 0x7c20
+#define AFE_GASRC15_NEW_CON9                 0x7c24
+#define AFE_GASRC15_NEW_CON10                0x7c28
+#define AFE_GASRC15_NEW_CON11                0x7c2c
+#define AFE_GASRC15_NEW_CON12                0x7c30
+#define AFE_GASRC15_NEW_CON13                0x7c34
+#define AFE_GASRC15_NEW_CON14                0x7c38
+#define AFE_GASRC15_NEW_IP_VERSION           0x7c3c
+
+#define AFE_MAX_REGISTER AFE_GASRC15_NEW_IP_VERSION
+
+#define AFE_IRQ_STATUS_BITS 0x87FFFFFF
+#define AFE_IRQ_CNT_SHIFT 0
+#define AFE_IRQ_CNT_MASK 0xffffff
+#endif
+
-- 
2.45.2



From darren.ye at mediatek.com  Wed May 14 01:11:06 2025
From: darren.ye at mediatek.com (Darren.Ye)
Date: Wed, 14 May 2025 16:11:06 +0800
Subject: [PATCH v3 04/10] ASoC: mediatek: mt8196: support ADDA in platform driver
In-Reply-To: <20250514081125.24475-1-darren.ye@mediatek.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
Message-ID: <20250514081125.24475-5-darren.ye@mediatek.com>

From: Darren Ye <darren.ye at mediatek.com>

Add mt8196 ADDA DAI driver support.

Signed-off-by: Darren Ye <darren.ye at mediatek.com>
---
 sound/soc/mediatek/mt8196/mt8196-dai-adda.c | 918 ++++++++++++++++++++
 1 file changed, 918 insertions(+)
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-dai-adda.c

diff --git a/sound/soc/mediatek/mt8196/mt8196-dai-adda.c b/sound/soc/mediatek/mt8196/mt8196-dai-adda.c
new file mode 100644
index 000000000000..1ccffd0030c3
--- /dev/null
+++ b/sound/soc/mediatek/mt8196/mt8196-dai-adda.c
@@ -0,0 +1,918 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *  MediaTek ALSA SoC Audio DAI ADDA Control
+ *
+ *  Copyright (c) 2024 MediaTek Inc.
+ *  Author: Darren Ye <darren.ye at mediatek.com>
+ */
+
+#include <linux/regmap.h>
+#include <linux/delay.h>
+#include "mt8196-afe-clk.h"
+#include "mt8196-afe-common.h"
+#include "mt8196-interconnection.h"
+
+#define MTKAIF4
+
+enum {
+	UL_IIR_SW = 0,
+	UL_IIR_5HZ,
+	UL_IIR_10HZ,
+	UL_IIR_25HZ,
+	UL_IIR_50HZ,
+	UL_IIR_75HZ,
+};
+
+enum {
+	MTK_AFE_ADDA_UL_RATE_8K = 0,
+	MTK_AFE_ADDA_UL_RATE_16K = 1,
+	MTK_AFE_ADDA_UL_RATE_32K = 2,
+	MTK_AFE_ADDA_UL_RATE_48K = 3,
+	MTK_AFE_ADDA_UL_RATE_96K = 4,
+	MTK_AFE_ADDA_UL_RATE_192K = 5,
+	MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
+};
+
+#ifdef MTKAIF4
+enum {
+	MTK_AFE_MTKAIF_RATE_8K = 0x0,
+	MTK_AFE_MTKAIF_RATE_12K = 0x1,
+	MTK_AFE_MTKAIF_RATE_16K = 0x2,
+	MTK_AFE_MTKAIF_RATE_24K = 0x3,
+	MTK_AFE_MTKAIF_RATE_32K = 0x4,
+	MTK_AFE_MTKAIF_RATE_48K = 0x5,
+	MTK_AFE_MTKAIF_RATE_64K = 0x6,
+	MTK_AFE_MTKAIF_RATE_96K = 0x7,
+	MTK_AFE_MTKAIF_RATE_128K = 0x8,
+	MTK_AFE_MTKAIF_RATE_192K = 0x9,
+	MTK_AFE_MTKAIF_RATE_256K = 0xa,
+	MTK_AFE_MTKAIF_RATE_384K = 0xb,
+	MTK_AFE_MTKAIF_RATE_11K = 0x10,
+	MTK_AFE_MTKAIF_RATE_22K = 0x11,
+	MTK_AFE_MTKAIF_RATE_44K = 0x12,
+	MTK_AFE_MTKAIF_RATE_88K = 0x13,
+	MTK_AFE_MTKAIF_RATE_176K = 0x14,
+	MTK_AFE_MTKAIF_RATE_352K = 0x15,
+};
+#endif
+
+struct mtk_afe_adda_priv {
+	int dl_rate;
+	int ul_rate;
+};
+
+static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
+					   unsigned int rate)
+{
+	switch (rate) {
+	case 8000:
+		return MTK_AFE_ADDA_UL_RATE_8K;
+	case 16000:
+		return MTK_AFE_ADDA_UL_RATE_16K;
+	case 32000:
+		return MTK_AFE_ADDA_UL_RATE_32K;
+	case 48000:
+		return MTK_AFE_ADDA_UL_RATE_48K;
+	case 96000:
+		return MTK_AFE_ADDA_UL_RATE_96K;
+	case 192000:
+		return MTK_AFE_ADDA_UL_RATE_192K;
+	default:
+		dev_info(afe->dev, "rate %d invalid, use 48kHz!!!\n", rate);
+		return MTK_AFE_ADDA_UL_RATE_48K;
+	}
+}
+
+#ifdef MTKAIF4
+static unsigned int mtkaif_rate_transform(struct mtk_base_afe *afe,
+					  unsigned int rate)
+{
+	switch (rate) {
+	case 8000:
+		return MTK_AFE_MTKAIF_RATE_8K;
+	case 11025:
+		return MTK_AFE_MTKAIF_RATE_11K;
+	case 12000:
+		return MTK_AFE_MTKAIF_RATE_12K;
+	case 16000:
+		return MTK_AFE_MTKAIF_RATE_16K;
+	case 22050:
+		return MTK_AFE_MTKAIF_RATE_22K;
+	case 24000:
+		return MTK_AFE_MTKAIF_RATE_24K;
+	case 32000:
+		return MTK_AFE_MTKAIF_RATE_32K;
+	case 44100:
+		return MTK_AFE_MTKAIF_RATE_44K;
+	case 48000:
+		return MTK_AFE_MTKAIF_RATE_48K;
+	case 96000:
+		return MTK_AFE_MTKAIF_RATE_96K;
+	case 192000:
+		return MTK_AFE_MTKAIF_RATE_192K;
+	default:
+		dev_info(afe->dev, "rate %d invalid, use 48kHz!!!\n", rate);
+		return MTK_AFE_MTKAIF_RATE_48K;
+	}
+}
+#endif
+
+enum {
+	SUPPLY_SEQ_ADDA_AFE_ON,
+	SUPPLY_SEQ_ADDA_FIFO,
+	SUPPLY_SEQ_ADDA_AP_DMIC,
+	SUPPLY_SEQ_ADDA_UL_ON,
+};
+
+static int mtk_adda_ul_src_dmic_phase_sync(struct mtk_base_afe *afe)
+{
+	dev_dbg(afe->dev, "set dmic phase sync\n");
+	// ul0~1
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1,
+			   UL0_PHASE_SYNC_HCLK_SET_MASK_SFT,
+			   0x1 << UL0_PHASE_SYNC_HCLK_SET_SFT);
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1,
+			   UL0_PHASE_SYNC_FCLK_SET_MASK_SFT,
+			   0x1 << UL0_PHASE_SYNC_FCLK_SET_SFT);
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1,
+			   UL1_PHASE_SYNC_HCLK_SET_MASK_SFT,
+			   0x1 << UL1_PHASE_SYNC_HCLK_SET_SFT);
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1,
+			   UL1_PHASE_SYNC_FCLK_SET_MASK_SFT,
+			   0x1 << UL1_PHASE_SYNC_FCLK_SET_SFT);
+	// dmic 0
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1,
+			   DMIC0_PHASE_SYNC_FCLK_SET_MASK_SFT,
+			   0x1 << DMIC0_PHASE_SYNC_FCLK_SET_SFT);
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1,
+			   DMIC0_PHASE_SYNC_HCLK_SET_MASK_SFT,
+			   0x1 << DMIC0_PHASE_SYNC_HCLK_SET_SFT);
+	// dmic 1
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1,
+			   DMIC1_PHASE_SYNC_FCLK_SET_MASK_SFT,
+			   0x1 << DMIC1_PHASE_SYNC_FCLK_SET_SFT);
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1,
+			   DMIC1_PHASE_SYNC_HCLK_SET_MASK_SFT,
+			   0x1 << DMIC1_PHASE_SYNC_HCLK_SET_SFT);
+	// ul0~1 phase sync clock
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0,
+			   DMIC1_PHASE_HCLK_SEL_MASK_SFT,
+			   0x1 << DMIC1_PHASE_HCLK_SEL_SFT);
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0,
+			   DMIC1_PHASE_FCLK_SEL_MASK_SFT,
+			   0x1 << DMIC1_PHASE_FCLK_SEL_SFT);
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0,
+			   DMIC0_PHASE_HCLK_SEL_MASK_SFT,
+			   0x1 << DMIC0_PHASE_HCLK_SEL_SFT);
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0,
+			   DMIC0_PHASE_FCLK_SEL_MASK_SFT,
+			   0x1 << DMIC0_PHASE_FCLK_SEL_SFT);
+	// dmic 0
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0,
+			   UL1_PHASE_HCLK_SEL_MASK_SFT,
+			   0x2 << UL1_PHASE_HCLK_SEL_SFT);
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0,
+			   UL1_PHASE_FCLK_SEL_MASK_SFT,
+			   0x2 << UL1_PHASE_FCLK_SEL_SFT);
+	// dmic 1
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0,
+			   UL0_PHASE_HCLK_SEL_MASK_SFT,
+			   0x2 << UL0_PHASE_HCLK_SEL_SFT);
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0,
+			   UL0_PHASE_FCLK_SEL_MASK_SFT,
+			   0x2 << UL0_PHASE_FCLK_SEL_SFT);
+
+	return 0;
+}
+
+static int mtk_adda_ul_src_dmic_phase_sync_clock(struct mtk_base_afe *afe)
+{
+	dev_dbg(afe->dev, "dmic turn on phase sync clk\n");
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0,
+			   UL_PHASE_SYNC_HCLK_1_ON_MASK_SFT,
+			   0x1 << UL_PHASE_SYNC_HCLK_1_ON_SFT);
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0,
+			   UL_PHASE_SYNC_HCLK_0_ON_MASK_SFT,
+			   0x1 << UL_PHASE_SYNC_HCLK_0_ON_SFT);
+
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0,
+			   UL_PHASE_SYNC_FCLK_1_ON_MASK_SFT,
+			   0x1 << UL_PHASE_SYNC_FCLK_1_ON_SFT);
+	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0,
+			   UL_PHASE_SYNC_FCLK_0_ON_MASK_SFT,
+			   0x1 << UL_PHASE_SYNC_FCLK_0_ON_SFT);
+
+	return 0;
+}
+
+static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id)
+{
+	unsigned int reg_con0 = 0, reg_con1 = 0;
+
+	dev_dbg(afe->dev, "id: %d\n", id);
+
+	switch (id) {
+	case MT8196_DAI_ADDA:
+	case MT8196_DAI_AP_DMIC:
+		reg_con0 = AFE_ADDA_UL0_SRC_CON0;
+		reg_con1 = AFE_ADDA_UL0_SRC_CON1;
+		break;
+	case MT8196_DAI_ADDA_CH34:
+	case MT8196_DAI_AP_DMIC_CH34:
+		reg_con0 = AFE_ADDA_UL1_SRC_CON0;
+		reg_con1 = AFE_ADDA_UL1_SRC_CON1;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	switch (id) {
+	case MT8196_DAI_AP_DMIC:
+		dev_dbg(afe->dev, "clear mtkaifv4 ul ch1ch2 mux\n");
+		regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0,
+				   MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK_SFT,
+				   0x0 << MTKAIFV4_UL_CH1CH2_IN_EN_SEL_SFT);
+		break;
+	case MT8196_DAI_AP_DMIC_CH34:
+		dev_dbg(afe->dev, "clear mtkaifv4 ul ch3ch4 mux\n");
+		regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0,
+				   MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK_SFT,
+				   0x0 << MTKAIFV4_UL_CH3CH4_IN_EN_SEL_SFT);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* choose Phase */
+	regmap_update_bits(afe->regmap, reg_con0,
+			   UL_DMIC_PHASE_SEL_CH1_MASK_SFT,
+			   0x0 << UL_DMIC_PHASE_SEL_CH1_SFT);
+	regmap_update_bits(afe->regmap, reg_con0,
+			   UL_DMIC_PHASE_SEL_CH2_MASK_SFT,
+			   0x4 << UL_DMIC_PHASE_SEL_CH2_SFT);
+
+	/* dmic mode, 3.25M*/
+	regmap_update_bits(afe->regmap, reg_con0,
+			   DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT,
+			   0x0);
+	regmap_update_bits(afe->regmap, reg_con0,
+			   DMIC_LOW_POWER_MODE_CTL_MASK_SFT,
+			   0x0);
+
+	/* turn on dmic, ch1, ch2 */
+	regmap_update_bits(afe->regmap, reg_con0,
+			   UL_SDM_3_LEVEL_CTL_MASK_SFT,
+			   0x1 << UL_SDM_3_LEVEL_CTL_SFT);
+	regmap_update_bits(afe->regmap, reg_con0,
+			   UL_MODE_3P25M_CH1_CTL_MASK_SFT,
+			   0x1 << UL_MODE_3P25M_CH1_CTL_SFT);
+	regmap_update_bits(afe->regmap, reg_con0,
+			   UL_MODE_3P25M_CH2_CTL_MASK_SFT,
+			   0x1 << UL_MODE_3P25M_CH2_CTL_SFT);
+
+	/* ul gain:  gain = 0x7fff/positive_gain = 0x0/gain_mode = 0x10 */
+	regmap_update_bits(afe->regmap, reg_con1,
+			   ADDA_UL_GAIN_VALUE_MASK_SFT,
+			   0x7fff << ADDA_UL_GAIN_VALUE_SFT);
+	regmap_update_bits(afe->regmap, reg_con1,
+			   ADDA_UL_POSTIVEGAIN_MASK_SFT,
+			   0x0 << ADDA_UL_POSTIVEGAIN_SFT);
+	/* gain_mode = 0x10: Add 0.5 gain at CIC output */
+	regmap_update_bits(afe->regmap, reg_con1,
+			   GAIN_MODE_MASK_SFT,
+			   0x02 << GAIN_MODE_SFT);
+	return 0;
+}
+
+static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
+			     struct snd_kcontrol *kcontrol,
+			     int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+
+	dev_dbg(afe->dev, "name %s, event 0x%x\n", w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
+		usleep_range(120, 130);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int mtk_adda_ch34_ul_event(struct snd_soc_dapm_widget *w,
+				  struct snd_kcontrol *kcontrol,
+				  int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+
+	dev_dbg(afe->dev, "name %s, event 0x%x\n", w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
+		usleep_range(120, 130);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int mtk_adda_ul_ap_dmic_event(struct snd_soc_dapm_widget *w,
+				     struct snd_kcontrol *kcontrol,
+				     int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+
+	dev_info(afe->dev, "name %s, event 0x%x\n", w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
+		usleep_range(120, 130);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int mtk_adda_ch34_ul_ap_dmic_event(struct snd_soc_dapm_widget *w,
+					  struct snd_kcontrol *kcontrol,
+					  int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+
+	dev_dbg(afe->dev, "name %s, event 0x%x\n", w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
+		usleep_range(120, 130);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+/* mtkaif dmic */
+static const char *const mt8196_adda_off_on_str[] = {
+	"Off", "On"
+};
+
+static const struct soc_enum mt8196_adda_enum[] = {
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8196_adda_off_on_str),
+			    mt8196_adda_off_on_str),
+};
+
+static const struct snd_kcontrol_new mtk_adda_controls[] = {
+};
+
+/* ADDA UL MUX */
+#define ADDA_UL_MUX_MASK 0x3
+enum {
+	ADDA_UL_MUX_MTKAIF = 0,
+	ADDA_UL_MUX_AP_DMIC,
+	ADDA_UL_MUX_AP_DMIC_MULTICH,
+};
+
+static const char *const adda_ul_mux_map[] = {
+	"MTKAIF", "AP_DMIC", "AP_DMIC_MULTI_CH",
+};
+
+static int adda_ul_map_value[] = {
+	ADDA_UL_MUX_MTKAIF,
+	ADDA_UL_MUX_AP_DMIC,
+	ADDA_UL_MUX_AP_DMIC_MULTICH,
+};
+
+static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum,
+				  SND_SOC_NOPM,
+				  0,
+				  ADDA_UL_MUX_MASK,
+				  adda_ul_mux_map,
+				  adda_ul_map_value);
+
+static const struct snd_kcontrol_new adda_ul_mux_control =
+	SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum);
+
+static const struct snd_kcontrol_new adda_ch34_ul_mux_control =
+	SOC_DAPM_ENUM("ADDA_CH34_UL_MUX Select", adda_ul_mux_map_enum);
+
+static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
+	/* inter-connections */
+	SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
+			      AUDIO_ENGEN_CON0, AUDIO_F3P25M_EN_ON_SFT, 0,
+			      NULL, 0),
+	SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
+			      AFE_ADDA_UL0_SRC_CON0,
+			      UL_SRC_ON_TMP_CTL_SFT, 0,
+			      mtk_adda_ul_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
+			      AFE_ADDA_UL1_SRC_CON0,
+			      UL_SRC_ON_TMP_CTL_SFT, 0,
+			      mtk_adda_ch34_ul_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
+			      AFE_ADDA_UL0_SRC_CON0,
+			      UL_AP_DMIC_ON_SFT, 0,
+			      mtk_adda_ul_ap_dmic_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("AP_DMIC_CH34_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
+			      AFE_ADDA_UL1_SRC_CON0,
+			      UL_AP_DMIC_ON_SFT, 0,
+			      mtk_adda_ch34_ul_ap_dmic_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO,
+			      AFE_ADDA_UL0_SRC_CON1,
+			      FIFO_SOFT_RST_SFT, 1,
+			      NULL, 0),
+	SND_SOC_DAPM_SUPPLY_S("ADDA_CH34_FIFO", SUPPLY_SEQ_ADDA_FIFO,
+			      AFE_ADDA_UL1_SRC_CON1,
+			      FIFO_SOFT_RST_SFT, 1,
+			      NULL, 0),
+	SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0,
+			 &adda_ul_mux_control),
+	SND_SOC_DAPM_MUX("ADDA_CH34_UL_Mux", SND_SOC_NOPM, 0, 0,
+			 &adda_ch34_ul_mux_control),
+	SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"),
+	SND_SOC_DAPM_INPUT("AP_DMIC_CH34_INPUT"),
+};
+
+static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
+	/* capture */
+	{"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"},
+	{"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"},
+	{"ADDA_UL_Mux", "AP_DMIC_MULTI_CH", "AP DMIC MULTICH Capture"},
+
+	{"ADDA_CH34_UL_Mux", "MTKAIF", "ADDA CH34 Capture"},
+	{"ADDA_CH34_UL_Mux", "AP_DMIC", "AP DMIC CH34 Capture"},
+	{"ADDA_CH34_UL_Mux", "AP_DMIC_MULTI_CH", "AP DMIC MULTICH Capture"},
+
+	{"AP DMIC Capture", NULL, "ADDA Enable"},
+	{"AP DMIC Capture", NULL, "ADDA Capture Enable"},
+	{"AP DMIC Capture", NULL, "ADDA_FIFO"},
+	{"AP DMIC Capture", NULL, "AP_DMIC_EN"},
+
+	{"AP DMIC CH34 Capture", NULL, "ADDA Enable"},
+	{"AP DMIC CH34 Capture", NULL, "ADDA CH34 Capture Enable"},
+	{"AP DMIC CH34 Capture", NULL, "ADDA_CH34_FIFO"},
+	{"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_EN"},
+
+	{"AP DMIC MULTICH Capture", NULL, "ADDA Enable"},
+	{"AP DMIC MULTICH Capture", NULL, "ADDA Capture Enable"},
+	{"AP DMIC MULTICH Capture", NULL, "ADDA CH34 Capture Enable"},
+	{"AP DMIC MULTICH Capture", NULL, "ADDA_FIFO"},
+	{"AP DMIC MULTICH Capture", NULL, "ADDA_CH34_FIFO"},
+	{"AP DMIC MULTICH Capture", NULL, "AP_DMIC_EN"},
+	{"AP DMIC MULTICH Capture", NULL, "AP_DMIC_CH34_EN"},
+	{"AP DMIC Capture", NULL, "AP_DMIC_INPUT"},
+	{"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_INPUT"},
+	{"AP DMIC MULTICH Capture", NULL, "AP_DMIC_INPUT"},
+};
+
+/* dai ops */
+static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
+				  struct snd_pcm_hw_params *params,
+				  struct snd_soc_dai *dai)
+{
+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	unsigned int rate = params_rate(params);
+#ifdef MTKAIF4
+	unsigned int mtkaif_rate = 0;
+#endif
+	int id = dai->id;
+	struct mtk_afe_adda_priv *adda_priv;
+
+	if (id >= MT8196_DAI_NUM || id < 0)
+		return -EINVAL;
+
+	adda_priv = afe_priv->dai_priv[id];
+
+	dev_info(afe->dev, "id %d, stream %d, rate %d\n",
+		 id,
+		 substream->stream,
+		 rate);
+
+	if (!adda_priv)
+		return -EINVAL;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		adda_priv->dl_rate = rate;
+
+#ifdef MTKAIF4
+		/* get mtkaif dl rate */
+		mtkaif_rate =
+			mtkaif_rate_transform(afe, adda_priv->dl_rate);
+#endif
+		if (id == MT8196_DAI_ADDA) {
+#ifdef MTKAIF4
+			/* MTKAIF sample rate config */
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0,
+					   MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT,
+					   mtkaif_rate << MTKAIFV4_TXIF_INPUT_MODE_SFT);
+			/* AFE_ADDA_MTKAIFV4_TX_CFG0 */
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0,
+					   MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT,
+					   0x0 << MTKAIFV4_TXIF_FOUR_CHANNEL_SFT);
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0,
+					   MTKAIFV4_ADDA_OUT_EN_SEL_MASK_SFT,
+					   0x1 << MTKAIFV4_ADDA_OUT_EN_SEL_SFT);
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0,
+					   MTKAIFV4_ADDA6_OUT_EN_SEL_MASK_SFT,
+					   0x1 << MTKAIFV4_ADDA6_OUT_EN_SEL_SFT);
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0,
+					   MTKAIFV4_TXIF_V4_MASK_SFT,
+					   0x1 << MTKAIFV4_TXIF_V4_SFT);
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0,
+					   MTKAIFV4_TXIF_EN_SEL_MASK_SFT,
+					   0x0 << MTKAIFV4_TXIF_EN_SEL_SFT);
+#endif
+			/* clean predistortion */
+		} else {
+#ifdef MTKAIF4
+			/* MTKAIF sample rate config */
+			regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_TX_CFG0,
+					   ADDA6_MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT,
+					   mtkaif_rate << ADDA6_MTKAIFV4_TXIF_INPUT_MODE_SFT);
+			/* AFE_ADDA6_MTKAIFV4_TX_CFG0 */
+			regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_TX_CFG0,
+					   ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT,
+					   0x0 << ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_SFT);
+			regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_TX_CFG0,
+					   ADDA6_MTKAIFV4_TXIF_EN_SEL_MASK_SFT,
+					   0x1 << ADDA6_MTKAIFV4_TXIF_EN_SEL_SFT);
+#endif
+		}
+	} else {
+		unsigned int voice_mode = 0;
+		unsigned int ul_src_con0 = 0;   /* default value */
+
+		adda_priv->ul_rate = rate;
+
+#ifdef MTKAIF4
+		/* get mtkaif dl rate */
+		mtkaif_rate =
+			mtkaif_rate_transform(afe, adda_priv->ul_rate);
+#endif
+
+		voice_mode = adda_ul_rate_transform(afe, rate);
+
+		ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
+
+		/* enable iir */
+		ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
+				UL_IIR_ON_TMP_CTL_MASK_SFT;
+		ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) &
+				UL_IIRMODE_CTL_MASK_SFT;
+
+		regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0,
+				   MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT,
+				   mtkaif_rate << MTKAIFV4_RXIF_INPUT_MODE_SFT);
+
+		regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_RX_CFG0,
+				   ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT,
+				   mtkaif_rate << ADDA6_MTKAIFV4_RXIF_INPUT_MODE_SFT);
+
+		switch (id) {
+		case MT8196_DAI_ADDA:
+		case MT8196_DAI_AP_DMIC:
+		case MT8196_DAI_AP_DMIC_MULTICH:
+#ifdef MTKAIF4
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0,
+					   MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT,
+					   mtkaif_rate << MTKAIFV4_RXIF_INPUT_MODE_SFT);
+			/* AFE_ADDA_MTKAIFV4_RX_CFG0 */
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0,
+					   MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT,
+					   0x1 << MTKAIFV4_RXIF_FOUR_CHANNEL_SFT);
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0,
+					   MTKAIFV4_RXIF_EN_SEL_MASK_SFT,
+					   0x0 << MTKAIFV4_RXIF_EN_SEL_SFT);
+			/* [28] loopback mode
+			 * 0: loopback adda tx to adda rx
+			 * 1: loopback adda6 tx to adda rx
+			 */
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0,
+					   MTKAIFV4_TXIF_EN_SEL_MASK_SFT,
+					   0x0 << MTKAIFV4_TXIF_EN_SEL_SFT);
+
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0,
+					   MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK_SFT,
+					   0x1 << MTKAIFV4_UL_CH1CH2_IN_EN_SEL_SFT);
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0,
+					   MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK_SFT,
+					   0x1 << MTKAIFV4_UL_CH3CH4_IN_EN_SEL_SFT);
+#endif
+
+			/* 35Hz @ 48k */
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL1_IIR_COEF_02_01, 0x00000000);
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL1_IIR_COEF_04_03, 0x00003FB8);
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL1_IIR_COEF_06_05, 0x3FB80000);
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL1_IIR_COEF_08_07, 0x3FB80000);
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL1_IIR_COEF_10_09, 0x0000C048);
+
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL1_SRC_CON0, ul_src_con0);
+
+			/* mtkaif_rxif_data_mode = 0, amic */
+			regmap_update_bits(afe->regmap,
+					   AFE_MTKAIF1_RX_CFG0,
+					   0x1 << 0,
+					   0x0 << 0);
+
+			/* 35Hz @ 48k */
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL0_IIR_COEF_02_01, 0x00000000);
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL0_IIR_COEF_04_03, 0x00003FB8);
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL0_IIR_COEF_06_05, 0x3FB80000);
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL0_IIR_COEF_08_07, 0x3FB80000);
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL0_IIR_COEF_10_09, 0x0000C048);
+
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL0_SRC_CON0, ul_src_con0);
+
+			/* mtkaif_rxif_data_mode = 0, amic */
+			regmap_update_bits(afe->regmap,
+					   AFE_MTKAIF0_RX_CFG0,
+					   0x1 << 0,
+					   0x0 << 0);
+			break;
+		case MT8196_DAI_ADDA_CH34:
+		case MT8196_DAI_AP_DMIC_CH34:
+#ifdef MTKAIF4
+			/* AFE_ADDA_MTKAIFV4_RX_CFG0 */
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0,
+					   MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT,
+					   0x1 << MTKAIFV4_RXIF_FOUR_CHANNEL_SFT);
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0,
+					   MTKAIFV4_RXIF_EN_SEL_MASK_SFT,
+					   0x0 << MTKAIFV4_RXIF_EN_SEL_SFT);
+
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0,
+					   MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK_SFT,
+					   0x1 << MTKAIFV4_UL_CH1CH2_IN_EN_SEL_SFT);
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0,
+					   MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK_SFT,
+					   0x1 << MTKAIFV4_UL_CH3CH4_IN_EN_SEL_SFT);
+
+#endif
+			/* 35Hz @ 48k */
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL1_IIR_COEF_02_01, 0x00000000);
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL1_IIR_COEF_04_03, 0x00003FB8);
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL1_IIR_COEF_06_05, 0x3FB80000);
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL1_IIR_COEF_08_07, 0x3FB80000);
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL1_IIR_COEF_10_09, 0x0000C048);
+
+			regmap_write(afe->regmap,
+				     AFE_ADDA_UL1_SRC_CON0, ul_src_con0);
+
+			/* mtkaif_rxif_data_mode = 0, amic */
+			regmap_update_bits(afe->regmap,
+					   AFE_MTKAIF1_RX_CFG0,
+					   0x1 << 0,
+					   0x0 << 0);
+
+			break;
+		case MT8196_DAI_ADDA_CH56:
+			regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_RX_CFG0,
+					   ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT,
+					   mtkaif_rate << ADDA6_MTKAIFV4_RXIF_INPUT_MODE_SFT);
+			/* AFE_ADDA6_MTKAIFV4_RX_CFG0 */
+			regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_RX_CFG0,
+					   ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT,
+					   0x1 << ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_SFT);
+			regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0,
+					   MTKAIFV4_UL_CH5CH6_IN_EN_SEL_MASK_SFT,
+					   0x1 << MTKAIFV4_UL_CH5CH6_IN_EN_SEL_SFT);
+			regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_RX_CFG0,
+					   ADDA6_MTKAIFV4_RXIF_EN_SEL_MASK_SFT,
+					   0x1 << ADDA6_MTKAIFV4_RXIF_EN_SEL_SFT);
+			break;
+		default:
+			break;
+		}
+
+		/* ap dmic */
+		switch (id) {
+		case MT8196_DAI_AP_DMIC:
+		case MT8196_DAI_AP_DMIC_CH34:
+			mtk_adda_ul_src_dmic(afe, id);
+			break;
+		case MT8196_DAI_AP_DMIC_MULTICH:
+			regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1,
+					   DMIC_CLK_PHASE_SYNC_SET_MASK_SFT,
+					   0x1 << DMIC_CLK_PHASE_SYNC_SET_SFT);
+			mtk_adda_ul_src_dmic_phase_sync(afe);
+			mtk_adda_ul_src_dmic(afe, MT8196_DAI_AP_DMIC);
+			mtk_adda_ul_src_dmic(afe, MT8196_DAI_AP_DMIC_CH34);
+			mtk_adda_ul_src_dmic_phase_sync_clock(afe);
+			break;
+		default:
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
+	.hw_params = mtk_dai_adda_hw_params,
+};
+
+/* dai driver */
+#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
+				 SNDRV_PCM_RATE_96000 |\
+				 SNDRV_PCM_RATE_192000)
+
+#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
+				SNDRV_PCM_RATE_16000 |\
+				SNDRV_PCM_RATE_32000 |\
+				SNDRV_PCM_RATE_48000 |\
+				SNDRV_PCM_RATE_96000 |\
+				SNDRV_PCM_RATE_192000)
+
+#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+			  SNDRV_PCM_FMTBIT_S24_LE |\
+			  SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
+	{
+		.name = "ADDA",
+		.id = MT8196_DAI_ADDA,
+		.playback = {
+			.stream_name = "ADDA Playback",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = MTK_ADDA_PLAYBACK_RATES,
+			.formats = MTK_ADDA_FORMATS,
+		},
+		.capture = {
+			.stream_name = "ADDA Capture",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = MTK_ADDA_CAPTURE_RATES,
+			.formats = MTK_ADDA_FORMATS,
+		},
+		.ops = &mtk_dai_adda_ops,
+	},
+	{
+		.name = "ADDA_CH34",
+		.id = MT8196_DAI_ADDA_CH34,
+		.playback = {
+			.stream_name = "ADDA CH34 Playback",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = MTK_ADDA_PLAYBACK_RATES,
+			.formats = MTK_ADDA_FORMATS,
+		},
+		.capture = {
+			.stream_name = "ADDA CH34 Capture",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = MTK_ADDA_CAPTURE_RATES,
+			.formats = MTK_ADDA_FORMATS,
+		},
+		.ops = &mtk_dai_adda_ops,
+	},
+	{
+		.name = "ADDA_CH56",
+		.id = MT8196_DAI_ADDA_CH56,
+		.capture = {
+			.stream_name = "ADDA CH56 Capture",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = MTK_ADDA_CAPTURE_RATES,
+			.formats = MTK_ADDA_FORMATS,
+		},
+		.ops = &mtk_dai_adda_ops,
+	},
+	{
+		.name = "AP_DMIC",
+		.id = MT8196_DAI_AP_DMIC,
+		.capture = {
+			.stream_name = "AP DMIC Capture",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = MTK_ADDA_CAPTURE_RATES,
+			.formats = MTK_ADDA_FORMATS,
+		},
+		.ops = &mtk_dai_adda_ops,
+	},
+	{
+		.name = "AP_DMIC_CH34",
+		.id = MT8196_DAI_AP_DMIC_CH34,
+		.capture = {
+			.stream_name = "AP DMIC CH34 Capture",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = MTK_ADDA_CAPTURE_RATES,
+			.formats = MTK_ADDA_FORMATS,
+		},
+		.ops = &mtk_dai_adda_ops,
+	},
+	{
+		.name = "AP_DMIC_MULTICH",
+		.id = MT8196_DAI_AP_DMIC_MULTICH,
+		.capture = {
+			.stream_name = "AP DMIC MULTICH Capture",
+			.channels_min = 1,
+			.channels_max = 4,
+			.rates = MTK_ADDA_CAPTURE_RATES,
+			.formats = MTK_ADDA_FORMATS,
+		},
+		.ops = &mtk_dai_adda_ops,
+	},
+};
+
+static int init_adda_priv_data(struct mtk_base_afe *afe)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_afe_adda_priv *adda_priv;
+	static const int adda_dai_list[] = {
+		MT8196_DAI_ADDA,
+		MT8196_DAI_ADDA_CH34,
+		MT8196_DAI_ADDA_CH56,
+		MT8196_DAI_AP_DMIC_MULTICH
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(adda_dai_list); i++) {
+		adda_priv = devm_kzalloc(afe->dev,
+					 sizeof(struct mtk_afe_adda_priv),
+					 GFP_KERNEL);
+		if (!adda_priv)
+			return -ENOMEM;
+
+		afe_priv->dai_priv[adda_dai_list[i]] = adda_priv;
+	}
+
+	/* ap dmic priv share with adda */
+	afe_priv->dai_priv[MT8196_DAI_AP_DMIC] =
+		afe_priv->dai_priv[MT8196_DAI_ADDA];
+	afe_priv->dai_priv[MT8196_DAI_AP_DMIC_CH34] =
+		afe_priv->dai_priv[MT8196_DAI_ADDA_CH34];
+
+	return 0;
+}
+
+int mt8196_dai_adda_register(struct mtk_base_afe *afe)
+{
+	struct mtk_base_afe_dai *dai;
+
+	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
+	if (!dai)
+		return -ENOMEM;
+
+	list_add(&dai->list, &afe->sub_dais);
+
+	dai->dai_drivers = mtk_dai_adda_driver;
+	dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
+
+	dai->controls = mtk_adda_controls;
+	dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
+	dai->dapm_widgets = mtk_dai_adda_widgets;
+	dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
+	dai->dapm_routes = mtk_dai_adda_routes;
+	dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
+
+	return init_adda_priv_data(afe);
+}
+
-- 
2.45.2



From julien.massot at collabora.com  Wed May 14 01:13:22 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Wed, 14 May 2025 10:13:22 +0200
Subject: [PATCH 2/4] dt-bindings: iommu: mediatek: mt8195 Accept up to 5
 interrupts
In-Reply-To: <ff8da58b-9e87-46d9-b4d2-4059ef05780d@collabora.com>
References: <20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb@collabora.com>
	 <20250505-mt8395-dtb-errors-v1-2-9c4714dcdcdb@collabora.com>
	 <baeae909-4d12-4cbd-a063-7ad165304b96@kernel.org>
	 <ff8da58b-9e87-46d9-b4d2-4059ef05780d@collabora.com>
Message-ID: <8cb04f202171821ceab379df78c4801f35443d77.camel@collabora.com>

Hi Krzysztof, Angelo,

On Thu, 2025-05-08 at 10:34 +0200, AngeloGioacchino Del Regno wrote:
> Il 08/05/25 08:03, Krzysztof Kozlowski ha scritto:
> > On 05/05/2025 15:23, Julien Massot wrote:
> > > 
> > > Fixes: 3b5838d1d82e3 ("arm64: dts: mt8195: Add iommu and smi nodes")
> > > Signed-off-by: Julien Massot <julien.massot at collabora.com>
> > > ---
> > > ? Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 3 ++-
> > > ? 1 file changed, 2 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > > b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > > index 75750c64157c868725c087500ac81be4e282c829..035941c2db32170e9a69a5363d8c05ef767bb251
> > > 100644
> > > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > > @@ -97,7 +97,8 @@ properties:
> > > ????? maxItems: 1
> > > ? 
> > > ??? interrupts:
> > > -??? maxItems: 1
> > > +??? minItems: 1
> > > +??? maxItems: 5
> > > ? 
> > Every iommu or just some (as described in commit msg) can have 5
> > interrupts? Looks you miss here proper constraints per variant.
> > 
> Technically, all of the IOMMUs can have more than one interrupt - but it's not
> clear which one and why, as documentation is lacking.
> 
> Let's restrict this discussion to MT8195 anyway, as it's the only one declaring
> those 5 interrupts...
> ...all of the IOMMUs declare just one, and mediatek,mt8195-iommu-infra declares 5.

Setting 5 interrupts will be restricted to mt8195 infra iommu in the v2.

Regards,
Julien


From darren.ye at mediatek.com  Wed May 14 01:11:08 2025
From: darren.ye at mediatek.com (Darren.Ye)
Date: Wed, 14 May 2025 16:11:08 +0800
Subject: [PATCH v3 06/10] ASoC: mediatek: mt8196: support TDM in platform driver
In-Reply-To: <20250514081125.24475-1-darren.ye@mediatek.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
Message-ID: <20250514081125.24475-7-darren.ye@mediatek.com>

From: Darren Ye <darren.ye at mediatek.com>

Add mt8196 TDM DAI driver support.

Signed-off-by: Darren Ye <darren.ye at mediatek.com>
---
 sound/soc/mediatek/mt8196/mt8196-dai-tdm.c | 862 +++++++++++++++++++++
 1 file changed, 862 insertions(+)
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-dai-tdm.c

diff --git a/sound/soc/mediatek/mt8196/mt8196-dai-tdm.c b/sound/soc/mediatek/mt8196/mt8196-dai-tdm.c
new file mode 100644
index 000000000000..c938d72ad39f
--- /dev/null
+++ b/sound/soc/mediatek/mt8196/mt8196-dai-tdm.c
@@ -0,0 +1,862 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *  MediaTek ALSA SoC Audio DAI TDM Control
+ *
+ *  Copyright (c) 2024 MediaTek Inc.
+ *  Author: Darren Ye <darren.ye at mediatek.com>
+ */
+
+#include <linux/regmap.h>
+#include <sound/pcm_params.h>
+#include "mt8196-afe-clk.h"
+#include "mt8196-afe-common.h"
+#include "mt8196-interconnection.h"
+
+struct mtk_afe_tdm_priv {
+	int bck_id;
+	int bck_rate;
+
+	int mclk_id;
+	int mclk_multiple; /* according to sample rate */
+	int mclk_rate;
+	int mclk_apll;
+};
+
+enum {
+	TDM_WLEN_16_BIT = 1,
+	TDM_WLEN_32_BIT = 2,
+};
+
+enum {
+	TDM_CHANNEL_BCK_16 = 0,
+	TDM_CHANNEL_BCK_24 = 1,
+	TDM_CHANNEL_BCK_32 = 2,
+};
+
+enum {
+	TDM_CHANNEL_NUM_2 = 0,
+	TDM_CHANNEL_NUM_4 = 1,
+	TDM_CHANNEL_NUM_8 = 2,
+};
+
+enum  {
+	TDM_CH_START_O30_O31 = 0,
+	TDM_CH_START_O32_O33,
+	TDM_CH_START_O34_O35,
+	TDM_CH_START_O36_O37,
+	TDM_CH_ZERO,
+};
+
+enum {
+	DPTX_CHANNEL_2,
+	DPTX_CHANNEL_8,
+};
+
+enum {
+	DPTX_WLEN_24_BIT,
+	DPTX_WLEN_16_BIT,
+};
+
+enum {
+	DPTX_CH_EN_MASK_2CH = 0x3,
+	DPTX_CH_EN_MASK_4CH = 0xf,
+	DPTX_CH_EN_MASK_6CH = 0x3f,
+	DPTX_CH_EN_MASK_8CH = 0xff,
+};
+
+static unsigned int get_tdm_wlen(snd_pcm_format_t format)
+{
+	return snd_pcm_format_physical_width(format) <= 16 ?
+	       TDM_WLEN_16_BIT : TDM_WLEN_32_BIT;
+}
+
+static unsigned int get_tdm_channel_bck(snd_pcm_format_t format)
+{
+	return snd_pcm_format_physical_width(format) <= 16 ?
+	       TDM_CHANNEL_BCK_16 : TDM_CHANNEL_BCK_32;
+}
+
+static unsigned int get_tdm_lrck_width(snd_pcm_format_t format)
+{
+	return snd_pcm_format_physical_width(format) - 1;
+}
+
+static unsigned int get_tdm_ch(unsigned int ch)
+{
+	switch (ch) {
+	case 1:
+	case 2:
+		return TDM_CHANNEL_NUM_2;
+	case 3:
+	case 4:
+		return TDM_CHANNEL_NUM_4;
+	case 5:
+	case 6:
+	case 7:
+	case 8:
+	default:
+		return TDM_CHANNEL_NUM_8;
+	}
+}
+
+static unsigned int get_dptx_ch_enable_mask(unsigned int ch)
+{
+	switch (ch) {
+	case 1:
+	case 2:
+		return DPTX_CH_EN_MASK_2CH;
+	case 3:
+	case 4:
+		return DPTX_CH_EN_MASK_4CH;
+	case 5:
+	case 6:
+		return DPTX_CH_EN_MASK_6CH;
+	case 7:
+	case 8:
+		return DPTX_CH_EN_MASK_8CH;
+	default:
+		pr_info("invalid channel num, default use 2ch\n");
+		return DPTX_CH_EN_MASK_2CH;
+	}
+}
+
+static unsigned int get_dptx_ch(unsigned int ch)
+{
+	if (ch == 2)
+		return DPTX_CHANNEL_2;
+	else
+		return DPTX_CHANNEL_8;
+}
+
+static unsigned int get_dptx_wlen(snd_pcm_format_t format)
+{
+	return snd_pcm_format_physical_width(format) <= 16 ?
+	       DPTX_WLEN_16_BIT : DPTX_WLEN_24_BIT;
+}
+
+/* interconnection */
+enum {
+	HDMI_CONN_CH0 = 0,
+	HDMI_CONN_CH1,
+	HDMI_CONN_CH2,
+	HDMI_CONN_CH3,
+	HDMI_CONN_CH4,
+	HDMI_CONN_CH5,
+	HDMI_CONN_CH6,
+	HDMI_CONN_CH7,
+};
+
+static const char *const hdmi_conn_mux_map[] = {
+	"CH0", "CH1", "CH2", "CH3",
+	"CH4", "CH5", "CH6", "CH7",
+};
+
+static int hdmi_conn_mux_map_value[] = {
+	HDMI_CONN_CH0,
+	HDMI_CONN_CH1,
+	HDMI_CONN_CH2,
+	HDMI_CONN_CH3,
+	HDMI_CONN_CH4,
+	HDMI_CONN_CH5,
+	HDMI_CONN_CH6,
+	HDMI_CONN_CH7,
+};
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum,
+				  AFE_HDMI_CONN0,
+				  HDMI_O_0_SFT,
+				  HDMI_O_0_MASK,
+				  hdmi_conn_mux_map,
+				  hdmi_conn_mux_map_value);
+
+static const struct snd_kcontrol_new hdmi_ch0_mux_control =
+	SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum);
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum,
+				  AFE_HDMI_CONN0,
+				  HDMI_O_1_SFT,
+				  HDMI_O_1_MASK,
+				  hdmi_conn_mux_map,
+				  hdmi_conn_mux_map_value);
+
+static const struct snd_kcontrol_new hdmi_ch1_mux_control =
+	SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum);
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum,
+				  AFE_HDMI_CONN0,
+				  HDMI_O_2_SFT,
+				  HDMI_O_2_MASK,
+				  hdmi_conn_mux_map,
+				  hdmi_conn_mux_map_value);
+
+static const struct snd_kcontrol_new hdmi_ch2_mux_control =
+	SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum);
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum,
+				  AFE_HDMI_CONN0,
+				  HDMI_O_3_SFT,
+				  HDMI_O_3_MASK,
+				  hdmi_conn_mux_map,
+				  hdmi_conn_mux_map_value);
+
+static const struct snd_kcontrol_new hdmi_ch3_mux_control =
+	SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum);
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum,
+				  AFE_HDMI_CONN0,
+				  HDMI_O_4_SFT,
+				  HDMI_O_4_MASK,
+				  hdmi_conn_mux_map,
+				  hdmi_conn_mux_map_value);
+
+static const struct snd_kcontrol_new hdmi_ch4_mux_control =
+	SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum);
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum,
+				  AFE_HDMI_CONN0,
+				  HDMI_O_5_SFT,
+				  HDMI_O_5_MASK,
+				  hdmi_conn_mux_map,
+				  hdmi_conn_mux_map_value);
+
+static const struct snd_kcontrol_new hdmi_ch5_mux_control =
+	SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum);
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum,
+				  AFE_HDMI_CONN0,
+				  HDMI_O_6_SFT,
+				  HDMI_O_6_MASK,
+				  hdmi_conn_mux_map,
+				  hdmi_conn_mux_map_value);
+
+static const struct snd_kcontrol_new hdmi_ch6_mux_control =
+	SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum);
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum,
+				  AFE_HDMI_CONN0,
+				  HDMI_O_7_SFT,
+				  HDMI_O_7_MASK,
+				  hdmi_conn_mux_map,
+				  hdmi_conn_mux_map_value);
+
+static const struct snd_kcontrol_new hdmi_ch7_mux_control =
+	SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum);
+
+static const char *const tdm_out_mux_map[] = {
+	"Disconnect", "Connect",
+};
+
+static int tdm_out_mux_map_value[] = {
+	0, 1,
+};
+
+static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum,
+		SND_SOC_NOPM,
+		0,
+		1,
+		tdm_out_mux_map,
+		tdm_out_mux_map_value);
+static const struct snd_kcontrol_new hdmi_out_mux_control =
+	SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum);
+
+static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum,
+		SND_SOC_NOPM,
+		0,
+		1,
+		tdm_out_mux_map,
+		tdm_out_mux_map_value);
+static const struct snd_kcontrol_new dptx_out_mux_control =
+	SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum);
+
+static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_virtual_out_mux_map_enum,
+		SND_SOC_NOPM,
+		0,
+		1,
+		tdm_out_mux_map,
+		tdm_out_mux_map_value);
+
+static const struct snd_kcontrol_new dptx_virtual_out_mux_control =
+	SOC_DAPM_ENUM("DPTX_VIRTUAL_OUT_MUX", dptx_virtual_out_mux_map_enum);
+
+enum {
+	SUPPLY_SEQ_APLL,
+	SUPPLY_SEQ_TDM_MCK_EN,
+	SUPPLY_SEQ_TDM_BCK_EN,
+	SUPPLY_SEQ_TDM_DPTX_MCK_EN,
+	SUPPLY_SEQ_TDM_DPTX_BCK_EN,
+	SUPPLY_SEQ_TDM_CG_EN,
+};
+
+static int get_tdm_id_by_name(const char *name)
+{
+	if (strstr(name, "DPTX"))
+		return MT8196_DAI_TDM_DPTX;
+	else
+		return MT8196_DAI_TDM;
+}
+
+static int mtk_tdm_bck_en_event(struct snd_soc_dapm_widget *w,
+				struct snd_kcontrol *kcontrol,
+				int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int dai_id = get_tdm_id_by_name(w->name);
+	struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
+
+	dev_dbg(cmpnt->dev, "name %s, event 0x%x, dai_id %d\n",
+		w->name, event, dai_id);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		mt8196_mck_enable(afe, tdm_priv->bck_id, tdm_priv->bck_rate);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		mt8196_mck_disable(afe, tdm_priv->bck_id);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int mtk_tdm_mck_en_event(struct snd_soc_dapm_widget *w,
+				struct snd_kcontrol *kcontrol,
+				int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int dai_id = get_tdm_id_by_name(w->name);
+	struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
+
+	dev_dbg(cmpnt->dev, "name %s, event 0x%x, dai_id %d\n",
+		w->name, event, dai_id);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		mt8196_mck_enable(afe, tdm_priv->mclk_id, tdm_priv->mclk_rate);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		tdm_priv->mclk_rate = 0;
+		mt8196_mck_disable(afe, tdm_priv->mclk_id);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int mtk_tdm_cg_event(struct snd_soc_dapm_widget *w,
+			    struct snd_kcontrol *kcontrol,
+			    int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int cg_id = MT8196_CLK_AFE_TDM_OUT;
+
+	dev_dbg(cmpnt->dev, "name %s, event 0x%x\n", w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		mt8196_afe_enable_clk(afe, afe_priv->clk[cg_id]);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		mt8196_afe_disable_clk(afe, afe_priv->clk[cg_id]);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static const struct snd_soc_dapm_widget mtk_dai_tdm_widgets[] = {
+	SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0,
+			 &hdmi_ch0_mux_control),
+	SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0,
+			 &hdmi_ch1_mux_control),
+	SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0,
+			 &hdmi_ch2_mux_control),
+	SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0,
+			 &hdmi_ch3_mux_control),
+	SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0,
+			 &hdmi_ch4_mux_control),
+	SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0,
+			 &hdmi_ch5_mux_control),
+	SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0,
+			 &hdmi_ch6_mux_control),
+	SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0,
+			 &hdmi_ch7_mux_control),
+	SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0,
+			 &hdmi_out_mux_control),
+	SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0,
+			 &dptx_out_mux_control),
+
+	SND_SOC_DAPM_SUPPLY_S("TDM_BCK", SUPPLY_SEQ_TDM_BCK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_tdm_bck_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_SUPPLY_S("TDM_MCK", SUPPLY_SEQ_TDM_MCK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_tdm_mck_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_SUPPLY_S("TDM_DPTX_BCK", SUPPLY_SEQ_TDM_DPTX_BCK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_tdm_bck_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_SUPPLY_S("TDM_DPTX_MCK", SUPPLY_SEQ_TDM_DPTX_MCK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_tdm_mck_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	/* cg */
+	SND_SOC_DAPM_SUPPLY_S("TDM_CG", SUPPLY_SEQ_TDM_CG_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_tdm_cg_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_MUX("DPTX_VIRTUAL_OUT_MUX",
+			 SND_SOC_NOPM, 0, 0, &dptx_virtual_out_mux_control),
+	SND_SOC_DAPM_OUTPUT("DPTX_VIRTUAL_OUT"),
+};
+
+static int mtk_afe_tdm_apll_connect(struct snd_soc_dapm_widget *source,
+				    struct snd_soc_dapm_widget *sink)
+{
+	struct snd_soc_dapm_widget *w = sink;
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int dai_id = get_tdm_id_by_name(w->name);
+	struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
+	int cur_apll;
+
+	/* which apll */
+	cur_apll = mt8196_get_apll_by_name(afe, source->name);
+
+	return (tdm_priv->mclk_apll == cur_apll) ? 1 : 0;
+}
+
+static const struct snd_soc_dapm_route mtk_dai_tdm_routes[] = {
+	{"HDMI_CH0_MUX", "CH0", "HDMI"},
+	{"HDMI_CH0_MUX", "CH1", "HDMI"},
+	{"HDMI_CH0_MUX", "CH2", "HDMI"},
+	{"HDMI_CH0_MUX", "CH3", "HDMI"},
+	{"HDMI_CH0_MUX", "CH4", "HDMI"},
+	{"HDMI_CH0_MUX", "CH5", "HDMI"},
+	{"HDMI_CH0_MUX", "CH6", "HDMI"},
+	{"HDMI_CH0_MUX", "CH7", "HDMI"},
+
+	{"HDMI_CH1_MUX", "CH0", "HDMI"},
+	{"HDMI_CH1_MUX", "CH1", "HDMI"},
+	{"HDMI_CH1_MUX", "CH2", "HDMI"},
+	{"HDMI_CH1_MUX", "CH3", "HDMI"},
+	{"HDMI_CH1_MUX", "CH4", "HDMI"},
+	{"HDMI_CH1_MUX", "CH5", "HDMI"},
+	{"HDMI_CH1_MUX", "CH6", "HDMI"},
+	{"HDMI_CH1_MUX", "CH7", "HDMI"},
+
+	{"HDMI_CH2_MUX", "CH0", "HDMI"},
+	{"HDMI_CH2_MUX", "CH1", "HDMI"},
+	{"HDMI_CH2_MUX", "CH2", "HDMI"},
+	{"HDMI_CH2_MUX", "CH3", "HDMI"},
+	{"HDMI_CH2_MUX", "CH4", "HDMI"},
+	{"HDMI_CH2_MUX", "CH5", "HDMI"},
+	{"HDMI_CH2_MUX", "CH6", "HDMI"},
+	{"HDMI_CH2_MUX", "CH7", "HDMI"},
+
+	{"HDMI_CH3_MUX", "CH0", "HDMI"},
+	{"HDMI_CH3_MUX", "CH1", "HDMI"},
+	{"HDMI_CH3_MUX", "CH2", "HDMI"},
+	{"HDMI_CH3_MUX", "CH3", "HDMI"},
+	{"HDMI_CH3_MUX", "CH4", "HDMI"},
+	{"HDMI_CH3_MUX", "CH5", "HDMI"},
+	{"HDMI_CH3_MUX", "CH6", "HDMI"},
+	{"HDMI_CH3_MUX", "CH7", "HDMI"},
+
+	{"HDMI_CH4_MUX", "CH0", "HDMI"},
+	{"HDMI_CH4_MUX", "CH1", "HDMI"},
+	{"HDMI_CH4_MUX", "CH2", "HDMI"},
+	{"HDMI_CH4_MUX", "CH3", "HDMI"},
+	{"HDMI_CH4_MUX", "CH4", "HDMI"},
+	{"HDMI_CH4_MUX", "CH5", "HDMI"},
+	{"HDMI_CH4_MUX", "CH6", "HDMI"},
+	{"HDMI_CH4_MUX", "CH7", "HDMI"},
+
+	{"HDMI_CH5_MUX", "CH0", "HDMI"},
+	{"HDMI_CH5_MUX", "CH1", "HDMI"},
+	{"HDMI_CH5_MUX", "CH2", "HDMI"},
+	{"HDMI_CH5_MUX", "CH3", "HDMI"},
+	{"HDMI_CH5_MUX", "CH4", "HDMI"},
+	{"HDMI_CH5_MUX", "CH5", "HDMI"},
+	{"HDMI_CH5_MUX", "CH6", "HDMI"},
+	{"HDMI_CH5_MUX", "CH7", "HDMI"},
+
+	{"HDMI_CH6_MUX", "CH0", "HDMI"},
+	{"HDMI_CH6_MUX", "CH1", "HDMI"},
+	{"HDMI_CH6_MUX", "CH2", "HDMI"},
+	{"HDMI_CH6_MUX", "CH3", "HDMI"},
+	{"HDMI_CH6_MUX", "CH4", "HDMI"},
+	{"HDMI_CH6_MUX", "CH5", "HDMI"},
+	{"HDMI_CH6_MUX", "CH6", "HDMI"},
+	{"HDMI_CH6_MUX", "CH7", "HDMI"},
+
+	{"HDMI_CH7_MUX", "CH0", "HDMI"},
+	{"HDMI_CH7_MUX", "CH1", "HDMI"},
+	{"HDMI_CH7_MUX", "CH2", "HDMI"},
+	{"HDMI_CH7_MUX", "CH3", "HDMI"},
+	{"HDMI_CH7_MUX", "CH4", "HDMI"},
+	{"HDMI_CH7_MUX", "CH5", "HDMI"},
+	{"HDMI_CH7_MUX", "CH6", "HDMI"},
+	{"HDMI_CH7_MUX", "CH7", "HDMI"},
+
+	{"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"},
+	{"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"},
+	{"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"},
+	{"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"},
+	{"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"},
+	{"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"},
+	{"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"},
+	{"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"},
+
+	{"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"},
+	{"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"},
+	{"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"},
+	{"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"},
+	{"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"},
+	{"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"},
+	{"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"},
+	{"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"},
+
+	{"TDM", NULL, "HDMI_OUT_MUX"},
+	{"TDM", NULL, "TDM_BCK"},
+	{"TDM", NULL, "TDM_CG"},
+
+	{"TDM_DPTX", NULL, "DPTX_OUT_MUX"},
+	{"TDM_DPTX", NULL, "TDM_DPTX_BCK"},
+	{"TDM_DPTX", NULL, "TDM_CG"},
+
+	{"TDM_BCK", NULL, "TDM_MCK"},
+	{"TDM_DPTX_BCK", NULL, "TDM_DPTX_MCK"},
+	{"TDM_MCK", NULL, APLL1_W_NAME, mtk_afe_tdm_apll_connect},
+	{"TDM_MCK", NULL, APLL2_W_NAME, mtk_afe_tdm_apll_connect},
+	{"TDM_DPTX_MCK", NULL, APLL1_W_NAME, mtk_afe_tdm_apll_connect},
+	{"TDM_DPTX_MCK", NULL, APLL2_W_NAME, mtk_afe_tdm_apll_connect},
+
+	{"DPTX_VIRTUAL_OUT_MUX", "Connect", "TDM_DPTX"},
+	{"DPTX_VIRTUAL_OUT", NULL, "DPTX_VIRTUAL_OUT_MUX"},
+};
+
+/* dai ops */
+static int mtk_dai_tdm_cal_mclk(struct mtk_base_afe *afe,
+				struct mtk_afe_tdm_priv *tdm_priv,
+				int freq)
+{
+	int apll;
+	int apll_rate;
+
+	apll = mt8196_get_apll_by_rate(afe, freq);
+	apll_rate = mt8196_get_apll_rate(afe, apll);
+
+	if (freq > apll_rate)
+		return -EINVAL;
+
+	if (apll_rate % freq != 0)
+		return -EINVAL;
+
+	tdm_priv->mclk_rate = freq;
+	tdm_priv->mclk_apll = apll;
+
+	return 0;
+}
+
+static int mtk_dai_tdm_hw_params(struct snd_pcm_substream *substream,
+				 struct snd_pcm_hw_params *params,
+				 struct snd_soc_dai *dai)
+{
+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int tdm_id = dai->id;
+	struct mtk_afe_tdm_priv *tdm_priv;
+	unsigned int rate = params_rate(params);
+	unsigned int channels = params_channels(params);
+	snd_pcm_format_t format = params_format(params);
+	unsigned int tdm_con = 0;
+
+	if (tdm_id >= MT8196_DAI_NUM || tdm_id < 0)
+		return -EINVAL;
+
+	tdm_priv = afe_priv->dai_priv[tdm_id];
+
+	if (!tdm_priv)
+		return -EINVAL;
+
+	/* calculate mclk_rate, if not set explicitly */
+	if (!tdm_priv->mclk_rate) {
+		tdm_priv->mclk_rate = rate * tdm_priv->mclk_multiple;
+		mtk_dai_tdm_cal_mclk(afe,
+				     tdm_priv,
+				     tdm_priv->mclk_rate);
+	}
+
+	/* calculate bck */
+	tdm_priv->bck_rate = rate *
+			     channels *
+			     snd_pcm_format_physical_width(format);
+
+	if (tdm_priv->bck_rate > tdm_priv->mclk_rate)
+		return -EINVAL;
+
+	if (tdm_priv->mclk_rate % tdm_priv->bck_rate != 0)
+		return -EINVAL;
+
+	dev_info(afe->dev, "id %d, rate %d, channels %d, format %d, mclk_rate %d, bck_rate %d\n",
+		 tdm_id, rate, channels, format,
+		 tdm_priv->mclk_rate, tdm_priv->bck_rate);
+
+	/* set tdm */
+	tdm_con = 0 << BCK_INVERSE_SFT;
+	tdm_con |= 0 << LRCK_INVERSE_SFT;
+	tdm_con |= 0 << DELAY_DATA_SFT;
+	tdm_con |= 1 << LEFT_ALIGN_SFT;
+	tdm_con |= get_tdm_wlen(format) << WLEN_SFT;
+	tdm_con |= get_tdm_ch(channels) << CHANNEL_NUM_SFT;
+	tdm_con |= get_tdm_channel_bck(format) << CHANNEL_BCK_CYCLES_SFT;
+	tdm_con |= get_tdm_lrck_width(format) << LRCK_TDM_WIDTH_SFT;
+	regmap_write(afe->regmap, AFE_TDM_CON1, tdm_con);
+
+	/* set dptx */
+	if (tdm_id == MT8196_DAI_TDM_DPTX) {
+		regmap_update_bits(afe->regmap, AFE_DPTX_CON,
+				   DPTX_CHANNEL_ENABLE_MASK_SFT,
+				   get_dptx_ch_enable_mask(channels) <<
+				   DPTX_CHANNEL_ENABLE_SFT);
+		regmap_update_bits(afe->regmap, AFE_DPTX_CON,
+				   DPTX_CHANNEL_NUMBER_MASK_SFT,
+				   get_dptx_ch(channels) <<
+				   DPTX_CHANNEL_NUMBER_SFT);
+		regmap_update_bits(afe->regmap, AFE_DPTX_CON,
+				   DPTX_16BIT_MASK_SFT,
+				   get_dptx_wlen(format) << DPTX_16BIT_SFT);
+	}
+		switch (channels) {
+		case 1:
+		case 2:
+			tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
+			tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT1_SFT;
+			tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
+			tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
+			break;
+		case 3:
+		case 4:
+			tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
+			tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
+			tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
+			tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
+			break;
+		case 5:
+		case 6:
+			tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
+			tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
+			tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;
+			tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
+			break;
+		case 7:
+		case 8:
+			tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
+			tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
+			tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;
+			tdm_con |= TDM_CH_START_O36_O37 << ST_CH_PAIR_SOUT3_SFT;
+			break;
+		default:
+			tdm_con = 0;
+		}
+	regmap_write(afe->regmap, AFE_TDM_CON2, tdm_con);
+	regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
+			   HDMI_CH_NUM_MASK_SFT,
+			   channels << HDMI_CH_NUM_SFT);
+
+	return 0;
+}
+
+static int mtk_dai_tdm_trigger(struct snd_pcm_substream *substream,
+			       int cmd,
+			       struct snd_soc_dai *dai)
+{
+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+	int tdm_id = dai->id;
+
+	dev_dbg(afe->dev, "cmd %d, tdm_id %d\n", cmd, tdm_id);
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+		/* enable Out control */
+		regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
+				   HDMI_OUT_ON_MASK_SFT,
+				   0x1 << HDMI_OUT_ON_SFT);
+
+		/* enable dptx */
+		if (tdm_id == MT8196_DAI_TDM_DPTX) {
+			regmap_update_bits(afe->regmap, AFE_DPTX_CON,
+					   DPTX_ON_MASK_SFT, 0x1 <<
+					   DPTX_ON_SFT);
+		}
+
+		/* enable tdm */
+		regmap_update_bits(afe->regmap, AFE_TDM_CON1,
+				   TDM_EN_MASK_SFT, 0x1 << TDM_EN_SFT);
+		break;
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+		/* disable tdm */
+		regmap_update_bits(afe->regmap, AFE_TDM_CON1,
+				   TDM_EN_MASK_SFT, 0);
+
+		/* disable dptx */
+		if (tdm_id == MT8196_DAI_TDM_DPTX) {
+			regmap_update_bits(afe->regmap, AFE_DPTX_CON,
+					   DPTX_ON_MASK_SFT, 0);
+		}
+
+		/* disable Out control */
+		regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
+				   HDMI_OUT_ON_MASK_SFT, 0);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int mtk_dai_tdm_set_sysclk(struct snd_soc_dai *dai,
+				  int clk_id, unsigned int freq, int dir)
+{
+	struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_afe_tdm_priv *tdm_priv;
+
+	if (dai->id >= MT8196_DAI_NUM || dai->id < 0)
+		return -EINVAL;
+
+	tdm_priv = afe_priv->dai_priv[dai->id];
+
+	if (!tdm_priv)
+		return -EINVAL;
+
+	if (dir != SND_SOC_CLOCK_OUT)
+		return -EINVAL;
+
+	dev_dbg(afe->dev, "freq %d\n", freq);
+
+	return mtk_dai_tdm_cal_mclk(afe, tdm_priv, freq);
+}
+
+static const struct snd_soc_dai_ops mtk_dai_tdm_ops = {
+	.hw_params = mtk_dai_tdm_hw_params,
+	.trigger = mtk_dai_tdm_trigger,
+	.set_sysclk = mtk_dai_tdm_set_sysclk,
+};
+
+/* dai driver */
+#define MTK_TDM_RATES (SNDRV_PCM_RATE_8000_48000 |\
+		       SNDRV_PCM_RATE_88200 |\
+		       SNDRV_PCM_RATE_96000 |\
+		       SNDRV_PCM_RATE_176400 |\
+		       SNDRV_PCM_RATE_192000)
+
+#define MTK_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+			 SNDRV_PCM_FMTBIT_S24_LE |\
+			 SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_driver mtk_dai_tdm_driver[] = {
+	{
+		.name = "TDM",
+		.id = MT8196_DAI_TDM,
+		.playback = {
+			.stream_name = "TDM",
+			.channels_min = 2,
+			.channels_max = 8,
+			.rates = MTK_TDM_RATES,
+			.formats = MTK_TDM_FORMATS,
+		},
+		.ops = &mtk_dai_tdm_ops,
+	},
+	{
+		.name = "TDM_DPTX",
+		.id = MT8196_DAI_TDM_DPTX,
+		.playback = {
+			.stream_name = "TDM_DPTX",
+			.channels_min = 2,
+			.channels_max = 8,
+			.rates = MTK_TDM_RATES,
+			.formats = MTK_TDM_FORMATS,
+		},
+		.ops = &mtk_dai_tdm_ops,
+	},
+};
+
+static struct mtk_afe_tdm_priv *init_tdm_priv_data(struct mtk_base_afe *afe,
+						   int id)
+{
+	struct mtk_afe_tdm_priv *tdm_priv;
+
+	tdm_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_afe_tdm_priv),
+				GFP_KERNEL);
+	if (!tdm_priv)
+		return NULL;
+
+	if (id == MT8196_DAI_TDM_DPTX)
+		tdm_priv->mclk_multiple = 256;
+	else
+		tdm_priv->mclk_multiple = 128;
+
+	tdm_priv->bck_id = MT8196_TDMOUT_BCK;
+	tdm_priv->mclk_id = MT8196_TDMOUT_MCK;
+
+	return tdm_priv;
+}
+
+int mt8196_dai_tdm_register(struct mtk_base_afe *afe)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_afe_tdm_priv *tdm_priv, *tdm_dptx_priv;
+	struct mtk_base_afe_dai *dai;
+
+	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
+	if (!dai)
+		return -ENOMEM;
+
+	list_add(&dai->list, &afe->sub_dais);
+
+	dai->dai_drivers = mtk_dai_tdm_driver;
+	dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_tdm_driver);
+
+	dai->dapm_widgets = mtk_dai_tdm_widgets;
+	dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_tdm_widgets);
+	dai->dapm_routes = mtk_dai_tdm_routes;
+	dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_tdm_routes);
+
+	tdm_priv = init_tdm_priv_data(afe, MT8196_DAI_TDM);
+	if (!tdm_priv)
+		return -ENOMEM;
+
+	tdm_dptx_priv = init_tdm_priv_data(afe, MT8196_DAI_TDM_DPTX);
+	if (!tdm_dptx_priv)
+		return -ENOMEM;
+
+	afe_priv->dai_priv[MT8196_DAI_TDM] = tdm_priv;
+	afe_priv->dai_priv[MT8196_DAI_TDM_DPTX] = tdm_dptx_priv;
+
+	return 0;
+}
+
-- 
2.45.2



From darren.ye at mediatek.com  Wed May 14 01:11:07 2025
From: darren.ye at mediatek.com (Darren.Ye)
Date: Wed, 14 May 2025 16:11:07 +0800
Subject: [PATCH v3 05/10] ASoC: mediatek: mt8196: support I2S in platform driver
In-Reply-To: <20250514081125.24475-1-darren.ye@mediatek.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
Message-ID: <20250514081125.24475-6-darren.ye@mediatek.com>

From: Darren Ye <darren.ye at mediatek.com>

Add mt8196 I2S DAI driver support.

Signed-off-by: Darren Ye <darren.ye at mediatek.com>
---
 sound/soc/mediatek/mt8196/mt8196-dai-i2s.c | 4052 ++++++++++++++++++++
 1 file changed, 4052 insertions(+)
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-dai-i2s.c

diff --git a/sound/soc/mediatek/mt8196/mt8196-dai-i2s.c b/sound/soc/mediatek/mt8196/mt8196-dai-i2s.c
new file mode 100644
index 000000000000..0d62e3ff22d0
--- /dev/null
+++ b/sound/soc/mediatek/mt8196/mt8196-dai-i2s.c
@@ -0,0 +1,4052 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *  MediaTek ALSA SoC Audio DAI I2S Control
+ *
+ *  Copyright (c) 2024 MediaTek Inc.
+ *  Author: Darren Ye <darren.ye at mediatek.com>
+ */
+
+#include <linux/bitops.h>
+#include <linux/regmap.h>
+#include <sound/pcm_params.h>
+#include "mt8196-afe-clk.h"
+#include "mt8196-afe-common.h"
+#include "mt8196-interconnection.h"
+#include "mtk-afe-fe-dai.h"
+
+#define ETDM_22M_CLOCK_THRES 11289600
+
+#define FM_SRC_CAIL
+enum {
+	ETDM_CLK_SOURCE_H26M = 0,
+	ETDM_CLK_SOURCE_APLL = 1,
+	ETDM_CLK_SOURCE_SPDIF = 2,
+	ETDM_CLK_SOURCE_HDMI = 3,
+	ETDM_CLK_SOURCE_EARC = 4,
+	ETDM_CLK_SOURCE_LINEIN = 5,
+};
+
+enum {
+	ETDM_RELATCH_SEL_H26M = 0,
+	ETDM_RELATCH_SEL_APLL = 1,
+};
+
+enum {
+	ETDM_RATE_8K = 0,
+	ETDM_RATE_12K = 1,
+	ETDM_RATE_16K = 2,
+	ETDM_RATE_24K = 3,
+	ETDM_RATE_32K = 4,
+	ETDM_RATE_48K = 5,
+	ETDM_RATE_64K = 6, //not support
+	ETDM_RATE_96K = 7,
+	ETDM_RATE_128K = 8, //not support
+	ETDM_RATE_192K = 9,
+	ETDM_RATE_256K = 10, //not support
+	ETDM_RATE_384K = 11,
+	ETDM_RATE_11025 = 16,
+	ETDM_RATE_22050 = 17,
+	ETDM_RATE_44100 = 18,
+	ETDM_RATE_88200 = 19,
+	ETDM_RATE_176400 = 20,
+	ETDM_RATE_352800 = 21,
+};
+
+enum {
+	ETDM_CONN_8K = 0,
+	ETDM_CONN_11K = 1,
+	ETDM_CONN_12K = 2,
+	ETDM_CONN_16K = 4,
+	ETDM_CONN_22K = 5,
+	ETDM_CONN_24K = 6,
+	ETDM_CONN_32K = 8,
+	ETDM_CONN_44K = 9,
+	ETDM_CONN_48K = 10,
+	ETDM_CONN_88K = 13,
+	ETDM_CONN_96K = 14,
+	ETDM_CONN_176K = 17,
+	ETDM_CONN_192K = 18,
+	ETDM_CONN_352K = 21,
+	ETDM_CONN_384K = 22,
+};
+
+enum {
+	ETDM_WLEN_8_BIT = 0x7,
+	ETDM_WLEN_16_BIT = 0xf,
+	ETDM_WLEN_32_BIT = 0x1f,
+};
+
+enum {
+	ETDM_SLAVE_SEL_ETDMIN0_MASTER = 0,
+	ETDM_SLAVE_SEL_ETDMIN0_SLAVE = 1,
+	ETDM_SLAVE_SEL_ETDMIN1_MASTER = 2,
+	ETDM_SLAVE_SEL_ETDMIN1_SLAVE = 3,
+	ETDM_SLAVE_SEL_ETDMIN2_MASTER = 4,
+	ETDM_SLAVE_SEL_ETDMIN2_SLAVE = 5,
+	ETDM_SLAVE_SEL_ETDMIN3_MASTER = 6,
+	ETDM_SLAVE_SEL_ETDMIN3_SLAVE = 7,
+	ETDM_SLAVE_SEL_ETDMOUT0_MASTER = 8,
+	ETDM_SLAVE_SEL_ETDMOUT0_SLAVE = 9,
+	ETDM_SLAVE_SEL_ETDMOUT1_MASTER = 10,
+	ETDM_SLAVE_SEL_ETDMOUT1_SLAVE = 11,
+	ETDM_SLAVE_SEL_ETDMOUT2_MASTER = 12,
+	ETDM_SLAVE_SEL_ETDMOUT2_SLAVE = 13,
+	ETDM_SLAVE_SEL_ETDMOUT3_MASTER = 14,
+	ETDM_SLAVE_SEL_ETDMOUT3_SLAVE = 15,
+};
+
+enum {
+	ETDM_SLAVE_SEL_ETDMIN4_MASTER = 0,
+	ETDM_SLAVE_SEL_ETDMIN4_SLAVE = 1,
+	ETDM_SLAVE_SEL_ETDMIN5_MASTER = 2,
+	ETDM_SLAVE_SEL_ETDMIN5_SLAVE = 3,
+	ETDM_SLAVE_SEL_ETDMIN6_MASTER = 4,
+	ETDM_SLAVE_SEL_ETDMIN6_SLAVE = 5,
+	ETDM_SLAVE_SEL_ETDMIN7_MASTER = 6,
+	ETDM_SLAVE_SEL_ETDMIN7_SLAVE = 7,
+	ETDM_SLAVE_SEL_ETDMOUT4_MASTER = 8,
+	ETDM_SLAVE_SEL_ETDMOUT4_SLAVE = 9,
+	ETDM_SLAVE_SEL_ETDMOUT5_MASTER = 10,
+	ETDM_SLAVE_SEL_ETDMOUT5_SLAVE = 11,
+	ETDM_SLAVE_SEL_ETDMOUT6_MASTER = 12,
+	ETDM_SLAVE_SEL_ETDMOUT6_SLAVE = 13,
+	ETDM_SLAVE_SEL_ETDMOUT7_MASTER = 14,
+	ETDM_SLAVE_SEL_ETDMOUT7_SLAVE = 15,
+};
+
+enum {
+	MTK_DAI_ETDM_FORMAT_I2S = 0,
+	MTK_DAI_ETDM_FORMAT_LJ,
+	MTK_DAI_ETDM_FORMAT_RJ,
+	MTK_DAI_ETDM_FORMAT_EIAJ,
+	MTK_DAI_ETDM_FORMAT_DSPA,
+	MTK_DAI_ETDM_FORMAT_DSPB,
+};
+
+static unsigned int get_etdm_wlen(snd_pcm_format_t format)
+{
+	unsigned int wlen = 0;
+
+	/* The reg_word_length should be >= reg_bit_length */
+	wlen = snd_pcm_format_physical_width(format);
+
+	if (wlen < 16)
+		return ETDM_WLEN_16_BIT;
+	else
+		return ETDM_WLEN_32_BIT;
+}
+
+static unsigned int get_etdm_lrck_width(snd_pcm_format_t format)
+{
+	/* The valid data bit number should be large than 7 due to hardware limitation. */
+	return snd_pcm_format_physical_width(format) - 1;
+}
+
+static unsigned int get_etdm_rate(unsigned int rate)
+{
+	switch (rate) {
+	case 8000:
+		return ETDM_RATE_8K;
+	case 12000:
+		return ETDM_RATE_12K;
+	case 16000:
+		return ETDM_RATE_16K;
+	case 24000:
+		return ETDM_RATE_24K;
+	case 32000:
+		return ETDM_RATE_32K;
+	case 48000:
+		return ETDM_RATE_48K;
+	case 64000:
+		return ETDM_RATE_64K;
+	case 96000:
+		return ETDM_RATE_96K;
+	case 128000:
+		return ETDM_RATE_128K;
+	case 192000:
+		return ETDM_RATE_192K;
+	case 256000:
+		return ETDM_RATE_256K;
+	case 384000:
+		return ETDM_RATE_384K;
+	case 11025:
+		return ETDM_RATE_11025;
+	case 22050:
+		return ETDM_RATE_22050;
+	case 44100:
+		return ETDM_RATE_44100;
+	case 88200:
+		return ETDM_RATE_88200;
+	case 176400:
+		return ETDM_RATE_176400;
+	case 352800:
+		return ETDM_RATE_352800;
+	default:
+		return 0;
+	}
+}
+
+static unsigned int get_etdm_inconn_rate(unsigned int rate)
+{
+	switch (rate) {
+	case 8000:
+		return ETDM_CONN_8K;
+	case 12000:
+		return ETDM_CONN_12K;
+	case 16000:
+		return ETDM_CONN_16K;
+	case 24000:
+		return ETDM_CONN_24K;
+	case 32000:
+		return ETDM_CONN_32K;
+	case 48000:
+		return ETDM_CONN_48K;
+	case 96000:
+		return ETDM_CONN_96K;
+	case 192000:
+		return ETDM_CONN_192K;
+	case 384000:
+		return ETDM_CONN_384K;
+	case 11025:
+		return ETDM_CONN_11K;
+	case 22050:
+		return ETDM_CONN_22K;
+	case 44100:
+		return ETDM_CONN_44K;
+	case 88200:
+		return ETDM_CONN_88K;
+	case 176400:
+		return ETDM_CONN_176K;
+	case 352800:
+		return ETDM_CONN_352K;
+	default:
+		return 0;
+	}
+}
+
+struct mtk_afe_i2s_priv {
+	int id;
+	int rate; /* for determine which apll to use */
+	int low_jitter_en;
+
+	const char *share_property_name;
+	int share_i2s_id;
+
+	int mclk_id;
+	int mclk_rate;
+	int mclk_apll;
+
+	int ch_num;
+	int sync;
+	int ip_mode;
+	int lpbk_mode;
+	unsigned int format;
+};
+
+/* this enum is merely for mtk_afe_i2s_priv & mtk_base_etdm_data declare */
+enum {
+	DAI_I2SIN0 = 0,
+	DAI_I2SIN1,
+	DAI_I2SIN2,
+	DAI_I2SIN3,
+	DAI_I2SIN4,
+	DAI_I2SIN6,
+	DAI_I2SOUT0,
+	DAI_I2SOUT1,
+	DAI_I2SOUT2,
+	DAI_I2SOUT3,
+	DAI_I2SOUT4,
+	DAI_I2SOUT6,
+	DAI_FMI2S_MASTER,
+	DAI_I2S_NUM,
+};
+
+static bool is_etdm_in_pad_top(unsigned int dai_num)
+{
+	if (dai_num >= DAI_I2S_NUM)
+		return false;
+
+	switch (dai_num) {
+	case DAI_I2SOUT4:
+	case DAI_I2SIN4:
+		return true;
+	default:
+		return false;
+	}
+}
+
+struct mtk_base_etdm_data {
+	int enable_reg;
+	int enable_mask;
+	int enable_shift;
+	int sync_reg;
+	int sync_mask;
+	int sync_shift;
+	int ch_reg;
+	int ch_mask;
+	int ch_shift;
+	int ip_mode_reg;
+	int ip_mode_mask;
+	int ip_mode_shift;
+	int init_count_reg;
+	int init_count_mask;
+	int init_count_shift;
+	int init_point_reg;
+	int init_point_mask;
+	int init_point_shift;
+	int lrck_reset_reg;
+	int lrck_reset_mask;
+	int lrck_reset_shift;
+	int clk_source_reg;
+	int clk_source_mask;
+	int clk_source_shift;
+	int ck_en_sel_reg;
+	int ck_en_sel_mask;
+	int ck_en_sel_shift;
+	int fs_timing_reg;
+	int fs_timing_mask;
+	int fs_timing_shift;
+	int relatch_en_sel_reg;
+	int relatch_en_sel_mask;
+	int relatch_en_sel_shift;
+	int use_afifo_reg;
+	int use_afifo_mask;
+	int use_afifo_shift;
+	int afifo_mode_reg;
+	int afifo_mode_mask;
+	int afifo_mode_shift;
+	int almost_end_ch_reg;
+	int almost_end_ch_mask;
+	int almost_end_ch_shift;
+	int almost_end_bit_reg;
+	int almost_end_bit_mask;
+	int almost_end_bit_shift;
+	int out2latch_time_reg;
+	int out2latch_time_mask;
+	int out2latch_time_shift;
+	int tdm_mode_reg;
+	int tdm_mode_mask;
+	int tdm_mode_shift;
+	int relatch_domain_sel_reg;
+	int relatch_domain_sel_mask;
+	int relatch_domain_sel_shift;
+	int bit_length_reg;
+	int bit_length_mask;
+	int bit_length_shift;
+	int word_length_reg;
+	int word_length_mask;
+	int word_length_shift;
+	int cowork_reg;
+	int cowork_mask;
+	int cowork_shift;
+	int cowork_val;
+	int in2latch_time_reg;
+	int in2latch_time_mask;
+	int in2latch_time_shift;
+	int pad_top_ck_en_reg;
+	int pad_top_ck_en_mask;
+	int pad_top_ck_en_shift;
+	int master_latch_reg;
+	int master_latch_mask;
+	int master_latch_shift;
+};
+
+const struct mtk_base_etdm_data mtk_etdm_data[DAI_I2S_NUM] = {
+	[DAI_I2SIN0] = {
+		.enable_reg = ETDM_IN0_CON0,
+		.enable_mask = REG_ETDM_IN_EN_MASK,
+		.enable_shift = REG_ETDM_IN_EN_SFT,
+		.sync_reg = ETDM_IN0_CON0,
+		.sync_mask = REG_SYNC_MODE_MASK,
+		.sync_shift = REG_SYNC_MODE_SFT,
+		.ch_reg = ETDM_IN0_CON0,
+		.ch_mask = REG_CH_NUM_MASK,
+		.ch_shift = REG_CH_NUM_SFT,
+		.ip_mode_reg = ETDM_IN0_CON2,
+		.ip_mode_mask = REG_MULTI_IP_MODE_MASK,
+		.ip_mode_shift = REG_MULTI_IP_MODE_SFT,
+		.init_count_reg = ETDM_IN0_CON1,
+		.init_count_mask = REG_INITIAL_COUNT_MASK,
+		.init_count_shift = REG_INITIAL_COUNT_SFT,
+		.init_point_reg = ETDM_IN0_CON1,
+		.init_point_mask = REG_INITIAL_POINT_MASK,
+		.init_point_shift = REG_INITIAL_POINT_SFT,
+		.lrck_reset_reg = ETDM_IN0_CON1,
+		.lrck_reset_mask = REG_LRCK_RESET_MASK,
+		.lrck_reset_shift = REG_LRCK_RESET_SFT,
+		.clk_source_reg = ETDM_IN0_CON2,
+		.clk_source_mask = REG_CLOCK_SOURCE_SEL_MASK,
+		.clk_source_shift = REG_CLOCK_SOURCE_SEL_SFT,
+		.ck_en_sel_reg = ETDM_IN0_CON2,
+		.ck_en_sel_mask = REG_CK_EN_SEL_AUTO_MASK,
+		.ck_en_sel_shift = REG_CK_EN_SEL_AUTO_SFT,
+		.fs_timing_reg = ETDM_IN0_CON3,
+		.fs_timing_mask = REG_FS_TIMING_SEL_MASK,
+		.fs_timing_shift = REG_FS_TIMING_SEL_SFT,
+		.relatch_en_sel_reg = ETDM_IN0_CON4,
+		.relatch_en_sel_mask = REG_RELATCH_1X_EN_SEL_MASK,
+		.relatch_en_sel_shift = REG_RELATCH_1X_EN_SEL_SFT,
+		.use_afifo_reg = ETDM_IN0_CON8,
+		.use_afifo_mask = REG_ETDM_USE_AFIFO_MASK,
+		.use_afifo_shift = REG_ETDM_USE_AFIFO_SFT,
+		.afifo_mode_reg = ETDM_IN0_CON8,
+		.afifo_mode_mask = REG_AFIFO_MODE_MASK,
+		.afifo_mode_shift = REG_AFIFO_MODE_SFT,
+		.almost_end_ch_reg = ETDM_IN0_CON9,
+		.almost_end_ch_mask = REG_ALMOST_END_CH_COUNT_MASK,
+		.almost_end_ch_shift = REG_ALMOST_END_CH_COUNT_SFT,
+		.almost_end_bit_reg = ETDM_IN0_CON9,
+		.almost_end_bit_mask = REG_ALMOST_END_BIT_COUNT_MASK,
+		.almost_end_bit_shift = REG_ALMOST_END_BIT_COUNT_SFT,
+		.out2latch_time_reg = ETDM_IN0_CON9,
+		.out2latch_time_mask = REG_OUT2LATCH_TIME_MASK,
+		.out2latch_time_shift = REG_OUT2LATCH_TIME_SFT,
+		.tdm_mode_reg = ETDM_IN0_CON0,
+		.tdm_mode_mask = REG_FMT_MASK,
+		.tdm_mode_shift = REG_FMT_SFT,
+		.relatch_domain_sel_reg = ETDM_IN0_CON0,
+		.relatch_domain_sel_mask = REG_RELATCH_1X_EN_DOMAIN_SEL_MASK,
+		.relatch_domain_sel_shift = REG_RELATCH_1X_EN_DOMAIN_SEL_SFT,
+		.bit_length_reg = ETDM_IN0_CON0,
+		.bit_length_mask = REG_BIT_LENGTH_MASK,
+		.bit_length_shift = REG_BIT_LENGTH_SFT,
+		.word_length_reg = ETDM_IN0_CON0,
+		.word_length_mask = REG_WORD_LENGTH_MASK,
+		.word_length_shift = REG_WORD_LENGTH_SFT,
+		.cowork_reg = ETDM_0_3_COWORK_CON0,
+		.cowork_mask = ETDM_IN0_SLAVE_SEL_MASK,
+		.cowork_shift = ETDM_IN0_SLAVE_SEL_SFT,
+		.cowork_val = ETDM_SLAVE_SEL_ETDMOUT0_MASTER,
+		.pad_top_ck_en_reg = -1,
+		.master_latch_reg = -1,
+	},
+	[DAI_I2SIN1] = {
+		.enable_reg = ETDM_IN1_CON0,
+		.enable_mask = REG_ETDM_IN_EN_MASK,
+		.enable_shift = REG_ETDM_IN_EN_SFT,
+		.sync_reg = ETDM_IN1_CON0,
+		.sync_mask = REG_SYNC_MODE_MASK,
+		.sync_shift = REG_SYNC_MODE_SFT,
+		.ch_reg = ETDM_IN1_CON0,
+		.ch_mask = REG_CH_NUM_MASK,
+		.ch_shift = REG_CH_NUM_SFT,
+		.ip_mode_reg = ETDM_IN1_CON2,
+		.ip_mode_mask = REG_MULTI_IP_MODE_MASK,
+		.ip_mode_shift = REG_MULTI_IP_MODE_SFT,
+		.init_count_reg = ETDM_IN1_CON1,
+		.init_count_mask = REG_INITIAL_COUNT_MASK,
+		.init_count_shift = REG_INITIAL_COUNT_SFT,
+		.init_point_reg = ETDM_IN1_CON1,
+		.init_point_mask = REG_INITIAL_POINT_MASK,
+		.init_point_shift = REG_INITIAL_POINT_SFT,
+		.lrck_reset_reg = ETDM_IN1_CON1,
+		.lrck_reset_mask = REG_LRCK_RESET_MASK,
+		.lrck_reset_shift = REG_LRCK_RESET_SFT,
+		.clk_source_reg = ETDM_IN1_CON2,
+		.clk_source_mask = REG_CLOCK_SOURCE_SEL_MASK,
+		.clk_source_shift = REG_CLOCK_SOURCE_SEL_SFT,
+		.ck_en_sel_reg = ETDM_IN1_CON2,
+		.ck_en_sel_mask = REG_CK_EN_SEL_AUTO_MASK,
+		.ck_en_sel_shift = REG_CK_EN_SEL_AUTO_SFT,
+		.fs_timing_reg = ETDM_IN1_CON3,
+		.fs_timing_mask = REG_FS_TIMING_SEL_MASK,
+		.fs_timing_shift = REG_FS_TIMING_SEL_SFT,
+		.relatch_en_sel_reg = ETDM_IN1_CON4,
+		.relatch_en_sel_mask = REG_RELATCH_1X_EN_SEL_MASK,
+		.relatch_en_sel_shift = REG_RELATCH_1X_EN_SEL_SFT,
+		.use_afifo_reg = ETDM_IN1_CON8,
+		.use_afifo_mask = REG_ETDM_USE_AFIFO_MASK,
+		.use_afifo_shift = REG_ETDM_USE_AFIFO_SFT,
+		.afifo_mode_reg = ETDM_IN1_CON8,
+		.afifo_mode_mask = REG_AFIFO_MODE_MASK,
+		.afifo_mode_shift = REG_AFIFO_MODE_SFT,
+		.almost_end_ch_reg = ETDM_IN1_CON9,
+		.almost_end_ch_mask = REG_ALMOST_END_CH_COUNT_MASK,
+		.almost_end_ch_shift = REG_ALMOST_END_CH_COUNT_SFT,
+		.almost_end_bit_reg = ETDM_IN1_CON9,
+		.almost_end_bit_mask = REG_ALMOST_END_BIT_COUNT_MASK,
+		.almost_end_bit_shift = REG_ALMOST_END_BIT_COUNT_SFT,
+		.out2latch_time_reg = ETDM_IN1_CON9,
+		.out2latch_time_mask = REG_OUT2LATCH_TIME_MASK,
+		.out2latch_time_shift = REG_OUT2LATCH_TIME_SFT,
+		.tdm_mode_reg = ETDM_IN1_CON0,
+		.tdm_mode_mask = REG_FMT_MASK,
+		.tdm_mode_shift = REG_FMT_SFT,
+		.relatch_domain_sel_reg = ETDM_IN1_CON0,
+		.relatch_domain_sel_mask = REG_RELATCH_1X_EN_DOMAIN_SEL_MASK,
+		.relatch_domain_sel_shift = REG_RELATCH_1X_EN_DOMAIN_SEL_SFT,
+		.bit_length_reg = ETDM_IN1_CON0,
+		.bit_length_mask = REG_BIT_LENGTH_MASK,
+		.bit_length_shift = REG_BIT_LENGTH_SFT,
+		.word_length_reg = ETDM_IN1_CON0,
+		.word_length_mask = REG_WORD_LENGTH_MASK,
+		.word_length_shift = REG_WORD_LENGTH_SFT,
+		.cowork_reg = ETDM_0_3_COWORK_CON1,
+		.cowork_mask = ETDM_IN1_SLAVE_SEL_MASK,
+		.cowork_shift = ETDM_IN1_SLAVE_SEL_SFT,
+		.cowork_val = ETDM_SLAVE_SEL_ETDMOUT1_MASTER,
+		.pad_top_ck_en_reg = -1,
+		.master_latch_reg = -1,
+	},
+	[DAI_I2SIN2] = {
+		.enable_reg = ETDM_IN2_CON0,
+		.enable_mask = REG_ETDM_IN_EN_MASK,
+		.enable_shift = REG_ETDM_IN_EN_SFT,
+		.sync_reg = ETDM_IN2_CON0,
+		.sync_mask = REG_SYNC_MODE_MASK,
+		.sync_shift = REG_SYNC_MODE_SFT,
+		.ch_reg = ETDM_IN2_CON0,
+		.ch_mask = REG_CH_NUM_MASK,
+		.ch_shift = REG_CH_NUM_SFT,
+		.ip_mode_reg = ETDM_IN2_CON2,
+		.ip_mode_mask = REG_MULTI_IP_MODE_MASK,
+		.ip_mode_shift = REG_MULTI_IP_MODE_SFT,
+		.init_count_reg = ETDM_IN2_CON1,
+		.init_count_mask = REG_INITIAL_COUNT_MASK,
+		.init_count_shift = REG_INITIAL_COUNT_SFT,
+		.init_point_reg = ETDM_IN2_CON1,
+		.init_point_mask = REG_INITIAL_POINT_MASK,
+		.init_point_shift = REG_INITIAL_POINT_SFT,
+		.lrck_reset_reg = ETDM_IN2_CON1,
+		.lrck_reset_mask = REG_LRCK_RESET_MASK,
+		.lrck_reset_shift = REG_LRCK_RESET_SFT,
+		.clk_source_reg = ETDM_IN2_CON2,
+		.clk_source_mask = REG_CLOCK_SOURCE_SEL_MASK,
+		.clk_source_shift = REG_CLOCK_SOURCE_SEL_SFT,
+		.ck_en_sel_reg = ETDM_IN2_CON2,
+		.ck_en_sel_mask = REG_CK_EN_SEL_AUTO_MASK,
+		.ck_en_sel_shift = REG_CK_EN_SEL_AUTO_SFT,
+		.fs_timing_reg = ETDM_IN2_CON3,
+		.fs_timing_mask = REG_FS_TIMING_SEL_MASK,
+		.fs_timing_shift = REG_FS_TIMING_SEL_SFT,
+		.relatch_en_sel_reg = ETDM_IN2_CON4,
+		.relatch_en_sel_mask = REG_RELATCH_1X_EN_SEL_MASK,
+		.relatch_en_sel_shift = REG_RELATCH_1X_EN_SEL_SFT,
+		.use_afifo_reg = ETDM_IN2_CON8,
+		.use_afifo_mask = REG_ETDM_USE_AFIFO_MASK,
+		.use_afifo_shift = REG_ETDM_USE_AFIFO_SFT,
+		.afifo_mode_reg = ETDM_IN2_CON8,
+		.afifo_mode_mask = REG_AFIFO_MODE_MASK,
+		.afifo_mode_shift = REG_AFIFO_MODE_SFT,
+		.almost_end_ch_reg = ETDM_IN2_CON9,
+		.almost_end_ch_mask = REG_ALMOST_END_CH_COUNT_MASK,
+		.almost_end_ch_shift = REG_ALMOST_END_CH_COUNT_SFT,
+		.almost_end_bit_reg = ETDM_IN2_CON9,
+		.almost_end_bit_mask = REG_ALMOST_END_BIT_COUNT_MASK,
+		.almost_end_bit_shift = REG_ALMOST_END_BIT_COUNT_SFT,
+		.out2latch_time_reg = ETDM_IN2_CON9,
+		.out2latch_time_mask = REG_OUT2LATCH_TIME_MASK,
+		.out2latch_time_shift = REG_OUT2LATCH_TIME_SFT,
+		.tdm_mode_reg = ETDM_IN2_CON0,
+		.tdm_mode_mask = REG_FMT_MASK,
+		.tdm_mode_shift = REG_FMT_SFT,
+		.relatch_domain_sel_reg = ETDM_IN2_CON0,
+		.relatch_domain_sel_mask = REG_RELATCH_1X_EN_DOMAIN_SEL_MASK,
+		.relatch_domain_sel_shift = REG_RELATCH_1X_EN_DOMAIN_SEL_SFT,
+		.bit_length_reg = ETDM_IN2_CON0,
+		.bit_length_mask = REG_BIT_LENGTH_MASK,
+		.bit_length_shift = REG_BIT_LENGTH_SFT,
+		.word_length_reg = ETDM_IN2_CON0,
+		.word_length_mask = REG_WORD_LENGTH_MASK,
+		.word_length_shift = REG_WORD_LENGTH_SFT,
+		.cowork_reg = ETDM_0_3_COWORK_CON2,
+		.cowork_mask = ETDM_IN2_SLAVE_SEL_MASK,
+		.cowork_shift = ETDM_IN2_SLAVE_SEL_SFT,
+		.cowork_val = ETDM_SLAVE_SEL_ETDMOUT2_MASTER,
+		.pad_top_ck_en_reg = -1,
+		.master_latch_reg = -1,
+	},
+	[DAI_I2SIN3] = {
+		.enable_reg = ETDM_IN3_CON0,
+		.enable_mask = REG_ETDM_IN_EN_MASK,
+		.enable_shift = REG_ETDM_IN_EN_SFT,
+		.sync_reg = ETDM_IN3_CON0,
+		.sync_mask = REG_SYNC_MODE_MASK,
+		.sync_shift = REG_SYNC_MODE_SFT,
+		.ch_reg = ETDM_IN3_CON0,
+		.ch_mask = REG_CH_NUM_MASK,
+		.ch_shift = REG_CH_NUM_SFT,
+		.ip_mode_reg = ETDM_IN3_CON2,
+		.ip_mode_mask = REG_MULTI_IP_MODE_MASK,
+		.ip_mode_shift = REG_MULTI_IP_MODE_SFT,
+		.init_count_reg = ETDM_IN3_CON1,
+		.init_count_mask = REG_INITIAL_COUNT_MASK,
+		.init_count_shift = REG_INITIAL_COUNT_SFT,
+		.init_point_reg = ETDM_IN3_CON1,
+		.init_point_mask = REG_INITIAL_POINT_MASK,
+		.init_point_shift = REG_INITIAL_POINT_SFT,
+		.lrck_reset_reg = ETDM_IN3_CON1,
+		.lrck_reset_mask = REG_LRCK_RESET_MASK,
+		.lrck_reset_shift = REG_LRCK_RESET_SFT,
+		.clk_source_reg = ETDM_IN3_CON2,
+		.clk_source_mask = REG_CLOCK_SOURCE_SEL_MASK,
+		.clk_source_shift = REG_CLOCK_SOURCE_SEL_SFT,
+		.ck_en_sel_reg = ETDM_IN3_CON2,
+		.ck_en_sel_mask = REG_CK_EN_SEL_AUTO_MASK,
+		.ck_en_sel_shift = REG_CK_EN_SEL_AUTO_SFT,
+		.fs_timing_reg = ETDM_IN3_CON3,
+		.fs_timing_mask = REG_FS_TIMING_SEL_MASK,
+		.fs_timing_shift = REG_FS_TIMING_SEL_SFT,
+		.relatch_en_sel_reg = ETDM_IN3_CON4,
+		.relatch_en_sel_mask = REG_RELATCH_1X_EN_SEL_MASK,
+		.relatch_en_sel_shift = REG_RELATCH_1X_EN_SEL_SFT,
+		.use_afifo_reg = ETDM_IN3_CON8,
+		.use_afifo_mask = REG_ETDM_USE_AFIFO_MASK,
+		.use_afifo_shift = REG_ETDM_USE_AFIFO_SFT,
+		.afifo_mode_reg = ETDM_IN3_CON8,
+		.afifo_mode_mask = REG_AFIFO_MODE_MASK,
+		.afifo_mode_shift = REG_AFIFO_MODE_SFT,
+		.almost_end_ch_reg = ETDM_IN3_CON9,
+		.almost_end_ch_mask = REG_ALMOST_END_CH_COUNT_MASK,
+		.almost_end_ch_shift = REG_ALMOST_END_CH_COUNT_SFT,
+		.almost_end_bit_reg = ETDM_IN3_CON9,
+		.almost_end_bit_mask = REG_ALMOST_END_BIT_COUNT_MASK,
+		.almost_end_bit_shift = REG_ALMOST_END_BIT_COUNT_SFT,
+		.out2latch_time_reg = ETDM_IN3_CON9,
+		.out2latch_time_mask = REG_OUT2LATCH_TIME_MASK,
+		.out2latch_time_shift = REG_OUT2LATCH_TIME_SFT,
+		.tdm_mode_reg = ETDM_IN3_CON0,
+		.tdm_mode_mask = REG_FMT_MASK,
+		.tdm_mode_shift = REG_FMT_SFT,
+		.relatch_domain_sel_reg = ETDM_IN3_CON0,
+		.relatch_domain_sel_mask = REG_RELATCH_1X_EN_DOMAIN_SEL_MASK,
+		.relatch_domain_sel_shift = REG_RELATCH_1X_EN_DOMAIN_SEL_SFT,
+		.bit_length_reg = ETDM_IN3_CON0,
+		.bit_length_mask = REG_BIT_LENGTH_MASK,
+		.bit_length_shift = REG_BIT_LENGTH_SFT,
+		.word_length_reg = ETDM_IN3_CON0,
+		.word_length_mask = REG_WORD_LENGTH_MASK,
+		.word_length_shift = REG_WORD_LENGTH_SFT,
+		.cowork_reg = ETDM_0_3_COWORK_CON3,
+		.cowork_mask = ETDM_IN3_SLAVE_SEL_MASK,
+		.cowork_shift = ETDM_IN3_SLAVE_SEL_SFT,
+		.cowork_val = ETDM_SLAVE_SEL_ETDMOUT3_MASTER,
+		.pad_top_ck_en_reg = -1,
+		.master_latch_reg = -1,
+	},
+	[DAI_I2SIN4] = {
+		.enable_reg = ETDM_IN4_CON0,
+		.enable_mask = REG_ETDM_IN_EN_MASK,
+		.enable_shift = REG_ETDM_IN_EN_SFT,
+		.sync_reg = ETDM_IN4_CON0,
+		.sync_mask = REG_SYNC_MODE_MASK,
+		.sync_shift = REG_SYNC_MODE_SFT,
+		.ch_reg = ETDM_IN4_CON0,
+		.ch_mask = REG_CH_NUM_MASK,
+		.ch_shift = REG_CH_NUM_SFT,
+		.ip_mode_reg = ETDM_IN4_CON2,
+		.ip_mode_mask = REG_MULTI_IP_MODE_MASK,
+		.ip_mode_shift = REG_MULTI_IP_MODE_SFT,
+		.init_count_reg = ETDM_IN4_CON1,
+		.init_count_mask = REG_INITIAL_COUNT_MASK,
+		.init_count_shift = REG_INITIAL_COUNT_SFT,
+		.init_point_reg = ETDM_IN4_CON1,
+		.init_point_mask = REG_INITIAL_POINT_MASK,
+		.init_point_shift = REG_INITIAL_POINT_SFT,
+		.lrck_reset_reg = ETDM_IN4_CON1,
+		.lrck_reset_mask = REG_LRCK_RESET_MASK,
+		.lrck_reset_shift = REG_LRCK_RESET_SFT,
+		.clk_source_reg = ETDM_IN4_CON2,
+		.clk_source_mask = REG_CLOCK_SOURCE_SEL_MASK,
+		.clk_source_shift = REG_CLOCK_SOURCE_SEL_SFT,
+		.ck_en_sel_reg = ETDM_IN4_CON2,
+		.ck_en_sel_mask = REG_CK_EN_SEL_AUTO_MASK,
+		.ck_en_sel_shift = REG_CK_EN_SEL_AUTO_SFT,
+		.fs_timing_reg = ETDM_IN4_CON3,
+		.fs_timing_mask = REG_FS_TIMING_SEL_MASK,
+		.fs_timing_shift = REG_FS_TIMING_SEL_SFT,
+		.relatch_en_sel_reg = ETDM_IN4_CON4,
+		.relatch_en_sel_mask = REG_RELATCH_1X_EN_SEL_MASK,
+		.relatch_en_sel_shift = REG_RELATCH_1X_EN_SEL_SFT,
+		.use_afifo_reg = ETDM_IN4_CON8,
+		.use_afifo_mask = REG_ETDM_USE_AFIFO_MASK,
+		.use_afifo_shift = REG_ETDM_USE_AFIFO_SFT,
+		.afifo_mode_reg = ETDM_IN4_CON8,
+		.afifo_mode_mask = REG_AFIFO_MODE_MASK,
+		.afifo_mode_shift = REG_AFIFO_MODE_SFT,
+		.almost_end_ch_reg = ETDM_IN4_CON9,
+		.almost_end_ch_mask = REG_ALMOST_END_CH_COUNT_MASK,
+		.almost_end_ch_shift = REG_ALMOST_END_CH_COUNT_SFT,
+		.almost_end_bit_reg = ETDM_IN4_CON9,
+		.almost_end_bit_mask = REG_ALMOST_END_BIT_COUNT_MASK,
+		.almost_end_bit_shift = REG_ALMOST_END_BIT_COUNT_SFT,
+		.out2latch_time_reg = ETDM_IN4_CON9,
+		.out2latch_time_mask = REG_OUT2LATCH_TIME_MASK,
+		.out2latch_time_shift = REG_OUT2LATCH_TIME_SFT,
+		.tdm_mode_reg = ETDM_IN4_CON0,
+		.tdm_mode_mask = REG_FMT_MASK,
+		.tdm_mode_shift = REG_FMT_SFT,
+		.relatch_domain_sel_reg = ETDM_IN4_CON0,
+		.relatch_domain_sel_mask = REG_RELATCH_1X_EN_DOMAIN_SEL_MASK,
+		.relatch_domain_sel_shift = REG_RELATCH_1X_EN_DOMAIN_SEL_SFT,
+		.bit_length_reg = ETDM_IN4_CON0,
+		.bit_length_mask = REG_BIT_LENGTH_MASK,
+		.bit_length_shift = REG_BIT_LENGTH_SFT,
+		.word_length_reg = ETDM_IN4_CON0,
+		.word_length_mask = REG_WORD_LENGTH_MASK,
+		.word_length_shift = REG_WORD_LENGTH_SFT,
+		.cowork_reg = ETDM_4_7_COWORK_CON0,
+		.cowork_mask = ETDM_IN4_SLAVE_SEL_MASK,
+		.cowork_shift = ETDM_IN4_SLAVE_SEL_SFT,
+		.cowork_val = ETDM_SLAVE_SEL_ETDMOUT4_MASTER,
+		.pad_top_ck_en_reg = AUD_TOP_CFG_VLP_RG,
+		.pad_top_ck_en_mask = RG_I2S4_PAD_TOP_CK_EN_MASK,
+		.pad_top_ck_en_shift = RG_I2S4_PAD_TOP_CK_EN_SFT,
+		.master_latch_reg = AUD_TOP_CFG_VLP_RG,
+		.master_latch_mask = RG_I2S4_IN_BCK_NEG_EG_LATCH_MASK,
+		.master_latch_shift = RG_I2S4_IN_BCK_NEG_EG_LATCH_SFT,
+	},
+	[DAI_I2SIN6] = {
+		.enable_reg = ETDM_IN6_CON0,
+		.enable_mask = REG_ETDM_IN_EN_MASK,
+		.enable_shift = REG_ETDM_IN_EN_SFT,
+		.sync_reg = ETDM_IN6_CON0,
+		.sync_mask = REG_SYNC_MODE_MASK,
+		.sync_shift = REG_SYNC_MODE_SFT,
+		.ch_reg = ETDM_IN6_CON0,
+		.ch_mask = REG_CH_NUM_MASK,
+		.ch_shift = REG_CH_NUM_SFT,
+		.ip_mode_reg = ETDM_IN6_CON2,
+		.ip_mode_mask = REG_MULTI_IP_MODE_MASK,
+		.ip_mode_shift = REG_MULTI_IP_MODE_SFT,
+		.init_count_reg = ETDM_IN6_CON1,
+		.init_count_mask = REG_INITIAL_COUNT_MASK,
+		.init_count_shift = REG_INITIAL_COUNT_SFT,
+		.init_point_reg = ETDM_IN6_CON1,
+		.init_point_mask = REG_INITIAL_POINT_MASK,
+		.init_point_shift = REG_INITIAL_POINT_SFT,
+		.lrck_reset_reg = ETDM_IN6_CON1,
+		.lrck_reset_mask = REG_LRCK_RESET_MASK,
+		.lrck_reset_shift = REG_LRCK_RESET_SFT,
+		.clk_source_reg = ETDM_IN6_CON2,
+		.clk_source_mask = REG_CLOCK_SOURCE_SEL_MASK,
+		.clk_source_shift = REG_CLOCK_SOURCE_SEL_SFT,
+		.ck_en_sel_reg = ETDM_IN6_CON2,
+		.ck_en_sel_mask = REG_CK_EN_SEL_AUTO_MASK,
+		.ck_en_sel_shift = REG_CK_EN_SEL_AUTO_SFT,
+		.fs_timing_reg = ETDM_IN6_CON3,
+		.fs_timing_mask = REG_FS_TIMING_SEL_MASK,
+		.fs_timing_shift = REG_FS_TIMING_SEL_SFT,
+		.relatch_en_sel_reg = ETDM_IN6_CON4,
+		.relatch_en_sel_mask = REG_RELATCH_1X_EN_SEL_MASK,
+		.relatch_en_sel_shift = REG_RELATCH_1X_EN_SEL_SFT,
+		.use_afifo_reg = ETDM_IN6_CON8,
+		.use_afifo_mask = REG_ETDM_USE_AFIFO_MASK,
+		.use_afifo_shift = REG_ETDM_USE_AFIFO_SFT,
+		.afifo_mode_reg = ETDM_IN6_CON8,
+		.afifo_mode_mask = REG_AFIFO_MODE_MASK,
+		.afifo_mode_shift = REG_AFIFO_MODE_SFT,
+		.almost_end_ch_reg = ETDM_IN6_CON9,
+		.almost_end_ch_mask = REG_ALMOST_END_CH_COUNT_MASK,
+		.almost_end_ch_shift = REG_ALMOST_END_CH_COUNT_SFT,
+		.almost_end_bit_reg = ETDM_IN6_CON9,
+		.almost_end_bit_mask = REG_ALMOST_END_BIT_COUNT_MASK,
+		.almost_end_bit_shift = REG_ALMOST_END_BIT_COUNT_SFT,
+		.out2latch_time_reg = ETDM_IN6_CON9,
+		.out2latch_time_mask = REG_OUT2LATCH_TIME_MASK,
+		.out2latch_time_shift = REG_OUT2LATCH_TIME_SFT,
+		.tdm_mode_reg = ETDM_IN6_CON0,
+		.tdm_mode_mask = REG_FMT_MASK,
+		.tdm_mode_shift = REG_FMT_SFT,
+		.relatch_domain_sel_reg = ETDM_IN6_CON0,
+		.relatch_domain_sel_mask = REG_RELATCH_1X_EN_DOMAIN_SEL_MASK,
+		.relatch_domain_sel_shift = REG_RELATCH_1X_EN_DOMAIN_SEL_SFT,
+		.bit_length_reg = ETDM_IN6_CON0,
+		.bit_length_mask = REG_BIT_LENGTH_MASK,
+		.bit_length_shift = REG_BIT_LENGTH_SFT,
+		.word_length_reg = ETDM_IN6_CON0,
+		.word_length_mask = REG_WORD_LENGTH_MASK,
+		.word_length_shift = REG_WORD_LENGTH_SFT,
+		.cowork_reg = ETDM_4_7_COWORK_CON2,
+		.cowork_mask = ETDM_IN6_SLAVE_SEL_MASK,
+		.cowork_shift = ETDM_IN6_SLAVE_SEL_SFT,
+		.cowork_val = ETDM_SLAVE_SEL_ETDMOUT6_MASTER,
+		.pad_top_ck_en_reg = -1,
+		.master_latch_reg = -1,
+	},
+	[DAI_I2SOUT0] = {
+		.enable_reg = ETDM_OUT0_CON0,
+		.enable_mask = OUT_REG_ETDM_OUT_EN_MASK,
+		.enable_shift = OUT_REG_ETDM_OUT_EN_SFT,
+		.sync_reg = ETDM_OUT0_CON0,
+		.sync_mask = REG_SYNC_MODE_MASK,
+		.sync_shift = REG_SYNC_MODE_SFT,
+		.ch_reg = ETDM_OUT0_CON0,
+		.ch_mask = REG_CH_NUM_MASK,
+		.ch_shift = REG_CH_NUM_SFT,
+		.init_count_reg = ETDM_OUT0_CON1,
+		.init_count_mask = OUT_REG_INITIAL_COUNT_MASK,
+		.init_count_shift = OUT_REG_INITIAL_COUNT_SFT,
+		.init_point_reg = ETDM_OUT0_CON1,
+		.init_point_mask = OUT_REG_INITIAL_POINT_MASK,
+		.init_point_shift = OUT_REG_INITIAL_POINT_SFT,
+		.lrck_reset_reg = ETDM_OUT0_CON1,
+		.lrck_reset_mask = OUT_REG_LRCK_RESET_MASK,
+		.lrck_reset_shift = OUT_REG_LRCK_RESET_SFT,
+		.clk_source_reg = ETDM_OUT0_CON4,
+		.clk_source_mask = OUT_REG_CLOCK_SOURCE_SEL_MASK,
+		.clk_source_shift = OUT_REG_CLOCK_SOURCE_SEL_SFT,
+		.fs_timing_reg = ETDM_OUT0_CON4,
+		.fs_timing_mask = OUT_REG_FS_TIMING_SEL_MASK,
+		.fs_timing_shift = OUT_REG_FS_TIMING_SEL_SFT,
+		.relatch_en_sel_reg = ETDM_OUT0_CON4,
+		.relatch_en_sel_mask = OUT_REG_RELATCH_EN_SEL_MASK,
+		.relatch_en_sel_shift = OUT_REG_RELATCH_EN_SEL_SFT,
+		.tdm_mode_reg = ETDM_OUT0_CON0,
+		.tdm_mode_mask = OUT_REG_FMT_MASK,
+		.tdm_mode_shift = OUT_REG_FMT_SFT,
+		.relatch_domain_sel_reg = ETDM_OUT0_CON0,
+		.relatch_domain_sel_mask = OUT_REG_RELATCH_DOMAIN_SEL_MASK,
+		.relatch_domain_sel_shift = OUT_REG_RELATCH_DOMAIN_SEL_SFT,
+		.bit_length_reg = ETDM_OUT0_CON0,
+		.bit_length_mask = OUT_REG_BIT_LENGTH_MASK,
+		.bit_length_shift = OUT_REG_BIT_LENGTH_SFT,
+		.word_length_reg = ETDM_OUT0_CON0,
+		.word_length_mask = OUT_REG_WORD_LENGTH_MASK,
+		.word_length_shift = OUT_REG_WORD_LENGTH_SFT,
+		.cowork_reg = ETDM_0_3_COWORK_CON0,
+		.cowork_mask = ETDM_OUT0_SLAVE_SEL_MASK,
+		.cowork_shift = ETDM_OUT0_SLAVE_SEL_SFT,
+		.cowork_val = ETDM_SLAVE_SEL_ETDMIN0_MASTER,
+		.in2latch_time_reg = ETDM_OUT0_CON2,
+		.in2latch_time_mask = OUT_REG_IN2LATCH_TIME_MASK,
+		.in2latch_time_shift = OUT_REG_IN2LATCH_TIME_SFT,
+		.pad_top_ck_en_reg = -1,
+		.master_latch_reg = -1,
+	},
+	[DAI_I2SOUT1] = {
+		.enable_reg = ETDM_OUT1_CON0,
+		.enable_mask = OUT_REG_ETDM_OUT_EN_MASK,
+		.enable_shift = OUT_REG_ETDM_OUT_EN_SFT,
+		.sync_reg = ETDM_OUT1_CON0,
+		.sync_mask = REG_SYNC_MODE_MASK,
+		.sync_shift = REG_SYNC_MODE_SFT,
+		.ch_reg = ETDM_OUT1_CON0,
+		.ch_mask = REG_CH_NUM_MASK,
+		.ch_shift = REG_CH_NUM_SFT,
+		.init_count_reg = ETDM_OUT1_CON1,
+		.init_count_mask = OUT_REG_INITIAL_COUNT_MASK,
+		.init_count_shift = OUT_REG_INITIAL_COUNT_SFT,
+		.init_point_reg = ETDM_OUT1_CON1,
+		.init_point_mask = OUT_REG_INITIAL_POINT_MASK,
+		.init_point_shift = OUT_REG_INITIAL_POINT_SFT,
+		.lrck_reset_reg = ETDM_OUT1_CON1,
+		.lrck_reset_mask = OUT_REG_LRCK_RESET_MASK,
+		.lrck_reset_shift = OUT_REG_LRCK_RESET_SFT,
+		.clk_source_reg = ETDM_OUT1_CON4,
+		.clk_source_mask = OUT_REG_CLOCK_SOURCE_SEL_MASK,
+		.clk_source_shift = OUT_REG_CLOCK_SOURCE_SEL_SFT,
+		.fs_timing_reg = ETDM_OUT1_CON4,
+		.fs_timing_mask = OUT_REG_FS_TIMING_SEL_MASK,
+		.fs_timing_shift = OUT_REG_FS_TIMING_SEL_SFT,
+		.relatch_en_sel_reg = ETDM_OUT1_CON4,
+		.relatch_en_sel_mask = OUT_REG_RELATCH_EN_SEL_MASK,
+		.relatch_en_sel_shift = OUT_REG_RELATCH_EN_SEL_SFT,
+		.tdm_mode_reg = ETDM_OUT1_CON0,
+		.tdm_mode_mask = OUT_REG_FMT_MASK,
+		.tdm_mode_shift = OUT_REG_FMT_SFT,
+		.relatch_domain_sel_reg = ETDM_OUT1_CON0,
+		.relatch_domain_sel_mask = OUT_REG_RELATCH_DOMAIN_SEL_MASK,
+		.relatch_domain_sel_shift = OUT_REG_RELATCH_DOMAIN_SEL_SFT,
+		.bit_length_reg = ETDM_OUT1_CON0,
+		.bit_length_mask = OUT_REG_BIT_LENGTH_MASK,
+		.bit_length_shift = OUT_REG_BIT_LENGTH_SFT,
+		.word_length_reg = ETDM_OUT1_CON0,
+		.word_length_mask = OUT_REG_WORD_LENGTH_MASK,
+		.word_length_shift = OUT_REG_WORD_LENGTH_SFT,
+		.cowork_reg = ETDM_0_3_COWORK_CON0,
+		.cowork_mask = ETDM_OUT1_SLAVE_SEL_MASK,
+		.cowork_shift = ETDM_OUT1_SLAVE_SEL_SFT,
+		.cowork_val = ETDM_SLAVE_SEL_ETDMIN1_MASTER,
+		.in2latch_time_reg = ETDM_OUT1_CON2,
+		.in2latch_time_mask = OUT_REG_IN2LATCH_TIME_MASK,
+		.in2latch_time_shift = OUT_REG_IN2LATCH_TIME_SFT,
+		.pad_top_ck_en_reg = -1,
+		.master_latch_reg = -1,
+	},
+	[DAI_I2SOUT2] = {
+		.enable_reg = ETDM_OUT2_CON0,
+		.enable_mask = OUT_REG_ETDM_OUT_EN_MASK,
+		.enable_shift = OUT_REG_ETDM_OUT_EN_SFT,
+		.sync_reg = ETDM_OUT2_CON0,
+		.sync_mask = REG_SYNC_MODE_MASK,
+		.sync_shift = REG_SYNC_MODE_SFT,
+		.ch_reg = ETDM_OUT2_CON0,
+		.ch_mask = REG_CH_NUM_MASK,
+		.ch_shift = REG_CH_NUM_SFT,
+		.init_count_reg = ETDM_OUT2_CON1,
+		.init_count_mask = OUT_REG_INITIAL_COUNT_MASK,
+		.init_count_shift = OUT_REG_INITIAL_COUNT_SFT,
+		.init_point_reg = ETDM_OUT2_CON1,
+		.init_point_mask = OUT_REG_INITIAL_POINT_MASK,
+		.init_point_shift = OUT_REG_INITIAL_POINT_SFT,
+		.lrck_reset_reg = ETDM_OUT2_CON1,
+		.lrck_reset_mask = OUT_REG_LRCK_RESET_MASK,
+		.lrck_reset_shift = OUT_REG_LRCK_RESET_SFT,
+		.clk_source_reg = ETDM_OUT2_CON4,
+		.clk_source_mask = OUT_REG_CLOCK_SOURCE_SEL_MASK,
+		.clk_source_shift = OUT_REG_CLOCK_SOURCE_SEL_SFT,
+		.fs_timing_reg = ETDM_OUT2_CON4,
+		.fs_timing_mask = OUT_REG_FS_TIMING_SEL_MASK,
+		.fs_timing_shift = OUT_REG_FS_TIMING_SEL_SFT,
+		.relatch_en_sel_reg = ETDM_OUT2_CON4,
+		.relatch_en_sel_mask = OUT_REG_RELATCH_EN_SEL_MASK,
+		.relatch_en_sel_shift = OUT_REG_RELATCH_EN_SEL_SFT,
+		.tdm_mode_reg = ETDM_OUT2_CON0,
+		.tdm_mode_mask = OUT_REG_FMT_MASK,
+		.tdm_mode_shift = OUT_REG_FMT_SFT,
+		.relatch_domain_sel_reg = ETDM_OUT2_CON0,
+		.relatch_domain_sel_mask = OUT_REG_RELATCH_DOMAIN_SEL_MASK,
+		.relatch_domain_sel_shift = OUT_REG_RELATCH_DOMAIN_SEL_SFT,
+		.bit_length_reg = ETDM_OUT2_CON0,
+		.bit_length_mask = OUT_REG_BIT_LENGTH_MASK,
+		.bit_length_shift = OUT_REG_BIT_LENGTH_SFT,
+		.word_length_reg = ETDM_OUT2_CON0,
+		.word_length_mask = OUT_REG_WORD_LENGTH_MASK,
+		.word_length_shift = OUT_REG_WORD_LENGTH_SFT,
+		.cowork_reg = ETDM_0_3_COWORK_CON2,
+		.cowork_mask = ETDM_OUT2_SLAVE_SEL_MASK,
+		.cowork_shift = ETDM_OUT2_SLAVE_SEL_SFT,
+		.cowork_val = ETDM_SLAVE_SEL_ETDMIN2_MASTER,
+		.in2latch_time_reg = ETDM_OUT2_CON2,
+		.in2latch_time_mask = OUT_REG_IN2LATCH_TIME_MASK,
+		.in2latch_time_shift = OUT_REG_IN2LATCH_TIME_SFT,
+		.pad_top_ck_en_reg = -1,
+		.master_latch_reg = -1,
+	},
+	[DAI_I2SOUT3] = {
+		.enable_reg = ETDM_OUT3_CON0,
+		.enable_mask = OUT_REG_ETDM_OUT_EN_MASK,
+		.enable_shift = OUT_REG_ETDM_OUT_EN_SFT,
+		.sync_reg = ETDM_OUT3_CON0,
+		.sync_mask = REG_SYNC_MODE_MASK,
+		.sync_shift = REG_SYNC_MODE_SFT,
+		.ch_reg = ETDM_OUT3_CON0,
+		.ch_mask = REG_CH_NUM_MASK,
+		.ch_shift = REG_CH_NUM_SFT,
+		.init_count_reg = ETDM_OUT3_CON1,
+		.init_count_mask = OUT_REG_INITIAL_COUNT_MASK,
+		.init_count_shift = OUT_REG_INITIAL_COUNT_SFT,
+		.init_point_reg = ETDM_OUT3_CON1,
+		.init_point_mask = OUT_REG_INITIAL_POINT_MASK,
+		.init_point_shift = OUT_REG_INITIAL_POINT_SFT,
+		.lrck_reset_reg = ETDM_OUT3_CON1,
+		.lrck_reset_mask = OUT_REG_LRCK_RESET_MASK,
+		.lrck_reset_shift = OUT_REG_LRCK_RESET_SFT,
+		.clk_source_reg = ETDM_OUT3_CON4,
+		.clk_source_mask = OUT_REG_CLOCK_SOURCE_SEL_MASK,
+		.clk_source_shift = OUT_REG_CLOCK_SOURCE_SEL_SFT,
+		.fs_timing_reg = ETDM_OUT3_CON4,
+		.fs_timing_mask = OUT_REG_FS_TIMING_SEL_MASK,
+		.fs_timing_shift = OUT_REG_FS_TIMING_SEL_SFT,
+		.relatch_en_sel_reg = ETDM_OUT3_CON4,
+		.relatch_en_sel_mask = OUT_REG_RELATCH_EN_SEL_MASK,
+		.relatch_en_sel_shift = OUT_REG_RELATCH_EN_SEL_SFT,
+		.tdm_mode_reg = ETDM_OUT3_CON0,
+		.tdm_mode_mask = OUT_REG_FMT_MASK,
+		.tdm_mode_shift = OUT_REG_FMT_SFT,
+		.relatch_domain_sel_reg = ETDM_OUT3_CON0,
+		.relatch_domain_sel_mask = OUT_REG_RELATCH_DOMAIN_SEL_MASK,
+		.relatch_domain_sel_shift = OUT_REG_RELATCH_DOMAIN_SEL_SFT,
+		.bit_length_reg = ETDM_OUT3_CON0,
+		.bit_length_mask = OUT_REG_BIT_LENGTH_MASK,
+		.bit_length_shift = OUT_REG_BIT_LENGTH_SFT,
+		.word_length_reg = ETDM_OUT3_CON0,
+		.word_length_mask = OUT_REG_WORD_LENGTH_MASK,
+		.word_length_shift = OUT_REG_WORD_LENGTH_SFT,
+		.cowork_reg = ETDM_0_3_COWORK_CON2,
+		.cowork_mask = ETDM_OUT3_SLAVE_SEL_MASK,
+		.cowork_shift = ETDM_OUT3_SLAVE_SEL_SFT,
+		.cowork_val = ETDM_SLAVE_SEL_ETDMIN3_MASTER,
+		.in2latch_time_reg = ETDM_OUT3_CON2,
+		.in2latch_time_mask = OUT_REG_IN2LATCH_TIME_MASK,
+		.in2latch_time_shift = OUT_REG_IN2LATCH_TIME_SFT,
+		.pad_top_ck_en_reg = -1,
+		.master_latch_reg = -1,
+	},
+	[DAI_I2SOUT4] = {
+		.enable_reg = ETDM_OUT4_CON0,
+		.enable_mask = OUT_REG_ETDM_OUT_EN_MASK,
+		.enable_shift = OUT_REG_ETDM_OUT_EN_SFT,
+		.sync_reg = ETDM_OUT4_CON0,
+		.sync_mask = REG_SYNC_MODE_MASK,
+		.sync_shift = REG_SYNC_MODE_SFT,
+		.ch_reg = ETDM_OUT4_CON0,
+		.ch_mask = REG_CH_NUM_MASK,
+		.ch_shift = REG_CH_NUM_SFT,
+		.init_count_reg = ETDM_OUT4_CON1,
+		.init_count_mask = OUT_REG_INITIAL_COUNT_MASK,
+		.init_count_shift = OUT_REG_INITIAL_COUNT_SFT,
+		.init_point_reg = ETDM_OUT4_CON1,
+		.init_point_mask = OUT_REG_INITIAL_POINT_MASK,
+		.init_point_shift = OUT_REG_INITIAL_POINT_SFT,
+		.lrck_reset_reg = ETDM_OUT4_CON1,
+		.lrck_reset_mask = OUT_REG_LRCK_RESET_MASK,
+		.lrck_reset_shift = OUT_REG_LRCK_RESET_SFT,
+		.clk_source_reg = ETDM_OUT4_CON4,
+		.clk_source_mask = OUT_REG_CLOCK_SOURCE_SEL_MASK,
+		.clk_source_shift = OUT_REG_CLOCK_SOURCE_SEL_SFT,
+		.fs_timing_reg = ETDM_OUT4_CON4,
+		.fs_timing_mask = OUT_REG_FS_TIMING_SEL_MASK,
+		.fs_timing_shift = OUT_REG_FS_TIMING_SEL_SFT,
+		.relatch_en_sel_reg = ETDM_OUT4_CON4,
+		.relatch_en_sel_mask = OUT_REG_RELATCH_EN_SEL_MASK,
+		.relatch_en_sel_shift = OUT_REG_RELATCH_EN_SEL_SFT,
+		.tdm_mode_reg = ETDM_OUT4_CON0,
+		.tdm_mode_mask = OUT_REG_FMT_MASK,
+		.tdm_mode_shift = OUT_REG_FMT_SFT,
+		.relatch_domain_sel_reg = ETDM_OUT4_CON0,
+		.relatch_domain_sel_mask = OUT_REG_RELATCH_DOMAIN_SEL_MASK,
+		.relatch_domain_sel_shift = OUT_REG_RELATCH_DOMAIN_SEL_SFT,
+		.bit_length_reg = ETDM_OUT4_CON0,
+		.bit_length_mask = OUT_REG_BIT_LENGTH_MASK,
+		.bit_length_shift = OUT_REG_BIT_LENGTH_SFT,
+		.word_length_reg = ETDM_OUT4_CON0,
+		.word_length_mask = OUT_REG_WORD_LENGTH_MASK,
+		.word_length_shift = OUT_REG_WORD_LENGTH_SFT,
+		.cowork_reg = ETDM_4_7_COWORK_CON0,
+		.cowork_mask = ETDM_OUT4_SLAVE_SEL_MASK,
+		.cowork_shift = ETDM_OUT4_SLAVE_SEL_SFT,
+		.cowork_val = ETDM_SLAVE_SEL_ETDMIN4_MASTER,
+		.in2latch_time_reg = ETDM_OUT4_CON2,
+		.in2latch_time_mask = OUT_REG_IN2LATCH_TIME_MASK,
+		.in2latch_time_shift = OUT_REG_IN2LATCH_TIME_SFT,
+		.pad_top_ck_en_reg = AUD_TOP_CFG_VLP_RG,
+		.pad_top_ck_en_mask = RG_I2S4_PAD_TOP_CK_EN_MASK,
+		.pad_top_ck_en_shift = RG_I2S4_PAD_TOP_CK_EN_SFT,
+		.master_latch_reg = AUD_TOP_CFG_VLP_RG,
+		.master_latch_mask = RG_I2S4_OUT_BCK_NEG_EG_LATCH_MASK,
+		.master_latch_shift = RG_I2S4_OUT_BCK_NEG_EG_LATCH_SFT,
+	},
+	[DAI_I2SOUT6] = {
+		.enable_reg = ETDM_OUT6_CON0,
+		.enable_mask = OUT_REG_ETDM_OUT_EN_MASK,
+		.enable_shift = OUT_REG_ETDM_OUT_EN_SFT,
+		.sync_reg = ETDM_OUT6_CON0,
+		.sync_mask = REG_SYNC_MODE_MASK,
+		.sync_shift = REG_SYNC_MODE_SFT,
+		.ch_reg = ETDM_OUT6_CON0,
+		.ch_mask = REG_CH_NUM_MASK,
+		.ch_shift = REG_CH_NUM_SFT,
+		.init_count_reg = ETDM_OUT6_CON1,
+		.init_count_mask = OUT_REG_INITIAL_COUNT_MASK,
+		.init_count_shift = OUT_REG_INITIAL_COUNT_SFT,
+		.init_point_reg = ETDM_OUT6_CON1,
+		.init_point_mask = OUT_REG_INITIAL_POINT_MASK,
+		.init_point_shift = OUT_REG_INITIAL_POINT_SFT,
+		.lrck_reset_reg = ETDM_OUT6_CON1,
+		.lrck_reset_mask = OUT_REG_LRCK_RESET_MASK,
+		.lrck_reset_shift = OUT_REG_LRCK_RESET_SFT,
+		.clk_source_reg = ETDM_OUT6_CON4,
+		.clk_source_mask = OUT_REG_CLOCK_SOURCE_SEL_MASK,
+		.clk_source_shift = OUT_REG_CLOCK_SOURCE_SEL_SFT,
+		.fs_timing_reg = ETDM_OUT6_CON4,
+		.fs_timing_mask = OUT_REG_FS_TIMING_SEL_MASK,
+		.fs_timing_shift = OUT_REG_FS_TIMING_SEL_SFT,
+		.relatch_en_sel_reg = ETDM_OUT6_CON4,
+		.relatch_en_sel_mask = OUT_REG_RELATCH_EN_SEL_MASK,
+		.relatch_en_sel_shift = OUT_REG_RELATCH_EN_SEL_SFT,
+		.tdm_mode_reg = ETDM_OUT6_CON0,
+		.tdm_mode_mask = OUT_REG_FMT_MASK,
+		.tdm_mode_shift = OUT_REG_FMT_SFT,
+		.relatch_domain_sel_reg = ETDM_OUT6_CON0,
+		.relatch_domain_sel_mask = OUT_REG_RELATCH_DOMAIN_SEL_MASK,
+		.relatch_domain_sel_shift = OUT_REG_RELATCH_DOMAIN_SEL_SFT,
+		.bit_length_reg = ETDM_OUT6_CON0,
+		.bit_length_mask = OUT_REG_BIT_LENGTH_MASK,
+		.bit_length_shift = OUT_REG_BIT_LENGTH_SFT,
+		.word_length_reg = ETDM_OUT6_CON0,
+		.word_length_mask = OUT_REG_WORD_LENGTH_MASK,
+		.word_length_shift = OUT_REG_WORD_LENGTH_SFT,
+		.cowork_reg = ETDM_4_7_COWORK_CON2,
+		.cowork_mask = ETDM_OUT6_SLAVE_SEL_MASK,
+		.cowork_shift = ETDM_OUT6_SLAVE_SEL_SFT,
+		.cowork_val = ETDM_SLAVE_SEL_ETDMIN6_MASTER,
+		.in2latch_time_reg = ETDM_OUT6_CON2,
+		.in2latch_time_mask = OUT_REG_IN2LATCH_TIME_MASK,
+		.in2latch_time_shift = OUT_REG_IN2LATCH_TIME_SFT,
+		.pad_top_ck_en_reg = -1,
+		.master_latch_reg = -1,
+	},
+
+};
+
+/* lpbk */
+static const int etdm_lpbk_idx_0[] = {
+	0x0, 0x8,
+};
+
+static const int etdm_lpbk_idx_1[] = {
+	0x2, 0xa,
+};
+
+static const int etdm_lpbk_idx_2[] = {
+	0x4, 0xc,
+};
+
+static const int etdm_lpbk_idx_3[] = {
+	0x6, 0xe,
+};
+
+static int etdm_lpbk_get(struct snd_kcontrol *kcontrol,
+			 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+		snd_soc_kcontrol_component(kcontrol);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
+	unsigned int value = 0;
+	unsigned int value_ipmode = 0;
+	unsigned int reg = 0;
+	unsigned int mask = 0;
+	unsigned int shift = 0;
+
+	if (!strcmp(kcontrol->id.name, "I2SIN0_LPBK")) {
+		reg = ETDM_0_3_COWORK_CON1;
+		mask = ETDM_IN0_SDATA0_SEL_MASK_SFT;
+		shift = ETDM_IN0_SDATA0_SEL_SFT;
+	} else if (!strcmp(kcontrol->id.name, "I2SIN1_LPBK")) {
+		reg = ETDM_0_3_COWORK_CON1;
+		mask = ETDM_IN1_SDATA0_SEL_MASK_SFT;
+		shift = ETDM_IN1_SDATA0_SEL_SFT;
+	} else if (!strcmp(kcontrol->id.name, "I2SIN2_LPBK")) {
+		reg = ETDM_0_3_COWORK_CON3;
+		mask = ETDM_IN2_SDATA0_SEL_MASK_SFT;
+		shift = ETDM_IN2_SDATA0_SEL_SFT;
+	} else if (!strcmp(kcontrol->id.name, "I2SIN3_LPBK")) {
+		reg = ETDM_0_3_COWORK_CON3;
+		mask = ETDM_IN3_SDATA0_SEL_MASK_SFT;
+		shift = ETDM_IN3_SDATA0_SEL_SFT;
+	} else if (!strcmp(kcontrol->id.name, "I2SIN4_LPBK")) {
+		reg = ETDM_4_7_COWORK_CON1;
+
+		// Get I2SIN4 multi-ip mode
+		regmap_read(afe->regmap, ETDM_IN4_CON2, &value_ipmode);
+		value_ipmode &= REG_MULTI_IP_MODE_MASK_SFT;
+		value_ipmode >>= REG_MULTI_IP_MODE_SFT;
+
+		if (value_ipmode) {
+			mask = ETDM_IN4_SDATA1_15_SEL_MASK_SFT;
+			shift = ETDM_IN4_SDATA1_15_SEL_SFT;
+		} else {
+			mask = ETDM_IN4_SDATA0_SEL_MASK_SFT;
+			shift = ETDM_IN4_SDATA0_SEL_SFT;
+		}
+	} else if (!strcmp(kcontrol->id.name, "I2SIN6_LPBK")) {
+		reg = ETDM_4_7_COWORK_CON3;
+		mask = ETDM_IN6_SDATA0_SEL_MASK_SFT;
+		shift = ETDM_IN6_SDATA0_SEL_SFT;
+	}
+
+	if (reg)
+		regmap_read(afe->regmap, reg, &value);
+
+	value &= mask;
+	value >>= shift;
+	ucontrol->value.enumerated.item[0] = value;
+
+	if (value == 0x8 || value == 0xa || value == 0xc || value == 0xe)
+		ucontrol->value.enumerated.item[0] = 1;
+	else
+		ucontrol->value.enumerated.item[0] = 0;
+
+	return 0;
+}
+
+static int etdm_lpbk_put(struct snd_kcontrol *kcontrol,
+			 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
+	unsigned int value = ucontrol->value.integer.value[0];
+	unsigned int value_ipmode = 0;
+	unsigned int reg = 0;
+	unsigned int val = 0;
+	unsigned int mask = 0;
+
+	if (value >= ARRAY_SIZE(etdm_lpbk_idx_0))
+		return -EINVAL;
+
+	if (!strcmp(kcontrol->id.name, "I2SIN0_LPBK")) {
+		reg = ETDM_0_3_COWORK_CON1;
+		mask = ETDM_IN0_SDATA0_SEL_MASK_SFT;
+		val = etdm_lpbk_idx_0[value] << ETDM_IN0_SDATA0_SEL_SFT;
+	} else if (!strcmp(kcontrol->id.name, "I2SIN1_LPBK")) {
+		reg = ETDM_0_3_COWORK_CON1;
+		mask = ETDM_IN1_SDATA0_SEL_MASK_SFT;
+		val = etdm_lpbk_idx_1[value] << ETDM_IN1_SDATA0_SEL_SFT;
+	} else if (!strcmp(kcontrol->id.name, "I2SIN2_LPBK")) {
+		reg = ETDM_0_3_COWORK_CON3;
+		mask = ETDM_IN2_SDATA0_SEL_MASK_SFT;
+		val = etdm_lpbk_idx_2[value] << ETDM_IN2_SDATA0_SEL_SFT;
+	} else if (!strcmp(kcontrol->id.name, "I2SIN3_LPBK")) {
+		reg = ETDM_0_3_COWORK_CON3;
+		mask = ETDM_IN3_SDATA0_SEL_MASK_SFT;
+		val = etdm_lpbk_idx_3[value] << ETDM_IN3_SDATA0_SEL_SFT;
+	} else if (!strcmp(kcontrol->id.name, "I2SIN4_LPBK")) {
+		reg = ETDM_4_7_COWORK_CON1;
+
+		// Get I2SIN4 multi-ip mode
+		regmap_read(afe->regmap, ETDM_IN4_CON2, &value_ipmode);
+		value_ipmode &= REG_MULTI_IP_MODE_MASK_SFT;
+		value_ipmode >>= REG_MULTI_IP_MODE_SFT;
+
+		if (!value) {
+			mask = ETDM_IN4_SDATA1_15_SEL_MASK_SFT |
+				ETDM_IN4_SDATA0_SEL_MASK_SFT;
+			val = (etdm_lpbk_idx_0[value] << ETDM_IN4_SDATA1_15_SEL_SFT) |
+				(etdm_lpbk_idx_0[value] << ETDM_IN4_SDATA0_SEL_SFT);
+		} else if (value_ipmode) {
+			mask = ETDM_IN4_SDATA1_15_SEL_MASK_SFT;
+			val = etdm_lpbk_idx_0[value] << ETDM_IN4_SDATA1_15_SEL_SFT;
+		} else {
+			mask = ETDM_IN4_SDATA0_SEL_MASK_SFT;
+			val = etdm_lpbk_idx_0[value] << ETDM_IN4_SDATA0_SEL_SFT;
+		}
+	} else {
+		reg = ETDM_4_7_COWORK_CON3;
+		mask = ETDM_IN6_SDATA0_SEL_MASK_SFT;
+		val = etdm_lpbk_idx_2[value] << ETDM_IN6_SDATA0_SEL_SFT;
+	}
+
+	if (reg)
+		regmap_update_bits(afe->regmap, reg, mask, val);
+
+	return 0;
+}
+
+static const char *const etdm_lpbk_map[] = {
+	"Off", "On",
+};
+
+static SOC_ENUM_SINGLE_EXT_DECL(etdm_lpbk_map_enum,
+				etdm_lpbk_map);
+/* lpbk */
+
+/* multi-ip mode */
+static const int etdm_ip_mode_idx[] = {
+	0x0, 0x1,
+};
+
+static int etdm_ip_mode_get(struct snd_kcontrol *kcontrol,
+			    struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+		snd_soc_kcontrol_component(kcontrol);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_afe_i2s_priv *i2sin4_priv = afe_priv->dai_priv[MT8196_DAI_I2S_IN4];
+
+	ucontrol->value.enumerated.item[0] = i2sin4_priv->ip_mode;
+
+	return 0;
+}
+
+static int etdm_ip_mode_put(struct snd_kcontrol *kcontrol,
+			    struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_afe_i2s_priv *i2sin4_priv = afe_priv->dai_priv[MT8196_DAI_I2S_IN4];
+	unsigned int value = ucontrol->value.integer.value[0];
+
+	if (value >= ARRAY_SIZE(etdm_ip_mode_idx))
+		return -EINVAL;
+
+	/* 0: One IP multi-channel 1: Multi-IP 2-channel */
+	i2sin4_priv->ip_mode = etdm_ip_mode_idx[value];
+
+	return 0;
+}
+
+static const char *const etdm_ip_mode_map[] = {
+	"Off", "On",
+};
+
+static SOC_ENUM_SINGLE_EXT_DECL(etdm_ip_mode_map_enum,
+				etdm_ip_mode_map);
+/* multi-ip mode */
+
+/* ch num */
+static const int etdm_ch_num_idx[] = {
+	0x2, 0x4, 0x6, 0x8,
+};
+
+static int etdm_ch_num_get(struct snd_kcontrol *kcontrol,
+			   struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+		snd_soc_kcontrol_component(kcontrol);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_afe_i2s_priv *i2sin4_priv = afe_priv->dai_priv[MT8196_DAI_I2S_IN4];
+	struct mtk_afe_i2s_priv *i2sout4_priv = afe_priv->dai_priv[MT8196_DAI_I2S_OUT4];
+	unsigned int value = 0;
+
+	if (!strcmp(kcontrol->id.name, "I2SIN4_CH_NUM"))
+		value = i2sin4_priv->ch_num;
+	else if (!strcmp(kcontrol->id.name, "I2SOUT4_CH_NUM"))
+		value = i2sout4_priv->ch_num;
+
+	if (value == 0x2)
+		ucontrol->value.enumerated.item[0] = 0;
+	else if (value == 0x4)
+		ucontrol->value.enumerated.item[0] = 1;
+	else if (value == 0x6)
+		ucontrol->value.enumerated.item[0] = 2;
+	else
+		ucontrol->value.enumerated.item[0] = 3;
+
+	return 0;
+}
+
+static int etdm_ch_num_put(struct snd_kcontrol *kcontrol,
+			   struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_afe_i2s_priv *i2sin4_priv = afe_priv->dai_priv[MT8196_DAI_I2S_IN4];
+	struct mtk_afe_i2s_priv *i2sout4_priv = afe_priv->dai_priv[MT8196_DAI_I2S_OUT4];
+	unsigned int value = ucontrol->value.integer.value[0];
+
+	if (value >= ARRAY_SIZE(etdm_ch_num_idx))
+		return -EINVAL;
+
+	if (!strcmp(kcontrol->id.name, "I2SIN4_CH_NUM"))
+		i2sin4_priv->ch_num = etdm_ch_num_idx[value];
+	else if (!strcmp(kcontrol->id.name, "I2SOUT4_CH_NUM"))
+		i2sout4_priv->ch_num = etdm_ch_num_idx[value];
+
+	return 0;
+}
+
+static const char *const etdm_ch_num_map[] = {
+	"2CH", "4CH", "6CH", "8CH",
+};
+
+static SOC_ENUM_SINGLE_EXT_DECL(etdm_ch_num_map_enum,
+				etdm_ch_num_map);
+/* ch num */
+
+enum {
+	I2S_FMT_EIAJ = 0,
+	I2S_FMT_I2S = 1,
+};
+
+enum {
+	I2S_WLEN_16_BIT = 0,
+	I2S_WLEN_32_BIT = 1,
+};
+
+enum {
+	I2S_HD_NORMAL = 0,
+	I2S_HD_LOW_JITTER = 1,
+};
+
+enum {
+	I2S1_SEL_O28_O29 = 0,
+	I2S1_SEL_O03_O04 = 1,
+};
+
+enum {
+	I2S_IN_PAD_CONNSYS = 0,
+	I2S_IN_PAD_IO_MUX = 1,
+};
+
+static unsigned int get_i2s_wlen(snd_pcm_format_t format)
+{
+	return snd_pcm_format_physical_width(format) <= 16 ?
+	       I2S_WLEN_16_BIT : I2S_WLEN_32_BIT;
+}
+
+#define MTK_AFE_I2SIN0_KCONTROL_NAME "I2SIN0_HD_Mux"
+#define MTK_AFE_I2SIN1_KCONTROL_NAME "I2SIN1_HD_Mux"
+#define MTK_AFE_I2SIN2_KCONTROL_NAME "I2SIN2_HD_Mux"
+#define MTK_AFE_I2SIN4_KCONTROL_NAME "I2SIN4_HD_Mux"
+#define MTK_AFE_I2SIN6_KCONTROL_NAME "I2SIN6_HD_Mux"
+#define MTK_AFE_I2SOUT0_KCONTROL_NAME "I2SOUT0_HD_Mux"
+#define MTK_AFE_I2SOUT1_KCONTROL_NAME "I2SOUT1_HD_Mux"
+#define MTK_AFE_I2SOUT2_KCONTROL_NAME "I2SOUT2_HD_Mux"
+#define MTK_AFE_I2SOUT4_KCONTROL_NAME "I2SOUT4_HD_Mux"
+#define MTK_AFE_I2SOUT6_KCONTROL_NAME "I2SOUT6_HD_Mux"
+#define MTK_AFE_FMI2S_MASTER_KCONTROL_NAME "FMI2S_MASTER_HD_Mux"
+
+#define I2SIN0_HD_EN_W_NAME "I2SIN0_HD_EN"
+#define I2SIN1_HD_EN_W_NAME "I2SIN1_HD_EN"
+#define I2SIN2_HD_EN_W_NAME "I2SIN2_HD_EN"
+#define I2SIN3_HD_EN_W_NAME "I2SIN3_HD_EN"
+#define I2SIN4_HD_EN_W_NAME "I2SIN4_HD_EN"
+#define I2SIN6_HD_EN_W_NAME "I2SIN6_HD_EN"
+#define I2SOUT0_HD_EN_W_NAME "I2SOUT0_HD_EN"
+#define I2SOUT1_HD_EN_W_NAME "I2SOUT1_HD_EN"
+#define I2SOUT2_HD_EN_W_NAME "I2SOUT2_HD_EN"
+#define I2SOUT3_HD_EN_W_NAME "I2SOUT3_HD_EN"
+#define I2SOUT4_HD_EN_W_NAME "I2SOUT4_HD_EN"
+#define I2SOUT6_HD_EN_W_NAME "I2SOUT6_HD_EN"
+#define FMI2S_MASTER_HD_EN_W_NAME "FMI2S_MASTER_HD_EN"
+
+#define I2SIN0_MCLK_EN_W_NAME "I2SIN0_MCLK_EN"
+#define I2SIN1_MCLK_EN_W_NAME "I2SIN1_MCLK_EN"
+#define I2SIN2_MCLK_EN_W_NAME "I2SIN2_MCLK_EN"
+#define I2SIN3_MCLK_EN_W_NAME "I2SIN3_MCLK_EN"
+#define I2SIN4_MCLK_EN_W_NAME "I2SIN4_MCLK_EN"
+#define I2SIN6_MCLK_EN_W_NAME "I2SIN6_MCLK_EN"
+#define I2SOUT0_MCLK_EN_W_NAME "I2SOUT0_MCLK_EN"
+#define I2SOUT1_MCLK_EN_W_NAME "I2SOUT1_MCLK_EN"
+#define I2SOUT2_MCLK_EN_W_NAME "I2SOUT2_MCLK_EN"
+#define I2SOUT3_MCLK_EN_W_NAME "I2SOUT3_MCLK_EN"
+#define I2SOUT4_MCLK_EN_W_NAME "I2SOUT4_MCLK_EN"
+#define I2SOUT6_MCLK_EN_W_NAME "I2SOUT6_MCLK_EN"
+#define FMI2S_MASTER_MCLK_EN_W_NAME "FMI2S_MASTER_MCLK_EN"
+
+static int get_i2s_id_by_name(struct mtk_base_afe *afe,
+			      const char *name)
+{
+	if (strncmp(name, "I2SIN0", 6) == 0)
+		return MT8196_DAI_I2S_IN0;
+	else if (strncmp(name, "I2SIN1", 6) == 0)
+		return MT8196_DAI_I2S_IN1;
+	else if (strncmp(name, "I2SIN2", 6) == 0)
+		return MT8196_DAI_I2S_IN2;
+	else if (strncmp(name, "I2SIN3", 6) == 0)
+		return MT8196_DAI_I2S_IN3;
+	else if (strncmp(name, "I2SIN4", 6) == 0)
+		return MT8196_DAI_I2S_IN4;
+	else if (strncmp(name, "I2SIN6", 6) == 0)
+		return MT8196_DAI_I2S_IN6;
+	else if (strncmp(name, "I2SOUT0", 7) == 0)
+		return MT8196_DAI_I2S_OUT0;
+	else if (strncmp(name, "I2SOUT1", 7) == 0)
+		return MT8196_DAI_I2S_OUT1;
+	else if (strncmp(name, "I2SOUT2", 7) == 0)
+		return MT8196_DAI_I2S_OUT2;
+	else if (strncmp(name, "I2SOUT3", 7) == 0)
+		return MT8196_DAI_I2S_OUT3;
+	else if (strncmp(name, "I2SOUT4", 7) == 0)
+		return MT8196_DAI_I2S_OUT4;
+	else if (strncmp(name, "I2SOUT6", 7) == 0)
+		return MT8196_DAI_I2S_OUT6;
+	else if (strncmp(name, "FMI2S_MASTER", 12) == 0)
+		return MT8196_DAI_FM_I2S_MASTER;
+	else
+		return -EINVAL;
+}
+
+static struct mtk_afe_i2s_priv *get_i2s_priv_by_name(struct mtk_base_afe *afe,
+						     const char *name)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int dai_id = get_i2s_id_by_name(afe, name);
+
+	if (dai_id < 0)
+		return NULL;
+
+	return afe_priv->dai_priv[dai_id];
+}
+
+/*
+ * bit mask for i2s low power control
+ * such as bit0 for i2s0, bit1 for i2s1...
+ * if set 1, means i2s low power mode
+ * if set 0, means i2s low jitter mode
+ * 0 for all i2s bit in default
+ */
+static unsigned int i2s_low_power_mask;
+static int mtk_i2s_low_power_mask_get(struct snd_kcontrol *kcontrol,
+				      struct snd_ctl_elem_value *ucontrol)
+{
+	pr_debug("%s(), mask: %x\n", __func__, i2s_low_power_mask);
+	ucontrol->value.integer.value[0] = i2s_low_power_mask;
+	return 0;
+}
+
+static int mtk_i2s_low_power_mask_set(struct snd_kcontrol *kcontrol,
+				      struct snd_ctl_elem_value *ucontrol)
+{
+	i2s_low_power_mask = ucontrol->value.integer.value[0];
+	return 0;
+}
+
+static int mtk_is_i2s_low_power(int i2s_num)
+{
+	int i2s_bit_shift;
+
+	i2s_bit_shift = i2s_num - MT8196_DAI_I2S_IN0;
+	if (i2s_bit_shift < 0 || i2s_bit_shift > MT8196_DAI_I2S_MAX_NUM)
+		return 0;
+
+	return (i2s_low_power_mask >> i2s_bit_shift) & 0x1;
+}
+
+/* low jitter control */
+static const char *const mt8196_i2s_hd_str[] = {
+	"Normal", "Low_Jitter"
+};
+
+static const struct soc_enum mt8196_i2s_enum[] = {
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8196_i2s_hd_str),
+			    mt8196_i2s_hd_str),
+};
+
+static int mt8196_i2s_hd_get(struct snd_kcontrol *kcontrol,
+			     struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mtk_afe_i2s_priv *i2s_priv;
+
+	i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name);
+
+	if (!i2s_priv)
+		return -EINVAL;
+
+	ucontrol->value.integer.value[0] = i2s_priv->low_jitter_en;
+
+	return 0;
+}
+
+static int mt8196_i2s_hd_set(struct snd_kcontrol *kcontrol,
+			     struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mtk_afe_i2s_priv *i2s_priv;
+	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+	int hd_en;
+
+	if (ucontrol->value.enumerated.item[0] >= e->items)
+		return -EINVAL;
+
+	hd_en = ucontrol->value.integer.value[0];
+
+	dev_dbg(afe->dev, "kcontrol name %s, hd_en %d\n", kcontrol->id.name, hd_en);
+
+	i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name);
+
+	if (!i2s_priv)
+		return -EINVAL;
+
+	i2s_priv->low_jitter_en = hd_en;
+
+	return 0;
+}
+
+static const struct snd_kcontrol_new mtk_dai_i2s_controls[] = {
+	SOC_ENUM_EXT(MTK_AFE_I2SIN0_KCONTROL_NAME, mt8196_i2s_enum[0],
+		     mt8196_i2s_hd_get, mt8196_i2s_hd_set),
+	SOC_ENUM_EXT(MTK_AFE_I2SIN1_KCONTROL_NAME, mt8196_i2s_enum[0],
+		     mt8196_i2s_hd_get, mt8196_i2s_hd_set),
+	SOC_ENUM_EXT(MTK_AFE_I2SIN2_KCONTROL_NAME, mt8196_i2s_enum[0],
+		     mt8196_i2s_hd_get, mt8196_i2s_hd_set),
+	SOC_ENUM_EXT(MTK_AFE_I2SIN4_KCONTROL_NAME, mt8196_i2s_enum[0],
+		     mt8196_i2s_hd_get, mt8196_i2s_hd_set),
+	SOC_ENUM_EXT(MTK_AFE_I2SIN6_KCONTROL_NAME, mt8196_i2s_enum[0],
+		     mt8196_i2s_hd_get, mt8196_i2s_hd_set),
+	SOC_ENUM_EXT(MTK_AFE_I2SOUT0_KCONTROL_NAME, mt8196_i2s_enum[0],
+		     mt8196_i2s_hd_get, mt8196_i2s_hd_set),
+	SOC_ENUM_EXT(MTK_AFE_I2SOUT1_KCONTROL_NAME, mt8196_i2s_enum[0],
+		     mt8196_i2s_hd_get, mt8196_i2s_hd_set),
+	SOC_ENUM_EXT(MTK_AFE_I2SOUT2_KCONTROL_NAME, mt8196_i2s_enum[0],
+		     mt8196_i2s_hd_get, mt8196_i2s_hd_set),
+	SOC_ENUM_EXT(MTK_AFE_I2SOUT4_KCONTROL_NAME, mt8196_i2s_enum[0],
+		     mt8196_i2s_hd_get, mt8196_i2s_hd_set),
+	SOC_ENUM_EXT(MTK_AFE_I2SOUT6_KCONTROL_NAME, mt8196_i2s_enum[0],
+		     mt8196_i2s_hd_get, mt8196_i2s_hd_set),
+	SOC_ENUM_EXT(MTK_AFE_FMI2S_MASTER_KCONTROL_NAME, mt8196_i2s_enum[0],
+		     mt8196_i2s_hd_get, mt8196_i2s_hd_set),
+	SOC_SINGLE_EXT("i2s_low_power_mask", SND_SOC_NOPM, 0, 0xffff, 0,
+		       mtk_i2s_low_power_mask_get,
+		       mtk_i2s_low_power_mask_set),
+
+	SOC_ENUM_EXT("I2SIN0_LPBK", etdm_lpbk_map_enum,
+		     etdm_lpbk_get, etdm_lpbk_put),
+	SOC_ENUM_EXT("I2SIN1_LPBK", etdm_lpbk_map_enum,
+		     etdm_lpbk_get, etdm_lpbk_put),
+	SOC_ENUM_EXT("I2SIN2_LPBK", etdm_lpbk_map_enum,
+		     etdm_lpbk_get, etdm_lpbk_put),
+	SOC_ENUM_EXT("I2SIN3_LPBK", etdm_lpbk_map_enum,
+		     etdm_lpbk_get, etdm_lpbk_put),
+	SOC_ENUM_EXT("I2SIN4_LPBK", etdm_lpbk_map_enum,
+		     etdm_lpbk_get, etdm_lpbk_put),
+	SOC_ENUM_EXT("I2SIN6_LPBK", etdm_lpbk_map_enum,
+		     etdm_lpbk_get, etdm_lpbk_put),
+	SOC_ENUM_EXT("I2SIN4_IP_MODE", etdm_ip_mode_map_enum,
+		     etdm_ip_mode_get, etdm_ip_mode_put),
+	SOC_ENUM_EXT("I2SIN4_CH_NUM", etdm_ch_num_map_enum,
+		     etdm_ch_num_get, etdm_ch_num_put),
+	SOC_ENUM_EXT("I2SOUT4_CH_NUM", etdm_ch_num_map_enum,
+		     etdm_ch_num_get, etdm_ch_num_put),
+};
+
+/* dai component */
+/* i2s virtual mux to output widget */
+static const char *const i2s_mux_map[] = {
+	"Normal", "Dummy_Widget",
+};
+
+static int i2s_mux_map_value[] = {
+	0, 1,
+};
+
+static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s_mux_map_enum,
+		SND_SOC_NOPM,
+		0,
+		1,
+		i2s_mux_map,
+		i2s_mux_map_value);
+
+static const struct snd_kcontrol_new i2s_in0_mux_control =
+	SOC_DAPM_ENUM("I2S IN0 Select", i2s_mux_map_enum);
+static const struct snd_kcontrol_new i2s_in1_mux_control =
+	SOC_DAPM_ENUM("I2S IN1 Select", i2s_mux_map_enum);
+static const struct snd_kcontrol_new i2s_in2_mux_control =
+	SOC_DAPM_ENUM("I2S IN2 Select", i2s_mux_map_enum);
+static const struct snd_kcontrol_new i2s_in3_mux_control =
+	SOC_DAPM_ENUM("I2S IN3 Select", i2s_mux_map_enum);
+static const struct snd_kcontrol_new i2s_in4_mux_control =
+	SOC_DAPM_ENUM("I2S IN4 Select", i2s_mux_map_enum);
+static const struct snd_kcontrol_new i2s_in6_mux_control =
+	SOC_DAPM_ENUM("I2S IN6 Select", i2s_mux_map_enum);
+static const struct snd_kcontrol_new i2s_out0_mux_control =
+	SOC_DAPM_ENUM("I2S OUT0 Select", i2s_mux_map_enum);
+static const struct snd_kcontrol_new i2s_out1_mux_control =
+	SOC_DAPM_ENUM("I2S OUT1 Select", i2s_mux_map_enum);
+static const struct snd_kcontrol_new i2s_out2_mux_control =
+	SOC_DAPM_ENUM("I2S OUT2 Select", i2s_mux_map_enum);
+static const struct snd_kcontrol_new i2s_out3_mux_control =
+	SOC_DAPM_ENUM("I2S OUT3 Select", i2s_mux_map_enum);
+static const struct snd_kcontrol_new i2s_out4_mux_control =
+	SOC_DAPM_ENUM("I2S OUT4 Select", i2s_mux_map_enum);
+static const struct snd_kcontrol_new i2s_out6_mux_control =
+	SOC_DAPM_ENUM("I2S OUT6 Select", i2s_mux_map_enum);
+
+/* interconnection */
+static const struct snd_kcontrol_new mtk_i2sout0_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN108_1, I_DL0_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN108_1, I_DL1_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN108_1, I_DL2_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN108_1, I_DL3_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN108_1, I_DL4_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN108_1, I_DL5_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN108_1, I_DL6_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN108_1, I_DL7_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN108_1, I_DL8_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN108_1, I_DL_24CH_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH1", AFE_CONN108_2, I_DL23_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH1", AFE_CONN108_2, I_DL24_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN108_0,
+				    I_GAIN0_OUT_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN108_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN108_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN108_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN108_4,
+				    I_PCM_0_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN108_4,
+				    I_PCM_1_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1", AFE_CONN108_6,
+				    I_SRC_2_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout0_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN109_1, I_DL0_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN109_1, I_DL1_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN109_1, I_DL2_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN109_1, I_DL3_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN109_1, I_DL4_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN109_1, I_DL5_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN109_1, I_DL6_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN109_1, I_DL7_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN109_1, I_DL8_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN109_1, I_DL_24CH_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH2", AFE_CONN109_2, I_DL23_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH2", AFE_CONN109_2, I_DL24_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN109_0,
+				    I_GAIN0_OUT_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN109_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN109_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN109_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN109_4,
+				    I_PCM_0_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN109_4,
+				    I_PCM_0_CAP_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN109_4,
+				    I_PCM_1_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN109_4,
+				    I_PCM_1_CAP_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2", AFE_CONN109_6,
+				    I_SRC_2_OUT_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout1_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN110_1, I_DL0_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN110_1, I_DL1_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN110_1, I_DL2_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN110_1, I_DL3_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN110_1, I_DL4_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN110_1, I_DL5_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN110_1, I_DL6_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN110_1, I_DL7_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN110_1, I_DL8_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN110_1, I_DL_24CH_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN110_0,
+				    I_GAIN0_OUT_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN110_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN110_4,
+				    I_PCM_0_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN110_4,
+				    I_PCM_1_CAP_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout1_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN111_1, I_DL0_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN111_1, I_DL1_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN111_1, I_DL2_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN111_1, I_DL3_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN111_1, I_DL4_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN111_1, I_DL5_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN111_1, I_DL6_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN111_1, I_DL7_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN111_1, I_DL8_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN111_1, I_DL_24CH_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN111_0,
+				    I_GAIN0_OUT_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN111_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN111_4,
+				    I_PCM_0_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN111_4,
+				    I_PCM_0_CAP_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN111_4,
+				    I_PCM_1_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN111_4,
+				    I_PCM_1_CAP_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout2_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN112_1, I_DL0_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN112_1, I_DL1_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN112_1, I_DL2_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN112_1, I_DL3_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN112_1, I_DL4_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN112_1, I_DL5_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN112_1, I_DL6_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN112_1, I_DL7_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN112_1, I_DL8_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN112_1, I_DL_24CH_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN112_0,
+				    I_GAIN0_OUT_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN112_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN112_4,
+				    I_PCM_0_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN112_4,
+				    I_PCM_1_CAP_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout2_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN113_1, I_DL0_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN113_1, I_DL1_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN113_1, I_DL2_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN113_1, I_DL3_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN113_1, I_DL4_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN113_1, I_DL5_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN113_1, I_DL6_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN113_1, I_DL7_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN113_1, I_DL8_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN113_1, I_DL_24CH_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN113_0,
+				    I_GAIN0_OUT_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN113_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN113_4,
+				    I_PCM_0_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN113_4,
+				    I_PCM_0_CAP_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN113_4,
+				    I_PCM_1_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN113_4,
+				    I_PCM_1_CAP_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout3_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN114_1, I_DL0_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN114_1, I_DL1_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN114_1, I_DL2_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN114_1, I_DL3_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN114_1, I_DL4_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN114_1, I_DL5_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN114_1, I_DL6_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN114_1, I_DL7_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN114_1, I_DL8_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN114_1, I_DL_24CH_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN114_0,
+				    I_GAIN0_OUT_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN114_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN114_4,
+				    I_PCM_0_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN114_4,
+				    I_PCM_1_CAP_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout3_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN115_1, I_DL0_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN115_1, I_DL1_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN115_1, I_DL2_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN115_1, I_DL3_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN115_1, I_DL4_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN115_1, I_DL5_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN115_1, I_DL6_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN115_1, I_DL7_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN115_1, I_DL8_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN115_1, I_DL_24CH_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN115_0,
+				    I_GAIN0_OUT_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN115_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN115_4,
+				    I_PCM_0_CAP_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN115_4,
+				    I_PCM_1_CAP_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN116_1, I_DL0_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN116_1, I_DL1_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN116_1, I_DL2_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN116_1, I_DL3_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN116_1, I_DL4_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN116_1, I_DL5_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN116_1, I_DL6_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN116_1, I_DL7_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN116_1, I_DL8_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN116_1, I_DL_24CH_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH1", AFE_CONN116_2, I_DL24_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN116_0,
+				    I_GAIN0_OUT_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN116_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN116_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN116_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN116_4,
+				    I_PCM_0_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN116_4,
+				    I_PCM_1_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1", AFE_CONN116_6,
+				    I_SRC_2_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN117_1, I_DL0_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN117_1, I_DL1_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN117_1, I_DL2_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN117_1, I_DL3_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN117_1, I_DL4_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN117_1, I_DL5_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN117_1, I_DL6_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN117_1, I_DL7_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN117_1, I_DL8_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN117_1, I_DL_24CH_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH2", AFE_CONN117_2, I_DL24_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN117_0,
+				    I_GAIN0_OUT_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN117_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN117_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN117_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN117_4,
+				    I_PCM_0_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN117_4,
+				    I_PCM_0_CAP_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN117_4,
+				    I_PCM_1_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN117_4,
+				    I_PCM_1_CAP_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2", AFE_CONN117_6,
+				    I_SRC_2_OUT_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch3_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH3", AFE_CONN118_1, I_DL_24CH_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN118_4,
+				    I_PCM_0_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN118_4,
+				    I_PCM_1_CAP_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch4_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH4", AFE_CONN119_1, I_DL_24CH_CH4, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN118_4,
+				    I_PCM_0_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN118_4,
+				    I_PCM_1_CAP_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch5_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH5", AFE_CONN120_1, I_DL_24CH_CH5, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch6_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH6", AFE_CONN121_1, I_DL_24CH_CH6, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch7_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH7", AFE_CONN122_1, I_DL_24CH_CH7, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch8_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH8", AFE_CONN123_1, I_DL_24CH_CH8, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout6_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN148_1, I_DL0_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN148_1, I_DL1_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN148_1, I_DL2_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN148_1, I_DL3_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN148_1, I_DL4_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN148_1, I_DL5_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN148_1, I_DL6_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN148_1, I_DL7_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN148_1, I_DL8_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH1", AFE_CONN148_2, I_DL23_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN148_1, I_DL_24CH_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN148_0,
+				    I_GAIN0_OUT_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN148_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN148_4,
+				    I_PCM_0_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN148_4,
+				    I_PCM_1_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH1", AFE_CONN148_6,
+				    I_SRC_1_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout6_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN149_1, I_DL0_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN149_1, I_DL1_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN149_1, I_DL2_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN149_1, I_DL3_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN149_1, I_DL4_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN149_1, I_DL5_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN149_1, I_DL6_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN149_1, I_DL7_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN149_1, I_DL8_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH2", AFE_CONN149_2, I_DL23_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN149_1, I_DL_24CH_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN149_0,
+				    I_GAIN0_OUT_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN149_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN149_4,
+				    I_PCM_0_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN149_4,
+				    I_PCM_0_CAP_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN149_4,
+				    I_PCM_1_CAP_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN149_4,
+				    I_PCM_1_CAP_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH2", AFE_CONN148_6,
+				    I_SRC_1_OUT_CH2, 1, 0),
+};
+
+enum {
+	SUPPLY_SEQ_APLL,
+	SUPPLY_SEQ_I2S_MCLK_EN,
+	SUPPLY_SEQ_I2S_HD_EN,
+	SUPPLY_SEQ_I2S_CG_EN,
+	SUPPLY_SEQ_I2S_EN,
+};
+
+static int mtk_i2s_hd_en_event(struct snd_soc_dapm_widget *w,
+			       struct snd_kcontrol *kcontrol,
+			       int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+
+	dev_dbg(cmpnt->dev, "name %s, event 0x%x\n", w->name, event);
+
+	return 0;
+}
+
+static int mtk_apll_event(struct snd_soc_dapm_widget *w,
+			  struct snd_kcontrol *kcontrol,
+			  int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+
+	dev_dbg(cmpnt->dev, "name %s, event 0x%x\n", w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		if (strcmp(w->name, APLL1_W_NAME) == 0)
+			mt8196_apll1_enable(afe);
+		else
+			mt8196_apll2_enable(afe);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		if (strcmp(w->name, APLL1_W_NAME) == 0)
+			mt8196_apll1_disable(afe);
+		else
+			mt8196_apll2_disable(afe);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int mtk_mclk_en_event(struct snd_soc_dapm_widget *w,
+			     struct snd_kcontrol *kcontrol,
+			     int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mtk_afe_i2s_priv *i2s_priv;
+
+	dev_dbg(cmpnt->dev, "name %s, event 0x%x\n", w->name, event);
+
+	i2s_priv = get_i2s_priv_by_name(afe, w->name);
+
+	if (!i2s_priv)
+		return -EINVAL;
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		mt8196_mck_enable(afe, i2s_priv->mclk_id, i2s_priv->mclk_rate);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		i2s_priv->mclk_rate = 0;
+		mt8196_mck_disable(afe, i2s_priv->mclk_id);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int mtk_dai_i2s_get_cg_id_by_dai_id(int dai_id)
+{
+	switch (dai_id) {
+	case MT8196_DAI_I2S_IN0:
+		return MT8196_CLK_AFE_ETDM_IN0;
+	case MT8196_DAI_I2S_IN1:
+		return MT8196_CLK_AFE_ETDM_IN1;
+	case MT8196_DAI_I2S_IN2:
+		return MT8196_CLK_AFE_ETDM_IN2;
+	case MT8196_DAI_I2S_IN3:
+		return MT8196_CLK_AFE_ETDM_IN3;
+	case MT8196_DAI_I2S_IN4:
+		return MT8196_CLK_AFE_ETDM_IN4;
+	case MT8196_DAI_I2S_IN6:
+		return MT8196_CLK_AFE_ETDM_IN6;
+	case MT8196_DAI_I2S_OUT0:
+		return MT8196_CLK_AFE_ETDM_OUT0;
+	case MT8196_DAI_I2S_OUT1:
+		return MT8196_CLK_AFE_ETDM_OUT1;
+	case MT8196_DAI_I2S_OUT2:
+		return MT8196_CLK_AFE_ETDM_OUT2;
+	case MT8196_DAI_I2S_OUT3:
+		return MT8196_CLK_AFE_ETDM_OUT3;
+	case MT8196_DAI_I2S_OUT4:
+		return MT8196_CLK_AFE_ETDM_OUT4;
+	case MT8196_DAI_I2S_OUT6:
+		return MT8196_CLK_AFE_ETDM_OUT6;
+	case MT8196_DAI_FM_I2S_MASTER:
+		return MT8196_CLK_AFE_FM_I2S;
+	default:
+		return -EINVAL;
+	}
+}
+
+static int mtk_i2s_cg_event(struct snd_soc_dapm_widget *w,
+			    struct snd_kcontrol *kcontrol,
+			    int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int cg_id;
+	int dai_id;
+
+	dev_dbg(cmpnt->dev, "name %s, event 0x%x\n", w->name, event);
+	dai_id = get_i2s_id_by_name(afe, w->name);
+	if (dai_id < 0) {
+		dev_err(afe->dev, "etdm_id < 0\n");
+		return 0;
+	}
+
+	cg_id = mtk_dai_i2s_get_cg_id_by_dai_id(dai_id);
+	if (cg_id < 0) {
+		dev_err(cmpnt->dev, "%s() cg_id < 0\n", __func__);
+		return 0;
+	}
+	dev_dbg(cmpnt->dev, "cg_id: %d\n", cg_id);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		mt8196_afe_enable_clk(afe, afe_priv->clk[cg_id]);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		mt8196_afe_disable_clk(afe, afe_priv->clk[cg_id]);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static const struct snd_soc_dapm_widget mtk_dai_i2s_widgets[] = {
+	SND_SOC_DAPM_MIXER("I2SOUT0_CH1", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout0_ch1_mix,
+			   ARRAY_SIZE(mtk_i2sout0_ch1_mix)),
+	SND_SOC_DAPM_MIXER("I2SOUT0_CH2", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout0_ch2_mix,
+			   ARRAY_SIZE(mtk_i2sout0_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("I2SOUT1_CH1", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout1_ch1_mix,
+			   ARRAY_SIZE(mtk_i2sout1_ch1_mix)),
+	SND_SOC_DAPM_MIXER("I2SOUT1_CH2", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout1_ch2_mix,
+			   ARRAY_SIZE(mtk_i2sout1_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("I2SOUT2_CH1", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout2_ch1_mix,
+			   ARRAY_SIZE(mtk_i2sout2_ch1_mix)),
+	SND_SOC_DAPM_MIXER("I2SOUT2_CH2", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout2_ch2_mix,
+			   ARRAY_SIZE(mtk_i2sout2_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("I2SOUT3_CH1", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout3_ch1_mix,
+			   ARRAY_SIZE(mtk_i2sout3_ch1_mix)),
+	SND_SOC_DAPM_MIXER("I2SOUT3_CH2", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout3_ch2_mix,
+			   ARRAY_SIZE(mtk_i2sout3_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("I2SOUT4_CH1", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout4_ch1_mix,
+			   ARRAY_SIZE(mtk_i2sout4_ch1_mix)),
+	SND_SOC_DAPM_MIXER("I2SOUT4_CH2", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout4_ch2_mix,
+			   ARRAY_SIZE(mtk_i2sout4_ch2_mix)),
+	SND_SOC_DAPM_MIXER("I2SOUT4_CH3", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout4_ch3_mix,
+			   ARRAY_SIZE(mtk_i2sout4_ch3_mix)),
+	SND_SOC_DAPM_MIXER("I2SOUT4_CH4", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout4_ch4_mix,
+			   ARRAY_SIZE(mtk_i2sout4_ch4_mix)),
+	SND_SOC_DAPM_MIXER("I2SOUT4_CH5", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout4_ch5_mix,
+			   ARRAY_SIZE(mtk_i2sout4_ch5_mix)),
+	SND_SOC_DAPM_MIXER("I2SOUT4_CH6", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout4_ch6_mix,
+			   ARRAY_SIZE(mtk_i2sout4_ch6_mix)),
+	SND_SOC_DAPM_MIXER("I2SOUT4_CH7", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout4_ch7_mix,
+			   ARRAY_SIZE(mtk_i2sout4_ch7_mix)),
+	SND_SOC_DAPM_MIXER("I2SOUT4_CH8", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout4_ch8_mix,
+			   ARRAY_SIZE(mtk_i2sout4_ch8_mix)),
+
+	SND_SOC_DAPM_MIXER("I2SOUT6_CH1", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout6_ch1_mix,
+			   ARRAY_SIZE(mtk_i2sout6_ch1_mix)),
+	SND_SOC_DAPM_MIXER("I2SOUT6_CH2", SND_SOC_NOPM, 0, 0,
+			   mtk_i2sout6_ch2_mix,
+			   ARRAY_SIZE(mtk_i2sout6_ch2_mix)),
+
+	/* i2s en*/
+	SND_SOC_DAPM_SUPPLY_S("I2SIN0_EN", SUPPLY_SEQ_I2S_EN,
+			      ETDM_IN0_CON0, REG_ETDM_IN_EN_SFT, 0,
+			      NULL, 0),
+	SND_SOC_DAPM_SUPPLY_S("I2SIN1_EN", SUPPLY_SEQ_I2S_EN,
+			      ETDM_IN1_CON0, REG_ETDM_IN_EN_SFT, 0,
+			      NULL, 0),
+	SND_SOC_DAPM_SUPPLY_S("I2SIN2_EN", SUPPLY_SEQ_I2S_EN,
+			      ETDM_IN2_CON0, REG_ETDM_IN_EN_SFT, 0,
+			      NULL, 0),
+	SND_SOC_DAPM_SUPPLY_S("I2SIN3_EN", SUPPLY_SEQ_I2S_EN,
+			      ETDM_IN3_CON0, REG_ETDM_IN_EN_SFT, 0,
+			      NULL, 0),
+	SND_SOC_DAPM_SUPPLY_S("I2SIN4_EN", SUPPLY_SEQ_I2S_EN,
+			      ETDM_IN4_CON0, REG_ETDM_IN_EN_SFT, 0,
+			      NULL, 0),
+	SND_SOC_DAPM_SUPPLY_S("I2SIN6_EN", SUPPLY_SEQ_I2S_EN,
+			      ETDM_IN6_CON0, REG_ETDM_IN_EN_SFT, 0,
+			      NULL, 0),
+	SND_SOC_DAPM_SUPPLY_S("I2SOUT0_EN", SUPPLY_SEQ_I2S_EN,
+			      ETDM_OUT0_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0,
+			      NULL, 0),
+	SND_SOC_DAPM_SUPPLY_S("I2SOUT1_EN", SUPPLY_SEQ_I2S_EN,
+			      ETDM_OUT1_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0,
+			      NULL, 0),
+	SND_SOC_DAPM_SUPPLY_S("I2SOUT2_EN", SUPPLY_SEQ_I2S_EN,
+			      ETDM_OUT2_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0,
+			      NULL, 0),
+	SND_SOC_DAPM_SUPPLY_S("I2SOUT3_EN", SUPPLY_SEQ_I2S_EN,
+			      ETDM_OUT3_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0,
+			      NULL, 0),
+	SND_SOC_DAPM_SUPPLY_S("I2SOUT4_EN", SUPPLY_SEQ_I2S_EN,
+			      ETDM_OUT4_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0,
+			      NULL, 0),
+	SND_SOC_DAPM_SUPPLY_S("I2SOUT6_EN", SUPPLY_SEQ_I2S_EN,
+			      ETDM_OUT6_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0,
+			      NULL, 0),
+	SND_SOC_DAPM_SUPPLY_S("FMI2S_MASTER_EN", SUPPLY_SEQ_I2S_EN,
+			      AFE_CONNSYS_I2S_CON, I2S_EN_SFT, 0,
+			      NULL, 0),
+
+	/* i2s hd en */
+	SND_SOC_DAPM_SUPPLY_S(I2SIN0_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_hd_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SIN1_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_hd_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SIN2_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_hd_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SIN3_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_hd_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SIN4_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_hd_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SIN6_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_hd_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SOUT0_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_hd_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SOUT1_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_hd_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SOUT2_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_hd_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SOUT3_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_hd_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SOUT4_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_hd_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SOUT6_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_hd_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(FMI2S_MASTER_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
+			      AFE_CONNSYS_I2S_CON, I2S_HDEN_SFT, 0,
+			      mtk_i2s_hd_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	/* i2s mclk en */
+	SND_SOC_DAPM_SUPPLY_S(I2SIN0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_mclk_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SIN1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_mclk_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SIN2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_mclk_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SIN3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_mclk_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SIN4_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_mclk_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SIN6_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_mclk_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SOUT0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_mclk_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SOUT1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_mclk_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SOUT2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_mclk_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SOUT3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_mclk_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SOUT4_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_mclk_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(I2SOUT6_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_mclk_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(FMI2S_MASTER_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_mclk_en_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	/* cg */
+	SND_SOC_DAPM_SUPPLY_S("I2SOUT0_CG", SUPPLY_SEQ_I2S_CG_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_cg_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("I2SOUT1_CG", SUPPLY_SEQ_I2S_CG_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_cg_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("I2SOUT2_CG", SUPPLY_SEQ_I2S_CG_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_cg_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("I2SOUT3_CG", SUPPLY_SEQ_I2S_CG_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_cg_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("I2SOUT4_CG", SUPPLY_SEQ_I2S_CG_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_cg_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("I2SOUT6_CG", SUPPLY_SEQ_I2S_CG_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_cg_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("I2SIN0_CG", SUPPLY_SEQ_I2S_CG_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_cg_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("I2SIN1_CG", SUPPLY_SEQ_I2S_CG_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_cg_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("I2SIN2_CG", SUPPLY_SEQ_I2S_CG_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_cg_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("I2SIN3_CG", SUPPLY_SEQ_I2S_CG_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_cg_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("I2SIN4_CG", SUPPLY_SEQ_I2S_CG_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_cg_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("I2SIN6_CG", SUPPLY_SEQ_I2S_CG_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_cg_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("FMI2S_MASTER_CG", SUPPLY_SEQ_I2S_CG_EN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_i2s_cg_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	/* apll */
+	SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_apll_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_apll_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	/* allow i2s on without codec on */
+	SND_SOC_DAPM_OUTPUT("I2S_DUMMY_OUT"),
+	SND_SOC_DAPM_MUX("I2S_OUT0_Mux",
+			 SND_SOC_NOPM, 0, 0, &i2s_out0_mux_control),
+	SND_SOC_DAPM_MUX("I2S_OUT1_Mux",
+			 SND_SOC_NOPM, 0, 0, &i2s_out1_mux_control),
+	SND_SOC_DAPM_MUX("I2S_OUT2_Mux",
+			 SND_SOC_NOPM, 0, 0, &i2s_out2_mux_control),
+	SND_SOC_DAPM_MUX("I2S_OUT3_Mux",
+			 SND_SOC_NOPM, 0, 0, &i2s_out3_mux_control),
+	SND_SOC_DAPM_MUX("I2S_OUT4_Mux",
+			 SND_SOC_NOPM, 0, 0, &i2s_out4_mux_control),
+	SND_SOC_DAPM_MUX("I2S_OUT6_Mux",
+			 SND_SOC_NOPM, 0, 0, &i2s_out6_mux_control),
+
+	SND_SOC_DAPM_INPUT("I2S_DUMMY_IN"),
+	SND_SOC_DAPM_MUX("I2S_IN0_Mux",
+			 SND_SOC_NOPM, 0, 0, &i2s_in0_mux_control),
+	SND_SOC_DAPM_MUX("I2S_IN1_Mux",
+			 SND_SOC_NOPM, 0, 0, &i2s_in1_mux_control),
+	SND_SOC_DAPM_MUX("I2S_IN2_Mux",
+			 SND_SOC_NOPM, 0, 0, &i2s_in2_mux_control),
+	SND_SOC_DAPM_MUX("I2S_IN3_Mux",
+			 SND_SOC_NOPM, 0, 0, &i2s_in3_mux_control),
+	SND_SOC_DAPM_MUX("I2S_IN4_Mux",
+			 SND_SOC_NOPM, 0, 0, &i2s_in4_mux_control),
+	SND_SOC_DAPM_MUX("I2S_IN6_Mux",
+			 SND_SOC_NOPM, 0, 0, &i2s_in6_mux_control),
+
+	SND_SOC_DAPM_MIXER("SOF_DMA_DL_24CH", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_MIXER("SOF_DMA_DL1", SND_SOC_NOPM, 0, 0, NULL, 0),
+};
+
+static int mtk_afe_i2s_share_connect(struct snd_soc_dapm_widget *source,
+				     struct snd_soc_dapm_widget *sink)
+{
+	struct snd_soc_dapm_widget *w = sink;
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mtk_afe_i2s_priv *i2s_priv;
+	int ret = 0;
+
+	i2s_priv = get_i2s_priv_by_name(afe, sink->name);
+
+	if (!i2s_priv)
+		return 0;
+
+	if (i2s_priv->share_i2s_id < 0)
+		return 0;
+
+	ret = (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name)) ? 1 : 0;
+
+	return ret;
+}
+
+static int mtk_afe_i2s_hd_connect(struct snd_soc_dapm_widget *source,
+				  struct snd_soc_dapm_widget *sink)
+{
+	struct snd_soc_dapm_widget *w = sink;
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mtk_afe_i2s_priv *i2s_priv;
+	int i2s_num;
+
+	i2s_priv = get_i2s_priv_by_name(afe, sink->name);
+
+	if (!i2s_priv)
+		return 0;
+
+	i2s_num = get_i2s_id_by_name(afe, source->name);
+	if (get_i2s_id_by_name(afe, sink->name) == i2s_num)
+		return !mtk_is_i2s_low_power(i2s_num) ||
+		       i2s_priv->low_jitter_en;
+
+	/* check if share i2s need hd en */
+	if (i2s_priv->share_i2s_id < 0)
+		return 0;
+
+	if (i2s_priv->share_i2s_id == i2s_num)
+		return !mtk_is_i2s_low_power(i2s_num) ||
+		       i2s_priv->low_jitter_en;
+
+	return 0;
+}
+
+static int mtk_afe_i2s_apll_connect(struct snd_soc_dapm_widget *source,
+				    struct snd_soc_dapm_widget *sink)
+{
+	struct snd_soc_dapm_widget *w = sink;
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mtk_afe_i2s_priv *i2s_priv;
+	int cur_apll;
+	int i2s_need_apll;
+
+	i2s_priv = get_i2s_priv_by_name(afe, w->name);
+
+	if (!i2s_priv)
+		return 0;
+
+	/* which apll */
+	cur_apll = mt8196_get_apll_by_name(afe, source->name);
+
+	/* choose APLL from i2s rate */
+	i2s_need_apll = mt8196_get_apll_by_rate(afe, i2s_priv->rate);
+
+	return (i2s_need_apll == cur_apll) ? 1 : 0;
+}
+
+static int mtk_afe_i2s_mclk_connect(struct snd_soc_dapm_widget *source,
+				    struct snd_soc_dapm_widget *sink)
+{
+	struct snd_soc_dapm_widget *w = sink;
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mtk_afe_i2s_priv *i2s_priv;
+
+	i2s_priv = get_i2s_priv_by_name(afe, sink->name);
+
+	if (!i2s_priv)
+		return 0;
+
+	if (get_i2s_id_by_name(afe, sink->name) ==
+	    get_i2s_id_by_name(afe, source->name))
+		return (i2s_priv->mclk_rate > 0) ? 1 : 0;
+
+	/* check if share i2s need mclk */
+	if (i2s_priv->share_i2s_id < 0)
+		return 0;
+
+	if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name))
+		return (i2s_priv->mclk_rate > 0) ? 1 : 0;
+
+	return 0;
+}
+
+static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source,
+				     struct snd_soc_dapm_widget *sink)
+{
+	struct snd_soc_dapm_widget *w = sink;
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mtk_afe_i2s_priv *i2s_priv;
+	int cur_apll;
+
+	i2s_priv = get_i2s_priv_by_name(afe, w->name);
+
+	if (!i2s_priv)
+		return 0;
+
+	/* which apll */
+	cur_apll = mt8196_get_apll_by_name(afe, source->name);
+
+	return (i2s_priv->mclk_apll == cur_apll) ? 1 : 0;
+}
+
+static const struct snd_soc_dapm_route mtk_dai_i2s_routes[] = {
+	/* i2sin0 */
+	{"I2SIN0", NULL, "I2SIN0_EN"},
+	{"I2SIN0", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN0", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN0", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN0", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN0", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN0", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN0", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN0", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN0", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN0", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN0", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN0", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect},
+
+	{"I2SIN0", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN0", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN0", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN0", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN0", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN0", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN0", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN0", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN0", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN0", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN0", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN0", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN0", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{I2SIN0_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+	{I2SIN0_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+
+	{"I2SIN0", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN0", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN0", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN0", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN0", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN0", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN0", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN0", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN0", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN0", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN0", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN0", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN0", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{I2SIN0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+	{I2SIN0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+	{"I2SIN0", NULL, "I2SIN0_CG"},
+
+	/* i2sin1 */
+	{"I2SIN1", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN1", NULL, "I2SIN1_EN"},
+	{"I2SIN1", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN1", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN1", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN1", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN1", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN1", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN1", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN1", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN1", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN1", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN1", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect},
+
+	{"I2SIN1", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN1", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN1", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN1", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN1", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN1", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN1", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN1", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN1", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN1", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN1", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN1", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN1", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{I2SIN1_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+	{I2SIN1_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+
+	{"I2SIN1", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN1", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN1", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN1", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN1", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN1", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN1", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN1", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN1", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN1", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN1", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN1", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN1", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{I2SIN1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+	{I2SIN1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+	{"I2SIN1", NULL, "I2SIN1_CG"},
+
+	/* i2sin2 */
+	{"I2SIN2", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN2", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN2", NULL, "I2SIN2_EN"},
+	{"I2SIN2", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN2", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN2", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN2", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN2", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN2", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN2", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN2", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN2", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN2", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect},
+
+	{"I2SIN2", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN2", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN2", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN2", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN2", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN2", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN2", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN2", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN2", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN2", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN2", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN2", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN2", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{I2SIN2_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+	{I2SIN2_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+
+	{"I2SIN2", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN2", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN2", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN2", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN2", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN2", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN2", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN2", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN2", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN2", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN2", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN2", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN2", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{I2SIN2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+	{I2SIN2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+	{"I2SIN2", NULL, "I2SIN2_CG"},
+
+	/* i2sin3 */
+	{"I2SIN3", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN3", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN3", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN3", NULL, "I2SIN3_EN"},
+	{"I2SIN3", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN3", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN3", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN3", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN3", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN3", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN3", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN3", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN3", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect},
+
+	{"I2SIN3", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN3", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN3", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN3", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN3", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN3", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN3", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN3", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN3", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN3", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN3", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN3", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN3", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{I2SIN3_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+	{I2SIN3_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+
+	{"I2SIN3", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN3", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN3", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN3", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN3", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN3", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN3", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN3", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN3", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN3", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN3", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN3", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN3", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{I2SIN3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+	{I2SIN3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+	{"I2SIN3", NULL, "I2SIN3_CG"},
+
+	/* i2sin4 */
+	{"I2SIN4", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN4", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN4", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN4", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN4", NULL, "I2SIN4_EN"},
+	{"I2SIN4", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN4", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN4", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN4", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN4", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN4", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN4", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN4", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect},
+
+	{"I2SIN4", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN4", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN4", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN4", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN4", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN4", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN4", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN4", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN4", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN4", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN4", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN4", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN4", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{I2SIN4_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+	{I2SIN4_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+
+	{"I2SIN4", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN4", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN4", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN4", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN4", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN4", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN4", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN4", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN4", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN4", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN4", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN4", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN4", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{I2SIN4_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+	{I2SIN4_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+	{"I2SIN4", NULL, "I2SIN4_CG"},
+
+	/* i2sin6 */
+	{"I2SIN6", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN6", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN6", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN6", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN6", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN6", NULL, "I2SIN6_EN"},
+	{"I2SIN6", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN6", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN6", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN6", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN6", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN6", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect},
+	{"I2SIN6", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect},
+
+	{"I2SIN6", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN6", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN6", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN6", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN6", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN6", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN6", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN6", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN6", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN6", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN6", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN6", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SIN6", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{I2SIN6_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+	{I2SIN6_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+
+	{"I2SIN6", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN6", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN6", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN6", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN6", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN6", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN6", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN6", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN6", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN6", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN6", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN6", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SIN6", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{I2SIN6_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+	{I2SIN6_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+	{"I2SIN6", NULL, "I2SIN6_CG"},
+	{"I2SIN6", NULL, "I2SOUT6_CG"},
+
+	/* i2sout0 */
+	{"I2SOUT0_CH1", "DL0_CH1", "DL0"},
+	{"I2SOUT0_CH2", "DL0_CH2", "DL0"},
+	{"I2SOUT0_CH1", "DL1_CH1", "DL1"},
+	{"I2SOUT0_CH2", "DL1_CH2", "DL1"},
+	{"I2SOUT0_CH1", "DL2_CH1", "DL2"},
+	{"I2SOUT0_CH2", "DL2_CH2", "DL2"},
+	{"I2SOUT0_CH1", "DL3_CH1", "DL3"},
+	{"I2SOUT0_CH2", "DL3_CH2", "DL3"},
+	{"I2SOUT0_CH1", "DL4_CH1", "DL4"},
+	{"I2SOUT0_CH2", "DL4_CH2", "DL4"},
+	{"I2SOUT0_CH1", "DL5_CH1", "DL5"},
+	{"I2SOUT0_CH2", "DL5_CH2", "DL5"},
+	{"I2SOUT0_CH1", "DL6_CH1", "DL6"},
+	{"I2SOUT0_CH2", "DL6_CH2", "DL6"},
+	{"I2SOUT0_CH1", "DL7_CH1", "DL7"},
+	{"I2SOUT0_CH2", "DL7_CH2", "DL7"},
+	{"I2SOUT0_CH1", "DL8_CH1", "DL8"},
+	{"I2SOUT0_CH2", "DL8_CH2", "DL8"},
+	{"I2SOUT0_CH1", "DL23_CH1", "DL23"},
+	{"I2SOUT0_CH2", "DL23_CH2", "DL23"},
+	{"I2SOUT0_CH1", "DL_24CH_CH1", "DL_24CH"},
+	{"I2SOUT0_CH2", "DL_24CH_CH2", "DL_24CH"},
+
+	{"I2SOUT0_CH1", "DL24_CH1", "DL24"},
+	{"I2SOUT0_CH2", "DL24_CH2", "DL24"},
+
+	{"I2SOUT0", NULL, "I2SOUT0_CH1"},
+	{"I2SOUT0", NULL, "I2SOUT0_CH2"},
+
+	{"I2SOUT0", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT0", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT0", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT0", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT0", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT0", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT0", NULL, "I2SOUT0_EN"},
+	{"I2SOUT0", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT0", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT0", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT0", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT0", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT0", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect},
+
+	{"I2SOUT0", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT0", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT0", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT0", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT0", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT0", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT0", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT0", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT0", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT0", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT0", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT0", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT0", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{I2SOUT0_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+	{I2SOUT0_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+
+	{"I2SOUT0", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT0", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT0", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT0", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT0", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT0", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT0", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT0", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT0", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT0", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT0", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT0", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT0", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{I2SOUT0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+	{I2SOUT0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+	{"I2SOUT0", NULL, "I2SOUT0_CG"},
+
+	/* i2sout1 */
+	{"I2SOUT1_CH1", "DL0_CH1", "DL0"},
+	{"I2SOUT1_CH2", "DL0_CH2", "DL0"},
+	{"I2SOUT1_CH1", "DL1_CH1", "DL1"},
+	{"I2SOUT1_CH2", "DL1_CH2", "DL1"},
+	{"I2SOUT1_CH1", "DL2_CH1", "DL2"},
+	{"I2SOUT1_CH2", "DL2_CH2", "DL2"},
+	{"I2SOUT1_CH1", "DL3_CH1", "DL3"},
+	{"I2SOUT1_CH2", "DL3_CH2", "DL3"},
+	{"I2SOUT1_CH1", "DL4_CH1", "DL4"},
+	{"I2SOUT1_CH2", "DL4_CH2", "DL4"},
+	{"I2SOUT1_CH1", "DL5_CH1", "DL5"},
+	{"I2SOUT1_CH2", "DL5_CH2", "DL5"},
+	{"I2SOUT1_CH1", "DL6_CH1", "DL6"},
+	{"I2SOUT1_CH2", "DL6_CH2", "DL6"},
+	{"I2SOUT1_CH1", "DL7_CH1", "DL7"},
+	{"I2SOUT1_CH2", "DL7_CH2", "DL7"},
+	{"I2SOUT1_CH1", "DL8_CH1", "DL8"},
+	{"I2SOUT1_CH2", "DL8_CH2", "DL8"},
+	{"I2SOUT1_CH1", "DL_24CH_CH1", "DL_24CH"},
+	{"I2SOUT1_CH2", "DL_24CH_CH2", "DL_24CH"},
+
+	{"I2SOUT1", NULL, "I2SOUT1_CH1"},
+	{"I2SOUT1", NULL, "I2SOUT1_CH2"},
+
+	{"I2SOUT1", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT1", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT1", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT1", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT1", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT1", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT1", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT1", NULL, "I2SOUT1_EN"},
+	{"I2SOUT1", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT1", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT1", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT1", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT1", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect},
+
+	{"I2SOUT1", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT1", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT1", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT1", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT1", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT1", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT1", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT1", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT1", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT1", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT1", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT1", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT1", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{I2SOUT1_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+	{I2SOUT1_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+
+	{"I2SOUT1", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT1", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT1", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT1", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT1", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT1", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT1", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT1", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT1", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT1", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT1", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT1", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT1", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{I2SOUT1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+	{I2SOUT1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+	{"I2SOUT1", NULL, "I2SOUT1_CG"},
+
+	/* i2sout2 */
+	{"I2SOUT2_CH1", "DL0_CH1", "DL0"},
+	{"I2SOUT2_CH2", "DL0_CH2", "DL0"},
+	{"I2SOUT2_CH1", "DL1_CH1", "DL1"},
+	{"I2SOUT2_CH2", "DL1_CH2", "DL1"},
+	{"I2SOUT2_CH1", "DL2_CH1", "DL2"},
+	{"I2SOUT2_CH2", "DL2_CH2", "DL2"},
+	{"I2SOUT2_CH1", "DL3_CH1", "DL3"},
+	{"I2SOUT2_CH2", "DL3_CH2", "DL3"},
+	{"I2SOUT2_CH1", "DL4_CH1", "DL4"},
+	{"I2SOUT2_CH2", "DL4_CH2", "DL4"},
+	{"I2SOUT2_CH1", "DL5_CH1", "DL5"},
+	{"I2SOUT2_CH2", "DL5_CH2", "DL5"},
+	{"I2SOUT2_CH1", "DL6_CH1", "DL6"},
+	{"I2SOUT2_CH2", "DL6_CH2", "DL6"},
+	{"I2SOUT2_CH1", "DL7_CH1", "DL7"},
+	{"I2SOUT2_CH2", "DL7_CH2", "DL7"},
+	{"I2SOUT2_CH1", "DL8_CH1", "DL8"},
+	{"I2SOUT2_CH2", "DL8_CH2", "DL8"},
+	{"I2SOUT2_CH1", "DL_24CH_CH1", "DL_24CH"},
+	{"I2SOUT2_CH2", "DL_24CH_CH2", "DL_24CH"},
+
+	{"I2SOUT2", NULL, "I2SOUT2_CH1"},
+	{"I2SOUT2", NULL, "I2SOUT2_CH2"},
+
+	{"I2SOUT2", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT2", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT2", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT2", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT2", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT2", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT2", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT2", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT2", NULL, "I2SOUT2_EN"},
+	{"I2SOUT2", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT2", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT2", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT2", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect},
+
+	{"I2SOUT2", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT2", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT2", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT2", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT2", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT2", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT2", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT2", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT2", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT2", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT2", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT2", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT2", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{I2SOUT2_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+	{I2SOUT2_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+
+	{"I2SOUT2", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT2", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT2", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT2", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT2", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT2", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT2", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT2", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT2", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT2", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT2", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT2", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT2", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{I2SOUT2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+	{I2SOUT2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+	{"I2SOUT2", NULL, "I2SOUT2_CG"},
+
+	/* i2sout3 */
+	{"I2SOUT3_CH1", "DL0_CH1", "DL0"},
+	{"I2SOUT3_CH2", "DL0_CH2", "DL0"},
+	{"I2SOUT3_CH1", "DL1_CH1", "DL1"},
+	{"I2SOUT3_CH2", "DL1_CH2", "DL1"},
+	{"I2SOUT3_CH1", "DL2_CH1", "DL2"},
+	{"I2SOUT3_CH2", "DL2_CH2", "DL2"},
+	{"I2SOUT3_CH1", "DL3_CH1", "DL3"},
+	{"I2SOUT3_CH2", "DL3_CH2", "DL3"},
+	{"I2SOUT3_CH1", "DL4_CH1", "DL4"},
+	{"I2SOUT3_CH2", "DL4_CH2", "DL4"},
+	{"I2SOUT3_CH1", "DL5_CH1", "DL5"},
+	{"I2SOUT3_CH2", "DL5_CH2", "DL5"},
+	{"I2SOUT3_CH1", "DL6_CH1", "DL6"},
+	{"I2SOUT3_CH2", "DL6_CH2", "DL6"},
+	{"I2SOUT3_CH1", "DL7_CH1", "DL7"},
+	{"I2SOUT3_CH2", "DL7_CH2", "DL7"},
+	{"I2SOUT3_CH1", "DL8_CH1", "DL8"},
+	{"I2SOUT3_CH2", "DL8_CH2", "DL8"},
+	{"I2SOUT3_CH1", "DL_24CH_CH1", "DL_24CH"},
+	{"I2SOUT3_CH2", "DL_24CH_CH2", "DL_24CH"},
+
+	{"I2SOUT3", NULL, "I2SOUT3_CH1"},
+	{"I2SOUT3", NULL, "I2SOUT3_CH2"},
+
+	{"I2SOUT3", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT3", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT3", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT3", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT3", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT3", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT3", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT3", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT3", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT3", NULL, "I2SOUT3_EN"},
+	{"I2SOUT3", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT3", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT3", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT3", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT3", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT3", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT3", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT3", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT3", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT3", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT3", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT3", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT3", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT3", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT3", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT3", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{I2SOUT3_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+	{I2SOUT3_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+
+	{"I2SOUT3", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT3", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT3", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT3", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT3", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT3", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT3", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT3", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT3", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT3", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT3", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT3", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT3", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{I2SOUT3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+	{I2SOUT3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+	{"I2SOUT3", NULL, "I2SOUT3_CG"},
+
+	/* i2sout4 */
+	{"I2SOUT4_CH1", "DL0_CH1", "DL0"},
+	{"I2SOUT4_CH2", "DL0_CH2", "DL0"},
+	{"I2SOUT4_CH1", "DL1_CH1", "DL1"},
+	{"I2SOUT4_CH2", "DL1_CH2", "DL1"},
+	{"I2SOUT4_CH1", "DL2_CH1", "DL2"},
+	{"I2SOUT4_CH2", "DL2_CH2", "DL2"},
+	{"I2SOUT4_CH1", "DL3_CH1", "DL3"},
+	{"I2SOUT4_CH2", "DL3_CH2", "DL3"},
+	{"I2SOUT4_CH1", "DL4_CH1", "DL4"},
+	{"I2SOUT4_CH2", "DL4_CH2", "DL4"},
+	{"I2SOUT4_CH1", "DL5_CH1", "DL5"},
+	{"I2SOUT4_CH2", "DL5_CH2", "DL5"},
+	{"I2SOUT4_CH1", "DL6_CH1", "DL6"},
+	{"I2SOUT4_CH2", "DL6_CH2", "DL6"},
+	{"I2SOUT4_CH1", "DL7_CH1", "DL7"},
+	{"I2SOUT4_CH2", "DL7_CH2", "DL7"},
+	{"I2SOUT4_CH1", "DL8_CH1", "DL8"},
+	{"I2SOUT4_CH2", "DL8_CH2", "DL8"},
+	{"I2SOUT4_CH1", "DL_24CH_CH1", "DL_24CH"},
+	{"I2SOUT4_CH2", "DL_24CH_CH2", "DL_24CH"},
+	{"I2SOUT4_CH3", "DL_24CH_CH3", "DL_24CH"},
+	{"I2SOUT4_CH4", "DL_24CH_CH4", "DL_24CH"},
+	{"I2SOUT4_CH5", "DL_24CH_CH5", "DL_24CH"},
+	{"I2SOUT4_CH6", "DL_24CH_CH6", "DL_24CH"},
+	{"I2SOUT4_CH7", "DL_24CH_CH7", "DL_24CH"},
+	{"I2SOUT4_CH8", "DL_24CH_CH8", "DL_24CH"},
+	{"I2SOUT4_CH1", "DL24_CH1", "DL24"},
+	{"I2SOUT4_CH2", "DL24_CH2", "DL24"},
+
+	/* SOF Downlink */
+	{"I2SOUT4_CH1", "DL_24CH_CH1", "SOF_DMA_DL_24CH"},
+	{"I2SOUT4_CH2", "DL_24CH_CH2", "SOF_DMA_DL_24CH"},
+	{"I2SOUT4_CH3", "DL_24CH_CH3", "SOF_DMA_DL_24CH"},
+	{"I2SOUT4_CH4", "DL_24CH_CH4", "SOF_DMA_DL_24CH"},
+
+	{"I2SOUT4", NULL, "I2SOUT4_CH1"},
+	{"I2SOUT4", NULL, "I2SOUT4_CH2"},
+	{"I2SOUT4", NULL, "I2SOUT4_CH3"},
+	{"I2SOUT4", NULL, "I2SOUT4_CH4"},
+	{"I2SOUT4", NULL, "I2SOUT4_CH5"},
+	{"I2SOUT4", NULL, "I2SOUT4_CH6"},
+	{"I2SOUT4", NULL, "I2SOUT4_CH7"},
+	{"I2SOUT4", NULL, "I2SOUT4_CH8"},
+
+	{"I2SOUT4", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT4", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT4", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT4", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT4", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT4", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT4", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT4", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT4", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT4", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT4", NULL, "I2SOUT4_EN"},
+	{"I2SOUT4", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT4", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect},
+
+	{"I2SOUT4", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT4", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT4", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT4", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT4", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT4", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT4", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT4", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT4", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT4", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT4", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT4", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT4", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{I2SOUT4_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+	{I2SOUT4_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+
+	{"I2SOUT4", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT4", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT4", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT4", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT4", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT4", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT4", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT4", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT4", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT4", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT4", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT4", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT4", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{I2SOUT4_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+	{I2SOUT4_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+	/* CG */
+	{"I2SOUT4", NULL, "I2SOUT4_CG"},
+
+	/* i2sout6 */
+	{"I2SOUT6_CH1", "DL0_CH1", "DL0"},
+	{"I2SOUT6_CH2", "DL0_CH2", "DL0"},
+	{"I2SOUT6_CH1", "DL1_CH1", "DL1"},
+	{"I2SOUT6_CH2", "DL1_CH2", "DL1"},
+	{"I2SOUT6_CH1", "DL2_CH1", "DL2"},
+	{"I2SOUT6_CH2", "DL2_CH2", "DL2"},
+	{"I2SOUT6_CH1", "DL3_CH1", "DL3"},
+	{"I2SOUT6_CH2", "DL3_CH2", "DL3"},
+	{"I2SOUT6_CH1", "DL4_CH1", "DL4"},
+	{"I2SOUT6_CH2", "DL4_CH2", "DL4"},
+	{"I2SOUT6_CH1", "DL5_CH1", "DL5"},
+	{"I2SOUT6_CH2", "DL5_CH2", "DL5"},
+	{"I2SOUT6_CH1", "DL6_CH1", "DL6"},
+	{"I2SOUT6_CH2", "DL6_CH2", "DL6"},
+	{"I2SOUT6_CH1", "DL7_CH1", "DL7"},
+	{"I2SOUT6_CH2", "DL7_CH2", "DL7"},
+	{"I2SOUT6_CH1", "DL8_CH1", "DL8"},
+	{"I2SOUT6_CH2", "DL8_CH2", "DL8"},
+	{"I2SOUT6_CH1", "DL23_CH1", "DL23"},
+	{"I2SOUT6_CH2", "DL23_CH2", "DL23"},
+	{"I2SOUT6_CH1", "DL_24CH_CH1", "DL_24CH"},
+	{"I2SOUT6_CH2", "DL_24CH_CH2", "DL_24CH"},
+
+	/* SOF Downlink */
+	{"I2SOUT6_CH1", "DL1_CH1", "SOF_DMA_DL1"},
+	{"I2SOUT6_CH2", "DL1_CH2", "SOF_DMA_DL1"},
+	{"I2SOUT6_CH1", "DL_24CH_CH1", "SOF_DMA_DL_24CH"},
+	{"I2SOUT6_CH2", "DL_24CH_CH2", "SOF_DMA_DL_24CH"},
+
+	{"I2SOUT6", NULL, "I2SOUT6_CH1"},
+	{"I2SOUT6", NULL, "I2SOUT6_CH2"},
+
+	{"I2SOUT6", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT6", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT6", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT6", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT6", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT6", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT6", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT6", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT6", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT6", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT6", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+	{"I2SOUT6", NULL, "I2SOUT6_EN"},
+	{"I2SOUT6", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect},
+
+	{"I2SOUT6", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT6", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT6", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT6", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT6", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT6", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT6", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT6", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT6", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT6", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT6", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT6", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"I2SOUT6", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{I2SOUT6_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+	{I2SOUT6_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+
+	{"I2SOUT6", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT6", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT6", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT6", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT6", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT6", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT6", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT6", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT6", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT6", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT6", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT6", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"I2SOUT6", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{I2SOUT6_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+	{I2SOUT6_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+	/* CG */
+	{"I2SOUT6", NULL, "I2SOUT6_CG"},
+	{"I2SOUT6", NULL, "I2SIN6_CG"},
+
+	/* fmi2s */
+	{"FMI2S_MASTER", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+	{"FMI2S_MASTER", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+	{"FMI2S_MASTER", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect},
+	{"FMI2S_MASTER", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect},
+	{"FMI2S_MASTER", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect},
+	{"FMI2S_MASTER", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect},
+	{"FMI2S_MASTER", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+	{"FMI2S_MASTER", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+	{"FMI2S_MASTER", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect},
+	{"FMI2S_MASTER", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect},
+	{"FMI2S_MASTER", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+	{"FMI2S_MASTER", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect},
+	{"FMI2S_MASTER", NULL, "FMI2S_MASTER_EN"},
+
+	{"FMI2S_MASTER", NULL, I2SIN0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"FMI2S_MASTER", NULL, I2SIN1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"FMI2S_MASTER", NULL, I2SIN2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"FMI2S_MASTER", NULL, I2SIN3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"FMI2S_MASTER", NULL, I2SIN4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"FMI2S_MASTER", NULL, I2SIN6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"FMI2S_MASTER", NULL, I2SOUT0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"FMI2S_MASTER", NULL, I2SOUT1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"FMI2S_MASTER", NULL, I2SOUT2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"FMI2S_MASTER", NULL, I2SOUT3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"FMI2S_MASTER", NULL, I2SOUT4_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"FMI2S_MASTER", NULL, I2SOUT6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{"FMI2S_MASTER", NULL, FMI2S_MASTER_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
+	{FMI2S_MASTER_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+	{FMI2S_MASTER_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+
+	{"FMI2S_MASTER", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"FMI2S_MASTER", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"FMI2S_MASTER", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"FMI2S_MASTER", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"FMI2S_MASTER", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"FMI2S_MASTER", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"FMI2S_MASTER", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"FMI2S_MASTER", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"FMI2S_MASTER", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"FMI2S_MASTER", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"FMI2S_MASTER", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"FMI2S_MASTER", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{"FMI2S_MASTER", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+	{FMI2S_MASTER_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+	{FMI2S_MASTER_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+	/* CG */
+	{"FMI2S_MASTER", NULL, "FMI2S_MASTER_CG"},
+
+	/* allow i2s on without codec on */
+	{"I2SIN0", NULL, "I2S_IN0_Mux"},
+	{"I2S_IN0_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
+
+	{"I2SIN1", NULL, "I2S_IN1_Mux"},
+	{"I2S_IN1_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
+
+	{"I2SIN2", NULL, "I2S_IN2_Mux"},
+	{"I2S_IN2_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
+
+	{"I2SIN3", NULL, "I2S_IN3_Mux"},
+	{"I2S_IN3_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
+
+	{"I2SIN4", NULL, "I2S_IN4_Mux"},
+	{"I2S_IN4_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
+
+	{"I2SIN6", NULL, "I2S_IN6_Mux"},
+	{"I2S_IN6_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
+
+	{"I2S_OUT0_Mux", "Dummy_Widget", "I2SOUT0"},
+	{"I2S_DUMMY_OUT", NULL, "I2S_OUT0_Mux"},
+
+	{"I2S_OUT1_Mux", "Dummy_Widget", "I2SOUT1"},
+	{"I2S_DUMMY_OUT", NULL, "I2S_OUT1_Mux"},
+
+	{"I2S_OUT2_Mux", "Dummy_Widget", "I2SOUT2"},
+	{"I2S_DUMMY_OUT", NULL, "I2S_OUT2_Mux"},
+
+	{"I2S_OUT3_Mux", "Dummy_Widget", "I2SOUT3"},
+	{"I2S_DUMMY_OUT", NULL, "I2S_OUT3_Mux"},
+	{"I2S_OUT4_Mux", "Dummy_Widget", "I2SOUT4"},
+	{"I2S_DUMMY_OUT", NULL, "I2S_OUT4_Mux"},
+
+	{"I2S_OUT6_Mux", "Dummy_Widget", "I2SOUT6"},
+	{"I2S_DUMMY_OUT", NULL, "I2S_OUT6_Mux"},
+};
+
+/* i2s dai ops*/
+static int mtk_dai_i2s_config(struct mtk_base_afe *afe,
+			      struct snd_pcm_hw_params *params,
+			      int i2s_id)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_afe_i2s_priv *i2s_priv;
+	struct mtk_afe_i2s_priv *i2sin_priv = NULL;
+	int id = i2s_id - MT8196_DAI_I2S_IN0; //47
+	struct mtk_base_etdm_data etdm_data;
+	unsigned int rate = params_rate(params);
+	unsigned int rate_reg = get_etdm_inconn_rate(rate);
+	snd_pcm_format_t format = params_format(params);
+	unsigned int channels = params_channels(params);
+	unsigned int i2s_con = 0;
+	int ret = 0;
+	int pad_top = 0;
+
+	if (i2s_id >= MT8196_DAI_NUM || i2s_id < 0)
+		return -EINVAL;
+	i2s_priv = afe_priv->dai_priv[i2s_id];
+
+	if (!i2s_priv)
+		return -EINVAL;
+
+	if (id < 0 || id >= DAI_I2S_NUM) {
+		dev_err(afe->dev, "i2s id is invalid\n");
+		return -EINVAL;
+	}
+
+	dev_info(afe->dev, "id: %d, rate: %d, pcm_fmt: %d, fmt: %d, ch: %d\n",
+		 i2s_id, rate, format, i2s_priv->format, channels);
+
+	i2s_priv->rate = rate;
+	etdm_data = mtk_etdm_data[id];
+
+	if (is_etdm_in_pad_top(id))
+		pad_top = 0x3;
+	else
+		pad_top = 0x5;
+
+	switch (id) {
+	case DAI_FMI2S_MASTER:
+		i2s_con = I2S_IN_PAD_IO_MUX << I2SIN_PAD_SEL_SFT;
+		i2s_con |= rate_reg << I2S_MODE_SFT;
+		i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT;
+		i2s_con |= get_i2s_wlen(format) << I2S_WLEN_SFT;
+		regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON,
+				   0xffffeffe, i2s_con);
+		break;
+	case DAI_I2SIN0:
+	case DAI_I2SIN1:
+	case DAI_I2SIN2:
+	case DAI_I2SIN3:
+	case DAI_I2SIN4:
+	case DAI_I2SIN6:
+		/* ---etdm in --- */
+		regmap_update_bits(afe->regmap,
+				   etdm_data.init_count_reg,
+				   etdm_data.init_count_mask << etdm_data.init_count_shift,
+				   0x5 << etdm_data.init_count_shift);
+
+		/* 3: pad top 5: no pad top */
+		regmap_update_bits(afe->regmap,
+				   etdm_data.init_point_reg,
+				   etdm_data.init_point_mask << etdm_data.init_point_shift,
+				   pad_top << etdm_data.init_point_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.lrck_reset_reg,
+				   etdm_data.lrck_reset_mask << etdm_data.lrck_reset_shift,
+				   0x1 << etdm_data.lrck_reset_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.clk_source_reg,
+				   etdm_data.clk_source_mask << etdm_data.clk_source_shift,
+				   ETDM_CLK_SOURCE_APLL << etdm_data.clk_source_shift);
+
+		/* 0: manual 1: auto */
+		regmap_update_bits(afe->regmap,
+				   etdm_data.ck_en_sel_reg,
+				   etdm_data.ck_en_sel_mask << etdm_data.ck_en_sel_shift,
+				   0x1 << etdm_data.ck_en_sel_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.fs_timing_reg,
+				   etdm_data.fs_timing_mask << etdm_data.fs_timing_shift,
+				   get_etdm_rate(rate) << etdm_data.fs_timing_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.relatch_en_sel_reg,
+				   etdm_data.relatch_en_sel_mask << etdm_data.relatch_en_sel_shift,
+				   get_etdm_inconn_rate(rate) << etdm_data.relatch_en_sel_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.use_afifo_reg,
+				   etdm_data.use_afifo_mask << etdm_data.use_afifo_shift,
+				   0x0 << etdm_data.use_afifo_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.afifo_mode_reg,
+				   etdm_data.afifo_mode_mask << etdm_data.afifo_mode_shift,
+				   0x0 << etdm_data.afifo_mode_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.almost_end_ch_reg,
+				   etdm_data.almost_end_ch_mask << etdm_data.almost_end_ch_shift,
+				   0x0 << etdm_data.almost_end_ch_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.almost_end_bit_reg,
+				   etdm_data.almost_end_bit_mask << etdm_data.almost_end_bit_shift,
+				   0x0 << etdm_data.almost_end_bit_shift);
+
+		if (is_etdm_in_pad_top(id)) {
+			regmap_update_bits(afe->regmap,
+					   etdm_data.out2latch_time_reg,
+					   etdm_data.out2latch_time_mask <<
+					   etdm_data.out2latch_time_shift,
+					   0x6 << etdm_data.out2latch_time_shift);
+		} else {
+			regmap_update_bits(afe->regmap,
+					   etdm_data.out2latch_time_reg,
+					   etdm_data.out2latch_time_mask <<
+					   etdm_data.out2latch_time_shift,
+					   0x4 << etdm_data.out2latch_time_shift);
+		}
+
+		if (id == DAI_I2SIN4) {
+			dev_dbg(afe->dev, "i2sin4, id: %d, fmt: %d, ch: %d, ip_mode: %d, sync: %d\n",
+				id,
+				i2s_priv->format,
+				channels,
+				i2s_priv->ip_mode,
+				i2s_priv->sync);
+
+			/* Fmt Mode: 0x00 i2s, 0x04 adsp_a, DSP_A mode for multi-channel */
+			regmap_update_bits(afe->regmap,
+					   etdm_data.tdm_mode_reg,
+					   etdm_data.tdm_mode_mask << etdm_data.tdm_mode_shift,
+					   i2s_priv->format << etdm_data.tdm_mode_shift);
+
+			/* set etdm ch */
+			regmap_update_bits(afe->regmap,
+					   etdm_data.ch_reg,
+					   etdm_data.ch_mask << etdm_data.ch_shift,
+					   (channels - 1) << etdm_data.ch_shift);
+
+			/* set etdm ip mode */
+			regmap_update_bits(afe->regmap,
+					   etdm_data.ip_mode_reg,
+					   etdm_data.ip_mode_mask << etdm_data.ip_mode_shift,
+					   i2s_priv->ip_mode << etdm_data.ip_mode_shift);
+
+			/* set etdm sync */
+			regmap_update_bits(afe->regmap,
+					   etdm_data.sync_reg,
+					   etdm_data.sync_mask << etdm_data.sync_shift,
+					   i2s_priv->sync << etdm_data.sync_shift);
+		} else {
+			/* default i2s */
+			regmap_update_bits(afe->regmap,
+					   etdm_data.tdm_mode_reg,
+					   etdm_data.tdm_mode_mask << etdm_data.tdm_mode_shift,
+					   0x0 << etdm_data.tdm_mode_shift);
+
+			/* set etdm sync */
+			regmap_update_bits(afe->regmap,
+					   etdm_data.sync_reg,
+					   etdm_data.sync_mask << etdm_data.sync_shift,
+					   0x0 << etdm_data.sync_shift);
+		}
+
+		/* APLL */
+		regmap_update_bits(afe->regmap,
+				   etdm_data.relatch_domain_sel_reg,
+				   etdm_data.relatch_domain_sel_mask <<
+				   etdm_data.relatch_domain_sel_shift,
+				   ETDM_RELATCH_SEL_APLL << etdm_data.relatch_domain_sel_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.bit_length_reg,
+				   etdm_data.bit_length_mask << etdm_data.bit_length_shift,
+				   get_etdm_lrck_width(format) << etdm_data.bit_length_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.word_length_reg,
+				   etdm_data.word_length_mask << etdm_data.word_length_shift,
+				   get_etdm_wlen(format) << etdm_data.word_length_shift);
+
+		/* ---etdm cowork --- */
+		regmap_update_bits(afe->regmap,
+				   etdm_data.cowork_reg,
+				   etdm_data.cowork_mask << etdm_data.cowork_shift,
+				   etdm_data.cowork_val << etdm_data.cowork_shift);
+
+		/* i2s with pad top setting */
+		if (is_etdm_in_pad_top(id) && etdm_data.pad_top_ck_en_reg != -1) {
+			regmap_update_bits(afe->regmap,
+					   etdm_data.pad_top_ck_en_reg,
+					   etdm_data.pad_top_ck_en_mask <<
+					   etdm_data.pad_top_ck_en_shift,
+					   0x1 << etdm_data.pad_top_ck_en_shift);
+
+			regmap_update_bits(afe->regmap,
+					   etdm_data.master_latch_reg,
+					   etdm_data.master_latch_mask <<
+					   etdm_data.master_latch_shift,
+					   0x0 << etdm_data.master_latch_shift);
+		}
+		break;
+	case DAI_I2SOUT0:
+	case DAI_I2SOUT1:
+	case DAI_I2SOUT2:
+	case DAI_I2SOUT3:
+	case DAI_I2SOUT4:
+	case DAI_I2SOUT6:
+		/* ---etdm out --- */
+		regmap_update_bits(afe->regmap,
+				   etdm_data.init_count_reg,
+				   etdm_data.init_count_mask << etdm_data.init_count_shift,
+				   0x5 << etdm_data.init_count_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.init_point_reg,
+				   etdm_data.init_point_mask << etdm_data.init_point_shift,
+				   0x6 << etdm_data.init_point_shift);
+
+		// clock speed > 22M need to set relatch time to avoid duplicate porint
+		if (rate * channels * (get_etdm_wlen(format) + 1) >= ETDM_22M_CLOCK_THRES &&
+		    get_etdm_wlen(format) >= 2) {
+			regmap_update_bits(afe->regmap,
+					   etdm_data.in2latch_time_reg,
+					   etdm_data.in2latch_time_mask <<
+					   etdm_data.in2latch_time_shift,
+					   (get_etdm_wlen(format) - 2) <<
+					   etdm_data.in2latch_time_shift);
+		} else {
+			regmap_update_bits(afe->regmap,
+					   etdm_data.in2latch_time_reg,
+					   etdm_data.in2latch_time_mask <<
+					   etdm_data.in2latch_time_shift,
+					   0x6 << etdm_data.in2latch_time_shift);
+		}
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.lrck_reset_reg,
+				   etdm_data.lrck_reset_mask << etdm_data.lrck_reset_shift,
+				   0x1 << etdm_data.lrck_reset_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.fs_timing_reg,
+				   etdm_data.fs_timing_mask << etdm_data.fs_timing_shift,
+				   get_etdm_rate(rate) << etdm_data.fs_timing_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.clk_source_reg,
+				   etdm_data.clk_source_mask << etdm_data.clk_source_shift,
+				   ETDM_CLK_SOURCE_APLL << etdm_data.clk_source_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.relatch_en_sel_reg,
+				   etdm_data.relatch_en_sel_mask << etdm_data.relatch_en_sel_shift,
+				   get_etdm_inconn_rate(rate) << etdm_data.relatch_en_sel_shift);
+
+		if (id == DAI_I2SOUT4) {
+			dev_dbg(afe->dev, "i2sout4, id: %d fmt: %d, ch: %d, sync: %d\n",
+				id, i2s_priv->format, channels, i2s_priv->sync);
+
+			/* Fmt Mode: 0x00 i2s, 0x04 adsp_a, DSP_A mode for multi-channel */
+			regmap_update_bits(afe->regmap,
+					   etdm_data.tdm_mode_reg,
+					   etdm_data.tdm_mode_mask << etdm_data.tdm_mode_shift,
+					   i2s_priv->format << etdm_data.tdm_mode_shift);
+
+			/* set etdm ch */
+			regmap_update_bits(afe->regmap,
+					   etdm_data.ch_reg,
+					   etdm_data.ch_mask << etdm_data.ch_shift,
+					   (channels - 1) << etdm_data.ch_shift);
+
+			/* set etdm sync */
+			regmap_update_bits(afe->regmap,
+					   etdm_data.sync_reg,
+					   etdm_data.sync_mask << etdm_data.sync_shift,
+					   i2s_priv->sync << etdm_data.sync_shift);
+		} else {
+			regmap_update_bits(afe->regmap,
+					   etdm_data.tdm_mode_reg,
+					   etdm_data.tdm_mode_mask << etdm_data.tdm_mode_shift,
+					   0x0 << etdm_data.tdm_mode_shift);
+		}
+
+		/* APLL */
+		regmap_update_bits(afe->regmap,
+				   etdm_data.relatch_domain_sel_reg,
+				   etdm_data.relatch_domain_sel_mask <<
+				   etdm_data.relatch_domain_sel_shift,
+				   ETDM_RELATCH_SEL_APLL << etdm_data.relatch_domain_sel_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.bit_length_reg,
+				   etdm_data.bit_length_mask << etdm_data.bit_length_shift,
+				   get_etdm_lrck_width(format) << etdm_data.bit_length_shift);
+
+		regmap_update_bits(afe->regmap,
+				   etdm_data.word_length_reg,
+				   etdm_data.word_length_mask << etdm_data.word_length_shift,
+				   get_etdm_wlen(format) << etdm_data.word_length_shift);
+
+		/* ---etdm cowork --- */
+		regmap_update_bits(afe->regmap,
+				   etdm_data.cowork_reg,
+				   etdm_data.cowork_mask << etdm_data.cowork_shift,
+				   etdm_data.cowork_val << etdm_data.cowork_shift);
+
+		/* i2s with pad top setting */
+		if (is_etdm_in_pad_top(id) && etdm_data.pad_top_ck_en_reg != -1) {
+			regmap_update_bits(afe->regmap,
+					   etdm_data.pad_top_ck_en_reg,
+					   etdm_data.cowork_mask << etdm_data.pad_top_ck_en_shift,
+					   0x1 << etdm_data.pad_top_ck_en_shift);
+
+			regmap_update_bits(afe->regmap,
+					   etdm_data.master_latch_reg,
+					   etdm_data.master_latch_mask <<
+					   etdm_data.master_latch_shift,
+					   0x0 << etdm_data.master_latch_shift);
+		}
+		break;
+	default:
+		dev_err(afe->dev, "id %d not support\n", id);
+		return -EINVAL;
+	}
+
+	/* set share i2s */
+	if (i2s_priv && i2s_priv->share_i2s_id >= 0) {
+		i2sin_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id];
+		i2sin_priv->format = i2s_priv->format;
+		ret = mtk_dai_i2s_config(afe, params, i2s_priv->share_i2s_id);
+	}
+
+	return ret;
+}
+
+static int mtk_dai_i2s_hw_params(struct snd_pcm_substream *substream,
+				 struct snd_pcm_hw_params *params,
+				 struct snd_soc_dai *dai)
+{
+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+
+	return mtk_dai_i2s_config(afe, params, dai->id);
+}
+
+static int mtk_dai_i2s_set_sysclk(struct snd_soc_dai *dai,
+				  int clk_id, unsigned int freq, int dir)
+{
+	struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_afe_i2s_priv *i2s_priv;
+	int apll;
+	int apll_rate;
+
+	if (dai->id >= MT8196_DAI_NUM || dai->id < 0)
+		return -EINVAL;
+	i2s_priv = afe_priv->dai_priv[dai->id];
+
+	dev_dbg(afe->dev, "freq: %u\n", freq);
+
+	if (!i2s_priv)
+		return -EINVAL;
+
+	if (dir != SND_SOC_CLOCK_OUT)
+		return -EINVAL;
+
+	apll = mt8196_get_apll_by_rate(afe, freq);
+	apll_rate = mt8196_get_apll_rate(afe, apll);
+
+	if (freq > apll_rate)
+		return -EINVAL;
+
+	if (apll_rate % freq != 0)
+		return -EINVAL;
+
+	i2s_priv->mclk_rate = freq;
+	i2s_priv->mclk_apll = apll;
+
+	if (i2s_priv->share_i2s_id > 0) {
+		struct mtk_afe_i2s_priv *share_i2s_priv;
+
+		share_i2s_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id];
+		if (!share_i2s_priv)
+			return -EINVAL;
+
+		share_i2s_priv->mclk_rate = i2s_priv->mclk_rate;
+		share_i2s_priv->mclk_apll = i2s_priv->mclk_apll;
+	}
+	return 0;
+}
+
+static int mtk_dai_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_afe_i2s_priv *i2s_priv;
+
+	if (dai->id >= MT8196_DAI_NUM || dai->id < 0)
+		return -EINVAL;
+
+	i2s_priv = afe_priv->dai_priv[dai->id];
+
+	if (!i2s_priv)
+		return -EINVAL;
+
+	dev_dbg(afe->dev, "dai->id: %d, fmt: 0x%x\n", dai->id, fmt);
+
+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+	case SND_SOC_DAIFMT_I2S:
+		i2s_priv->format = MTK_DAI_ETDM_FORMAT_I2S;
+		break;
+	case SND_SOC_DAIFMT_LEFT_J:
+		i2s_priv->format = MTK_DAI_ETDM_FORMAT_LJ;
+		break;
+	case SND_SOC_DAIFMT_RIGHT_J:
+		i2s_priv->format = MTK_DAI_ETDM_FORMAT_RJ;
+		break;
+	case SND_SOC_DAIFMT_DSP_A:
+		i2s_priv->format = MTK_DAI_ETDM_FORMAT_DSPA;
+		break;
+	case SND_SOC_DAIFMT_DSP_B:
+		i2s_priv->format = MTK_DAI_ETDM_FORMAT_DSPB;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	dev_dbg(afe->dev, "dai->id: %d, i2s_priv->format: 0x%x\n",
+		dai->id, i2s_priv->format);
+
+	return 0;
+}
+
+static const struct snd_soc_dai_ops mtk_dai_i2s_ops = {
+	.hw_params = mtk_dai_i2s_hw_params,
+	.set_sysclk = mtk_dai_i2s_set_sysclk,
+	.set_fmt = mtk_dai_i2s_set_fmt,
+};
+
+/* dai driver */
+#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_384000)
+#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S8 |\
+			  SNDRV_PCM_FMTBIT_S16_LE |\
+			  SNDRV_PCM_FMTBIT_S24_LE |\
+			  SNDRV_PCM_FMTBIT_S32_LE)
+
+#define MT8196_I2S_DAI_PLAYBACK(_name, _id, max_ch) \
+{ \
+	.name = #_name, \
+	.id = _id, \
+	.playback = { \
+		.stream_name = #_name, \
+		.channels_min = 1, \
+		.channels_max = max_ch, \
+		.rates = MTK_ETDM_RATES, \
+		.formats = MTK_ETDM_FORMATS, \
+	}, \
+	.ops = &mtk_dai_i2s_ops, \
+}
+
+#define MT8196_I2S_DAI_CAPTURE(_name, _id, max_ch) \
+{ \
+	.name = #_name, \
+	.id = _id, \
+	.capture = { \
+		.stream_name = #_name, \
+		.channels_min = 1, \
+		.channels_max = max_ch, \
+		.rates = MTK_ETDM_RATES, \
+		.formats = MTK_ETDM_FORMATS, \
+	}, \
+	.ops = &mtk_dai_i2s_ops, \
+}
+
+static struct snd_soc_dai_driver mtk_dai_i2s_driver[] = {
+	/* capture */
+	MT8196_I2S_DAI_CAPTURE(I2SIN0, MT8196_DAI_I2S_IN0, 2),
+	MT8196_I2S_DAI_CAPTURE(I2SIN1, MT8196_DAI_I2S_IN1, 2),
+	MT8196_I2S_DAI_CAPTURE(I2SIN2, MT8196_DAI_I2S_IN2, 2),
+	MT8196_I2S_DAI_CAPTURE(I2SIN3, MT8196_DAI_I2S_IN3, 2),
+	MT8196_I2S_DAI_CAPTURE(I2SIN4, MT8196_DAI_I2S_IN4, 8),
+	MT8196_I2S_DAI_CAPTURE(I2SIN6, MT8196_DAI_I2S_IN6, 2),
+	MT8196_I2S_DAI_CAPTURE(FMI2S_MASTER, MT8196_DAI_FM_I2S_MASTER, 2),
+	/* playback */
+	MT8196_I2S_DAI_PLAYBACK(I2SOUT0, MT8196_DAI_I2S_OUT0, 2),
+	MT8196_I2S_DAI_PLAYBACK(I2SOUT1, MT8196_DAI_I2S_OUT1, 2),
+	MT8196_I2S_DAI_PLAYBACK(I2SOUT2, MT8196_DAI_I2S_OUT2, 2),
+	MT8196_I2S_DAI_PLAYBACK(I2SOUT3, MT8196_DAI_I2S_OUT3, 2),
+	MT8196_I2S_DAI_PLAYBACK(I2SOUT4, MT8196_DAI_I2S_OUT4, 8),
+	MT8196_I2S_DAI_PLAYBACK(I2SOUT6, MT8196_DAI_I2S_OUT6, 2),
+};
+
+static const struct mtk_afe_i2s_priv mt8196_i2s_priv[DAI_I2S_NUM] = {
+	[DAI_I2SIN0] = {
+		.id = MT8196_DAI_I2S_IN0,
+		.mclk_id = MT8196_I2SIN0_MCK,
+		.share_property_name = "i2sin0-share",
+		.share_i2s_id = -1,
+	},
+	[DAI_I2SIN1] = {
+		.id = MT8196_DAI_I2S_IN1,
+		.mclk_id = MT8196_I2SIN1_MCK,
+		.share_property_name = "i2sin1-share",
+		.share_i2s_id = -1,
+	},
+	[DAI_I2SIN2] = {
+		.id = MT8196_DAI_I2S_IN2,
+		.mclk_id = MT8196_I2SIN0_MCK,
+		.share_property_name = "i2sin2-share",
+		.share_i2s_id = -1,
+	},
+	[DAI_I2SIN3] = {
+		.id = MT8196_DAI_I2S_IN3,
+		.mclk_id = MT8196_I2SIN0_MCK,
+		.share_property_name = "i2sin3-share",
+		.share_i2s_id = -1,
+	},
+	[DAI_I2SIN4] = {
+		.id = MT8196_DAI_I2S_IN4,
+		.mclk_id = MT8196_I2SIN0_MCK,
+		.share_property_name = "i2sin4-share",
+		.share_i2s_id = -1,
+		.sync = 0,
+		.ip_mode = 0,
+	},
+	[DAI_I2SIN6] = {
+		.id = MT8196_DAI_I2S_IN6,
+		.mclk_id = MT8196_I2SIN0_MCK,
+		.share_property_name = "i2sout6-share",
+		.share_i2s_id = -1,
+	},
+	[DAI_I2SOUT0] = {
+		.id = MT8196_DAI_I2S_OUT0,
+		.mclk_id = MT8196_I2SIN0_MCK,
+		.share_property_name = "i2sout0-share",
+		.share_i2s_id = MT8196_DAI_I2S_IN0,
+	},
+	[DAI_I2SOUT1] = {
+		.id = MT8196_DAI_I2S_OUT1,
+		.mclk_id = MT8196_I2SIN1_MCK,
+		.share_property_name = "i2sout1-share",
+		.share_i2s_id = MT8196_DAI_I2S_IN1,
+	},
+	[DAI_I2SOUT2] = {
+		.id = MT8196_DAI_I2S_OUT2,
+		.mclk_id = MT8196_I2SIN0_MCK,
+		.share_property_name = "i2sout2-share",
+		.share_i2s_id = MT8196_DAI_I2S_IN2,
+	},
+	[DAI_I2SOUT3] = {
+		.id = MT8196_DAI_I2S_OUT3,
+		.mclk_id = MT8196_I2SIN0_MCK,
+		.share_property_name = "i2sout3-share",
+		.share_i2s_id = MT8196_DAI_I2S_IN3,
+	},
+	[DAI_I2SOUT4] = {
+		.id = MT8196_DAI_I2S_OUT4,
+		.mclk_id = MT8196_I2SIN0_MCK,
+		.share_property_name = "i2sout4-share",
+		.share_i2s_id = MT8196_DAI_I2S_IN4,
+		.sync = 0,
+	},
+	[DAI_I2SOUT6] = {
+		.id = MT8196_DAI_I2S_OUT6,
+		.mclk_id = MT8196_I2SIN0_MCK,
+		.share_property_name = "i2sout6-share",
+		.share_i2s_id = MT8196_DAI_I2S_IN6,
+	},
+	[DAI_FMI2S_MASTER] = {
+		.id = MT8196_DAI_FM_I2S_MASTER,
+		.mclk_id = MT8196_FMI2S_MCK,
+		.share_property_name = "fmi2s-share",
+		.share_i2s_id = -1,
+	},
+};
+
+static int mt8196_dai_i2s_get_share(struct mtk_base_afe *afe)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	const struct device_node *of_node = afe->dev->of_node;
+	const char *of_str;
+	const char *property_name;
+	struct mtk_afe_i2s_priv *i2s_priv;
+	int i;
+
+	for (i = 0; i < DAI_I2S_NUM; i++) {
+		i2s_priv = afe_priv->dai_priv[mt8196_i2s_priv[i].id];
+		property_name = mt8196_i2s_priv[i].share_property_name;
+		if (of_property_read_string(of_node, property_name, &of_str))
+			continue;
+		i2s_priv->share_i2s_id = get_i2s_id_by_name(afe, of_str);
+	}
+	return 0;
+}
+
+static int init_i2s_priv_data(struct mtk_base_afe *afe)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_afe_i2s_priv *i2s_priv;
+	int size;
+	int id;
+	int i;
+
+	for (i = 0; i < DAI_I2S_NUM; i++) {
+		if (&mt8196_i2s_priv[i]) {
+			id = mt8196_i2s_priv[i].id;
+			size = sizeof(struct mtk_afe_i2s_priv);
+
+			if (id >= MT8196_DAI_NUM || id < 0)
+				return -EINVAL;
+
+			i2s_priv = devm_kzalloc(afe->dev, size, GFP_KERNEL);
+			if (!i2s_priv)
+				return -ENOMEM;
+
+			memcpy(i2s_priv, &mt8196_i2s_priv[i], size);
+
+			afe_priv->dai_priv[id] = i2s_priv;
+		}
+	}
+	return 0;
+}
+
+int mt8196_dai_i2s_register(struct mtk_base_afe *afe)
+{
+	struct mtk_base_afe_dai *dai;
+	int ret;
+
+	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
+	if (!dai)
+		return -ENOMEM;
+
+	list_add(&dai->list, &afe->sub_dais);
+
+	dai->dai_drivers = mtk_dai_i2s_driver;
+	dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_i2s_driver);
+
+	dai->controls = mtk_dai_i2s_controls;
+	dai->num_controls = ARRAY_SIZE(mtk_dai_i2s_controls);
+	dai->dapm_widgets = mtk_dai_i2s_widgets;
+	dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_i2s_widgets);
+	dai->dapm_routes = mtk_dai_i2s_routes;
+	dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_i2s_routes);
+
+	/* set all dai i2s private data */
+	ret = init_i2s_priv_data(afe);
+	if (ret)
+		return ret;
+
+	/* parse share i2s */
+	ret = mt8196_dai_i2s_get_share(afe);
+	if (ret)
+		return ret;
+
+	return 0;
+}
-- 
2.45.2



From darren.ye at mediatek.com  Wed May 14 01:11:09 2025
From: darren.ye at mediatek.com (Darren.Ye)
Date: Wed, 14 May 2025 16:11:09 +0800
Subject: [PATCH v3 07/10] ASoC: mediatek: mt8196: add platform driver
In-Reply-To: <20250514081125.24475-1-darren.ye@mediatek.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
Message-ID: <20250514081125.24475-8-darren.ye@mediatek.com>

From: Darren Ye <darren.ye at mediatek.com>

Add mt8196 platform driver.

Signed-off-by: Darren Ye <darren.ye at mediatek.com>
---
 sound/soc/mediatek/Kconfig                 |   10 +
 sound/soc/mediatek/Makefile                |    1 +
 sound/soc/mediatek/mt8196/Makefile         |   15 +
 sound/soc/mediatek/mt8196/mt8196-afe-pcm.c | 2642 ++++++++++++++++++++
 4 files changed, 2668 insertions(+)
 create mode 100644 sound/soc/mediatek/mt8196/Makefile
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-pcm.c

diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig
index 90e367586493..63d4abebb539 100644
--- a/sound/soc/mediatek/Kconfig
+++ b/sound/soc/mediatek/Kconfig
@@ -319,3 +319,13 @@ config SND_SOC_MT8365_MT6357
 	  boards with the MT6357 PMIC codec.
 	  Select Y if you have such device.
 	  If unsure select "N".
+
+config SND_SOC_MT8196
+	tristate "ASoC support for Mediatek MT8196 chip"
+	depends on ARCH_MEDIATEK
+	select SND_SOC_MEDIATEK
+	help
+	  This adds ASoC driver for Mediatek MT8196 boards
+	  that can be used with other codecs.
+	  Select Y if you have such device.
+	  If unsure select "N".
\ No newline at end of file
diff --git a/sound/soc/mediatek/Makefile b/sound/soc/mediatek/Makefile
index 4b55434f2168..11d7c484a5d3 100644
--- a/sound/soc/mediatek/Makefile
+++ b/sound/soc/mediatek/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_SND_SOC_MT8188) += mt8188/
 obj-$(CONFIG_SND_SOC_MT8192) += mt8192/
 obj-$(CONFIG_SND_SOC_MT8195) += mt8195/
 obj-$(CONFIG_SND_SOC_MT8365) += mt8365/
+obj-$(CONFIG_SND_SOC_MT8196) += mt8196/
diff --git a/sound/soc/mediatek/mt8196/Makefile b/sound/soc/mediatek/mt8196/Makefile
new file mode 100644
index 000000000000..b8a51a53d52a
--- /dev/null
+++ b/sound/soc/mediatek/mt8196/Makefile
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0
+
+# common include path
+subdir-ccflags-y += -I$(srctree)/sound/soc/mediatek/common
+
+# platform driver
+snd-soc-mt8196-afe-objs += \
+	mt8196-afe-pcm.o \
+	mt8196-afe-clk.o \
+	mt8196-audsys-clk.o \
+	mt8196-dai-adda.o \
+	mt8196-dai-i2s.o \
+	mt8196-dai-tdm.o
+
+obj-$(CONFIG_SND_SOC_MT8196) += snd-soc-mt8196-afe.o
diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-pcm.c b/sound/soc/mediatek/mt8196/mt8196-afe-pcm.c
new file mode 100644
index 000000000000..c790827727e0
--- /dev/null
+++ b/sound/soc/mediatek/mt8196/mt8196-afe-pcm.c
@@ -0,0 +1,2642 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *  Mediatek ALSA SoC AFE platform driver for 8196
+ *
+ *  Copyright (c) 2024 MediaTek Inc.
+ *  Author: Darren Ye <darren.ye at mediatek.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/of_device.h>
+#include <sound/soc.h>
+#include <linux/of_reserved_mem.h>
+
+#include "mt8196-afe-clk.h"
+#include "mt8196-afe-common.h"
+#include "mtk-afe-fe-dai.h"
+#include "mtk-afe-platform-driver.h"
+#include "mt8196-interconnection.h"
+
+static const struct snd_pcm_hardware mt8196_afe_hardware = {
+	.info = (SNDRV_PCM_INFO_MMAP |
+		 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP |
+		 SNDRV_PCM_INFO_INTERLEAVED |
+		 SNDRV_PCM_INFO_MMAP_VALID),
+	.formats = (SNDRV_PCM_FMTBIT_S16_LE |
+		    SNDRV_PCM_FMTBIT_S24_LE |
+		    SNDRV_PCM_FMTBIT_S32_LE),
+	.period_bytes_min = 96,
+	.period_bytes_max = 4 * 48 * 1024,
+	.periods_min = 2,
+	.periods_max = 256,
+	.buffer_bytes_max = 256 * 1024,
+	.fifo_size = 0,
+};
+
+static unsigned int mt8196_rate_transform(struct device *dev,
+					  unsigned int rate)
+{
+	switch (rate) {
+	case 8000:
+		return MTK_AFE_IPM2P0_RATE_8K;
+	case 11025:
+		return MTK_AFE_IPM2P0_RATE_11K;
+	case 12000:
+		return MTK_AFE_IPM2P0_RATE_12K;
+	case 16000:
+		return MTK_AFE_IPM2P0_RATE_16K;
+	case 22050:
+		return MTK_AFE_IPM2P0_RATE_22K;
+	case 24000:
+		return MTK_AFE_IPM2P0_RATE_24K;
+	case 32000:
+		return MTK_AFE_IPM2P0_RATE_32K;
+	case 44100:
+		return MTK_AFE_IPM2P0_RATE_44K;
+	case 48000:
+		return MTK_AFE_IPM2P0_RATE_48K;
+	case 88200:
+		return MTK_AFE_IPM2P0_RATE_88K;
+	case 96000:
+		return MTK_AFE_IPM2P0_RATE_96K;
+	case 176400:
+		return MTK_AFE_IPM2P0_RATE_176K;
+	case 192000:
+		return MTK_AFE_IPM2P0_RATE_192K;
+	/* not support 260K */
+	case 352800:
+		return MTK_AFE_IPM2P0_RATE_352K;
+	case 384000:
+		return MTK_AFE_IPM2P0_RATE_384K;
+	default:
+		dev_info(dev, "rate %u invalid, use %d!!!\n",
+			 rate, MTK_AFE_IPM2P0_RATE_48K);
+		return MTK_AFE_IPM2P0_RATE_48K;
+	}
+}
+
+static void mt8196_set_cm_rate(struct mtk_base_afe *afe, int id, unsigned int rate)
+{
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+
+	afe_priv->cm_rate[id] = rate;
+}
+
+static int mt8196_convert_cm_ch(unsigned int ch)
+{
+	return ch - 1;
+}
+
+static unsigned int calculate_cm_update(int rate, int ch)
+{
+	unsigned int update_val;
+
+	update_val = 26000000 / rate / (ch / 2);
+	update_val = update_val * 10 / 7;
+	if (update_val > 100)
+		update_val = 100;
+	if (update_val < 7)
+		update_val = 7;
+
+	return update_val;
+}
+
+static int mt8196_set_cm(struct mtk_base_afe *afe, int id,
+			 bool update, bool swap, unsigned int ch)
+{
+	unsigned int rate = 0;
+	unsigned int update_val = 0;
+	int reg;
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+
+	dev_dbg(afe->dev, "CM%d, rate %d, update %d, swap %d, ch %d\n",
+		id, rate, update, swap, ch);
+
+	rate = afe_priv->cm_rate[id];
+	update_val = update ? calculate_cm_update(rate, (int)ch) : 0x64;
+
+	reg = AFE_CM0_CON0 + 0x10 * id;
+	/* update cnt */
+	regmap_update_bits(afe->regmap,
+			   reg,
+			   AFE_CM_UPDATE_CNT_MASK << AFE_CM_UPDATE_CNT_SFT,
+			   update_val << AFE_CM_UPDATE_CNT_SFT);
+
+	/* rate */
+	regmap_update_bits(afe->regmap,
+			   reg,
+			   AFE_CM_1X_EN_SEL_FS_MASK << AFE_CM_1X_EN_SEL_FS_SFT,
+			   rate << AFE_CM_1X_EN_SEL_FS_SFT);
+
+	/* ch num */
+	ch = mt8196_convert_cm_ch(ch);
+	regmap_update_bits(afe->regmap,
+			   reg,
+			   AFE_CM_CH_NUM_MASK << AFE_CM_CH_NUM_SFT,
+			   ch << AFE_CM_CH_NUM_SFT);
+
+	/* swap */
+	regmap_update_bits(afe->regmap,
+			   reg,
+			   AFE_CM_BYTE_SWAP_MASK << AFE_CM_BYTE_SWAP_SFT,
+			   swap << AFE_CM_BYTE_SWAP_SFT);
+
+	return 0;
+}
+
+static int mt8196_enable_cm_bypass(struct mtk_base_afe *afe, int id, bool en)
+{
+	int reg = AFE_CM0_CON0 + 0x10 * id;
+
+	regmap_update_bits(afe->regmap,
+			   reg,
+			   AFE_CM_BYPASS_MODE_MASK << AFE_CM_BYPASS_MODE_SFT,
+			   en << AFE_CM_BYPASS_MODE_SFT);
+
+	return 0;
+}
+
+static int mt8196_fe_startup(struct snd_pcm_substream *substream,
+			     struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+	int memif_num = cpu_dai->id;
+	struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
+	const struct snd_pcm_hardware *mtk_afe_hardware = afe->mtk_afe_hardware;
+	int ret;
+
+	dev_dbg(afe->dev, "memif_num: %d.\n", memif_num);
+
+	memif->substream = substream;
+
+	snd_pcm_hw_constraint_step(substream->runtime, 0,
+				   SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 16);
+
+	snd_soc_set_runtime_hwparams(substream, mtk_afe_hardware);
+
+	ret = snd_pcm_hw_constraint_integer(runtime,
+					    SNDRV_PCM_HW_PARAM_PERIODS);
+	if (ret < 0)
+		dev_info(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
+
+	/* dynamic allocate irq to memif */
+	if (memif->irq_usage < 0) {
+		int irq_id = mtk_dynamic_irq_acquire(afe);
+
+		if (irq_id != afe->irqs_size) {
+			/* link */
+			memif->irq_usage = irq_id;
+		} else {
+			dev_err(afe->dev, "no more asys irq\n");
+			ret = -EBUSY;
+		}
+	}
+	return ret;
+}
+
+static void mt8196_fe_shutdown(struct snd_pcm_substream *substream,
+			       struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+	int memif_num = cpu_dai->id;
+	struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
+	int irq_id = memif->irq_usage;
+
+	dev_dbg(afe->dev, "memif_num: %d.\n", memif_num);
+
+	memif->substream = NULL;
+	afe_priv->irq_cnt[memif_num] = 0;
+	afe_priv->xrun_assert[memif_num] = 0;
+
+	if (!memif->const_irq) {
+		mtk_dynamic_irq_release(afe, irq_id);
+		memif->irq_usage = -1;
+		memif->substream = NULL;
+	}
+}
+
+static int mt8196_fe_hw_params(struct snd_pcm_substream *substream,
+			       struct snd_pcm_hw_params *params,
+			       struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+	unsigned int channels = params_channels(params);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	int id = snd_soc_rtd_to_cpu(rtd, 0)->id;
+	struct mtk_base_afe_memif *memif = &afe->memif[id];
+	const struct mtk_base_memif_data *data = memif->data;
+
+	afe_priv->cm_channels = channels;
+
+	/* set channels */
+	if (data->ch_num_shift >= 0) {
+		regmap_update_bits(afe->regmap, data->ch_num_reg,
+				   data->ch_num_maskbit << data->ch_num_shift,
+				   channels << data->ch_num_shift);
+	}
+
+	return mtk_afe_fe_hw_params(substream, params, dai);
+}
+
+static int mt8196_fe_trigger(struct snd_pcm_substream *substream, int cmd,
+			     struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+	struct snd_pcm_runtime *const runtime = substream->runtime;
+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+	int id = cpu_dai->id;
+	struct mtk_base_afe_memif *memif = &afe->memif[id];
+	int irq_id = memif->irq_usage;
+	struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id];
+	const struct mtk_base_irq_data *irq_data = irqs->irq_data;
+	unsigned int counter = runtime->period_size;
+	unsigned int rate = runtime->rate;
+	int fs;
+	int ret = 0;
+	unsigned int tmp_reg = 0;
+
+	dev_info(afe->dev, "%s cmd %d, irq_id %d\n",
+		 memif->data->name, cmd, irq_id);
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+		dev_dbg(afe->dev, "%s cmd %d, id %d\n",
+			memif->data->name, cmd, id);
+		ret = mtk_memif_set_enable(afe, id);
+		if (ret) {
+			dev_err(afe->dev, "id %d, memif enable fail.\n", id);
+			return ret;
+		}
+
+		/*
+		 * for small latency record
+		 * ul memif need read some data before irq enable
+		 */
+		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+			if ((runtime->period_size * 1000) / rate <= 10)
+				usleep_range(300, 350);
+		}
+
+		/* set irq counter */
+		if (afe_priv->irq_cnt[id] > 0)
+			counter = afe_priv->irq_cnt[id];
+
+		regmap_update_bits(afe->regmap,
+				   irq_data->irq_cnt_reg,
+				   irq_data->irq_cnt_maskbit << irq_data->irq_cnt_shift,
+				   counter << irq_data->irq_cnt_shift);
+
+		/* set irq fs */
+		fs = afe->irq_fs(substream, runtime->rate);
+		if (fs < 0)
+			return -EINVAL;
+
+		if (irq_data->irq_fs_reg >= 0)
+			regmap_update_bits(afe->regmap,
+					   irq_data->irq_fs_reg,
+					   irq_data->irq_fs_maskbit << irq_data->irq_fs_shift,
+					   fs << irq_data->irq_fs_shift);
+
+		/* enable interrupt */
+		regmap_update_bits(afe->regmap,
+				   irq_data->irq_en_reg,
+				   1 << irq_data->irq_en_shift,
+				   1 << irq_data->irq_en_shift);
+
+		return 0;
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+		ret = mtk_memif_set_disable(afe, id);
+		if (ret) {
+			dev_warn(afe->dev,
+				 "id %d, memif disable fail\n", id);
+		}
+
+		/* disable interrupt */
+		regmap_update_bits(afe->regmap,
+				   irq_data->irq_en_reg,
+				   1 << irq_data->irq_en_shift,
+				   0 << irq_data->irq_en_shift);
+
+		/* clear pending IRQ */
+		regmap_read(afe->regmap, irq_data->irq_clr_reg, &tmp_reg);
+		regmap_update_bits(afe->regmap, irq_data->irq_clr_reg,
+				   AFE_IRQ_CLR_CFG_MASK_SFT | AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT,
+				   tmp_reg ^ (AFE_IRQ_CLR_CFG_MASK_SFT |
+				   AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT));
+
+		return ret;
+	default:
+		return -EINVAL;
+	}
+}
+
+static int mt8196_memif_fs(struct snd_pcm_substream *substream,
+			   unsigned int rate)
+{
+	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+	struct snd_soc_component *component =
+		snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
+	struct mtk_base_afe *afe = NULL;
+	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+	int id = cpu_dai->id;
+	unsigned int rate_reg = 0;
+	int cm = 0;
+
+	if (!component)
+		return -EINVAL;
+
+	afe = snd_soc_component_get_drvdata(component);
+
+	if (!afe)
+		return -EINVAL;
+
+	rate_reg = mt8196_rate_transform(afe->dev, rate);
+
+	switch (id) {
+	case MT8196_MEMIF_VUL8:
+	case MT8196_MEMIF_VUL_CM0:
+		cm = CM0;
+		break;
+	case MT8196_MEMIF_VUL9:
+	case MT8196_MEMIF_VUL_CM1:
+		cm = CM1;
+		break;
+	case MT8196_MEMIF_VUL10:
+	case MT8196_MEMIF_VUL_CM2:
+		cm = CM2;
+		break;
+	default:
+		cm = CM0;
+		break;
+	}
+
+	mt8196_set_cm_rate(afe, cm, rate_reg);
+
+	return rate_reg;
+}
+
+static int mt8196_get_dai_fs(struct mtk_base_afe *afe,
+			     int dai_id, unsigned int rate)
+{
+	return mt8196_rate_transform(afe->dev, rate);
+}
+
+static int mt8196_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
+{
+	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+	struct snd_soc_component *component =
+		snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
+	struct mtk_base_afe *afe = NULL;
+
+	if (!component)
+		return -EINVAL;
+	afe = snd_soc_component_get_drvdata(component);
+	return mt8196_rate_transform(afe->dev, rate);
+}
+
+static int mt8196_get_memif_pbuf_size(struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+
+	if ((runtime->period_size * 1000) / runtime->rate > 10)
+		return MT8196_MEMIF_PBUF_SIZE_256_BYTES;
+	else
+		return MT8196_MEMIF_PBUF_SIZE_32_BYTES;
+}
+
+/* FE DAIs */
+static const struct snd_soc_dai_ops mt8196_memif_dai_ops = {
+	.startup        = mt8196_fe_startup,
+	.shutdown       = mt8196_fe_shutdown,
+	.hw_params      = mt8196_fe_hw_params,
+	.hw_free        = mtk_afe_fe_hw_free,
+	.prepare        = mtk_afe_fe_prepare,
+	.trigger        = mt8196_fe_trigger,
+};
+
+#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
+		       SNDRV_PCM_RATE_88200 |\
+		       SNDRV_PCM_RATE_96000 |\
+		       SNDRV_PCM_RATE_176400 |\
+		       SNDRV_PCM_RATE_192000)
+
+#define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
+			   SNDRV_PCM_RATE_16000 |\
+			   SNDRV_PCM_RATE_32000 |\
+			   SNDRV_PCM_RATE_48000)
+
+#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+			 SNDRV_PCM_FMTBIT_S24_LE |\
+			 SNDRV_PCM_FMTBIT_S32_LE)
+
+#define MT8196_FE_DAI_PLAYBACK(_name, _id, max_ch) \
+{ \
+	.name = #_name, \
+	.id = _id, \
+	.playback = { \
+		.stream_name = #_name, \
+		.channels_min = 1, \
+		.channels_max = max_ch, \
+		.rates = MTK_PCM_RATES, \
+		.formats = MTK_PCM_FORMATS, \
+	}, \
+	.ops = &mt8196_memif_dai_ops, \
+}
+
+#define MT8196_FE_DAI_CAPTURE(_name, _id, max_ch) \
+{ \
+	.name = #_name, \
+	.id = _id, \
+	.capture = { \
+		.stream_name = #_name, \
+		.channels_min = 1, \
+		.channels_max = max_ch, \
+		.rates = MTK_PCM_RATES, \
+		.formats = MTK_PCM_FORMATS, \
+	}, \
+	.ops = &mt8196_memif_dai_ops, \
+}
+
+static struct snd_soc_dai_driver mt8196_memif_dai_driver[] = {
+	/* FE DAIs: memory intefaces to CPU */
+	/* Playback */
+	MT8196_FE_DAI_PLAYBACK(DL0, MT8196_MEMIF_DL0, 2),
+	MT8196_FE_DAI_PLAYBACK(DL1, MT8196_MEMIF_DL1, 2),
+	MT8196_FE_DAI_PLAYBACK(DL2, MT8196_MEMIF_DL2, 2),
+	MT8196_FE_DAI_PLAYBACK(DL3, MT8196_MEMIF_DL3, 2),
+	MT8196_FE_DAI_PLAYBACK(DL4, MT8196_MEMIF_DL4, 2),
+	MT8196_FE_DAI_PLAYBACK(DL5, MT8196_MEMIF_DL5, 2),
+	MT8196_FE_DAI_PLAYBACK(DL6, MT8196_MEMIF_DL6, 2),
+	MT8196_FE_DAI_PLAYBACK(DL7, MT8196_MEMIF_DL7, 2),
+	MT8196_FE_DAI_PLAYBACK(DL8, MT8196_MEMIF_DL8, 2),
+	MT8196_FE_DAI_PLAYBACK(DL23, MT8196_MEMIF_DL23, 2),
+	MT8196_FE_DAI_PLAYBACK(DL24, MT8196_MEMIF_DL24, 2),
+	MT8196_FE_DAI_PLAYBACK(DL25, MT8196_MEMIF_DL25, 2),
+	MT8196_FE_DAI_PLAYBACK(DL26, MT8196_MEMIF_DL26, 2),
+	MT8196_FE_DAI_PLAYBACK(DL_4CH, MT8196_MEMIF_DL_4CH, 4),
+	MT8196_FE_DAI_PLAYBACK(DL_24CH, MT8196_MEMIF_DL_24CH, 8),
+	MT8196_FE_DAI_PLAYBACK(HDMI, MT8196_MEMIF_HDMI, 8),
+	/* Capture */
+	MT8196_FE_DAI_CAPTURE(UL0, MT8196_MEMIF_VUL0, 2),
+	MT8196_FE_DAI_CAPTURE(UL1, MT8196_MEMIF_VUL1, 2),
+	MT8196_FE_DAI_CAPTURE(UL2, MT8196_MEMIF_VUL2, 2),
+	MT8196_FE_DAI_CAPTURE(UL3, MT8196_MEMIF_VUL3, 2),
+	MT8196_FE_DAI_CAPTURE(UL4, MT8196_MEMIF_VUL4, 2),
+	MT8196_FE_DAI_CAPTURE(UL5, MT8196_MEMIF_VUL5, 2),
+	MT8196_FE_DAI_CAPTURE(UL6, MT8196_MEMIF_VUL6, 2),
+	MT8196_FE_DAI_CAPTURE(UL7, MT8196_MEMIF_VUL7, 2),
+	MT8196_FE_DAI_CAPTURE(UL8, MT8196_MEMIF_VUL8, 2),
+	MT8196_FE_DAI_CAPTURE(UL9, MT8196_MEMIF_VUL9, 16),
+	MT8196_FE_DAI_CAPTURE(UL10, MT8196_MEMIF_VUL10, 2),
+	MT8196_FE_DAI_CAPTURE(UL24, MT8196_MEMIF_VUL24, 2),
+	MT8196_FE_DAI_CAPTURE(UL25, MT8196_MEMIF_VUL25, 2),
+	MT8196_FE_DAI_CAPTURE(UL26, MT8196_MEMIF_VUL26, 2),
+	MT8196_FE_DAI_CAPTURE(UL_CM0, MT8196_MEMIF_VUL_CM0, 8),
+	MT8196_FE_DAI_CAPTURE(UL_CM1, MT8196_MEMIF_VUL_CM1, 16),
+	MT8196_FE_DAI_CAPTURE(UL_CM2, MT8196_MEMIF_VUL_CM2, 32),
+	MT8196_FE_DAI_CAPTURE(UL_ETDM_IN0, MT8196_MEMIF_ETDM_IN0, 2),
+	MT8196_FE_DAI_CAPTURE(UL_ETDM_IN1, MT8196_MEMIF_ETDM_IN1, 2),
+	MT8196_FE_DAI_CAPTURE(UL_ETDM_IN2, MT8196_MEMIF_ETDM_IN2, 2),
+	MT8196_FE_DAI_CAPTURE(UL_ETDM_IN3, MT8196_MEMIF_ETDM_IN3, 2),
+	MT8196_FE_DAI_CAPTURE(UL_ETDM_IN4, MT8196_MEMIF_ETDM_IN4, 2),
+	MT8196_FE_DAI_CAPTURE(UL_ETDM_IN6, MT8196_MEMIF_ETDM_IN6, 2),
+};
+
+static const struct snd_kcontrol_new mt8196_pcm_kcontrols[] = {
+};
+
+enum {
+	CM0_MUX_VUL8_2CH,
+	CM0_MUX_VUL8_8CH,
+	CM0_MUX_MASK,
+};
+
+enum {
+	CM1_MUX_VUL9_2CH,
+	CM1_MUX_VUL9_16CH,
+	CM1_MUX_MASK,
+};
+
+enum {
+	CM2_MUX_VUL10_2CH,
+	CM2_MUX_VUL10_32CH,
+	CM2_MUX_MASK,
+};
+
+static int ul_cm0_event(struct snd_soc_dapm_widget *w,
+			struct snd_kcontrol *kcontrol,
+			int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	unsigned int channels = afe_priv->cm_channels;
+
+	dev_dbg(afe->dev, "event 0x%x, name %s, channels %u\n",
+		event, w->name, channels);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		mt8196_enable_cm_bypass(afe, CM0, 0x0);
+		mt8196_set_cm(afe, CM0, true, false, channels);
+		mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_CM0]);
+		break;
+	case SND_SOC_DAPM_PRE_PMD:
+		mt8196_enable_cm_bypass(afe, CM0, 0x1);
+		mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_CM0]);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int ul_cm1_event(struct snd_soc_dapm_widget *w,
+			struct snd_kcontrol *kcontrol,
+			int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	unsigned int channels = afe_priv->cm_channels;
+
+	dev_dbg(afe->dev, "event 0x%x, name %s, channels %u\n",
+		event, w->name, channels);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		mt8196_enable_cm_bypass(afe, CM1, 0x0);
+		mt8196_set_cm(afe, CM1, true, false, channels);
+		mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_CM1]);
+		break;
+	case SND_SOC_DAPM_PRE_PMD:
+		mt8196_enable_cm_bypass(afe, CM1, 0x1);
+		mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_CM1]);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int ul_cm2_event(struct snd_soc_dapm_widget *w,
+			struct snd_kcontrol *kcontrol,
+			int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mt8196_afe_private *afe_priv = afe->platform_priv;
+	unsigned int channels = afe_priv->cm_channels;
+
+	dev_dbg(afe->dev, "event 0x%x, name %s, channels %u\n",
+		event, w->name, channels);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		mt8196_enable_cm_bypass(afe, CM2, 0x0);
+		mt8196_set_cm(afe, CM2, true, false, channels);
+		mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_CM2]);
+		break;
+	case SND_SOC_DAPM_PRE_PMD:
+		mt8196_enable_cm_bypass(afe, CM2, 0x1);
+		mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_CM2]);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+/* dma widget & routes*/
+static const struct snd_kcontrol_new memif_ul0_ch1_mix[] = {
+	/* Normal record */
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN018_0,
+				    I_ADDA_UL_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul0_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN019_0,
+				    I_ADDA_UL_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN4_CH1", AFE_CONN020_4,
+				    I_I2SIN4_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH1", AFE_CONN020_5,
+				    I_I2SIN6_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN4_CH2", AFE_CONN021_4,
+				    I_I2SIN4_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH2", AFE_CONN021_5,
+				    I_I2SIN6_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN022_0,
+				    I_ADDA_UL_CH3, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN023_0,
+				    I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN024_4,
+				    I_I2SIN0_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH1", AFE_CONN024_4,
+				    I_I2SIN1_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN3_CH1", AFE_CONN024_4,
+				    I_I2SIN3_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN4_CH1", AFE_CONN024_4,
+				    I_I2SIN4_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN025_4,
+				    I_I2SIN0_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH2", AFE_CONN025_4,
+				    I_I2SIN1_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN3_CH2", AFE_CONN025_4,
+				    I_I2SIN3_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN4_CH2", AFE_CONN025_4,
+				    I_I2SIN4_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN026_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN026_1,
+				    I_DL0_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN026_1,
+				    I_DL1_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN026_1,
+				    I_DL6_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN026_1,
+				    I_DL2_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN026_1,
+				    I_DL3_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN026_1,
+				    I_DL_24CH_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN026_4,
+				    I_I2SIN0_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN027_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN027_1,
+				    I_DL0_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN027_1,
+				    I_DL1_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN027_1,
+				    I_DL6_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN027_1,
+				    I_DL2_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN027_1,
+				    I_DL3_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN027_1,
+				    I_DL_24CH_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN027_4,
+				    I_I2SIN0_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul5_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN3_CH1", AFE_CONN028_4,
+				    I_I2SIN3_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul5_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN3_CH2", AFE_CONN029_4,
+				    I_I2SIN3_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul6_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN030_0,
+				    I_ADDA_UL_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul6_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN031_0,
+				    I_ADDA_UL_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul7_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN032_0,
+				    I_ADDA_UL_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul7_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN033_0,
+				    I_ADDA_UL_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul8_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN034_0,
+				    I_ADDA_UL_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul8_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN035_0,
+				    I_ADDA_UL_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul9_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN036_0,
+				    I_ADDA_UL_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul9_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN037_0,
+				    I_ADDA_UL_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul10_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN038_0,
+				    I_ADDA_UL_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul10_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN039_0,
+				    I_ADDA_UL_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul24_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN066_4,
+				    I_I2SIN0_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH1", AFE_CONN066_5,
+				    I_I2SIN6_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul24_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN067_4,
+				    I_I2SIN0_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH2", AFE_CONN067_5,
+				    I_I2SIN6_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul25_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN068_4,
+				    I_I2SIN0_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH1", AFE_CONN068_5,
+				    I_I2SIN6_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul25_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN069_4,
+				    I_I2SIN0_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH2", AFE_CONN069_5,
+				    I_I2SIN6_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul26_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN070_4,
+				    I_I2SIN0_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH1", AFE_CONN070_5,
+				    I_I2SIN6_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul26_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN071_4,
+				    I_I2SIN0_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH2", AFE_CONN071_5,
+				    I_I2SIN6_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN040_0,
+				    I_ADDA_UL_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN041_0,
+				    I_ADDA_UL_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch3_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN042_0,
+				    I_ADDA_UL_CH3, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch4_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN043_0,
+				    I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch5_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN044_0,
+				    I_ADDA_UL_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch6_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN045_0,
+				    I_ADDA_UL_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch7_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN046_0,
+				    I_ADDA_UL_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch8_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN047_0,
+				    I_ADDA_UL_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN048_0,
+				    I_ADDA_UL_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN049_0,
+				    I_ADDA_UL_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch3_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN050_0,
+				    I_ADDA_UL_CH3, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch4_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN051_0,
+				    I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch5_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN052_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN052_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN052_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN052_0,
+				    I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch6_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN053_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN053_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN053_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN053_0,
+				    I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch7_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN054_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN054_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN054_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN054_0,
+				    I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch8_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN055_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN055_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN055_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN055_0,
+				    I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch9_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN056_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN056_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN056_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN056_0,
+				    I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch10_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN057_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN057_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN057_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN057_0,
+				    I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch11_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN058_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN058_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN058_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN058_0,
+				    I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch12_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN059_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN059_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN059_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN059_0,
+				    I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch13_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN060_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN060_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN060_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN060_0,
+				    I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch14_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN061_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN061_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN061_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN061_0,
+				    I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch15_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN062_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN062_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN062_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN062_0,
+				    I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch16_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN063_0,
+				    I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN063_0,
+				    I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN063_0,
+				    I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN063_0,
+				    I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch1_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN064_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN064_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN064_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN064_0, I_ADDA_UL_CH4, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN064_0, I_ADDA_UL_CH5, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN064_0, I_ADDA_UL_CH6, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch2_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN065_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN065_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN065_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN065_0, I_ADDA_UL_CH4, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN065_0, I_ADDA_UL_CH5, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN065_0, I_ADDA_UL_CH6, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch3_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN066_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN066_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN066_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN066_0, I_ADDA_UL_CH4, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN066_0, I_ADDA_UL_CH5, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN066_0, I_ADDA_UL_CH6, 1, 0)
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch4_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN067_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN067_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN067_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN067_0, I_ADDA_UL_CH4, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN067_0, I_ADDA_UL_CH5, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN067_0, I_ADDA_UL_CH6, 1, 0)
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch5_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN068_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN068_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN068_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN068_0, I_ADDA_UL_CH4, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN068_0, I_ADDA_UL_CH5, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN068_0, I_ADDA_UL_CH6, 1, 0)
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch6_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN069_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN069_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN069_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN069_0, I_ADDA_UL_CH4, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN069_0, I_ADDA_UL_CH5, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN069_0, I_ADDA_UL_CH6, 1, 0)
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch7_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN070_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN070_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN070_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN070_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch8_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN071_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN071_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN071_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN071_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch9_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN072_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN072_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN072_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN072_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch10_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN073_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN073_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN073_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN073_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch11_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN074_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN074_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN074_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN074_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch12_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN075_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN075_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN075_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN075_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch13_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN076_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN076_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN076_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN076_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch14_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN077_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN077_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN077_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN077_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch15_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN078_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN078_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN078_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN078_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch16_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN079_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN079_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN079_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN079_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch17_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN080_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN080_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN080_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN080_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch18_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN081_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN081_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN081_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN081_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch19_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN082_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN082_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN082_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN082_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch20_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN083_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN083_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN083_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN083_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch21_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN084_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN084_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN084_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN084_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch22_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN085_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN085_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN085_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN085_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch23_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN086_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN086_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN086_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN086_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch24_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN087_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN087_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN087_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN087_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch25_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN088_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN088_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN088_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN088_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch26_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN089_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN089_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN089_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN089_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch27_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN090_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN090_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN090_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN090_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch28_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN091_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN091_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN091_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN091_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch29_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN092_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN092_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN092_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN092_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch30_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN093_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN093_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN093_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN093_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch31_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN094_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN094_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN094_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN094_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm2_ch32_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN095_0, I_ADDA_UL_CH1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN095_0, I_ADDA_UL_CH2, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN095_0, I_ADDA_UL_CH3, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN095_0, I_ADDA_UL_CH4, 1, 0),
+};
+
+static const char * const cm0_mux_map[] = {
+	"CM0_8CH_PATH",
+	"UL8_2CH_PATH",
+};
+
+static const char * const cm1_mux_map[] = {
+	"CM1_16CH_PATH",
+	"UL9_2CH_PATH",
+};
+
+static const char * const cm2_mux_map[] = {
+	"CM2_32CH_PATH",
+	"UL10_2CH_PATH",
+};
+
+static int cm0_mux_map_value[] = {
+	CM0_MUX_VUL8_8CH,
+	CM0_MUX_VUL8_2CH,
+};
+
+static int cm1_mux_map_value[] = {
+	CM1_MUX_VUL9_16CH,
+	CM1_MUX_VUL9_2CH,
+};
+
+static int cm2_mux_map_value[] = {
+	CM2_MUX_VUL10_32CH,
+	CM2_MUX_VUL10_2CH,
+};
+
+static SOC_VALUE_ENUM_SINGLE_DECL(ul_cm0_mux_map_enum,
+				  AFE_CM0_CON0,
+				  AFE_CM0_OUTPUT_MUX_SFT,
+				  AFE_CM0_OUTPUT_MUX_MASK,
+				  cm0_mux_map,
+				  cm0_mux_map_value);
+static SOC_VALUE_ENUM_SINGLE_DECL(ul_cm1_mux_map_enum,
+				  AFE_CM1_CON0,
+				  AFE_CM1_OUTPUT_MUX_SFT,
+				  AFE_CM1_OUTPUT_MUX_MASK,
+				  cm1_mux_map,
+				  cm1_mux_map_value);
+static SOC_VALUE_ENUM_SINGLE_DECL(ul_cm2_mux_map_enum,
+				  AFE_CM2_CON0,
+				  AFE_CM2_OUTPUT_MUX_SFT,
+				  AFE_CM2_OUTPUT_MUX_MASK,
+				  cm2_mux_map,
+				  cm2_mux_map_value);
+
+static const struct snd_kcontrol_new ul_cm0_mux_control =
+	SOC_DAPM_ENUM("CM0_UL_MUX Route", ul_cm0_mux_map_enum);
+
+static const struct snd_kcontrol_new ul_cm1_mux_control =
+	SOC_DAPM_ENUM("CM1_UL_MUX Route", ul_cm1_mux_map_enum);
+
+static const struct snd_kcontrol_new ul_cm2_mux_control =
+	SOC_DAPM_ENUM("CM2_UL_MUX Route", ul_cm2_mux_map_enum);
+
+static const struct snd_soc_dapm_widget mt8196_memif_widgets[] = {
+	/* inter-connections */
+	SND_SOC_DAPM_MIXER("UL0_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul0_ch1_mix, ARRAY_SIZE(memif_ul0_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL0_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul0_ch2_mix, ARRAY_SIZE(memif_ul0_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("UL5_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul5_ch1_mix, ARRAY_SIZE(memif_ul5_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL5_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul5_ch2_mix, ARRAY_SIZE(memif_ul5_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("UL6_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul6_ch1_mix, ARRAY_SIZE(memif_ul6_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL6_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul6_ch2_mix, ARRAY_SIZE(memif_ul6_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("UL7_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul7_ch1_mix, ARRAY_SIZE(memif_ul7_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL7_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul7_ch2_mix, ARRAY_SIZE(memif_ul7_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("UL8_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul8_ch1_mix, ARRAY_SIZE(memif_ul8_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL8_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul8_ch2_mix, ARRAY_SIZE(memif_ul8_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("UL9_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul9_ch1_mix, ARRAY_SIZE(memif_ul9_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL9_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul9_ch2_mix, ARRAY_SIZE(memif_ul9_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("UL10_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul10_ch1_mix, ARRAY_SIZE(memif_ul10_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL10_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul10_ch2_mix, ARRAY_SIZE(memif_ul10_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("UL24_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul24_ch1_mix, ARRAY_SIZE(memif_ul24_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL24_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul24_ch2_mix, ARRAY_SIZE(memif_ul24_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("UL25_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul25_ch1_mix, ARRAY_SIZE(memif_ul25_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL25_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul25_ch2_mix, ARRAY_SIZE(memif_ul25_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("UL26_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul26_ch1_mix, ARRAY_SIZE(memif_ul26_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL26_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul26_ch2_mix, ARRAY_SIZE(memif_ul26_ch2_mix)),
+
+	SND_SOC_DAPM_MIXER("UL_CM0_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm0_ch1_mix, ARRAY_SIZE(memif_ul_cm0_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM0_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm0_ch2_mix, ARRAY_SIZE(memif_ul_cm0_ch2_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM0_CH3", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm0_ch3_mix, ARRAY_SIZE(memif_ul_cm0_ch3_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM0_CH4", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm0_ch4_mix, ARRAY_SIZE(memif_ul_cm0_ch4_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM0_CH5", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm0_ch5_mix, ARRAY_SIZE(memif_ul_cm0_ch5_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM0_CH6", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm0_ch6_mix, ARRAY_SIZE(memif_ul_cm0_ch6_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM0_CH7", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm0_ch7_mix, ARRAY_SIZE(memif_ul_cm0_ch7_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM0_CH8", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm0_ch8_mix, ARRAY_SIZE(memif_ul_cm0_ch8_mix)),
+	SND_SOC_DAPM_MUX("CM0_UL_MUX", SND_SOC_NOPM, 0, 0,
+			 &ul_cm0_mux_control),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch1_mix, ARRAY_SIZE(memif_ul_cm1_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch2_mix, ARRAY_SIZE(memif_ul_cm1_ch2_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH3", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch3_mix, ARRAY_SIZE(memif_ul_cm1_ch3_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH4", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch4_mix, ARRAY_SIZE(memif_ul_cm1_ch4_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH5", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch5_mix, ARRAY_SIZE(memif_ul_cm1_ch5_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH6", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch6_mix, ARRAY_SIZE(memif_ul_cm1_ch6_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH7", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch7_mix, ARRAY_SIZE(memif_ul_cm1_ch7_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH8", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch8_mix, ARRAY_SIZE(memif_ul_cm1_ch8_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH9", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch9_mix, ARRAY_SIZE(memif_ul_cm1_ch9_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH10", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch10_mix, ARRAY_SIZE(memif_ul_cm1_ch10_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH11", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch11_mix, ARRAY_SIZE(memif_ul_cm1_ch11_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH12", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch12_mix, ARRAY_SIZE(memif_ul_cm1_ch12_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH13", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch13_mix, ARRAY_SIZE(memif_ul_cm1_ch13_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH14", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch14_mix, ARRAY_SIZE(memif_ul_cm1_ch14_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH15", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch15_mix, ARRAY_SIZE(memif_ul_cm1_ch15_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM1_CH16", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm1_ch16_mix, ARRAY_SIZE(memif_ul_cm1_ch16_mix)),
+	SND_SOC_DAPM_MUX("CM1_UL_MUX", SND_SOC_NOPM, 0, 0,
+			 &ul_cm1_mux_control),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH1", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch1_mix, ARRAY_SIZE(memif_ul_cm2_ch1_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH2", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch2_mix, ARRAY_SIZE(memif_ul_cm2_ch2_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH3", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch3_mix, ARRAY_SIZE(memif_ul_cm2_ch3_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH4", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch4_mix, ARRAY_SIZE(memif_ul_cm2_ch4_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH5", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch5_mix, ARRAY_SIZE(memif_ul_cm2_ch5_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH6", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch6_mix, ARRAY_SIZE(memif_ul_cm2_ch6_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH7", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch7_mix, ARRAY_SIZE(memif_ul_cm2_ch7_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH8", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch8_mix, ARRAY_SIZE(memif_ul_cm2_ch8_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH9", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch9_mix, ARRAY_SIZE(memif_ul_cm2_ch9_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH10", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch10_mix, ARRAY_SIZE(memif_ul_cm2_ch10_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH11", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch11_mix, ARRAY_SIZE(memif_ul_cm2_ch11_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH12", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch12_mix, ARRAY_SIZE(memif_ul_cm2_ch12_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH13", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch13_mix, ARRAY_SIZE(memif_ul_cm2_ch13_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH14", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch14_mix, ARRAY_SIZE(memif_ul_cm2_ch14_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH15", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch15_mix, ARRAY_SIZE(memif_ul_cm2_ch15_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH16", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch16_mix, ARRAY_SIZE(memif_ul_cm2_ch16_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH17", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch17_mix, ARRAY_SIZE(memif_ul_cm2_ch17_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH18", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch18_mix, ARRAY_SIZE(memif_ul_cm2_ch18_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH19", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch19_mix, ARRAY_SIZE(memif_ul_cm2_ch19_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH20", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch20_mix, ARRAY_SIZE(memif_ul_cm2_ch20_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH21", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch21_mix, ARRAY_SIZE(memif_ul_cm2_ch21_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH22", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch22_mix, ARRAY_SIZE(memif_ul_cm2_ch22_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH23", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch23_mix, ARRAY_SIZE(memif_ul_cm2_ch23_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH24", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch24_mix, ARRAY_SIZE(memif_ul_cm2_ch24_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH25", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch25_mix, ARRAY_SIZE(memif_ul_cm2_ch25_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH26", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch26_mix, ARRAY_SIZE(memif_ul_cm2_ch26_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH27", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch27_mix, ARRAY_SIZE(memif_ul_cm2_ch27_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH28", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch28_mix, ARRAY_SIZE(memif_ul_cm2_ch28_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH29", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch29_mix, ARRAY_SIZE(memif_ul_cm2_ch29_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH30", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch30_mix, ARRAY_SIZE(memif_ul_cm2_ch30_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH31", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch31_mix, ARRAY_SIZE(memif_ul_cm2_ch31_mix)),
+	SND_SOC_DAPM_MIXER("UL_CM2_CH32", SND_SOC_NOPM, 0, 0,
+			   memif_ul_cm2_ch32_mix, ARRAY_SIZE(memif_ul_cm2_ch32_mix)),
+	SND_SOC_DAPM_MUX("CM2_UL_MUX", SND_SOC_NOPM, 0, 0,
+			 &ul_cm2_mux_control),
+
+	SND_SOC_DAPM_SUPPLY("CM0_Enable",
+			    AFE_CM0_CON0, AFE_CM0_ON_SFT, 0,
+			    ul_cm0_event,
+			    SND_SOC_DAPM_PRE_PMU |
+			    SND_SOC_DAPM_PRE_PMD),
+
+	SND_SOC_DAPM_SUPPLY("CM1_Enable",
+			    AFE_CM1_CON0, AFE_CM1_ON_SFT, 0,
+			    ul_cm1_event,
+			    SND_SOC_DAPM_PRE_PMU |
+			    SND_SOC_DAPM_PRE_PMD),
+
+	SND_SOC_DAPM_SUPPLY("CM2_Enable",
+			    AFE_CM2_CON0, AFE_CM2_ON_SFT, 0,
+			    ul_cm2_event,
+			    SND_SOC_DAPM_PRE_PMU |
+			    SND_SOC_DAPM_PRE_PMD),
+
+	SND_SOC_DAPM_MIXER("SOF_DMA_UL0", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_MIXER("SOF_DMA_UL1", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_MIXER("SOF_DMA_UL2", SND_SOC_NOPM, 0, 0, NULL, 0),
+};
+
+static const struct snd_soc_dapm_route mt8196_memif_routes[] = {
+	{"UL0", NULL, "UL0_CH1"},
+	{"UL0", NULL, "UL0_CH2"},
+	/* Normal record */
+	{"UL0_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
+	{"UL0_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
+	/* SOF Uplink */
+	{"SOF_DMA_UL0", NULL, "UL0_CH1"},
+	{"SOF_DMA_UL0", NULL, "UL0_CH2"},
+
+	{"UL1", NULL, "UL1_CH1"},
+	{"UL1", NULL, "UL1_CH2"},
+	{"UL1_CH1", "I2SIN4_CH1", "I2SIN4"},
+	{"UL1_CH2", "I2SIN4_CH2", "I2SIN4"},
+	{"UL1_CH1", "I2SIN6_CH1", "I2SIN6"},
+	{"UL1_CH2", "I2SIN6_CH2", "I2SIN6"},
+	/* SOF Uplink */
+	{"SOF_DMA_UL1", NULL, "UL1_CH1"},
+	{"SOF_DMA_UL1", NULL, "UL1_CH2"},
+
+	{"UL2", NULL, "UL2_CH1"},
+	{"UL2", NULL, "UL2_CH2"},
+	{"UL2_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
+	{"UL2_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
+	/* SOF Uplink */
+	{"SOF_DMA_UL2", NULL, "UL2_CH1"},
+	{"SOF_DMA_UL2", NULL, "UL2_CH2"},
+
+	{"UL3", NULL, "UL3_CH1"},
+	{"UL3", NULL, "UL3_CH2"},
+	{"UL3_CH1", "I2SIN0_CH1", "I2SIN0"},
+	{"UL3_CH2", "I2SIN0_CH2", "I2SIN0"},
+	{"UL3_CH1", "I2SIN1_CH1", "I2SIN1"},
+	{"UL3_CH2", "I2SIN1_CH2", "I2SIN1"},
+	{"UL3_CH1", "I2SIN3_CH1", "I2SIN3"},
+	{"UL3_CH2", "I2SIN3_CH2", "I2SIN3"},
+	{"UL3_CH1", "I2SIN4_CH1", "I2SIN4"},
+	{"UL3_CH2", "I2SIN4_CH2", "I2SIN4"},
+
+	{"UL4", NULL, "UL4_CH1"},
+	{"UL4", NULL, "UL4_CH2"},
+	{"UL4_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
+	{"UL4_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
+	{"UL4_CH1", "I2SIN0_CH1", "I2SIN0"},
+	{"UL4_CH2", "I2SIN0_CH2", "I2SIN0"},
+
+	{"UL5", NULL, "UL5_CH1"},
+	{"UL5", NULL, "UL5_CH2"},
+	{"UL5_CH1", "I2SIN3_CH1", "I2SIN3"},
+	{"UL5_CH2", "I2SIN3_CH2", "I2SIN3"},
+
+	{"UL6", NULL, "UL6_CH1"},
+	{"UL6", NULL, "UL6_CH2"},
+	{"UL6_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
+	{"UL6_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
+
+	{"UL7", NULL, "UL7_CH1"},
+	{"UL7", NULL, "UL7_CH2"},
+	{"UL7_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
+	{"UL7_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
+
+	{"UL8", NULL, "CM0_UL_MUX"},
+	{"CM0_UL_MUX", "UL8_2CH_PATH", "UL8_CH1"},
+	{"CM0_UL_MUX", "UL8_2CH_PATH", "UL8_CH2"},
+	{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH1"},
+	{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH2"},
+	{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH3"},
+	{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH4"},
+	{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH5"},
+	{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH6"},
+	{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH7"},
+	{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH8"},
+	{"UL_CM0_CH1", NULL, "CM0_Enable"},
+	{"UL_CM0_CH2", NULL, "CM0_Enable"},
+	{"UL_CM0_CH3", NULL, "CM0_Enable"},
+	{"UL_CM0_CH4", NULL, "CM0_Enable"},
+	{"UL_CM0_CH5", NULL, "CM0_Enable"},
+	{"UL_CM0_CH6", NULL, "CM0_Enable"},
+	{"UL_CM0_CH7", NULL, "CM0_Enable"},
+	{"UL_CM0_CH8", NULL, "CM0_Enable"},
+
+	/* UL9 */
+	{"UL9", NULL, "CM1_UL_MUX"},
+	{"CM1_UL_MUX", "UL9_2CH_PATH", "UL9_CH1"},
+	{"CM1_UL_MUX", "UL9_2CH_PATH", "UL9_CH2"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH1"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH2"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH3"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH4"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH5"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH6"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH7"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH8"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH9"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH10"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH11"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH12"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH13"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH14"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH15"},
+	{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH16"},
+	{"UL_CM1_CH1", NULL, "CM1_Enable"},
+	{"UL_CM1_CH2", NULL, "CM1_Enable"},
+	{"UL_CM1_CH3", NULL, "CM1_Enable"},
+	{"UL_CM1_CH4", NULL, "CM1_Enable"},
+	{"UL_CM1_CH5", NULL, "CM1_Enable"},
+	{"UL_CM1_CH6", NULL, "CM1_Enable"},
+	{"UL_CM1_CH7", NULL, "CM1_Enable"},
+	{"UL_CM1_CH8", NULL, "CM1_Enable"},
+	{"UL_CM1_CH9", NULL, "CM1_Enable"},
+	{"UL_CM1_CH10", NULL, "CM1_Enable"},
+	{"UL_CM1_CH11", NULL, "CM1_Enable"},
+	{"UL_CM1_CH12", NULL, "CM1_Enable"},
+	{"UL_CM1_CH13", NULL, "CM1_Enable"},
+	{"UL_CM1_CH14", NULL, "CM1_Enable"},
+	{"UL_CM1_CH15", NULL, "CM1_Enable"},
+	{"UL_CM1_CH16", NULL, "CM1_Enable"},
+	{"UL9_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
+	{"UL9_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
+
+	{"UL10", NULL, "CM2_UL_MUX"},
+	{"CM2_UL_MUX", "UL10_2CH_PATH", "UL10_CH1"},
+	{"CM2_UL_MUX", "UL10_2CH_PATH", "UL10_CH2"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH1"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH2"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH3"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH4"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH5"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH6"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH7"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH8"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH9"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH10"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH11"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH12"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH13"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH14"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH15"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH16"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH17"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH18"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH19"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH20"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH21"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH22"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH23"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH24"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH25"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH26"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH27"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH28"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH29"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH30"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH31"},
+	{"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH32"},
+	{"UL_CM2_CH1", NULL, "CM2_Enable"},
+	{"UL_CM2_CH2", NULL, "CM2_Enable"},
+	{"UL_CM2_CH3", NULL, "CM2_Enable"},
+	{"UL_CM2_CH4", NULL, "CM2_Enable"},
+	{"UL_CM2_CH5", NULL, "CM2_Enable"},
+	{"UL_CM2_CH6", NULL, "CM2_Enable"},
+	{"UL_CM2_CH7", NULL, "CM2_Enable"},
+	{"UL_CM2_CH8", NULL, "CM2_Enable"},
+	{"UL_CM2_CH9", NULL, "CM2_Enable"},
+	{"UL_CM2_CH10", NULL, "CM2_Enable"},
+	{"UL_CM2_CH11", NULL, "CM2_Enable"},
+	{"UL_CM2_CH12", NULL, "CM2_Enable"},
+	{"UL_CM2_CH13", NULL, "CM2_Enable"},
+	{"UL_CM2_CH14", NULL, "CM2_Enable"},
+	{"UL_CM2_CH15", NULL, "CM2_Enable"},
+	{"UL_CM2_CH16", NULL, "CM2_Enable"},
+	{"UL_CM2_CH17", NULL, "CM2_Enable"},
+	{"UL_CM2_CH18", NULL, "CM2_Enable"},
+	{"UL_CM2_CH19", NULL, "CM2_Enable"},
+	{"UL_CM2_CH20", NULL, "CM2_Enable"},
+	{"UL_CM2_CH21", NULL, "CM2_Enable"},
+	{"UL_CM2_CH22", NULL, "CM2_Enable"},
+	{"UL_CM2_CH23", NULL, "CM2_Enable"},
+	{"UL_CM2_CH24", NULL, "CM2_Enable"},
+	{"UL_CM2_CH25", NULL, "CM2_Enable"},
+	{"UL_CM2_CH26", NULL, "CM2_Enable"},
+	{"UL_CM2_CH27", NULL, "CM2_Enable"},
+	{"UL_CM2_CH28", NULL, "CM2_Enable"},
+	{"UL_CM2_CH29", NULL, "CM2_Enable"},
+	{"UL_CM2_CH30", NULL, "CM2_Enable"},
+	{"UL_CM2_CH31", NULL, "CM2_Enable"},
+	{"UL_CM2_CH32", NULL, "CM2_Enable"},
+	{"UL10_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
+	{"UL10_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
+
+	{"UL24", NULL, "UL24_CH1"},
+	{"UL24", NULL, "UL24_CH2"},
+	{"UL24_CH1", "I2SIN6_CH1", "I2SIN6"},
+	{"UL24_CH2", "I2SIN6_CH2", "I2SIN6"},
+	{"UL24_CH1", "I2SIN0_CH1", "I2SIN0"},
+	{"UL24_CH2", "I2SIN0_CH2", "I2SIN0"},
+
+	{"UL25", NULL, "UL25_CH1"},
+	{"UL25", NULL, "UL25_CH2"},
+	{"UL25_CH1", "I2SIN6_CH1", "I2SIN6"},
+	{"UL25_CH2", "I2SIN6_CH2", "I2SIN6"},
+	{"UL25_CH1", "I2SIN0_CH1", "I2SIN0"},
+	{"UL25_CH2", "I2SIN0_CH2", "I2SIN0"},
+
+	{"UL26", NULL, "UL26_CH1"},
+	{"UL26", NULL, "UL26_CH2"},
+	{"UL26_CH1", "I2SIN6_CH1", "I2SIN6"},
+	{"UL26_CH2", "I2SIN6_CH2", "I2SIN6"},
+	{"UL26_CH1", "I2SIN0_CH1", "I2SIN0"},
+	{"UL26_CH2", "I2SIN0_CH2", "I2SIN0"},
+
+	{"UL_CM0", NULL, "UL_CM0_CH1"},
+	{"UL_CM0", NULL, "UL_CM0_CH2"},
+	{"UL_CM0", NULL, "UL_CM0_CH3"},
+	{"UL_CM0", NULL, "UL_CM0_CH4"},
+	{"UL_CM0", NULL, "UL_CM0_CH5"},
+	{"UL_CM0", NULL, "UL_CM0_CH6"},
+	{"UL_CM0", NULL, "UL_CM0_CH7"},
+	{"UL_CM0", NULL, "UL_CM0_CH8"},
+	{"UL_CM0_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
+	{"UL_CM0_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
+	{"UL_CM0_CH3", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
+	{"UL_CM0_CH4", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
+
+	{"UL_CM1", NULL, "UL_CM1_CH1"},
+	{"UL_CM1", NULL, "UL_CM1_CH2"},
+	{"UL_CM1", NULL, "UL_CM1_CH3"},
+	{"UL_CM1", NULL, "UL_CM1_CH4"},
+	{"UL_CM1", NULL, "UL_CM1_CH5"},
+	{"UL_CM1", NULL, "UL_CM1_CH6"},
+	{"UL_CM1", NULL, "UL_CM1_CH7"},
+	{"UL_CM1", NULL, "UL_CM1_CH8"},
+	{"UL_CM1", NULL, "UL_CM1_CH9"},
+	{"UL_CM1", NULL, "UL_CM1_CH10"},
+	{"UL_CM1", NULL, "UL_CM1_CH11"},
+	{"UL_CM1", NULL, "UL_CM1_CH12"},
+	{"UL_CM1", NULL, "UL_CM1_CH13"},
+	{"UL_CM1", NULL, "UL_CM1_CH14"},
+	{"UL_CM1", NULL, "UL_CM1_CH15"},
+	{"UL_CM1", NULL, "UL_CM1_CH16"},
+	{"UL_CM1_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
+	{"UL_CM1_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
+	{"UL_CM1_CH3", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
+	{"UL_CM1_CH4", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
+
+	{"UL_CM2", NULL, "UL_CM2_CH1"},
+	{"UL_CM2", NULL, "UL_CM2_CH2"},
+	{"UL_CM2", NULL, "UL_CM2_CH3"},
+	{"UL_CM2", NULL, "UL_CM2_CH4"},
+	{"UL_CM2", NULL, "UL_CM2_CH5"},
+	{"UL_CM2", NULL, "UL_CM2_CH6"},
+	{"UL_CM2", NULL, "UL_CM2_CH7"},
+	{"UL_CM2", NULL, "UL_CM2_CH8"},
+	{"UL_CM2", NULL, "UL_CM2_CH9"},
+	{"UL_CM2", NULL, "UL_CM2_CH10"},
+	{"UL_CM2", NULL, "UL_CM2_CH11"},
+	{"UL_CM2", NULL, "UL_CM2_CH12"},
+	{"UL_CM2", NULL, "UL_CM2_CH13"},
+	{"UL_CM2", NULL, "UL_CM2_CH14"},
+	{"UL_CM2", NULL, "UL_CM2_CH15"},
+	{"UL_CM2", NULL, "UL_CM2_CH16"},
+	{"UL_CM2", NULL, "UL_CM2_CH17"},
+	{"UL_CM2", NULL, "UL_CM2_CH18"},
+	{"UL_CM2", NULL, "UL_CM2_CH19"},
+	{"UL_CM2", NULL, "UL_CM2_CH20"},
+	{"UL_CM2", NULL, "UL_CM2_CH21"},
+	{"UL_CM2", NULL, "UL_CM2_CH22"},
+	{"UL_CM2", NULL, "UL_CM2_CH23"},
+	{"UL_CM2", NULL, "UL_CM2_CH24"},
+	{"UL_CM2", NULL, "UL_CM2_CH25"},
+	{"UL_CM2", NULL, "UL_CM2_CH26"},
+	{"UL_CM2", NULL, "UL_CM2_CH27"},
+	{"UL_CM2", NULL, "UL_CM2_CH28"},
+	{"UL_CM2", NULL, "UL_CM2_CH29"},
+	{"UL_CM2", NULL, "UL_CM2_CH30"},
+	{"UL_CM2", NULL, "UL_CM2_CH31"},
+	{"UL_CM2", NULL, "UL_CM2_CH32"},
+	{"UL_CM2_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
+	{"UL_CM2_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
+	{"UL_CM2_CH3", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
+	{"UL_CM2_CH4", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
+};
+
+#define MT8196_DL_MEMIF(_id) \
+	[MT8196_MEMIF_##_id] = { \
+		.name = #_id, \
+		.id = MT8196_MEMIF_##_id, \
+		.reg_ofs_base = AFE_##_id##_BASE, \
+		.reg_ofs_cur = AFE_##_id##_CUR, \
+		.reg_ofs_end = AFE_##_id##_END, \
+		.reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \
+		.reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \
+		.reg_ofs_end_msb = AFE_##_id##_END_MSB, \
+		.fs_reg = AFE_##_id##_CON0, \
+		.fs_shift = _id##_SEL_FS_SFT, \
+		.fs_maskbit = _id##_SEL_FS_MASK, \
+		.mono_reg = AFE_##_id##_CON0, \
+		.mono_shift = _id##_MONO_SFT, \
+		.enable_reg = AFE_##_id##_CON0, \
+		.enable_shift = _id##_ON_SFT, \
+		.hd_reg = AFE_##_id##_CON0, \
+		.hd_shift = _id##_HD_MODE_SFT, \
+		.hd_align_reg = AFE_##_id##_CON0, \
+		.hd_align_mshift = _id##_HALIGN_SFT, \
+		.agent_disable_reg = -1, \
+		.agent_disable_shift = -1, \
+		.msb_reg = -1, \
+		.msb_shift = -1, \
+		.pbuf_reg = AFE_##_id##_CON0, \
+		.pbuf_mask = _id##_PBUF_SIZE_MASK, \
+		.pbuf_shift = _id##_PBUF_SIZE_SFT, \
+		.minlen_reg = AFE_##_id##_CON0, \
+		.minlen_mask = _id##_MINLEN_MASK, \
+		.minlen_shift = _id##_MINLEN_SFT, \
+}
+
+#define MT8196_MULTI_DL_MEMIF(_id) \
+	[MT8196_MEMIF_##_id] = { \
+		.name = #_id, \
+		.id = MT8196_MEMIF_##_id, \
+		.reg_ofs_base = AFE_##_id##_BASE, \
+		.reg_ofs_cur = AFE_##_id##_CUR, \
+		.reg_ofs_end = AFE_##_id##_END, \
+		.reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \
+		.reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \
+		.reg_ofs_end_msb = AFE_##_id##_END_MSB, \
+		.fs_reg = AFE_##_id##_CON0, \
+		.fs_shift = _id##_SEL_FS_SFT, \
+		.fs_maskbit = _id##_SEL_FS_MASK, \
+		.mono_reg = -1, \
+		.mono_shift = -1, \
+		.enable_reg = AFE_##_id##_CON0, \
+		.enable_shift = _id##_ON_SFT, \
+		.hd_reg = AFE_##_id##_CON0, \
+		.hd_shift = _id##_HD_MODE_SFT, \
+		.hd_align_reg = AFE_##_id##_CON0, \
+		.hd_align_mshift = _id##_HALIGN_SFT, \
+		.agent_disable_reg = -1, \
+		.agent_disable_shift = -1, \
+		.msb_reg = -1, \
+		.msb_shift = -1, \
+		.pbuf_reg = AFE_##_id##_CON0, \
+		.pbuf_mask = _id##_PBUF_SIZE_MASK, \
+		.pbuf_shift = _id##_PBUF_SIZE_SFT, \
+		.minlen_reg = AFE_##_id##_CON0, \
+		.minlen_mask = _id##_MINLEN_MASK, \
+		.minlen_shift = _id##_MINLEN_SFT, \
+		.ch_num_reg = AFE_##_id##_CON0, \
+		.ch_num_maskbit = _id##_NUM_MASK, \
+		.ch_num_shift = _id##_NUM_SFT, \
+}
+
+#define MT8196_UL_MEMIF(_id, _fs_shift, _fs_maskbit, _mono_shift) \
+	[MT8196_MEMIF_##_id] = { \
+		.name = #_id, \
+		.id = MT8196_MEMIF_##_id, \
+		.reg_ofs_base = AFE_##_id##_BASE, \
+		.reg_ofs_cur = AFE_##_id##_CUR, \
+		.reg_ofs_end = AFE_##_id##_END, \
+		.reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \
+		.reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \
+		.reg_ofs_end_msb = AFE_##_id##_END_MSB, \
+		.fs_reg = AFE_##_id##_CON0, \
+		.fs_shift = _fs_shift, \
+		.fs_maskbit = _fs_maskbit, \
+		.mono_reg = AFE_##_id##_CON0, \
+		.mono_shift = _mono_shift, \
+		.enable_reg = AFE_##_id##_CON0, \
+		.enable_shift = _id##_ON_SFT, \
+		.hd_reg = AFE_##_id##_CON0, \
+		.hd_shift = _id##_HD_MODE_SFT, \
+		.hd_align_reg = AFE_##_id##_CON0, \
+		.hd_align_mshift = _id##_HALIGN_SFT, \
+		.agent_disable_reg = -1, \
+		.agent_disable_shift = -1, \
+		.msb_reg = -1, \
+		.msb_shift = -1, \
+	}
+
+/* For convenience with macros: missing register fields */
+#define HDMI_SEL_FS_SFT			-1
+#define HDMI_SEL_FS_MASK		-1
+
+/* For convenience with macros: register name differences */
+#define AFE_HDMI_BASE			AFE_HDMI_OUT_BASE
+#define AFE_HDMI_CUR			AFE_HDMI_OUT_CUR
+#define AFE_HDMI_END			AFE_HDMI_OUT_END
+#define AFE_HDMI_BASE_MSB		AFE_HDMI_OUT_BASE_MSB
+#define AFE_HDMI_CUR_MSB		AFE_HDMI_OUT_CUR_MSB
+#define AFE_HDMI_END_MSB		AFE_HDMI_OUT_END_MSB
+#define AFE_HDMI_CON0			AFE_HDMI_OUT_CON0
+#define HDMI_ON_SFT				HDMI_OUT_ON_SFT
+#define HDMI_HD_MODE_SFT		HDMI_OUT_HD_MODE_SFT
+#define HDMI_HALIGN_SFT			HDMI_OUT_HALIGN_SFT
+#define HDMI_PBUF_SIZE_MASK		HDMI_OUT_PBUF_SIZE_MASK
+#define HDMI_PBUF_SIZE_SFT		HDMI_OUT_PBUF_SIZE_SFT
+#define HDMI_MINLEN_MASK		HDMI_OUT_MINLEN_MASK
+#define HDMI_MINLEN_SFT			HDMI_OUT_MINLEN_SFT
+#define HDMI_NUM_MASK			HDMI_CH_NUM_MASK
+#define HDMI_NUM_SFT			HDMI_CH_NUM_SFT
+
+static const struct mtk_base_memif_data memif_data[MT8196_MEMIF_NUM] = {
+	MT8196_DL_MEMIF(DL0),
+	MT8196_DL_MEMIF(DL1),
+	MT8196_DL_MEMIF(DL2),
+	MT8196_DL_MEMIF(DL3),
+	MT8196_DL_MEMIF(DL4),
+	MT8196_DL_MEMIF(DL5),
+	MT8196_DL_MEMIF(DL6),
+	MT8196_DL_MEMIF(DL7),
+	MT8196_DL_MEMIF(DL8),
+	MT8196_DL_MEMIF(DL23),
+	MT8196_DL_MEMIF(DL24),
+	MT8196_DL_MEMIF(DL25),
+	MT8196_DL_MEMIF(DL26),
+	MT8196_MULTI_DL_MEMIF(DL_4CH),
+	MT8196_MULTI_DL_MEMIF(DL_24CH),
+	MT8196_MULTI_DL_MEMIF(HDMI),
+	MT8196_UL_MEMIF(VUL0, VUL0_SEL_FS_SFT, VUL0_SEL_FS_MASK, VUL0_MONO_SFT),
+	MT8196_UL_MEMIF(VUL1, VUL1_SEL_FS_SFT, VUL1_SEL_FS_MASK, VUL1_MONO_SFT),
+	MT8196_UL_MEMIF(VUL2, VUL2_SEL_FS_SFT, VUL2_SEL_FS_MASK, VUL2_MONO_SFT),
+	MT8196_UL_MEMIF(VUL3, VUL3_SEL_FS_SFT, VUL3_SEL_FS_MASK, VUL3_MONO_SFT),
+	MT8196_UL_MEMIF(VUL4, VUL4_SEL_FS_SFT, VUL4_SEL_FS_MASK, VUL4_MONO_SFT),
+	MT8196_UL_MEMIF(VUL5, VUL5_SEL_FS_SFT, VUL5_SEL_FS_MASK, VUL5_MONO_SFT),
+	MT8196_UL_MEMIF(VUL6, VUL6_SEL_FS_SFT, VUL6_SEL_FS_MASK, VUL6_MONO_SFT),
+	MT8196_UL_MEMIF(VUL7, VUL7_SEL_FS_SFT, VUL7_SEL_FS_MASK, VUL7_MONO_SFT),
+	MT8196_UL_MEMIF(VUL8, VUL8_SEL_FS_SFT, VUL8_SEL_FS_MASK, VUL8_MONO_SFT),
+	MT8196_UL_MEMIF(VUL9, VUL9_SEL_FS_SFT, VUL9_SEL_FS_MASK, VUL9_MONO_SFT),
+	MT8196_UL_MEMIF(VUL10, VUL10_SEL_FS_SFT, VUL10_SEL_FS_MASK, VUL10_MONO_SFT),
+	MT8196_UL_MEMIF(VUL24, VUL24_SEL_FS_SFT, VUL24_SEL_FS_MASK, VUL24_MONO_SFT),
+	MT8196_UL_MEMIF(VUL25, VUL25_SEL_FS_SFT, VUL25_SEL_FS_MASK, VUL25_MONO_SFT),
+	MT8196_UL_MEMIF(VUL26, VUL26_SEL_FS_SFT, VUL26_SEL_FS_MASK, VUL26_MONO_SFT),
+	MT8196_UL_MEMIF(VUL_CM0, -1, -1, -1),
+	MT8196_UL_MEMIF(VUL_CM1, -1, -1, -1),
+	MT8196_UL_MEMIF(VUL_CM2, -1, -1, -1),
+	MT8196_UL_MEMIF(ETDM_IN0, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1),
+	MT8196_UL_MEMIF(ETDM_IN1, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1),
+	MT8196_UL_MEMIF(ETDM_IN2, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1),
+	MT8196_UL_MEMIF(ETDM_IN3, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1),
+	MT8196_UL_MEMIF(ETDM_IN4, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1),
+	MT8196_UL_MEMIF(ETDM_IN6, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1),
+};
+
+#define MT8183_AFE_IRQ_BASE(_id, _fs_reg, _fs_shift, _fs_maskbit)	\
+	[MT8183_IRQ_##_id] = {	\
+		.id = MT8183_IRQ_##_id,			\
+		.irq_cnt_reg = AFE_IRQ_MCU_CNT##_id,	\
+		.irq_cnt_shift = 0,			\
+		.irq_cnt_maskbit = 0x3ffff,		\
+		.irq_fs_reg = _fs_reg,			\
+		.irq_fs_shift = _fs_shift,		\
+		.irq_fs_maskbit = _fs_maskbit,		\
+		.irq_en_reg = AFE_IRQ_MCU_CON0,		\
+		.irq_en_shift = IRQ##_id##_MCU_ON_SFT,	\
+		.irq_clr_reg = AFE_IRQ_MCU_CLR,		\
+		.irq_clr_shift = IRQ##_id##_MCU_CLR_SFT,	\
+	}
+
+#define MT8196_AFE_IRQ(_id)	\
+	[MT8196_IRQ_##_id] = { \
+		.id = MT8196_IRQ_##_id, \
+		.irq_cnt_reg = AFE_IRQ##_id##_MCU_CFG1, \
+		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT, \
+		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK, \
+		.irq_fs_reg = AFE_IRQ##_id##_MCU_CFG0, \
+		.irq_fs_shift = AFE_IRQ##_id##_MCU_FS_SFT, \
+		.irq_fs_maskbit = AFE_IRQ##_id##_MCU_FS_MASK, \
+		.irq_en_reg = AFE_IRQ##_id##_MCU_CFG0, \
+		.irq_en_shift = AFE_IRQ##_id##_MCU_ON_SFT, \
+		.irq_clr_reg = AFE_IRQ##_id##_MCU_CFG1, \
+		.irq_clr_shift = AFE_IRQ##_id##_CLR_CFG_SFT, \
+	}
+
+#define MT8196_AFE_TDM_IRQ(_id)	\
+	[MT8196_IRQ_##_id] = { \
+		.id = MT8196_CUS_IRQ_TDM, \
+		.irq_cnt_reg = AFE_CUSTOM_IRQ0_MCU_CFG1, \
+		.irq_cnt_shift = AFE_CUSTOM_IRQ0_MCU_CNT_SFT, \
+		.irq_cnt_maskbit = AFE_CUSTOM_IRQ0_MCU_CNT_MASK, \
+		.irq_fs_reg = -1, \
+		.irq_fs_shift = -1, \
+		.irq_fs_maskbit = -1, \
+		.irq_en_reg = AFE_CUSTOM_IRQ0_MCU_CFG0, \
+		.irq_en_shift = AFE_CUSTOM_IRQ0_MCU_ON_SFT, \
+		.irq_clr_reg = AFE_CUSTOM_IRQ0_MCU_CFG1, \
+		.irq_clr_shift = AFE_CUSTOM_IRQ0_CLR_CFG_SFT, \
+	}
+
+static const struct mtk_base_irq_data irq_data[MT8196_IRQ_NUM] = {
+	MT8196_AFE_IRQ(0),
+	MT8196_AFE_IRQ(1),
+	MT8196_AFE_IRQ(2),
+	MT8196_AFE_IRQ(3),
+	MT8196_AFE_IRQ(4),
+	MT8196_AFE_IRQ(5),
+	MT8196_AFE_IRQ(6),
+	MT8196_AFE_IRQ(7),
+	MT8196_AFE_IRQ(8),
+	MT8196_AFE_IRQ(9),
+	MT8196_AFE_IRQ(10),
+	MT8196_AFE_IRQ(11),
+	MT8196_AFE_IRQ(12),
+	MT8196_AFE_IRQ(13),
+	MT8196_AFE_IRQ(14),
+	MT8196_AFE_IRQ(15),
+	MT8196_AFE_IRQ(16),
+	MT8196_AFE_IRQ(17),
+	MT8196_AFE_IRQ(18),
+	MT8196_AFE_IRQ(19),
+	MT8196_AFE_IRQ(20),
+	MT8196_AFE_IRQ(21),
+	MT8196_AFE_IRQ(22),
+	MT8196_AFE_IRQ(23),
+	MT8196_AFE_IRQ(24),
+	MT8196_AFE_IRQ(25),
+	MT8196_AFE_IRQ(26),
+	MT8196_AFE_TDM_IRQ(31),
+};
+
+static const int memif_irq_usage[MT8196_MEMIF_NUM] = {
+	/* TODO: verify each memif & irq */
+	[MT8196_MEMIF_DL0] = MT8196_IRQ_0,
+	[MT8196_MEMIF_DL1] = MT8196_IRQ_1,
+	[MT8196_MEMIF_DL2] = MT8196_IRQ_2,
+	[MT8196_MEMIF_DL3] = MT8196_IRQ_3,
+	[MT8196_MEMIF_DL4] = MT8196_IRQ_4,
+	[MT8196_MEMIF_DL5] = MT8196_IRQ_5,
+	[MT8196_MEMIF_DL6] = MT8196_IRQ_6,
+	[MT8196_MEMIF_DL7] = MT8196_IRQ_7,
+	[MT8196_MEMIF_DL8] = MT8196_IRQ_8,
+	[MT8196_MEMIF_DL23] = MT8196_IRQ_9,
+	[MT8196_MEMIF_DL24] = MT8196_IRQ_10,
+	[MT8196_MEMIF_DL25] = MT8196_IRQ_11,
+	[MT8196_MEMIF_DL26] = MT8196_IRQ_0,
+	[MT8196_MEMIF_DL_4CH] = MT8196_IRQ_0,
+	[MT8196_MEMIF_DL_24CH] = MT8196_IRQ_12,
+	[MT8196_MEMIF_VUL0] = MT8196_IRQ_13,
+	[MT8196_MEMIF_VUL1] = MT8196_IRQ_14,
+	[MT8196_MEMIF_VUL2] = MT8196_IRQ_15,
+	[MT8196_MEMIF_VUL3] = MT8196_IRQ_16,
+	[MT8196_MEMIF_VUL4] = MT8196_IRQ_17,
+	[MT8196_MEMIF_VUL5] = MT8196_IRQ_18,
+	[MT8196_MEMIF_VUL6] = MT8196_IRQ_19,
+	[MT8196_MEMIF_VUL7] = MT8196_IRQ_20,
+	[MT8196_MEMIF_VUL8] = MT8196_IRQ_21,
+	[MT8196_MEMIF_VUL9] = MT8196_IRQ_22,
+	[MT8196_MEMIF_VUL10] = MT8196_IRQ_23,
+	[MT8196_MEMIF_VUL24] = MT8196_IRQ_24,
+	[MT8196_MEMIF_VUL25] = MT8196_IRQ_25,
+	[MT8196_MEMIF_VUL26] = MT8196_IRQ_0,
+	[MT8196_MEMIF_VUL_CM0] = MT8196_IRQ_26,
+	[MT8196_MEMIF_VUL_CM1] = MT8196_IRQ_0,
+	[MT8196_MEMIF_VUL_CM2] = MT8196_IRQ_0,
+	[MT8196_MEMIF_ETDM_IN0] = MT8196_IRQ_0,
+	[MT8196_MEMIF_ETDM_IN1] = MT8196_IRQ_0,
+	[MT8196_MEMIF_ETDM_IN2] = MT8196_IRQ_0,
+	[MT8196_MEMIF_ETDM_IN3] = MT8196_IRQ_0,
+	[MT8196_MEMIF_ETDM_IN4] = MT8196_IRQ_0,
+	[MT8196_MEMIF_ETDM_IN6] = MT8196_IRQ_0,
+	[MT8196_MEMIF_HDMI] = MT8196_IRQ_31
+};
+
+static bool mt8196_is_volatile_reg(struct device *dev, unsigned int reg)
+{
+	/* these auto-gen reg has read-only bit, so put it as volatile */
+	/* volatile reg cannot be cached, so cannot be set when power off */
+	switch (reg) {
+	case AUDIO_TOP_CON0 ... AUDIO_TOP_CON4:
+	case AFE_APLL1_TUNER_MON0:
+	case AFE_APLL2_TUNER_MON0:
+	case AFE_SPM_CONTROL_ACK:
+	case AUDIO_TOP_IP_VERSION:
+	case AUDIO_ENGEN_CON0_MON:
+	case AUD_TOP_MON_RG:
+	case AFE_CONNSYS_I2S_IPM_VER_MON:
+	case AFE_CONNSYS_I2S_MON:
+	case AFE_PCM_INTF_MON:
+	case AFE_PCM_TOP_IP_VERSION:
+	case AFE_IRQ_MCU_STATUS:
+	case AFE_CUSTOM_IRQ_MCU_STATUS:
+	case AFE_IRQ_MCU_MON0 ... AFE_IRQ26_CNT_MON:
+	case AFE_CUSTOM_IRQ0_CNT_MON:
+	case AFE_STF_MON:
+	case AFE_STF_IP_VERSION:
+	case AFE_CM0_MON:
+	case AFE_CM0_IP_VERSION:
+	case AFE_CM1_MON:
+	case AFE_CM1_IP_VERSION:
+	case AFE_ADDA_UL0_SRC_DEBUG_MON0 ... AFE_ADDA_UL0_SRC_MON1:
+	case AFE_ADDA_UL0_IP_VERSION:
+	case AFE_ADDA_UL1_SRC_DEBUG_MON0 ... AFE_ADDA_UL1_SRC_MON1:
+	case AFE_ADDA_UL1_IP_VERSION:
+	case AFE_MTKAIF_IPM_VER_MON:
+	case AFE_MTKAIF_MON:
+	case AFE_AUD_PAD_TOP_MON:
+	case AFE_ADDA_MTKAIFV4_MON0 ... AFE_ADDA6_MTKAIFV4_MON0:
+	case ETDM_IN0_MON:
+	case ETDM_IN1_MON:
+	case ETDM_IN2_MON:
+	case ETDM_IN4_MON:
+	case ETDM_IN6_MON:
+	case ETDM_OUT0_MON:
+	case ETDM_OUT1_MON:
+	case ETDM_OUT2_MON:
+	case ETDM_OUT4_MON:
+	case ETDM_OUT6_MON:
+	case AFE_DPTX_MON:
+	case AFE_TDM_TOP_IP_VERSION:
+	case AFE_CONN_MON0 ... AFE_CONN_MON5:
+	case AFE_CBIP_SLV_DECODER_MON0 ... AFE_CBIP_SLV_MUX_MON1:
+	case AFE_DL0_CUR_MSB ... AFE_DL0_CUR:
+	case AFE_DL0_RCH_MON ... AFE_DL0_LCH_MON:
+	case AFE_DL1_CUR_MSB ... AFE_DL1_CUR:
+	case AFE_DL1_RCH_MON ... AFE_DL1_LCH_MON:
+	case AFE_DL2_CUR_MSB ... AFE_DL2_CUR:
+	case AFE_DL2_RCH_MON ... AFE_DL2_LCH_MON:
+	case AFE_DL3_CUR_MSB ... AFE_DL3_CUR:
+	case AFE_DL3_RCH_MON ... AFE_DL3_LCH_MON:
+	case AFE_DL4_CUR_MSB ... AFE_DL4_CUR:
+	case AFE_DL4_RCH_MON ... AFE_DL4_LCH_MON:
+	case AFE_DL5_CUR_MSB ... AFE_DL5_CUR:
+	case AFE_DL5_RCH_MON ... AFE_DL5_LCH_MON:
+	case AFE_DL6_CUR_MSB ... AFE_DL6_CUR:
+	case AFE_DL6_RCH_MON ... AFE_DL6_LCH_MON:
+	case AFE_DL7_CUR_MSB ... AFE_DL7_CUR:
+	case AFE_DL7_RCH_MON ... AFE_DL7_LCH_MON:
+	case AFE_DL8_CUR_MSB ... AFE_DL8_CUR:
+	case AFE_DL8_RCH_MON ... AFE_DL8_LCH_MON:
+	case AFE_DL_24CH_CUR_MSB ... AFE_DL_24CH_CUR:
+	case AFE_DL_4CH_CUR_MSB ... AFE_DL_4CH_CUR:
+	case AFE_DL23_CUR_MSB ... AFE_DL23_CUR:
+	case AFE_DL23_RCH_MON ... AFE_DL23_LCH_MON:
+	case AFE_DL24_CUR_MSB ... AFE_DL24_CUR:
+	case AFE_DL24_RCH_MON ... AFE_DL24_LCH_MON:
+	case AFE_DL25_CUR_MSB ... AFE_DL25_CUR:
+	case AFE_DL25_RCH_MON ... AFE_DL25_LCH_MON:
+	case AFE_DL26_CUR_MSB ... AFE_DL26_CUR:
+	case AFE_DL26_RCH_MON ... AFE_DL26_LCH_MON:
+	case AFE_VUL0_CUR_MSB ... AFE_VUL0_CUR:
+	case AFE_VUL1_CUR_MSB ... AFE_VUL1_CUR:
+	case AFE_VUL2_CUR_MSB ... AFE_VUL2_CUR:
+	case AFE_VUL3_CUR_MSB ... AFE_VUL3_CUR:
+	case AFE_VUL4_CUR_MSB ... AFE_VUL4_CUR:
+	case AFE_VUL5_CUR_MSB ... AFE_VUL5_CUR:
+	case AFE_VUL6_CUR_MSB ... AFE_VUL6_CUR:
+	case AFE_VUL7_CUR_MSB ... AFE_VUL7_CUR:
+	case AFE_VUL8_CUR_MSB ... AFE_VUL8_CUR:
+	case AFE_VUL9_CUR_MSB ... AFE_VUL9_CUR:
+	case AFE_VUL10_CUR_MSB ... AFE_VUL10_CUR:
+	case AFE_VUL24_CUR_MSB ... AFE_VUL24_CUR:
+	case AFE_VUL25_CUR_MSB ... AFE_VUL25_CUR:
+	case AFE_VUL25_RCH_MON ... AFE_VUL25_LCH_MON:
+	case AFE_VUL26_CUR_MSB ... AFE_VUL26_CUR:
+	case AFE_VUL_CM0_BASE_MSB ... AFE_VUL_CM0_CON0:
+	case AFE_VUL_CM1_CUR_MSB ... AFE_VUL_CM1_CUR:
+	case AFE_VUL_CM2_CUR_MSB ... AFE_VUL_CM2_CUR:
+	case AFE_ETDM_IN0_CUR_MSB ... AFE_ETDM_IN0_CUR:
+	case AFE_ETDM_IN1_CUR_MSB ... AFE_ETDM_IN1_CUR:
+	case AFE_ETDM_IN2_CUR_MSB ... AFE_ETDM_IN2_CUR:
+	case AFE_ETDM_IN3_CUR_MSB ... AFE_ETDM_IN3_CUR:
+	case AFE_ETDM_IN4_CUR_MSB ... AFE_ETDM_IN4_CUR:
+	case AFE_ETDM_IN6_CUR_MSB ... AFE_ETDM_IN6_CUR:
+	case AFE_HDMI_OUT_CUR_MSB ... AFE_HDMI_OUT_CUR:
+	case AFE_HDMI_OUT_END:
+	case AFE_PROT_SIDEBAND0_MON ... AFE_DOMAIN_SIDEBAND9_MON:
+	case AFE_PCM0_INTF_CON1_MASK_MON ... AFE_ADDA_UL1_SRC_CON0_MASK_MON:
+	case AFE_IRQ_MCU_EN ... AFE_IRQ_MCU_DSP2_EN:
+	case AFE_DL5_CON0:
+	case AFE_DL6_CON0:
+	case AFE_DL23_CON0:
+	case AFE_DL_24CH_CON0:
+	case AFE_VUL1_CON0:
+	case AFE_VUL3_CON0:
+	case AFE_VUL4_CON0:
+	case AFE_VUL5_CON0:
+	case AFE_VUL9_CON0:
+	case AFE_VUL25_CON0:
+	case AFE_IRQ0_MCU_CFG0 ... AFE_IRQ26_MCU_CFG1:
+		return true;
+	default:
+		return false;
+	};
+}
+
+static const struct regmap_config mt8196_afe_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+
+	.volatile_reg = mt8196_is_volatile_reg,
+
+	.max_register = AFE_MAX_REGISTER,
+	.num_reg_defaults_raw = AFE_MAX_REGISTER,
+
+	.cache_type = REGCACHE_FLAT,
+};
+
+static irqreturn_t mt8196_afe_irq_handler(int irq_id, void *dev)
+{
+	struct mtk_base_afe *afe = dev;
+	struct mtk_base_afe_irq *irq;
+	unsigned int status = 0;
+	unsigned int status_mcu;
+	unsigned int mcu_en = 0;
+	unsigned int cus_status = 0;
+	unsigned int cus_status_mcu;
+	unsigned int cus_mcu_en = 0;
+	unsigned int tmp_reg = 0;
+	int ret, cus_ret;
+	int i;
+	struct timespec64 ts64;
+	unsigned long long t1, t2;
+	/* one interrupt period = 5ms */
+	unsigned long long timeout_limit = 5000000;
+
+	/* get irq that is sent to MCU */
+	regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
+	regmap_read(afe->regmap, AFE_CUSTOM_IRQ_MCU_EN, &cus_mcu_en);
+
+	ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
+	cus_ret = regmap_read(afe->regmap, AFE_CUSTOM_IRQ_MCU_STATUS, &cus_status);
+	/* only care IRQ which is sent to MCU */
+	status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
+	cus_status_mcu = cus_status & cus_mcu_en & AFE_IRQ_STATUS_BITS;
+	if ((ret || !status_mcu) &&
+	    (cus_ret || !cus_status_mcu)) {
+		dev_info(afe->dev, "irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
+			 ret, status, mcu_en);
+		dev_info(afe->dev, "irq status err, ret %d, cus_status_mcu 0x%x, cus_mcu_en 0x%x\n",
+			 ret, cus_status_mcu, cus_mcu_en);
+
+		goto err_irq;
+	}
+
+	ktime_get_ts64(&ts64);
+	t1 = timespec64_to_ns(&ts64);
+
+	for (i = 0; i < MT8196_MEMIF_NUM; i++) {
+		struct mtk_base_afe_memif *memif = &afe->memif[i];
+
+		if (!memif->substream)
+			continue;
+
+		if (memif->irq_usage < 0)
+			continue;
+		irq = &afe->irqs[memif->irq_usage];
+
+		if (i == MT8196_MEMIF_HDMI) {
+			if (cus_status_mcu & (0x1 << irq->irq_data->id))
+				snd_pcm_period_elapsed(memif->substream);
+		} else {
+			if (status_mcu & (0x1 << irq->irq_data->id))
+				snd_pcm_period_elapsed(memif->substream);
+		}
+	}
+
+	ktime_get_ts64(&ts64);
+	t2 = timespec64_to_ns(&ts64);
+	t2 = t2 - t1; /* in ns (10^9) */
+
+	if (t2 > timeout_limit) {
+		dev_warn(afe->dev, "mcu_en 0x%x, cus_mcu_en 0x%x, timeout %llu, limit %llu, ret %d\n",
+			 mcu_en, cus_mcu_en,
+			 t2, timeout_limit, ret);
+	}
+
+err_irq:
+	/* clear irq */
+	for (i = 0; i < MT8196_IRQ_NUM; ++i) {
+		/* cus_status_mcu only bit0 is used for TDM */
+		if ((status_mcu & (0x1 << i)) || (cus_status_mcu & 0x1)) {
+			regmap_read(afe->regmap, irq_data[i].irq_clr_reg, &tmp_reg);
+			regmap_update_bits(afe->regmap, irq_data[i].irq_clr_reg,
+					   AFE_IRQ_CLR_CFG_MASK_SFT |
+					   AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT,
+					   tmp_reg ^ (AFE_IRQ_CLR_CFG_MASK_SFT |
+					   AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT));
+		}
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int mt8196_afe_runtime_suspend(struct device *dev)
+{
+	struct mtk_base_afe *afe = dev_get_drvdata(dev);
+	unsigned int value = 0;
+	unsigned int tmp_reg = 0;
+	int ret = 0, i;
+
+	if (!afe->regmap) {
+		dev_err(afe->dev, "skip regmap\n");
+		goto skip_regmap;
+	}
+
+	/* disable AFE */
+	mt8196_afe_disable_main_clock(afe);
+
+	ret = regmap_read_poll_timeout(afe->regmap,
+				       AUDIO_ENGEN_CON0_MON,
+				       value,
+				       (value & AUDIO_ENGEN_MON_SFT) == 0,
+				       20,
+				       1 * 1000 * 1000);
+	dev_dbg(afe->dev, "read_poll ret %d\n", ret);
+	if (ret)
+		dev_info(afe->dev, "ret %d\n", ret);
+
+	/* make sure all irq status are cleared */
+	for (i = 0; i < MT8196_IRQ_NUM; ++i) {
+		regmap_read(afe->regmap, irq_data[i].irq_clr_reg, &tmp_reg);
+		regmap_update_bits(afe->regmap, irq_data[i].irq_clr_reg,
+				   AFE_IRQ_CLR_CFG_MASK_SFT | AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT,
+				   tmp_reg ^ (AFE_IRQ_CLR_CFG_MASK_SFT |
+				   AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT));
+	}
+
+	/* reset audio 26M request */
+	regmap_update_bits(afe->regmap,
+			   AFE_SPM_CONTROL_REQ, 0x1, 0x0);
+
+	/* cache only */
+	regcache_cache_only(afe->regmap, true);
+	regcache_mark_dirty(afe->regmap);
+
+skip_regmap:
+	mt8196_afe_disable_reg_rw_clk(afe);
+	return 0;
+}
+
+static int mt8196_afe_runtime_resume(struct device *dev)
+{
+	struct mtk_base_afe *afe = dev_get_drvdata(dev);
+	int ret = 0;
+
+	ret = mt8196_afe_enable_reg_rw_clk(afe);
+	if (ret)
+		return ret;
+
+	if (!afe->regmap) {
+		dev_warn(afe->dev, "skip regmap\n");
+		goto skip_regmap;
+	}
+	regcache_cache_only(afe->regmap, false);
+	regcache_sync(afe->regmap);
+
+	/* set audio 26M request */
+	regmap_update_bits(afe->regmap, AFE_SPM_CONTROL_REQ, 0x1, 0x1);
+	regmap_update_bits(afe->regmap, AFE_CBIP_CFG0, 0x1, 0x1);
+
+	/* force cpu use 8_24 format when writing 32bit data */
+	regmap_update_bits(afe->regmap, AFE_MEMIF_CON0,
+			   CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT);
+
+	/* enable AFE */
+	mt8196_afe_enable_main_clock(afe);
+
+skip_regmap:
+	return 0;
+}
+
+static int mt8196_afe_component_probe(struct snd_soc_component *component)
+{
+	if (component)
+		mtk_afe_add_sub_dai_control(component);
+
+	return 0;
+}
+
+static int mt8196_afe_pcm_open(struct snd_soc_component *component,
+			       struct snd_pcm_substream *substream)
+{
+	/* set the wait_for_avail to 2 sec*/
+	substream->wait_time = msecs_to_jiffies(2 * 1000);
+
+	return 0;
+}
+
+static void mt8196_afe_pcm_free(struct snd_soc_component *component, struct snd_pcm *pcm)
+{
+	snd_pcm_lib_preallocate_free_for_all(pcm);
+}
+
+static const struct snd_soc_component_driver mt8196_afe_component = {
+	.name = AFE_PCM_NAME,
+	.probe = mt8196_afe_component_probe,
+	.pcm_construct = mtk_afe_pcm_new,
+	.pcm_destruct = mt8196_afe_pcm_free,
+	.open = mt8196_afe_pcm_open,
+	.pointer = mtk_afe_pcm_pointer,
+};
+
+static int mt8196_dai_memif_register(struct mtk_base_afe *afe)
+{
+	struct mtk_base_afe_dai *dai;
+
+	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
+	if (!dai)
+		return -ENOMEM;
+
+	list_add(&dai->list, &afe->sub_dais);
+
+	dai->dai_drivers = mt8196_memif_dai_driver;
+	dai->num_dai_drivers = ARRAY_SIZE(mt8196_memif_dai_driver);
+
+	dai->controls = mt8196_pcm_kcontrols;
+	dai->num_controls = ARRAY_SIZE(mt8196_pcm_kcontrols);
+	dai->dapm_widgets = mt8196_memif_widgets;
+	dai->num_dapm_widgets = ARRAY_SIZE(mt8196_memif_widgets);
+	dai->dapm_routes = mt8196_memif_routes;
+	dai->num_dapm_routes = ARRAY_SIZE(mt8196_memif_routes);
+	return 0;
+}
+
+typedef int (*dai_register_cb)(struct mtk_base_afe *);
+static const dai_register_cb dai_register_cbs[] = {
+	mt8196_dai_adda_register,
+	mt8196_dai_i2s_register,
+	mt8196_dai_tdm_register,
+	mt8196_dai_memif_register,
+};
+
+static int mt8196_afe_pcm_dev_probe(struct platform_device *pdev)
+{
+	int ret, i;
+	unsigned int tmp_reg = 0;
+	int irq_id;
+	struct mtk_base_afe *afe;
+	struct mt8196_afe_private *afe_priv;
+	struct device *dev = &pdev->dev;
+
+	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34));
+	if (ret)
+		return ret;
+
+	ret = of_reserved_mem_device_init(dev);
+	if (ret)
+		dev_err(dev, "failed to assign memory region: %d\n", ret);
+
+	afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL);
+	if (!afe)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, afe);
+
+	afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv),
+					  GFP_KERNEL);
+	if (!afe->platform_priv)
+		return -ENOMEM;
+
+	afe_priv = afe->platform_priv;
+	afe->dev = dev;
+
+	afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(afe->base_addr))
+		return dev_err_probe(dev, PTR_ERR(afe->base_addr),
+				     "AFE base_addr not found\n");
+
+	/* init audio related clock */
+	ret = mt8196_init_clock(afe);
+	if (ret)
+		return dev_err_probe(dev, ret, "init clock error.\n");
+
+	/* init memif */
+	/* IPM2.0 no need banding */
+	afe->memif_32bit_supported = 1;
+	afe->memif_size = MT8196_MEMIF_NUM;
+	afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
+				  GFP_KERNEL);
+
+	if (!afe->memif)
+		return -ENOMEM;
+
+	for (i = 0; i < afe->memif_size; i++) {
+		afe->memif[i].data = &memif_data[i];
+		afe->memif[i].irq_usage = memif_irq_usage[i];
+		afe->memif[i].const_irq = 1;
+	}
+
+	mutex_init(&afe->irq_alloc_lock);
+
+	/* init irq */
+	afe->irqs_size = MT8196_IRQ_NUM;
+	afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
+				 GFP_KERNEL);
+
+	if (!afe->irqs)
+		return -ENOMEM;
+
+	for (i = 0; i < afe->irqs_size; i++)
+		afe->irqs[i].irq_data = &irq_data[i];
+
+	/* request irq */
+	irq_id = platform_get_irq(pdev, 0);
+	if (irq_id < 0)
+		return dev_err_probe(dev, irq_id, "no irq found");
+
+	ret = devm_request_irq(dev, irq_id, mt8196_afe_irq_handler,
+			       IRQF_TRIGGER_NONE,
+			       "Afe_ISR_Handle", (void *)afe);
+	if (ret)
+		return dev_err_probe(dev, ret, "could not request_irq for Afe_ISR_Handle\n");
+
+	ret = enable_irq_wake(irq_id);
+	if (ret < 0)
+		dev_warn(dev, "enable_irq_wake %d ret: %d\n", irq_id, ret);
+
+	/* init sub_dais */
+	INIT_LIST_HEAD(&afe->sub_dais);
+
+	for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
+		ret = dai_register_cbs[i](afe);
+		if (ret)
+			return dev_err_probe(dev, ret, "dai register i %d fail\n", i);
+	}
+
+	/* init dai_driver and component_driver */
+	ret = mtk_afe_combine_sub_dai(afe);
+	if (ret)
+		return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
+
+	/* others */
+	afe->mtk_afe_hardware = &mt8196_afe_hardware;
+	afe->memif_fs = mt8196_memif_fs;
+	afe->irq_fs = mt8196_irq_fs;
+	afe->get_dai_fs = mt8196_get_dai_fs;
+	afe->get_memif_pbuf_size = mt8196_get_memif_pbuf_size;
+
+	afe->runtime_resume = mt8196_afe_runtime_resume;
+	afe->runtime_suspend = mt8196_afe_runtime_suspend;
+
+	ret = devm_pm_runtime_enable(dev);
+	if (ret)
+		return ret;
+
+	/* Audio device is part of genpd.
+	 * Set audio as syscore device to prevent
+	 * genpd automatically power off audio
+	 * device when suspend
+	 */
+	dev_pm_syscore_device(dev, true);
+
+	/* enable clock for regcache get default value from hw */
+	pm_runtime_get_sync(dev);
+
+	afe->regmap = devm_regmap_init_mmio(dev, afe->base_addr,
+					    &mt8196_afe_regmap_config);
+	if (IS_ERR(afe->regmap))
+		return PTR_ERR(afe->regmap);
+
+	regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &tmp_reg);
+	regmap_write(afe->regmap, AFE_IRQ_MCU_EN, 0xffffffff);
+	regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &tmp_reg);
+
+	pm_runtime_put_sync(dev);
+
+	regcache_cache_only(afe->regmap, true);
+	regcache_mark_dirty(afe->regmap);
+
+	/* register component */
+	ret = devm_snd_soc_register_component(dev,
+					      &mt8196_afe_component,
+					      afe->dai_drivers,
+					      afe->num_dai_drivers);
+	if (ret) {
+		dev_warn(dev, "afe component err\n");
+		goto err_pm_disable;
+	}
+
+	return 0;
+
+err_pm_disable:
+	pm_runtime_disable(dev);
+	return ret;
+}
+
+static void mt8196_afe_pcm_dev_remove(struct platform_device *pdev)
+{
+	struct mtk_base_afe *afe = platform_get_drvdata(pdev);
+	struct device *dev = &pdev->dev;
+
+	pm_runtime_disable(dev);
+	if (!pm_runtime_status_suspended(dev))
+		mt8196_afe_runtime_suspend(dev);
+
+	/* disable afe clock */
+	mt8196_afe_disable_reg_rw_clk(afe);
+	mt8196_afe_disable_main_clock(afe);
+}
+
+static const struct of_device_id mt8196_afe_pcm_dt_match[] = {
+	{ .compatible = "mediatek,mt8196-afe", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, mt8196_afe_pcm_dt_match);
+
+static const struct dev_pm_ops mt8196_afe_pm_ops = {
+	SET_RUNTIME_PM_OPS(mt8196_afe_runtime_suspend,
+			   mt8196_afe_runtime_resume, NULL)
+};
+
+static struct platform_driver mt8196_afe_pcm_driver = {
+	.driver = {
+		.name = "mt8196-afe",
+		.of_match_table = mt8196_afe_pcm_dt_match,
+#if IS_ENABLED(CONFIG_PM)
+		.pm = &mt8196_afe_pm_ops,
+#endif
+	},
+	.probe = mt8196_afe_pcm_dev_probe,
+	.remove = mt8196_afe_pcm_dev_remove,
+};
+
+module_platform_driver(mt8196_afe_pcm_driver);
+
+MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8196");
+MODULE_AUTHOR("Darren Ye <darren.ye at mediatek.com>");
+MODULE_LICENSE("GPL");
-- 
2.45.2



From darren.ye at mediatek.com  Wed May 14 01:11:10 2025
From: darren.ye at mediatek.com (Darren.Ye)
Date: Wed, 14 May 2025 16:11:10 +0800
Subject: [PATCH v3 08/10] ASoC: dt-bindings: mediatek,mt8196-afe: add audio AFE document
In-Reply-To: <20250514081125.24475-1-darren.ye@mediatek.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
Message-ID: <20250514081125.24475-9-darren.ye@mediatek.com>

From: Darren Ye <darren.ye at mediatek.com>

Add mt8196 audio AFE document.

Signed-off-by: Darren Ye <darren.ye at mediatek.com>
---
 .../bindings/sound/mediatek,mt8196-afe.yaml   | 155 ++++++++++++++++++
 1 file changed, 155 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml

diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml
new file mode 100644
index 000000000000..384a97ab5f4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml
@@ -0,0 +1,155 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/mediatek,mt8196-afe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Audio Front End PCM controller for MT8196
+
+maintainers:
+  - Darren Ye <darren.ye at mediatek.com>
+
+properties:
+  compatible:
+    const: mediatek,mt8196-afe
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  memory-region:
+    maxItems: 1
+
+  mediatek,vlpcksys:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: To set up the apll12 tuner
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: mux for audio intbus
+      - description: mux for audio engen1
+      - description: mux for audio engen2
+      - description: mux for audio h
+      - description: vlp 26m clock
+      - description: audio apll1 clock
+      - description: audio apll2 clock
+      - description: audio apll1 divide4
+      - description: audio apll2 divide4
+      - description: audio apll12 divide for i2sin0
+      - description: audio apll12 divide for i2sin1
+      - description: audio apll12 divide for fmi2s
+      - description: audio apll12 divide for tdmout mck
+      - description: audio apll12 divide for tdmout bck
+      - description: mux for audio apll1
+      - description: mux for audio apll2
+      - description: mux for i2sin0 mck
+      - description: mux for i2sin1 mck
+      - description: mux for fmi2s mck
+      - description: mux for tdmout mck
+      - description: mux for adsp clock
+      - description: 26m clock
+
+  clock-names:
+    items:
+      - const: top_aud_intbus
+      - const: top_aud_eng1
+      - const: top_aud_eng2
+      - const: top_aud_h
+      - const: vlp_clk26m
+      - const: apll1
+      - const: apll2
+      - const: apll1_d4
+      - const: apll2_d4
+      - const: apll12_div_i2sin0
+      - const: apll12_div_i2sin1
+      - const: apll12_div_fmi2s
+      - const: apll12_div_tdmout_m
+      - const: apll12_div_tdmout_b
+      - const: top_apll1
+      - const: top_apll2
+      - const: top_i2sin0
+      - const: top_i2sin1
+      - const: top_fmi2s
+      - const: top_tdmout
+      - const: top_adsp
+      - const: clk26m
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - mediatek,vlpcksys
+  - power-domains
+  - memory-region
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        afe at 1a110000 {
+            compatible = "mediatek,mt8196-afe";
+            reg = <0 0x1a110000 0 0x9000>;
+            interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 0>;
+            memory-region = <&afe_dma_mem_reserved>;
+            mediatek,vlpcksys = <&vlp_cksys_clk>;
+            power-domains = <&scpsys 14>; //MT8196_POWER_DOMAIN_AUDIO
+            clocks = <&vlp_cksys_clk 40>, //CLK_VLP_CK_AUD_INTBUS_SEL
+                     <&vlp_cksys_clk 38>, //CLK_VLP_CK_AUD_ENGEN1_SEL
+                     <&vlp_cksys_clk 39>, //CLK_VLP_CK_AUD_ENGEN2_SEL
+                     <&vlp_cksys_clk 37>, //CLK_VLP_CK_AUDIO_H_SEL
+                     <&vlp_cksys_clk 45>, //CLK_VLP_CK_CLKSQ
+                     <&cksys_clk 129>, //CLK_CK_APLL1
+                     <&cksys_clk 132>, //CLK_CK_APLL2
+                     <&cksys_clk 130>, //CLK_CK_APLL1_D4
+                     <&cksys_clk 133>, //CLK_CK_APLL2_D4
+                     <&cksys_clk 80>, //CLK_CK_APLL12_CK_DIV_I2SIN0
+                     <&cksys_clk 81>, //CLK_CK_APLL12_CK_DIV_I2SIN1
+                     <&cksys_clk 92>, //CLK_CK_APLL12_CK_DIV_FMI2S
+                     <&cksys_clk 93>, //CLK_CK_APLL12_CK_DIV_TDMOUT_M
+                     <&cksys_clk 94>, //CLK_CK_APLL12_CK_DIV_TDMOUT_B
+                     <&cksys_clk 43>, //CLK_CK_AUD_1_SEL
+                     <&cksys_clk 44>, //CLK_CK_AUD_2_SEL
+                     <&cksys_clk 66>, //CLK_CK_APLL_I2SIN0_MCK_SEL
+                     <&cksys_clk 67>, //CLK_CK_APLL_I2SIN1_MCK_SEL
+                     <&cksys_clk 78>, //CLK_CK_APLL_FMI2S_MCK_SEL
+                     <&cksys_clk 79>, //CLK_CK_APLL_TDMOUT_MCK_SEL
+                     <&cksys_clk 45>, //CLK_CK_ADSP_SEL
+                     <&cksys_clk 140>; //CLK_CK_TCK_26M_MX9
+            clock-names = "top_aud_intbus",
+                          "top_aud_eng1",
+                          "top_aud_eng2",
+                          "top_aud_h",
+                          "vlp_clk26m",
+                          "apll1",
+                          "apll2",
+                          "apll1_d4",
+                          "apll2_d4",
+                          "apll12_div_i2sin0",
+                          "apll12_div_i2sin1",
+                          "apll12_div_fmi2s",
+                          "apll12_div_tdmout_m",
+                          "apll12_div_tdmout_b",
+                          "top_apll1",
+                          "top_apll2",
+                          "top_i2sin0",
+                          "top_i2sin1",
+                          "top_fmi2s",
+                          "top_tdmout",
+                          "top_adsp",
+                          "clk26m";
+        };
+    };
-- 
2.45.2



From darren.ye at mediatek.com  Wed May 14 01:11:11 2025
From: darren.ye at mediatek.com (Darren.Ye)
Date: Wed, 14 May 2025 16:11:11 +0800
Subject: [PATCH v3 09/10] ASoC: mediatek: mt8196: add machine driver with nau8825
In-Reply-To: <20250514081125.24475-1-darren.ye@mediatek.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
Message-ID: <20250514081125.24475-10-darren.ye@mediatek.com>

From: Darren Ye <darren.ye at mediatek.com>

Add support for mt8196 board with nau8825.

Signed-off-by: Darren Ye <darren.ye at mediatek.com>
---
 sound/soc/mediatek/Kconfig                 |  22 +-
 sound/soc/mediatek/mt8196/Makefile         |   3 +
 sound/soc/mediatek/mt8196/mt8196-nau8825.c | 869 +++++++++++++++++++++
 3 files changed, 893 insertions(+), 1 deletion(-)
 create mode 100644 sound/soc/mediatek/mt8196/mt8196-nau8825.c

diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig
index 63d4abebb539..90515f7df2cb 100644
--- a/sound/soc/mediatek/Kconfig
+++ b/sound/soc/mediatek/Kconfig
@@ -328,4 +328,24 @@ config SND_SOC_MT8196
 	  This adds ASoC driver for Mediatek MT8196 boards
 	  that can be used with other codecs.
 	  Select Y if you have such device.
-	  If unsure select "N".
\ No newline at end of file
+	  If unsure select "N".
+
+config SND_SOC_MT8196_NAU8825
+	tristate "ASoc Audio driver for MT8196 with NAU8825 and I2S codec"
+	depends on SND_SOC_MT8196
+	depends on I2C
+	select SND_SOC_HDMI_CODEC
+	select SND_SOC_DMIC
+	select SND_SOC_NAU8315
+	select SND_SOC_NAU8825
+	select SND_SOC_RT5645
+	select SND_SOC_RT5682_I2C
+	select SND_SOC_RT5682S
+	select SND_SOC_TAS2781_COMLIB
+	select SND_SOC_TAS2781_FMWLIB
+	select SND_SOC_TAS2781_I2C
+	help
+	  This adds support for ASoC machine driver for MediaTek MT8196
+	  boards with the NAU8825 and other I2S audio codecs.
+	  Select Y if you have such device.
+	  If unsure select "N".
diff --git a/sound/soc/mediatek/mt8196/Makefile b/sound/soc/mediatek/mt8196/Makefile
index b8a51a53d52a..453279a11313 100644
--- a/sound/soc/mediatek/mt8196/Makefile
+++ b/sound/soc/mediatek/mt8196/Makefile
@@ -13,3 +13,6 @@ snd-soc-mt8196-afe-objs += \
 	mt8196-dai-tdm.o
 
 obj-$(CONFIG_SND_SOC_MT8196) += snd-soc-mt8196-afe.o
+
+# machine driver
+obj-$(CONFIG_SND_SOC_MT8196_NAU8825) += mt8196-nau8825.o
diff --git a/sound/soc/mediatek/mt8196/mt8196-nau8825.c b/sound/soc/mediatek/mt8196/mt8196-nau8825.c
new file mode 100644
index 000000000000..6452484a2777
--- /dev/null
+++ b/sound/soc/mediatek/mt8196/mt8196-nau8825.c
@@ -0,0 +1,869 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *  mt8196-nau8825.c  --  mt8196 nau8825 ALSA SoC machine driver
+ *
+ *  Copyright (c) 2024 MediaTek Inc.
+ *  Author: Darren Ye <darren.ye at mediatek.com>
+ */
+
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/jack.h>
+#include <linux/input.h>
+#include <linux/of_device.h>
+
+#include "mtk-afe-platform-driver.h"
+#include "mt8196-afe-common.h"
+#include "mtk-afe-platform-driver.h"
+#include "mtk-soundcard-driver.h"
+#include "mtk-dsp-sof-common.h"
+#include "mtk-soc-card.h"
+
+#include "../../codecs/nau8825.h"
+#include "../../codecs/rt5682s.h"
+
+#define NAU8825_HS_PRESENT	BIT(0)
+#define RT5682S_HS_PRESENT	BIT(1)
+#define RT5650_HS_PRESENT	BIT(2)
+
+/*
+ * Nau88l25
+ */
+#define NAU8825_CODEC_DAI  "nau8825-hifi"
+
+/*
+ * Rt5682s
+ */
+#define RT5682S_CODEC_DAI     "rt5682s-aif1"
+
+/*
+ * Rt5650
+ */
+#define RT5650_CODEC_DAI     "rt5645-aif1"
+
+#define SOF_DMA_DL1 "SOF_DMA_DL1"
+#define SOF_DMA_DL_24CH "SOF_DMA_DL_24CH"
+#define SOF_DMA_UL0 "SOF_DMA_UL0"
+#define SOF_DMA_UL1 "SOF_DMA_UL1"
+#define SOF_DMA_UL2 "SOF_DMA_UL2"
+
+enum mt8196_jacks {
+	MT8196_JACK_HEADSET,
+	MT8196_JACK_DP,
+	MT8196_JACK_HDMI,
+	MT8196_JACK_MAX,
+};
+
+static struct snd_soc_jack_pin mt8196_dp_jack_pins[] = {
+	{
+		.pin = "DP",
+		.mask = SND_JACK_LINEOUT,
+	},
+};
+
+static struct snd_soc_jack_pin mt8196_hdmi_jack_pins[] = {
+	{
+		.pin = "HDMI",
+		.mask = SND_JACK_LINEOUT,
+	},
+};
+
+static struct snd_soc_jack_pin nau8825_jack_pins[] = {
+	{
+		.pin    = "Headphone Jack",
+		.mask   = SND_JACK_HEADPHONE,
+	},
+	{
+		.pin    = "Headset Mic",
+		.mask   = SND_JACK_MICROPHONE,
+	},
+};
+
+static const struct snd_kcontrol_new mt8196_dumb_spk_controls[] = {
+	SOC_DAPM_PIN_SWITCH("Ext Spk"),
+};
+
+static const struct snd_soc_dapm_widget mt8196_dumb_spk_widgets[] = {
+	SND_SOC_DAPM_SPK("Ext Spk", NULL),
+};
+
+static const struct snd_soc_dapm_widget mt8196_nau8825_widgets[] = {
+	SND_SOC_DAPM_HP("Headphone Jack", NULL),
+	SND_SOC_DAPM_MIC("Headset Mic", NULL),
+	SND_SOC_DAPM_SINK("DP"),
+};
+
+static const struct snd_kcontrol_new mt8196_nau8825_controls[] = {
+	SOC_DAPM_PIN_SWITCH("Headphone Jack"),
+	SOC_DAPM_PIN_SWITCH("Headset Mic"),
+};
+
+#define EXT_SPK_AMP_W_NAME "Ext_Speaker_Amp"
+
+static struct snd_soc_card mt8196_nau8825_soc_card;
+
+static const struct snd_soc_dapm_widget mt8196_nau8825_card_widgets[] = {
+	/* dynamic pinctrl */
+	SND_SOC_DAPM_PINCTRL("ETDMIN_SPK_PIN", "aud-gpio-i2sin4-on", "aud-gpio-i2sin4-off"),
+	SND_SOC_DAPM_PINCTRL("ETDMOUT_SPK_PIN", "aud-gpio-i2sout4-on", "aud-gpio-i2sout4-off"),
+	SND_SOC_DAPM_PINCTRL("ETDMIN_HP_PIN", "aud-gpio-i2sin6-on", "aud-gpio-i2sin6-off"),
+	SND_SOC_DAPM_PINCTRL("ETDMOUT_HP_PIN", "aud-gpio-i2sout6-on", "aud-gpio-i2sout6-off"),
+	SND_SOC_DAPM_PINCTRL("ETDMIN_HDMI_PIN", "aud-gpio-i2sin3-on", "aud-gpio-i2sin3-off"),
+	SND_SOC_DAPM_PINCTRL("ETDMOUT_HDMI_PIN", "aud-gpio-i2sout3-on", "aud-gpio-i2sout3-off"),
+	SND_SOC_DAPM_PINCTRL("AP_DMIC0_PIN", "aud-gpio-ap-dmic-on", "aud-gpio-ap-dmic-off"),
+	SND_SOC_DAPM_PINCTRL("AP_DMIC1_PIN", "aud-gpio-ap-dmic1-on", "aud-gpio-ap-dmic1-off"),
+};
+
+static const struct snd_soc_dapm_route mt8196_nau8825_card_routes[] = {
+};
+
+static const struct snd_kcontrol_new mt8196_nau8825_card_controls[] = {
+	SOC_DAPM_PIN_SWITCH(EXT_SPK_AMP_W_NAME),
+};
+
+/*
+ * define mtk_spk_i2s_mck node in dts when need mclk,
+ * BE i2s need assign snd_soc_ops = mt8196_nau8825_i2s_ops
+ */
+static int mt8196_nau8825_i2s_hw_params(struct snd_pcm_substream *substream,
+					struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	unsigned int rate = params_rate(params);
+	unsigned int mclk_fs_ratio = 128;
+	unsigned int mclk_fs = rate * mclk_fs_ratio;
+	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+
+	return snd_soc_dai_set_sysclk(cpu_dai,
+				      0, mclk_fs, SND_SOC_CLOCK_OUT);
+}
+
+static const struct snd_soc_ops mt8196_nau8825_i2s_ops = {
+	.hw_params = mt8196_nau8825_i2s_hw_params,
+};
+
+static int mt8196_dptx_hw_params(struct snd_pcm_substream *substream,
+				 struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	unsigned int rate = params_rate(params);
+	unsigned int mclk_fs_ratio = 256;
+	unsigned int mclk_fs = rate * mclk_fs_ratio;
+	struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0);
+
+	return snd_soc_dai_set_sysclk(dai, 0, mclk_fs, SND_SOC_CLOCK_OUT);
+}
+
+static const struct snd_soc_ops mt8196_dptx_ops = {
+	.hw_params = mt8196_dptx_hw_params,
+};
+
+static int mt8196_dptx_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+				       struct snd_pcm_hw_params *params)
+{
+	dev_info(rtd->dev, "fix format to 32bit\n");
+
+	/* fix BE i2s format to 32bit, clean param mask first */
+	snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
+			     0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
+
+	params_set_format(params, SNDRV_PCM_FORMAT_S32_LE);
+
+	return 0;
+}
+
+static int mt8196_i2s_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+				      struct snd_pcm_hw_params *params)
+{
+	dev_info(rtd->dev, "fix format to 32bit\n");
+
+	/* fix BE i2s format to 32bit, clean param mask first */
+	snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
+			     0, SNDRV_PCM_FORMAT_LAST);
+
+	params_set_format(params, SNDRV_PCM_FORMAT_S32_LE);
+	return 0;
+}
+
+static int mt8196_sof_be_hw_params(struct snd_pcm_substream *substream,
+				   struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+	struct snd_soc_component *cmpnt_afe = NULL;
+	struct snd_soc_pcm_runtime *runtime;
+
+	/* find afe component */
+	for_each_card_rtds(rtd->card, runtime) {
+		cmpnt_afe = snd_soc_rtdcom_lookup(runtime, AFE_PCM_NAME);
+		if (cmpnt_afe) {
+			dev_info(rtd->dev, "component->name: %s\n", cmpnt_afe->name);
+			break;
+		}
+	}
+
+	if (cmpnt_afe && !pm_runtime_active(cmpnt_afe->dev)) {
+		dev_err(rtd->dev, "afe pm runtime is not active!!\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct snd_soc_ops mt8196_sof_be_ops = {
+	.hw_params = mt8196_sof_be_hw_params,
+};
+
+static const struct sof_conn_stream g_sof_conn_streams[] = {
+	{
+		.sof_link = "AFE_SOF_DL1",
+		.sof_dma = SOF_DMA_DL1,
+		.stream_dir = SNDRV_PCM_STREAM_PLAYBACK
+	},
+	{
+		.sof_link = "AFE_SOF_DL_24CH",
+		.sof_dma = SOF_DMA_DL_24CH,
+		.stream_dir = SNDRV_PCM_STREAM_PLAYBACK
+	},
+	{
+		.sof_link = "AFE_SOF_UL0",
+		.sof_dma = SOF_DMA_UL0,
+		.stream_dir = SNDRV_PCM_STREAM_CAPTURE
+	},
+	{
+		.sof_link = "AFE_SOF_UL1",
+		.sof_dma = SOF_DMA_UL1,
+		.stream_dir = SNDRV_PCM_STREAM_CAPTURE
+	},
+	{
+		.sof_link = "AFE_SOF_UL2",
+		.sof_dma = SOF_DMA_UL2,
+		.stream_dir = SNDRV_PCM_STREAM_CAPTURE
+	},
+};
+
+/* FE */
+SND_SOC_DAILINK_DEFS(playback1,
+		     DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback_24ch,
+		     DAILINK_COMP_ARRAY(COMP_CPU("DL_24CH")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture0,
+		     DAILINK_COMP_ARRAY(COMP_CPU("UL0")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture1,
+		     DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture2,
+		     DAILINK_COMP_ARRAY(COMP_CPU("UL2")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback_hdmi,
+		     DAILINK_COMP_ARRAY(COMP_CPU("HDMI")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback2,
+		     DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture_cm0,
+		     DAILINK_COMP_ARRAY(COMP_CPU("UL_CM0")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+/* BE */
+SND_SOC_DAILINK_DEFS(ap_dmic,
+		     DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(ap_dmic_ch34,
+		     DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC_CH34")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(ap_dmic_multich,
+		     DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC_MULTICH")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(i2sin6,
+		     DAILINK_COMP_ARRAY(COMP_CPU("I2SIN6")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(i2sout3,
+		     DAILINK_COMP_ARRAY(COMP_CPU("I2SOUT3")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(i2sout4,
+		     DAILINK_COMP_ARRAY(COMP_CPU("I2SOUT4")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(i2sout6,
+		     DAILINK_COMP_ARRAY(COMP_CPU("I2SOUT6")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(tdm_dptx,
+		     DAILINK_COMP_ARRAY(COMP_CPU("TDM_DPTX")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(AFE_SOF_DL_24CH,
+		     DAILINK_COMP_ARRAY(COMP_CPU("SOF_DL_24CH")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(AFE_SOF_DL1,
+		     DAILINK_COMP_ARRAY(COMP_CPU("SOF_DL1")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(AFE_SOF_UL0,
+		     DAILINK_COMP_ARRAY(COMP_CPU("SOF_UL0")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(AFE_SOF_UL1,
+		     DAILINK_COMP_ARRAY(COMP_CPU("SOF_UL1")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(AFE_SOF_UL2,
+		     DAILINK_COMP_ARRAY(COMP_CPU("SOF_UL2")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+static struct snd_soc_dai_link mt8196_nau8825_dai_links[] = {
+	/*
+	 * The SOF topology expects PCM streams 0~4 to be available
+	 * for the SOF PCM streams. Put the SOF BE definitions here
+	 * so that the PCM device numbers are skipped over.
+	 * (BE dailinks do not have PCM devices created.)
+	 */
+	{
+		.name = "AFE_SOF_DL_24CH",
+		.no_pcm = 1,
+		.playback_only = 1,
+		.ops = &mt8196_sof_be_ops,
+		SND_SOC_DAILINK_REG(AFE_SOF_DL_24CH),
+	},
+	{
+		.name = "AFE_SOF_DL1",
+		.no_pcm = 1,
+		.playback_only = 1,
+		.ops = &mt8196_sof_be_ops,
+		SND_SOC_DAILINK_REG(AFE_SOF_DL1),
+	},
+	{
+		.name = "AFE_SOF_UL0",
+		.no_pcm = 1,
+		.capture_only = 1,
+		.ops = &mt8196_sof_be_ops,
+		SND_SOC_DAILINK_REG(AFE_SOF_UL0),
+	},
+	{
+		.name = "AFE_SOF_UL1",
+		.no_pcm = 1,
+		.capture_only = 1,
+		.ops = &mt8196_sof_be_ops,
+		SND_SOC_DAILINK_REG(AFE_SOF_UL1),
+	},
+	{
+		.name = "AFE_SOF_UL2",
+		.no_pcm = 1,
+		.capture_only = 1,
+		.ops = &mt8196_sof_be_ops,
+		SND_SOC_DAILINK_REG(AFE_SOF_UL2),
+	},
+	/* Front End DAI links */
+	{
+		.name = "HDMI_FE",
+		.stream_name = "HDMI Playback",
+		.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+			    SND_SOC_DPCM_TRIGGER_PRE},
+		.dynamic = 1,
+		.playback_only = 1,
+		SND_SOC_DAILINK_REG(playback_hdmi),
+	},
+	{
+		.name = "DL2_FE",
+		.stream_name = "DL2 Playback",
+		.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+			    SND_SOC_DPCM_TRIGGER_PRE},
+		.dynamic = 1,
+		.playback_only = 1,
+		SND_SOC_DAILINK_REG(playback2),
+	},
+	{
+		.name = "UL_CM0_FE",
+		.stream_name = "UL_CM0 Capture",
+		.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+			    SND_SOC_DPCM_TRIGGER_PRE},
+		.dynamic = 1,
+		.capture_only = 1,
+		SND_SOC_DAILINK_REG(capture_cm0),
+	},
+	{
+		.name = "DL_24CH_FE",
+		.stream_name = "DL_24CH Playback",
+		.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+				SND_SOC_DPCM_TRIGGER_PRE},
+		.dynamic = 1,
+		.playback_only = 1,
+		SND_SOC_DAILINK_REG(playback_24ch),
+	},
+	{
+		.name = "DL1_FE",
+		.stream_name = "DL1 Playback",
+		.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+				SND_SOC_DPCM_TRIGGER_PRE},
+		.dynamic = 1,
+		.playback_only = 1,
+		SND_SOC_DAILINK_REG(playback1),
+	},
+	{
+		.name = "UL0_FE",
+		.stream_name = "UL0 Capture",
+		.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+				SND_SOC_DPCM_TRIGGER_PRE},
+		.dynamic = 1,
+		.capture_only = 1,
+		SND_SOC_DAILINK_REG(capture0),
+	},
+	{
+		.name = "UL1_FE",
+		.stream_name = "UL1 Capture",
+		.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+				SND_SOC_DPCM_TRIGGER_PRE},
+		.dynamic = 1,
+		.capture_only = 1,
+		SND_SOC_DAILINK_REG(capture1),
+	},
+	{
+		.name = "UL2_FE",
+		.stream_name = "UL2 Capture",
+		.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+				SND_SOC_DPCM_TRIGGER_PRE},
+		.dynamic = 1,
+		.capture_only = 1,
+		SND_SOC_DAILINK_REG(capture2),
+	},
+	/* Back End DAI links */
+	{
+		.name = "I2SIN6_BE",
+		.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
+			| SND_SOC_DAIFMT_GATED,
+		.ops = &mt8196_nau8825_i2s_ops,
+		.no_pcm = 1,
+		.capture_only = 1,
+		.ignore_suspend = 1,
+		.be_hw_params_fixup = mt8196_i2s_hw_params_fixup,
+		SND_SOC_DAILINK_REG(i2sin6),
+	},
+	{
+		.name = "I2SOUT4_BE",
+		.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
+			| SND_SOC_DAIFMT_GATED,
+		.ops = &mt8196_nau8825_i2s_ops,
+		.no_pcm = 1,
+		.playback_only = 1,
+		.ignore_suspend = 1,
+		.ignore_pmdown_time = 1,
+		.be_hw_params_fixup = mt8196_i2s_hw_params_fixup,
+		SND_SOC_DAILINK_REG(i2sout4),
+	},
+	{
+		.name = "I2SOUT6_BE",
+		.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
+			| SND_SOC_DAIFMT_GATED,
+		.ops = &mt8196_nau8825_i2s_ops,
+		.no_pcm = 1,
+		.playback_only = 1,
+		.ignore_suspend = 1,
+		.be_hw_params_fixup = mt8196_i2s_hw_params_fixup,
+		SND_SOC_DAILINK_REG(i2sout6),
+	},
+	{
+		.name = "AP_DMIC_BE",
+		.no_pcm = 1,
+		.capture_only = 1,
+		.ignore_suspend = 1,
+		SND_SOC_DAILINK_REG(ap_dmic),
+	},
+	{
+		.name = "AP_DMIC_CH34_BE",
+		.no_pcm = 1,
+		.capture_only = 1,
+		.ignore_suspend = 1,
+		SND_SOC_DAILINK_REG(ap_dmic_ch34),
+	},
+	{
+		.name = "AP_DMIC_MULTICH_BE",
+		.no_pcm = 1,
+		.capture_only = 1,
+		.ignore_suspend = 1,
+		SND_SOC_DAILINK_REG(ap_dmic_multich),
+	},
+	{
+		.name = "TDM_DPTX_BE",
+		.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
+			| SND_SOC_DAIFMT_GATED,
+		.ops = &mt8196_dptx_ops,
+		.be_hw_params_fixup = mt8196_dptx_hw_params_fixup,
+		.no_pcm = 1,
+		.playback_only = 1,
+		.ignore_suspend = 1,
+		SND_SOC_DAILINK_REG(tdm_dptx),
+	},
+	{
+		.name = "I2SOUT3_BE",
+		.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
+			| SND_SOC_DAIFMT_GATED,
+		.ops = &mt8196_nau8825_i2s_ops,
+		.no_pcm = 1,
+		.playback_only = 1,
+		.ignore_suspend = 1,
+		SND_SOC_DAILINK_REG(i2sout3),
+	},
+};
+
+static int mt8196_dumb_amp_init(struct snd_soc_pcm_runtime *rtd)
+{
+	struct snd_soc_card *card = rtd->card;
+	int ret = 0;
+
+	ret = snd_soc_dapm_new_controls(&card->dapm, mt8196_dumb_spk_widgets,
+					ARRAY_SIZE(mt8196_dumb_spk_widgets));
+	if (ret) {
+		dev_err(rtd->dev, "unable to add Dumb Speaker dapm, ret %d\n", ret);
+		return ret;
+	}
+
+	ret = snd_soc_add_card_controls(card, mt8196_dumb_spk_controls,
+					ARRAY_SIZE(mt8196_dumb_spk_controls));
+	if (ret) {
+		dev_err(rtd->dev, "unable to add Dumb card controls, ret %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int mt8196_dptx_codec_init(struct snd_soc_pcm_runtime *rtd)
+{
+	struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(rtd->card);
+	struct snd_soc_jack *jack = &soc_card_data->card_data->jacks[MT8196_JACK_DP];
+	struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component;
+	int ret = 0;
+
+	ret = snd_soc_card_jack_new_pins(rtd->card, "DP Jack", SND_JACK_LINEOUT,
+					 jack, mt8196_dp_jack_pins,
+					 ARRAY_SIZE(mt8196_dp_jack_pins));
+	if (ret) {
+		dev_err(rtd->dev, "new jack failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = snd_soc_component_set_jack(component, jack, NULL);
+	if (ret) {
+		dev_err(rtd->dev, "set jack failed on %s (ret=%d)\n",
+			component->name, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int mt8196_hdmi_codec_init(struct snd_soc_pcm_runtime *rtd)
+{
+	struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(rtd->card);
+	struct snd_soc_jack *jack = &soc_card_data->card_data->jacks[MT8196_JACK_HDMI];
+	struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component;
+	int ret = 0;
+
+	ret = snd_soc_card_jack_new_pins(rtd->card, "HDMI Jack", SND_JACK_LINEOUT,
+					 jack, mt8196_hdmi_jack_pins,
+					 ARRAY_SIZE(mt8196_hdmi_jack_pins));
+	if (ret) {
+		dev_err(rtd->dev, "new jack failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = snd_soc_component_set_jack(component, jack, NULL);
+	if (ret) {
+		dev_err(rtd->dev, "set jack failed on %s (ret=%d)\n",
+			component->name, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int mt8196_headset_codec_init(struct snd_soc_pcm_runtime *rtd)
+{
+	struct snd_soc_card *card = rtd->card;
+	struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(card);
+	struct snd_soc_jack *jack = &soc_card_data->card_data->jacks[MT8196_JACK_HEADSET];
+	struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component;
+	int ret;
+	int type;
+
+	ret = snd_soc_dapm_new_controls(&card->dapm, mt8196_nau8825_widgets,
+					ARRAY_SIZE(mt8196_nau8825_widgets));
+	if (ret) {
+		dev_err(rtd->dev, "unable to add nau8825 card widget, ret %d\n", ret);
+		return ret;
+	}
+
+	ret = snd_soc_add_card_controls(card, mt8196_nau8825_controls,
+					ARRAY_SIZE(mt8196_nau8825_controls));
+	if (ret) {
+		dev_err(rtd->dev, "unable to add nau8825 card controls, ret %d\n", ret);
+		return ret;
+	}
+
+	ret = snd_soc_card_jack_new_pins(rtd->card, "Headset Jack",
+					 SND_JACK_HEADSET | SND_JACK_BTN_0 |
+					 SND_JACK_BTN_1 | SND_JACK_BTN_2 |
+					 SND_JACK_BTN_3,
+					 jack,
+					 nau8825_jack_pins,
+					 ARRAY_SIZE(nau8825_jack_pins));
+	if (ret) {
+		dev_err(rtd->dev, "Headset Jack creation failed: %d\n", ret);
+		return ret;
+	}
+
+	snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
+	snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
+	snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
+	snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
+
+	type = SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 | SND_JACK_BTN_3;
+	ret = snd_soc_component_set_jack(component, jack, (void *)&type);
+
+	if (ret) {
+		dev_err(rtd->dev, "Headset Jack call-back failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+};
+
+static void mt8196_headset_codec_exit(struct snd_soc_pcm_runtime *rtd)
+{
+	struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component;
+
+	snd_soc_component_set_jack(component, NULL, NULL);
+}
+
+static int mt8196_nau8825_hw_params(struct snd_pcm_substream *substream,
+				    struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+	struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
+	unsigned int rate = params_rate(params);
+	unsigned int bit_width = params_width(params);
+	int clk_freq, ret;
+
+	clk_freq = rate * 2 * bit_width;
+
+	/* Configure clock for codec */
+	ret = snd_soc_dai_set_sysclk(codec_dai, NAU8825_CLK_FLL_BLK, 0,
+				     SND_SOC_CLOCK_IN);
+	if (ret < 0) {
+		dev_err(codec_dai->dev, "can't set BCLK clock %d\n", ret);
+		return ret;
+	}
+
+	/* Configure pll for codec */
+	ret = snd_soc_dai_set_pll(codec_dai, 0, 0, clk_freq,
+				  params_rate(params) * 256);
+	if (ret < 0) {
+		dev_err(codec_dai->dev, "can't set BCLK: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct snd_soc_ops mt8196_nau8825_ops = {
+	.hw_params = mt8196_nau8825_hw_params,
+};
+
+static int mt8196_rt5682s_i2s_hw_params(struct snd_pcm_substream *substream,
+					struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_card *card = rtd->card;
+	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+	struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
+	unsigned int rate = params_rate(params);
+	int bitwidth;
+	int ret;
+
+	bitwidth = snd_pcm_format_width(params_format(params));
+	if (bitwidth < 0) {
+		dev_err(card->dev, "invalid bit width: %d\n", bitwidth);
+		return bitwidth;
+	}
+
+	ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x00, 0x0, 0x2, bitwidth);
+	if (ret) {
+		dev_err(card->dev, "failed to set tdm slot\n");
+		return ret;
+	}
+
+	ret = snd_soc_dai_set_pll(codec_dai, RT5682S_PLL1, RT5682S_PLL_S_BCLK1,
+				  rate * 32, rate * 512);
+	if (ret) {
+		dev_err(card->dev, "failed to set pll\n");
+		return ret;
+	}
+
+	dev_info(card->dev, "%s set mclk rate: %d\n", __func__, rate * 512);
+
+	ret = snd_soc_dai_set_sysclk(codec_dai, RT5682S_SCLK_S_MCLK,
+				     rate * 512, SND_SOC_CLOCK_IN);
+	if (ret) {
+		dev_err(card->dev, "failed to set sysclk\n");
+		return ret;
+	}
+
+	return snd_soc_dai_set_sysclk(cpu_dai, 0, rate * 512,
+				      SND_SOC_CLOCK_OUT);
+}
+
+static const struct snd_soc_ops mt8196_rt5682s_i2s_ops = {
+	.hw_params = mt8196_rt5682s_i2s_hw_params,
+};
+
+static int mt8196_nau8825_soc_card_probe(struct mtk_soc_card_data *soc_card_data, bool legacy)
+{
+	struct snd_soc_card *card = soc_card_data->card_data->card;
+	struct snd_soc_dai_link *dai_link;
+	bool init_nau8825 = false;
+	bool init_rt5682s = false;
+	bool init_rt5650 = false;
+	bool init_dumb = false;
+	int i;
+
+	dev_info(card->dev, "legacy: %d\n", legacy);
+
+	for_each_card_prelinks(card, i, dai_link) {
+		if (strcmp(dai_link->name, "TDM_DPTX_BE") == 0) {
+			if (dai_link->num_codecs &&
+			    strcmp(dai_link->codecs->dai_name, "snd-soc-dummy-dai"))
+				dai_link->init = mt8196_dptx_codec_init;
+		} else if (strcmp(dai_link->name, "I2SOUT3_BE") == 0) {
+			if (dai_link->num_codecs &&
+			    strcmp(dai_link->codecs->dai_name, "snd-soc-dummy-dai"))
+				dai_link->init = mt8196_hdmi_codec_init;
+		} else if (strcmp(dai_link->name, "I2SOUT6_BE") == 0 ||
+			   strcmp(dai_link->name, "I2SIN6_BE") == 0) {
+			if (!strcmp(dai_link->codecs->dai_name, NAU8825_CODEC_DAI)) {
+				dai_link->ops = &mt8196_nau8825_ops;
+				if (!init_nau8825) {
+					dai_link->init = mt8196_headset_codec_init;
+					dai_link->exit = mt8196_headset_codec_exit;
+					init_nau8825 = true;
+				}
+			} else if (!strcmp(dai_link->codecs->dai_name, RT5682S_CODEC_DAI)) {
+				dai_link->ops = &mt8196_rt5682s_i2s_ops;
+				if (!init_rt5682s) {
+					dai_link->init = mt8196_headset_codec_init;
+					dai_link->exit = mt8196_headset_codec_exit;
+					init_rt5682s = true;
+				}
+			} else if (!strcmp(dai_link->codecs->dai_name, RT5650_CODEC_DAI)) {
+				dai_link->ops = &mt8196_rt5682s_i2s_ops;
+				if (!init_rt5650) {
+					dai_link->init = mt8196_headset_codec_init;
+					dai_link->exit = mt8196_headset_codec_exit;
+					init_rt5650 = true;
+				}
+			} else {
+				if (strcmp(dai_link->codecs->dai_name, "snd-soc-dummy-dai")) {
+					if (!init_dumb) {
+						dai_link->init = mt8196_dumb_amp_init;
+						init_dumb = true;
+					}
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+
+static const struct mtk_sof_priv mt8196_sof_priv = {
+	.conn_streams = g_sof_conn_streams,
+	.num_streams = ARRAY_SIZE(g_sof_conn_streams),
+};
+
+static struct snd_soc_card mt8196_nau8825_soc_card = {
+	.owner = THIS_MODULE,
+	.dai_link = mt8196_nau8825_dai_links,
+	.num_links = ARRAY_SIZE(mt8196_nau8825_dai_links),
+	.dapm_widgets = mt8196_nau8825_card_widgets,
+	.num_dapm_widgets = ARRAY_SIZE(mt8196_nau8825_card_widgets),
+	.dapm_routes = mt8196_nau8825_card_routes,
+	.num_dapm_routes = ARRAY_SIZE(mt8196_nau8825_card_routes),
+	.controls = mt8196_nau8825_card_controls,
+	.num_controls = ARRAY_SIZE(mt8196_nau8825_card_controls),
+};
+
+static const struct mtk_soundcard_pdata mt8196_nau8825_card = {
+	.card_name = "mt8196_nau8825",
+	.card_data = &(struct mtk_platform_card_data) {
+		.card = &mt8196_nau8825_soc_card,
+		.num_jacks = MT8196_JACK_MAX,
+		.flags = NAU8825_HS_PRESENT
+	},
+	.sof_priv = &mt8196_sof_priv,
+	.soc_probe = mt8196_nau8825_soc_card_probe,
+};
+
+static const struct mtk_soundcard_pdata mt8196_rt5682s_card = {
+	.card_name = "mt8196_rt5682s",
+	.card_data = &(struct mtk_platform_card_data) {
+		.card = &mt8196_nau8825_soc_card,
+		.num_jacks = MT8196_JACK_MAX,
+		.flags = RT5682S_HS_PRESENT
+	},
+	.sof_priv = &mt8196_sof_priv,
+	.soc_probe = mt8196_nau8825_soc_card_probe,
+};
+
+static const struct mtk_soundcard_pdata mt8196_rt5650_card = {
+	.card_name = "mt8196_rt5650",
+	.card_data = &(struct mtk_platform_card_data) {
+		.card = &mt8196_nau8825_soc_card,
+		.num_jacks = MT8196_JACK_MAX,
+		.flags = RT5650_HS_PRESENT
+	},
+	.sof_priv = &mt8196_sof_priv,
+	.soc_probe = mt8196_nau8825_soc_card_probe,
+};
+
+static const struct of_device_id mt8196_nau8825_dt_match[] = {
+	{.compatible = "mediatek,mt8196-nau8825-sound", .data = &mt8196_nau8825_card,},
+	{.compatible = "mediatek,mt8196-rt5682s-sound", .data = &mt8196_rt5682s_card,},
+	{.compatible = "mediatek,mt8196-rt5650-sound", .data = &mt8196_rt5650_card,},
+	{}
+};
+MODULE_DEVICE_TABLE(of, mt8196_nau8825_dt_match);
+
+static struct platform_driver mt8196_nau8825_driver = {
+	.driver = {
+		.name = "mt8196-nau8825",
+		.of_match_table = mt8196_nau8825_dt_match,
+		.pm = &snd_soc_pm_ops,
+	},
+	.probe = mtk_soundcard_common_probe,
+};
+module_platform_driver(mt8196_nau8825_driver);
+
+/* Module information */
+MODULE_DESCRIPTION("MT8196 nau8825 ALSA SoC machine driver");
+MODULE_AUTHOR("Darren Ye <darren.ye at mediatek.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("mt8196 nau8825 soc card");
+
-- 
2.45.2



From darren.ye at mediatek.com  Wed May 14 01:11:12 2025
From: darren.ye at mediatek.com (Darren.Ye)
Date: Wed, 14 May 2025 16:11:12 +0800
Subject: [PATCH v3 10/10] ASoC: dt-bindings: mediatek,mt8196-nau8825: add mt8196-nau8825 document
In-Reply-To: <20250514081125.24475-1-darren.ye@mediatek.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
Message-ID: <20250514081125.24475-11-darren.ye@mediatek.com>

From: Darren Ye <darren.ye at mediatek.com>

Add document for mt8196 board with nau8825.

Signed-off-by: Darren Ye <darren.ye at mediatek.com>
---
 .../sound/mediatek,mt8196-nau8825.yaml        | 115 ++++++++++++++++++
 1 file changed, 115 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt8196-nau8825.yaml

diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8196-nau8825.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8196-nau8825.yaml
new file mode 100644
index 000000000000..8f9aa8b816e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mediatek,mt8196-nau8825.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/mediatek,mt8196-nau8825.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT8196 ASoC sound card
+
+maintainers:
+  - Darren Ye <darren.ye at mediatek.com>
+
+allOf:
+  - $ref: sound-card-common.yaml#
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt8196-nau8825-sound
+      - mediatek,mt8196-rt5682s-sound
+      - mediatek,mt8196-rt5650-sound
+
+  audio-routing:
+    description:
+      Valid names could be the input or output widgets of audio components,
+      power supplies, MicBias of codec and the software switch.
+
+  mediatek,platform:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: The phandle of MT8188 ASoC platform.
+
+  mediatek,adsp:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      The phandle of the MT8188 ADSP platform, which is the optional Audio DSP
+      hardware that provides additional audio functionalities if present.
+      The AFE will link to ADSP when the phandle is provided.
+
+patternProperties:
+  "^dai-link-[0-9]+$":
+    type: object
+    description:
+      Container for dai-link level properties and CODEC sub-nodes.
+
+    properties:
+      link-name:
+        description:
+          This property corresponds to the name of the BE dai-link to which
+          we are going to update parameters in this node.
+        items:
+          enum:
+            - TDM_DPTX_BE
+            - I2SOUT6_BE
+            - I2SIN6_BE
+            - I2SOUT4_BE
+            - I2SOUT3_BE
+
+      codec:
+        description: Holds subnode which indicates codec dai.
+        type: object
+        additionalProperties: false
+        properties:
+          sound-dai:
+            minItems: 1
+            maxItems: 2
+        required:
+          - sound-dai
+
+      dai-format:
+        description: audio format.
+        items:
+          enum:
+            - i2s
+            - right_j
+            - left_j
+            - dsp_a
+            - dsp_b
+
+      mediatek,clk-provider:
+        $ref: /schemas/types.yaml#/definitions/string
+        description: Indicates dai-link clock master.
+        items:
+          enum:
+            - cpu
+            - codec
+
+    additionalProperties: false
+
+    required:
+      - link-name
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - mediatek,platform
+
+examples:
+  - |
+    sound {
+        compatible = "mediatek,mt8196-nau8825-sound";
+        model = "mt8196-nau8825";
+        mediatek,platform = <&afe>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&aud_pins_default>;
+        dai-link-0 {
+            link-name = "I2SOUT6_BE";
+            dai-format = "i2s";
+            mediatek,clk-provider = "cpu";
+            codec {
+                sound-dai = <&nau8825>;
+            };
+        };
+    };
+
+...
-- 
2.45.2



From broonie at kernel.org  Wed May 14 01:17:30 2025
From: broonie at kernel.org (Mark Brown)
Date: Wed, 14 May 2025 10:17:30 +0200
Subject: [PATCH v3 04/10] ASoC: mediatek: mt8196: support ADDA in
 platform driver
In-Reply-To: <20250514081125.24475-5-darren.ye@mediatek.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
 <20250514081125.24475-5-darren.ye@mediatek.com>
Message-ID: <aCRRmk2Vqplbbusn@finisterre.sirena.org.uk>

On Wed, May 14, 2025 at 04:11:06PM +0800, Darren.Ye wrote:

> +#include <linux/regmap.h>
> +#include <linux/delay.h>
> +#include "mt8196-afe-clk.h"
> +#include "mt8196-afe-common.h"
> +#include "mt8196-interconnection.h"
> +
> +#define MTKAIF4

This define is there unconditionally, what's it for?
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From julien.massot at collabora.com  Wed May 14 01:19:55 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Wed, 14 May 2025 10:19:55 +0200
Subject: [PATCH v2 0/3] mt8395/mt6359: Fix several dtb-check errors
Message-ID: <20250514-mt8395-dtb-errors-v2-0-d67b9077c59a@collabora.com>

Hi,
This patch series addresses several dtb-check errors reported for the mt8395-genio-1200-evk.dtb and mt8395-radxa-nio-12l.dtb device trees.

The fixes include:
- Adding the missing #sound-dai-cells property in the mt6397 binding.
- Allowing 5 interrupts in the MediaTek IOMMU binding to support MT8395 properly.
- Renaming the rtc node to match expected schema naming.

Signed-off-by: Julien Massot <julien.massot at collabora.com>
---
Changes in v2:
- Patch 1/3: Add ref to dai-common as suggested by Krzysztof
- Patch 2/3: Only accept 5 interrupts for mt8195 infra IOMMU
- Patch 3/3: Add missing S-o-B
- I did not include the 'Reviewed-by' from Angelo and Nicolas since the 1/3 and
2/3 changed from v1
- Link to v1: https://lore.kernel.org/r/20250505-mt8395-dtb-errors-v1-0-9c4714dcdcdb at collabora.com

---
Julien Massot (3):
      dt-bindings: mfd: mediatek: mt6397: Add #sound-dai-cells property
      dt-bindings: iommu: mediatek: Support 5 IRQs on MT8195 infra IOMMU
      arm64: dts: mt6359: Rename RTC node to match binding expectations

 .../devicetree/bindings/iommu/mediatek,iommu.yaml      | 18 +++++++++++++++++-
 .../devicetree/bindings/mfd/mediatek,mt6397.yaml       |  6 ++++++
 arch/arm64/boot/dts/mediatek/mt6359.dtsi               |  2 +-
 3 files changed, 24 insertions(+), 2 deletions(-)
---
base-commit: ed61cb3d78d585209ec775933078e268544fe9a4
change-id: 20250505-mt8395-dtb-errors-0847ffc12f44

Best regards,
-- 
Julien Massot <julien.massot at collabora.com>



From julien.massot at collabora.com  Wed May 14 01:19:56 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Wed, 14 May 2025 10:19:56 +0200
Subject: [PATCH v2 1/3] dt-bindings: mfd: mediatek: mt6397: Add
 #sound-dai-cells property
In-Reply-To: <20250514-mt8395-dtb-errors-v2-0-d67b9077c59a@collabora.com>
References: <20250514-mt8395-dtb-errors-v2-0-d67b9077c59a@collabora.com>
Message-ID: <20250514-mt8395-dtb-errors-v2-1-d67b9077c59a@collabora.com>

The 'mt6359.dtsi' file already uses the '#sound-dai-cells' property.
Add the corresponding property to the binding to fix the following
dtb-check error:

mediatek/mt8395-radxa-nio-12l.dtb: pmic: '#sound-dai-cells', 'mt6359rtc' do not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6397.yaml#

Fixes: 9bc8353be720 ("arm64: dts: mt6359: Add #sound-dai-cells property")
Signed-off-by: Julien Massot <julien.massot at collabora.com>
---
 Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
index 6a89b479d10fad3c8b61cab5a3af1453baca4d1a..9580c4ec1ae00f1dd1182357d8b0a5035a1b7f82 100644
--- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
+++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
@@ -30,6 +30,9 @@ description: |
   See the following for pwrap node definitions:
   Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
 
+allOf:
+  - $ref: /schemas/sound/dai-common.yaml#
+
 properties:
   compatible:
     oneOf:
@@ -53,6 +56,9 @@ properties:
   "#interrupt-cells":
     const: 2
 
+  '#sound-dai-cells':
+    const: 1
+
   rtc:
     type: object
     $ref: /schemas/rtc/rtc.yaml#

-- 
2.49.0



From julien.massot at collabora.com  Wed May 14 01:19:57 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Wed, 14 May 2025 10:19:57 +0200
Subject: [PATCH v2 2/3] dt-bindings: iommu: mediatek: Support 5 IRQs on
 MT8195 infra IOMMU
In-Reply-To: <20250514-mt8395-dtb-errors-v2-0-d67b9077c59a@collabora.com>
References: <20250514-mt8395-dtb-errors-v2-0-d67b9077c59a@collabora.com>
Message-ID: <20250514-mt8395-dtb-errors-v2-2-d67b9077c59a@collabora.com>

The MT8195 Infra IOMMU is currently the only Mediatek IOMMU instance that
uses five interrupts instead of one.

Update the binding to allow either one or five interrupts, depending on
the compatible string. This avoids dtbs_check errors on platforms like
the Radxa NIO 12L using the MT8395 SoC:

mediatek/mt8395-radxa-nio-12l.dtb: infra-iommu at 10315000: interrupts:
[[0, 795, 4, 0], [0, 796, 4, 0], [0, 797, 4, 0], [0, 798, 4, 0], [0, 799, 4, 0]] is too long

Fixes: 3b5838d1d82e3 ("arm64: dts: mt8195: Add iommu and smi nodes")
Signed-off-by: Julien Massot <julien.massot at collabora.com>
---
 .../devicetree/bindings/iommu/mediatek,iommu.yaml      | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index 75750c64157c868725c087500ac81be4e282c829..5068617a5146c8a8d61234d83c19d2848d5e708f 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -97,7 +97,8 @@ properties:
     maxItems: 1
 
   interrupts:
-    maxItems: 1
+    minItems: 1
+    maxItems: 5
 
   clocks:
     items:
@@ -201,6 +202,21 @@ allOf:
       required:
         - mediatek,infracfg
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - mediatek,mt8195-iommu-infra
+    then:
+      properties:
+        interrupts:
+          minItems: 5
+    else:
+      properties:
+        interrupts:
+          maxItems: 1
+
   - if: # The IOMMUs don't have larbs.
       not:
         properties:

-- 
2.49.0



From julien.massot at collabora.com  Wed May 14 01:19:58 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Wed, 14 May 2025 10:19:58 +0200
Subject: [PATCH v2 3/3] arm64: dts: mt6359: Rename RTC node to match
 binding expectations
In-Reply-To: <20250514-mt8395-dtb-errors-v2-0-d67b9077c59a@collabora.com>
References: <20250514-mt8395-dtb-errors-v2-0-d67b9077c59a@collabora.com>
Message-ID: <20250514-mt8395-dtb-errors-v2-3-d67b9077c59a@collabora.com>

Rename the node 'mt6359rtc' to 'rtc', as required by the binding.

Fix the following dtb-check error:

mediatek/mt8395-radxa-nio-12l.dtb: pmic: 'mt6359rtc' do not match
any of the regexes: 'pinctrl-[0-9]+'

Fixes: 3b7d143be4b7 ("arm64: dts: mt6359: add PMIC MT6359 related nodes")
Signed-off-by: Julien Massot <julien.massot at collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6359.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi
index 0c479404b3fe3adc9789386e34bda4dc580b5abd..467d8a4c2aa7f16ade92a287ecdeed5089302045 100644
--- a/arch/arm64/boot/dts/mediatek/mt6359.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi
@@ -300,7 +300,7 @@ mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub {
 			};
 		};
 
-		mt6359rtc: mt6359rtc {
+		mt6359rtc: rtc {
 			compatible = "mediatek,mt6358-rtc";
 		};
 	};

-- 
2.49.0



From angelogioacchino.delregno at collabora.com  Wed May 14 01:23:33 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 14 May 2025 10:23:33 +0200
Subject: [GIT,PULL,1/2] MediaTek ARM64 DTS updates for v6.16
In-Reply-To: <7e8718b0-df78-44a6-a102-89529d6abcce@app.fastmail.com>
References: <20250506091736.125733-1-angelogioacchino.delregno@collabora.com>
 <7e8718b0-df78-44a6-a102-89529d6abcce@app.fastmail.com>
Message-ID: <ed7ad534-a517-4005-b61e-c8f2e82f1b27@collabora.com>

Il 09/05/25 22:54, Arnd Bergmann ha scritto:
> On Tue, May 6, 2025, at 11:17, AngeloGioacchino Del Regno wrote:
> 
>>     - Since SCP firmwares are available on linux-firmware, the
>>       necessary nodes for the dual-core SCP were added to devicetree
>>       along with the firmware-name property in mt8390-genio-common,
>>       enabling hardware video encoders and decoders on the MediaTek
>>       Genio 510 and Genio 700 EVKs.
> 
> This looks wrong to me: the devicetree should never care about
> particular file names in a Linux repository.
> 
> Usually what happens is that the device driver must work with
> a particular firmware version, so the driver is the one that
> constructs a name based on what firmware is knows and what
> hardware it is running on, so a newer version of the driver
> can attempt to load a newer firmware that may be incompatible
> with the old driver.
> 
> The other patches in the branch all look fine to me.
> 
> Can you resend the pull request without these patches and
> try to come up with a different approach?
> 
>       Arnd

Uhm, I'm not sure if there was a misunderstanding - not only the MediaTek
devicetrees do that, but also Qualcomm ones are doing the same with their
adsp, cdsp, modem and adreno zap firmwares...

....not sure, should I drop those commits for now?

Thanks,
Angelo


From broonie at kernel.org  Wed May 14 01:54:15 2025
From: broonie at kernel.org (Mark Brown)
Date: Wed, 14 May 2025 10:54:15 +0200
Subject: [PATCH 0/3] ASoC: mediatek: mt8183-afe-pcm: Shorten source code
In-Reply-To: <20250425082551.1467042-1-wenst@chromium.org>
References: <20250425082551.1467042-1-wenst@chromium.org>
Message-ID: <aCRaN27p32c9gxDN@finisterre.sirena.org.uk>

On Fri, Apr 25, 2025 at 04:25:47PM +0800, Chen-Yu Tsai wrote:

> This series is meant as an example on how to use macros and range cases
> to shorten the MediaTek audio frontend drivers. The drivers have large
> tables describing the registers and register fields for every supported
> audio DMA interface. (Some are actually skipped!) There's a lot of
> duplication which can be eliminated using macros. This should serve as
> a reference for the MT8196 AFE driver that I had commented on.

AngeloGioacchino?
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From broonie at kernel.org  Wed May 14 01:54:37 2025
From: broonie at kernel.org (Mark Brown)
Date: Wed, 14 May 2025 10:54:37 +0200
Subject: [PATCH v2 00/13] ASoC: mediatek: use reserved memory or enable
 buffer pre-allocation
In-Reply-To: <20250424102509.1083185-1-wenst@chromium.org>
References: <20250424102509.1083185-1-wenst@chromium.org>
Message-ID: <aCRaTY76dnaavsrd@finisterre.sirena.org.uk>

On Thu, Apr 24, 2025 at 06:24:54PM +0800, Chen-Yu Tsai wrote:

> This is v2 of what was just a single patch "ASoC: mediatek: re-enable
> buffer pre-allocation on some platforms". Link to v1:
> 
>     https://lore.kernel.org/all/20250401085659.1222008-1-wenst at chromium.org/
> 
> Angelo requested that these platforms use reserved memory regions if
> possible, and fall back to pre-allocated buffers only if that fails,
> to align with other MediaTek SoCs / platforms that already use reserved
> memory. The series covers MediaTek's MT8173, MT8183, MT8186, and MT8192
> SoCs.

AngeloGioacchino?
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From Darren.Ye at mediatek.com  Wed May 14 01:58:42 2025
From: Darren.Ye at mediatek.com (=?utf-8?B?RGFycmVuIFllICjlj7bpo54p?=)
Date: Wed, 14 May 2025 08:58:42 +0000
Subject: [PATCH v3 04/10] ASoC: mediatek: mt8196: support ADDA in platform
 driver
In-Reply-To: <aCRRmk2Vqplbbusn@finisterre.sirena.org.uk>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
	 <20250514081125.24475-5-darren.ye@mediatek.com>
	 <aCRRmk2Vqplbbusn@finisterre.sirena.org.uk>
Message-ID: <9a6602b1e185403a0e21e6d6ce7887de0136bcb6.camel@mediatek.com>

On Wed, 2025-05-14 at 10:17 +0200, Mark Brown wrote:
> On Wed, May 14, 2025 at 04:11:06PM +0800, Darren.Ye wrote:
> 
> > +#include <linux/regmap.h>
> > +#include <linux/delay.h>
> > +#include "mt8196-afe-clk.h"
> > +#include "mt8196-afe-common.h"
> > +#include "mt8196-interconnection.h"
> > +
> > +#define MTKAIF4
> 
> This define is there unconditionally, what's it for?

> In order for the DMIC and MTKAIF4 interface to coexist, this define
can be removed.

From angelogioacchino.delregno at collabora.com  Wed May 14 02:22:57 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 14 May 2025 11:22:57 +0200
Subject: [PATCH v2 1/3] dt-bindings: display: mediatek: Add compatibles for MT8188 MDP3
Message-ID: <20250514092259.47035-1-angelogioacchino.delregno@collabora.com>

Add compatible strings for the AAL, COLOR, MERGE and PADDING
hardware components found in MediaTek's MT8188 SoC.

This hardware is compatible with MT8195.

Acked-by: Nicolas Dufresne <nicolas.dufresne at collabora.com>
Acked-by: Chun-Kuang Hu <chunkuang.hu at mediatek.com>
Acked-by: Conor Dooley <conor.dooley at microchip.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
---
 .../bindings/display/mediatek/mediatek,aal.yaml        |  4 ++++
 .../bindings/display/mediatek/mediatek,color.yaml      |  4 ++++
 .../bindings/display/mediatek/mediatek,merge.yaml      |  4 ++++
 .../bindings/display/mediatek/mediatek,padding.yaml    | 10 +++++++---
 4 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
index 5d2089dc596e..daf90ebb39bf 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
@@ -25,6 +25,10 @@ properties:
           - mediatek,mt8173-disp-aal
           - mediatek,mt8183-disp-aal
           - mediatek,mt8195-mdp3-aal
+      - items:
+          - enum:
+              - mediatek,mt8188-mdp3-aal
+          - const: mediatek,mt8195-mdp3-aal
       - items:
           - enum:
               - mediatek,mt2712-disp-aal
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
index 6160439ce4d7..5564f4063317 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
@@ -27,6 +27,10 @@ properties:
           - mediatek,mt8167-disp-color
           - mediatek,mt8173-disp-color
           - mediatek,mt8195-mdp3-color
+      - items:
+          - enum:
+              - mediatek,mt8188-mdp3-color
+          - const: mediatek,mt8195-mdp3-color
       - items:
           - enum:
               - mediatek,mt7623-disp-color
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index 0de9f64f3f84..3798a25402d3 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -25,6 +25,10 @@ properties:
           - mediatek,mt8173-disp-merge
           - mediatek,mt8195-disp-merge
           - mediatek,mt8195-mdp3-merge
+      - items:
+          - enum:
+              - mediatek,mt8188-mdp3-merge
+          - const: mediatek,mt8195-mdp3-merge
       - items:
           - const: mediatek,mt6795-disp-merge
           - const: mediatek,mt8173-disp-merge
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
index be07bbdc54e3..86787866ced0 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
@@ -20,9 +20,13 @@ description:
 
 properties:
   compatible:
-    enum:
-      - mediatek,mt8188-disp-padding
-      - mediatek,mt8195-mdp3-padding
+    oneOf:
+      - enum:
+          - mediatek,mt8188-disp-padding
+          - mediatek,mt8195-mdp3-padding
+      - items:
+          - const: mediatek,mt8188-mdp3-padding
+          - const: mediatek,mt8195-mdp3-padding
 
   reg:
     maxItems: 1
-- 
2.49.0



From angelogioacchino.delregno at collabora.com  Wed May 14 02:22:58 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 14 May 2025 11:22:58 +0200
Subject: [PATCH v2 2/3] dt-bindings: media: mediatek: mdp3: Add compatibles for MT8188 MDP3
In-Reply-To: <20250514092259.47035-1-angelogioacchino.delregno@collabora.com>
References: <20250514092259.47035-1-angelogioacchino.delregno@collabora.com>
Message-ID: <20250514092259.47035-2-angelogioacchino.delregno@collabora.com>

Add compatible strings for the FG, HDR, RSZ, STITCH, TCC, TDSHP
and WROT hardware components found in MediaTek's MT8188 SoC.

This hardware is compatible with MT8195.

Acked-by: Nicolas Dufresne <nicolas.dufresne at collabora.com>
Acked-by: Conor Dooley <conor.dooley at microchip.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
---
 .../devicetree/bindings/media/mediatek,mdp3-fg.yaml       | 8 ++++++--
 .../devicetree/bindings/media/mediatek,mdp3-hdr.yaml      | 8 ++++++--
 .../devicetree/bindings/media/mediatek,mdp3-rsz.yaml      | 1 +
 .../devicetree/bindings/media/mediatek,mdp3-stitch.yaml   | 8 ++++++--
 .../devicetree/bindings/media/mediatek,mdp3-tcc.yaml      | 8 ++++++--
 .../devicetree/bindings/media/mediatek,mdp3-tdshp.yaml    | 8 ++++++--
 .../devicetree/bindings/media/mediatek,mdp3-wrot.yaml     | 1 +
 7 files changed, 32 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
index 03f31b009085..40fda59fa8a8 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
@@ -16,8 +16,12 @@ description:
 
 properties:
   compatible:
-    enum:
-      - mediatek,mt8195-mdp3-fg
+    oneOf:
+      - enum:
+          - mediatek,mt8195-mdp3-fg
+      - items:
+          - const: mediatek,mt8188-mdp3-fg
+          - const: mediatek,mt8195-mdp3-fg
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
index d4609bba6578..d9f926c20220 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
@@ -16,8 +16,12 @@ description:
 
 properties:
   compatible:
-    enum:
-      - mediatek,mt8195-mdp3-hdr
+    oneOf:
+      - enum:
+          - mediatek,mt8195-mdp3-hdr
+      - items:
+          - const: mediatek,mt8188-mdp3-hdr
+          - const: mediatek,mt8195-mdp3-hdr
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
index f5676bec4326..8124c39d73e9 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
@@ -20,6 +20,7 @@ properties:
           - mediatek,mt8183-mdp3-rsz
       - items:
           - enum:
+              - mediatek,mt8188-mdp3-rsz
               - mediatek,mt8195-mdp3-rsz
           - const: mediatek,mt8183-mdp3-rsz
 
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
index d815bea29154..1d8e7e202c42 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
@@ -16,8 +16,12 @@ description:
 
 properties:
   compatible:
-    enum:
-      - mediatek,mt8195-mdp3-stitch
+    oneOf:
+      - enum:
+          - mediatek,mt8195-mdp3-stitch
+      - items:
+          - const: mediatek,mt8188-mdp3-stitch
+          - const: mediatek,mt8195-mdp3-stitch
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
index 14ea556d4f82..6cff7c073ce4 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
@@ -17,8 +17,12 @@ description:
 
 properties:
   compatible:
-    enum:
-      - mediatek,mt8195-mdp3-tcc
+    oneOf:
+      - enum:
+          - mediatek,mt8195-mdp3-tcc
+      - items:
+          - const: mediatek,mt8188-mdp3-tcc
+          - const: mediatek,mt8195-mdp3-tcc
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
index 8ab7f2d8e148..cdfa27324738 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
@@ -16,8 +16,12 @@ description:
 
 properties:
   compatible:
-    enum:
-      - mediatek,mt8195-mdp3-tdshp
+    oneOf:
+      - enum:
+          - mediatek,mt8195-mdp3-tdshp
+      - items:
+          - const: mediatek,mt8188-mdp3-tdshp
+          - const: mediatek,mt8195-mdp3-tdshp
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
index 53a679338402..b6269f4f9fd6 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
@@ -20,6 +20,7 @@ properties:
           - mediatek,mt8183-mdp3-wrot
       - items:
           - enum:
+              - mediatek,mt8188-mdp3-wrot
               - mediatek,mt8195-mdp3-wrot
           - const: mediatek,mt8183-mdp3-wrot
 
-- 
2.49.0



From angelogioacchino.delregno at collabora.com  Wed May 14 02:22:59 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 14 May 2025 11:22:59 +0200
Subject: [PATCH v2 3/3] arm64: dts: mediatek: mt8188: Add all Multimedia Data Path 3 nodes
In-Reply-To: <20250514092259.47035-1-angelogioacchino.delregno@collabora.com>
References: <20250514092259.47035-1-angelogioacchino.delregno@collabora.com>
Message-ID: <20250514092259.47035-3-angelogioacchino.delregno@collabora.com>

Add all of the Multimedia Data Path 3 (MDP3) related nodes
including its Mutex instances, one for each VPPSYS block, and
all of its DMA controllers, Film Grain (FG), HDR, Adaptive Ambient
Light (AAL), Frame Resizer (RSZ), Tone Curve Conversion (TCC),
Two-Dimensional Sharpness (TDSHP), and others, enabling the entire
MDP3 macro-block.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 299 +++++++++++++++++++++++
 1 file changed, 299 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 29d35ca94597..55260357ac66 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -2224,6 +2224,118 @@ vppsys0: syscon at 14000000 {
 			#clock-cells = <1>;
 		};
 
+		dma-controller at 14001000 {
+			compatible = "mediatek,mt8188-mdp3-rdma";
+			reg = <0 0x14001000 0 0x1000>;
+			#dma-cells = <1>;
+			clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
+			mboxes = <&gce0 13 CMDQ_THR_PRIO_1>,
+				 <&gce0 14 CMDQ_THR_PRIO_1>,
+				 <&gce0 16 CMDQ_THR_PRIO_1>,
+				 <&gce0 21 CMDQ_THR_PRIO_1>,
+				 <&gce0 22 CMDQ_THR_PRIO_1>;
+			iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
+			mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
+					      <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
+			mediatek,scp = <&scp>;
+		};
+
+		display at 14002000 {
+			compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
+			reg = <0 0x14002000 0 0x1000>;
+			clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
+		};
+
+		display at 14004000 {
+			compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
+			reg = <0 0x14004000 0 0x1000>;
+			clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
+		};
+
+		display at 14005000 {
+			compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
+			reg = <0 0x14005000 0 0x1000>;
+			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
+		};
+
+		display at 14006000 {
+			compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+			reg = <0 0x14006000 0 0x1000>;
+			clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
+			mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
+					      <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
+		};
+
+		display at 14007000 {
+			compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
+			reg = <0 0x14007000 0 0x1000>;
+			clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
+		};
+
+		display at 14008000 {
+			compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
+			reg = <0 0x14008000 0 0x1000>;
+			interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
+		};
+
+		display at 14009000 {
+			compatible = "mediatek,mt8188-mdp3-ovl", "mediatek,mt8195-mdp3-ovl";
+			reg = <0 0x14009000 0 0x1000>;
+			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
+			iommus = <&vpp_iommu M4U_PORT_L4_MDP_OVL>;
+		};
+
+		display at 1400a000 {
+			compatible = "mediatek,mt8188-mdp3-padding", "mediatek,mt8195-mdp3-padding";
+			reg = <0 0x1400a000 0 0x1000>;
+			clocks = <&vppsys0 CLK_VPP0_PADDING>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
+		};
+
+		display at 1400b000 {
+			compatible = "mediatek,mt8188-mdp3-tcc", "mediatek,mt8195-mdp3-tcc";
+			reg = <0 0x1400b000 0 0x1000>;
+			clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
+		};
+
+		display at 1400c000 {
+			compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+			reg = <0 0x1400c000 0 0x1000>;
+			#dma-cells = <1>;
+			clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
+			iommus = <&vpp_iommu M4U_PORT_L4_MDP_WROT>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
+			mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
+					      <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>;
+		};
+
+		mutex at 1400f000 {
+			compatible = "mediatek,mt8188-vpp-mutex";
+			reg = <0 0x1400f000 0 0x1000>;
+			interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vppsys0 CLK_VPP0_MUTEX>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
+		};
+
 		vpp_smi_common: smi at 14012000 {
 			compatible = "mediatek,mt8188-smi-common-vpp";
 			reg = <0 0x14012000 0 0x1000>;
@@ -2255,6 +2367,184 @@ vpp_iommu: iommu at 14018000 {
 			mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb7 &larb23>;
 		};
 
+		dma-controller at 14f09000 {
+			compatible = "mediatek,mt8188-mdp3-rdma";
+			reg = <0 0x14f09000 0 0x1000>;
+			#dma-cells = <1>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
+			iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
+			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
+					      <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>;
+		};
+
+		dma-controller at 14f0a000 {
+			compatible = "mediatek,mt8188-mdp3-rdma";
+			reg = <0 0x14f0a000 0 0x1000>;
+			#dma-cells = <1>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
+			iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
+			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
+					      <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>;
+		};
+
+		display at 14f0c000 {
+			compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
+			reg = <0 0x14f0c000 0 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
+		};
+
+		display at 14f0d000 {
+			compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
+			reg = <0 0x14f0d000 0 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
+		};
+
+		display at 14f0f000 {
+			compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
+			reg = <0 0x14f0f000 0 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
+		};
+
+		display at 14f10000 {
+			compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
+			reg = <0 0x14f10000 0 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
+		};
+
+		display at 14f12000 {
+			compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
+			reg = <0 0x14f12000 0 0x1000>;
+			interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
+		};
+
+		display at 14f13000 {
+			compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
+			reg = <0 0x14f13000 0 0x1000>;
+			interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
+		};
+
+		display at 14f15000 {
+			compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+			reg = <0 0x14f15000 0 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
+			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
+					      <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
+		};
+
+		display at 14f16000 {
+			compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+			reg = <0 0x14f16000 0 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
+			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
+					      <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
+		};
+
+		display at 14f18000 {
+			compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
+			reg = <0 0x14f18000 0 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
+		};
+
+		display at 14f19000 {
+			compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
+			reg = <0 0x14f19000 0 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
+		};
+
+		display at 14f1a000 {
+			compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge";
+			reg = <0 0x14f1a000 0 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
+		};
+
+		display at 14f1b000 {
+			compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge";
+			reg = <0 0x14f1b000 0 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
+		};
+
+		display at 14f1d000 {
+			compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
+			reg = <0 0x14f1d000 0 0x1000>;
+			interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
+		};
+
+		display at 14f1e000 {
+			compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
+			reg = <0 0x14f1e000 0 0x1000>;
+			interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
+		};
+
+		display at 14f21000 {
+			compatible = "mediatek,mt8188-mdp3-padding",
+				     "mediatek,mt8195-mdp3-padding";
+			reg = <0 0x14f21000 0 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
+		};
+
+		display at 14f22000 {
+			compatible = "mediatek,mt8188-mdp3-padding",
+				     "mediatek,mt8195-mdp3-padding";
+			reg = <0 0x14f22000 0 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
+		};
+
+		display at 14f24000 {
+			compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+			reg = <0 0x14f24000 0 0x1000>;
+			#dma-cells = <1>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
+			iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
+			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
+					      <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>;
+		};
+
+		display at 14f25000 {
+			compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+			reg = <0 0x14f25000 0 0x1000>;
+			#dma-cells = <1>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
+			iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
+			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
+					      <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
+		};
+
 		wpesys: clock-controller at 14e00000 {
 			compatible = "mediatek,mt8188-wpesys";
 			reg = <0 0x14e00000 0 0x1000>;
@@ -2284,6 +2574,15 @@ vppsys1: syscon at 14f00000 {
 			#clock-cells = <1>;
 		};
 
+		mutex at 14f01000 {
+			compatible = "mediatek,mt8188-vpp-mutex";
+			reg = <0 0x14f01000 0 0x1000>;
+			interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
+		};
+
 		larb5: smi at 14f02000 {
 			compatible = "mediatek,mt8188-smi-larb";
 			reg = <0 0x14f02000 0 0x1000>;
-- 
2.49.0



From angelogioacchino.delregno at collabora.com  Wed May 14 02:26:26 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 14 May 2025 11:26:26 +0200
Subject: [PATCH v2 3/3] arm64: dts: mediatek: mt8188: Add all Multimedia
 Data Path 3 nodes
In-Reply-To: <20250514092259.47035-3-angelogioacchino.delregno@collabora.com>
References: <20250514092259.47035-1-angelogioacchino.delregno@collabora.com>
 <20250514092259.47035-3-angelogioacchino.delregno@collabora.com>
Message-ID: <439db3ea-4fb7-4944-b182-222663c09b3d@collabora.com>

Il 14/05/25 11:22, AngeloGioacchino Del Regno ha scritto:
> Add all of the Multimedia Data Path 3 (MDP3) related nodes
> including its Mutex instances, one for each VPPSYS block, and
> all of its DMA controllers, Film Grain (FG), HDR, Adaptive Ambient
> Light (AAL), Frame Resizer (RSZ), Tone Curve Conversion (TCC),
> Two-Dimensional Sharpness (TDSHP), and others, enabling the entire
> MDP3 macro-block.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

Rob, sorry again for missing your previous email about the warnings
generated by this commit.

I ran a dtbs_check on this and I didn't see any warning - can you please urgently
check and confirm that I didn't miss anything on this one so that I can pull it in
the MediaTek trees for a fixed up PR?

If anything else is wrong with this one, I'll have to just drop it and delay this
for the next cycle as it's really too late (my bad, though).

Many many thanks,
Angelo


> ---
>   arch/arm64/boot/dts/mediatek/mt8188.dtsi | 299 +++++++++++++++++++++++
>   1 file changed, 299 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> index 29d35ca94597..55260357ac66 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> @@ -2224,6 +2224,118 @@ vppsys0: syscon at 14000000 {
>   			#clock-cells = <1>;
>   		};
>   
> +		dma-controller at 14001000 {
> +			compatible = "mediatek,mt8188-mdp3-rdma";
> +			reg = <0 0x14001000 0 0x1000>;
> +			#dma-cells = <1>;
> +			clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
> +			mboxes = <&gce0 13 CMDQ_THR_PRIO_1>,
> +				 <&gce0 14 CMDQ_THR_PRIO_1>,
> +				 <&gce0 16 CMDQ_THR_PRIO_1>,
> +				 <&gce0 21 CMDQ_THR_PRIO_1>,
> +				 <&gce0 22 CMDQ_THR_PRIO_1>;
> +			iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
> +			mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
> +					      <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
> +			mediatek,scp = <&scp>;
> +		};
> +
> +		display at 14002000 {
> +			compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
> +			reg = <0 0x14002000 0 0x1000>;
> +			clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
> +		};
> +
> +		display at 14004000 {
> +			compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
> +			reg = <0 0x14004000 0 0x1000>;
> +			clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
> +		};
> +
> +		display at 14005000 {
> +			compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
> +			reg = <0 0x14005000 0 0x1000>;
> +			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
> +		};
> +
> +		display at 14006000 {
> +			compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
> +			reg = <0 0x14006000 0 0x1000>;
> +			clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
> +			mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
> +					      <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
> +		};
> +
> +		display at 14007000 {
> +			compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
> +			reg = <0 0x14007000 0 0x1000>;
> +			clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
> +		};
> +
> +		display at 14008000 {
> +			compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
> +			reg = <0 0x14008000 0 0x1000>;
> +			interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
> +		};
> +
> +		display at 14009000 {
> +			compatible = "mediatek,mt8188-mdp3-ovl", "mediatek,mt8195-mdp3-ovl";
> +			reg = <0 0x14009000 0 0x1000>;
> +			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
> +			iommus = <&vpp_iommu M4U_PORT_L4_MDP_OVL>;
> +		};
> +
> +		display at 1400a000 {
> +			compatible = "mediatek,mt8188-mdp3-padding", "mediatek,mt8195-mdp3-padding";
> +			reg = <0 0x1400a000 0 0x1000>;
> +			clocks = <&vppsys0 CLK_VPP0_PADDING>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
> +		};
> +
> +		display at 1400b000 {
> +			compatible = "mediatek,mt8188-mdp3-tcc", "mediatek,mt8195-mdp3-tcc";
> +			reg = <0 0x1400b000 0 0x1000>;
> +			clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
> +		};
> +
> +		display at 1400c000 {
> +			compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
> +			reg = <0 0x1400c000 0 0x1000>;
> +			#dma-cells = <1>;
> +			clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
> +			iommus = <&vpp_iommu M4U_PORT_L4_MDP_WROT>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
> +			mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
> +					      <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>;
> +		};
> +
> +		mutex at 1400f000 {
> +			compatible = "mediatek,mt8188-vpp-mutex";
> +			reg = <0 0x1400f000 0 0x1000>;
> +			interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&vppsys0 CLK_VPP0_MUTEX>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
> +		};
> +
>   		vpp_smi_common: smi at 14012000 {
>   			compatible = "mediatek,mt8188-smi-common-vpp";
>   			reg = <0 0x14012000 0 0x1000>;
> @@ -2255,6 +2367,184 @@ vpp_iommu: iommu at 14018000 {
>   			mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb7 &larb23>;
>   		};
>   
> +		dma-controller at 14f09000 {
> +			compatible = "mediatek,mt8188-mdp3-rdma";
> +			reg = <0 0x14f09000 0 0x1000>;
> +			#dma-cells = <1>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
> +			iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
> +			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
> +					      <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>;
> +		};
> +
> +		dma-controller at 14f0a000 {
> +			compatible = "mediatek,mt8188-mdp3-rdma";
> +			reg = <0 0x14f0a000 0 0x1000>;
> +			#dma-cells = <1>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
> +			iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
> +			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
> +					      <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>;
> +		};
> +
> +		display at 14f0c000 {
> +			compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
> +			reg = <0 0x14f0c000 0 0x1000>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
> +		};
> +
> +		display at 14f0d000 {
> +			compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
> +			reg = <0 0x14f0d000 0 0x1000>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
> +		};
> +
> +		display at 14f0f000 {
> +			compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
> +			reg = <0 0x14f0f000 0 0x1000>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
> +		};
> +
> +		display at 14f10000 {
> +			compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
> +			reg = <0 0x14f10000 0 0x1000>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
> +		};
> +
> +		display at 14f12000 {
> +			compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
> +			reg = <0 0x14f12000 0 0x1000>;
> +			interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
> +		};
> +
> +		display at 14f13000 {
> +			compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
> +			reg = <0 0x14f13000 0 0x1000>;
> +			interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
> +		};
> +
> +		display at 14f15000 {
> +			compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
> +			reg = <0 0x14f15000 0 0x1000>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
> +			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
> +					      <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
> +		};
> +
> +		display at 14f16000 {
> +			compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
> +			reg = <0 0x14f16000 0 0x1000>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
> +			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
> +					      <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
> +		};
> +
> +		display at 14f18000 {
> +			compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
> +			reg = <0 0x14f18000 0 0x1000>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
> +		};
> +
> +		display at 14f19000 {
> +			compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
> +			reg = <0 0x14f19000 0 0x1000>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
> +		};
> +
> +		display at 14f1a000 {
> +			compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge";
> +			reg = <0 0x14f1a000 0 0x1000>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
> +		};
> +
> +		display at 14f1b000 {
> +			compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge";
> +			reg = <0 0x14f1b000 0 0x1000>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
> +		};
> +
> +		display at 14f1d000 {
> +			compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
> +			reg = <0 0x14f1d000 0 0x1000>;
> +			interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
> +		};
> +
> +		display at 14f1e000 {
> +			compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
> +			reg = <0 0x14f1e000 0 0x1000>;
> +			interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
> +		};
> +
> +		display at 14f21000 {
> +			compatible = "mediatek,mt8188-mdp3-padding",
> +				     "mediatek,mt8195-mdp3-padding";
> +			reg = <0 0x14f21000 0 0x1000>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
> +		};
> +
> +		display at 14f22000 {
> +			compatible = "mediatek,mt8188-mdp3-padding",
> +				     "mediatek,mt8195-mdp3-padding";
> +			reg = <0 0x14f22000 0 0x1000>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
> +		};
> +
> +		display at 14f24000 {
> +			compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
> +			reg = <0 0x14f24000 0 0x1000>;
> +			#dma-cells = <1>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
> +			iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
> +			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
> +					      <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>;
> +		};
> +
> +		display at 14f25000 {
> +			compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
> +			reg = <0 0x14f25000 0 0x1000>;
> +			#dma-cells = <1>;
> +			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
> +			iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
> +			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
> +					      <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
> +		};
> +
>   		wpesys: clock-controller at 14e00000 {
>   			compatible = "mediatek,mt8188-wpesys";
>   			reg = <0 0x14e00000 0 0x1000>;
> @@ -2284,6 +2574,15 @@ vppsys1: syscon at 14f00000 {
>   			#clock-cells = <1>;
>   		};
>   
> +		mutex at 14f01000 {
> +			compatible = "mediatek,mt8188-vpp-mutex";
> +			reg = <0 0x14f01000 0 0x1000>;
> +			interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> +			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
> +		};
> +
>   		larb5: smi at 14f02000 {
>   			compatible = "mediatek,mt8188-smi-larb";
>   			reg = <0 0x14f02000 0 0x1000>;




From Paul-pl.Chen at mediatek.com  Wed May 14 03:00:44 2025
From: Paul-pl.Chen at mediatek.com (=?utf-8?B?UGF1bC1wbCBDaGVuICjpmbPmn4/pnJYp?=)
Date: Wed, 14 May 2025 10:00:44 +0000
Subject: [PATCH v2 10/15] drm/mediatek: add EXDMA support for MT8196
In-Reply-To: <9e0c4c80b5caaf168e99b8cd8ca74958eaac3aa9.camel@mediatek.com>
References: <20250321093435.94835-1-paul-pl.chen@mediatek.com>
	 <20250321093435.94835-11-paul-pl.chen@mediatek.com>
	 <9e0c4c80b5caaf168e99b8cd8ca74958eaac3aa9.camel@mediatek.com>
Message-ID: <031cbc906aa551882e61aa6f9c3e1e40ec19a37f.camel@mediatek.com>

On Mon, 2025-03-24 at 03:00 +0000, CK Hu (???) wrote:
> On Fri, 2025-03-21 at 17:33 +0800, paul-pl.chen wrote:
> > From: Nancy Lin <nancy.lin at mediatek.com>
> > 
> > EXDMA is a DMA engine for reading data from DRAM with
> > various DRAM footprints and data formats. For input
> > sources in certain color formats and color domains,
> > EXDMA also includes a color transfer function to
> > process pixels into a consistent color domain.
> > New Add: 6320385 Fix RG16 and refine RG24
> > 
> > Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
> > Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
> > ---
> > ?drivers/gpu/drm/mediatek/Makefile???????? |?? 1 +
> > ?drivers/gpu/drm/mediatek/mtk_ddp_comp.c?? |?? 1 +
> > ?drivers/gpu/drm/mediatek/mtk_ddp_comp.h?? |?? 1 +
> > ?drivers/gpu/drm/mediatek/mtk_disp_drv.h?? |?? 9 +
> > ?drivers/gpu/drm/mediatek/mtk_disp_exdma.c | 372
> > ++++++++++++++++++++++
> > ?drivers/gpu/drm/mediatek/mtk_drm_drv.c??? |?? 1 +
> > ?drivers/gpu/drm/mediatek/mtk_drm_drv.h??? |?? 1 +
> > ?7 files changed, 386 insertions(+)
> > ?create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_exdma.c
> > 
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 32a2ed6c0cfe..db92f4fb353d 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -5,6 +5,7 @@ mediatek-drm-y := mtk_crtc.o \
> > ?		? mtk_disp_aal.o \
> > ?		? mtk_disp_ccorr.o \
> > ?		? mtk_disp_color.o \
> > +		? mtk_disp_exdma.o \
> > ?		? mtk_disp_gamma.o \
> > ?		? mtk_disp_merge.o \
> > ?		? mtk_disp_ovl.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > index edc6417639e6..3e0739d8e6f1 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > @@ -445,6 +445,7 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> > ?	[MTK_DP_INTF] = "dp-intf",
> > ?	[MTK_DPI] = "dpi",
> > ?	[MTK_DSI] = "dsi",
> > +	[MTK_OVL_EXDMA] = "exdma",
> > ?};
> > ?
> > ?struct mtk_ddp_comp_match {
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > index 39720b27f4e9..86dc0ee3924c 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > @@ -43,6 +43,7 @@ enum mtk_ddp_comp_type {
> > ?	MTK_DPI,
> > ?	MTK_DP_INTF,
> > ?	MTK_DSI,
> > +	MTK_OVL_EXDMA,
> > ?	MTK_DDP_COMP_TYPE_MAX,
> > ?};
> > ?
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 04217a36939c..4e3d2510bef5 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -39,6 +39,15 @@ void mtk_color_config(struct device *dev,
> > unsigned int w,
> > ?		????? unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt);
> > ?void mtk_color_start(struct device *dev);
> > ?
> > +int mtk_disp_exdma_clk_enable(struct device *dev);
> > +void mtk_disp_exdma_clk_disable(struct device *dev);
> > +void mtk_disp_exdma_start(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_disp_exdma_stop(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_disp_exdma_layer_config(struct device *dev, struct
> > mtk_plane_state *state,
> > +				 struct cmdq_pkt *cmdq_pkt);
> > +const u32 *mtk_disp_exdma_get_formats(struct device *dev);
> > +size_t mtk_disp_exdma_get_num_formats(struct device *dev);
> > +
> > ?void mtk_dither_set_common(void __iomem *regs, struct
> > cmdq_client_reg *cmdq_reg,
> > ?			?? unsigned int bpc, unsigned int cfg,
> > ?			?? unsigned int dither_en, struct cmdq_pkt
> > *cmdq_pkt);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_exdma.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_exdma.c
> > new file mode 100644
> > index 000000000000..d4f7021f98d7
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_exdma.c
> > @@ -0,0 +1,372 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2025 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <drm/drm_blend.h>
> > +#include <drm/drm_framebuffer.h>
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_disp_drv.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_disp_ovl.h"
> > +
> > +#define DISP_REG_OVL_EXDMA_EN_CON		0xc
> > +#define OVL_EXDMA_OP_8BIT_MODE				BIT(4)
> > +#define OVL_EXDMA_HG_FOVL_EXDMA_CK_ON			BIT(8)
> > +#define OVL_EXDMA_HF_FOVL_EXDMA_CK_ON			BIT(10)
> > +#define DISP_REG_OVL_EXDMA_DATAPATH_CON		0x014
> > +#define OVL_EXDMA_DATAPATH_CON_LAYER_SMI_ID_EN		BIT(0)
> > +#define OVL_EXDMA_DATAPATH_CON_GCLAST_EN		BIT(24)
> > +#define OVL_EXDMA_DATAPATH_CON_HDR_GCLAST_EN		BIT(25)
> > +#define DISP_REG_OVL_EXDMA_EN			0x020
> > +#define OVL_EXDMA_EN					BIT(0)
> > +#define DISP_REG_OVL_EXDMA_RST			0x024
> > +#define OVL_EXDMA_RST					BIT(0)
> > +#define DISP_REG_OVL_EXDMA_ROI_SIZE		0x030
> > +#define DISP_REG_OVL_EXDMA_L0_EN		0x040
> > +#define
> > OVL_EXDMA_L0_EN					BIT(0)
> > +#define DISP_REG_OVL_EXDMA_OFFSET		0x044
> 
> DISP_REG_OVL_EXDMA_OFFSET is useless, so drop it.
> 
> 
Sorry, this is misleading naming, I will change it to 
DISP_REG_OVL_EXDMA_L0_OFFSET. It woulde use in the driver
> 
> 
> > +#define DISP_REG_OVL_EXDMA_SRC_SIZE		0x048
> > +#define DISP_REG_OVL_EXDMA_L0_CLRFMT		0x050
> > +#define OVL_EXDMA_CON_FLD_CLRFMT			GENMASK(3,
> > 0)
> > +#define OVL_EXDMA_CON_CLRFMT_MAN			BIT(4)
> > +#define OVL_EXDMA_CON_FLD_CLRFMT_NB			GENMASK(9,
> > 8)
> > +#define OVL_EXDMA_CON_CLRFMT_NB_10_BIT			BIT(8)
> > +#define
> > OVL_EXDMA_CON_BYTE_SWAP				BIT(16)
> > +#define OVL_EXDMA_CON_RGB_SWAP				BIT(17)
> > +#define DISP_REG_OVL_EXDMA_RDMA0_CTRL		0x100
> > +#define OVL_EXDMA_RDMA0_EN				BIT(0)
> > +#define DISP_REG_OVL_EXDMA_RDMA_BURST_CON1	0x1f4
> > +#define OVL_EXDMA_RDMA_BURST_CON1_BURST16_EN		BIT(28)
> > +#define OVL_EXDMA_RDMA_BURST_CON1_DDR_EN		BIT(30)
> > +#define OVL_EXDMA_RDMA_BURST_CON1_DDR_ACK_EN		BIT(31)
> > +#define DISP_REG_OVL_EXDMA_DUMMY_REG		0x200
> > +#define OVL_EXDMA_EXT_DDR_EN_OPT			BIT(2)
> > +#define OVL_EXDMA_FORCE_EXT_DDR_EN			BIT(3)
> > +#define DISP_REG_OVL_EXDMA_GDRDY_PRD		0x208
> > +#define DISP_REG_OVL_EXDMA_PITCH_MSB		0x2f0
> > +#define DISP_REG_OVL_EXDMA_PITCH		0x2f4
> > +#define
> > OVL_EXDMA_L0_SRC_PITCH				GENMASK(15, 0)
> > +#define OVL_EXDMA_L0_CONST_BLD				BIT(28)
> > +#define
> > OVL_EXDMA_L0_SRC_PITCH_MASK			GENMASK(15, 0)
> > +#define DISP_REG_OVL_EXDMA_L0_GUSER_EXT		0x2fc
> > +#define OVL_EXDMA_RDMA0_L0_VCSEL			BIT(5)
> > +#define OVL_EXDMA_RDMA0_HDR_L0_VCSEL			BIT(21)
> > +#define DISP_REG_OVL_EXDMA_CON			0x300
> > +#define
> > OVL_EXDMA_CON_FLD_INT_MTX_SEL			GENMASK(19, 16)
> > +#define OVL_EXDMA_CON_INT_MTX_BT601_TO_RGB		(6 << 16)
> > +#define OVL_EXDMA_CON_INT_MTX_BT709_TO_RGB		(7 << 16)
> > +#define OVL_EXDMA_CON_INT_MTX_EN			BIT(27)
> > +#define DISP_REG_OVL_EXDMA_ADDR			0xf40
> > +#define DISP_REG_OVL_EXDMA_MOUT			0xff0
> > +#define
> > OVL_EXDMA_MOUT_OUT_DATA				BIT(0)
> 
> OVL_EXDMA_MOUT_OUT_DATA is useless, so drop it.
It would used in the driver mtk_disp_exdma_start() 
in the next version of the patch.

> 
> > +#define OVL_EXDMA_MOUT_BGCLR_OUT			BIT(1)
> > +
> > +static const u32 formats[] = {
> > +	DRM_FORMAT_XRGB8888,
> > +	DRM_FORMAT_ARGB8888,
> > +	DRM_FORMAT_BGRX8888,
> > +	DRM_FORMAT_BGRA8888,
> > +	DRM_FORMAT_ABGR8888,
> > +	DRM_FORMAT_XBGR8888,
> > +	DRM_FORMAT_RGBX8888,
> > +	DRM_FORMAT_RGBA8888,
> > +	DRM_FORMAT_RGB888,
> > +	DRM_FORMAT_BGR888,
> > +	DRM_FORMAT_RGB565,
> > +	DRM_FORMAT_BGR565,
> 
> In this version, you add BGR565. If mt8195 also support BGR565, add
> BGR565 to mt8195_formats[] and merge these two array.
> 
Sure, I will fix it.
> 
> > +	DRM_FORMAT_UYVY,
> > +	DRM_FORMAT_YUYV,
> > +	DRM_FORMAT_XRGB2101010,
> > +	DRM_FORMAT_ARGB2101010,
> > +	DRM_FORMAT_RGBX1010102,
> > +	DRM_FORMAT_RGBA1010102,
> > +	DRM_FORMAT_XBGR2101010,
> > +	DRM_FORMAT_ABGR2101010,
> > +	DRM_FORMAT_BGRX1010102,
> > +	DRM_FORMAT_BGRA1010102,
> > +};
> > +
> > +struct mtk_disp_exdma {
> > +	void __iomem		*regs;
> > +	struct clk		*clk;
> > +	struct cmdq_client_reg	cmdq_reg;
> > +	struct device		*larb;
> > +};
> > +
> > +static unsigned int? mtk_disp_exdma_color_convert(unsigned int
> > color_encoding)
> > +{
> > +	switch (color_encoding) {
> > +	default:
> > +	case DRM_COLOR_YCBCR_BT709:
> > +		return OVL_EXDMA_CON_INT_MTX_BT709_TO_RGB;
> > +	case DRM_COLOR_YCBCR_BT601:
> > +		return OVL_EXDMA_CON_INT_MTX_BT601_TO_RGB;
> > +	}
> > +}
> > +
> > +void mtk_disp_exdma_start(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +	struct mtk_disp_exdma *priv = dev_get_drvdata(dev);
> > +	unsigned int value = 0, mask = 0;
> 
> It's not necessary to initialize these variable.
Sure, I will fix it.
> 
> > +
> > +	value = OVL_EXDMA_RDMA_BURST_CON1_BURST16_EN |
> > OVL_EXDMA_RDMA_BURST_CON1_DDR_ACK_EN;
> > +	mask = OVL_EXDMA_RDMA_BURST_CON1_BURST16_EN |
> > OVL_EXDMA_RDMA_BURST_CON1_DDR_EN |
> > +	?????? OVL_EXDMA_RDMA_BURST_CON1_DDR_ACK_EN;
> 
> It seems that you clear OVL_EXDMA_RDMA_BURST_CON1_DDR_EN. Describe
> why you clear it.

This configuration of clear OVL_EXDMA_RDMA_BURST_CON1_DDR_EN is to 
enable dynamic power switching mechanism for EXDMA, which is "SRT" mode
The SRT mode will have better power efficiency.  
> 
> > +	mtk_ddp_write_mask(cmdq_pkt, value, &priv->cmdq_reg, priv-
> > >regs,
> > +			?? DISP_REG_OVL_EXDMA_RDMA_BURST_CON1,
> > mask);
> > +	/*
> > +	 * The dummy register is used in the configuration of the
> > EXDMA engine to
> > +	 * write commands to DRAM, ensuring that data transfers
> > occur normally.
> 
> EXDMA would write data into DRAM? Describe more clear so I could
> understand this.
> 
> > +	 */
> > +	value = OVL_EXDMA_EXT_DDR_EN_OPT |
> > OVL_EXDMA_FORCE_EXT_DDR_EN;
> > +	mask = OVL_EXDMA_EXT_DDR_EN_OPT |
> > OVL_EXDMA_FORCE_EXT_DDR_EN;
> 
> mask is identical to value, so just use value.

OK I will make it clean to value.
> 
> > +	mtk_ddp_write_mask(cmdq_pkt, value, &priv->cmdq_reg, priv-
> > >regs,
> > +			?? DISP_REG_OVL_EXDMA_DUMMY_REG, mask);
> > +
> > +	value = OVL_EXDMA_DATAPATH_CON_LAYER_SMI_ID_EN |
> > +		OVL_EXDMA_DATAPATH_CON_HDR_GCLAST_EN |
> > +		OVL_EXDMA_DATAPATH_CON_GCLAST_EN;
> > +	mask = OVL_EXDMA_DATAPATH_CON_LAYER_SMI_ID_EN |
> > +	?????? OVL_EXDMA_DATAPATH_CON_HDR_GCLAST_EN |
> > +	?????? OVL_EXDMA_DATAPATH_CON_GCLAST_EN;
> > +	mtk_ddp_write_mask(cmdq_pkt, value, &priv->cmdq_reg, priv-
> > >regs,
> > +			?? DISP_REG_OVL_EXDMA_DATAPATH_CON, mask);
> > +
> > +	mtk_ddp_write_mask(cmdq_pkt, OVL_EXDMA_MOUT_BGCLR_OUT,
> > &priv->cmdq_reg,
> > +			?? priv->regs, DISP_REG_OVL_EXDMA_MOUT,
> > +			?? OVL_EXDMA_MOUT_BGCLR_OUT |
> > OVL_EXDMA_MOUT_OUT_DATA);
> > +
> > +	mtk_ddp_write(cmdq_pkt, ~0, &priv->cmdq_reg, priv->regs,
> > DISP_REG_OVL_EXDMA_GDRDY_PRD);
> > +
> > +	mtk_ddp_write_mask(cmdq_pkt, OVL_EXDMA_RDMA0_EN, &priv-
> > >cmdq_reg, priv->regs,
> > +			?? DISP_REG_OVL_EXDMA_RDMA0_CTRL,
> > OVL_EXDMA_RDMA0_EN);
> 
> EXDMA has layer config function, and RDMA would enable/disable by
> layer, so move OVL_EXDMA_RDMA0_EN config to layer config function.
> 
> > +	mtk_ddp_write_mask(cmdq_pkt, OVL_EXDMA_L0_EN, &priv-
> > >cmdq_reg, priv->regs,
> > +			?? DISP_REG_OVL_EXDMA_L0_EN,
> > OVL_EXDMA_L0_EN);
> 
> EXDMA has layer config function, and L0 would enable/disable by
> layer, so move OVL_EXDMA_L0_EN config to layer config function.

OK I will fix move the config to the layer configuation function.
> 
> > +
> > +	mtk_ddp_write_mask(cmdq_pkt, OVL_EXDMA_EN, &priv-
> > >cmdq_reg, priv->regs,
> > +			?? DISP_REG_OVL_EXDMA_EN, OVL_EXDMA_EN);
> > +}
> > +
> > +void mtk_disp_exdma_stop(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +	struct mtk_disp_exdma *priv = dev_get_drvdata(dev);
> > +
> > +	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv-
> > >regs,
> > +			?? DISP_REG_OVL_EXDMA_EN, OVL_EXDMA_EN);
> > +	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv-
> > >regs,
> > +			?? DISP_REG_OVL_EXDMA_RDMA0_CTRL,
> > OVL_EXDMA_RDMA0_EN);
> > +	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv-
> > >regs,
> > +			?? DISP_REG_OVL_EXDMA_DATAPATH_CON,
> > OVL_EXDMA_DATAPATH_CON_LAYER_SMI_ID_EN);
> > +	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv-
> > >regs,
> > +			?? DISP_REG_OVL_EXDMA_L0_EN,
> > OVL_EXDMA_L0_EN);
> > +	mtk_ddp_write_mask(cmdq_pkt, OVL_EXDMA_RST, &priv-
> > >cmdq_reg, priv->regs,
> > +			?? DISP_REG_OVL_EXDMA_RST, OVL_EXDMA_RST);
> > +	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv-
> > >regs,
> > +			?? DISP_REG_OVL_EXDMA_RST, OVL_EXDMA_RST);
> > +}
> > +
> > +void mtk_disp_exdma_layer_config(struct device *dev, struct
> > mtk_plane_state *state,
> > +				 struct cmdq_pkt *cmdq_pkt)
> > +{
> > +	struct mtk_disp_exdma *priv = dev_get_drvdata(dev);
> > +	struct mtk_plane_pending_state *pending = &state->pending;
> > +	const struct drm_format_info *fmt_info =
> > drm_format_info(pending->format);
> > +	unsigned int align_width = 0;
> > +	bool csc_enable = (fmt_info) ? fmt_info->is_yuv : false;
> > +	unsigned int blend_mode = mtk_ovl_get_blend_mode(state,
> > +							
> > BIT(DRM_MODE_BLEND_PREMULTI) |
> > +							
> > BIT(DRM_MODE_BLEND_COVERAGE) |
> > +							
> > BIT(DRM_MODE_BLEND_PIXEL_NONE));
> > +	unsigned int val = 0;
> 
> It's not necessary to initialize val.
> 
OK I will fix it.
> > +	unsigned int clrfmt_mask = OVL_EXDMA_CON_RGB_SWAP |
> > +				?? OVL_EXDMA_CON_BYTE_SWAP |
> > +				?? OVL_EXDMA_CON_CLRFMT_MAN |
> > +				?? OVL_EXDMA_CON_FLD_CLRFMT |
> > +				?? OVL_EXDMA_CON_FLD_CLRFMT_NB;
> > +
> > +	if (!pending->enable) {
> > +		mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
> > priv->regs,
> > +				?? DISP_REG_OVL_EXDMA_RDMA0_CTRL,
> > OVL_EXDMA_RDMA0_EN);
> > +		mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
> > priv->regs,
> > +				?? DISP_REG_OVL_EXDMA_L0_EN,
> > OVL_EXDMA_L0_EN);
> > +		return;
> > +	}
> > +
> > +	/* OVLSYS is in 1T2P domain, width needs to be 2 pixels
> > align */
> > +	align_width = ALIGN_DOWN(pending->width, 2);
> 
> If width is 101, change width to 100 would get correct display
> output?
> 
yes, and i will remove this ALIGN_DOWN. 
> > +
> > +	mtk_ddp_write(cmdq_pkt, pending->height << 16 |
> > align_width, &priv->cmdq_reg,
> > +		????? priv->regs, DISP_REG_OVL_EXDMA_ROI_SIZE);
> > +
> > +	mtk_ddp_write(cmdq_pkt, pending->height << 16 |
> > align_width, &priv->cmdq_reg,
> > +		????? priv->regs, DISP_REG_OVL_EXDMA_SRC_SIZE);
> > +	mtk_ddp_write(cmdq_pkt, pending->height << 16 |
> > align_width, &priv->cmdq_reg,
> > +		????? priv->regs, DISP_REG_OVL_EXDMA_SRC_SIZE);
> 
> Why do you duplicate DISP_REG_OVL_EXDMA_SRC_SIZE register setting?

Yes this is the redundant code, I will fix it.
> 
> > +
> > +	mtk_ddp_write_mask(cmdq_pkt, pending->pitch, &priv-
> > >cmdq_reg,
> > +			?? priv->regs, DISP_REG_OVL_EXDMA_PITCH,
> > OVL_EXDMA_L0_SRC_PITCH_MASK);
> > +	mtk_ddp_write_mask(cmdq_pkt, pending->pitch >> 16, &priv-
> > >cmdq_reg, priv->regs,
> > +			?? DISP_REG_OVL_EXDMA_PITCH_MSB, 0xf);
> 
> Symbolize 0xf.

Sure, we will Symbolize the magic number.
> 
> > +
> > +	val = mtk_disp_exdma_color_convert(pending-
> > >color_encoding);
> > +	if (csc_enable)
> > +		val |= OVL_EXDMA_CON_INT_MTX_EN;
> > +	mtk_ddp_write_mask(cmdq_pkt, val, &priv->cmdq_reg, priv-
> > >regs, DISP_REG_OVL_EXDMA_CON,
> > +			?? OVL_EXDMA_CON_FLD_INT_MTX_SEL |
> > OVL_EXDMA_CON_INT_MTX_EN);
> 
> You have no way to disable csc.
> If first frame is YUV format, you enable csc.
> And second frame is RGB, you does not disable csc, so RGB would do
> csc and display incorrect result.
> 
> 
I have checked when the val is equal to zero, it will clear the bit
OVL_EXDMA_CON_INIT_MTX_EN. So we don't have to worry this problem.
> > +
> > +	val = mtk_ovl_fmt_convert(pending->format, blend_mode,
> > true, false, 0,
> > +				? OVL_EXDMA_CON_CLRFMT_MAN,
> > OVL_EXDMA_CON_BYTE_SWAP,
> > +				? OVL_EXDMA_CON_RGB_SWAP);
> > +	if (mtk_ovl_is_10bit_rgb(pending->format))
> > +		val |= OVL_EXDMA_CON_CLRFMT_NB_10_BIT;
> > +	mtk_ddp_write_mask(cmdq_pkt, val, &priv->cmdq_reg, priv-
> > >regs,
> > +			?? DISP_REG_OVL_EXDMA_L0_CLRFMT,
> > clrfmt_mask);
> > +
> > +	val = OVL_EXDMA_HG_FOVL_EXDMA_CK_ON |
> > OVL_EXDMA_HF_FOVL_EXDMA_CK_ON |
> 
> Does CK_ON mean clock on? If so, where do you turn off the clock?
> 
OK, I will add the code to turn off it.
> 
> > +		OVL_EXDMA_OP_8BIT_MODE;
> > +	mtk_ddp_write_mask(cmdq_pkt, val, &priv->cmdq_reg, priv-
> > >regs,
> > +			?? DISP_REG_OVL_EXDMA_EN_CON, val);
> > +
> > +	val = OVL_EXDMA_RDMA0_L0_VCSEL |
> > OVL_EXDMA_RDMA0_HDR_L0_VCSEL;
> > +	mtk_ddp_write_mask(cmdq_pkt, val, &priv->cmdq_reg, priv-
> > >regs,
> > +			?? DISP_REG_OVL_EXDMA_L0_GUSER_EXT, val);
> > +
> > +	val = pending->pitch;
> > +	if (mtk_ovl_is_ignore_pixel_alpha(state, blend_mode))
> > +		val |= OVL_EXDMA_L0_CONST_BLD;
> > +	mtk_ddp_write_mask(cmdq_pkt, val, &priv->cmdq_reg, priv-
> > >regs, DISP_REG_OVL_EXDMA_PITCH,
> > +			?? OVL_EXDMA_L0_CONST_BLD |
> > OVL_EXDMA_L0_SRC_PITCH);
> > +}
> > +
> > +const u32 *mtk_disp_exdma_get_formats(struct device *dev)
> > +{
> > +	return formats;
> > +}
> > +
> > +size_t mtk_disp_exdma_get_num_formats(struct device *dev)
> > +{
> > +	return ARRAY_SIZE(formats);
> > +}
> > +
> > +int mtk_disp_exdma_clk_enable(struct device *dev)
> > +{
> > +	struct mtk_disp_exdma *exdma = dev_get_drvdata(dev);
> > +
> > +	return clk_prepare_enable(exdma->clk);
> > +}
> > +
> > +void mtk_disp_exdma_clk_disable(struct device *dev)
> > +{
> > +	struct mtk_disp_exdma *exdma = dev_get_drvdata(dev);
> > +
> > +	clk_disable_unprepare(exdma->clk);
> > +}
> > +
> > +static int mtk_disp_exdma_bind(struct device *dev, struct device
> > *master,
> > +			?????? void *data)
> > +{
> > +	return 0;
> > +}
> > +
> > +static void mtk_disp_exdma_unbind(struct device *dev, struct
> > device *master,
> > +				? void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_exdma_component_ops = {
> > +	.bind	= mtk_disp_exdma_bind,
> > +	.unbind = mtk_disp_exdma_unbind,
> > +};
> > +
> > +static int mtk_disp_exdma_probe(struct platform_device *pdev)
> > +{
> > +	struct device *dev = &pdev->dev;
> > +	struct platform_device *larb_pdev = NULL;
> > +	struct device_node *larb_node = NULL;
> > +	struct resource *res;
> > +	struct mtk_disp_exdma *priv;
> > +	int ret = 0;
> > +
> > +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > +	if (!priv)
> > +		return -ENOMEM;
> > +
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	priv->regs = devm_ioremap_resource(dev, res);
> > +	if (IS_ERR(priv->regs)) {
> > +		dev_err(dev, "failed to ioremap exdma\n");
> > +		return PTR_ERR(priv->regs);
> > +	}
> > +
> > +	priv->clk = devm_clk_get(dev, NULL);
> > +	if (IS_ERR(priv->clk)) {
> > +		dev_err(dev, "failed to get exdma clk\n");
> > +		return PTR_ERR(priv->clk);
> > +	}
> > +
> > +	larb_node = of_parse_phandle(dev->of_node,
> > "mediatek,larb", 0);
> > +	if (larb_node) {
> > +		larb_pdev = of_find_device_by_node(larb_node);
> > +		if (larb_pdev)
> > +			priv->larb = &larb_pdev->dev;
> > +		of_node_put(larb_node);
> > +	}
> > +
> > +	if (!priv->larb) {
> > +		dev_dbg(dev, "not find larb dev");
> > +		return -EPROBE_DEFER;
> > +	}
> > +	device_link_add(dev, priv->larb, DL_FLAG_PM_RUNTIME |
> > DL_FLAG_STATELESS);
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > +	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> 
> You does not define cmdq client reg in binding document, so it seems
> this series depend on some cmdq series.
> Add the dependency information in cover letter.
> 
MT8196 EXDMA doesn't support GCE subsys id, so we must use this
to get the EXDMA pa info to the cmdq_reg structure.


Best, Paul

> > +	if (ret)
> > +		dev_dbg(dev, "No mediatek,gce-client-reg\n");
> > +#endif
> > +	platform_set_drvdata(pdev, priv);
> > +
> > +	pm_runtime_enable(dev);
> > +
> > +	ret = component_add(dev, &mtk_disp_exdma_component_ops);
> > +	if (ret != 0) {
> > +		pm_runtime_disable(dev);
> > +		dev_err(dev, "Failed to add component: %d\n",
> > ret);
> > +	}
> > +	return ret;
> > +}
> > +
> > +static void mtk_disp_exdma_remove(struct platform_device *pdev)
> > +{
> > +	component_del(&pdev->dev, &mtk_disp_exdma_component_ops);
> > +	pm_runtime_disable(&pdev->dev);
> > +}
> > +
> > +static const struct of_device_id mtk_disp_exdma_driver_dt_match[]
> > = {
> > +	{ .compatible = "mediatek,mt8196-exdma", },
> > +	{},
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_disp_exdma_driver_dt_match);
> > +
> > +struct platform_driver mtk_disp_exdma_driver = {
> > +	.probe = mtk_disp_exdma_probe,
> > +	.remove = mtk_disp_exdma_remove,
> > +	.driver = {
> > +		.name = "mediatek-disp-exdma",
> > +		.owner = THIS_MODULE,
> > +		.of_match_table = mtk_disp_exdma_driver_dt_match,
> > +	},
> > +};
> > +
> > +MODULE_AUTHOR("Nancy Lin <nancy.lin at mediatek.com>");
> > +MODULE_DESCRIPTION("MediaTek Exdma Driver");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 74158b9d6503..bb7306a942ff 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -1276,6 +1276,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> > ?	&mtk_disp_aal_driver,
> > ?	&mtk_disp_ccorr_driver,
> > ?	&mtk_disp_color_driver,
> > +	&mtk_disp_exdma_driver,
> > ?	&mtk_disp_gamma_driver,
> > ?	&mtk_disp_merge_driver,
> > ?	&mtk_disp_ovl_adaptor_driver,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index 675cdc90a440..898a75898775 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -72,6 +72,7 @@ struct mtk_drm_private {
> > ?extern struct platform_driver mtk_disp_aal_driver;
> > ?extern struct platform_driver mtk_disp_ccorr_driver;
> > ?extern struct platform_driver mtk_disp_color_driver;
> > +extern struct platform_driver mtk_disp_exdma_driver;
> > ?extern struct platform_driver mtk_disp_gamma_driver;
> > ?extern struct platform_driver mtk_disp_merge_driver;
> > ?extern struct platform_driver mtk_disp_ovl_adaptor_driver;
> 


From jinjian.song at fibocom.com  Wed May 14 03:47:28 2025
From: jinjian.song at fibocom.com (Jinjian Song)
Date: Wed, 14 May 2025 18:47:28 +0800
Subject: [net-next v1] net: wwan: t7xx: Parameterize data plane RX BAT and FAG count
Message-ID: <20250514104728.10869-1-jinjian.song@fibocom.com>

The DMA buffer for data plane RX is currently fixed, being parameterized
to allow configuration.

Signed-off-by: Jinjian Song <jinjian.song at fibocom.com>
---
 drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.c | 12 +++++-------
 drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h |  3 +++
 drivers/net/wwan/t7xx/t7xx_pci.c           | 10 ++++++++++
 3 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.c b/drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.c
index 6a7a26085fc7..7848e470432c 100644
--- a/drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.c
+++ b/drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.c
@@ -49,9 +49,7 @@
 #include "t7xx_netdev.h"
 #include "t7xx_pci.h"
 
-#define DPMAIF_BAT_COUNT		8192
-#define DPMAIF_FRG_COUNT		4814
-#define DPMAIF_PIT_COUNT		(DPMAIF_BAT_COUNT * 2)
+#define DPMAIF_PIT_COUNT		(dpmaif_bat_count * 2)
 
 #define DPMAIF_BAT_CNT_THRESHOLD	30
 #define DPMAIF_PIT_CNT_THRESHOLD	60
@@ -279,7 +277,7 @@ static int t7xx_frag_bat_cur_bid_check(struct dpmaif_rx_queue *rxq,
 	struct dpmaif_bat_request *bat_frag = rxq->bat_frag;
 	struct dpmaif_bat_page *bat_page;
 
-	if (cur_bid >= DPMAIF_FRG_COUNT)
+	if (cur_bid >= dpmaif_frg_count)
 		return -EINVAL;
 
 	bat_page = bat_frag->bat_skb + cur_bid;
@@ -448,7 +446,7 @@ static int t7xx_bat_cur_bid_check(struct dpmaif_rx_queue *rxq, const unsigned in
 	struct dpmaif_bat_skb *bat_skb = rxq->bat_req->bat_skb;
 
 	bat_skb += cur_bid;
-	if (cur_bid >= DPMAIF_BAT_COUNT || !bat_skb->skb)
+	if (cur_bid >= dpmaif_bat_count || !bat_skb->skb)
 		return -EINVAL;
 
 	return 0;
@@ -944,11 +942,11 @@ int t7xx_dpmaif_bat_alloc(const struct dpmaif_ctrl *dpmaif_ctrl, struct dpmaif_b
 
 	if (buf_type == BAT_TYPE_FRAG) {
 		sw_buf_size = sizeof(struct dpmaif_bat_page);
-		bat_req->bat_size_cnt = DPMAIF_FRG_COUNT;
+		bat_req->bat_size_cnt = dpmaif_frg_count;
 		bat_req->pkt_buf_sz = DPMAIF_HW_FRG_PKTBUF;
 	} else {
 		sw_buf_size = sizeof(struct dpmaif_bat_skb);
-		bat_req->bat_size_cnt = DPMAIF_BAT_COUNT;
+		bat_req->bat_size_cnt = dpmaif_bat_count;
 		bat_req->pkt_buf_sz = DPMAIF_HW_BAT_PKTBUF;
 	}
 
diff --git a/drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h b/drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h
index f4e1b69ad426..4709770fc489 100644
--- a/drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h
+++ b/drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h
@@ -22,6 +22,9 @@
 
 #include "t7xx_hif_dpmaif.h"
 
+extern uint dpmaif_bat_count;
+extern uint dpmaif_frg_count;
+
 #define NETIF_MASK		GENMASK(4, 0)
 
 #define PKT_TYPE_IP4		0
diff --git a/drivers/net/wwan/t7xx/t7xx_pci.c b/drivers/net/wwan/t7xx/t7xx_pci.c
index 8bf63f2dcbbf..021a05b49225 100644
--- a/drivers/net/wwan/t7xx/t7xx_pci.c
+++ b/drivers/net/wwan/t7xx/t7xx_pci.c
@@ -28,6 +28,7 @@
 #include <linux/jiffies.h>
 #include <linux/list.h>
 #include <linux/module.h>
+#include <linux/moduleparam.h>
 #include <linux/mutex.h>
 #include <linux/pci.h>
 #include <linux/pm.h>
@@ -54,6 +55,15 @@
 #define PM_RESOURCE_POLL_TIMEOUT_US	10000
 #define PM_RESOURCE_POLL_STEP_US	100
 
+uint dpmaif_bat_count = 8192;
+uint dpmaif_frg_count = 4814;
+
+module_param(dpmaif_bat_count, uint, 0644);
+MODULE_PARM_DESC(dpmaif_bat_count, "BAT entry count");
+
+module_param(dpmaif_frg_count, uint, 0644);
+MODULE_PARM_DESC(dpmaif_frg_count, "FRG entry count");
+
 static const char * const t7xx_mode_names[] = {
 	[T7XX_UNKNOWN] = "unknown",
 	[T7XX_READY] = "ready",
-- 
2.34.1



From krzk at kernel.org  Wed May 14 03:51:38 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Wed, 14 May 2025 12:51:38 +0200
Subject: [PATCH v3 10/10] ASoC: dt-bindings: mediatek,mt8196-nau8825: add
 mt8196-nau8825 document
In-Reply-To: <20250514081125.24475-11-darren.ye@mediatek.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
 <20250514081125.24475-11-darren.ye@mediatek.com>
Message-ID: <67a7343b-fd1e-4276-83b0-baa28d19f207@kernel.org>

On 14/05/2025 10:11, Darren.Ye wrote:


A nit, subject: drop second/last, redundant "document". The
"dt-bindings" prefix is already stating that this is a document.
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18

> +
> +properties:
> +  compatible:
> +    enum:
> +      - mediatek,mt8196-nau8825-sound
> +      - mediatek,mt8196-rt5682s-sound
> +      - mediatek,mt8196-rt5650-sound
> +
> +  audio-routing:
> +    description:
> +      Valid names could be the input or output widgets of audio components,
> +      power supplies, MicBias of codec and the software switch.

Nothing improved. I asked to drop the property. Why do you need it?
> +
> +  mediatek,platform:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: The phandle of MT8188 ASoC platform.
> +
> +  mediatek,adsp:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      The phandle of the MT8188 ADSP platform, which is the optional Audio DSP
> +      hardware that provides additional audio functionalities if present.
> +      The AFE will link to ADSP when the phandle is provided.
> +

...

> +      codec:
> +        description: Holds subnode which indicates codec dai.
> +        type: object
> +        additionalProperties: false
> +        properties:
> +          sound-dai:
> +            minItems: 1
> +            maxItems: 2
> +        required:
> +          - sound-dai
> +
> +      dai-format:
> +        description: audio format.
> +        items:
> +          enum:
> +            - i2s
> +            - right_j
> +            - left_j
> +            - dsp_a
> +            - dsp_b
> +
> +      mediatek,clk-provider:
> +        $ref: /schemas/types.yaml#/definitions/string
> +        description: Indicates dai-link clock master.
> +        items:

Drop items

> +          enum:
> +            - cpu
> +            - codec
> +
> +    additionalProperties: false
> +
> +    required:
> +      - link-name
> +
> +unevaluatedProperties: false

This goes after required: block.

> +
> +required:
> +  - compatible
> +  - mediatek,platform


Best regards,
Krzysztof


From krzk at kernel.org  Wed May 14 03:54:12 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Wed, 14 May 2025 12:54:12 +0200
Subject: [PATCH v3 08/10] ASoC: dt-bindings: mediatek,mt8196-afe: add
 audio AFE document
In-Reply-To: <20250514081125.24475-9-darren.ye@mediatek.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
 <20250514081125.24475-9-darren.ye@mediatek.com>
Message-ID: <e74d82b3-ed4a-433b-9305-a80b68130a6f@kernel.org>

On 14/05/2025 10:11, Darren.Ye wrote:
> From: Darren Ye <darren.ye at mediatek.com>
> 
> Add mt8196 audio AFE document.

A nit, subject: drop second/last, redundant "document".
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18

> 
> Signed-off-by: Darren Ye <darren.ye at mediatek.com>


...

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - mediatek,vlpcksys
> +  - power-domains
> +  - memory-region
> +  - clocks
> +  - clock-names


Keep the same order as in properties:.


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

<form letter>
This is an automated instruction, just in case, because many review tags
are being ignored. If you know the process, you can skip it (please do
not feel offended by me posting it here - no bad intentions intended).
If you do not know the process, here is a short explanation:

Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions
of patchset, under or above your Signed-off-by tag, unless patch changed
significantly (e.g. new properties added to the DT bindings). Tag is
"received", when provided in a message replied to you on the mailing
list. Tools like b4 can help here. However, there's no need to repost
patches *only* to add the tags. The upstream maintainer will do that for
tags received on the version they apply.

Full context and explanation:
https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst#L577
</form letter>


Best regards,
Krzysztof


From krzysztof.kozlowski at linaro.org  Wed May 14 03:57:03 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 14 May 2025 12:57:03 +0200
Subject: [PATCH] ASoC: dt-bindings: mediatek: Simplify mediatek,clk-provider
Message-ID: <20250514105702.28622-2-krzysztof.kozlowski@linaro.org>

"mediatek,clk-provider" property is a string, not an string array, thus
"items" is not really correct.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 .../devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml  | 7 +++----
 .../bindings/sound/mt8186-mt6366-da7219-max98357.yaml      | 7 +++----
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml
index 76d5a437dc8f..7ba2ea2dfa0b 100644
--- a/Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml
+++ b/Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml
@@ -96,10 +96,9 @@ patternProperties:
       mediatek,clk-provider:
         $ref: /schemas/types.yaml#/definitions/string
         description: Indicates dai-link clock master.
-        items:
-          enum:
-            - cpu
-            - codec
+        enum:
+          - cpu
+          - codec
 
     additionalProperties: false
 
diff --git a/Documentation/devicetree/bindings/sound/mt8186-mt6366-da7219-max98357.yaml b/Documentation/devicetree/bindings/sound/mt8186-mt6366-da7219-max98357.yaml
index cbc641ecbe94..037f21443ad1 100644
--- a/Documentation/devicetree/bindings/sound/mt8186-mt6366-da7219-max98357.yaml
+++ b/Documentation/devicetree/bindings/sound/mt8186-mt6366-da7219-max98357.yaml
@@ -124,10 +124,9 @@ patternProperties:
       mediatek,clk-provider:
         $ref: /schemas/types.yaml#/definitions/string
         description: Indicates dai-link clock master.
-        items:
-          enum:
-            - cpu
-            - codec
+        enum:
+          - cpu
+          - codec
 
     required:
       - link-name
-- 
2.45.2



From SkyLake.Huang at mediatek.com  Wed May 14 03:57:36 2025
From: SkyLake.Huang at mediatek.com (Sky Huang)
Date: Wed, 14 May 2025 18:57:36 +0800
Subject: [PATCH net-next v3 0/2] Add built-in 2.5G ethernet phy support on MT7988
Message-ID: <20250514105738.1438421-1-SkyLake.Huang@mediatek.com>

From: Sky Huang <skylake.huang at mediatek.com>

This patchset adds support for built-in 2.5Gphy on MT7988, change file
and config sequence in related Kconfig and Makefile.

---
Change in v2:
- Add missing dt-bindings and dts node.
- Remove mtk_phy_leds_state_init() temporarily. I'm going to add LED support
later.
- Remove "Firmware loading/trigger ok" log.
- Add macro define for 0x800e & 0x800f

Change in v3:
1. Remove unnecessary headers and unnecessary print log.
2. ioremap IO space (MT7988_2P5GE_PMB_FW_BASE/MTK_2P5GPHY_MCU_CSR_BASE)
directly instead of of_iomap() compatible node (mediatek,2p5gphy-fw) from dtsi
3. Call mt798x_2p5ge_phy_load_fw() from .probe instead of .config_init. This is
tested ok with openWRT-24.10 and "mediatek/mt7988/i2p5ge-phy-pmb.bin" firmware
is embedded into kernel image instead of rootfs image.
4. Use request_firmware_direct instead of request_firmware. We don't want sysfs
fallback in this driver to avoid blocking.
5. Remove mtk_i2p5ge_phy_priv sturct since it's not used anymore.
---
Sky Huang (2):
  net: phy: mediatek: Sort config and file names in Kconfig and Makefile
  net: phy: mediatek: add driver for built-in 2.5G ethernet PHY on
    MT7988

 MAINTAINERS                          |   1 +
 drivers/net/phy/mediatek/Kconfig     |  31 ++-
 drivers/net/phy/mediatek/Makefile    |   3 +-
 drivers/net/phy/mediatek/mtk-2p5ge.c | 322 +++++++++++++++++++++++++++
 4 files changed, 346 insertions(+), 11 deletions(-)
 create mode 100644 drivers/net/phy/mediatek/mtk-2p5ge.c

-- 
2.45.2



From SkyLake.Huang at mediatek.com  Wed May 14 03:57:37 2025
From: SkyLake.Huang at mediatek.com (Sky Huang)
Date: Wed, 14 May 2025 18:57:37 +0800
Subject: [PATCH net-next v3 1/2] net: phy: mediatek: Sort config and file names in Kconfig and Makefile
In-Reply-To: <20250514105738.1438421-1-SkyLake.Huang@mediatek.com>
References: <20250514105738.1438421-1-SkyLake.Huang@mediatek.com>
Message-ID: <20250514105738.1438421-2-SkyLake.Huang@mediatek.com>

From: Sky Huang <skylake.huang at mediatek.com>

Sort config and file names in Kconfig and Makefile in
drivers/net/phy/mediatek/ according to sequence in MAINTAINERS.

Signed-off-by: Sky Huang <skylake.huang at mediatek.com>
---
 drivers/net/phy/mediatek/Kconfig  | 28 ++++++++++++++--------------
 drivers/net/phy/mediatek/Makefile |  2 +-
 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/net/phy/mediatek/Kconfig b/drivers/net/phy/mediatek/Kconfig
index 4308002bb82c..3abf23e37b4b 100644
--- a/drivers/net/phy/mediatek/Kconfig
+++ b/drivers/net/phy/mediatek/Kconfig
@@ -1,18 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
-config MTK_NET_PHYLIB
-	tristate
-
-config MEDIATEK_GE_PHY
-	tristate "MediaTek Gigabit Ethernet PHYs"
-	select MTK_NET_PHYLIB
-	help
-	  Supports the MediaTek non-built-in Gigabit Ethernet PHYs.
-
-	  Non-built-in Gigabit Ethernet PHYs include mt7530/mt7531.
-	  You may find mt7530 inside mt7621. This driver shares some
-	  common operations with MediaTek SoC built-in Gigabit
-	  Ethernet PHYs.
-
 config MEDIATEK_GE_SOC_PHY
 	tristate "MediaTek SoC Ethernet PHYs"
 	depends on ARM64 || COMPILE_TEST
@@ -26,3 +12,17 @@ config MEDIATEK_GE_SOC_PHY
 	  the MT7981 and MT7988 SoCs. These PHYs need calibration data
 	  present in the SoCs efuse and will dynamically calibrate VCM
 	  (common-mode voltage) during startup.
+
+config MTK_NET_PHYLIB
+	tristate
+
+config MEDIATEK_GE_PHY
+	tristate "MediaTek Gigabit Ethernet PHYs"
+	select MTK_NET_PHYLIB
+	help
+	  Supports the MediaTek non-built-in Gigabit Ethernet PHYs.
+
+	  Non-built-in Gigabit Ethernet PHYs include mt7530/mt7531.
+	  You may find mt7530 inside mt7621. This driver shares some
+	  common operations with MediaTek SoC built-in Gigabit
+	  Ethernet PHYs.
diff --git a/drivers/net/phy/mediatek/Makefile b/drivers/net/phy/mediatek/Makefile
index 814879d0abe5..ff13205d614f 100644
--- a/drivers/net/phy/mediatek/Makefile
+++ b/drivers/net/phy/mediatek/Makefile
@@ -1,4 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)	+= mtk-ge-soc.o
 obj-$(CONFIG_MTK_NET_PHYLIB)		+= mtk-phy-lib.o
 obj-$(CONFIG_MEDIATEK_GE_PHY)		+= mtk-ge.o
-obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)	+= mtk-ge-soc.o
-- 
2.45.2



From SkyLake.Huang at mediatek.com  Wed May 14 03:57:38 2025
From: SkyLake.Huang at mediatek.com (Sky Huang)
Date: Wed, 14 May 2025 18:57:38 +0800
Subject: [PATCH net-next v3 2/2] net: phy: mediatek: add driver for built-in 2.5G ethernet PHY on MT7988
In-Reply-To: <20250514105738.1438421-1-SkyLake.Huang@mediatek.com>
References: <20250514105738.1438421-1-SkyLake.Huang@mediatek.com>
Message-ID: <20250514105738.1438421-3-SkyLake.Huang@mediatek.com>

From: Sky Huang <skylake.huang at mediatek.com>

Add support for internal 2.5Gphy on MT7988. This driver will load
necessary firmware and add appropriate time delay to make sure
that firmware works stably. The firmware loading procedure takes
about 11ms in this driver.

Signed-off-by: Sky Huang <skylake.huang at mediatek.com>
---
 MAINTAINERS                          |   1 +
 drivers/net/phy/mediatek/Kconfig     |  11 +
 drivers/net/phy/mediatek/Makefile    |   1 +
 drivers/net/phy/mediatek/mtk-2p5ge.c | 322 +++++++++++++++++++++++++++
 4 files changed, 335 insertions(+)
 create mode 100644 drivers/net/phy/mediatek/mtk-2p5ge.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 800d23264c94..5541126b4a4c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15035,6 +15035,7 @@ M:	Qingfang Deng <dqfext at gmail.com>
 M:	SkyLake Huang <SkyLake.Huang at mediatek.com>
 L:	netdev at vger.kernel.org
 S:	Maintained
+F:	drivers/net/phy/mediatek/mtk-2p5ge.c
 F:	drivers/net/phy/mediatek/mtk-ge-soc.c
 F:	drivers/net/phy/mediatek/mtk-phy-lib.c
 F:	drivers/net/phy/mediatek/mtk-ge.c
diff --git a/drivers/net/phy/mediatek/Kconfig b/drivers/net/phy/mediatek/Kconfig
index 3abf23e37b4b..e440caf3bd04 100644
--- a/drivers/net/phy/mediatek/Kconfig
+++ b/drivers/net/phy/mediatek/Kconfig
@@ -1,4 +1,15 @@
 # SPDX-License-Identifier: GPL-2.0-only
+config MEDIATEK_2P5GE_PHY
+	tristate "MediaTek 2.5Gb Ethernet PHYs"
+	depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
+	select MTK_NET_PHYLIB
+	help
+	  Supports MediaTek SoC built-in 2.5Gb Ethernet PHYs.
+
+	  This will load necessary firmware and add appropriate time delay.
+	  Accelerate this procedure through internal pbus instead of MDIO
+	  bus. Certain link-up issues will also be fixed here.
+
 config MEDIATEK_GE_SOC_PHY
 	tristate "MediaTek SoC Ethernet PHYs"
 	depends on ARM64 || COMPILE_TEST
diff --git a/drivers/net/phy/mediatek/Makefile b/drivers/net/phy/mediatek/Makefile
index ff13205d614f..f3c534889b30 100644
--- a/drivers/net/phy/mediatek/Makefile
+++ b/drivers/net/phy/mediatek/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_MEDIATEK_2P5GE_PHY)	+= mtk-2p5ge.o
 obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)	+= mtk-ge-soc.o
 obj-$(CONFIG_MTK_NET_PHYLIB)		+= mtk-phy-lib.o
 obj-$(CONFIG_MEDIATEK_GE_PHY)		+= mtk-ge.o
diff --git a/drivers/net/phy/mediatek/mtk-2p5ge.c b/drivers/net/phy/mediatek/mtk-2p5ge.c
new file mode 100644
index 000000000000..2386360dd77e
--- /dev/null
+++ b/drivers/net/phy/mediatek/mtk-2p5ge.c
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <linux/bitfield.h>
+#include <linux/firmware.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/phy.h>
+
+#include "mtk.h"
+
+#define MTK_2P5GPHY_ID_MT7988		(0x00339c11)
+
+#define MT7988_2P5GE_PMB_FW		"mediatek/mt7988/i2p5ge-phy-pmb.bin"
+#define MT7988_2P5GE_PMB_FW_SIZE	(0x20000)
+#define MT7988_2P5GE_PMB_FW_BASE	(0x0f100000)
+#define MT7988_2P5GE_PMB_FW_LEN		(0x20000)
+#define MTK_2P5GPHY_MCU_CSR_BASE	(0x0f0f0000)
+#define MTK_2P5GPHY_MCU_CSR_LEN		(0x20)
+#define MD32_EN_CFG			(0x18)
+#define   MD32_EN			BIT(0)
+
+#define BASE100T_STATUS_EXTEND		(0x10)
+#define BASE1000T_STATUS_EXTEND		(0x11)
+#define EXTEND_CTRL_AND_STATUS		(0x16)
+
+#define PHY_AUX_CTRL_STATUS		(0x1d)
+#define   PHY_AUX_DPX_MASK		GENMASK(5, 5)
+#define   PHY_AUX_SPEED_MASK		GENMASK(4, 2)
+
+/* Registers on MDIO_MMD_VEND1 */
+#define MTK_PHY_LPI_PCS_DSP_CTRL		(0x121)
+#define   MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK	GENMASK(12, 8)
+
+#define MTK_PHY_HOST_CMD1		0x800e
+#define MTK_PHY_HOST_CMD2		0x800f
+/* Registers on Token Ring debug nodes */
+/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
+#define AUTO_NP_10XEN				BIT(6)
+
+enum {
+	PHY_AUX_SPD_10 = 0,
+	PHY_AUX_SPD_100,
+	PHY_AUX_SPD_1000,
+	PHY_AUX_SPD_2500,
+};
+
+static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev)
+{
+	void __iomem *mcu_csr_base, *pmb_addr;
+	struct device *dev = &phydev->mdio.dev;
+	const struct firmware *fw;
+	int ret, i;
+	u32 reg;
+
+	pmb_addr = ioremap(MT7988_2P5GE_PMB_FW_BASE, MT7988_2P5GE_PMB_FW_LEN);
+	if (!pmb_addr)
+		return -ENOMEM;
+	mcu_csr_base = ioremap(MTK_2P5GPHY_MCU_CSR_BASE,
+			       MTK_2P5GPHY_MCU_CSR_LEN);
+	if (!mcu_csr_base) {
+		ret = -ENOMEM;
+		goto free_pmb;
+	}
+
+	ret = request_firmware_direct(&fw, MT7988_2P5GE_PMB_FW, dev);
+	if (ret) {
+		dev_err(dev, "failed to load firmware: %s, ret: %d\n",
+			MT7988_2P5GE_PMB_FW, ret);
+		goto free;
+	}
+
+	if (fw->size != MT7988_2P5GE_PMB_FW_SIZE) {
+		dev_err(dev, "Firmware size 0x%zx != 0x%x\n",
+			fw->size, MT7988_2P5GE_PMB_FW_SIZE);
+		ret = -EINVAL;
+		goto release_fw;
+	}
+
+	reg = readw(mcu_csr_base + MD32_EN_CFG);
+	if (reg & MD32_EN) {
+		phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
+		usleep_range(10000, 11000);
+	}
+	phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
+
+	/* Write magic number to safely stall MCU */
+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD1, 0x1100);
+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD2, 0x00df);
+
+	for (i = 0; i < MT7988_2P5GE_PMB_FW_SIZE - 1; i += 4)
+		writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
+
+	writew(reg & ~MD32_EN, mcu_csr_base + MD32_EN_CFG);
+	writew(reg | MD32_EN, mcu_csr_base + MD32_EN_CFG);
+	phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
+	/* We need a delay here to stabilize initialization of MCU */
+	usleep_range(7000, 8000);
+
+	dev_info(dev, "Firmware date code: %x/%x/%x, version: %x.%x\n",
+		 be16_to_cpu(*((__be16 *)(fw->data +
+					  MT7988_2P5GE_PMB_FW_SIZE - 8))),
+		 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 6),
+		 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 5),
+		 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 2),
+		 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 1));
+
+release_fw:
+	release_firmware(fw);
+free:
+	iounmap(mcu_csr_base);
+free_pmb:
+	iounmap(pmb_addr);
+
+	return ret;
+}
+
+static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
+{
+	struct pinctrl *pinctrl;
+
+	/* Check if PHY interface type is compatible */
+	if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL)
+		return -ENODEV;
+
+	/* Setup LED */
+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
+			 MTK_PHY_LED_ON_POLARITY | MTK_PHY_LED_ON_LINK10 |
+			 MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK1000 |
+			 MTK_PHY_LED_ON_LINK2500);
+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
+			 MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX);
+
+	/* Switch pinctrl after setting polarity to avoid bogus blinking */
+	pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
+	if (IS_ERR(pinctrl))
+		dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
+
+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL,
+		       MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0);
+
+	/* Enable 16-bit next page exchange bit if 1000-BT isn't advertising */
+	mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, AUTO_NP_10XEN,
+		      FIELD_PREP(AUTO_NP_10XEN, 0x1));
+
+	/* Enable HW auto downshift */
+	phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
+			 MTK_PHY_AUX_CTRL_AND_STATUS,
+			 0, MTK_PHY_ENABLE_DOWNSHIFT);
+
+	return 0;
+}
+
+static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
+{
+	bool changed = false;
+	u32 adv;
+	int ret;
+
+	ret = genphy_c45_an_config_aneg(phydev);
+	if (ret < 0)
+		return ret;
+	if (ret > 0)
+		changed = true;
+
+	/* Clause 45 doesn't define 1000BaseT support. Use Clause 22 instead in
+	 * our design.
+	 */
+	adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
+	ret = phy_modify_changed(phydev, MII_CTRL1000, ADVERTISE_1000FULL, adv);
+	if (ret < 0)
+		return ret;
+	if (ret > 0)
+		changed = true;
+
+	return __genphy_config_aneg(phydev, changed);
+}
+
+static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
+{
+	int ret;
+
+	ret = genphy_c45_pma_read_abilities(phydev);
+	if (ret)
+		return ret;
+
+	/* This phy can't handle collision, and neither can (XFI)MAC it's
+	 * connected to. Although it can do HDX handshake, it doesn't support
+	 * CSMA/CD that HDX requires.
+	 */
+	linkmode_clear_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
+			   phydev->supported);
+
+	return 0;
+}
+
+static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
+{
+	int ret;
+
+	/* When MDIO_STAT1_LSTATUS is raised genphy_c45_read_link(), this phy
+	 * actually hasn't finished AN. So use CL22's link update function
+	 * instead.
+	 */
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	phydev->speed = SPEED_UNKNOWN;
+	phydev->duplex = DUPLEX_UNKNOWN;
+	phydev->pause = 0;
+	phydev->asym_pause = 0;
+
+	/* We'll read link speed through vendor specific registers down below.
+	 * So remove phy_resolve_aneg_linkmode (AN on) & genphy_c45_read_pma
+	 * (AN off).
+	 */
+	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
+		ret = genphy_c45_read_lpa(phydev);
+		if (ret < 0)
+			return ret;
+
+		/* Clause 45 doesn't define 1000BaseT support. Read the link
+		 * partner's 1G advertisement via Clause 22.
+		 */
+		ret = phy_read(phydev, MII_STAT1000);
+		if (ret < 0)
+			return ret;
+		mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
+	} else if (phydev->autoneg == AUTONEG_DISABLE) {
+		linkmode_zero(phydev->lp_advertising);
+	}
+
+	if (phydev->link) {
+		ret = phy_read(phydev, PHY_AUX_CTRL_STATUS);
+		if (ret < 0)
+			return ret;
+
+		switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
+		case PHY_AUX_SPD_10:
+			phydev->speed = SPEED_10;
+			break;
+		case PHY_AUX_SPD_100:
+			phydev->speed = SPEED_100;
+			break;
+		case PHY_AUX_SPD_1000:
+			phydev->speed = SPEED_1000;
+			break;
+		case PHY_AUX_SPD_2500:
+			phydev->speed = SPEED_2500;
+			break;
+		}
+
+		phydev->duplex = DUPLEX_FULL;
+		phydev->rate_matching = RATE_MATCH_PAUSE;
+	}
+
+	return 0;
+}
+
+static int mt798x_2p5ge_phy_get_rate_matching(struct phy_device *phydev,
+					      phy_interface_t iface)
+{
+	return RATE_MATCH_PAUSE;
+}
+
+static int mt798x_2p5ge_phy_probe(struct phy_device *phydev)
+{
+	int ret;
+
+	switch (phydev->drv->phy_id) {
+	case MTK_2P5GPHY_ID_MT7988:
+		/* This built-in 2.5GbE hardware only sets MDIO_DEVS_PMAPMD.
+		 * Set the rest by this driver since PCS/AN/VEND1/VEND2 MDIO
+		 * manageable devices actually exist.
+		 */
+		phydev->c45_ids.mmds_present |= MDIO_DEVS_PCS |
+						MDIO_DEVS_AN |
+						MDIO_DEVS_VEND1 |
+						MDIO_DEVS_VEND2;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ret = mt798x_2p5ge_phy_load_fw(phydev);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static struct phy_driver mtk_2p5gephy_driver[] = {
+	{
+		PHY_ID_MATCH_MODEL(MTK_2P5GPHY_ID_MT7988),
+		.name = "MediaTek MT7988 2.5GbE PHY",
+		.probe = mt798x_2p5ge_phy_probe,
+		.config_init = mt798x_2p5ge_phy_config_init,
+		.config_aneg = mt798x_2p5ge_phy_config_aneg,
+		.get_features = mt798x_2p5ge_phy_get_features,
+		.read_status = mt798x_2p5ge_phy_read_status,
+		.get_rate_matching = mt798x_2p5ge_phy_get_rate_matching,
+		.suspend = genphy_suspend,
+		.resume = genphy_resume,
+		.read_page = mtk_phy_read_page,
+		.write_page = mtk_phy_write_page,
+	},
+};
+
+module_phy_driver(mtk_2p5gephy_driver);
+
+static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
+	{ PHY_ID_MATCH_VENDOR(0x00339c00) },
+	{ }
+};
+
+MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
+MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang at mediatek.com>");
+MODULE_LICENSE("GPL");
+
+MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
+MODULE_FIRMWARE(MT7988_2P5GE_PMB_FW);
-- 
2.45.2



From vkoul at kernel.org  Wed May 14 04:37:09 2025
From: vkoul at kernel.org (Vinod Koul)
Date: Wed, 14 May 2025 12:37:09 +0100
Subject: (subset) [PATCH v4 0/8] Add Bananapi R4 variants and add xsphy
In-Reply-To: <20250422132438.15735-1-linux@fw-web.de>
References: <20250422132438.15735-1-linux@fw-web.de>
Message-ID: <174722262951.85510.8563581978956288115.b4-ty@kernel.org>


On Tue, 22 Apr 2025 15:24:23 +0200, Frank Wunderlich wrote:
> With this series i continue the mt7988/bananapi-r4 dts upstream work
> 
> changes in v4:
> - changes based on review comments in v3 (mostly bindings)
> - changed topmisc unit address to match reg
> 
> Daniel Golle (1):
>   phy: mediatek: xsphy: support type switch by pericfg
> 
> [...]

Applied, thanks!

[3/8] dt-bindings: phy: mtk-xs-phy: Add mt7988 compatible
      commit: 117d09e2830d6ff6c1bb2dc5629f972504fde51e
[4/8] dt-bindings: phy: mtk-xs-phy: support type switch by pericfg
      commit: b484b25a486962b568ada1f55c1b96dfd96b912d
[6/8] phy: mediatek: xsphy: support type switch by pericfg
      commit: f85eb659a48cc2f0c98a122e760552b69e56c06f

Best regards,
-- 
~Vinod




From vkoul at kernel.org  Wed May 14 04:37:24 2025
From: vkoul at kernel.org (Vinod Koul)
Date: Wed, 14 May 2025 12:37:24 +0100
Subject: [PATCH 1/2] dt-bindings: phy: mediatek,dsi-phy: Add support
 for MT6893
In-Reply-To: <20250416120220.147798-1-angelogioacchino.delregno@collabora.com>
References: <20250416120220.147798-1-angelogioacchino.delregno@collabora.com>
Message-ID: <174722264485.85510.16108514718041133697.b4-ty@kernel.org>


On Wed, 16 Apr 2025 14:02:19 +0200, AngeloGioacchino Del Regno wrote:
> Add support for the MediaTek Dimensity 1200 (MT6893) SoC: the DSI
> PHY found in this chip is fully compatible with the one found in
> the MT8183 SoC.
> 
> 

Applied, thanks!

[1/2] dt-bindings: phy: mediatek,dsi-phy: Add support for MT6893
      commit: fe750a871d90e081c52ce1988e1fbc85576152a3
[2/2] dt-bindings: phy: mediatek,tphy: Add support for MT6893
      commit: 1b1e949924fb59e98d9401681b139e92e75686ac

Best regards,
-- 
~Vinod




From andrew at lunn.ch  Wed May 14 05:09:24 2025
From: andrew at lunn.ch (Andrew Lunn)
Date: Wed, 14 May 2025 14:09:24 +0200
Subject: [PATCH net-next v3 1/2] net: phy: mediatek: Sort config and file
 names in Kconfig and Makefile
In-Reply-To: <20250514105738.1438421-2-SkyLake.Huang@mediatek.com>
References: <20250514105738.1438421-1-SkyLake.Huang@mediatek.com>
 <20250514105738.1438421-2-SkyLake.Huang@mediatek.com>
Message-ID: <2147e0e3-44c0-4fd8-916d-53291dc86a6a@lunn.ch>

On Wed, May 14, 2025 at 06:57:37PM +0800, Sky Huang wrote:
> From: Sky Huang <skylake.huang at mediatek.com>
> 
> Sort config and file names in Kconfig and Makefile in
> drivers/net/phy/mediatek/ according to sequence in MAINTAINERS.

If you use "make menuconfig" you will notice PHYs are sorted by
tristate string. So having Gigabit before Soc is correct.

> --- a/drivers/net/phy/mediatek/Makefile
> +++ b/drivers/net/phy/mediatek/Makefile
> @@ -1,4 +1,4 @@
>  # SPDX-License-Identifier: GPL-2.0
> +obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)	+= mtk-ge-soc.o
>  obj-$(CONFIG_MTK_NET_PHYLIB)		+= mtk-phy-lib.o
>  obj-$(CONFIG_MEDIATEK_GE_PHY)		+= mtk-ge.o
> -obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)	+= mtk-ge-soc.o

These should be in alphabetic order based on CONFIG_. So
CONFIG_MTK_NET_PHYLIB is what should move.

    Andrew

---
pw-bot: cr


From linux at armlinux.org.uk  Wed May 14 05:13:26 2025
From: linux at armlinux.org.uk (Russell King (Oracle))
Date: Wed, 14 May 2025 13:13:26 +0100
Subject: [PATCH net-next v3 2/2] net: phy: mediatek: add driver for
 built-in 2.5G ethernet PHY on MT7988
In-Reply-To: <20250514105738.1438421-3-SkyLake.Huang@mediatek.com>
References: <20250514105738.1438421-1-SkyLake.Huang@mediatek.com>
 <20250514105738.1438421-3-SkyLake.Huang@mediatek.com>
Message-ID: <aCSI5k7uUgAlpSsy@shell.armlinux.org.uk>

Hi,

On Wed, May 14, 2025 at 06:57:38PM +0800, Sky Huang wrote:
> +#define MTK_2P5GPHY_ID_MT7988		(0x00339c11)
> +
> +#define MT7988_2P5GE_PMB_FW		"mediatek/mt7988/i2p5ge-phy-pmb.bin"
> +#define MT7988_2P5GE_PMB_FW_SIZE	(0x20000)
> +#define MT7988_2P5GE_PMB_FW_BASE	(0x0f100000)
> +#define MT7988_2P5GE_PMB_FW_LEN		(0x20000)
> +#define MTK_2P5GPHY_MCU_CSR_BASE	(0x0f0f0000)
> +#define MTK_2P5GPHY_MCU_CSR_LEN		(0x20)
> +#define MD32_EN_CFG			(0x18)

These parens are all unnecessary, as are ones below around a simple
number.

> +#define   MD32_EN			BIT(0)
> +
> +#define BASE100T_STATUS_EXTEND		(0x10)
> +#define BASE1000T_STATUS_EXTEND		(0x11)
> +#define EXTEND_CTRL_AND_STATUS		(0x16)
> +
> +#define PHY_AUX_CTRL_STATUS		(0x1d)
> +#define   PHY_AUX_DPX_MASK		GENMASK(5, 5)
> +#define   PHY_AUX_SPEED_MASK		GENMASK(4, 2)
> +
> +/* Registers on MDIO_MMD_VEND1 */
> +#define MTK_PHY_LPI_PCS_DSP_CTRL		(0x121)

...

> +static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev)
> +{
> +	void __iomem *mcu_csr_base, *pmb_addr;
> +	struct device *dev = &phydev->mdio.dev;

This will attract a comment about reverse christmas tree.

> +	const struct firmware *fw;
> +	int ret, i;
> +	u32 reg;

...

> +static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
> +{
> +	struct pinctrl *pinctrl;
> +
> +	/* Check if PHY interface type is compatible */
> +	if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL)
> +		return -ENODEV;
> +
> +	/* Setup LED */
> +	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
> +			 MTK_PHY_LED_ON_POLARITY | MTK_PHY_LED_ON_LINK10 |
> +			 MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK1000 |
> +			 MTK_PHY_LED_ON_LINK2500);
> +	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
> +			 MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX);
> +
> +	/* Switch pinctrl after setting polarity to avoid bogus blinking */
> +	pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
> +	if (IS_ERR(pinctrl))
> +		dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");

No, don't do this. config_init() can be called multiple times during
the lifetime of the driver bound to the device, and each time it is,
a new managed-dev structure will be allocated to release this action
each time, thus consuming more and more memory, or possibly failing
after the first depending on the pinctrl_get_select() behaviour.
Please find a different way.

...

> +static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
> +{
> +	bool changed = false;
> +	u32 adv;
> +	int ret;
> +
> +	ret = genphy_c45_an_config_aneg(phydev);
> +	if (ret < 0)
> +		return ret;
> +	if (ret > 0)
> +		changed = true;
> +
> +	/* Clause 45 doesn't define 1000BaseT support. Use Clause 22 instead in
> +	 * our design.
> +	 */
> +	adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
> +	ret = phy_modify_changed(phydev, MII_CTRL1000, ADVERTISE_1000FULL, adv);
> +	if (ret < 0)
> +		return ret;
> +	if (ret > 0)
> +		changed = true;
> +
> +	return __genphy_config_aneg(phydev, changed);

Do you want this (which will program EEE and the 10/100 advert) or do
you want genphy_check_and_restart_aneg() here? Note that
genphy_c45_an_config_aneg() will already have programmed both the EEE
and 10/100 adverts via the C45 registers.

Thanks.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!


From nfraprado at collabora.com  Wed May 14 05:36:06 2025
From: nfraprado at collabora.com (=?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?=)
Date: Wed, 14 May 2025 08:36:06 -0400
Subject: [PATCH] regulator: dt-bindings: mt6357: Drop fixed compatible
 requirement
Message-ID: <20250514-mt6357-regulator-fixed-compatibles-removal-bindings-v1-1-2421e9cc6cc7@collabora.com>

Some of the regulators on the MT6357 PMIC currently reference the
fixed-regulator dt-binding, which enforces the presence of a
regulator-fixed compatible. However since all regulators on the MT6357
PMIC are handled by a single mt6357-regulator driver, probed through
MFD, the compatibles don't serve any purpose. In fact they cause
failures in the DT kselftest since they aren't probed by the fixed
regulator driver as would be expected. Furthermore this is the only
dt-binding in this family like this: mt6359-regulator and
mt6358-regulator don't require those compatibles.

Commit d77e89b7b03f ("arm64: dts: mediatek: mt6357: Drop regulator-fixed
compatibles") removed the compatibles from Devicetree, but missed
updating the binding, which still requires them, introducing dt-binding
errors. Remove the compatible requirement by referencing the plain
regulator dt-binding instead to fix the dt-binding errors.

Fixes: d77e89b7b03f ("arm64: dts: mediatek: mt6357: Drop regulator-fixed compatibles")
Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
---
 .../bindings/regulator/mediatek,mt6357-regulator.yaml        | 12 +-----------
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml
index 6327bb2f6ee080a178ff3e982768c5eb0595e771..698266c09e25359a516d969a0487cc94444b842d 100644
--- a/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml
@@ -33,7 +33,7 @@ patternProperties:
 
   "^ldo-v(camio18|aud28|aux18|io18|io28|rf12|rf18|cn18|cn28|fe28)$":
     type: object
-    $ref: fixed-regulator.yaml#
+    $ref: regulator.yaml#
     unevaluatedProperties: false
     description:
       Properties for single fixed LDO regulator.
@@ -112,7 +112,6 @@ examples:
           regulator-enable-ramp-delay = <220>;
         };
         mt6357_vfe28_reg: ldo-vfe28 {
-          compatible = "regulator-fixed";
           regulator-name = "vfe28";
           regulator-min-microvolt = <2800000>;
           regulator-max-microvolt = <2800000>;
@@ -125,14 +124,12 @@ examples:
           regulator-enable-ramp-delay = <110>;
         };
         mt6357_vrf18_reg: ldo-vrf18 {
-          compatible = "regulator-fixed";
           regulator-name = "vrf18";
           regulator-min-microvolt = <1800000>;
           regulator-max-microvolt = <1800000>;
           regulator-enable-ramp-delay = <110>;
         };
         mt6357_vrf12_reg: ldo-vrf12 {
-          compatible = "regulator-fixed";
           regulator-name = "vrf12";
           regulator-min-microvolt = <1200000>;
           regulator-max-microvolt = <1200000>;
@@ -157,14 +154,12 @@ examples:
           regulator-enable-ramp-delay = <264>;
         };
         mt6357_vcn28_reg: ldo-vcn28 {
-          compatible = "regulator-fixed";
           regulator-name = "vcn28";
           regulator-min-microvolt = <2800000>;
           regulator-max-microvolt = <2800000>;
           regulator-enable-ramp-delay = <264>;
         };
         mt6357_vcn18_reg: ldo-vcn18 {
-          compatible = "regulator-fixed";
           regulator-name = "vcn18";
           regulator-min-microvolt = <1800000>;
           regulator-max-microvolt = <1800000>;
@@ -183,7 +178,6 @@ examples:
           regulator-enable-ramp-delay = <264>;
         };
         mt6357_vcamio_reg: ldo-vcamio18 {
-          compatible = "regulator-fixed";
           regulator-name = "vcamio";
           regulator-min-microvolt = <1800000>;
           regulator-max-microvolt = <1800000>;
@@ -212,28 +206,24 @@ examples:
           regulator-always-on;
         };
         mt6357_vaux18_reg: ldo-vaux18 {
-          compatible = "regulator-fixed";
           regulator-name = "vaux18";
           regulator-min-microvolt = <1800000>;
           regulator-max-microvolt = <1800000>;
           regulator-enable-ramp-delay = <264>;
         };
         mt6357_vaud28_reg: ldo-vaud28 {
-          compatible = "regulator-fixed";
           regulator-name = "vaud28";
           regulator-min-microvolt = <2800000>;
           regulator-max-microvolt = <2800000>;
           regulator-enable-ramp-delay = <264>;
         };
         mt6357_vio28_reg: ldo-vio28 {
-          compatible = "regulator-fixed";
           regulator-name = "vio28";
           regulator-min-microvolt = <2800000>;
           regulator-max-microvolt = <2800000>;
           regulator-enable-ramp-delay = <264>;
         };
         mt6357_vio18_reg: ldo-vio18 {
-          compatible = "regulator-fixed";
           regulator-name = "vio18";
           regulator-min-microvolt = <1800000>;
           regulator-max-microvolt = <1800000>;

---
base-commit: edef457004774e598fc4c1b7d1d4f0bcd9d0bb30
change-id: 20250513-mt6357-regulator-fixed-compatibles-removal-bindings-5e61fa4e5847

Best regards,
-- 
N?colas F. R. A. Prado <nfraprado at collabora.com>



From robh at kernel.org  Wed May 14 05:56:34 2025
From: robh at kernel.org (Rob Herring)
Date: Wed, 14 May 2025 07:56:34 -0500
Subject: [PATCH v2 3/3] arm64: dts: mediatek: mt8188: Add all Multimedia
 Data Path 3 nodes
In-Reply-To: <439db3ea-4fb7-4944-b182-222663c09b3d@collabora.com>
References: <20250514092259.47035-1-angelogioacchino.delregno@collabora.com>
 <20250514092259.47035-3-angelogioacchino.delregno@collabora.com> <439db3ea-4fb7-4944-b182-222663c09b3d@collabora.com>
Message-ID: <CAL_JsqLwXwmt5Smutvv+V-HfLzgYCqb-YRVx9ydD7rfmkiWoeA@mail.gmail.com>

On Wed, May 14, 2025 at 4:26?AM AngeloGioacchino Del Regno
<angelogioacchino.delregno at collabora.com> wrote:
>
> Il 14/05/25 11:22, AngeloGioacchino Del Regno ha scritto:
> > Add all of the Multimedia Data Path 3 (MDP3) related nodes
> > including its Mutex instances, one for each VPPSYS block, and
> > all of its DMA controllers, Film Grain (FG), HDR, Adaptive Ambient
> > Light (AAL), Frame Resizer (RSZ), Tone Curve Conversion (TCC),
> > Two-Dimensional Sharpness (TDSHP), and others, enabling the entire
> > MDP3 macro-block.
> >
> > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

Acked-by: Rob Herring (Arm) <robh at kernel.org>

> Rob, sorry again for missing your previous email about the warnings
> generated by this commit.
>
> I ran a dtbs_check on this and I didn't see any warning - can you please urgently
> check and confirm that I didn't miss anything on this one so that I can pull it in
> the MediaTek trees for a fixed up PR?
>
> If anything else is wrong with this one, I'll have to just drop it and delay this
> for the next cycle as it's really too late (my bad, though).

Thanks for fixing. FYI, Linus' and next trees are tested daily here:

https://gitlab.com/robherring/linux-dt/-/jobs

platform-warnings.log has the top warnings and undocumented
compatibles by platform family.

Rob


From angelogioacchino.delregno at collabora.com  Wed May 14 06:02:38 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 14 May 2025 15:02:38 +0200
Subject: [PATCH v2 3/3] arm64: dts: mediatek: mt8188: Add all Multimedia
 Data Path 3 nodes
In-Reply-To: <CAL_JsqLwXwmt5Smutvv+V-HfLzgYCqb-YRVx9ydD7rfmkiWoeA@mail.gmail.com>
References: <20250514092259.47035-1-angelogioacchino.delregno@collabora.com>
 <20250514092259.47035-3-angelogioacchino.delregno@collabora.com>
 <439db3ea-4fb7-4944-b182-222663c09b3d@collabora.com>
 <CAL_JsqLwXwmt5Smutvv+V-HfLzgYCqb-YRVx9ydD7rfmkiWoeA@mail.gmail.com>
Message-ID: <0d530e65-1c22-4538-9234-802541e5326a@collabora.com>

Il 14/05/25 14:56, Rob Herring ha scritto:
> On Wed, May 14, 2025 at 4:26?AM AngeloGioacchino Del Regno
> <angelogioacchino.delregno at collabora.com> wrote:
>>
>> Il 14/05/25 11:22, AngeloGioacchino Del Regno ha scritto:
>>> Add all of the Multimedia Data Path 3 (MDP3) related nodes
>>> including its Mutex instances, one for each VPPSYS block, and
>>> all of its DMA controllers, Film Grain (FG), HDR, Adaptive Ambient
>>> Light (AAL), Frame Resizer (RSZ), Tone Curve Conversion (TCC),
>>> Two-Dimensional Sharpness (TDSHP), and others, enabling the entire
>>> MDP3 macro-block.
>>>
>>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> 
> Acked-by: Rob Herring (Arm) <robh at kernel.org>
> 
>> Rob, sorry again for missing your previous email about the warnings
>> generated by this commit.
>>
>> I ran a dtbs_check on this and I didn't see any warning - can you please urgently
>> check and confirm that I didn't miss anything on this one so that I can pull it in
>> the MediaTek trees for a fixed up PR?
>>
>> If anything else is wrong with this one, I'll have to just drop it and delay this
>> for the next cycle as it's really too late (my bad, though).
> 
> Thanks for fixing.

Thank you for the very fast ack, highly appreciated.

I have just learnt that Arnd accidentally pulled the branch anyway, so I will
have to resend this as a fix on top - it will be just a diff between the current
one and this commit that you acked.

I guess I can retain your ack on the diff-only commit, as the result will be
exactly the same as this v2.

> FYI, Linus' and next trees are tested daily here:
> 
> https://gitlab.com/robherring/linux-dt/-/jobs
> 
> platform-warnings.log has the top warnings and undocumented
> compatibles by platform family.
> 
That's very useful! Didn't know about it - thanks, that'll make my maintainer
life easier. Bookmarked!

Cheers,
Angelo




From ggo at tuxedocomputers.com  Wed May 14 06:15:28 2025
From: ggo at tuxedocomputers.com (ggo at tuxedocomputers.com)
Date: Wed, 14 May 2025 15:15:28 +0200
Subject: 6 Ghz frequencies always listed as disabled in newer kernels
 with Mediatek MT7921K (RZ608)
In-Reply-To: <SI2PR03MB532296077BDB2BEBE79DDB2885FC2@SI2PR03MB5322.apcprd03.prod.outlook.com>
References: <18be5ba2-6dc4-4766-9944-59cb46c8dfaf@devture.com>
 <SI2PR03MB532296077BDB2BEBE79DDB2885FC2@SI2PR03MB5322.apcprd03.prod.outlook.com>
Message-ID: <8db21316-9db2-4ef8-95ca-bec9b6623211@tuxedocomputers.com>

Hi Yen,

Friendly reminder of this topic.

We have the same problem with RZ608 and RZ616: All 6GHz channels are
disabled by mt7921_regd_channel_update().

Is there anything I can do to help?

Regards,
Georg


Am 12.02.25 um 03:18 schrieb Mingyen Hsieh (???):
> Hi Slavi,
> 
> Thank you for reporting this issue.
> I will look into what went wrong.
> 
> Best Regards,
> Yen.
> 
> -----Original Message-----
> From: Slavi Pantaleev <slavi at devture.com> 
> Sent: Monday, February 10, 2025 10:56 PM
> To: Felix Fietkau <nbd at nbd.name>; Lorenzo Bianconi <lorenzo at kernel.org>; Ryder Lee <Ryder.Lee at mediatek.com>; Kalle Valo <kvalo at kernel.org>; Matthias Brugger <matthias.bgg at gmail.com>; AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>; Mingyen Hsieh (???) <Mingyen.Hsieh at mediatek.com>; Deren Wu (???) <Deren.Wu at mediatek.com>; linux-wireless at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-mediatek at lists.infradead.org
> Subject: 6 Ghz frequencies always listed as disabled in newer kernels with Mediatek MT7921K (RZ608)
> 
> 
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> Hello!
> 
> This is in regard to Bugzilla Bug 218731 - Tri-band AMD RZ608 (MediaTek
> MT7921K) has 6GHz band disabled in kernel 6.7+ despite working in <=6.6
> 
> URL: https://urldefense.com/v3/__https://bugzilla.kernel.org/show_bug.cgi?id=218731__;!!CTRNKA9wMg0ARbw!hwgyrPE5EUmlhv276MLdhh3io-OmXeYvNMVGUpAUbJ7wgc9z8WI4fZoD0Ze1WlIlqf_1qrieE1unap_P8_E$
> 
> I'm in Bulgaria and `iw reg get` reports this:
> 
> ```
> global
> country BG: DFS-ETSI
>          (2400 - 2483 @ 40), (N/A, 20), (N/A)
>          (5150 - 5250 @ 80), (N/A, 23), (N/A), NO-OUTDOOR, AUTO-BW
>          (5250 - 5350 @ 80), (N/A, 20), (0 ms), NO-OUTDOOR, DFS, AUTO-BW
>          (5470 - 5725 @ 160), (N/A, 26), (0 ms), DFS
>          (5725 - 5875 @ 80), (N/A, 13), (N/A)
>          (5945 - 6425 @ 160), (N/A, 23), (N/A), NO-OUTDOOR
>          (57000 - 66000 @ 2160), (N/A, 40), (N/A) ```
> 
> For testing purposes, I've also tried switching to another regulatory domain (`US`, `DE`, `SE`, `NL`) via `iw reg set ..`.
> 
> Regardless of the regulatory domain, `iw list | grep -A 15 Frequencies` always reports the 6 Ghz frequencies as disabled on newer kernels.
> 
> As the original bug reporter has discovered, the regression begins to appear in kernel 6.7.0 while it isn't present in 6.6.30.
> I've done a bisection and the results are like this:
> 
> 1. [bad] mainline (954a209f431c06b62718a49b403bd4c549f0d6fb)
> 2. [good] v6.6.30
> 3. [bad] v6.7.12
> 4. [good] v6.6
> 5. [bad] edd8e84ae9514e93368f56c3715b11af52df6c3b
> 6. [bad] 89ed67ef126c4160349c1b96fdb775ea6170ac90
> 7. [good] b827ac419721a106ae2fccaa40576b0594edad92
> 8. [bad] d1a02ed66fe62aa2edd77bd54e270ebc33bd12ff
> 9. [good] 3abbd0699b678fc48e0100704338cff9180fe4bb
> 10. [good] 5a423552e0d9bb882f22cb0bf85f520ca2692706
> 11. [bad] 56a7bb12c78ffa1b02e154b1d779ed2a1555fa3c
> 12. [good] a3c2dd96487f1dd734c9443a3472c8dafa689813
> 13. [bad] 089482a06b74a40d45773b1871182e8f04be026b
> 14. [good] fce9c967820a72f600abbf061d7077861685a14d
> 15. [good] c948b5da6bbec742b433138e3e3f9537a85af2e5
> 16. [good] 9585316a2aaf773a67846bdc8bbdd4df1e9622fa
> 17. [good] 51ba0e3a15eb1643116a93674e230e11b9499592
> 18. [bad] 09382d8f8641bc12fffc41a93eb9b37be0e653c0
> 19. [good] 4fc8df50fd41c2762d893211487be0ecb24c6a05
> 
> 09382d8f8641bc12fffc41a93eb9b37be0e653c0 is reported as the first bad commit.
> 
> URL:
> https://urldefense.com/v3/__https://kernel.googlesource.com/pub/scm/linux/kernel/git/stable/linux/*/09382d8f8641bc12fffc41a93eb9b37be0e653c0__;Kw!!CTRNKA9wMg0ARbw!hwgyrPE5EUmlhv276MLdhh3io-OmXeYvNMVGUpAUbJ7wgc9z8WI4fZoD0Ze1WlIlqf_1qrieE1unR0MDLCs$
> 
> Regards
> 



From angelogioacchino.delregno at collabora.com  Wed May 14 06:42:50 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 14 May 2025 15:42:50 +0200
Subject: [PATCH] ASoC: dt-bindings: mediatek: Simplify
 mediatek,clk-provider
In-Reply-To: <20250514105702.28622-2-krzysztof.kozlowski@linaro.org>
References: <20250514105702.28622-2-krzysztof.kozlowski@linaro.org>
Message-ID: <2734351a-7214-4c60-b61f-432aace5a040@collabora.com>

Il 14/05/25 12:57, Krzysztof Kozlowski ha scritto:
> "mediatek,clk-provider" property is a string, not an string array, thus
> "items" is not really correct.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>




From angelogioacchino.delregno at collabora.com  Wed May 14 06:43:55 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 14 May 2025 15:43:55 +0200
Subject: [PATCH v2 3/3] arm64: dts: mt6359: Rename RTC node to match
 binding expectations
In-Reply-To: <20250514-mt8395-dtb-errors-v2-3-d67b9077c59a@collabora.com>
References: <20250514-mt8395-dtb-errors-v2-0-d67b9077c59a@collabora.com>
 <20250514-mt8395-dtb-errors-v2-3-d67b9077c59a@collabora.com>
Message-ID: <6fc2027b-2afc-433f-a9af-c458221c96ce@collabora.com>

Il 14/05/25 10:19, Julien Massot ha scritto:
> Rename the node 'mt6359rtc' to 'rtc', as required by the binding.
> 
> Fix the following dtb-check error:
> 
> mediatek/mt8395-radxa-nio-12l.dtb: pmic: 'mt6359rtc' do not match
> any of the regexes: 'pinctrl-[0-9]+'
> 
> Fixes: 3b7d143be4b7 ("arm64: dts: mt6359: add PMIC MT6359 related nodes")
> Signed-off-by: Julien Massot <julien.massot at collabora.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>




From angelogioacchino.delregno at collabora.com  Wed May 14 06:45:10 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 14 May 2025 15:45:10 +0200
Subject: [PATCH v2 1/3] dt-bindings: mfd: mediatek: mt6397: Add
 #sound-dai-cells property
In-Reply-To: <20250514-mt8395-dtb-errors-v2-1-d67b9077c59a@collabora.com>
References: <20250514-mt8395-dtb-errors-v2-0-d67b9077c59a@collabora.com>
 <20250514-mt8395-dtb-errors-v2-1-d67b9077c59a@collabora.com>
Message-ID: <825f9c5c-79e8-42f4-b489-854e58211fca@collabora.com>

Il 14/05/25 10:19, Julien Massot ha scritto:
> The 'mt6359.dtsi' file already uses the '#sound-dai-cells' property.
> Add the corresponding property to the binding to fix the following
> dtb-check error:
> 
> mediatek/mt8395-radxa-nio-12l.dtb: pmic: '#sound-dai-cells', 'mt6359rtc' do not match any of the regexes: 'pinctrl-[0-9]+'
> from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6397.yaml#
> 
> Fixes: 9bc8353be720 ("arm64: dts: mt6359: Add #sound-dai-cells property")
> Signed-off-by: Julien Massot <julien.massot at collabora.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>



From angelogioacchino.delregno at collabora.com  Wed May 14 06:47:17 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 14 May 2025 15:47:17 +0200
Subject: [PATCH v4] arm64: defconfig: mediatek: enable PHY drivers
In-Reply-To: <20250512131933.1247830-1-vignesh.raman@collabora.com>
References: <20250512131933.1247830-1-vignesh.raman@collabora.com>
Message-ID: <8df2c0c4-600b-4410-b578-cd77170d5e37@collabora.com>

Il 12/05/25 15:19, Vignesh Raman ha scritto:
> The mediatek display driver fails to probe on mt8173-elm-hana and
> mt8183-kukui-jacuzzi-juniper-sku16 in v6.14-rc4 due to missing PHY
> configurations.
> 
> Commit 924d66011f24 ("drm/mediatek: stop selecting foreign drivers")
> stopped selecting the MediaTek PHY drivers, requiring them to be
> explicitly enabled in defconfig.
> 
> Enable the following PHY drivers for MediaTek platforms:
> CONFIG_PHY_MTK_HDMI=m for HDMI display
> CONFIG_PHY_MTK_MIPI_DSI=m for DSI display
> CONFIG_PHY_MTK_DP=m for DP display
> 
> Fixes: 924d66011f24 ("drm/mediatek: stop selecting foreign drivers")
> Reviewed-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
> Signed-off-by: Vignesh Raman <vignesh.raman at collabora.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>




From angelogioacchino.delregno at collabora.com  Wed May 14 06:49:48 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 14 May 2025 15:49:48 +0200
Subject: [PATCH 0/3] ASoC: mediatek: mt8183-afe-pcm: Shorten source code
In-Reply-To: <20250425082551.1467042-1-wenst@chromium.org>
References: <20250425082551.1467042-1-wenst@chromium.org>
Message-ID: <86b55c96-7ec3-48ed-83b4-f434d7fcb5c2@collabora.com>

Il 25/04/25 10:25, Chen-Yu Tsai ha scritto:
> Hi folks,
> 
> This series is meant as an example on how to use macros and range cases
> to shorten the MediaTek audio frontend drivers. The drivers have large
> tables describing the registers and register fields for every supported
> audio DMA interface. (Some are actually skipped!) There's a lot of
> duplication which can be eliminated using macros. This should serve as
> a reference for the MT8196 AFE driver that I had commented on.
> 
> The three patches tackle separate tables in the driver. The remaining
> one that could be tackled is the list of DAIs; but that one has more
> differences between each entry, so I haven't done it yet.
> 
> Please take a look.
> 


Sorry for the very long wait here; the entire series is

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

Cheers,
Angelo



From daniel.lezcano at linaro.org  Wed May 14 06:51:58 2025
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 14 May 2025 15:51:58 +0200
Subject: [PATCH v5 0/7] Add EcoNet EN751221 MIPS platform support
In-Reply-To: <aCNhVw7oMRhHQNq_@alpha.franken.de>
References: <20250507134500.390547-1-cjd@cjdns.fr>
 <aCNWM5Xq7wnHVCrc@mai.linaro.org> <aCNhVw7oMRhHQNq_@alpha.franken.de>
Message-ID: <b4c704d9-c94e-4e89-b3ed-f715bef4e379@linaro.org>

On 5/13/25 17:12, Thomas Bogendoerfer wrote:
> On Tue, May 13, 2025 at 04:24:51PM +0200, Daniel Lezcano wrote:
>> On Wed, May 07, 2025 at 01:44:53PM +0000, Caleb James DeLisle wrote:
>>> EcoNet MIPS SoCs are big endian machines based on 34Kc and 1004Kc
>>> processors. They are found in xDSL and xPON modems, and contain PCM
>>> (VoIP), Ethernet, USB, GPIO, I2C, SPI (Flash), UART, and PCIe.
>>>
>>> The EcoNet MIPS SoCs are divided broadly into two families, the
>>> EN751221 family based on the 34Kc, and the EN751627 family based on
>>> the 1004Kc. Individual SoCs within a family are very similar, only
>>> with different peripherals.
>>>
>>> This patchset adds basic "boots to a console" support for the EN751221
>>> family and adds SmartFiber XP8421-B, a low cost commercially available
>>> board that is useful for testing and development.
>>>
>>> Note that Airoha (AN7523, AN7581) is similar to EcoNet in terms of
>>> peripherals, and for historical reasons Airoha chips are sometimes
>>> referred to with the EN75xx prefix. However this is a different
>>> platform because Airoha chips are ARM based.
>>>
>>> This patchset is against mips-next.
>>>
>>> v4 -> v5
>>> * 2/7 clocksource/drivers: Add EcoNet Timer HPT driver:
>>>    * Improve explanation of HPT timer in changelog
>>>    * Move pr_info to pr_debug per recommendation
>>>    * Remove pointless debug on spurious interrupt
>>>    * Small code-style change
>>
>> Shall I pick the clocksource + bindings changes through my tree ?
> 
> please do, I'll take the remaining patches.


Applied patch 1 et 2, thanks!


-- 
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog


From broonie at kernel.org  Wed May 14 07:36:09 2025
From: broonie at kernel.org (Mark Brown)
Date: Wed, 14 May 2025 16:36:09 +0200
Subject: [PATCH 0/3] ASoC: mediatek: mt8183-afe-pcm: Shorten source code
In-Reply-To: <86b55c96-7ec3-48ed-83b4-f434d7fcb5c2@collabora.com>
References: <20250425082551.1467042-1-wenst@chromium.org>
 <86b55c96-7ec3-48ed-83b4-f434d7fcb5c2@collabora.com>
Message-ID: <aCSqWbT9t1T29HT_@finisterre.sirena.org.uk>

On Wed, May 14, 2025 at 03:49:48PM +0200, AngeloGioacchino Del Regno wrote:
> Il 25/04/25 10:25, Chen-Yu Tsai ha scritto:

> > This series is meant as an example on how to use macros and range cases
> > to shorten the MediaTek audio frontend drivers. The drivers have large
> > tables describing the registers and register fields for every supported
> > audio DMA interface. (Some are actually skipped!) There's a lot of
> > duplication which can be eliminated using macros. This should serve as
> > a reference for the MT8196 AFE driver that I had commented on.

> Sorry for the very long wait here; the entire series is

> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

Unfortunately this doesn't apply against current code (I guess due to
development in the intervening time), could you please check and resend?
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From vkoul at kernel.org  Wed May 14 08:02:38 2025
From: vkoul at kernel.org (Vinod Koul)
Date: Wed, 14 May 2025 16:02:38 +0100
Subject: [PATCH v2] dmaengine: mediatek: Fix a possible deadlock error
 in mtk_cqdma_tx_status()
In-Reply-To: <20250508073634.3719-1-chenqiuji666@gmail.com>
References: <20250508073634.3719-1-chenqiuji666@gmail.com>
Message-ID: <174723495814.115648.10076437402947235700.b4-ty@kernel.org>


On Thu, 08 May 2025 15:36:33 +0800, Qiu-ji Chen wrote:
> Fix a potential deadlock bug. Observe that in the mtk-cqdma.c
> file, functions like mtk_cqdma_issue_pending() and
> mtk_cqdma_free_active_desc() properly acquire the pc lock before the vc
> lock when handling pc and vc fields. However, mtk_cqdma_tx_status()
> violates this order by first acquiring the vc lock before invoking
> mtk_cqdma_find_active_desc(), which subsequently takes the pc lock. This
> reversed locking sequence (vc ? pc) contradicts the established
> pc ? vc order and creates deadlock risks.
> 
> [...]

Applied, thanks!

[1/1] dmaengine: mediatek: Fix a possible deadlock error in mtk_cqdma_tx_status()
      commit: 157ae5ffd76a2857ccb4b7ce40bc5a344ca00395

Best regards,
-- 
~Vinod




From conor at kernel.org  Wed May 14 08:14:27 2025
From: conor at kernel.org (Conor Dooley)
Date: Wed, 14 May 2025 16:14:27 +0100
Subject: [PATCH] regulator: dt-bindings: mt6357: Drop fixed compatible
 requirement
In-Reply-To: <20250514-mt6357-regulator-fixed-compatibles-removal-bindings-v1-1-2421e9cc6cc7@collabora.com>
References: <20250514-mt6357-regulator-fixed-compatibles-removal-bindings-v1-1-2421e9cc6cc7@collabora.com>
Message-ID: <20250514-unifier-drone-9e50962071ff@spud>

On Wed, May 14, 2025 at 08:36:06AM -0400, N?colas F. R. A. Prado wrote:
> Some of the regulators on the MT6357 PMIC currently reference the
> fixed-regulator dt-binding, which enforces the presence of a
> regulator-fixed compatible. However since all regulators on the MT6357
> PMIC are handled by a single mt6357-regulator driver, probed through
> MFD, the compatibles don't serve any purpose. In fact they cause
> failures in the DT kselftest since they aren't probed by the fixed
> regulator driver as would be expected. Furthermore this is the only
> dt-binding in this family like this: mt6359-regulator and
> mt6358-regulator don't require those compatibles.
> 
> Commit d77e89b7b03f ("arm64: dts: mediatek: mt6357: Drop regulator-fixed
> compatibles") removed the compatibles from Devicetree, but missed
> updating the binding, which still requires them, introducing dt-binding
> errors. Remove the compatible requirement by referencing the plain
> regulator dt-binding instead to fix the dt-binding errors.
> 
> Fixes: d77e89b7b03f ("arm64: dts: mediatek: mt6357: Drop regulator-fixed compatibles")
> Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>

Acked-by: Conor Dooley <conor.dooley at microchip.com>
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From conor at kernel.org  Wed May 14 08:50:37 2025
From: conor at kernel.org (Conor Dooley)
Date: Wed, 14 May 2025 16:50:37 +0100
Subject: [PATCH] ASoC: dt-bindings: mediatek: Simplify
 mediatek,clk-provider
In-Reply-To: <20250514105702.28622-2-krzysztof.kozlowski@linaro.org>
References: <20250514105702.28622-2-krzysztof.kozlowski@linaro.org>
Message-ID: <20250514-stir-porridge-b52d88b50ae1@spud>

On Wed, May 14, 2025 at 12:57:03PM +0200, Krzysztof Kozlowski wrote:
> "mediatek,clk-provider" property is a string, not an string array, thus
> "items" is not really correct.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Acked-by: Conor Dooley <conor.dooley at microchip.com>
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From Paul-pl.Chen at mediatek.com  Wed May 14 09:18:12 2025
From: Paul-pl.Chen at mediatek.com (=?utf-8?B?UGF1bC1wbCBDaGVuICjpmbPmn4/pnJYp?=)
Date: Wed, 14 May 2025 16:18:12 +0000
Subject: [PATCH v2 13/15] drm/mediatek: add ovlsys_adaptor support for
 MT8196
In-Reply-To: <b69660b04b9569399600d4ba8a4f785f620c8aeb.camel@mediatek.com>
References: <20250321093435.94835-1-paul-pl.chen@mediatek.com>
	 <20250321093435.94835-14-paul-pl.chen@mediatek.com>
	 <b69660b04b9569399600d4ba8a4f785f620c8aeb.camel@mediatek.com>
Message-ID: <833c8f9c5efb1dcfdac9b3ddec2501ddabae845f.camel@mediatek.com>

On Fri, 2025-04-11 at 03:07 +0000, CK Hu (???) wrote:
> On Fri, 2025-03-21 at 17:33 +0800, paul-pl.chen wrote:
> > From: Nancy Lin <nancy.lin at mediatek.com>
> > 
> > Ovlsys_adaptor is an encapsulated module designed to
> > simplify the DRM control flow. This module is composed
> > of 20 EXDMAs, 20 BLENDERs, and 12 OUTPROCs.
> > Two EXDMAs merge into one layer, allowing the module
> > to support 20 layers for 3 display paths.
> > Ovlsys_adaptor driver is integrated within the
> > mtk_ddp_comp framework.
> > 
> > Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
> > Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
> > ---
> > ?drivers/gpu/drm/mediatek/Makefile???????????? |?? 1 +
> > ?drivers/gpu/drm/mediatek/mtk_ddp_comp.c?????? |? 28 +
> > ?drivers/gpu/drm/mediatek/mtk_ddp_comp.h?????? |?? 1 +
> > ?drivers/gpu/drm/mediatek/mtk_disp_drv.h?????? |? 32 +
> > ?.../drm/mediatek/mtk_disp_ovlsys_adaptor.c??? | 797
> > ++++++++++++++++++
> > ?drivers/gpu/drm/mediatek/mtk_drm_drv.c??????? |? 73 ++
> > ?drivers/gpu/drm/mediatek/mtk_drm_drv.h??????? |? 11 +-
> > ?7 files changed, 942 insertions(+), 1 deletion(-)
> > ?create mode 100644
> > drivers/gpu/drm/mediatek/mtk_disp_ovlsys_adaptor.c
> > 
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 9546bc6b7b2e..dedf50860d3f 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -9,6 +9,7 @@ mediatek-drm-y := mtk_crtc.o \
> > ?		? mtk_disp_exdma.o \
> > ?		? mtk_disp_gamma.o \
> > ?		? mtk_disp_merge.o \
> > +		? mtk_disp_ovlsys_adaptor.o \
> > ?		? mtk_disp_ovl.o \
> > ?		? mtk_disp_outproc.o \
> > ?		? mtk_disp_ovl_adaptor.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > index cc780744f060..c96e027359ac 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > @@ -368,6 +368,31 @@ static const struct mtk_ddp_comp_funcs ddp_ovl
> > = {
> > ?	.get_num_formats = mtk_ovl_get_num_formats,
> > ?};
> > ?
> > +static const struct mtk_ddp_comp_funcs ddp_ovlsys_adaptor = {
> > +	.power_on = mtk_ovlsys_adaptor_power_on,
> > +	.power_off = mtk_ovlsys_adaptor_power_off,
> > +	.clk_enable = mtk_ovlsys_adaptor_clk_enable,
> > +	.clk_disable = mtk_ovlsys_adaptor_clk_disable,
> > +	.config = mtk_ovlsys_adaptor_config,
> > +	.start = mtk_ovlsys_adaptor_start,
> > +	.stop = mtk_ovlsys_adaptor_stop,
> > +	.layer_check = mtk_ovlsys_adaptor_layer_check,
> > +	.layer_nr = mtk_ovlsys_adaptor_layer_nr,
> > +	.layer_config = mtk_ovlsys_adaptor_layer_config,
> > +	.register_vblank_cb =
> > mtk_ovlsys_adaptor_register_vblank_cb,
> > +	.unregister_vblank_cb =
> > mtk_ovlsys_adaptor_unregister_vblank_cb,
> > +	.enable_vblank = mtk_ovlsys_adaptor_enable_vblank,
> > +	.disable_vblank = mtk_ovlsys_adaptor_disable_vblank,
> > +	.dma_dev_get = mtk_ovlsys_adaptor_dma_dev_get,
> > +	.connect = mtk_ovlsys_adaptor_connect,
> > +	.disconnect = mtk_ovlsys_adaptor_disconnect,
> > +	.add = mtk_ovlsys_adaptor_add_comp,
> > +	.remove = mtk_ovlsys_adaptor_remove_comp,
> > +	.get_blend_modes = mtk_ovlsys_adaptor_get_blend_modes,
> > +	.get_formats = mtk_ovlsys_adaptor_get_formats,
> > +	.get_num_formats = mtk_ovlsys_adaptor_get_num_formats,
> > +};
> > +
> > ?static const struct mtk_ddp_comp_funcs ddp_postmask = {
> > ?	.clk_enable = mtk_ddp_clk_enable,
> > ?	.clk_disable = mtk_ddp_clk_disable,
> > @@ -437,6 +462,7 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> > ?	[MTK_DISP_OVL] = "ovl",
> > ?	[MTK_DISP_OVL_2L] = "ovl-2l",
> > ?	[MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor",
> > +	[MTK_DISP_OVLSYS_ADAPTOR] = "ovlsys_adaptor",
> > ?	[MTK_DISP_POSTMASK] = "postmask",
> > ?	[MTK_DISP_PWM] = "pwm",
> > ?	[MTK_DISP_RDMA] = "rdma",
> > @@ -469,6 +495,8 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
> > ?	[DDP_COMPONENT_DPI0]		= {
> > MTK_DPI,			0, &ddp_dpi },
> > ?	[DDP_COMPONENT_DPI1]		= {
> > MTK_DPI,			1, &ddp_dpi },
> > ?	[DDP_COMPONENT_DRM_OVL_ADAPTOR]	= {
> > MTK_DISP_OVL_ADAPTOR,	0, &ddp_ovl_adaptor },
> > +	[DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0] = {
> > MTK_DISP_OVLSYS_ADAPTOR, 0, &ddp_ovlsys_adaptor},
> > +	[DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1] = {
> > MTK_DISP_OVLSYS_ADAPTOR, 1, &ddp_ovlsys_adaptor},
> > ?	[DDP_COMPONENT_DSC0]		= {
> > MTK_DISP_DSC,		0, &ddp_dsc },
> > ?	[DDP_COMPONENT_DSC1]		= {
> > MTK_DISP_DSC,		1, &ddp_dsc },
> > ?	[DDP_COMPONENT_DSI0]		= {
> > MTK_DSI,			0, &ddp_dsi },
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > index b33d3289b8b6..ef64ce7a071f 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > @@ -33,6 +33,7 @@ enum mtk_ddp_comp_type {
> > ?	MTK_DISP_MUTEX,
> > ?	MTK_DISP_OD,
> > ?	MTK_DISP_OVL,
> > +	MTK_DISP_OVLSYS_ADAPTOR,
> > ?	MTK_DISP_OVL_2L,
> > ?	MTK_DISP_OVL_ADAPTOR,
> > ?	MTK_DISP_POSTMASK,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 3c519a662074..1ff8c4593fc1 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -174,6 +174,38 @@ size_t mtk_ovl_adaptor_get_num_formats(struct
> > device *dev);
> > ?enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct device
> > *dev,
> > ?						const struct
> > drm_display_mode *mode);
> > ?
> > +int mtk_ovlsys_adaptor_power_on(struct device *dev);
> > +void mtk_ovlsys_adaptor_power_off(struct device *dev);
> > +void mtk_ovlsys_adaptor_add_comp(struct device *dev, struct
> > mtk_mutex *mutex);
> > +void mtk_ovlsys_adaptor_remove_comp(struct device *dev, struct
> > mtk_mutex *mutex);
> > +void mtk_ovlsys_adaptor_connect(struct device *dev, struct device
> > *mmsys_dev,
> > +				unsigned int next);
> > +void mtk_ovlsys_adaptor_disconnect(struct device *dev, struct
> > device *mmsys_dev,
> > +				?? unsigned int next);
> > +int mtk_ovlsys_adaptor_clk_enable(struct device *dev);
> > +void mtk_ovlsys_adaptor_clk_disable(struct device *dev);
> > +void mtk_ovlsys_adaptor_config(struct device *dev, unsigned int w,
> > +			?????? unsigned int h, unsigned int
> > vrefresh,
> > +			?????? unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_ovlsys_adaptor_layer_config(struct device *dev, unsigned
> > int idx,
> > +				???? struct mtk_plane_state
> > *state,
> > +				???? struct cmdq_pkt *cmdq_pkt);
> > +int mtk_ovlsys_adaptor_layer_check(struct device *dev,
> > +				?? unsigned int idx,
> > +				?? struct mtk_plane_state
> > *mtk_state);
> > +void mtk_ovlsys_adaptor_register_vblank_cb(struct device *dev,
> > void (*vblank_cb)(void *),
> > +					?? void *vblank_cb_data);
> > +void mtk_ovlsys_adaptor_unregister_vblank_cb(struct device *dev);
> > +void mtk_ovlsys_adaptor_enable_vblank(struct device *dev);
> > +void mtk_ovlsys_adaptor_disable_vblank(struct device *dev);
> > +void mtk_ovlsys_adaptor_start(struct device *dev);
> > +void mtk_ovlsys_adaptor_stop(struct device *dev);
> > +unsigned int mtk_ovlsys_adaptor_layer_nr(struct device *dev);
> > +struct device *mtk_ovlsys_adaptor_dma_dev_get(struct device *dev);
> > +u32 mtk_ovlsys_adaptor_get_blend_modes(struct device *dev);
> > +const u32 *mtk_ovlsys_adaptor_get_formats(struct device *dev);
> > +size_t mtk_ovlsys_adaptor_get_num_formats(struct device *dev);
> > +
> > ?void mtk_rdma_bypass_shadow(struct device *dev);
> > ?int mtk_rdma_clk_enable(struct device *dev);
> > ?void mtk_rdma_clk_disable(struct device *dev);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovlsys_adaptor.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovlsys_adaptor.c
> > new file mode 100644
> > index 000000000000..04cb555bd77b
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovlsys_adaptor.c
> > @@ -0,0 +1,797 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2025 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <drm/drm_of.h>
> > +#include <drm/drm_print.h>
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/reset.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-mutex.h>
> > +
> > +#include "mtk_disp_blender.h"
> > +#include "mtk_disp_drv.h"
> > +#include "mtk_crtc.h"
> 
> Alphabetic order.
> 
OK, I will fix it.
> > +#include "mtk_ddp_comp.h"
> 
> Ditto.

OK, I will fix it.
> 
> > +#include "mtk_drm_drv.h"
> > +
> > +#define OVLSYS_ADAPTOR_DRIVER_DATA_MAX_SIZE 8191
> > +
> > +enum mtk_ovlsys_adaptor_comp_type {
> > +	OVLSYS_ADAPTOR_TYPE_EXDMA = 0,
> > +	OVLSYS_ADAPTOR_TYPE_BLENDER,
> > +	OVLSYS_ADAPTOR_TYPE_OUTPROC,
> > +	OVLSYS_ADAPTOR_TYPE_NUM,
> > +};
> > +
> > +enum mtk_ovlsys_adaptor_comp_id {
> > +	OVLSYS_ADAPTOR_EXDMA0,
> > +	OVLSYS_ADAPTOR_EXDMA1,
> > +	OVLSYS_ADAPTOR_EXDMA2,
> > +	OVLSYS_ADAPTOR_EXDMA3,
> > +	OVLSYS_ADAPTOR_EXDMA4,
> > +	OVLSYS_ADAPTOR_EXDMA5,
> > +	OVLSYS_ADAPTOR_EXDMA6,
> > +	OVLSYS_ADAPTOR_EXDMA7,
> > +	OVLSYS_ADAPTOR_EXDMA8,
> > +	OVLSYS_ADAPTOR_EXDMA9,
> > +	OVLSYS_ADAPTOR_EXDMA10,
> > +	OVLSYS_ADAPTOR_EXDMA11,
> > +	OVLSYS_ADAPTOR_EXDMA12,
> > +	OVLSYS_ADAPTOR_EXDMA13,
> > +	OVLSYS_ADAPTOR_EXDMA14,
> > +	OVLSYS_ADAPTOR_EXDMA15,
> > +	OVLSYS_ADAPTOR_EXDMA16,
> > +	OVLSYS_ADAPTOR_EXDMA17,
> > +	OVLSYS_ADAPTOR_EXDMA18,
> > +	OVLSYS_ADAPTOR_EXDMA19,
> > +	OVLSYS_ADAPTOR_BLENDER0,
> > +	OVLSYS_ADAPTOR_BLENDER1,
> > +	OVLSYS_ADAPTOR_BLENDER2,
> > +	OVLSYS_ADAPTOR_BLENDER3,
> > +	OVLSYS_ADAPTOR_BLENDER4,
> > +	OVLSYS_ADAPTOR_BLENDER5,
> > +	OVLSYS_ADAPTOR_BLENDER6,
> > +	OVLSYS_ADAPTOR_BLENDER7,
> > +	OVLSYS_ADAPTOR_BLENDER8,
> > +	OVLSYS_ADAPTOR_BLENDER9,
> > +	OVLSYS_ADAPTOR_BLENDER10,
> > +	OVLSYS_ADAPTOR_BLENDER11,
> > +	OVLSYS_ADAPTOR_BLENDER12,
> > +	OVLSYS_ADAPTOR_BLENDER13,
> > +	OVLSYS_ADAPTOR_BLENDER14,
> > +	OVLSYS_ADAPTOR_BLENDER15,
> > +	OVLSYS_ADAPTOR_BLENDER16,
> > +	OVLSYS_ADAPTOR_BLENDER17,
> > +	OVLSYS_ADAPTOR_BLENDER18,
> > +	OVLSYS_ADAPTOR_BLENDER19,
> > +	OVLSYS_ADAPTOR_OUTPROC0,
> > +	OVLSYS_ADAPTOR_OUTPROC1,
> > +	OVLSYS_ADAPTOR_OUTPROC2,
> > +	OVLSYS_ADAPTOR_OUTPROC3,
> > +	OVLSYS_ADAPTOR_OUTPROC4,
> > +	OVLSYS_ADAPTOR_OUTPROC5,
> > +	OVLSYS_ADAPTOR_OUTPROC6,
> > +	OVLSYS_ADAPTOR_OUTPROC7,
> > +	OVLSYS_ADAPTOR_OUTPROC8,
> > +	OVLSYS_ADAPTOR_OUTPROC9,
> > +	OVLSYS_ADAPTOR_OUTPROC10,
> > +	OVLSYS_ADAPTOR_OUTPROC11,
> > +	OVLSYS_ADAPTOR_ID_MAX
> > +};
> > +
> > +struct ovlsys_adaptor_comp_match {
> > +	enum mtk_ovlsys_adaptor_comp_type type;
> > +	int alias_id;
> > +	enum mtk_ddp_comp_id comp_id;
> > +};
> > +
> > +struct mtk_disp_ovlsys_adaptor {
> > +	struct device *ovl_adaptor_comp[OVLSYS_ADAPTOR_ID_MAX];
> > +	struct device *mmsys_dev;
> > +	const unsigned int *path;
> > +	unsigned int path_size;
> > +	unsigned int layer_nr;
> > +	bool children_bound;
> > +	unsigned int max_size;
> 
> It's not necessary to store max_size in private data.
> Drop this and use OVLSYS_ADAPTOR_DRIVER_DATA_MAX_SIZE directly.
> 
OK, I will fix it and use OVLSYS_ADAPTOR_DRIVER_DATA_MAX_SIZE 

directly to replace the max_size.
> > +};
> > +
> > +static const char * const
> > private_comp_stem[OVLSYS_ADAPTOR_TYPE_NUM] = {
> > +	[OVLSYS_ADAPTOR_TYPE_EXDMA]	= "exdma",
> > +	[OVLSYS_ADAPTOR_TYPE_BLENDER]	= "blender",
> > +	[OVLSYS_ADAPTOR_TYPE_OUTPROC]	= "outproc",
> > +};
> > +
> > +static const struct ovlsys_adaptor_comp_match
> > comp_matches[OVLSYS_ADAPTOR_ID_MAX] = {
> > +	[OVLSYS_ADAPTOR_EXDMA0]?? = { OVLSYS_ADAPTOR_TYPE_EXDMA,
> > 0, DDP_COMPONENT_ID_MAX},
> > +	[OVLSYS_ADAPTOR_EXDMA1]	? = {
> > OVLSYS_ADAPTOR_TYPE_EXDMA, 1, DDP_COMPONENT_ID_MAX},
> > +	[OVLSYS_ADAPTOR_EXDMA2]	? = {
> > OVLSYS_ADAPTOR_TYPE_EXDMA, 2, DDP_COMPONENT_OVL0_EXDMA2},
> > +	[OVLSYS_ADAPTOR_EXDMA3]	? = {
> > OVLSYS_ADAPTOR_TYPE_EXDMA, 3, DDP_COMPONENT_OVL0_EXDMA3},
> > +	[OVLSYS_ADAPTOR_EXDMA4]	? = {
> > OVLSYS_ADAPTOR_TYPE_EXDMA, 4, DDP_COMPONENT_OVL0_EXDMA4},
> > +	[OVLSYS_ADAPTOR_EXDMA5]	? = {
> > OVLSYS_ADAPTOR_TYPE_EXDMA, 5, DDP_COMPONENT_OVL0_EXDMA5},
> > +	[OVLSYS_ADAPTOR_EXDMA6]	? = {
> > OVLSYS_ADAPTOR_TYPE_EXDMA, 6, DDP_COMPONENT_OVL0_EXDMA6},
> > +	[OVLSYS_ADAPTOR_EXDMA7]	? = {
> > OVLSYS_ADAPTOR_TYPE_EXDMA, 7, DDP_COMPONENT_OVL0_EXDMA7},
> > +	[OVLSYS_ADAPTOR_EXDMA8]	? = {
> > OVLSYS_ADAPTOR_TYPE_EXDMA, 8, DDP_COMPONENT_OVL0_EXDMA8},
> > +	[OVLSYS_ADAPTOR_EXDMA9]	? = {
> > OVLSYS_ADAPTOR_TYPE_EXDMA, 9, DDP_COMPONENT_OVL0_EXDMA9},
> > +	[OVLSYS_ADAPTOR_EXDMA12]?? = { OVLSYS_ADAPTOR_TYPE_EXDMA,
> > 12, DDP_COMPONENT_OVL1_EXDMA2},
> > +	[OVLSYS_ADAPTOR_EXDMA13]?? = { OVLSYS_ADAPTOR_TYPE_EXDMA,
> > 13, DDP_COMPONENT_OVL1_EXDMA3},
> > +	[OVLSYS_ADAPTOR_EXDMA14]?? = { OVLSYS_ADAPTOR_TYPE_EXDMA,
> > 14, DDP_COMPONENT_OVL1_EXDMA4},
> > +	[OVLSYS_ADAPTOR_EXDMA15]?? = { OVLSYS_ADAPTOR_TYPE_EXDMA,
> > 15, DDP_COMPONENT_OVL1_EXDMA5},
> > +	[OVLSYS_ADAPTOR_EXDMA16]?? = { OVLSYS_ADAPTOR_TYPE_EXDMA,
> > 16, DDP_COMPONENT_OVL1_EXDMA6},
> > +	[OVLSYS_ADAPTOR_EXDMA17]?? = { OVLSYS_ADAPTOR_TYPE_EXDMA,
> > 17, DDP_COMPONENT_OVL1_EXDMA7},
> > +	[OVLSYS_ADAPTOR_EXDMA18]?? = { OVLSYS_ADAPTOR_TYPE_EXDMA,
> > 18, DDP_COMPONENT_OVL1_EXDMA8},
> > +	[OVLSYS_ADAPTOR_EXDMA19]?? = { OVLSYS_ADAPTOR_TYPE_EXDMA,
> > 19, DDP_COMPONENT_OVL1_EXDMA9},
> > +	[OVLSYS_ADAPTOR_BLENDER1] = { OVLSYS_ADAPTOR_TYPE_BLENDER,
> > 1, DDP_COMPONENT_OVL0_BLENDER1},
> > +	[OVLSYS_ADAPTOR_BLENDER2] = { OVLSYS_ADAPTOR_TYPE_BLENDER,
> > 2, DDP_COMPONENT_OVL0_BLENDER2},
> > +	[OVLSYS_ADAPTOR_BLENDER3] = { OVLSYS_ADAPTOR_TYPE_BLENDER,
> > 3, DDP_COMPONENT_OVL0_BLENDER3},
> > +	[OVLSYS_ADAPTOR_BLENDER4] = { OVLSYS_ADAPTOR_TYPE_BLENDER,
> > 4, DDP_COMPONENT_OVL0_BLENDER4},
> > +	[OVLSYS_ADAPTOR_BLENDER5] = { OVLSYS_ADAPTOR_TYPE_BLENDER,
> > 5, DDP_COMPONENT_OVL0_BLENDER5},
> > +	[OVLSYS_ADAPTOR_BLENDER6] = { OVLSYS_ADAPTOR_TYPE_BLENDER,
> > 6, DDP_COMPONENT_OVL0_BLENDER6},
> > +	[OVLSYS_ADAPTOR_BLENDER7] = { OVLSYS_ADAPTOR_TYPE_BLENDER,
> > 7, DDP_COMPONENT_OVL0_BLENDER7},
> > +	[OVLSYS_ADAPTOR_BLENDER8] = { OVLSYS_ADAPTOR_TYPE_BLENDER,
> > 8, DDP_COMPONENT_OVL0_BLENDER8},
> > +	[OVLSYS_ADAPTOR_BLENDER9] = { OVLSYS_ADAPTOR_TYPE_BLENDER,
> > 9, DDP_COMPONENT_OVL0_BLENDER9},
> > +	[OVLSYS_ADAPTOR_BLENDER11] = {
> > +		OVLSYS_ADAPTOR_TYPE_BLENDER, 11,
> > DDP_COMPONENT_OVL1_BLENDER1},
> > +	[OVLSYS_ADAPTOR_BLENDER12] = {
> > +		OVLSYS_ADAPTOR_TYPE_BLENDER, 12,
> > DDP_COMPONENT_OVL1_BLENDER2},
> > +	[OVLSYS_ADAPTOR_BLENDER13] = {
> > +		OVLSYS_ADAPTOR_TYPE_BLENDER, 13,
> > DDP_COMPONENT_OVL1_BLENDER3},
> > +	[OVLSYS_ADAPTOR_BLENDER14] = {
> > +		OVLSYS_ADAPTOR_TYPE_BLENDER, 14,
> > DDP_COMPONENT_OVL1_BLENDER4},
> > +	[OVLSYS_ADAPTOR_BLENDER15] = {
> > +		OVLSYS_ADAPTOR_TYPE_BLENDER, 15,
> > DDP_COMPONENT_OVL1_BLENDER5},
> > +	[OVLSYS_ADAPTOR_BLENDER16] = {
> > +		OVLSYS_ADAPTOR_TYPE_BLENDER, 16,
> > DDP_COMPONENT_OVL1_BLENDER6},
> > +	[OVLSYS_ADAPTOR_BLENDER17] = {
> > +		OVLSYS_ADAPTOR_TYPE_BLENDER, 17,
> > DDP_COMPONENT_OVL1_BLENDER7},
> > +	[OVLSYS_ADAPTOR_BLENDER18] = {
> > +		OVLSYS_ADAPTOR_TYPE_BLENDER, 18,
> > DDP_COMPONENT_OVL1_BLENDER8},
> > +	[OVLSYS_ADAPTOR_BLENDER19] = {
> > +		OVLSYS_ADAPTOR_TYPE_BLENDER, 19,
> > DDP_COMPONENT_OVL1_BLENDER9},
> > +	[OVLSYS_ADAPTOR_OUTPROC0] = { OVLSYS_ADAPTOR_TYPE_OUTPROC,
> > 0, DDP_COMPONENT_OVL0_OUTPROC0},
> > +	[OVLSYS_ADAPTOR_OUTPROC1] = { OVLSYS_ADAPTOR_TYPE_OUTPROC,
> > 1, DDP_COMPONENT_OVL0_OUTPROC1},
> > +	[OVLSYS_ADAPTOR_OUTPROC6] = { OVLSYS_ADAPTOR_TYPE_OUTPROC,
> > 6, DDP_COMPONENT_OVL1_OUTPROC0},
> > +};
> > +
> > +static const unsigned int mt8196_mtk_ovl_main[] = {
> > +	OVLSYS_ADAPTOR_EXDMA2,
> > +	OVLSYS_ADAPTOR_BLENDER1,
> > +	OVLSYS_ADAPTOR_EXDMA3,
> > +	OVLSYS_ADAPTOR_BLENDER2,
> > +	OVLSYS_ADAPTOR_EXDMA4,
> > +	OVLSYS_ADAPTOR_BLENDER3,
> > +	OVLSYS_ADAPTOR_EXDMA5,
> > +	OVLSYS_ADAPTOR_BLENDER4,
> > +	OVLSYS_ADAPTOR_OUTPROC0,
> > +};
> > +
> > +static const unsigned int mt8196_mtk_ovl_ext[] = {
> > +	OVLSYS_ADAPTOR_EXDMA6,
> > +	OVLSYS_ADAPTOR_BLENDER5,
> > +	OVLSYS_ADAPTOR_EXDMA7,
> > +	OVLSYS_ADAPTOR_BLENDER6,
> > +	OVLSYS_ADAPTOR_EXDMA8,
> > +	OVLSYS_ADAPTOR_BLENDER7,
> > +	OVLSYS_ADAPTOR_EXDMA9,
> > +	OVLSYS_ADAPTOR_BLENDER8,
> > +	OVLSYS_ADAPTOR_OUTPROC1,
> > +};
> > +
> > +static const unsigned int mt8196_mtk_ovl_third[] = {
> > +	OVLSYS_ADAPTOR_EXDMA12,
> > +	OVLSYS_ADAPTOR_BLENDER11,
> > +	OVLSYS_ADAPTOR_EXDMA13,
> > +	OVLSYS_ADAPTOR_BLENDER12,
> > +	OVLSYS_ADAPTOR_EXDMA14,
> > +	OVLSYS_ADAPTOR_BLENDER13,
> > +	OVLSYS_ADAPTOR_EXDMA15,
> > +	OVLSYS_ADAPTOR_BLENDER14,
> > +	OVLSYS_ADAPTOR_OUTPROC6,
> > +};
> > +
> > +static enum mtk_ovlsys_adaptor_comp_type get_type(enum
> > mtk_ovlsys_adaptor_comp_id id)
> > +{
> > +	return comp_matches[id].type;
> > +}
> > +
> > +static enum mtk_ddp_comp_id get_ddp_comp_id(enum
> > mtk_ovlsys_adaptor_comp_id id)
> > +{
> > +	return comp_matches[id].comp_id;
> > +}
> > +
> > +static struct device *get_comp_by_type_idx(struct device *dev,
> > +					?? enum
> > mtk_ovlsys_adaptor_comp_type type,
> > +					?? unsigned int idx)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	int i;
> > +	int count = 0;
> > +
> > +	for (i = 0; i < priv->path_size; i++) {
> > +		if (get_type(priv->path[i]) == type) {
> > +			if (count == idx)
> > +				return priv-
> > >ovl_adaptor_comp[priv->path[i]];
> > +			count++;
> > +		}
> > +	}
> > +	return NULL;
> > +}
> > +
> > +int mtk_ovlsys_adaptor_power_on(struct device *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	struct device *comp;
> > +	int ret = 0;
> > +	int i;
> > +
> > +	for (i = 0; i < OVLSYS_ADAPTOR_ID_MAX; i++) {
> 
> Why this for-loop is not as below example?
> 
> for (i = 0; i < priv->path_size; i++) {
> 
OK, I will try to fix this in the way of using  riv->path_size.
> > +		comp = priv->ovl_adaptor_comp[i];
> > +
> > +		if (!comp)
> > +			continue;
> > +
> > +		if (get_type(i) != OVLSYS_ADAPTOR_TYPE_EXDMA)
> 
> Why only EXDMA need power on?

The whole ovlsys_adatopr has the EXDMA, BLENDER, OUT_PROC,
and the ovlsys_adator using the same power source.

> 
> > +			continue;
> > +
> > +		ret = pm_runtime_get_sync(comp);
> > +		if (ret < 0) {
> > +			dev_err(dev, "Failed to enable power
> > domain %d, err %d\n", i, ret);
> > +			goto pwr_err;
> > +		}
> > +	}
> > +
> > +	return ret;
> > +pwr_err:
> > +	while (--i >= 0) {
> > +		comp = priv->ovl_adaptor_comp[i];
> > +		if (!comp)
> > +			continue;
> > +		if (get_type(i) != OVLSYS_ADAPTOR_TYPE_EXDMA)
> > +			continue;
> > +		pm_runtime_put(priv->ovl_adaptor_comp[i]);
> > +	}
> > +
> > +	return ret;
> > +}
> > +
> > +void mtk_ovlsys_adaptor_power_off(struct device *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	struct device *comp;
> > +	int i;
> > +
> > +	for (i = 0; i < OVLSYS_ADAPTOR_ID_MAX; i++) {
> > +		comp = priv->ovl_adaptor_comp[i];
> > +
> > +		if (!comp)
> > +			continue;
> > +
> > +		if (get_type(i) == OVLSYS_ADAPTOR_TYPE_EXDMA)
> > +			pm_runtime_put(comp);
> > +	}
> > +}
> > +
> > +void mtk_ovlsys_adaptor_layer_config(struct device *dev, unsigned
> > int idx,
> > +				???? struct mtk_plane_state
> > *state,
> > +				???? struct cmdq_pkt *cmdq_pkt)
> > +{
> > +	struct mtk_plane_pending_state *pending = &state->pending;
> > +	struct device *exdma;
> > +	struct device *blender;
> > +	unsigned int align_width = 0;
> > +	const struct drm_format_info *fmt_info =
> > drm_format_info(pending->format);
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +
> > +	DRM_DEV_DEBUG_DRIVER(dev, "idx:%d enable:%d fmt:0x%x
> > addr:0x%pad fb_w:%d {%d,%d,%d,%d}\n",
> > +			???? idx, pending->enable, pending-
> > >format,
> > +			???? &pending->addr, (pending->pitch /
> > fmt_info->cpp[0]),
> > +			???? pending->x, pending->y, pending-
> > >width, pending->height);
> > +
> > +	exdma = get_comp_by_type_idx(dev,
> > OVLSYS_ADAPTOR_TYPE_EXDMA, idx);
> 
> exdma = priv->ovl_adaptor_comp[priv->path[idx * 2]];
> 
> > +	if (!exdma) {
> 
> You just need to check idx < priv->layer_nr.
> 
> 
OK I will try to fix it.
> 
> > +		dev_err(dev, "%s: exdma%d comp not found\n",
> > __func__, idx);
> > +		return;
> > +	}
> > +	blender = get_comp_by_type_idx(dev,
> > OVLSYS_ADAPTOR_TYPE_BLENDER, idx);
> 
> blender = priv->ovl_adaptor_comp[priv->path[idx * 2 + 1]];
> 
> > +	if (!blender) {
> > +		dev_err(dev, "%s: blender%d comp not found\n",
> > __func__, idx);
> > +		return;
> > +	}
> > +
> > +	/* OVLSYS is in 1T2P domain, width needs to be 2 pixels
> > align */
> > +	align_width = ALIGN_DOWN(pending->width, 2);
> > +
> > +	if (pending->height == 0 || align_width == 0 ||
> > +	??? pending->x > priv->max_size || pending->y > priv-
> > >max_size) {
> > +		pending->enable = false;
> 
> Why modify pending->enable?
> 
> 
The EXDMA and BLENDER's layer_config setting is all check the flag. 

pending->enable
> 
> 
> 
> > +		mtk_disp_exdma_layer_config(exdma, state,
> > cmdq_pkt);
> > +		mtk_disp_blender_layer_config(blender, state,
> > cmdq_pkt);
> > +		return;
> > +	}
> > +
> > +	mtk_disp_exdma_layer_config(exdma, state, cmdq_pkt);
> > +
> > +	mtk_disp_blender_layer_config(blender, state, cmdq_pkt);
> > +
> > +	mtk_disp_exdma_start(exdma, cmdq_pkt);
> > +	mtk_disp_blender_start(blender, cmdq_pkt);
> 
> The start function is done in ovlsys_start(), so remove these start
> function.
> 
OK I will fix it.
> 
> > +}
> > +
> > +void mtk_ovlsys_adaptor_config(struct device *dev, unsigned int w,
> > +			?????? unsigned int h, unsigned int
> > vrefresh,
> > +			?????? unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	int i;
> > +	int blender_idx = 0;
> > +	bool most_top;
> > +	bool most_bottom;
> > +
> > +	for (i = 0; i < priv->path_size; i++) {
> > +		if (get_type(priv->path[i]) ==
> > OVLSYS_ADAPTOR_TYPE_BLENDER) {
> > +			blender_idx++;
> > +
> > +			if (priv->layer_nr == 1) {
> > +				most_top??? =
> > true;	/*SINGLE_BLENDER;*/
> > +				most_bottom = false;	/*blender
> > is LAST_BLENDER*/
> 
> Only one blender, so most_bottom = true;
Ok, I will fix it.
> 
> > +			} else if (blender_idx == 1) {
> > +				most_top??? = false;	/* NON-
> > SINGLE LAYER */
> > +				most_bottom = true;	/* FIRST
> > LAYER */
> > +			} else if (blender_idx == priv->layer_nr)
> > {
> > +				most_top??? = true;	/* NON-
> > SINGLE LAYER */
> > +				most_bottom = false;	/* LAST
> > LAYER */
> > +			} else {
> > +				most_top = false;	/* NON-
> > SINGLE LAYER */
> > +				most_bottom = false;	/* OTHER
> > LAYER */
> > +			}
> > +
> > +			mtk_disp_blender_config(priv-
> > >ovl_adaptor_comp[priv->path[i]], w, h,
> > +						vrefresh, bpc,
> > most_top, most_bottom, cmdq_pkt);
> 
> You could remove the if-else checking, and 
> 
> mtk_disp_blender_config(priv->ovl_adaptor_comp[priv->path[i]], w, h,
> ?vrefresh, bpc, blender_idx == priv->layer_nr,
> 			blender_idx == 1, cmdq_pkt);

Ok, I will fix it.
> 
> > +		} else if (get_type(priv->path[i]) ==
> > OVLSYS_ADAPTOR_TYPE_OUTPROC) {
> > +			mtk_disp_outproc_config(priv-
> > >ovl_adaptor_comp[priv->path[i]], w, h,
> > +						vrefresh, bpc,
> > cmdq_pkt);
> > +		}
> > +	}
> > +}
> > +
> > +int mtk_ovlsys_adaptor_layer_check(struct device *dev,
> > +				?? unsigned int idx,
> > +				?? struct mtk_plane_state
> > *mtk_state)
> > +{
> > +	struct drm_plane_state *state = &mtk_state->base;
> > +
> > +	/* Check if any unsupported rotation is set */
> > +	if (state->rotation & ~DRM_MODE_ROTATE_0)
> > +		return -EINVAL;
> > +
> > +	return 0;
> > +}
> > +
> > +void mtk_ovlsys_adaptor_start(struct device *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	int i;
> > +
> > +	for (i = 0; i < priv->path_size; i++) {
> > +		if (get_type(priv->path[i]) ==
> > OVLSYS_ADAPTOR_TYPE_EXDMA)
> > +			mtk_disp_exdma_start(priv-
> > >ovl_adaptor_comp[priv->path[i]], NULL);
> > +		else if (get_type(priv->path[i]) ==
> > OVLSYS_ADAPTOR_TYPE_BLENDER)
> > +			mtk_disp_blender_start(priv-
> > >ovl_adaptor_comp[priv->path[i]], NULL);
> > +		else
> > +			mtk_disp_outproc_start(priv-
> > >ovl_adaptor_comp[priv->path[i]]);
> > +	}
> 
> I think the order in path has some rule, so this for-loop could be
> simplified as
> 
> for (i = 0; i < (priv->path_size - 1); i += 2) {
> 	mtk_disp_exdma_start(priv->ovl_adaptor_comp[priv->path[i]],
> NULL);
> 	mtk_disp_blender_start(priv->ovl_adaptor_comp[priv->path[i +
> 1]], NULL);
> }
> 
Ok, I will fix it.
> mtk_disp_outproc_start(priv->ovl_adaptor_comp[priv->path[i]]);
> 
> > +}
> > +
> > +void mtk_ovlsys_adaptor_stop(struct device *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	int i;
> > +
> > +	for (i = 0; i < priv->path_size; i++) {
> > +		if (get_type(priv->path[i]) ==
> > OVLSYS_ADAPTOR_TYPE_EXDMA)
> > +			mtk_disp_exdma_stop(priv-
> > >ovl_adaptor_comp[priv->path[i]], NULL);
> > +		else if (get_type(priv->path[i]) ==
> > OVLSYS_ADAPTOR_TYPE_BLENDER)
> > +			mtk_disp_blender_stop(priv-
> > >ovl_adaptor_comp[priv->path[i]], NULL);
> > +		else
> > +			mtk_disp_outproc_stop(priv-
> > >ovl_adaptor_comp[priv->path[i]]);
> > +	}
> > +}
> > +
> > +int mtk_ovlsys_adaptor_clk_enable(struct device *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	struct device *comp;
> > +	int ret = 0;
> > +	int i;
> > +
> > +	for (i = 0; i < OVLSYS_ADAPTOR_ID_MAX; i++) {
> 
> Why this for-loop is not as below?
> 
Ok, I will fix it.
> for (i = 0; i < priv->path_size; i++) {
> 
> > +		comp = priv->ovl_adaptor_comp[i];
> > +
> > +		if (!comp)
> > +			continue;
> > +
> > +		if (get_type(i) == OVLSYS_ADAPTOR_TYPE_EXDMA)
> > +			ret = mtk_disp_exdma_clk_enable(comp);
> > +		else if (get_type(i) ==
> > OVLSYS_ADAPTOR_TYPE_BLENDER)
> > +			ret = mtk_disp_blender_clk_enable(comp);
> > +		else
> > +			ret = mtk_disp_outproc_clk_enable(comp);
> > +
> > +		if (ret) {
> > +			dev_err(dev, "Failed to enable clock %d,
> > err %d\n", i, ret);
> > +			goto clk_err;
> > +		}
> > +	}
> > +
> > +	return ret;
> > +
> > +clk_err:
> > +	while (--i >= 0) {
> > +		comp = priv->ovl_adaptor_comp[i];
> > +		if (!comp)
> > +			continue;
> > +		if (get_type(i) == OVLSYS_ADAPTOR_TYPE_EXDMA)
> > +			mtk_disp_exdma_clk_disable(comp);
> > +		else if (get_type(i) ==
> > OVLSYS_ADAPTOR_TYPE_BLENDER)
> > +			mtk_disp_blender_clk_disable(comp);
> > +		else
> > +			mtk_disp_outproc_clk_disable(comp);
> > +	}
> > +	i = OVLSYS_ADAPTOR_ID_MAX;
> 
> Why assign i here?
> 
It's the redundant. I will fix it.
> 
> > +
> > +	return ret;
> > +}
> > +
> > +void mtk_ovlsys_adaptor_clk_disable(struct device *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	struct device *comp;
> > +	int i;
> > +
> > +	for (i = 0; i < OVLSYS_ADAPTOR_ID_MAX; i++) {
> > +		comp = priv->ovl_adaptor_comp[i];
> > +
> > +		if (!comp)
> > +			continue;
> > +
> > +		if (get_type(i) == OVLSYS_ADAPTOR_TYPE_EXDMA)
> > +			mtk_disp_exdma_clk_disable(comp);
> > +		else if (get_type(i) ==
> > OVLSYS_ADAPTOR_TYPE_BLENDER)
> > +			mtk_disp_blender_clk_disable(comp);
> > +		else
> > +			mtk_disp_outproc_clk_disable(comp);
> > +	}
> > +}
> > +
> > +unsigned int mtk_ovlsys_adaptor_layer_nr(struct device *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +
> > +	return priv->layer_nr;
> > +}
> > +
> > +struct device *mtk_ovlsys_adaptor_dma_dev_get(struct device *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +
> > +	return priv->ovl_adaptor_comp[priv->path[0]];
> > +}
> > +
> > +void mtk_ovlsys_adaptor_register_vblank_cb(struct device *dev,
> > void (*vblank_cb)(void *),
> > +					?? void *vblank_cb_data)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +
> > +	mtk_disp_outproc_register_vblank_cb(priv-
> > >ovl_adaptor_comp[priv->path[priv->path_size - 1]],
> > +					??? vblank_cb,
> > vblank_cb_data);
> > +}
> > +
> > +void mtk_ovlsys_adaptor_unregister_vblank_cb(struct device *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	struct device *comp = priv->ovl_adaptor_comp[priv-
> > >path[priv->path_size - 1]];
> > +
> > +	mtk_disp_outproc_unregister_vblank_cb(comp);
> > +}
> > +
> > +void mtk_ovlsys_adaptor_enable_vblank(struct device *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +
> > +	mtk_disp_outproc_enable_vblank(priv-
> > >ovl_adaptor_comp[priv->path[priv->path_size - 1]]);
> > +}
> > +
> > +void mtk_ovlsys_adaptor_disable_vblank(struct device *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +
> > +	mtk_disp_outproc_disable_vblank(priv-
> > >ovl_adaptor_comp[priv->path[priv->path_size - 1]]);
> > +}
> > +
> > +u32 mtk_ovlsys_adaptor_get_blend_modes(struct device *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	struct device *comp;
> > +	int i;
> > +
> > +	for (i = 0; i < priv->path_size; i++)
> > +		if (get_type(priv->path[i]) ==
> > OVLSYS_ADAPTOR_TYPE_BLENDER) {
> > +			comp = priv->ovl_adaptor_comp[priv-
> > >path[i]];
> > +			return
> > mtk_disp_blender_get_blend_modes(comp);
> > +		}
> 
> In mtk_ovlsys_adaptor_get_formats(), you have assume that priv-
> >ovl_adaptor_comp[priv->path[0]] is exdma,
> so you could assume that priv->ovl_adaptor_comp[priv->path[1]] is
> blender.
> Then
> 
> return mtk_disp_blender_get_blend_modes(priv->ovl_adaptor_comp[priv-
> >path[1]]);
> 
Ok, I will try to fix it.
> > +
> > +	return 0;
> > +}
> > +
> > +const u32 *mtk_ovlsys_adaptor_get_formats(struct device *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +
> > +	return mtk_disp_exdma_get_formats(priv-
> > >ovl_adaptor_comp[priv->path[0]]);
> > +}
> > +
> > +size_t mtk_ovlsys_adaptor_get_num_formats(struct device *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +
> > +	return mtk_disp_exdma_get_num_formats(priv-
> > >ovl_adaptor_comp[priv->path[0]]);
> > +}
> > +
> > +void mtk_ovlsys_adaptor_add_comp(struct device *dev, struct
> > mtk_mutex *mutex)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	int i;
> > +
> > +	for (i = 0; i < priv->path_size; i++)
> > +		mtk_mutex_add_comp(mutex, get_ddp_comp_id(priv-
> > >path[i]));
> > +}
> > +
> > +void mtk_ovlsys_adaptor_remove_comp(struct device *dev, struct
> > mtk_mutex *mutex)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	int i;
> > +
> > +	for (i = 0; i < priv->path_size; i++)
> > +		mtk_mutex_remove_comp(mutex, get_ddp_comp_id(priv-
> > >path[i]));
> > +}
> > +
> > +void mtk_ovlsys_adaptor_connect(struct device *dev, struct device
> > *mmsys_dev, unsigned int next)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	int i;
> > +
> > +	for (i = 0; i < priv->path_size - 1; i++)
> > +		mtk_mmsys_ddp_connect(mmsys_dev,
> > get_ddp_comp_id(priv->path[i]),
> > +				????? get_ddp_comp_id(priv->path[i
> > + 1]));
> > +
> > +	mtk_mmsys_ddp_connect(mmsys_dev, get_ddp_comp_id(priv-
> > >path[i]), next);
> > +}
> > +
> > +void mtk_ovlsys_adaptor_disconnect(struct device *dev, struct
> > device *mmsys_dev, unsigned int next)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	int i;
> > +
> > +	for (i = 0; i < priv->path_size - 1; i++)
> > +		mtk_mmsys_ddp_disconnect(mmsys_dev,
> > get_ddp_comp_id(priv->path[i]),
> > +					 get_ddp_comp_id(priv-
> > >path[i + 1]));
> > +
> > +	mtk_mmsys_ddp_disconnect(mmsys_dev, get_ddp_comp_id(priv-
> > >path[i]), next);
> > +}
> > +
> > +static int ovlsys_adaptor_comp_get_id(struct device *dev, struct
> > device_node *node,
> > +				????? enum
> > mtk_ovlsys_adaptor_comp_type type,
> > +				????? enum mtk_ddp_comp_id
> > *comp_id)
> > +{
> > +	int alias_id = of_alias_get_id(node,
> > private_comp_stem[type]);
> > +	int i;
> > +
> > +	for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> > +		if (comp_matches[i].type == type &&
> > +		??? comp_matches[i].alias_id == alias_id) {
> > +			*comp_id = comp_matches[i].comp_id;
> > +			return i;
> > +		}
> > +	dev_warn(dev, "Failed to get id. type: %d, alias: %d\n",
> > type, alias_id);
> > +	return -EINVAL;
> > +}
> > +
> > +static const struct of_device_id mtk_ovlsys_adaptor_comp_dt_ids[]
> > = {
> > +	{
> > +		.compatible = "mediatek,mt8196-exdma",
> > +		.data = (void *)OVLSYS_ADAPTOR_TYPE_EXDMA,
> > +	}, {
> > +		.compatible = "mediatek,mt8196-blender",
> > +		.data = (void *)OVLSYS_ADAPTOR_TYPE_BLENDER,
> > +	}, {
> > +		.compatible = "mediatek,mt8196-outproc",
> > +		.data = (void *)OVLSYS_ADAPTOR_TYPE_OUTPROC,
> > +	},
> > +	{},
> > +};
> > +
> > +static int ovlsys_adaptor_comp_init(struct device *dev, struct
> > component_match **match)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	struct device_node *node, *parent;
> > +	struct platform_device *comp_pdev;
> > +	int i;
> > +
> > +	parent = dev->parent->parent->of_node->parent;
> > +
> > +	for_each_child_of_node(parent, node) {
> 
> for_each_child_of_node_scoped()
> 
Ok, I will fix it.
> > +		const struct of_device_id *of_id;
> > +		enum mtk_ovlsys_adaptor_comp_type type;
> > +		enum mtk_ddp_comp_id comp_id;
> 
> comp_id is useless, drop it.

Ok, I will fix it.
> 
> > +		int id;
> > +		bool found = false;
> > +
> > +		of_id =
> > of_match_node(mtk_ovlsys_adaptor_comp_dt_ids, node);
> > +		if (!of_id)
> > +			continue;
> > +
> > +		if (!of_device_is_available(node)) {
> > +			dev_dbg(dev, "Skipping disabled component
> > %pOF\n",
> > +				node);
> > +			continue;
> > +		}
> > +
> > +		type = (enum
> > mtk_ovlsys_adaptor_comp_type)(uintptr_t)of_id->data;
> > +		id = ovlsys_adaptor_comp_get_id(dev, node, type,
> > &comp_id);
> > +		if (id < 0) {
> > +			dev_warn(dev, "Skipping unknown component
> > %pOF\n",
> > +				 node);
> > +			continue;
> > +		}
> > +
> > +		for (i = 0; i < priv->path_size; i++)
> > +			if (priv->path[i] == id)
> > +				found = true;
> > +
> > +		if (!found)
> > +			continue;
> > +
> > +		comp_pdev = of_find_device_by_node(node);
> > +		if (!comp_pdev)
> > +			return -EPROBE_DEFER;
> > +
> > +		priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
> > +
> > +		drm_of_component_match_add(dev, match,
> > component_compare_of, node);
> > +		dev_dbg(dev, "Adding component match for %pOF\n",
> > node);
> > +	}
> > +
> > +	if (!*match) {
> > +		dev_err(dev, "No match device for
> > ovlsys_adaptor\n");
> > +		return -ENODEV;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static int mtk_disp_ovlsys_adaptor_comp_bind(struct device *dev,
> > struct device *master,
> > +					???? void *data)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +
> > +	if (!priv->children_bound)
> > +		return -EPROBE_DEFER;
> > +
> > +	return 0;
> > +}
> > +
> > +static void mtk_disp_ovlsys_adaptor_comp_unbind(struct device
> > *dev, struct device *master,
> > +						void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_ovlsys_adaptor_comp_ops
> > = {
> > +	.bind	= mtk_disp_ovlsys_adaptor_comp_bind,
> > +	.unbind = mtk_disp_ovlsys_adaptor_comp_unbind,
> > +};
> > +
> > +static int mtk_disp_ovlsys_adaptor_master_bind(struct device *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +	int ret, i;
> > +	unsigned int layer_nr = 0;
> > +
> > +	ret = component_bind_all(dev, priv->mmsys_dev);
> > +	if (ret)
> > +		return dev_err_probe(dev, ret, "component_bind_all
> > failed!\n");
> > +
> > +	priv->children_bound = true;
> > +
> > +	for (i = 0; i < priv->path_size; i++)
> > +		if (comp_matches[priv->path[i]].type ==
> > OVLSYS_ADAPTOR_TYPE_BLENDER)
> > +			layer_nr++;
> 
> It seems you could drop layer_nr.
> Assign priv->layer_nr to 0 first, and then priv->layer_nr++.

Ok, I will fix it.
> 
> > +	priv->layer_nr = layer_nr;
> > +
> > +	return 0;
> > +}
> > +
> > +static void mtk_disp_ovlsys_adaptor_master_unbind(struct device
> > *dev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv =
> > dev_get_drvdata(dev);
> > +
> > +	priv->children_bound = false;
> > +}
> > +
> > +static const struct component_master_ops
> > mtk_disp_ovlsys_adaptor_master_ops = {
> > +	.bind		= mtk_disp_ovlsys_adaptor_master_bind,
> > +	.unbind		=
> > mtk_disp_ovlsys_adaptor_master_unbind,
> > +};
> > +
> > +static int mtk_disp_ovlsys_adaptor_probe(struct platform_device
> > *pdev)
> > +{
> > +	struct mtk_disp_ovlsys_adaptor *priv;
> > +	struct device *dev = &pdev->dev;
> > +	struct component_match *match = NULL;
> > +	struct mtk_ovlsys_platform_data *ovlsys_priv;
> > //mtk_drm_ovlsys_private
> 
> Remove the comment.

Ok, I will fix it.
> 
> > +	int ret;
> > +
> > +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > +	if (!priv)
> > +		return -ENOMEM;
> > +
> > +	platform_set_drvdata(pdev, priv);
> > +
> > +	ovlsys_priv = pdev->dev.platform_data;
> > +	priv->mmsys_dev = ovlsys_priv->mmsys_dev;
> > +	priv->max_size = OVLSYS_ADAPTOR_DRIVER_DATA_MAX_SIZE;
> > +
> > +	if (ovlsys_priv->use_path == CRTC_MAIN) {
> > +		priv->path = mt8196_mtk_ovl_main;
> > +		priv->path_size = ARRAY_SIZE(mt8196_mtk_ovl_main);
> > +	} else if (ovlsys_priv->use_path == CRTC_EXT) {
> > +		priv->path = mt8196_mtk_ovl_ext;
> > +		priv->path_size = ARRAY_SIZE(mt8196_mtk_ovl_ext);
> > +	} else if (ovlsys_priv->use_path == CRTC_THIRD) {
> > +		priv->path = mt8196_mtk_ovl_third;
> > +		priv->path_size =
> > ARRAY_SIZE(mt8196_mtk_ovl_third);
> > +	}
> > +
> > +	ret = ovlsys_adaptor_comp_init(dev, &match);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	component_master_add_with_match(dev,
> > &mtk_disp_ovlsys_adaptor_master_ops, match);
> > +
> > +	pm_runtime_enable(dev);
> > +
> > +	ret = component_add(dev,
> > &mtk_disp_ovlsys_adaptor_comp_ops);
> > +	if (ret != 0) {
> > +		pm_runtime_disable(dev);
> > +		dev_err(dev, "Failed to add component: %d\n",
> > ret);
> > +	}
> > +
> > +	return ret;
> > +}
> > +
> > +static void mtk_disp_ovlsys_adaptor_remove(struct platform_device
> > *pdev)
> > +{
> > +	component_master_del(&pdev->dev,
> > &mtk_disp_ovlsys_adaptor_master_ops);
> > +	pm_runtime_disable(&pdev->dev);
> > +}
> > +
> > +struct platform_driver mtk_disp_ovlsys_adaptor_driver = {
> > +	.probe		= mtk_disp_ovlsys_adaptor_probe,
> > +	.remove		= mtk_disp_ovlsys_adaptor_remove,
> > +	.driver		= {
> > +		.name	= "mediatek-disp-ovlsys-adaptor",
> > +		.owner	= THIS_MODULE,
> > +	},
> > +};
> > +
> > +MODULE_AUTHOR("Nancy Lin <nancy.lin at mediatek.com>");
> > +MODULE_DESCRIPTION("MediaTek Ovlsys Adaptor Driver");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index f7b9c7a982a7..0639201e2e92 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -457,6 +457,27 @@ static bool mtk_drm_find_mmsys_comp(struct
> > mtk_drm_private *private, int comp_id
> > ?	return false;
> > ?}
> > ?
> > +static int mtk_drm_mmsys_comp_in_path(struct mtk_drm_private
> > *private, int comp_id)
> > +{
> > +	const struct mtk_mmsys_driver_data *drv_data = private-
> > >data;
> > +	int i;
> > +
> > +	if (drv_data->main_path)
> > +		for (i = 0; i < drv_data->main_len; i++)
> > +			if (drv_data->main_path[i] == comp_id)
> > +				return CRTC_MAIN;
> > +	if (drv_data->ext_path)
> > +		for (i = 0; i < drv_data->ext_len; i++)
> > +			if (drv_data->ext_path[i] == comp_id)
> > +				return CRTC_EXT;
> > +	if (drv_data->third_path)
> > +		for (i = 0; i < drv_data->third_len; i++)
> > +			if (drv_data->third_path[i] == comp_id)
> > +				return CRTC_THIRD;
> > +
> 
> This function is almost like mtk_drm_find_mmsys_comp(), try to merge
> them.
> 

Ok, I will try to merge the mtk_drm_find_mmsys_comp() and
mtk_drm_mmsys_comp_in_path.
> > +	return -EINVAL;
> > +}
> > +
> > ?static int mtk_drm_kms_init(struct drm_device *drm)
> > ?{
> > ?	struct mtk_drm_private *private = drm->dev_private;
> > @@ -1122,6 +1143,57 @@ static int mtk_drm_probe(struct
> > platform_device *pdev)
> > ?		component_match_add(dev, &match, compare_dev,
> > &ovl_adaptor->dev);
> > ?	}
> > ?
> > +	if (mtk_drm_find_mmsys_comp(private,
> > DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0)) {
> > +		struct mtk_ovlsys_platform_data ovlsys_priv;
> > +
> > +		ovlsys_priv.mmsys_dev = private->mmsys_dev;
> > +		ovlsys_priv.use_path =
> > +		mtk_drm_mmsys_comp_in_path(private,
> > DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0);
> > +		ovl_adaptor =
> > +			platform_device_register_data(dev,
> > "mediatek-disp-ovlsys-adaptor",
> > +						?????
> > PLATFORM_DEVID_AUTO,
> > +						????? (void
> > *)&ovlsys_priv,
> > +						?????
> > sizeof(struct mtk_ovlsys_platform_data));
> > +		private-
> > >ddp_comp[DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0].dev = &ovl_adaptor-
> > >dev;
> > +		mtk_ddp_comp_init(NULL, &private-
> > >ddp_comp[DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0],
> > +				?
> > DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0);
> > +		component_match_add(dev, &match, compare_dev,
> > &ovl_adaptor->dev);
> > +	}
> > +
> > +	if (mtk_drm_find_mmsys_comp(private,
> > DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1)) {
> > +		struct mtk_ovlsys_platform_data ovlsys_priv;
> > //mtk_drm_ovlsys_private
> > +
> > +		ovlsys_priv.mmsys_dev = private->mmsys_dev;
> > +		ovlsys_priv.use_path =
> > +		mtk_drm_mmsys_comp_in_path(private,
> > DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1);
> > +		ovl_adaptor =
> > +			platform_device_register_data(dev,
> > "mediatek-disp-ovlsys-adaptor",
> > +						?????
> > PLATFORM_DEVID_AUTO,
> > +						????? (void
> > *)&ovlsys_priv,
> > +						?????
> > sizeof(struct mtk_ovlsys_platform_data));
> > +		private-
> > >ddp_comp[DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1].dev = &ovl_adaptor-
> > >dev;
> > +		mtk_ddp_comp_init(NULL, &private-
> > >ddp_comp[DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1],
> > +				?
> > DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1);
> > +		component_match_add(dev, &match, compare_dev,
> > &ovl_adaptor->dev);
> > +	}
> > +
> > +	if (mtk_drm_find_mmsys_comp(private,
> > DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2)) {
> > +		struct mtk_ovlsys_platform_data ovlsys_priv;
> > +
> > +		ovlsys_priv.mmsys_dev = private->mmsys_dev;
> > +		ovlsys_priv.use_path =
> > +			mtk_drm_mmsys_comp_in_path(private,
> > DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2);
> > +		ovl_adaptor =
> > +			platform_device_register_data(dev,
> > "mediatek-disp-ovlsys-adaptor",
> > +						?????
> > PLATFORM_DEVID_AUTO,
> > +						????? (void
> > *)&ovlsys_priv,
> > +						?????
> > sizeof(struct? mtk_ovlsys_platform_data));
> > +		private-
> > >ddp_comp[DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2].dev = &ovl_adaptor-
> > >dev;
> > +		mtk_ddp_comp_init(NULL, &private-
> > >ddp_comp[DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2],
> > +				?
> > DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2);
> > +		component_match_add(dev, &match, compare_dev,
> > &ovl_adaptor->dev);
> > +	}
> 
> The code about these three path are almost the same.
> Try to merge them.
> You could use one function with different parameter
> (such as DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0,
> DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1,
> DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2).
> 
OK I will try to merge them.
> > +
> > ?	/* Iterate over sibling DISP function blocks */
> > ?	for_each_child_of_node(phandle->parent, node) {
> > ?		enum mtk_ddp_comp_type comp_type;
> > @@ -1283,6 +1355,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> > ?	&mtk_disp_outproc_driver,
> > ?	&mtk_disp_ovl_adaptor_driver,
> > ?	&mtk_disp_ovl_driver,
> > +	&mtk_disp_ovlsys_adaptor_driver,
> > ?	&mtk_disp_rdma_driver,
> > ?	&mtk_dpi_driver,
> > ?	&mtk_drm_platform_driver,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index c4717c37b0f1..6e9ed9837c5b 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -11,7 +11,9 @@
> > ?
> > ?#define MAX_CONNECTOR	2
> > ?#define DDP_COMPONENT_DRM_OVL_ADAPTOR (DDP_COMPONENT_ID_MAX + 1)
> > -#define DDP_COMPONENT_DRM_ID_MAX (DDP_COMPONENT_DRM_OVL_ADAPTOR +
> > 1)
> > +#define DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0
> > (DDP_COMPONENT_DRM_OVL_ADAPTOR + 1)
> > +#define DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1
> > (DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0 + 1)
> > +#define DDP_COMPONENT_DRM_ID_MAX
> > (DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1 + 1)
> > ?
> > ?enum mtk_crtc_path {
> > ?	CRTC_MAIN,
> > @@ -69,6 +71,12 @@ struct mtk_drm_private {
> > ?	struct mtk_drm_private **all_drm_private;
> > ?};
> > ?
> > +struct mtk_ovlsys_platform_data {//mtk_drm_ovlsys_private
> 
> Remove this comment
> 
Ok, I will fix it.
> 
> > +	struct device *mmsys_dev;
> > +	struct device *mutex_dev;
> 
> mutex_dev is useless, drop it.
> 
> Regards,
> CK
> 
Ok, I will fix it. Thanks for all the comment and review.


Best, Paul
> > +	unsigned int use_path;
> > +};
> > +
> > ?extern struct platform_driver mtk_disp_aal_driver;
> > ?extern struct platform_driver mtk_disp_blender_driver;
> > ?extern struct platform_driver mtk_disp_ccorr_driver;
> > @@ -79,6 +87,7 @@ extern struct platform_driver
> > mtk_disp_merge_driver;
> > ?extern struct platform_driver mtk_disp_outproc_driver;
> > ?extern struct platform_driver mtk_disp_ovl_adaptor_driver;
> > ?extern struct platform_driver mtk_disp_ovl_driver;
> > +extern struct platform_driver mtk_disp_ovlsys_adaptor_driver;
> > ?extern struct platform_driver mtk_disp_rdma_driver;
> > ?extern struct platform_driver mtk_dpi_driver;
> > ?extern struct platform_driver mtk_dsi_driver;
> 


From Paul-pl.Chen at mediatek.com  Wed May 14 09:25:30 2025
From: Paul-pl.Chen at mediatek.com (=?utf-8?B?UGF1bC1wbCBDaGVuICjpmbPmn4/pnJYp?=)
Date: Wed, 14 May 2025 16:25:30 +0000
Subject: [PATCH v2 03/15] dt-bindings: display: mediatek: add EXDMA yaml
 for MT8196
In-Reply-To: <990774c68015d73fee297d12992d7c3e6421cc71.camel@mediatek.com>
References: <20250321093435.94835-1-paul-pl.chen@mediatek.com>
	 <20250321093435.94835-4-paul-pl.chen@mediatek.com>
	 <990774c68015d73fee297d12992d7c3e6421cc71.camel@mediatek.com>
Message-ID: <4051e2b2249625f0e957352a4a2dfe2cf50818a4.camel@mediatek.com>

On Mon, 2025-03-24 at 02:45 +0000, CK Hu (???) wrote:
> On Fri, 2025-03-21 at 17:33 +0800, paul-pl.chen wrote:
> > From: Paul-pl Chen <paul-pl.chen at mediatek.com>
> > 
> > Add mediatek,exdma.yaml to support EXDMA for MT8196.
> > The MediaTek display overlap extended DMA engine, namely
> > OVL_EXDMA or EXDMA, primarily functions as a DMA engine
> > for reading data from DRAM with various DRAM footprints
> > and data formats.
> > 
> > Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
> > ---
> > ?.../bindings/dma/mediatek,exdma.yaml????????? | 70
> > +++++++++++++++++++
> > ?1 file changed, 70 insertions(+)
> > ?create mode 100644
> > Documentation/devicetree/bindings/dma/mediatek,exdma.yaml
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/dma/mediatek,exdma.yaml
> > b/Documentation/devicetree/bindings/dma/mediatek,exdma.yaml
> > new file mode 100644
> > index 000000000000..de7f8283bb48
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/mediatek,exdma.yaml
> > @@ -0,0 +1,70 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/dma/mediatek,exdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!jH_-2I8NkTUX90vbZGjduUAo4on8DsCGFTrVX5jUdxL_zpKt5PSPRGm31otPZ4wIDzI2h9HFGbF4DC5jPw1nejo$
> > ?
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jH_-2I8NkTUX90vbZGjduUAo4on8DsCGFTrVX5jUdxL_zpKt5PSPRGm31otPZ4wIDzI2h9HFGbF4DC5jr1jxJoQ$
> > ?
> > +
> > +title: MediaTek display overlap extended DMA engine
> > +
> > +maintainers:
> > +? - Chun-Kuang Hu <chunkuang.hu at kernel.org>
> > +? - Philipp Zabel <p.zabel at pengutronix.de>
> > +
> > +description:
> > +? The MediaTek display overlap extended DMA engine, namely
> > OVL_EXDMA or EXDMA,
> > +? primarily functions as a DMA engine for reading data from DRAM
> > with various
> > +? DRAM footprints and data formats. For input sources in certain
> > color formats
> > +? and color domains, OVL_EXDMA also includes a color transfer
> > function
> > +? to process pixels into a consistent color domain.
> > +
> > +properties:
> > +? compatible:
> > +??? const: mediatek,mt8196-exdma
> > +
> > +? reg:
> > +??? maxItems: 1
> > +
> > +? clocks:
> > +??? maxItems: 1
> > +
> > +? power-domains:
> > +??? maxItems: 1
> > +
> > +? mediatek,larb:
> > +??? $ref: /schemas/types.yaml#/definitions/phandle
> > +??? description: |
> > +????? A phandle to the local arbiters node in the current SoCs.
> > +????? Refer to bindings/memory-controllers/mediatek,smi-larb.yaml.
> > +
> > +? iommus:
> > +??? maxItems: 1
> > +
> > +? '#dma-cells':
> > +??? const: 1
> > +
> > +required:
> > +? - compatible
> > +? - reg
> > +? - clocks
> > +? - power-domains
> > +? - mediatek,larb
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +? - |
> > +
> > +??? soc {
> > +??????? #address-cells = <2>;
> > +??????? #size-cells = <2>;
> > +
> > +??????? disp_ovl0_exdma2: dma-controller at 32850000 {
> > +??????????? compatible = "mediatek,mt8196-exdma";
> > +??????????? reg = <0 0x32850000 0 0x1000>;
> > +??????????? clocks = <&ovlsys_config_clk 13>;
> > +??????????? power-domains = <&hfrpsys 12>;
> > +??????????? mediatek,larb = <&smi_larb0>;
> 
> larb is controlled by iommu, and exdma has already point to iommu.
> OVL also not point to larb, so it's not necessary to point to larb
> here.
> 
> Regards,
> CK
> 
> 
> 
This is for the device-link.

Best, Paul
> 
> > +??????????? iommus = <&mm_smmu 144>;
> > +??????????? #dma-cells = <1>;
> > +??????? };
> > +??? };
> 


From lorenzo at kernel.org  Wed May 14 10:09:56 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 14 May 2025 19:09:56 +0200
Subject: [PATCH net-next 0/2] net: airoha: Add per-flow stats support to hw
 flowtable offloading
Message-ID: <20250514-airoha-en7581-flowstats-v1-0-c00ede12a2ca@kernel.org>

Introduce per-flow stats accounting to the flowtable hw offload in the
airoha_eth driver. Flow stats are split in the PPE and NPU modules:
- PPE: accounts for high 32bit of per-flow stats
- NPU: accounts for low 32bit of per-flow stats

---
Lorenzo Bianconi (2):
      net: airoha: npu: Move memory allocation in airoha_npu_send_msg() caller
      net: airoha: Add FLOW_CLS_STATS callback support

 drivers/net/ethernet/airoha/Kconfig              |   7 +
 drivers/net/ethernet/airoha/airoha_eth.h         |  33 +++
 drivers/net/ethernet/airoha/airoha_npu.c         | 175 ++++++++++-----
 drivers/net/ethernet/airoha/airoha_npu.h         |   4 +-
 drivers/net/ethernet/airoha/airoha_ppe.c         | 265 +++++++++++++++++++++--
 drivers/net/ethernet/airoha/airoha_ppe_debugfs.c |   9 +-
 6 files changed, 420 insertions(+), 73 deletions(-)
---
base-commit: 664bf117a30804b442a88a8462591bb23f5a0f22
change-id: 20250415-airoha-en7581-flowstats-7e69cf3fd94d

Best regards,
-- 
Lorenzo Bianconi <lorenzo at kernel.org>



From lorenzo at kernel.org  Wed May 14 10:09:57 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 14 May 2025 19:09:57 +0200
Subject: [PATCH net-next 1/2] net: airoha: npu: Move memory allocation in
 airoha_npu_send_msg() caller
In-Reply-To: <20250514-airoha-en7581-flowstats-v1-0-c00ede12a2ca@kernel.org>
References: <20250514-airoha-en7581-flowstats-v1-0-c00ede12a2ca@kernel.org>
Message-ID: <20250514-airoha-en7581-flowstats-v1-1-c00ede12a2ca@kernel.org>

Move ppe_mbox_data struct memory allocation from airoha_npu_send_msg
routine to the caller one. This is a preliminary patch to enable wlan NPU
offloading and flow counter stats support.

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 drivers/net/ethernet/airoha/airoha_npu.c | 123 ++++++++++++++++++-------------
 1 file changed, 70 insertions(+), 53 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_npu.c b/drivers/net/ethernet/airoha/airoha_npu.c
index ead0625e781f57cd7c5883b6dd3d441db62292d3..2371677296aff1382f6e0516a8798739029e03fb 100644
--- a/drivers/net/ethernet/airoha/airoha_npu.c
+++ b/drivers/net/ethernet/airoha/airoha_npu.c
@@ -124,17 +124,12 @@ static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,
 	u16 core = 0; /* FIXME */
 	u32 val, offset = core << 4;
 	dma_addr_t dma_addr;
-	void *addr;
 	int ret;
 
-	addr = kmemdup(p, size, GFP_ATOMIC);
-	if (!addr)
-		return -ENOMEM;
-
-	dma_addr = dma_map_single(npu->dev, addr, size, DMA_TO_DEVICE);
+	dma_addr = dma_map_single(npu->dev, p, size, DMA_TO_DEVICE);
 	ret = dma_mapping_error(npu->dev, dma_addr);
 	if (ret)
-		goto out;
+		return ret;
 
 	spin_lock_bh(&npu->cores[core].lock);
 
@@ -155,8 +150,6 @@ static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,
 	spin_unlock_bh(&npu->cores[core].lock);
 
 	dma_unmap_single(npu->dev, dma_addr, size, DMA_TO_DEVICE);
-out:
-	kfree(addr);
 
 	return ret;
 }
@@ -261,76 +254,100 @@ static irqreturn_t airoha_npu_wdt_handler(int irq, void *core_instance)
 
 static int airoha_npu_ppe_init(struct airoha_npu *npu)
 {
-	struct ppe_mbox_data ppe_data = {
-		.func_type = NPU_OP_SET,
-		.func_id = PPE_FUNC_SET_WAIT_HWNAT_INIT,
-		.init_info = {
-			.ppe_type = PPE_TYPE_L2B_IPV4_IPV6,
-			.wan_mode = QDMA_WAN_ETHER,
-		},
-	};
+	struct ppe_mbox_data *ppe_data;
+	int err;
 
-	return airoha_npu_send_msg(npu, NPU_FUNC_PPE, &ppe_data,
-				   sizeof(struct ppe_mbox_data));
+	ppe_data = kzalloc(sizeof(*ppe_data), GFP_KERNEL);
+	if (!ppe_data)
+		return -ENOMEM;
+
+	ppe_data->func_type = NPU_OP_SET;
+	ppe_data->func_id = PPE_FUNC_SET_WAIT_HWNAT_INIT;
+	ppe_data->init_info.ppe_type = PPE_TYPE_L2B_IPV4_IPV6;
+	ppe_data->init_info.wan_mode = QDMA_WAN_ETHER;
+
+	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
+				  sizeof(*ppe_data));
+	kfree(ppe_data);
+
+	return err;
 }
 
 static int airoha_npu_ppe_deinit(struct airoha_npu *npu)
 {
-	struct ppe_mbox_data ppe_data = {
-		.func_type = NPU_OP_SET,
-		.func_id = PPE_FUNC_SET_WAIT_HWNAT_DEINIT,
-	};
+	struct ppe_mbox_data *ppe_data;
+	int err;
+
+	ppe_data = kzalloc(sizeof(*ppe_data), GFP_KERNEL);
+	if (!ppe_data)
+		return -ENOMEM;
+
+	ppe_data->func_type = NPU_OP_SET;
+	ppe_data->func_id = PPE_FUNC_SET_WAIT_HWNAT_DEINIT;
 
-	return airoha_npu_send_msg(npu, NPU_FUNC_PPE, &ppe_data,
-				   sizeof(struct ppe_mbox_data));
+	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
+				  sizeof(*ppe_data));
+	kfree(ppe_data);
+
+	return err;
 }
 
 static int airoha_npu_ppe_flush_sram_entries(struct airoha_npu *npu,
 					     dma_addr_t foe_addr,
 					     int sram_num_entries)
 {
-	struct ppe_mbox_data ppe_data = {
-		.func_type = NPU_OP_SET,
-		.func_id = PPE_FUNC_SET_WAIT_API,
-		.set_info = {
-			.func_id = PPE_SRAM_RESET_VAL,
-			.data = foe_addr,
-			.size = sram_num_entries,
-		},
-	};
+	struct ppe_mbox_data *ppe_data;
+	int err;
+
+	ppe_data = kzalloc(sizeof(*ppe_data), GFP_KERNEL);
+	if (!ppe_data)
+		return -ENOMEM;
 
-	return airoha_npu_send_msg(npu, NPU_FUNC_PPE, &ppe_data,
-				   sizeof(struct ppe_mbox_data));
+	ppe_data->func_type = NPU_OP_SET;
+	ppe_data->func_id = PPE_FUNC_SET_WAIT_API;
+	ppe_data->set_info.func_id = PPE_SRAM_RESET_VAL;
+	ppe_data->set_info.data = foe_addr;
+	ppe_data->set_info.size = sram_num_entries;
+
+	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
+				  sizeof(*ppe_data));
+	kfree(ppe_data);
+
+	return err;
 }
 
 static int airoha_npu_foe_commit_entry(struct airoha_npu *npu,
 				       dma_addr_t foe_addr,
 				       u32 entry_size, u32 hash, bool ppe2)
 {
-	struct ppe_mbox_data ppe_data = {
-		.func_type = NPU_OP_SET,
-		.func_id = PPE_FUNC_SET_WAIT_API,
-		.set_info = {
-			.data = foe_addr,
-			.size = entry_size,
-		},
-	};
+	struct ppe_mbox_data *ppe_data;
 	int err;
 
-	ppe_data.set_info.func_id = ppe2 ? PPE2_SRAM_SET_ENTRY
-					 : PPE_SRAM_SET_ENTRY;
+	ppe_data = kzalloc(sizeof(*ppe_data), GFP_ATOMIC);
+	if (!ppe_data)
+		return -ENOMEM;
+
+	ppe_data->func_type = NPU_OP_SET;
+	ppe_data->func_id = PPE_FUNC_SET_WAIT_API;
+	ppe_data->set_info.data = foe_addr;
+	ppe_data->set_info.size = entry_size;
+	ppe_data->set_info.func_id = ppe2 ? PPE2_SRAM_SET_ENTRY
+					  : PPE_SRAM_SET_ENTRY;
 
-	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, &ppe_data,
-				  sizeof(struct ppe_mbox_data));
+	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
+				  sizeof(*ppe_data));
 	if (err)
 		return err;
 
-	ppe_data.set_info.func_id = PPE_SRAM_SET_VAL;
-	ppe_data.set_info.data = hash;
-	ppe_data.set_info.size = sizeof(u32);
+	ppe_data->set_info.func_id = PPE_SRAM_SET_VAL;
+	ppe_data->set_info.data = hash;
+	ppe_data->set_info.size = sizeof(u32);
+
+	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
+				  sizeof(*ppe_data));
+	kfree(ppe_data);
 
-	return airoha_npu_send_msg(npu, NPU_FUNC_PPE, &ppe_data,
-				   sizeof(struct ppe_mbox_data));
+	return err;
 }
 
 struct airoha_npu *airoha_npu_get(struct device *dev)

-- 
2.49.0



From lorenzo at kernel.org  Wed May 14 10:09:58 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 14 May 2025 19:09:58 +0200
Subject: [PATCH net-next 2/2] net: airoha: Add FLOW_CLS_STATS callback
 support
In-Reply-To: <20250514-airoha-en7581-flowstats-v1-0-c00ede12a2ca@kernel.org>
References: <20250514-airoha-en7581-flowstats-v1-0-c00ede12a2ca@kernel.org>
Message-ID: <20250514-airoha-en7581-flowstats-v1-2-c00ede12a2ca@kernel.org>

Introduce per-flow stats accounting to the flowtable hw offload in
the airoha_eth driver. Flow stats are split in the PPE and NPU modules:
- PPE: accounts for high 32bit of per-flow stats
- NPU: accounts for low 32bit of per-flow stats

FLOW_CLS_STATS can be enabled or disabled at compile time.

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 drivers/net/ethernet/airoha/Kconfig              |   7 +
 drivers/net/ethernet/airoha/airoha_eth.h         |  33 +++
 drivers/net/ethernet/airoha/airoha_npu.c         |  52 ++++-
 drivers/net/ethernet/airoha/airoha_npu.h         |   4 +-
 drivers/net/ethernet/airoha/airoha_ppe.c         | 265 +++++++++++++++++++++--
 drivers/net/ethernet/airoha/airoha_ppe_debugfs.c |   9 +-
 6 files changed, 350 insertions(+), 20 deletions(-)

diff --git a/drivers/net/ethernet/airoha/Kconfig b/drivers/net/ethernet/airoha/Kconfig
index 1a4cf6a259f67adf9c6115e05de16b0585092573..ad3ce501e7a577b839b674406900ddaea88a9b83 100644
--- a/drivers/net/ethernet/airoha/Kconfig
+++ b/drivers/net/ethernet/airoha/Kconfig
@@ -24,4 +24,11 @@ config NET_AIROHA
 	  This driver supports the gigabit ethernet MACs in the
 	  Airoha SoC family.
 
+config NET_AIROHA_FLOW_STATS
+	default y
+	bool "Airoha flow stats"
+	depends on NET_AIROHA && NET_AIROHA_NPU
+	help
+	  Enable Aiorha flowtable statistic counters.
+
 endif #NET_VENDOR_AIROHA
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index 53f39083a8b05f365056f5d063f801c03e777953..531a3c49c1562a986111a1ce1c215c8751c16e09 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -50,6 +50,14 @@
 #define PPE_NUM				2
 #define PPE1_SRAM_NUM_ENTRIES		(8 * 1024)
 #define PPE_SRAM_NUM_ENTRIES		(2 * PPE1_SRAM_NUM_ENTRIES)
+#ifdef CONFIG_NET_AIROHA_FLOW_STATS
+#define PPE1_STATS_NUM_ENTRIES		(4 * 1024)
+#else
+#define PPE1_STATS_NUM_ENTRIES		0
+#endif /* CONFIG_NET_AIROHA_FLOW_STATS */
+#define PPE_STATS_NUM_ENTRIES		(2 * PPE1_STATS_NUM_ENTRIES)
+#define PPE1_SRAM_NUM_DATA_ENTRIES	(PPE1_SRAM_NUM_ENTRIES - PPE1_STATS_NUM_ENTRIES)
+#define PPE_SRAM_NUM_DATA_ENTRIES	(2 * PPE1_SRAM_NUM_DATA_ENTRIES)
 #define PPE_DRAM_NUM_ENTRIES		(16 * 1024)
 #define PPE_NUM_ENTRIES			(PPE_SRAM_NUM_ENTRIES + PPE_DRAM_NUM_ENTRIES)
 #define PPE_HASH_MASK			(PPE_NUM_ENTRIES - 1)
@@ -261,6 +269,8 @@ struct airoha_foe_mac_info {
 
 	u16 pppoe_id;
 	u16 src_mac_lo;
+
+	u32 meter;
 };
 
 #define AIROHA_FOE_IB1_UNBIND_PREBIND		BIT(24)
@@ -296,6 +306,11 @@ struct airoha_foe_mac_info {
 #define AIROHA_FOE_TUNNEL			BIT(6)
 #define AIROHA_FOE_TUNNEL_ID			GENMASK(5, 0)
 
+#define AIROHA_FOE_TUNNEL_MTU			GENMASK(31, 16)
+#define AIROHA_FOE_ACNT_GRP3			GENMASK(15, 9)
+#define AIROHA_FOE_METER_GRP3			GENMASK(8, 5)
+#define AIROHA_FOE_METER_GRP2			GENMASK(4, 0)
+
 struct airoha_foe_bridge {
 	u32 dest_mac_hi;
 
@@ -379,6 +394,8 @@ struct airoha_foe_ipv6 {
 	u32 ib2;
 
 	struct airoha_foe_mac_info_common l2;
+
+	u32 meter;
 };
 
 struct airoha_foe_entry {
@@ -397,6 +414,16 @@ struct airoha_foe_entry {
 	};
 };
 
+struct airoha_foe_stats {
+	u32 bytes;
+	u32 packets;
+};
+
+struct airoha_foe_stats64 {
+	u64 bytes;
+	u64 packets;
+};
+
 struct airoha_flow_data {
 	struct ethhdr eth;
 
@@ -447,6 +474,7 @@ struct airoha_flow_table_entry {
 	struct hlist_node l2_subflow_node; /* PPE L2 subflow entry */
 	u32 hash;
 
+	struct airoha_foe_stats64 stats;
 	enum airoha_flow_entry_type type;
 
 	struct rhash_head node;
@@ -523,6 +551,9 @@ struct airoha_ppe {
 	struct hlist_head *foe_flow;
 	u16 foe_check_time[PPE_NUM_ENTRIES];
 
+	struct airoha_foe_stats *foe_stats;
+	dma_addr_t foe_stats_dma;
+
 	struct dentry *debugfs_dir;
 };
 
@@ -582,6 +613,8 @@ int airoha_ppe_init(struct airoha_eth *eth);
 void airoha_ppe_deinit(struct airoha_eth *eth);
 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe,
 						  u32 hash);
+void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash,
+				    struct airoha_foe_stats64 *stats);
 
 #ifdef CONFIG_DEBUG_FS
 int airoha_ppe_debugfs_init(struct airoha_ppe *ppe);
diff --git a/drivers/net/ethernet/airoha/airoha_npu.c b/drivers/net/ethernet/airoha/airoha_npu.c
index 2371677296aff1382f6e0516a8798739029e03fb..a20e5916d3b0efd0859f347b33ff4e78b41e17ab 100644
--- a/drivers/net/ethernet/airoha/airoha_npu.c
+++ b/drivers/net/ethernet/airoha/airoha_npu.c
@@ -12,6 +12,7 @@
 #include <linux/of_reserved_mem.h>
 #include <linux/regmap.h>
 
+#include "airoha_eth.h"
 #include "airoha_npu.h"
 
 #define NPU_EN7581_FIRMWARE_DATA		"airoha/en7581_npu_data.bin"
@@ -72,6 +73,7 @@ enum {
 	PPE_FUNC_SET_WAIT_HWNAT_INIT,
 	PPE_FUNC_SET_WAIT_HWNAT_DEINIT,
 	PPE_FUNC_SET_WAIT_API,
+	PPE_FUNC_SET_WAIT_FLOW_STATS_SETUP,
 };
 
 enum {
@@ -115,6 +117,10 @@ struct ppe_mbox_data {
 			u32 size;
 			u32 data;
 		} set_info;
+		struct {
+			u32 npu_stats_addr;
+			u32 foe_stats_addr;
+		} stats_info;
 	};
 };
 
@@ -350,7 +356,40 @@ static int airoha_npu_foe_commit_entry(struct airoha_npu *npu,
 	return err;
 }
 
-struct airoha_npu *airoha_npu_get(struct device *dev)
+static int airoha_npu_stats_setup(struct airoha_npu *npu,
+				  dma_addr_t foe_stats_addr)
+{
+	int err, size = PPE_STATS_NUM_ENTRIES * sizeof(*npu->stats);
+	struct ppe_mbox_data *ppe_data;
+	void *stats;
+
+	if (!size) /* flow stats are disabled */
+		return 0;
+
+	ppe_data = kzalloc(sizeof(*ppe_data), GFP_ATOMIC);
+	if (!ppe_data)
+		return -ENOMEM;
+
+	ppe_data->func_type = NPU_OP_SET;
+	ppe_data->func_id = PPE_FUNC_SET_WAIT_FLOW_STATS_SETUP;
+	ppe_data->stats_info.foe_stats_addr = foe_stats_addr;
+
+	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
+				  sizeof(*ppe_data));
+	if (err)
+		return err;
+
+	stats = devm_ioremap(npu->dev,
+			     ppe_data->stats_info.npu_stats_addr, size);
+	if (!stats)
+		return -ENOMEM;
+
+	npu->stats = stats;
+
+	return 0;
+}
+
+struct airoha_npu *airoha_npu_get(struct device *dev, dma_addr_t *stats_addr)
 {
 	struct platform_device *pdev;
 	struct device_node *np;
@@ -388,6 +427,17 @@ struct airoha_npu *airoha_npu_get(struct device *dev)
 		goto error_module_put;
 	}
 
+	if (stats_addr) {
+		int err;
+
+		err = airoha_npu_stats_setup(npu, *stats_addr);
+		if (err) {
+			dev_err(dev, "failed to allocate npu stats buffer\n");
+			npu = ERR_PTR(err);
+			goto error_module_put;
+		}
+	}
+
 	return npu;
 
 error_module_put:
diff --git a/drivers/net/ethernet/airoha/airoha_npu.h b/drivers/net/ethernet/airoha/airoha_npu.h
index a2b8ae4d947398c1a4f1bb40c2b5118298e40481..7faeb90db6a7347024b56e5deb2a04e45de6c052 100644
--- a/drivers/net/ethernet/airoha/airoha_npu.h
+++ b/drivers/net/ethernet/airoha/airoha_npu.h
@@ -17,6 +17,8 @@ struct airoha_npu {
 		struct work_struct wdt_work;
 	} cores[NPU_NUM_CORES];
 
+	struct airoha_foe_stats *stats;
+
 	struct {
 		int (*ppe_init)(struct airoha_npu *npu);
 		int (*ppe_deinit)(struct airoha_npu *npu);
@@ -30,5 +32,5 @@ struct airoha_npu {
 	} ops;
 };
 
-struct airoha_npu *airoha_npu_get(struct device *dev);
+struct airoha_npu *airoha_npu_get(struct device *dev, dma_addr_t *stats_addr);
 void airoha_npu_put(struct airoha_npu *npu);
diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
index 6e9787c2843bc4f09240a0bbbd1f506c099d615e..9be0020695458c4a63a10a0d990f826baecf6f94 100644
--- a/drivers/net/ethernet/airoha/airoha_ppe.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe.c
@@ -102,7 +102,7 @@ static void airoha_ppe_hw_init(struct airoha_ppe *ppe)
 
 	if (airoha_ppe2_is_enabled(eth)) {
 		sram_num_entries =
-			PPE_RAM_NUM_ENTRIES_SHIFT(PPE1_SRAM_NUM_ENTRIES);
+			PPE_RAM_NUM_ENTRIES_SHIFT(PPE1_SRAM_NUM_DATA_ENTRIES);
 		airoha_fe_rmw(eth, REG_PPE_TB_CFG(0),
 			      PPE_SRAM_TB_NUM_ENTRY_MASK |
 			      PPE_DRAM_TB_NUM_ENTRY_MASK,
@@ -119,7 +119,7 @@ static void airoha_ppe_hw_init(struct airoha_ppe *ppe)
 					 dram_num_entries));
 	} else {
 		sram_num_entries =
-			PPE_RAM_NUM_ENTRIES_SHIFT(PPE_SRAM_NUM_ENTRIES);
+			PPE_RAM_NUM_ENTRIES_SHIFT(PPE_SRAM_NUM_DATA_ENTRIES);
 		airoha_fe_rmw(eth, REG_PPE_TB_CFG(0),
 			      PPE_SRAM_TB_NUM_ENTRY_MASK |
 			      PPE_DRAM_TB_NUM_ENTRY_MASK,
@@ -417,6 +417,77 @@ static u32 airoha_ppe_foe_get_entry_hash(struct airoha_foe_entry *hwe)
 	return hash;
 }
 
+static u32 airoha_ppe_foe_get_flow_stats_index(struct airoha_ppe *ppe, u32 hash)
+{
+	if (!airoha_ppe2_is_enabled(ppe->eth))
+		return hash;
+
+	return hash >= PPE_STATS_NUM_ENTRIES ? hash - PPE1_STATS_NUM_ENTRIES
+					     : hash;
+}
+
+static void airoha_ppe_foe_flow_stat_entry_reset(struct airoha_ppe *ppe,
+						 struct airoha_npu *npu,
+						 int index)
+{
+	memset(&npu->stats[index], 0, sizeof(*npu->stats));
+	memset(&ppe->foe_stats[index], 0, sizeof(*ppe->foe_stats));
+}
+
+static void airoha_ppe_foe_flow_stats_reset(struct airoha_ppe *ppe,
+					    struct airoha_npu *npu)
+{
+	int i;
+
+	for (i = 0; i < PPE_STATS_NUM_ENTRIES; i++)
+		airoha_ppe_foe_flow_stat_entry_reset(ppe, npu, i);
+}
+
+static void airoha_ppe_foe_flow_stats_update(struct airoha_ppe *ppe,
+					     struct airoha_npu *npu,
+					     struct airoha_foe_entry *hwe,
+					     u32 hash)
+{
+	int type = FIELD_GET(AIROHA_FOE_IB1_BIND_PACKET_TYPE, hwe->ib1);
+	u32 index, pse_port, val, *data, *ib2, *meter;
+	u8 nbq;
+
+	index = airoha_ppe_foe_get_flow_stats_index(ppe, hash);
+	if (index >= PPE_STATS_NUM_ENTRIES)
+		return;
+
+	if (type == PPE_PKT_TYPE_BRIDGE) {
+		data = &hwe->bridge.data;
+		ib2 = &hwe->bridge.ib2;
+		meter = &hwe->bridge.l2.meter;
+	} else if (type >= PPE_PKT_TYPE_IPV6_ROUTE_3T) {
+		data = &hwe->ipv6.data;
+		ib2 = &hwe->ipv6.ib2;
+		meter = &hwe->ipv6.meter;
+	} else {
+		data = &hwe->ipv4.data;
+		ib2 = &hwe->ipv4.ib2;
+		meter = &hwe->ipv4.l2.meter;
+	}
+
+	airoha_ppe_foe_flow_stat_entry_reset(ppe, npu, index);
+
+	val = FIELD_GET(AIROHA_FOE_CHANNEL | AIROHA_FOE_QID, *data);
+	*data = (*data & ~AIROHA_FOE_ACTDP) |
+		FIELD_PREP(AIROHA_FOE_ACTDP, val);
+
+	val = *ib2 & (AIROHA_FOE_IB2_NBQ | AIROHA_FOE_IB2_PSE_PORT |
+		      AIROHA_FOE_IB2_PSE_QOS | AIROHA_FOE_IB2_FAST_PATH);
+	*meter |= FIELD_PREP(AIROHA_FOE_TUNNEL_MTU, val);
+
+	pse_port = FIELD_GET(AIROHA_FOE_IB2_PSE_PORT, *ib2);
+	nbq = pse_port == 1 ? 6 : 5;
+	*ib2 &= ~(AIROHA_FOE_IB2_NBQ | AIROHA_FOE_IB2_PSE_PORT |
+		  AIROHA_FOE_IB2_PSE_QOS);
+	*ib2 |= FIELD_PREP(AIROHA_FOE_IB2_PSE_PORT, 6) |
+		FIELD_PREP(AIROHA_FOE_IB2_NBQ, nbq);
+}
+
 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe,
 						  u32 hash)
 {
@@ -470,6 +541,8 @@ static int airoha_ppe_foe_commit_entry(struct airoha_ppe *ppe,
 	struct airoha_foe_entry *hwe = ppe->foe + hash * sizeof(*hwe);
 	u32 ts = airoha_ppe_get_timestamp(ppe);
 	struct airoha_eth *eth = ppe->eth;
+	struct airoha_npu *npu;
+	int err = 0;
 
 	memcpy(&hwe->d, &e->d, sizeof(*hwe) - sizeof(hwe->ib1));
 	wmb();
@@ -478,25 +551,28 @@ static int airoha_ppe_foe_commit_entry(struct airoha_ppe *ppe,
 	e->ib1 |= FIELD_PREP(AIROHA_FOE_IB1_BIND_TIMESTAMP, ts);
 	hwe->ib1 = e->ib1;
 
+	rcu_read_lock();
+
+	npu = rcu_dereference(eth->npu);
+	if (!npu) {
+		err = -ENODEV;
+		goto unlock;
+	}
+
+	airoha_ppe_foe_flow_stats_update(ppe, npu, hwe, hash);
+
 	if (hash < PPE_SRAM_NUM_ENTRIES) {
 		dma_addr_t addr = ppe->foe_dma + hash * sizeof(*hwe);
 		bool ppe2 = airoha_ppe2_is_enabled(eth) &&
 			    hash >= PPE1_SRAM_NUM_ENTRIES;
-		struct airoha_npu *npu;
-		int err = -ENODEV;
 
-		rcu_read_lock();
-		npu = rcu_dereference(eth->npu);
-		if (npu)
-			err = npu->ops.ppe_foe_commit_entry(npu, addr,
-							    sizeof(*hwe), hash,
-							    ppe2);
-		rcu_read_unlock();
-
-		return err;
+		err = npu->ops.ppe_foe_commit_entry(npu, addr, sizeof(*hwe),
+						    hash, ppe2);
 	}
+unlock:
+	rcu_read_unlock();
 
-	return 0;
+	return err;
 }
 
 static void airoha_ppe_foe_remove_flow(struct airoha_ppe *ppe,
@@ -582,6 +658,7 @@ airoha_ppe_foe_commit_subflow_entry(struct airoha_ppe *ppe,
 		l2->common.etype = ETH_P_IPV6;
 
 	hwe.bridge.ib2 = e->data.bridge.ib2;
+	hwe.bridge.data = e->data.bridge.data;
 	airoha_ppe_foe_commit_entry(ppe, &hwe, hash);
 
 	return 0;
@@ -681,6 +758,98 @@ static int airoha_ppe_foe_flow_commit_entry(struct airoha_ppe *ppe,
 	return 0;
 }
 
+static int airoha_ppe_get_entry_idle_time(struct airoha_ppe *ppe, u32 ib1)
+{
+	u32 state = FIELD_GET(AIROHA_FOE_IB1_BIND_STATE, ib1);
+	u32 ts, ts_mask, now = airoha_ppe_get_timestamp(ppe);
+	int idle;
+
+	if (state == AIROHA_FOE_STATE_BIND) {
+		ts = FIELD_GET(AIROHA_FOE_IB1_BIND_TIMESTAMP, ib1);
+		ts_mask = AIROHA_FOE_IB1_BIND_TIMESTAMP;
+	} else {
+		ts = FIELD_GET(AIROHA_FOE_IB1_UNBIND_TIMESTAMP, ib1);
+		now = FIELD_GET(AIROHA_FOE_IB1_UNBIND_TIMESTAMP, now);
+		ts_mask = AIROHA_FOE_IB1_UNBIND_TIMESTAMP;
+	}
+	idle = now - ts;
+
+	return idle < 0 ? idle + ts_mask + 1 : idle;
+}
+
+static void
+airoha_ppe_foe_flow_l2_entry_update(struct airoha_ppe *ppe,
+				    struct airoha_flow_table_entry *e)
+{
+	int min_idle = airoha_ppe_get_entry_idle_time(ppe, e->data.ib1);
+	struct airoha_flow_table_entry *iter;
+	struct hlist_node *n;
+
+	lockdep_assert_held(&ppe_lock);
+
+	hlist_for_each_entry_safe(iter, n, &e->l2_flows, l2_subflow_node) {
+		struct airoha_foe_entry *hwe;
+		u32 ib1, state;
+		int idle;
+
+		hwe = airoha_ppe_foe_get_entry(ppe, iter->hash);
+		ib1 = READ_ONCE(hwe->ib1);
+
+		state = FIELD_GET(AIROHA_FOE_IB1_BIND_STATE, ib1);
+		if (state != AIROHA_FOE_STATE_BIND) {
+			iter->hash = 0xffff;
+			airoha_ppe_foe_remove_flow(ppe, iter);
+			continue;
+		}
+
+		idle = airoha_ppe_get_entry_idle_time(ppe, ib1);
+		if (idle >= min_idle)
+			continue;
+
+		min_idle = idle;
+		e->data.ib1 &= ~AIROHA_FOE_IB1_BIND_TIMESTAMP;
+		e->data.ib1 |= ib1 & AIROHA_FOE_IB1_BIND_TIMESTAMP;
+	}
+}
+
+static void airoha_ppe_foe_flow_entry_update(struct airoha_ppe *ppe,
+					     struct airoha_flow_table_entry *e)
+{
+	struct airoha_foe_entry *hwe_p, hwe = {};
+
+	spin_lock_bh(&ppe_lock);
+
+	if (e->type == FLOW_TYPE_L2) {
+		airoha_ppe_foe_flow_l2_entry_update(ppe, e);
+		goto unlock;
+	}
+
+	if (e->hash == 0xffff)
+		goto unlock;
+
+	hwe_p = airoha_ppe_foe_get_entry(ppe, e->hash);
+	if (!hwe_p)
+		goto unlock;
+
+	memcpy(&hwe, hwe_p, sizeof(*hwe_p));
+	if (!airoha_ppe_foe_compare_entry(e, &hwe)) {
+		e->hash = 0xffff;
+		goto unlock;
+	}
+
+	e->data.ib1 = hwe.ib1;
+unlock:
+	spin_unlock_bh(&ppe_lock);
+}
+
+static int airoha_ppe_entry_idle_time(struct airoha_ppe *ppe,
+				      struct airoha_flow_table_entry *e)
+{
+	airoha_ppe_foe_flow_entry_update(ppe, e);
+
+	return airoha_ppe_get_entry_idle_time(ppe, e->data.ib1);
+}
+
 static int airoha_ppe_flow_offload_replace(struct airoha_gdm_port *port,
 					   struct flow_cls_offload *f)
 {
@@ -896,6 +1065,56 @@ static int airoha_ppe_flow_offload_destroy(struct airoha_gdm_port *port,
 	return 0;
 }
 
+void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash,
+				    struct airoha_foe_stats64 *stats)
+{
+	u32 index = airoha_ppe_foe_get_flow_stats_index(ppe, hash);
+	struct airoha_eth *eth = ppe->eth;
+	struct airoha_npu *npu;
+
+	if (index >= PPE_STATS_NUM_ENTRIES)
+		return;
+
+	rcu_read_lock();
+
+	npu = rcu_dereference(eth->npu);
+	if (npu) {
+		stats->packets = ((u64)ppe->foe_stats[index].packets) << 32 |
+				 npu->stats[index].packets;
+		stats->bytes = ((u64)ppe->foe_stats[index].bytes) << 32 |
+			       npu->stats[index].bytes;
+	}
+
+	rcu_read_unlock();
+}
+
+static int airoha_ppe_flow_offload_stats(struct airoha_gdm_port *port,
+					 struct flow_cls_offload *f)
+{
+	struct airoha_eth *eth = port->qdma->eth;
+	struct airoha_flow_table_entry *e;
+	u32 idle;
+
+	e = rhashtable_lookup(&eth->flow_table, &f->cookie,
+			      airoha_flow_table_params);
+	if (!e)
+		return -ENOENT;
+
+	idle = airoha_ppe_entry_idle_time(eth->ppe, e);
+	f->stats.lastused = jiffies - idle * HZ;
+
+	if (e->hash != 0xffff) {
+		struct airoha_foe_stats64 stats = {};
+
+		airoha_ppe_foe_entry_get_stats(eth->ppe, e->hash, &stats);
+		f->stats.pkts += (stats.packets - e->stats.packets);
+		f->stats.bytes += (stats.bytes - e->stats.bytes);
+		e->stats = stats;
+	}
+
+	return 0;
+}
+
 static int airoha_ppe_flow_offload_cmd(struct airoha_gdm_port *port,
 				       struct flow_cls_offload *f)
 {
@@ -904,6 +1123,8 @@ static int airoha_ppe_flow_offload_cmd(struct airoha_gdm_port *port,
 		return airoha_ppe_flow_offload_replace(port, f);
 	case FLOW_CLS_DESTROY:
 		return airoha_ppe_flow_offload_destroy(port, f);
+	case FLOW_CLS_STATS:
+		return airoha_ppe_flow_offload_stats(port, f);
 	default:
 		break;
 	}
@@ -929,11 +1150,12 @@ static int airoha_ppe_flush_sram_entries(struct airoha_ppe *ppe,
 
 static struct airoha_npu *airoha_ppe_npu_get(struct airoha_eth *eth)
 {
-	struct airoha_npu *npu = airoha_npu_get(eth->dev);
+	struct airoha_npu *npu = airoha_npu_get(eth->dev,
+						&eth->ppe->foe_stats_dma);
 
 	if (IS_ERR(npu)) {
 		request_module("airoha-npu");
-		npu = airoha_npu_get(eth->dev);
+		npu = airoha_npu_get(eth->dev, &eth->ppe->foe_stats_dma);
 	}
 
 	return npu;
@@ -956,6 +1178,8 @@ static int airoha_ppe_offload_setup(struct airoha_eth *eth)
 	if (err)
 		goto error_npu_put;
 
+	airoha_ppe_foe_flow_stats_reset(eth->ppe, npu);
+
 	rcu_assign_pointer(eth->npu, npu);
 	synchronize_rcu();
 
@@ -1027,6 +1251,15 @@ int airoha_ppe_init(struct airoha_eth *eth)
 	if (!ppe->foe_flow)
 		return -ENOMEM;
 
+	foe_size = PPE_STATS_NUM_ENTRIES * sizeof(*ppe->foe_stats);
+	if (foe_size) {
+		ppe->foe_stats = dmam_alloc_coherent(eth->dev, foe_size,
+						     &ppe->foe_stats_dma,
+						     GFP_KERNEL);
+		if (!ppe->foe_stats)
+			return -ENOMEM;
+	}
+
 	err = rhashtable_init(&eth->flow_table, &airoha_flow_table_params);
 	if (err)
 		return err;
diff --git a/drivers/net/ethernet/airoha/airoha_ppe_debugfs.c b/drivers/net/ethernet/airoha/airoha_ppe_debugfs.c
index 3cdc6fd53fc751235d65c277a35c69ab6935ceec..05a756233f6a44fa51d1c57dd39d89c8ea488054 100644
--- a/drivers/net/ethernet/airoha/airoha_ppe_debugfs.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe_debugfs.c
@@ -61,6 +61,7 @@ static int airoha_ppe_debugfs_foe_show(struct seq_file *m, void *private,
 		u16 *src_port = NULL, *dest_port = NULL;
 		struct airoha_foe_mac_info_common *l2;
 		unsigned char h_source[ETH_ALEN] = {};
+		struct airoha_foe_stats64 stats = {};
 		unsigned char h_dest[ETH_ALEN];
 		struct airoha_foe_entry *hwe;
 		u32 type, state, ib2, data;
@@ -144,14 +145,18 @@ static int airoha_ppe_debugfs_foe_show(struct seq_file *m, void *private,
 				cpu_to_be16(hwe->ipv4.l2.src_mac_lo);
 		}
 
+		airoha_ppe_foe_entry_get_stats(ppe, i, &stats);
+
 		*((__be32 *)h_dest) = cpu_to_be32(l2->dest_mac_hi);
 		*((__be16 *)&h_dest[4]) = cpu_to_be16(l2->dest_mac_lo);
 		*((__be32 *)h_source) = cpu_to_be32(l2->src_mac_hi);
 
 		seq_printf(m, " eth=%pM->%pM etype=%04x data=%08x"
-			      " vlan=%d,%d ib1=%08x ib2=%08x\n",
+			      " vlan=%d,%d ib1=%08x ib2=%08x"
+			      " packets=%llu bytes=%llu\n",
 			   h_source, h_dest, l2->etype, data,
-			   l2->vlan1, l2->vlan2, hwe->ib1, ib2);
+			   l2->vlan1, l2->vlan2, hwe->ib1, ib2,
+			   stats.packets, stats.bytes);
 	}
 
 	return 0;

-- 
2.49.0



From treapking at chromium.org  Wed May 14 12:49:02 2025
From: treapking at chromium.org (Pin-yen Lin)
Date: Wed, 14 May 2025 15:49:02 -0400
Subject: [PATCH] thermal/drivers/mediatek/lvts_thermal: Remove redundant
 code in lvts_ctrl_configure
In-Reply-To: <77c4437f2643475de495733d7840421198b78f49.camel@mediatek.com>
References: <20240410000730.628043-1-treapking@chromium.org>
 <9c5aa4fb-a83c-470e-acf8-dd31303e50c2@collabora.com> <77c4437f2643475de495733d7840421198b78f49.camel@mediatek.com>
Message-ID: <CAEXTbpdNxFd7-RMXyvYraqC5cj_BgycAO6JWdNUo50DVn+yntw@mail.gmail.com>

Hi Chang-Yi,

On Wed, Apr 30, 2025 at 4:26?AM Chang-Yi Lin (???)
<ds_chang-yi.lin at mediatek.com> wrote:
>
> On Wed, 2024-04-10 at 11:55 +0200, AngeloGioacchino Del Regno wrote:
> > Il 10/04/24 02:07, Pin-yen Lin ha scritto:
> > > The removed variable assignment is never written to the register,
> > > so it
> > > has no effect on the device behavior.  Mediatek has confirmed that
> > > it
> > > is not required to initialize this register for current platforms,
> > > so
> > > remove this segment to avoid confusion.
> > >
> > > Signed-off-by: Pin-yen Lin <treapking at chromium.org>
> > >
> >
> > Added Nicolas Pitre to the loop;
> >
> > Nicolas, since you're pushing support for those, can you please check
> > if CALSCALE
> > is used/useful/necessary on MT8186/88 before I give a R-b to this
> > commit?
> >
> > P.S.: Can anyone from MediaTek please confirm if the 0x300 value is
> > right for this
> >        register? I'd still like Linux to properly initialize the
> > registers, even if
> >        this could technically be a default value.
> >
> >
> > > ---
> > >
> > >   drivers/thermal/mediatek/lvts_thermal.c | 6 ------
> > >   1 file changed, 6 deletions(-)
> > >
> > > diff --git a/drivers/thermal/mediatek/lvts_thermal.c
> > > b/drivers/thermal/mediatek/lvts_thermal.c
> > > index fd4bd650c77a..48d2f8ba3f18 100644
> > > --- a/drivers/thermal/mediatek/lvts_thermal.c
> > > +++ b/drivers/thermal/mediatek/lvts_thermal.c
> > > @@ -985,12 +985,6 @@ static int lvts_ctrl_configure(struct device
> > > *dev, struct lvts_ctrl *lvts_ctrl)
> > >   value = LVTS_TSSEL_CONF;
> > >   writel(value, LVTS_TSSEL(lvts_ctrl->base));
> > >
> > > -/*
> > > - * LVTS_CALSCALE : ADC voltage round
> > > - */
> > > -value = 0x300;
> > > -value = LVTS_CALSCALE_CONF;
> >
> > As a side note, I believe that the original author wanted to write,
> > instead...
> >
> > value = LVTS_CALSCALE_CONF;
> > writel(value, LVTS_CALSCALE(lvts_ctrl->base);
> >
> > Cheers,
> > Angelo
> >
> > > -
> > >   /*
> > >    * LVTS_MSRCTL0 : Sensor filtering strategy
> > >    *
> >
> >
> Base on xiaojun.zheng
>      The register is for PTP function, and in MT8192 it's not required
> to do such setting any more

This driver is now also used by mt7988, mt8188, and mt8195. Could you
confirm if the PTP function are not required for all these SoCs, so we
are safe to remove this?

As a side note, Mediatek explained PTP in an offline discussion with us:
PTPOD stands for PTP (Performance Thermal Power) OD (Overdrive).
PTPOD is a technique to let the HW runs at the same frequency but with
lower operating voltage to save power.

Regards,
Pin-yen
>
>
> ************* MEDIATEK Confidentiality Notice
>  ********************
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> attachments) may be confidential, proprietary, privileged, or otherwise
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>
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> disclose the content of this e-mail to any other person. Thank you!


From robh at kernel.org  Wed May 14 13:08:16 2025
From: robh at kernel.org (Rob Herring)
Date: Wed, 14 May 2025 15:08:16 -0500
Subject: [PATCH net-next v2 1/2] dt-bindings: net: airoha: Add EN7581
 memory-region property
In-Reply-To: <20250509-airopha-desc-sram-v2-1-9dc3d8076dfb@kernel.org>
References: <20250509-airopha-desc-sram-v2-0-9dc3d8076dfb@kernel.org>
 <20250509-airopha-desc-sram-v2-1-9dc3d8076dfb@kernel.org>
Message-ID: <20250514200816.GA2934563-robh@kernel.org>

On Fri, May 09, 2025 at 04:51:33PM +0200, Lorenzo Bianconi wrote:
> Introduce the memory-region and memory-region-names properties for the
> ethernet node available on EN7581 SoC. In order to improve performances,
> EN7581 SoC supports allocating buffers for hw forwarding queues in SRAM
> instead of DRAM if available on the system.

But 'reserved-memory' is generally for system memory which is DRAM 
though we unfortunately don't enforce that. For small onchip SRAM, you 
should be using the mmio-sram binding and the 'sram' property.

> 
> Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
> ---
>  .../devicetree/bindings/net/airoha,en7581-eth.yaml          | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
> index 0fdd1126541774acacc783d98e4c089b2d2b85e2..6d22131ac2f9e28390b9e785ce33e8d983eafd0f 100644
> --- a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
> +++ b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
> @@ -57,6 +57,16 @@ properties:
>        - const: hsi-mac
>        - const: xfp-mac
>  
> +  memory-region:
> +    items:
> +      - description: QDMA0 buffer memory
> +      - description: QDMA1 buffer memory
> +
> +  memory-region-names:
> +    items:
> +      - const: qdma0-buf
> +      - const: qdma1-buf
> +
>    "#address-cells":
>      const: 1
>  
> @@ -140,6 +150,9 @@ examples:
>                       <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
>                       <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
>  
> +        memory-region = <&qdma0_buf>, <&qdma1_buf>;
> +        memory-region-names = "qdma0-buf", "qdma1-buf";
> +
>          airoha,npu = <&npu>;
>  
>          #address-cells = <1>;
> 
> -- 
> 2.49.0
> 


From bvanassche at acm.org  Wed May 14 14:04:56 2025
From: bvanassche at acm.org (Bart Van Assche)
Date: Wed, 14 May 2025 14:04:56 -0700
Subject: [PATCH v2] ufs: core: Add HID support
In-Reply-To: <20250512131519.138-1-tanghuan@vivo.com>
References: <20250512131519.138-1-tanghuan@vivo.com>
Message-ID: <88718b2f-0583-4444-8bf0-7ecf9a45329c@acm.org>

On 5/12/25 6:15 AM, Huan Tang wrote:
> +What:		/sys/bus/platform/drivers/ufshcd/*/ufs_hid/hid_analysis_trigger
> +What:		/sys/bus/platform/devices/*.ufs/ufs_hid/hid_analysis_trigger
> +Date:		April 2025
> +Contact:	Huan Tang <tanghuan at vivo.com>
> +Description:
> +		The host can enable or disable HID analysis operation.
> +
> +		=======  =========================================
> +		disable   disable HID analysis operation
> +		enable    enable HID analysis operation
> +		=======  =========================================
> +
> +		The file is write only.

All HID sysfs attributes occur in the "ufs_hid" directory and have a
"hid_" prefix. That's two times "hid". Please remove the "hid_" prefix
from the sysfs attribute names since it is redundant.

> +static struct attribute *ufs_sysfs_ufs_hid[] = {
> +	&dev_attr_hid_analysis_trigger.attr,
> +	&dev_attr_hid_defrag_trigger.attr,
> +	&dev_attr_hid_fragmented_size.attr,
> +	&dev_attr_hid_defrag_size.attr,
> +	&dev_attr_hid_progress_ratio.attr,
> +	&dev_attr_hid_state.attr,
> +	NULL,
> +};
> +
> +static const struct attribute_group ufs_sysfs_ufs_hid_group = {
> +	.name = "ufs_hid",
> +	.attrs = ufs_sysfs_ufs_hid,
> +};

Isn't the prefix "ufs_" in "ufs_hid" redundant since this sysfs group
occurs under a UFS host controller directory?

Regarding the name of this sysfs group, "ufs" occurs twice in that
name (ufs_sysfs_ufs_hid_group). Please make sure that "ufs" only occurs
once in that sysfs group name.

>   #define UFS_LUN_DESC_PARAM(_pname, _puname, _duname, _size)		\
>   static ssize_t _pname##_show(struct device *dev,			\
>   	struct device_attribute *attr, char *buf)			\
> @@ -1898,6 +2079,7 @@ const struct attribute_group ufs_sysfs_lun_attributes_group = {
>   
>   void ufs_sysfs_add_nodes(struct device *dev)
>   {
> +	struct ufs_hba *hba = dev_get_drvdata(dev);
>   	int ret;
>   
>   	ret = sysfs_create_groups(&dev->kobj, ufs_sysfs_groups);
> @@ -1905,9 +2087,22 @@ void ufs_sysfs_add_nodes(struct device *dev)
>   		dev_err(dev,
>   			"%s: sysfs groups creation failed (err = %d)\n",
>   			__func__, ret);
> +
> +	if (hba->dev_info.hid_sup) {
> +		ret = sysfs_create_group(&dev->kobj, &ufs_sysfs_ufs_hid_group);
> +		if (ret)
> +			dev_err(dev,
> +				"%s: sysfs ufs_hid group creation failed (err = %d)\n",
> +				__func__, ret);
> +	}
>   }

Please merge ufs_sysfs_ufs_hid_group into ufs_sysfs_groups, remove the
new sysfs_create_group() call and add a visibility callback in
ufs_sysfs_ufs_hid_group that only makes the attributes in this group
visible if hba->dev_info.hid_sup == true.

Otherwise this patch looks good to me.

Thanks,

Bart.


From robh at kernel.org  Wed May 14 14:16:58 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Wed, 14 May 2025 16:16:58 -0500
Subject: [PATCH v1 02/14] dt-bindings: net: dsa: mediatek,mt7530: add
 dsa-port definition for mt7988
In-Reply-To: <20250511141942.10284-3-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
 <20250511141942.10284-3-linux@fw-web.de>
Message-ID: <174725741810.3051350.2895104132991545164.robh@kernel.org>


On Sun, 11 May 2025 16:19:18 +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w at public-files.de>
> 
> Add own dsa-port binding for SoC with internal switch where only phy-mode
> 'internal' is valid.
> 
> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> ---
>  .../bindings/net/dsa/mediatek,mt7530.yaml          | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
> 

Reviewed-by: Rob Herring (Arm) <robh at kernel.org>



From robh at kernel.org  Wed May 14 14:18:10 2025
From: robh at kernel.org (Rob Herring)
Date: Wed, 14 May 2025 16:18:10 -0500
Subject: [PATCH v1 03/14] dt-bindings: net: dsa: mediatek,mt7530: add
 internal mdio bus
In-Reply-To: <20250511141942.10284-4-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
 <20250511141942.10284-4-linux@fw-web.de>
Message-ID: <20250514211810.GA3051536-robh@kernel.org>

On Sun, May 11, 2025 at 04:19:19PM +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w at public-files.de>
> 
> Mt7988 buildin switch has own mdio bus where ge-phys are connected.
> Add related property for this.
> 
> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> ---
>  Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
> index bb22c36749fc..5f1363278f43 100644
> --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
> +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
> @@ -156,6 +156,9 @@ properties:
>      maxItems: 1
>  
>  patternProperties:
> +  "^mdio(-bus)?$":

Really need 2 names?

> +    $ref: /schemas/net/mdio.yaml#

       unevaluatedProperties: false

> +
>    "^(ethernet-)?ports$":
>      type: object
>      additionalProperties: true
> -- 
> 2.43.0
> 


From robh at kernel.org  Wed May 14 14:32:47 2025
From: robh at kernel.org (Rob Herring)
Date: Wed, 14 May 2025 16:32:47 -0500
Subject: [net-next PATCH v4 07/11] dt-bindings: net: ethernet-controller:
 permit to define multiple PCS
In-Reply-To: <20250511201250.3789083-8-ansuelsmth@gmail.com>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-8-ansuelsmth@gmail.com>
Message-ID: <20250514213247.GA3053278-robh@kernel.org>

On Sun, May 11, 2025 at 10:12:33PM +0200, Christian Marangi wrote:
> Drop the limitation of a single PCS in pcs-handle property. Multiple PCS
> can be defined for an ethrnet-controller node to support various PHY

typo

> interface mode type.
> 
> It's very common for SoCs to have a 2 or more dedicated PCS for Base-X
> (for example SGMII, 1000base-x, 2500base-x, ...) and Base-R (for example
> USXGMII,10base-r, ...) with the MAC selecting one of the other based on
> the attached PHY.

I'm confused what you need. The restriction was no arg cells allowed. 
Any number of phandles was allowed. The former would need a 
"#pcs-handle-cells" type property.

> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---
>  Documentation/devicetree/bindings/net/ethernet-controller.yaml | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
> index 7cbf11bbe99c..60605b34d242 100644
> --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
> +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
> @@ -84,8 +84,6 @@ properties:
>  
>    pcs-handle:
>      $ref: /schemas/types.yaml#/definitions/phandle-array
> -    items:
> -      maxItems: 1
>      description:
>        Specifies a reference to a node representing a PCS PHY device on a MDIO
>        bus to link with an external PHY (phy-handle) if exists.
> -- 
> 2.48.1
> 


From chunkuang.hu at kernel.org  Wed May 14 16:36:47 2025
From: chunkuang.hu at kernel.org (Chun-Kuang Hu)
Date: Wed, 14 May 2025 23:36:47 +0000
Subject: [GIT PULL] mediatek drm next - 20250515
Message-ID: <20250514233647.15907-1-chunkuang.hu@kernel.org>

Hi, Dave & Daniel:

This includes:
1. Prepare for support MT8195/88 HDMIv2 and DDCv2
2. DPI: Cleanups and add support for more formats
3. Cleanups and sanitization
4. Replace custom compare_dev with component_compare_of

Regards,
Chun-Kuang.

The following changes since commit 0af2f6be1b4281385b618cb86ad946eded089ac8:

  Linux 6.15-rc1 (2025-04-06 13:11:33 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git tags/mediatek-drm-next-20250515

for you to fetch changes up to 07c39476a75bf2541dbdb37815b60cc134cf9aff:

  drm/mediatek: Replace custom compare_dev with component_compare_of (2025-05-14 23:12:24 +0000)

----------------------------------------------------------------
Mediatek DRM Next - 20250515

1. Prepare for support MT8195/88 HDMIv2 and DDCv2
2. DPI: Cleanups and add support for more formats
3. Cleanups and sanitization
4. Replace custom compare_dev with component_compare_of

----------------------------------------------------------------
AngeloGioacchino Del Regno (20):
      dt-bindings: display: mediatek: Add binding for HDMIv2 DDC
      dt-bindings: display: mediatek: Add binding for MT8195 HDMI-TX v2
      drm/mediatek: mtk_cec: Switch to register as module_platform_driver
      drm/mediatek: mtk_hdmi_ddc: Switch to register as module_platform_driver
      drm/mediatek: mtk_hdmi: Convert to module_platform_driver macro
      drm/mediatek: mtk_hdmi: Disgregate function mtk_hdmi_audio_set_param()
      drm/mediatek: mtk_hdmi: Move audio params selection to new function
      drm/mediatek: mtk_hdmi: Move plugged_cb/codec_dev setting to new function
      drm/mediatek: mtk_hdmi: Move N/CTS setting to new function
      drm/mediatek: mtk_hdmi: Use dev_err_probe() in mtk_hdmi_dt_parse_pdata()
      drm/mediatek: mtk_hdmi: Move CEC device parsing in new function
      drm/mediatek: mtk_hdmi: Move output init to mtk_hdmi_register_audio_driver()
      drm/mediatek: mtk_dpi: Use switch in mtk_dpi_config_color_format()
      drm/mediatek: mtk_dpi: Add local helpers for bus format parameters
      drm/mediatek: mtk_dpi: Add support for additional output formats
      drm/mediatek: mtk_dpi: Allow additional output formats on MT8195/88
      drm/mediatek: mtk_dpi: Rename output fmts array for MT8195 DP_INTF
      drm/mediatek: mtk_drm_drv: Fix kobject put for mtk_mutex device ptr
      drm/mediatek: Fix kobject put for component sub-drivers
      drm/mediatek: mtk_drm_drv: Unbind secondary mmsys components on err

Guillaume Ranquet (1):
      drm/mediatek: hdmi: Use regmap instead of iomem for main registers

Krzysztof Kozlowski (1):
      drm/mediatek/hdmi: Use syscon_regmap_lookup_by_phandle_args

Tang Dongxing (1):
      drm/mediatek: Replace custom compare_dev with component_compare_of

 .../display/mediatek/mediatek,mt8195-hdmi-ddc.yaml |  41 +++
 .../display/mediatek/mediatek,mt8195-hdmi.yaml     | 151 ++++++++
 drivers/gpu/drm/mediatek/Makefile                  |   8 +-
 drivers/gpu/drm/mediatek/mtk_cec.c                 |   7 +-
 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c    |   7 +-
 drivers/gpu/drm/mediatek/mtk_dpi.c                 | 117 +++++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c             |  31 +-
 drivers/gpu/drm/mediatek/mtk_hdmi.c                | 410 +++++++++------------
 drivers/gpu/drm/mediatek/mtk_hdmi.h                |  14 -
 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c            |   2 +-
 10 files changed, 497 insertions(+), 291 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
 delete mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.h


From kuba at kernel.org  Wed May 14 19:09:17 2025
From: kuba at kernel.org (Jakub Kicinski)
Date: Wed, 14 May 2025 19:09:17 -0700
Subject: [PATCH net] net: airoha: Fix page recycling in
 airoha_qdma_rx_process()
In-Reply-To: <20250513-airoha-fix-rx-process-error-condition-v1-1-e5d70cd7c066@kernel.org>
References: <20250513-airoha-fix-rx-process-error-condition-v1-1-e5d70cd7c066@kernel.org>
Message-ID: <20250514190917.4b0ff404@kernel.org>

On Tue, 13 May 2025 18:34:44 +0200 Lorenzo Bianconi wrote:
> Do not recycle the page twice in airoha_qdma_rx_process routine in case
> of error. Just run dev_kfree_skb() if the skb has been allocated and marked
> for recycling. Run page_pool_put_full_page() directly if the skb has not
> been allocated yet.
> Moreover, rely on DMA address from queue entry element instead of reading
> it from the DMA descriptor for DMA syncing in airoha_qdma_rx_process().
> 
> Fixes: e12182ddb6e71 ("net: airoha: Enable Rx Scatter-Gather")

Missed your sign-off.
-- 
pw-bot: cr


From patchwork-bot+netdevbpf at kernel.org  Wed May 14 19:40:39 2025
From: patchwork-bot+netdevbpf at kernel.org (patchwork-bot+netdevbpf at kernel.org)
Date: Thu, 15 May 2025 02:40:39 +0000
Subject: [PATCH net] net: ethernet: mtk_eth_soc: fix typo for declaration
 MT7988 ESW capability
In-Reply-To: <b8b37f409d1280fad9c4d32521e6207f63cd3213.1747110258.git.daniel@makrotopia.org>
References: <b8b37f409d1280fad9c4d32521e6207f63cd3213.1747110258.git.daniel@makrotopia.org>
Message-ID: <174727683900.2587108.2642829871364981642.git-patchwork-notify@kernel.org>

Hello:

This patch was applied to netdev/net.git (main)
by Jakub Kicinski <kuba at kernel.org>:

On Tue, 13 May 2025 05:27:30 +0100 you wrote:
> From: Bo-Cun Chen <bc-bocun.chen at mediatek.com>
> 
> Since MTK_ESW_BIT is a bit number rather than a bitmap, it causes
> MTK_HAS_CAPS to produce incorrect results. This leads to the ETH
> driver not declaring MAC capabilities correctly for the MT7988 ESW.
> 
> Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC")
> Signed-off-by: Bo-Cun Chen <bc-bocun.chen at mediatek.com>
> Signed-off-by: Daniel Golle <daniel at makrotopia.org>
> 
> [...]

Here is the summary with links:
  - [net] net: ethernet: mtk_eth_soc: fix typo for declaration MT7988 ESW capability
    https://git.kernel.org/netdev/net/c/1bdea6fad6fb

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html




From jinjian.song at fibocom.com  Wed May 14 20:17:42 2025
From: jinjian.song at fibocom.com (Jinjian Song)
Date: Thu, 15 May 2025 11:17:42 +0800
Subject: [net v1] net: wwan: t7xx: Fix napi rx poll issue
Message-ID: <20250515031743.246178-1-jinjian.song@fibocom.com>

When driver handles the napi rx polling requests, the netdev might
have been released by the dellink logic triggered by the disconnect
operation on user plane. However, in the logic of processing skb in
polling, an invalid netdev is still being used, which causes a panic.

BUG: kernel NULL pointer dereference, address: 00000000000000f1
Oops: 0000 [#1] PREEMPT SMP NOPTI
RIP: 0010:dev_gro_receive+0x3a/0x620
[...]
Call Trace:
 <IRQ>
 ? __die_body+0x68/0xb0
 ? page_fault_oops+0x379/0x3e0
 ? exc_page_fault+0x4f/0xa0
 ? asm_exc_page_fault+0x22/0x30
 ? __pfx_t7xx_ccmni_recv_skb+0x10/0x10 [mtk_t7xx (HASH:1400 7)]
 ? dev_gro_receive+0x3a/0x620
 napi_gro_receive+0xad/0x170
 t7xx_ccmni_recv_skb+0x48/0x70 [mtk_t7xx (HASH:1400 7)]
 t7xx_dpmaif_napi_rx_poll+0x590/0x800 [mtk_t7xx (HASH:1400 7)]
 net_rx_action+0x103/0x470
 irq_exit_rcu+0x13a/0x310
 sysvec_apic_timer_interrupt+0x56/0x90
 </IRQ>

Fixes: 5545b7b9f294 ("net: wwan: t7xx: Add NAPI support")
Signed-off-by: Jinjian Song <jinjian.song at fibocom.com>
---
 drivers/net/wwan/t7xx/t7xx_netdev.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/wwan/t7xx/t7xx_netdev.c b/drivers/net/wwan/t7xx/t7xx_netdev.c
index 91fa082e9cab..2116ff81728b 100644
--- a/drivers/net/wwan/t7xx/t7xx_netdev.c
+++ b/drivers/net/wwan/t7xx/t7xx_netdev.c
@@ -324,6 +324,7 @@ static void t7xx_ccmni_wwan_dellink(void *ctxt, struct net_device *dev, struct l
 	if (WARN_ON(ctlb->ccmni_inst[if_id] != ccmni))
 		return;
 
+	ctlb->ccmni_inst[if_id] = NULL;
 	unregister_netdevice(dev);
 }
 
-- 
2.34.1



From shayne.chen at mediatek.com  Wed May 14 20:29:44 2025
From: shayne.chen at mediatek.com (Shayne Chen)
Date: Thu, 15 May 2025 11:29:44 +0800
Subject: [PATCH mt76-next 1/9] wifi: mt76: remove capability of partial bandwidth UL MU-MIMO
Message-ID: <20250515032952.1653494-1-shayne.chen@mediatek.com>

From: Howard Hsu <howard-yh.hsu at mediatek.com>

The firmware only supports full bandwidth UL MU-MIMO, so remove the
partial bandwidth capability from HE PHY CAP.

Signed-off-by: Howard Hsu <howard-yh.hsu at mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen at mediatek.com>
---
 drivers/net/wireless/mediatek/mt76/mt7915/init.c | 3 +--
 drivers/net/wireless/mediatek/mt76/mt7996/init.c | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/init.c b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
index 57d5be94624b..be9527dd0269 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
@@ -925,8 +925,7 @@ mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy,
 
 	c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US;
 	if (!is_mt7915(&dev->mt76))
-		c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO |
-		     IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO;
+		c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO;
 	elem->phy_cap_info[2] |= c;
 
 	c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/init.c b/drivers/net/wireless/mediatek/mt76/mt7996/init.c
index ff835a6f77ce..b77fa94df8c7 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/init.c
@@ -1116,8 +1116,7 @@ mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy,
 	elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
 
 	c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
-	    IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO |
-	    IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO;
+	    IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO;
 	elem->phy_cap_info[2] |= c;
 
 	c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE;
-- 
2.39.2



From shayne.chen at mediatek.com  Wed May 14 20:29:45 2025
From: shayne.chen at mediatek.com (Shayne Chen)
Date: Thu, 15 May 2025 11:29:45 +0800
Subject: [PATCH mt76-next 2/9] wifi: mt76: mt7996: fix beamformee SS field
In-Reply-To: <20250515032952.1653494-1-shayne.chen@mediatek.com>
References: <20250515032952.1653494-1-shayne.chen@mediatek.com>
Message-ID: <20250515032952.1653494-2-shayne.chen@mediatek.com>

From: Howard Hsu <howard-yh.hsu at mediatek.com>

Fix the beamformee SS field for the mt7996, mt7992 and mt7990 chipsets.
For the mt7992, this value shall be set to 0x4, while the others shall
be set to 0x3.

Fixes: 5b20557593d4 ("wifi: mt76: connac: adjust phy capabilities based on band constraints")
Signed-off-by: Howard Hsu <howard-yh.hsu at mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen at mediatek.com>
---
 drivers/net/wireless/mediatek/mt76/mt7996/init.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/init.c b/drivers/net/wireless/mediatek/mt76/mt7996/init.c
index b77fa94df8c7..5c545293f294 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/init.c
@@ -1121,12 +1121,12 @@ mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy,
 
 	c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE;
 
-	if (is_mt7996(phy->mt76->dev))
-		c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 |
-		     (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4 * non_2g);
-	else
+	if (is_mt7992(phy->mt76->dev))
 		c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_5 |
 		     (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_5 * non_2g);
+	else
+		c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 |
+		     (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4 * non_2g);
 
 	elem->phy_cap_info[4] |= c;
 
-- 
2.39.2



From shayne.chen at mediatek.com  Wed May 14 20:29:48 2025
From: shayne.chen at mediatek.com (Shayne Chen)
Date: Thu, 15 May 2025 11:29:48 +0800
Subject: [PATCH mt76-next 5/9] wifi: mt76: mt7996: fix invalid NSS setting when TX path differs from NSS
In-Reply-To: <20250515032952.1653494-1-shayne.chen@mediatek.com>
References: <20250515032952.1653494-1-shayne.chen@mediatek.com>
Message-ID: <20250515032952.1653494-5-shayne.chen@mediatek.com>

From: Peter Chiu <chui-hao.chiu at mediatek.com>

The maximum TX path and NSS may differ on a band. For example, one variant
of the MT7992 has 5 TX paths and 4 NSS on the 5 GHz band. To address this,
add orig_antenna_mask to record the maximum NSS and prevent setting an
invalid NSS in mt7996_set_antenna().

Fixes: 69d54ce7491d ("wifi: mt76: mt7996: switch to single multi-radio wiphy")
Signed-off-by: Peter Chiu <chui-hao.chiu at mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen at mediatek.com>
---
 drivers/net/wireless/mediatek/mt76/mt7996/eeprom.c | 1 +
 drivers/net/wireless/mediatek/mt76/mt7996/main.c   | 3 ++-
 drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h | 1 +
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/eeprom.c b/drivers/net/wireless/mediatek/mt76/mt7996/eeprom.c
index 7bfd19ed9594..87c6192b6384 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/eeprom.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/eeprom.c
@@ -310,6 +310,7 @@ int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy)
 		phy->has_aux_rx = true;
 
 	mphy->antenna_mask = BIT(nss) - 1;
+	phy->orig_antenna_mask = mphy->antenna_mask;
 	mphy->chainmask = (BIT(path) - 1) << dev->chainshift[band_idx];
 	phy->orig_chainmask = mphy->chainmask;
 	dev->chainmask |= mphy->chainmask;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/main.c b/drivers/net/wireless/mediatek/mt76/mt7996/main.c
index 91c64e3a0860..85c5d76c0c2c 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/main.c
@@ -1518,7 +1518,8 @@ mt7996_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
 		u8 shift = dev->chainshift[band_idx];
 
 		phy->mt76->chainmask = tx_ant & phy->orig_chainmask;
-		phy->mt76->antenna_mask = phy->mt76->chainmask >> shift;
+		phy->mt76->antenna_mask = (phy->mt76->chainmask >> shift) &
+					  phy->orig_antenna_mask;
 
 		mt76_set_stream_caps(phy->mt76, true);
 		mt7996_set_stream_vht_txbf_caps(phy);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h b/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
index 7c334e319547..c75189a02316 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
@@ -312,6 +312,7 @@ struct mt7996_phy {
 	struct mt76_channel_state state_ts;
 
 	u16 orig_chainmask;
+	u16 orig_antenna_mask;
 
 	bool has_aux_rx;
 	bool counter_reset;
-- 
2.39.2



From shayne.chen at mediatek.com  Wed May 14 20:29:52 2025
From: shayne.chen at mediatek.com (Shayne Chen)
Date: Thu, 15 May 2025 11:29:52 +0800
Subject: [PATCH mt76-next 9/9] wifi: mt76: support power delta calculation for 5 TX paths
In-Reply-To: <20250515032952.1653494-1-shayne.chen@mediatek.com>
References: <20250515032952.1653494-1-shayne.chen@mediatek.com>
Message-ID: <20250515032952.1653494-9-shayne.chen@mediatek.com>

One variant of MT7992 has 5 TX paths, so extend the power delta function
to support it. Also, rename nss_delta to path_delta since the value is
based on the number of TX paths rather tha the number of spatial streams.
(path delta [0.5 dBm] = 10 * log(path number) [dBm] * 2)

Co-developed-by: StanleyYP Wang <StanleyYP.Wang at mediatek.com>
Signed-off-by: StanleyYP Wang <StanleyYP.Wang at mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen at mediatek.com>
---
 drivers/net/wireless/mediatek/mt76/mac80211.c    | 4 ++--
 drivers/net/wireless/mediatek/mt76/mt76.h        | 8 ++++----
 drivers/net/wireless/mediatek/mt76/mt7615/init.c | 2 +-
 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c  | 6 +++---
 drivers/net/wireless/mediatek/mt76/mt7915/init.c | 4 ++--
 drivers/net/wireless/mediatek/mt76/mt7996/init.c | 6 +++---
 drivers/net/wireless/mediatek/mt76/mt7996/main.c | 2 +-
 7 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mac80211.c b/drivers/net/wireless/mediatek/mt76/mac80211.c
index e9605dc22291..45c8db939d55 100644
--- a/drivers/net/wireless/mediatek/mt76/mac80211.c
+++ b/drivers/net/wireless/mediatek/mt76/mac80211.c
@@ -1705,7 +1705,7 @@ s8 mt76_get_power_bound(struct mt76_phy *phy, s8 txpower)
 	int n_chains = hweight16(phy->chainmask);
 
 	txpower = mt76_get_sar_power(phy, phy->chandef.chan, txpower * 2);
-	txpower -= mt76_tx_power_nss_delta(n_chains);
+	txpower -= mt76_tx_power_path_delta(n_chains);
 
 	return txpower;
 }
@@ -1721,7 +1721,7 @@ int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 		return -EINVAL;
 
 	n_chains = hweight16(phy->chainmask);
-	delta = mt76_tx_power_nss_delta(n_chains);
+	delta = mt76_tx_power_path_delta(n_chains);
 	*dbm = DIV_ROUND_UP(phy->txpower_cur + delta, 2);
 
 	return 0;
diff --git a/drivers/net/wireless/mediatek/mt76/mt76.h b/drivers/net/wireless/mediatek/mt76/mt76.h
index d7cd467b812f..7707c51b974e 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76.h
@@ -1386,12 +1386,12 @@ static inline bool mt76_is_skb_pktid(u8 pktid)
 	return pktid >= MT_PACKET_ID_FIRST;
 }
 
-static inline u8 mt76_tx_power_nss_delta(u8 nss)
+static inline u8 mt76_tx_power_path_delta(u8 path)
 {
-	static const u8 nss_delta[4] = { 0, 6, 9, 12 };
-	u8 idx = nss - 1;
+	static const u8 path_delta[5] = { 0, 6, 9, 12, 14 };
+	u8 idx = path - 1;
 
-	return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0;
+	return (idx < ARRAY_SIZE(path_delta)) ? path_delta[idx] : 0;
 }
 
 static inline bool mt76_testmode_enabled(struct mt76_phy *phy)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/init.c b/drivers/net/wireless/mediatek/mt76/mt7615/init.c
index 66ba3be27343..aae80005a3c1 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7615/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7615/init.c
@@ -273,7 +273,7 @@ void mt7615_init_txpower(struct mt7615_dev *dev,
 			 struct ieee80211_supported_band *sband)
 {
 	int i, n_chains = hweight8(dev->mphy.antenna_mask), target_chains;
-	int delta_idx, delta = mt76_tx_power_nss_delta(n_chains);
+	int delta_idx, delta = mt76_tx_power_path_delta(n_chains);
 	u8 *eep = (u8 *)dev->mt76.eeprom.data;
 	enum nl80211_band band = sband->band;
 	struct mt76_power_limits limits;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7615/mcu.c
index b8fcd4eb3fbb..4064e193d4de 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7615/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7615/mcu.c
@@ -2067,7 +2067,7 @@ static void mt7615_mcu_set_txpower_sku(struct mt7615_phy *phy, u8 *sku)
 	};
 
 	tx_power = mt76_get_sar_power(mphy, mphy->chandef.chan, tx_power);
-	tx_power -= mt76_tx_power_nss_delta(n_chains);
+	tx_power -= mt76_tx_power_path_delta(n_chains);
 	tx_power = mt76_get_rate_power_limits(mphy, mphy->chandef.chan,
 					      &limits, tx_power);
 	mphy->txpower_cur = tx_power;
@@ -2084,8 +2084,8 @@ static void mt7615_mcu_set_txpower_sku(struct mt7615_phy *phy, u8 *sku)
 		int delta = 0;
 
 		if (i < n_chains - 1)
-			delta = mt76_tx_power_nss_delta(n_chains) -
-				mt76_tx_power_nss_delta(i + 1);
+			delta = mt76_tx_power_path_delta(n_chains) -
+				mt76_tx_power_path_delta(i + 1);
 		sku[MT_SKU_1SS_DELTA + i] = delta;
 	}
 }
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/init.c b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
index be9527dd0269..3e30ca5155d2 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
@@ -285,7 +285,7 @@ static void __mt7915_init_txpower(struct mt7915_phy *phy,
 {
 	struct mt7915_dev *dev = phy->dev;
 	int i, n_chains = hweight16(phy->mt76->chainmask);
-	int nss_delta = mt76_tx_power_nss_delta(n_chains);
+	int path_delta = mt76_tx_power_path_delta(n_chains);
 	int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band);
 	struct mt76_power_limits limits;
 
@@ -305,7 +305,7 @@ static void __mt7915_init_txpower(struct mt7915_phy *phy,
 		target_power = mt76_get_rate_power_limits(phy->mt76, chan,
 							  &limits,
 							  target_power);
-		target_power += nss_delta;
+		target_power += path_delta;
 		target_power = DIV_ROUND_UP(target_power, 2);
 		chan->max_power = min_t(int, chan->max_reg_power,
 					target_power);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/init.c b/drivers/net/wireless/mediatek/mt76/mt7996/init.c
index 213c7bcd4ade..a9599c286328 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/init.c
@@ -317,8 +317,8 @@ static void __mt7996_init_txpower(struct mt7996_phy *phy,
 				  struct ieee80211_supported_band *sband)
 {
 	struct mt7996_dev *dev = phy->dev;
-	int i, nss = hweight16(phy->mt76->chainmask);
-	int nss_delta = mt76_tx_power_nss_delta(nss);
+	int i, n_chains = hweight16(phy->mt76->chainmask);
+	int path_delta = mt76_tx_power_path_delta(n_chains);
 	int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band);
 	struct mt76_power_limits limits;
 
@@ -330,7 +330,7 @@ static void __mt7996_init_txpower(struct mt7996_phy *phy,
 		target_power = mt76_get_rate_power_limits(phy->mt76, chan,
 							  &limits,
 							  target_power);
-		target_power += nss_delta;
+		target_power += path_delta;
 		target_power = DIV_ROUND_UP(target_power, 2);
 		chan->max_power = min_t(int, chan->max_reg_power,
 					target_power);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/main.c b/drivers/net/wireless/mediatek/mt76/mt7996/main.c
index 85c5d76c0c2c..970c1f890d56 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/main.c
@@ -684,7 +684,7 @@ mt7996_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 	}
 
 	n_chains = hweight16(phy->mt76->chainmask);
-	delta = mt76_tx_power_nss_delta(n_chains);
+	delta = mt76_tx_power_path_delta(n_chains);
 	*dbm = DIV_ROUND_UP(phy->mt76->txpower_cur + delta, 2);
 
 	return 0;
-- 
2.39.2



From shayne.chen at mediatek.com  Wed May 14 20:29:51 2025
From: shayne.chen at mediatek.com (Shayne Chen)
Date: Thu, 15 May 2025 11:29:51 +0800
Subject: [PATCH mt76-next 8/9] wifi: mt76: fix available_antennas setting
In-Reply-To: <20250515032952.1653494-1-shayne.chen@mediatek.com>
References: <20250515032952.1653494-1-shayne.chen@mediatek.com>
Message-ID: <20250515032952.1653494-8-shayne.chen@mediatek.com>

Check if available_antennas_tx and available_antennas_rx are already set
during the per-chip initialization phase; otherwise, they could be
overwritten with incorrect values.

Fixes: 69d54ce7491d ("wifi: mt76: mt7996: switch to single multi-radio wiphy")
Signed-off-by: Shayne Chen <shayne.chen at mediatek.com>
---
 drivers/net/wireless/mediatek/mt76/mac80211.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mac80211.c b/drivers/net/wireless/mediatek/mt76/mac80211.c
index b88d7e10742e..e9605dc22291 100644
--- a/drivers/net/wireless/mediatek/mt76/mac80211.c
+++ b/drivers/net/wireless/mediatek/mt76/mac80211.c
@@ -449,8 +449,10 @@ mt76_phy_init(struct mt76_phy *phy, struct ieee80211_hw *hw)
 	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_AIRTIME_FAIRNESS);
 	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_AQL);
 
-	wiphy->available_antennas_tx = phy->antenna_mask;
-	wiphy->available_antennas_rx = phy->antenna_mask;
+	if (!wiphy->available_antennas_tx)
+		wiphy->available_antennas_tx = phy->antenna_mask;
+	if (!wiphy->available_antennas_rx)
+		wiphy->available_antennas_rx = phy->antenna_mask;
 
 	wiphy->sar_capa = &mt76_sar_capa;
 	phy->frp = devm_kcalloc(dev->dev, wiphy->sar_capa->num_freq_ranges,
-- 
2.39.2



From shayne.chen at mediatek.com  Wed May 14 20:29:50 2025
From: shayne.chen at mediatek.com (Shayne Chen)
Date: Thu, 15 May 2025 11:29:50 +0800
Subject: [PATCH mt76-next 7/9] wifi: mt76: mt7996: fix RX buffer size of MCU event
In-Reply-To: <20250515032952.1653494-1-shayne.chen@mediatek.com>
References: <20250515032952.1653494-1-shayne.chen@mediatek.com>
Message-ID: <20250515032952.1653494-7-shayne.chen@mediatek.com>

Some management frames are first processed by the firmware and then
passed to the driver through the MCU event rings. In CONNAC3, event rings
do not support scatter-gather and have a size limitation of 2048 bytes.
If a packet sized between 1728 and 2048 bytes arrives from an event ring,
the ring will hang because the driver attempts to use scatter-gather to
process it.

To fix this, include the size of struct skb_shared_info in the MCU RX
buffer size to prevent scatter-gather from being used for event skb in
mt76_dma_rx_fill_buf().

Fixes: 98686cd21624 ("wifi: mt76: mt7996: add driver for MediaTek Wi-Fi 7 (802.11be) devices")
Co-developed-by: Peter Chiu <chui-hao.chiu at mediatek.com>
Signed-off-by: Peter Chiu <chui-hao.chiu at mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen at mediatek.com>
---
 drivers/net/wireless/mediatek/mt76/mt7996/dma.c    | 4 ++--
 drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h | 3 +++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/dma.c b/drivers/net/wireless/mediatek/mt76/mt7996/dma.c
index fe8cc1d3f738..c8bef0b2a144 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/dma.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/dma.c
@@ -531,7 +531,7 @@ int mt7996_dma_init(struct mt7996_dev *dev)
 	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
 			       MT_RXQ_ID(MT_RXQ_MCU),
 			       MT7996_RX_MCU_RING_SIZE,
-			       MT_RX_BUF_SIZE,
+			       MT7996_RX_MCU_BUF_SIZE,
 			       MT_RXQ_RING_BASE(MT_RXQ_MCU));
 	if (ret)
 		return ret;
@@ -540,7 +540,7 @@ int mt7996_dma_init(struct mt7996_dev *dev)
 	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
 			       MT_RXQ_ID(MT_RXQ_MCU_WA),
 			       MT7996_RX_MCU_RING_SIZE_WA,
-			       MT_RX_BUF_SIZE,
+			       MT7996_RX_MCU_BUF_SIZE,
 			       MT_RXQ_RING_BASE(MT_RXQ_MCU_WA));
 	if (ret)
 		return ret;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h b/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
index c75189a02316..1ad6bc046f7c 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
@@ -29,6 +29,9 @@
 #define MT7996_RX_RING_SIZE		1536
 #define MT7996_RX_MCU_RING_SIZE		512
 #define MT7996_RX_MCU_RING_SIZE_WA	1024
+/* scatter-gather of mcu event is not supported in connac3 */
+#define MT7996_RX_MCU_BUF_SIZE		(2048 + \
+					 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
 
 #define MT7996_DEVICE_ID		0x7990
 #define MT7996_DEVICE_ID_2		0x7991
-- 
2.39.2



From shayne.chen at mediatek.com  Wed May 14 20:29:47 2025
From: shayne.chen at mediatek.com (Shayne Chen)
Date: Thu, 15 May 2025 11:29:47 +0800
Subject: [PATCH mt76-next 4/9] wifi: mt76: mt7996: drop fragments with multicast or broadcast RA
In-Reply-To: <20250515032952.1653494-1-shayne.chen@mediatek.com>
References: <20250515032952.1653494-1-shayne.chen@mediatek.com>
Message-ID: <20250515032952.1653494-4-shayne.chen@mediatek.com>

From: Benjamin Lin <benjamin-jw.lin at mediatek.com>

IEEE 802.11 fragmentation can only be applied to unicast frames.
Therefore, drop fragments with multicast or broadcast RA. This patch
addresses vulnerabilities such as CVE-2020-26145.

Signed-off-by: Benjamin Lin <benjamin-jw.lin at mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen at mediatek.com>
---
 drivers/net/wireless/mediatek/mt76/mt7996/mac.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
index 771c16e8d10c..0dbd4662bc84 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
@@ -647,6 +647,14 @@ mt7996_mac_fill_rx(struct mt7996_dev *dev, enum mt76_rxq_id q,
 		status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME;
 	}
 
+	/* IEEE 802.11 fragmentation can only be applied to unicast frames.
+	 * Hence, drop fragments with multicast/broadcast RA.
+	 * This check fixes vulnerabilities, like CVE-2020-26145.
+	 */
+	if ((ieee80211_has_morefrags(fc) || seq_ctrl & IEEE80211_SCTL_FRAG) &&
+	    FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) != MT_RXD3_NORMAL_U2M)
+		return -EINVAL;
+
 	hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
 	if (hdr_trans && ieee80211_has_morefrags(fc)) {
 		if (mt7996_reverse_frag0_hdr_trans(skb, hdr_gap))
-- 
2.39.2



From shayne.chen at mediatek.com  Wed May 14 20:29:46 2025
From: shayne.chen at mediatek.com (Shayne Chen)
Date: Thu, 15 May 2025 11:29:46 +0800
Subject: [PATCH mt76-next 3/9] wifi: mt76: mt7996: set EHT max ampdu length capability
In-Reply-To: <20250515032952.1653494-1-shayne.chen@mediatek.com>
References: <20250515032952.1653494-1-shayne.chen@mediatek.com>
Message-ID: <20250515032952.1653494-3-shayne.chen@mediatek.com>

From: Peter Chiu <chui-hao.chiu at mediatek.com>

Set the max AMPDU length in the EHT MAC CAP. Without this patch, the
peer station cannot obtain the correct capability, which prevents
achieving peak throughput on the 2 GHz band.

Fixes: 1816ad9381e0 ("wifi: mt76: mt7996: add max mpdu len capability")
Signed-off-by: Peter Chiu <chui-hao.chiu at mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen at mediatek.com>
---
 drivers/net/wireless/mediatek/mt76/mt7996/init.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/init.c b/drivers/net/wireless/mediatek/mt76/mt7996/init.c
index 5c545293f294..213c7bcd4ade 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/init.c
@@ -1326,6 +1326,9 @@ mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band,
 		u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454,
 			       IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
 
+	eht_cap_elem->mac_cap_info[1] |=
+		IEEE80211_EHT_MAC_CAP1_MAX_AMPDU_LEN_MASK;
+
 	eht_cap_elem->phy_cap_info[0] =
 		IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
 		IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER |
-- 
2.39.2



From shayne.chen at mediatek.com  Wed May 14 20:29:49 2025
From: shayne.chen at mediatek.com (Shayne Chen)
Date: Thu, 15 May 2025 11:29:49 +0800
Subject: [PATCH mt76-next 6/9] wifi: mt76: mt7996: change max beacon size
In-Reply-To: <20250515032952.1653494-1-shayne.chen@mediatek.com>
References: <20250515032952.1653494-1-shayne.chen@mediatek.com>
Message-ID: <20250515032952.1653494-6-shayne.chen@mediatek.com>

From: Peter Chiu <chui-hao.chiu at mediatek.com>

According to hardware capability, the maximum beacon size is 2048 bytes
minus the size of TLV headers.

Signed-off-by: Peter Chiu <chui-hao.chiu at mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen at mediatek.com>
---
 drivers/net/wireless/mediatek/mt76/mt7996/mcu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mcu.h b/drivers/net/wireless/mediatek/mt76/mt7996/mcu.h
index fd660e913b82..130ea95626d5 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mcu.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mcu.h
@@ -832,13 +832,13 @@ enum {
 					 sizeof(struct sta_rec_eht_mld) +	\
 					 sizeof(struct tlv))
 
-#define MT7996_MAX_BEACON_SIZE		1338
 #define MT7996_BEACON_UPDATE_SIZE	(sizeof(struct bss_req_hdr) +		\
 					 sizeof(struct bss_bcn_content_tlv) +	\
 					 4 + MT_TXD_SIZE +			\
 					 sizeof(struct bss_bcn_cntdwn_tlv) +	\
 					 sizeof(struct bss_bcn_mbss_tlv))
-#define MT7996_MAX_BSS_OFFLOAD_SIZE	(MT7996_MAX_BEACON_SIZE +		\
+#define MT7996_MAX_BSS_OFFLOAD_SIZE	2048
+#define MT7996_MAX_BEACON_SIZE		(MT7996_MAX_BSS_OFFLOAD_SIZE - \
 					 MT7996_BEACON_UPDATE_SIZE)
 
 enum {
-- 
2.39.2



From Darren.Ye at mediatek.com  Wed May 14 20:50:54 2025
From: Darren.Ye at mediatek.com (=?utf-8?B?RGFycmVuIFllICjlj7bpo54p?=)
Date: Thu, 15 May 2025 03:50:54 +0000
Subject: [PATCH v3 10/10] ASoC: dt-bindings: mediatek,mt8196-nau8825: add
 mt8196-nau8825 document
In-Reply-To: <67a7343b-fd1e-4276-83b0-baa28d19f207@kernel.org>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
	 <20250514081125.24475-11-darren.ye@mediatek.com>
	 <67a7343b-fd1e-4276-83b0-baa28d19f207@kernel.org>
Message-ID: <a4771a76db6489b6c8507d602fc4cfca17432091.camel@mediatek.com>

On Wed, 2025-05-14 at 12:51 +0200, Krzysztof Kozlowski wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 14/05/2025 10:11, Darren.Ye wrote:
> 
> 
> A nit, subject: drop second/last, redundant "document". The
> "dt-bindings" prefix is already stating that this is a document.
> See also:
> 
https://urldefense.com/v3/__https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst*L18__;Iw!!CTRNKA9wMg0ARbw!n2tXtMjEajr9rjHgxY8HrobIrVxtB-rr5xjm626EgyDG7NvXrrcPBhoZZwxgdLatAHHuyyUpD9gF0g$
> 
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - mediatek,mt8196-nau8825-sound
> > +      - mediatek,mt8196-rt5682s-sound
> > +      - mediatek,mt8196-rt5650-sound
> > +
> > +  audio-routing:
> > +    description:
> > +      Valid names could be the input or output widgets of audio
> > components,
> > +      power supplies, MicBias of codec and the software switch.
> 
> Nothing improved. I asked to drop the property. Why do you need it?

> I am so sorry to lose your advice and make up the next version,
thanks. confirm with you again the remove of audio-routing property.
>
> > +
> > +  mediatek,platform:
> > +    $ref: /schemas/types.yaml#/definitions/phandle
> > +    description: The phandle of MT8188 ASoC platform.
> > +
> > +  mediatek,adsp:
> > +    $ref: /schemas/types.yaml#/definitions/phandle
> > +    description:
> > +      The phandle of the MT8188 ADSP platform, which is the
> > optional Audio DSP
> > +      hardware that provides additional audio functionalities if
> > present.
> > +      The AFE will link to ADSP when the phandle is provided.
> > +
> 
> ...
> remove of mediatek,adsp property.
> 
> > +      codec:
> > +        description: Holds subnode which indicates codec dai.
> > +        type: object
> > +        additionalProperties: false
> > +        properties:
> > +          sound-dai:
> > +            minItems: 1
> > +            maxItems: 2
> > +        required:
> > +          - sound-dai
> > +
> > +      dai-format:
> > +        description: audio format.
> > +        items:
> > +          enum:
> > +            - i2s
> > +            - right_j
> > +            - left_j
> > +            - dsp_a
> > +            - dsp_b
> > +
> > +      mediatek,clk-provider:
> > +        $ref: /schemas/types.yaml#/definitions/string
> > +        description: Indicates dai-link clock master.
> > +        items:
> 
> Drop items
>
> Drop items: line
>
> +          enum:
> > +            - cpu
> > +            - codec
> > +
> > +    additionalProperties: false
> > +
> > +    required:
> > +      - link-name
> > +
> > +unevaluatedProperties: false
> 
> This goes after required: block.
> 
> modify as follows 
> required:
>   - compatible
>   - mediatek,platform
>
> unevaluatedProperties: false
>
> Best regards,
> Darren
>
> > +
> > +required:
> > +  - compatible
> > +  - mediatek,platform
> 
> 
> Best regards,
> Krzysztof

From Darren.Ye at mediatek.com  Wed May 14 20:57:51 2025
From: Darren.Ye at mediatek.com (=?utf-8?B?RGFycmVuIFllICjlj7bpo54p?=)
Date: Thu, 15 May 2025 03:57:51 +0000
Subject: [PATCH v3 08/10] ASoC: dt-bindings: mediatek,mt8196-afe: add
 audio AFE document
In-Reply-To: <e74d82b3-ed4a-433b-9305-a80b68130a6f@kernel.org>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
	 <20250514081125.24475-9-darren.ye@mediatek.com>
	 <e74d82b3-ed4a-433b-9305-a80b68130a6f@kernel.org>
Message-ID: <01c01a1e0571b88935ad666675b74f40b4cd4a46.camel@mediatek.com>

On Wed, 2025-05-14 at 12:54 +0200, Krzysztof Kozlowski wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 14/05/2025 10:11, Darren.Ye wrote:
> > From: Darren Ye <darren.ye at mediatek.com>
> > 
> > Add mt8196 audio AFE document.
> 
> A nit, subject: drop second/last, redundant "document".
> See also:
> 
https://urldefense.com/v3/__https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst*L18__;Iw!!CTRNKA9wMg0ARbw!iSQl6_WMX8Q6wsBj4pVe7Tdnbd2zpPwSmHMSm4hlhkD0lO7h5JSAr28-dUj_DwLrXhU_IByy_QWQGQ$
> 
> > 
> > Signed-off-by: Darren Ye <darren.ye at mediatek.com>
> 
> 
> ...
> 
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - mediatek,vlpcksys
> > +  - power-domains
> > +  - memory-region
> > +  - clocks
> > +  - clock-names
> 
> 
> Keep the same order as in properties:.
> 

ok, thanks.

Best regards,
Darren

> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> 
> <form letter>
> This is an automated instruction, just in case, because many review
> tags
> are being ignored. If you know the process, you can skip it (please
> do
> not feel offended by me posting it here - no bad intentions
> intended).
> If you do not know the process, here is a short explanation:
> 
> Please add Acked-by/Reviewed-by/Tested-by tags when posting new
> versions
> of patchset, under or above your Signed-off-by tag, unless patch
> changed
> significantly (e.g. new properties added to the DT bindings). Tag is
> "received", when provided in a message replied to you on the mailing
> list. Tools like b4 can help here. However, there's no need to repost
> patches *only* to add the tags. The upstream maintainer will do that
> for
> tags received on the version they apply.
> 
> Full context and explanation:
> 
https://urldefense.com/v3/__https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst*L577__;Iw!!CTRNKA9wMg0ARbw!iSQl6_WMX8Q6wsBj4pVe7Tdnbd2zpPwSmHMSm4hlhkD0lO7h5JSAr28-dUj_DwLrXhU_IBzvkGpWKg$
> </form letter>
> 
> 
> Best regards,
> Krzysztof

From lkp at intel.com  Wed May 14 21:41:50 2025
From: lkp at intel.com (kernel test robot)
Date: Thu, 15 May 2025 12:41:50 +0800
Subject: [PATCH v3 07/10] ASoC: mediatek: mt8196: add platform driver
In-Reply-To: <20250514081125.24475-8-darren.ye@mediatek.com>
References: <20250514081125.24475-8-darren.ye@mediatek.com>
Message-ID: <202505151200.uFAkmc5O-lkp@intel.com>

Hi Darren.Ye,

kernel test robot noticed the following build warnings:

[auto build test WARNING on broonie-sound/for-next]
[also build test WARNING on broonie-spi/for-next robh/for-next linus/master v6.15-rc6 next-20250514]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Darren-Ye/ASoC-mediatek-common-modify-mtk-afe-platform-driver-for-mt8196/20250514-161921
base:   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
patch link:    https://lore.kernel.org/r/20250514081125.24475-8-darren.ye%40mediatek.com
patch subject: [PATCH v3 07/10] ASoC: mediatek: mt8196: add platform driver
config: arm-allmodconfig (https://download.01.org/0day-ci/archive/20250515/202505151200.uFAkmc5O-lkp at intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250515/202505151200.uFAkmc5O-lkp at intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505151200.uFAkmc5O-lkp at intel.com/

All warnings (new ones prefixed by >>):

>> sound/soc/mediatek/mt8196/mt8196-dai-adda.c:384:30: warning: 'mt8196_adda_enum' defined but not used [-Wunused-const-variable=]
     384 | static const struct soc_enum mt8196_adda_enum[] = {
         |                              ^~~~~~~~~~~~~~~~
--
   sound/soc/mediatek/mt8196/mt8196-dai-i2s.c: In function 'init_i2s_priv_data':
>> sound/soc/mediatek/mt8196/mt8196-dai-i2s.c:4001:21: warning: the comparison will always evaluate as 'true' for the address of 'mt8196_i2s_priv' will never be NULL [-Waddress]
    4001 |                 if (&mt8196_i2s_priv[i]) {
         |                     ^
   sound/soc/mediatek/mt8196/mt8196-dai-i2s.c:3889:38: note: 'mt8196_i2s_priv' declared here
    3889 | static const struct mtk_afe_i2s_priv mt8196_i2s_priv[DAI_I2S_NUM] = {
         |                                      ^~~~~~~~~~~~~~~


vim +/mt8196_adda_enum +384 sound/soc/mediatek/mt8196/mt8196-dai-adda.c

640b731680b027 Darren Ye 2025-05-14  383  
640b731680b027 Darren Ye 2025-05-14 @384  static const struct soc_enum mt8196_adda_enum[] = {
640b731680b027 Darren Ye 2025-05-14  385  	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8196_adda_off_on_str),
640b731680b027 Darren Ye 2025-05-14  386  			    mt8196_adda_off_on_str),
640b731680b027 Darren Ye 2025-05-14  387  };
640b731680b027 Darren Ye 2025-05-14  388  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki


From frank-w at public-files.de  Wed May 14 22:40:49 2025
From: frank-w at public-files.de (Frank Wunderlich)
Date: Thu, 15 May 2025 05:40:49 +0000
Subject: Aw: Re: [PATCH v1 03/14] dt-bindings: net: dsa: mediatek,mt7530:
 add internal mdio bus
In-Reply-To: <20250514211810.GA3051536-robh@kernel.org>
References: <20250511141942.10284-1-linux@fw-web.de>
 <20250511141942.10284-4-linux@fw-web.de>
 <20250514211810.GA3051536-robh@kernel.org>
Message-ID: <trinity-59d5f7b7-741b-4cd0-80c5-45191f6918e4-1747287649179@trinity-msg-rest-gmx-gmx-live-f4858f84-4zhfg>

Hi Rob,

thanks for review

> Gesendet: Mittwoch, 14. Mai 2025 um 23:18
> Von: "Rob Herring" <robh at kernel.org>
> Betreff: Re: [PATCH v1 03/14] dt-bindings: net: dsa: mediatek,mt7530: add internal mdio bus
>
> On Sun, May 11, 2025 at 04:19:19PM +0200, Frank Wunderlich wrote:
> > From: Frank Wunderlich <frank-w at public-files.de>
> > 
> > Mt7988 buildin switch has own mdio bus where ge-phys are connected.
> > Add related property for this.
> > 
> > Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> > ---
> >  Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
> > index bb22c36749fc..5f1363278f43 100644
> > --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
> > +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
> > @@ -156,6 +156,9 @@ properties:
> >      maxItems: 1
> >  
> >  patternProperties:
> > +  "^mdio(-bus)?$":
> 
> Really need 2 names?

no, i only tried to stay close to definition in mdio.yaml ;) there are some mt7988 boards floating around
where i do not know the dts. But i can make only "mdio" to be changed later if needed.

> > +    $ref: /schemas/net/mdio.yaml#
> 
>        unevaluatedProperties: false

ok, then i need to add 'mediatek,pio' subproperty in next round...would be ok in this way?

  "^mdio(-bus)?$":
    $ref: /schemas/net/mdio.yaml#
    unevaluatedProperties: false

    properties:
      mediatek,pio:
        $ref: /schemas/types.yaml#/definitions/phandle
        description:
          Phandle pointing to the mediatek pinctrl node.

regards Frank


From wenst at chromium.org  Wed May 14 23:13:53 2025
From: wenst at chromium.org (Chen-Yu Tsai)
Date: Thu, 15 May 2025 14:13:53 +0800
Subject: [PATCH 0/3] ASoC: mediatek: mt8183-afe-pcm: Shorten source code
In-Reply-To: <aCSqWbT9t1T29HT_@finisterre.sirena.org.uk>
References: <20250425082551.1467042-1-wenst@chromium.org> <86b55c96-7ec3-48ed-83b4-f434d7fcb5c2@collabora.com>
 <aCSqWbT9t1T29HT_@finisterre.sirena.org.uk>
Message-ID: <CAGXv+5Eq1=TqhZmdhNY5H1s52omit7CZhNhYpRddcJAxGN2P6g@mail.gmail.com>

On Wed, May 14, 2025 at 10:36?PM Mark Brown <broonie at kernel.org> wrote:
>
> On Wed, May 14, 2025 at 03:49:48PM +0200, AngeloGioacchino Del Regno wrote:
> > Il 25/04/25 10:25, Chen-Yu Tsai ha scritto:
>
> > > This series is meant as an example on how to use macros and range cases
> > > to shorten the MediaTek audio frontend drivers. The drivers have large
> > > tables describing the registers and register fields for every supported
> > > audio DMA interface. (Some are actually skipped!) There's a lot of
> > > duplication which can be eliminated using macros. This should serve as
> > > a reference for the MT8196 AFE driver that I had commented on.
>
> > Sorry for the very long wait here; the entire series is
>
> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
>
> Unfortunately this doesn't apply against current code (I guess due to
> development in the intervening time), could you please check and resend?

This series is based on the other series that I sent for reworking
reserved memory, in particular the patch

    ASoC: mediatek: mt8183-afe-pcm: Support >32 bit DMA addresses

touches the same parts.

Since this series is ready, I'll rebase it and resend.

ChenYu


From lorenzo at kernel.org  Wed May 14 23:33:00 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Thu, 15 May 2025 08:33:00 +0200
Subject: [PATCH net] net: airoha: Fix page recycling in
 airoha_qdma_rx_process()
In-Reply-To: <20250514190917.4b0ff404@kernel.org>
References: <20250513-airoha-fix-rx-process-error-condition-v1-1-e5d70cd7c066@kernel.org>
 <20250514190917.4b0ff404@kernel.org>
Message-ID: <aCWKnGVkjlS_d1I2@lore-desk>

> On Tue, 13 May 2025 18:34:44 +0200 Lorenzo Bianconi wrote:
> > Do not recycle the page twice in airoha_qdma_rx_process routine in case
> > of error. Just run dev_kfree_skb() if the skb has been allocated and marked
> > for recycling. Run page_pool_put_full_page() directly if the skb has not
> > been allocated yet.
> > Moreover, rely on DMA address from queue entry element instead of reading
> > it from the DMA descriptor for DMA syncing in airoha_qdma_rx_process().
> > 
> > Fixes: e12182ddb6e71 ("net: airoha: Enable Rx Scatter-Gather")
> 
> Missed your sign-off.

ops, let me fix it in v2.

Regards,
Lorenzo

> -- 
> pw-bot: cr
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From lorenzo at kernel.org  Wed May 14 23:33:06 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Thu, 15 May 2025 08:33:06 +0200
Subject: [PATCH net v2] net: airoha: Fix page recycling in
 airoha_qdma_rx_process()
Message-ID: <20250515-airoha-fix-rx-process-error-condition-v2-1-657e92c894b9@kernel.org>

Do not recycle the page twice in airoha_qdma_rx_process routine in case
of error. Just run dev_kfree_skb() if the skb has been allocated and marked
for recycling. Run page_pool_put_full_page() directly if the skb has not
been allocated yet.
Moreover, rely on DMA address from queue entry element instead of reading
it from the DMA descriptor for DMA syncing in airoha_qdma_rx_process().

Fixes: e12182ddb6e71 ("net: airoha: Enable Rx Scatter-Gather")
Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
Changes in v2:
- Add missing signed-off-by
- Link to v1: https://lore.kernel.org/r/20250513-airoha-fix-rx-process-error-condition-v1-1-e5d70cd7c066 at kernel.org
---
 drivers/net/ethernet/airoha/airoha_eth.c | 22 +++++++++-------------
 1 file changed, 9 insertions(+), 13 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index d748dc6de92367365db9f9548f9af52a7fdac187..1e9ab65218ff144d99b47f5d4ad5ff4f9c227418 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -614,7 +614,6 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
 		struct airoha_queue_entry *e = &q->entry[q->tail];
 		struct airoha_qdma_desc *desc = &q->desc[q->tail];
 		u32 hash, reason, msg1 = le32_to_cpu(desc->msg1);
-		dma_addr_t dma_addr = le32_to_cpu(desc->addr);
 		struct page *page = virt_to_head_page(e->buf);
 		u32 desc_ctrl = le32_to_cpu(desc->ctrl);
 		struct airoha_gdm_port *port;
@@ -623,22 +622,16 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
 		if (!(desc_ctrl & QDMA_DESC_DONE_MASK))
 			break;
 
-		if (!dma_addr)
-			break;
-
-		len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl);
-		if (!len)
-			break;
-
 		q->tail = (q->tail + 1) % q->ndesc;
 		q->queued--;
 
-		dma_sync_single_for_cpu(eth->dev, dma_addr,
+		dma_sync_single_for_cpu(eth->dev, e->dma_addr,
 					SKB_WITH_OVERHEAD(q->buf_size), dir);
 
+		len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl);
 		data_len = q->skb ? q->buf_size
 				  : SKB_WITH_OVERHEAD(q->buf_size);
-		if (data_len < len)
+		if (!len || data_len < len)
 			goto free_frag;
 
 		p = airoha_qdma_get_gdm_port(eth, desc);
@@ -701,9 +694,12 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
 		q->skb = NULL;
 		continue;
 free_frag:
-		page_pool_put_full_page(q->page_pool, page, true);
-		dev_kfree_skb(q->skb);
-		q->skb = NULL;
+		if (q->skb) {
+			dev_kfree_skb(q->skb);
+			q->skb = NULL;
+		} else {
+			page_pool_put_full_page(q->page_pool, page, true);
+		}
 	}
 	airoha_qdma_fill_rx_queue(q);
 

---
base-commit: 09db7a4d287d1a2bcfc04df023c103d1213a0518
change-id: 20250513-airoha-fix-rx-process-error-condition-b6e5db52fd4f

Best regards,
-- 
Lorenzo Bianconi <lorenzo at kernel.org>



From lkp at intel.com  Thu May 15 00:27:42 2025
From: lkp at intel.com (kernel test robot)
Date: Thu, 15 May 2025 15:27:42 +0800
Subject: [PATCH v3 09/10] ASoC: mediatek: mt8196: add machine driver with
 nau8825
In-Reply-To: <20250514081125.24475-10-darren.ye@mediatek.com>
References: <20250514081125.24475-10-darren.ye@mediatek.com>
Message-ID: <202505151544.DAAAOmfW-lkp@intel.com>

Hi Darren.Ye,

kernel test robot noticed the following build errors:

[auto build test ERROR on broonie-sound/for-next]
[also build test ERROR on broonie-spi/for-next robh/for-next linus/master v6.15-rc6 next-20250514]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Darren-Ye/ASoC-mediatek-common-modify-mtk-afe-platform-driver-for-mt8196/20250514-161921
base:   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
patch link:    https://lore.kernel.org/r/20250514081125.24475-10-darren.ye%40mediatek.com
patch subject: [PATCH v3 09/10] ASoC: mediatek: mt8196: add machine driver with nau8825
config: arm-allmodconfig (https://download.01.org/0day-ci/archive/20250515/202505151544.DAAAOmfW-lkp at intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250515/202505151544.DAAAOmfW-lkp at intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505151544.DAAAOmfW-lkp at intel.com/

All errors (new ones prefixed by >>):

>> sound/soc/mediatek/mt8196/mt8196-nau8825.c:451:49: error: 'SND_SOC_DAIFMT_CBS_CFS' undeclared here (not in a function); did you mean 'SND_SOC_DAIFMT_CBP_CFC'?
     451 |                 .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
         |                                                 ^~~~~~~~~~~~~~~~~~~~~~
         |                                                 SND_SOC_DAIFMT_CBP_CFC


vim +451 sound/soc/mediatek/mt8196/mt8196-nau8825.c

   245	
   246	/* FE */
   247	SND_SOC_DAILINK_DEFS(playback1,
   248			     DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
   249			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   250			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   251	SND_SOC_DAILINK_DEFS(playback_24ch,
   252			     DAILINK_COMP_ARRAY(COMP_CPU("DL_24CH")),
   253			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   254			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   255	SND_SOC_DAILINK_DEFS(capture0,
   256			     DAILINK_COMP_ARRAY(COMP_CPU("UL0")),
   257			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   258			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   259	SND_SOC_DAILINK_DEFS(capture1,
   260			     DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
   261			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   262			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   263	SND_SOC_DAILINK_DEFS(capture2,
   264			     DAILINK_COMP_ARRAY(COMP_CPU("UL2")),
   265			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   266			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   267	SND_SOC_DAILINK_DEFS(playback_hdmi,
   268			     DAILINK_COMP_ARRAY(COMP_CPU("HDMI")),
   269			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   270			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   271	SND_SOC_DAILINK_DEFS(playback2,
   272			     DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
   273			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   274			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   275	SND_SOC_DAILINK_DEFS(capture_cm0,
   276			     DAILINK_COMP_ARRAY(COMP_CPU("UL_CM0")),
   277			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   278			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   279	/* BE */
   280	SND_SOC_DAILINK_DEFS(ap_dmic,
   281			     DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC")),
   282			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   283			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   284	SND_SOC_DAILINK_DEFS(ap_dmic_ch34,
   285			     DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC_CH34")),
   286			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   287			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   288	SND_SOC_DAILINK_DEFS(ap_dmic_multich,
   289			     DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC_MULTICH")),
   290			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   291			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   292	SND_SOC_DAILINK_DEFS(i2sin6,
   293			     DAILINK_COMP_ARRAY(COMP_CPU("I2SIN6")),
   294			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   295			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   296	SND_SOC_DAILINK_DEFS(i2sout3,
   297			     DAILINK_COMP_ARRAY(COMP_CPU("I2SOUT3")),
   298			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   299			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   300	SND_SOC_DAILINK_DEFS(i2sout4,
   301			     DAILINK_COMP_ARRAY(COMP_CPU("I2SOUT4")),
   302			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   303			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   304	SND_SOC_DAILINK_DEFS(i2sout6,
   305			     DAILINK_COMP_ARRAY(COMP_CPU("I2SOUT6")),
   306			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   307			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   308	SND_SOC_DAILINK_DEFS(tdm_dptx,
   309			     DAILINK_COMP_ARRAY(COMP_CPU("TDM_DPTX")),
   310			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   311			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   312	SND_SOC_DAILINK_DEFS(AFE_SOF_DL_24CH,
   313			     DAILINK_COMP_ARRAY(COMP_CPU("SOF_DL_24CH")),
   314			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   315			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   316	SND_SOC_DAILINK_DEFS(AFE_SOF_DL1,
   317			     DAILINK_COMP_ARRAY(COMP_CPU("SOF_DL1")),
   318			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   319			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   320	SND_SOC_DAILINK_DEFS(AFE_SOF_UL0,
   321			     DAILINK_COMP_ARRAY(COMP_CPU("SOF_UL0")),
   322			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   323			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   324	SND_SOC_DAILINK_DEFS(AFE_SOF_UL1,
   325			     DAILINK_COMP_ARRAY(COMP_CPU("SOF_UL1")),
   326			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   327			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   328	SND_SOC_DAILINK_DEFS(AFE_SOF_UL2,
   329			     DAILINK_COMP_ARRAY(COMP_CPU("SOF_UL2")),
   330			     DAILINK_COMP_ARRAY(COMP_DUMMY()),
   331			     DAILINK_COMP_ARRAY(COMP_EMPTY()));
   332	
   333	static struct snd_soc_dai_link mt8196_nau8825_dai_links[] = {
   334		/*
   335		 * The SOF topology expects PCM streams 0~4 to be available
   336		 * for the SOF PCM streams. Put the SOF BE definitions here
   337		 * so that the PCM device numbers are skipped over.
   338		 * (BE dailinks do not have PCM devices created.)
   339		 */
   340		{
   341			.name = "AFE_SOF_DL_24CH",
   342			.no_pcm = 1,
   343			.playback_only = 1,
   344			.ops = &mt8196_sof_be_ops,
   345			SND_SOC_DAILINK_REG(AFE_SOF_DL_24CH),
   346		},
   347		{
   348			.name = "AFE_SOF_DL1",
   349			.no_pcm = 1,
   350			.playback_only = 1,
   351			.ops = &mt8196_sof_be_ops,
   352			SND_SOC_DAILINK_REG(AFE_SOF_DL1),
   353		},
   354		{
   355			.name = "AFE_SOF_UL0",
   356			.no_pcm = 1,
   357			.capture_only = 1,
   358			.ops = &mt8196_sof_be_ops,
   359			SND_SOC_DAILINK_REG(AFE_SOF_UL0),
   360		},
   361		{
   362			.name = "AFE_SOF_UL1",
   363			.no_pcm = 1,
   364			.capture_only = 1,
   365			.ops = &mt8196_sof_be_ops,
   366			SND_SOC_DAILINK_REG(AFE_SOF_UL1),
   367		},
   368		{
   369			.name = "AFE_SOF_UL2",
   370			.no_pcm = 1,
   371			.capture_only = 1,
   372			.ops = &mt8196_sof_be_ops,
   373			SND_SOC_DAILINK_REG(AFE_SOF_UL2),
   374		},
   375		/* Front End DAI links */
   376		{
   377			.name = "HDMI_FE",
   378			.stream_name = "HDMI Playback",
   379			.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
   380				    SND_SOC_DPCM_TRIGGER_PRE},
   381			.dynamic = 1,
   382			.playback_only = 1,
   383			SND_SOC_DAILINK_REG(playback_hdmi),
   384		},
   385		{
   386			.name = "DL2_FE",
   387			.stream_name = "DL2 Playback",
   388			.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
   389				    SND_SOC_DPCM_TRIGGER_PRE},
   390			.dynamic = 1,
   391			.playback_only = 1,
   392			SND_SOC_DAILINK_REG(playback2),
   393		},
   394		{
   395			.name = "UL_CM0_FE",
   396			.stream_name = "UL_CM0 Capture",
   397			.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
   398				    SND_SOC_DPCM_TRIGGER_PRE},
   399			.dynamic = 1,
   400			.capture_only = 1,
   401			SND_SOC_DAILINK_REG(capture_cm0),
   402		},
   403		{
   404			.name = "DL_24CH_FE",
   405			.stream_name = "DL_24CH Playback",
   406			.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
   407					SND_SOC_DPCM_TRIGGER_PRE},
   408			.dynamic = 1,
   409			.playback_only = 1,
   410			SND_SOC_DAILINK_REG(playback_24ch),
   411		},
   412		{
   413			.name = "DL1_FE",
   414			.stream_name = "DL1 Playback",
   415			.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
   416					SND_SOC_DPCM_TRIGGER_PRE},
   417			.dynamic = 1,
   418			.playback_only = 1,
   419			SND_SOC_DAILINK_REG(playback1),
   420		},
   421		{
   422			.name = "UL0_FE",
   423			.stream_name = "UL0 Capture",
   424			.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
   425					SND_SOC_DPCM_TRIGGER_PRE},
   426			.dynamic = 1,
   427			.capture_only = 1,
   428			SND_SOC_DAILINK_REG(capture0),
   429		},
   430		{
   431			.name = "UL1_FE",
   432			.stream_name = "UL1 Capture",
   433			.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
   434					SND_SOC_DPCM_TRIGGER_PRE},
   435			.dynamic = 1,
   436			.capture_only = 1,
   437			SND_SOC_DAILINK_REG(capture1),
   438		},
   439		{
   440			.name = "UL2_FE",
   441			.stream_name = "UL2 Capture",
   442			.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
   443					SND_SOC_DPCM_TRIGGER_PRE},
   444			.dynamic = 1,
   445			.capture_only = 1,
   446			SND_SOC_DAILINK_REG(capture2),
   447		},
   448		/* Back End DAI links */
   449		{
   450			.name = "I2SIN6_BE",
 > 451			.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
   452				| SND_SOC_DAIFMT_GATED,
   453			.ops = &mt8196_nau8825_i2s_ops,
   454			.no_pcm = 1,
   455			.capture_only = 1,
   456			.ignore_suspend = 1,
   457			.be_hw_params_fixup = mt8196_i2s_hw_params_fixup,
   458			SND_SOC_DAILINK_REG(i2sin6),
   459		},
   460		{
   461			.name = "I2SOUT4_BE",
   462			.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
   463				| SND_SOC_DAIFMT_GATED,
   464			.ops = &mt8196_nau8825_i2s_ops,
   465			.no_pcm = 1,
   466			.playback_only = 1,
   467			.ignore_suspend = 1,
   468			.ignore_pmdown_time = 1,
   469			.be_hw_params_fixup = mt8196_i2s_hw_params_fixup,
   470			SND_SOC_DAILINK_REG(i2sout4),
   471		},
   472		{
   473			.name = "I2SOUT6_BE",
   474			.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
   475				| SND_SOC_DAIFMT_GATED,
   476			.ops = &mt8196_nau8825_i2s_ops,
   477			.no_pcm = 1,
   478			.playback_only = 1,
   479			.ignore_suspend = 1,
   480			.be_hw_params_fixup = mt8196_i2s_hw_params_fixup,
   481			SND_SOC_DAILINK_REG(i2sout6),
   482		},
   483		{
   484			.name = "AP_DMIC_BE",
   485			.no_pcm = 1,
   486			.capture_only = 1,
   487			.ignore_suspend = 1,
   488			SND_SOC_DAILINK_REG(ap_dmic),
   489		},
   490		{
   491			.name = "AP_DMIC_CH34_BE",
   492			.no_pcm = 1,
   493			.capture_only = 1,
   494			.ignore_suspend = 1,
   495			SND_SOC_DAILINK_REG(ap_dmic_ch34),
   496		},
   497		{
   498			.name = "AP_DMIC_MULTICH_BE",
   499			.no_pcm = 1,
   500			.capture_only = 1,
   501			.ignore_suspend = 1,
   502			SND_SOC_DAILINK_REG(ap_dmic_multich),
   503		},
   504		{
   505			.name = "TDM_DPTX_BE",
   506			.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
   507				| SND_SOC_DAIFMT_GATED,
   508			.ops = &mt8196_dptx_ops,
   509			.be_hw_params_fixup = mt8196_dptx_hw_params_fixup,
   510			.no_pcm = 1,
   511			.playback_only = 1,
   512			.ignore_suspend = 1,
   513			SND_SOC_DAILINK_REG(tdm_dptx),
   514		},
   515		{
   516			.name = "I2SOUT3_BE",
   517			.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
   518				| SND_SOC_DAIFMT_GATED,
   519			.ops = &mt8196_nau8825_i2s_ops,
   520			.no_pcm = 1,
   521			.playback_only = 1,
   522			.ignore_suspend = 1,
   523			SND_SOC_DAILINK_REG(i2sout3),
   524		},
   525	};
   526	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki


From broonie at kernel.org  Thu May 15 00:35:21 2025
From: broonie at kernel.org (Mark Brown)
Date: Thu, 15 May 2025 09:35:21 +0200
Subject: [PATCH] ASoC: dt-bindings: mediatek: Simplify
 mediatek,clk-provider
In-Reply-To: <20250514105702.28622-2-krzysztof.kozlowski@linaro.org>
References: <20250514105702.28622-2-krzysztof.kozlowski@linaro.org>
Message-ID: <174729452159.272498.16252204109859942609.b4-ty@kernel.org>

On Wed, 14 May 2025 12:57:03 +0200, Krzysztof Kozlowski wrote:
> "mediatek,clk-provider" property is a string, not an string array, thus
> "items" is not really correct.
> 
> 

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[1/1] ASoC: dt-bindings: mediatek: Simplify mediatek,clk-provider
      commit: 0e4e9d75899cae4e7f379c50fa3d0121eff9641f

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark



From wenst at chromium.org  Thu May 15 00:38:20 2025
From: wenst at chromium.org (Chen-Yu Tsai)
Date: Thu, 15 May 2025 15:38:20 +0800
Subject: [PATCH v2 0/3] ASoC: mediatek: mt8183-afe-pcm: Shorten source code
Message-ID: <20250515073825.4155297-1-wenst@chromium.org>

Hi folks,

Changes since v1:
- Rebased on top of -next, dropping changes that cover the DMA address
  MSB registers

This series is meant as an example on how to use macros and range cases
to shorten the MediaTek audio frontend drivers. The drivers have large
tables describing the registers and register fields for every supported
audio DMA interface. (Some are actually skipped!) There's a lot of
duplication which can be eliminated using macros. This should serve as
a reference for the MT8196 AFE driver that I had commented on.

The three patches tackle separate tables in the driver. The remaining
one that could be tackled is the list of DAIs; but that one has more
differences between each entry, so I haven't done it yet.

Please take a look.


Thanks
ChenYu


Chen-Yu Tsai (3):
  ASoC: mediatek: mt8183-afe-pcm: Shorten memif_data table using macros
  ASoC: mediatek: mt8183-afe-pcm: Shorten irq_data table using macros
  ASoC: mediatek: mt8183-afe-pcm: shorten mt8183_is_volatile_reg()

 sound/soc/mediatek/mt8183/mt8183-afe-pcm.c | 571 +++++----------------
 1 file changed, 127 insertions(+), 444 deletions(-)

-- 
2.49.0.1045.g170613ef41-goog



From wenst at chromium.org  Thu May 15 00:38:21 2025
From: wenst at chromium.org (Chen-Yu Tsai)
Date: Thu, 15 May 2025 15:38:21 +0800
Subject: [PATCH v2 1/3] ASoC: mediatek: mt8183-afe-pcm: Shorten memif_data table using macros
In-Reply-To: <20250515073825.4155297-1-wenst@chromium.org>
References: <20250515073825.4155297-1-wenst@chromium.org>
Message-ID: <20250515073825.4155297-2-wenst@chromium.org>

The memif_data table describes all the supported PCM channels for the
audio frontend. Most of the fields are either the same or can be derived
from the interface's name. This results in a very long table (in source
code) that can be shortened with macros.

Do just that. Some "convenience" macros were added to cover non-existent
register fields that would otherwise require multiple layers of macros
to handle.

Signed-off-by: Chen-Yu Tsai <wenst at chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
---
Changes since v1:
- Rebased onto -next, dropping bits for DMA address MSB registers
---
 sound/soc/mediatek/mt8183/mt8183-afe-pcm.c | 243 +++++----------------
 1 file changed, 54 insertions(+), 189 deletions(-)

diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
index d083b4bf0f95..a4bed8e335d8 100644
--- a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
+++ b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
@@ -424,196 +424,61 @@ static const struct snd_soc_component_driver mt8183_afe_pcm_dai_component = {
 	.name = "mt8183-afe-pcm-dai",
 };
 
+#define MT8183_MEMIF_BASE(_id, _en_reg, _fs_reg, _mono_reg)    \
+	[MT8183_MEMIF_##_id] = { \
+		.name = #_id,				\
+		.id = MT8183_MEMIF_##_id,		\
+		.reg_ofs_base = AFE_##_id##_BASE,	\
+		.reg_ofs_cur = AFE_##_id##_CUR,		\
+		.reg_ofs_end = AFE_##_id##_END,		\
+		.fs_reg = (_fs_reg),			\
+		.fs_shift = _id##_MODE_SFT,		\
+		.fs_maskbit = _id##_MODE_MASK,		\
+		.mono_reg = (_mono_reg),		\
+		.mono_shift = _id##_DATA_SFT,		\
+		.enable_reg = (_en_reg),		\
+		.enable_shift = _id##_ON_SFT,		\
+		.hd_reg = AFE_MEMIF_HD_MODE,		\
+		.hd_align_reg = AFE_MEMIF_HDALIGN,	\
+		.hd_shift = _id##_HD_SFT,		\
+		.hd_align_mshift = _id##_HD_ALIGN_SFT,	\
+		.agent_disable_reg = -1,		\
+		.agent_disable_shift = -1,		\
+		.msb_reg = -1,				\
+		.msb_shift = -1,			\
+	}
+
+#define MT8183_MEMIF(_id, _fs_reg, _mono_reg) \
+		MT8183_MEMIF_BASE(_id, AFE_DAC_CON0, _fs_reg, _mono_reg)
+
+/* For convenience with macros: missing register fields */
+#define MOD_DAI_DATA_SFT	-1
+#define HDMI_MODE_SFT		-1
+#define HDMI_MODE_MASK		-1
+#define HDMI_DATA_SFT		-1
+#define HDMI_ON_SFT		-1
+
+/* For convenience with macros: register name differences */
+#define AFE_VUL12_BASE		AFE_VUL_D2_BASE
+#define AFE_VUL12_CUR		AFE_VUL_D2_CUR
+#define AFE_VUL12_END		AFE_VUL_D2_END
+#define AWB2_HD_ALIGN_SFT	AWB2_ALIGN_SFT
+#define VUL12_DATA_SFT		VUL12_MONO_SFT
+#define AFE_HDMI_BASE		AFE_HDMI_OUT_BASE
+#define AFE_HDMI_CUR		AFE_HDMI_OUT_CUR
+#define AFE_HDMI_END		AFE_HDMI_OUT_END
+
 static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
-	[MT8183_MEMIF_DL1] = {
-		.name = "DL1",
-		.id = MT8183_MEMIF_DL1,
-		.reg_ofs_base = AFE_DL1_BASE,
-		.reg_ofs_cur = AFE_DL1_CUR,
-		.fs_reg = AFE_DAC_CON1,
-		.fs_shift = DL1_MODE_SFT,
-		.fs_maskbit = DL1_MODE_MASK,
-		.mono_reg = AFE_DAC_CON1,
-		.mono_shift = DL1_DATA_SFT,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = DL1_ON_SFT,
-		.hd_reg = AFE_MEMIF_HD_MODE,
-		.hd_align_reg = AFE_MEMIF_HDALIGN,
-		.hd_shift = DL1_HD_SFT,
-		.hd_align_mshift = DL1_HD_ALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-	},
-	[MT8183_MEMIF_DL2] = {
-		.name = "DL2",
-		.id = MT8183_MEMIF_DL2,
-		.reg_ofs_base = AFE_DL2_BASE,
-		.reg_ofs_cur = AFE_DL2_CUR,
-		.fs_reg = AFE_DAC_CON1,
-		.fs_shift = DL2_MODE_SFT,
-		.fs_maskbit = DL2_MODE_MASK,
-		.mono_reg = AFE_DAC_CON1,
-		.mono_shift = DL2_DATA_SFT,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = DL2_ON_SFT,
-		.hd_reg = AFE_MEMIF_HD_MODE,
-		.hd_align_reg = AFE_MEMIF_HDALIGN,
-		.hd_shift = DL2_HD_SFT,
-		.hd_align_mshift = DL2_HD_ALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-	},
-	[MT8183_MEMIF_DL3] = {
-		.name = "DL3",
-		.id = MT8183_MEMIF_DL3,
-		.reg_ofs_base = AFE_DL3_BASE,
-		.reg_ofs_cur = AFE_DL3_CUR,
-		.fs_reg = AFE_DAC_CON2,
-		.fs_shift = DL3_MODE_SFT,
-		.fs_maskbit = DL3_MODE_MASK,
-		.mono_reg = AFE_DAC_CON1,
-		.mono_shift = DL3_DATA_SFT,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = DL3_ON_SFT,
-		.hd_reg = AFE_MEMIF_HD_MODE,
-		.hd_align_reg = AFE_MEMIF_HDALIGN,
-		.hd_shift = DL3_HD_SFT,
-		.hd_align_mshift = DL3_HD_ALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-	},
-	[MT8183_MEMIF_VUL2] = {
-		.name = "VUL2",
-		.id = MT8183_MEMIF_VUL2,
-		.reg_ofs_base = AFE_VUL2_BASE,
-		.reg_ofs_cur = AFE_VUL2_CUR,
-		.fs_reg = AFE_DAC_CON2,
-		.fs_shift = VUL2_MODE_SFT,
-		.fs_maskbit = VUL2_MODE_MASK,
-		.mono_reg = AFE_DAC_CON2,
-		.mono_shift = VUL2_DATA_SFT,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = VUL2_ON_SFT,
-		.hd_reg = AFE_MEMIF_HD_MODE,
-		.hd_align_reg = AFE_MEMIF_HDALIGN,
-		.hd_shift = VUL2_HD_SFT,
-		.hd_align_mshift = VUL2_HD_ALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-	},
-	[MT8183_MEMIF_AWB] = {
-		.name = "AWB",
-		.id = MT8183_MEMIF_AWB,
-		.reg_ofs_base = AFE_AWB_BASE,
-		.reg_ofs_cur = AFE_AWB_CUR,
-		.fs_reg = AFE_DAC_CON1,
-		.fs_shift = AWB_MODE_SFT,
-		.fs_maskbit = AWB_MODE_MASK,
-		.mono_reg = AFE_DAC_CON1,
-		.mono_shift = AWB_DATA_SFT,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = AWB_ON_SFT,
-		.hd_reg = AFE_MEMIF_HD_MODE,
-		.hd_align_reg = AFE_MEMIF_HDALIGN,
-		.hd_shift = AWB_HD_SFT,
-		.hd_align_mshift = AWB_HD_ALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-	},
-	[MT8183_MEMIF_AWB2] = {
-		.name = "AWB2",
-		.id = MT8183_MEMIF_AWB2,
-		.reg_ofs_base = AFE_AWB2_BASE,
-		.reg_ofs_cur = AFE_AWB2_CUR,
-		.fs_reg = AFE_DAC_CON2,
-		.fs_shift = AWB2_MODE_SFT,
-		.fs_maskbit = AWB2_MODE_MASK,
-		.mono_reg = AFE_DAC_CON2,
-		.mono_shift = AWB2_DATA_SFT,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = AWB2_ON_SFT,
-		.hd_reg = AFE_MEMIF_HD_MODE,
-		.hd_align_reg = AFE_MEMIF_HDALIGN,
-		.hd_shift = AWB2_HD_SFT,
-		.hd_align_mshift = AWB2_ALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-	},
-	[MT8183_MEMIF_VUL12] = {
-		.name = "VUL12",
-		.id = MT8183_MEMIF_VUL12,
-		.reg_ofs_base = AFE_VUL_D2_BASE,
-		.reg_ofs_cur = AFE_VUL_D2_CUR,
-		.fs_reg = AFE_DAC_CON0,
-		.fs_shift = VUL12_MODE_SFT,
-		.fs_maskbit = VUL12_MODE_MASK,
-		.mono_reg = AFE_DAC_CON0,
-		.mono_shift = VUL12_MONO_SFT,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = VUL12_ON_SFT,
-		.hd_reg = AFE_MEMIF_HD_MODE,
-		.hd_align_reg = AFE_MEMIF_HDALIGN,
-		.hd_shift = VUL12_HD_SFT,
-		.hd_align_mshift = VUL12_HD_ALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-	},
-	[MT8183_MEMIF_MOD_DAI] = {
-		.name = "MOD_DAI",
-		.id = MT8183_MEMIF_MOD_DAI,
-		.reg_ofs_base = AFE_MOD_DAI_BASE,
-		.reg_ofs_cur = AFE_MOD_DAI_CUR,
-		.fs_reg = AFE_DAC_CON1,
-		.fs_shift = MOD_DAI_MODE_SFT,
-		.fs_maskbit = MOD_DAI_MODE_MASK,
-		.mono_reg = -1,
-		.mono_shift = 0,
-		.enable_reg = AFE_DAC_CON0,
-		.enable_shift = MOD_DAI_ON_SFT,
-		.hd_reg = AFE_MEMIF_HD_MODE,
-		.hd_align_reg = AFE_MEMIF_HDALIGN,
-		.hd_shift = MOD_DAI_HD_SFT,
-		.hd_align_mshift = MOD_DAI_HD_ALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-	},
-	[MT8183_MEMIF_HDMI] = {
-		.name = "HDMI",
-		.id = MT8183_MEMIF_HDMI,
-		.reg_ofs_base = AFE_HDMI_OUT_BASE,
-		.reg_ofs_cur = AFE_HDMI_OUT_CUR,
-		.fs_reg = -1,
-		.fs_shift = -1,
-		.fs_maskbit = -1,
-		.mono_reg = -1,
-		.mono_shift = -1,
-		.enable_reg = -1,	/* control in tdm for sync start */
-		.enable_shift = -1,
-		.hd_reg = AFE_MEMIF_HD_MODE,
-		.hd_align_reg = AFE_MEMIF_HDALIGN,
-		.hd_shift = HDMI_HD_SFT,
-		.hd_align_mshift = HDMI_HD_ALIGN_SFT,
-		.agent_disable_reg = -1,
-		.agent_disable_shift = -1,
-		.msb_reg = -1,
-		.msb_shift = -1,
-	},
+	MT8183_MEMIF(DL1, AFE_DAC_CON1, AFE_DAC_CON1),
+	MT8183_MEMIF(DL2, AFE_DAC_CON1, AFE_DAC_CON1),
+	MT8183_MEMIF(DL3, AFE_DAC_CON2, AFE_DAC_CON1),
+	MT8183_MEMIF(VUL2, AFE_DAC_CON2, AFE_DAC_CON2),
+	MT8183_MEMIF(AWB, AFE_DAC_CON1, AFE_DAC_CON1),
+	MT8183_MEMIF(AWB2, AFE_DAC_CON2, AFE_DAC_CON2),
+	MT8183_MEMIF(VUL12, AFE_DAC_CON0, AFE_DAC_CON0),
+	MT8183_MEMIF(MOD_DAI, AFE_DAC_CON1, -1),
+	/* enable control in tdm for sync start */
+	MT8183_MEMIF_BASE(HDMI, -1, -1, -1),
 };
 
 static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = {
-- 
2.49.0.1045.g170613ef41-goog



From wenst at chromium.org  Thu May 15 00:38:22 2025
From: wenst at chromium.org (Chen-Yu Tsai)
Date: Thu, 15 May 2025 15:38:22 +0800
Subject: [PATCH v2 2/3] ASoC: mediatek: mt8183-afe-pcm: Shorten irq_data table using macros
In-Reply-To: <20250515073825.4155297-1-wenst@chromium.org>
References: <20250515073825.4155297-1-wenst@chromium.org>
Message-ID: <20250515073825.4155297-3-wenst@chromium.org>

The irq_data table describes all the supported interrupts for the audio
frontend. The parameters are either the same or can be derived from the
interrupt number. This results in a very long table (in source code)
that can be shortened with macros.

Do just that.

Signed-off-by: Chen-Yu Tsai <wenst at chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
---
 sound/soc/mediatek/mt8183/mt8183-afe-pcm.c | 176 ++++-----------------
 1 file changed, 33 insertions(+), 143 deletions(-)

diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
index a4bed8e335d8..fe315224a259 100644
--- a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
+++ b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
@@ -481,150 +481,40 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
 	MT8183_MEMIF_BASE(HDMI, -1, -1, -1),
 };
 
+#define MT8183_AFE_IRQ_BASE(_id, _fs_reg, _fs_shift, _fs_maskbit)	\
+	[MT8183_IRQ_##_id] = {	\
+		.id = MT8183_IRQ_##_id,			\
+		.irq_cnt_reg = AFE_IRQ_MCU_CNT##_id,	\
+		.irq_cnt_shift = 0,			\
+		.irq_cnt_maskbit = 0x3ffff,		\
+		.irq_fs_reg = _fs_reg,			\
+		.irq_fs_shift = _fs_shift,		\
+		.irq_fs_maskbit = _fs_maskbit,		\
+		.irq_en_reg = AFE_IRQ_MCU_CON0,		\
+		.irq_en_shift = IRQ##_id##_MCU_ON_SFT,	\
+		.irq_clr_reg = AFE_IRQ_MCU_CLR,		\
+		.irq_clr_shift = IRQ##_id##_MCU_CLR_SFT,	\
+	}
+
+#define MT8183_AFE_IRQ(_id) \
+	MT8183_AFE_IRQ_BASE(_id, AFE_IRQ_MCU_CON1 + _id / 8 * 4,	\
+			    IRQ##_id##_MCU_MODE_SFT,	\
+			    IRQ##_id##_MCU_MODE_MASK)
+
+#define MT8183_AFE_IRQ_NOFS(_id) MT8183_AFE_IRQ_BASE(_id, -1, -1, -1)
+
 static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = {
-	[MT8183_IRQ_0] = {
-		.id = MT8183_IRQ_0,
-		.irq_cnt_reg = AFE_IRQ_MCU_CNT0,
-		.irq_cnt_shift = 0,
-		.irq_cnt_maskbit = 0x3ffff,
-		.irq_fs_reg = AFE_IRQ_MCU_CON1,
-		.irq_fs_shift = IRQ0_MCU_MODE_SFT,
-		.irq_fs_maskbit = IRQ0_MCU_MODE_MASK,
-		.irq_en_reg = AFE_IRQ_MCU_CON0,
-		.irq_en_shift = IRQ0_MCU_ON_SFT,
-		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-		.irq_clr_shift = IRQ0_MCU_CLR_SFT,
-	},
-	[MT8183_IRQ_1] = {
-		.id = MT8183_IRQ_1,
-		.irq_cnt_reg = AFE_IRQ_MCU_CNT1,
-		.irq_cnt_shift = 0,
-		.irq_cnt_maskbit = 0x3ffff,
-		.irq_fs_reg = AFE_IRQ_MCU_CON1,
-		.irq_fs_shift = IRQ1_MCU_MODE_SFT,
-		.irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
-		.irq_en_reg = AFE_IRQ_MCU_CON0,
-		.irq_en_shift = IRQ1_MCU_ON_SFT,
-		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-		.irq_clr_shift = IRQ1_MCU_CLR_SFT,
-	},
-	[MT8183_IRQ_2] = {
-		.id = MT8183_IRQ_2,
-		.irq_cnt_reg = AFE_IRQ_MCU_CNT2,
-		.irq_cnt_shift = 0,
-		.irq_cnt_maskbit = 0x3ffff,
-		.irq_fs_reg = AFE_IRQ_MCU_CON1,
-		.irq_fs_shift = IRQ2_MCU_MODE_SFT,
-		.irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
-		.irq_en_reg = AFE_IRQ_MCU_CON0,
-		.irq_en_shift = IRQ2_MCU_ON_SFT,
-		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-		.irq_clr_shift = IRQ2_MCU_CLR_SFT,
-	},
-	[MT8183_IRQ_3] = {
-		.id = MT8183_IRQ_3,
-		.irq_cnt_reg = AFE_IRQ_MCU_CNT3,
-		.irq_cnt_shift = 0,
-		.irq_cnt_maskbit = 0x3ffff,
-		.irq_fs_reg = AFE_IRQ_MCU_CON1,
-		.irq_fs_shift = IRQ3_MCU_MODE_SFT,
-		.irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
-		.irq_en_reg = AFE_IRQ_MCU_CON0,
-		.irq_en_shift = IRQ3_MCU_ON_SFT,
-		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-		.irq_clr_shift = IRQ3_MCU_CLR_SFT,
-	},
-	[MT8183_IRQ_4] = {
-		.id = MT8183_IRQ_4,
-		.irq_cnt_reg = AFE_IRQ_MCU_CNT4,
-		.irq_cnt_shift = 0,
-		.irq_cnt_maskbit = 0x3ffff,
-		.irq_fs_reg = AFE_IRQ_MCU_CON1,
-		.irq_fs_shift = IRQ4_MCU_MODE_SFT,
-		.irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
-		.irq_en_reg = AFE_IRQ_MCU_CON0,
-		.irq_en_shift = IRQ4_MCU_ON_SFT,
-		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-		.irq_clr_shift = IRQ4_MCU_CLR_SFT,
-	},
-	[MT8183_IRQ_5] = {
-		.id = MT8183_IRQ_5,
-		.irq_cnt_reg = AFE_IRQ_MCU_CNT5,
-		.irq_cnt_shift = 0,
-		.irq_cnt_maskbit = 0x3ffff,
-		.irq_fs_reg = AFE_IRQ_MCU_CON1,
-		.irq_fs_shift = IRQ5_MCU_MODE_SFT,
-		.irq_fs_maskbit = IRQ5_MCU_MODE_MASK,
-		.irq_en_reg = AFE_IRQ_MCU_CON0,
-		.irq_en_shift = IRQ5_MCU_ON_SFT,
-		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-		.irq_clr_shift = IRQ5_MCU_CLR_SFT,
-	},
-	[MT8183_IRQ_6] = {
-		.id = MT8183_IRQ_6,
-		.irq_cnt_reg = AFE_IRQ_MCU_CNT6,
-		.irq_cnt_shift = 0,
-		.irq_cnt_maskbit = 0x3ffff,
-		.irq_fs_reg = AFE_IRQ_MCU_CON1,
-		.irq_fs_shift = IRQ6_MCU_MODE_SFT,
-		.irq_fs_maskbit = IRQ6_MCU_MODE_MASK,
-		.irq_en_reg = AFE_IRQ_MCU_CON0,
-		.irq_en_shift = IRQ6_MCU_ON_SFT,
-		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-		.irq_clr_shift = IRQ6_MCU_CLR_SFT,
-	},
-	[MT8183_IRQ_7] = {
-		.id = MT8183_IRQ_7,
-		.irq_cnt_reg = AFE_IRQ_MCU_CNT7,
-		.irq_cnt_shift = 0,
-		.irq_cnt_maskbit = 0x3ffff,
-		.irq_fs_reg = AFE_IRQ_MCU_CON1,
-		.irq_fs_shift = IRQ7_MCU_MODE_SFT,
-		.irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
-		.irq_en_reg = AFE_IRQ_MCU_CON0,
-		.irq_en_shift = IRQ7_MCU_ON_SFT,
-		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-		.irq_clr_shift = IRQ7_MCU_CLR_SFT,
-	},
-	[MT8183_IRQ_8] = {
-		.id = MT8183_IRQ_8,
-		.irq_cnt_reg = AFE_IRQ_MCU_CNT8,
-		.irq_cnt_shift = 0,
-		.irq_cnt_maskbit = 0x3ffff,
-		.irq_fs_reg = -1,
-		.irq_fs_shift = -1,
-		.irq_fs_maskbit = -1,
-		.irq_en_reg = AFE_IRQ_MCU_CON0,
-		.irq_en_shift = IRQ8_MCU_ON_SFT,
-		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-		.irq_clr_shift = IRQ8_MCU_CLR_SFT,
-	},
-	[MT8183_IRQ_11] = {
-		.id = MT8183_IRQ_11,
-		.irq_cnt_reg = AFE_IRQ_MCU_CNT11,
-		.irq_cnt_shift = 0,
-		.irq_cnt_maskbit = 0x3ffff,
-		.irq_fs_reg = AFE_IRQ_MCU_CON2,
-		.irq_fs_shift = IRQ11_MCU_MODE_SFT,
-		.irq_fs_maskbit = IRQ11_MCU_MODE_MASK,
-		.irq_en_reg = AFE_IRQ_MCU_CON0,
-		.irq_en_shift = IRQ11_MCU_ON_SFT,
-		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-		.irq_clr_shift = IRQ11_MCU_CLR_SFT,
-	},
-	[MT8183_IRQ_12] = {
-		.id = MT8183_IRQ_12,
-		.irq_cnt_reg = AFE_IRQ_MCU_CNT12,
-		.irq_cnt_shift = 0,
-		.irq_cnt_maskbit = 0x3ffff,
-		.irq_fs_reg = AFE_IRQ_MCU_CON2,
-		.irq_fs_shift = IRQ12_MCU_MODE_SFT,
-		.irq_fs_maskbit = IRQ12_MCU_MODE_MASK,
-		.irq_en_reg = AFE_IRQ_MCU_CON0,
-		.irq_en_shift = IRQ12_MCU_ON_SFT,
-		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-		.irq_clr_shift = IRQ12_MCU_CLR_SFT,
-	},
+	MT8183_AFE_IRQ(0),
+	MT8183_AFE_IRQ(1),
+	MT8183_AFE_IRQ(2),
+	MT8183_AFE_IRQ(3),
+	MT8183_AFE_IRQ(4),
+	MT8183_AFE_IRQ(5),
+	MT8183_AFE_IRQ(6),
+	MT8183_AFE_IRQ(7),
+	MT8183_AFE_IRQ_NOFS(8),
+	MT8183_AFE_IRQ(11),
+	MT8183_AFE_IRQ(12),
 };
 
 static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg)
-- 
2.49.0.1045.g170613ef41-goog



From wenst at chromium.org  Thu May 15 00:38:23 2025
From: wenst at chromium.org (Chen-Yu Tsai)
Date: Thu, 15 May 2025 15:38:23 +0800
Subject: [PATCH v2 3/3] ASoC: mediatek: mt8183-afe-pcm: shorten mt8183_is_volatile_reg()
In-Reply-To: <20250515073825.4155297-1-wenst@chromium.org>
References: <20250515073825.4155297-1-wenst@chromium.org>
Message-ID: <20250515073825.4155297-4-wenst@chromium.org>

mt8183_is_volatile_reg() is a large switch-case block that lists out
every register that is volatile. Since many pairs of registers have
consecutive addresses, the cases can be compressed down with the
ellipsis, i.e. GCC extension "case ranges" [1] to cover more addresses
in one case, shortening the source code.

This is not completely the same, since the addresses are 4-byte aligned,
and using the case ranges feature adds all unaligned addresses in
between. In practice this doesn't matter since the unaligned addresses
are blocked by the regmap core. This also ends up compiling slightly
smaller with a reduction of 128 bytes in the text section.

[1] https://gcc.gnu.org/onlinedocs/gcc/Case-Ranges.html

Signed-off-by: Chen-Yu Tsai <wenst at chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
---
 sound/soc/mediatek/mt8183/mt8183-afe-pcm.c | 152 ++++++---------------
 1 file changed, 40 insertions(+), 112 deletions(-)

diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
index fe315224a259..e8884354995c 100644
--- a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
+++ b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
@@ -522,86 +522,46 @@ static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg)
 	/* these auto-gen reg has read-only bit, so put it as volatile */
 	/* volatile reg cannot be cached, so cannot be set when power off */
 	switch (reg) {
-	case AUDIO_TOP_CON0:	/* reg bit controlled by CCF */
-	case AUDIO_TOP_CON1:	/* reg bit controlled by CCF */
+	case AUDIO_TOP_CON0 ... AUDIO_TOP_CON1:	/* reg bit controlled by CCF */
 	case AUDIO_TOP_CON3:
-	case AFE_DL1_CUR:
-	case AFE_DL1_END:
-	case AFE_DL2_CUR:
-	case AFE_DL2_END:
-	case AFE_AWB_END:
-	case AFE_AWB_CUR:
-	case AFE_VUL_END:
-	case AFE_VUL_CUR:
-	case AFE_MEMIF_MON0:
-	case AFE_MEMIF_MON1:
-	case AFE_MEMIF_MON2:
-	case AFE_MEMIF_MON3:
-	case AFE_MEMIF_MON4:
-	case AFE_MEMIF_MON5:
-	case AFE_MEMIF_MON6:
-	case AFE_MEMIF_MON7:
-	case AFE_MEMIF_MON8:
-	case AFE_MEMIF_MON9:
-	case AFE_ADDA_SRC_DEBUG_MON0:
-	case AFE_ADDA_SRC_DEBUG_MON1:
-	case AFE_ADDA_UL_SRC_MON0:
-	case AFE_ADDA_UL_SRC_MON1:
+	case AFE_DL1_CUR ... AFE_DL1_END:
+	case AFE_DL2_CUR ... AFE_DL2_END:
+	case AFE_AWB_END ... AFE_AWB_CUR:
+	case AFE_VUL_END ... AFE_VUL_CUR:
+	case AFE_MEMIF_MON0 ... AFE_MEMIF_MON9:
+	case AFE_ADDA_SRC_DEBUG_MON0 ... AFE_ADDA_SRC_DEBUG_MON1:
+	case AFE_ADDA_UL_SRC_MON0 ... AFE_ADDA_UL_SRC_MON1:
 	case AFE_SIDETONE_MON:
-	case AFE_SIDETONE_CON0:
-	case AFE_SIDETONE_COEFF:
+	case AFE_SIDETONE_CON0 ... AFE_SIDETONE_COEFF:
 	case AFE_BUS_MON0:
-	case AFE_MRGIF_MON0:
-	case AFE_MRGIF_MON1:
-	case AFE_MRGIF_MON2:
-	case AFE_I2S_MON:
+	case AFE_MRGIF_MON0 ... AFE_I2S_MON:
 	case AFE_DAC_MON:
-	case AFE_VUL2_END:
-	case AFE_VUL2_CUR:
-	case AFE_IRQ0_MCU_CNT_MON:
-	case AFE_IRQ6_MCU_CNT_MON:
-	case AFE_MOD_DAI_END:
-	case AFE_MOD_DAI_CUR:
-	case AFE_VUL_D2_END:
-	case AFE_VUL_D2_CUR:
-	case AFE_DL3_CUR:
-	case AFE_DL3_END:
+	case AFE_VUL2_END ... AFE_VUL2_CUR:
+	case AFE_IRQ0_MCU_CNT_MON ... AFE_IRQ6_MCU_CNT_MON:
+	case AFE_MOD_DAI_END ... AFE_MOD_DAI_CUR:
+	case AFE_VUL_D2_END ... AFE_VUL_D2_CUR:
+	case AFE_DL3_CUR ... AFE_DL3_END:
 	case AFE_HDMI_OUT_CON0:
-	case AFE_HDMI_OUT_CUR:
-	case AFE_HDMI_OUT_END:
-	case AFE_IRQ3_MCU_CNT_MON:
-	case AFE_IRQ4_MCU_CNT_MON:
-	case AFE_IRQ_MCU_STATUS:
-	case AFE_IRQ_MCU_CLR:
+	case AFE_HDMI_OUT_CUR ... AFE_HDMI_OUT_END:
+	case AFE_IRQ3_MCU_CNT_MON... AFE_IRQ4_MCU_CNT_MON:
+	case AFE_IRQ_MCU_STATUS ... AFE_IRQ_MCU_CLR:
 	case AFE_IRQ_MCU_MON2:
-	case AFE_IRQ1_MCU_CNT_MON:
-	case AFE_IRQ2_MCU_CNT_MON:
-	case AFE_IRQ1_MCU_EN_CNT_MON:
-	case AFE_IRQ5_MCU_CNT_MON:
+	case AFE_IRQ1_MCU_CNT_MON ... AFE_IRQ5_MCU_CNT_MON:
 	case AFE_IRQ7_MCU_CNT_MON:
 	case AFE_GAIN1_CUR:
 	case AFE_GAIN2_CUR:
 	case AFE_SRAM_DELSEL_CON0:
-	case AFE_SRAM_DELSEL_CON2:
-	case AFE_SRAM_DELSEL_CON3:
-	case AFE_ASRC_2CH_CON12:
-	case AFE_ASRC_2CH_CON13:
+	case AFE_SRAM_DELSEL_CON2 ... AFE_SRAM_DELSEL_CON3:
+	case AFE_ASRC_2CH_CON12 ... AFE_ASRC_2CH_CON13:
 	case PCM_INTF_CON2:
-	case FPGA_CFG0:
-	case FPGA_CFG1:
-	case FPGA_CFG2:
-	case FPGA_CFG3:
-	case AUDIO_TOP_DBG_MON0:
-	case AUDIO_TOP_DBG_MON1:
-	case AFE_IRQ8_MCU_CNT_MON:
-	case AFE_IRQ11_MCU_CNT_MON:
-	case AFE_IRQ12_MCU_CNT_MON:
+	case FPGA_CFG0 ... FPGA_CFG1:
+	case FPGA_CFG2 ... FPGA_CFG3:
+	case AUDIO_TOP_DBG_MON0 ... AUDIO_TOP_DBG_MON1:
+	case AFE_IRQ8_MCU_CNT_MON ... AFE_IRQ12_MCU_CNT_MON:
 	case AFE_CBIP_MON0:
-	case AFE_CBIP_SLV_MUX_MON0:
-	case AFE_CBIP_SLV_DECODER_MON0:
+	case AFE_CBIP_SLV_MUX_MON0 ... AFE_CBIP_SLV_DECODER_MON0:
 	case AFE_ADDA6_SRC_DEBUG_MON0:
-	case AFE_ADD6A_UL_SRC_MON0:
-	case AFE_ADDA6_UL_SRC_MON1:
+	case AFE_ADD6A_UL_SRC_MON0... AFE_ADDA6_UL_SRC_MON1:
 	case AFE_DL1_CUR_MSB:
 	case AFE_DL2_CUR_MSB:
 	case AFE_AWB_CUR_MSB:
@@ -611,55 +571,23 @@ static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg)
 	case AFE_VUL_D2_CUR_MSB:
 	case AFE_DL3_CUR_MSB:
 	case AFE_HDMI_OUT_CUR_MSB:
-	case AFE_AWB2_END:
-	case AFE_AWB2_CUR:
+	case AFE_AWB2_END ... AFE_AWB2_CUR:
 	case AFE_AWB2_CUR_MSB:
-	case AFE_ADDA_DL_SDM_FIFO_MON:
-	case AFE_ADDA_DL_SRC_LCH_MON:
-	case AFE_ADDA_DL_SRC_RCH_MON:
-	case AFE_ADDA_DL_SDM_OUT_MON:
-	case AFE_CONNSYS_I2S_MON:
-	case AFE_ASRC_2CH_CON0:
-	case AFE_ASRC_2CH_CON2:
-	case AFE_ASRC_2CH_CON3:
-	case AFE_ASRC_2CH_CON4:
-	case AFE_ASRC_2CH_CON5:
-	case AFE_ASRC_2CH_CON7:
-	case AFE_ASRC_2CH_CON8:
-	case AFE_MEMIF_MON12:
-	case AFE_MEMIF_MON13:
-	case AFE_MEMIF_MON14:
-	case AFE_MEMIF_MON15:
-	case AFE_MEMIF_MON16:
-	case AFE_MEMIF_MON17:
-	case AFE_MEMIF_MON18:
-	case AFE_MEMIF_MON19:
-	case AFE_MEMIF_MON20:
-	case AFE_MEMIF_MON21:
-	case AFE_MEMIF_MON22:
-	case AFE_MEMIF_MON23:
-	case AFE_MEMIF_MON24:
-	case AFE_ADDA_MTKAIF_MON0:
-	case AFE_ADDA_MTKAIF_MON1:
+	case AFE_ADDA_DL_SDM_FIFO_MON ... AFE_ADDA_DL_SDM_OUT_MON:
+	case AFE_CONNSYS_I2S_MON ... AFE_ASRC_2CH_CON0:
+	case AFE_ASRC_2CH_CON2 ... AFE_ASRC_2CH_CON5:
+	case AFE_ASRC_2CH_CON7 ... AFE_ASRC_2CH_CON8:
+	case AFE_MEMIF_MON12 ... AFE_MEMIF_MON24:
+	case AFE_ADDA_MTKAIF_MON0 ... AFE_ADDA_MTKAIF_MON1:
 	case AFE_AUD_PAD_TOP:
 	case AFE_GENERAL1_ASRC_2CH_CON0:
-	case AFE_GENERAL1_ASRC_2CH_CON2:
-	case AFE_GENERAL1_ASRC_2CH_CON3:
-	case AFE_GENERAL1_ASRC_2CH_CON4:
-	case AFE_GENERAL1_ASRC_2CH_CON5:
-	case AFE_GENERAL1_ASRC_2CH_CON7:
-	case AFE_GENERAL1_ASRC_2CH_CON8:
-	case AFE_GENERAL1_ASRC_2CH_CON12:
-	case AFE_GENERAL1_ASRC_2CH_CON13:
+	case AFE_GENERAL1_ASRC_2CH_CON2 ... AFE_GENERAL1_ASRC_2CH_CON5:
+	case AFE_GENERAL1_ASRC_2CH_CON7 ... AFE_GENERAL1_ASRC_2CH_CON8:
+	case AFE_GENERAL1_ASRC_2CH_CON12 ... AFE_GENERAL1_ASRC_2CH_CON13:
 	case AFE_GENERAL2_ASRC_2CH_CON0:
-	case AFE_GENERAL2_ASRC_2CH_CON2:
-	case AFE_GENERAL2_ASRC_2CH_CON3:
-	case AFE_GENERAL2_ASRC_2CH_CON4:
-	case AFE_GENERAL2_ASRC_2CH_CON5:
-	case AFE_GENERAL2_ASRC_2CH_CON7:
-	case AFE_GENERAL2_ASRC_2CH_CON8:
-	case AFE_GENERAL2_ASRC_2CH_CON12:
-	case AFE_GENERAL2_ASRC_2CH_CON13:
+	case AFE_GENERAL2_ASRC_2CH_CON2 ... AFE_GENERAL2_ASRC_2CH_CON5:
+	case AFE_GENERAL2_ASRC_2CH_CON7 ... AFE_GENERAL2_ASRC_2CH_CON8:
+	case AFE_GENERAL2_ASRC_2CH_CON12 ... AFE_GENERAL2_ASRC_2CH_CON13:
 		return true;
 	default:
 		return false;
-- 
2.49.0.1045.g170613ef41-goog



From broonie at kernel.org  Thu May 15 00:43:10 2025
From: broonie at kernel.org (Mark Brown)
Date: Thu, 15 May 2025 09:43:10 +0200
Subject: [PATCH] regulator: dt-bindings: mt6357: Drop fixed compatible
 requirement
In-Reply-To: <20250514-mt6357-regulator-fixed-compatibles-removal-bindings-v1-1-2421e9cc6cc7@collabora.com>
References: <20250514-mt6357-regulator-fixed-compatibles-removal-bindings-v1-1-2421e9cc6cc7@collabora.com>
Message-ID: <174729499095.280025.830867783307923858.b4-ty@kernel.org>

On Wed, 14 May 2025 08:36:06 -0400, N?colas F. R. A. Prado wrote:
> Some of the regulators on the MT6357 PMIC currently reference the
> fixed-regulator dt-binding, which enforces the presence of a
> regulator-fixed compatible. However since all regulators on the MT6357
> PMIC are handled by a single mt6357-regulator driver, probed through
> MFD, the compatibles don't serve any purpose. In fact they cause
> failures in the DT kselftest since they aren't probed by the fixed
> regulator driver as would be expected. Furthermore this is the only
> dt-binding in this family like this: mt6359-regulator and
> mt6358-regulator don't require those compatibles.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git for-next

Thanks!

[1/1] regulator: dt-bindings: mt6357: Drop fixed compatible requirement
      commit: 9cfdd7752ba5f8cc9b8191e8c9aeeec246241fa4

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark



From filip.ostrowski at profinix.pl  Thu May 15 01:05:22 2025
From: filip.ostrowski at profinix.pl (Filip Ostrowski)
Date: Thu, 15 May 2025 08:05:22 GMT
Subject: Prezentacja
Message-ID: <20250515084500-0.1.fl.5well.0.4qra8mvmj0@profinix.pl>

Dzie? dobry!

Czy m?g?bym przedstawi? rozwi?zanie, kt?re umo?liwia monitoring ka?dego auta w czasie rzeczywistym w tym jego pozycj?, zu?ycie paliwa i przebieg?

Dodatkowo nasze narz?dzie minimalizuje koszty utrzymania samochod?w, skraca czas przejazd?w, a tak?e umo?liwia tworzenie planu tras czy dostaw.

Z naszej wiedzy i do?wiadczenia korzysta ju? ponad 49 tys. Klient?w. Monitorujemy 809 000 pojazd?w na ca?ym ?wiecie, co jest nasz? najlepsz? wizyt?wk?.

Bardzo prosz? o e-maila zwrotnego, je?li mogliby?my wsp?lnie om?wi? potencja? wykorzystania takiego rozwi?zania w Pa?stwa firmie.


Pozdrawiam
Filip Ostrowski


From angelogioacchino.delregno at collabora.com  Thu May 15 01:30:26 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Thu, 15 May 2025 10:30:26 +0200
Subject: [PATCH v3 03/10] ASoC: mediatek: mt8196: support audio clock
 control
In-Reply-To: <20250514081125.24475-4-darren.ye@mediatek.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
 <20250514081125.24475-4-darren.ye@mediatek.com>
Message-ID: <be75ac83-5421-4bb0-a28a-57be639f427c@collabora.com>

Il 14/05/25 10:11, Darren.Ye ha scritto:
> From: Darren Ye <darren.ye at mediatek.com>
> 
> Add audio clock wrapper and audio tuner control.
> 
> Signed-off-by: Darren Ye <darren.ye at mediatek.com>
> ---
>   sound/soc/mediatek/mt8196/mt8196-afe-clk.c    | 723 ++++++++++++++++++
>   sound/soc/mediatek/mt8196/mt8196-afe-clk.h    | 142 ++++
>   sound/soc/mediatek/mt8196/mt8196-audsys-clk.c | 252 ++++++
>   sound/soc/mediatek/mt8196/mt8196-audsys-clk.h |  14 +
>   .../soc/mediatek/mt8196/mt8196-audsys-clkid.h |  78 ++
>   5 files changed, 1209 insertions(+)
>   create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-clk.c
>   create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-clk.h
>   create mode 100644 sound/soc/mediatek/mt8196/mt8196-audsys-clk.c
>   create mode 100644 sound/soc/mediatek/mt8196/mt8196-audsys-clk.h
>   create mode 100644 sound/soc/mediatek/mt8196/mt8196-audsys-clkid.h
> 
> diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-clk.c b/sound/soc/mediatek/mt8196/mt8196-afe-clk.c
> new file mode 100644
> index 000000000000..83b5ee9d30ef
> --- /dev/null
> +++ b/sound/soc/mediatek/mt8196/mt8196-afe-clk.c
> @@ -0,0 +1,723 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + *  mt8196-afe-clk.c  --  Mediatek 8196 afe clock ctrl

mt8196-afe-clk.c - MediaTek MT8196 AFE Clock Control

> + *
> + *  Copyright (c) 2024 MediaTek Inc.
> + *  Author: Darren Ye <darren.ye at mediatek.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include "mt8196-afe-common.h"
> +#include "mt8196-audsys-clk.h"
> +#include "mt8196-afe-clk.h"
> +

..snip..

> +
> +static int mt8196_afe_disable_apll(struct mtk_base_afe *afe)
> +{
> +	struct mt8196_afe_private *afe_priv = afe->platform_priv;
> +	int ret = 0;
> +
> +	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
> +	if (ret)
> +		return ret;
> +
> +	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1]);
> +	if (ret)
> +		goto clk_ck_mux_aud1_err;
> +
> +	ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1],
> +					afe_priv->clk[MT8196_CLK_TOP_CLK26M]);
> +	if (ret)
> +		goto clk_ck_mux_aud1_parent_err;
> +
> +	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2]);
> +	if (ret)
> +		goto clk_ck_mux_aud2_err;
> +
> +	ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2],
> +					afe_priv->clk[MT8196_CLK_TOP_CLK26M]);
> +	if (ret)
> +		goto clk_ck_mux_aud2_parent_err;
> +
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1]);
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2]);
> +	mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
> +				  afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
> +	return 0;
> +
> +clk_ck_mux_aud2_parent_err:
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2]);
> +clk_ck_mux_aud2_err:
> +	mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1],
> +				  afe_priv->clk[MT8196_CLK_TOP_APLL1_CK]);
> +clk_ck_mux_aud1_parent_err:
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1]);
> +clk_ck_mux_aud1_err:
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
> +
> +	return ret;
> +}
> +
> +static void mt8196_afe_apll_init(struct mtk_base_afe *afe)
> +{
> +	struct mt8196_afe_private *afe_priv = afe->platform_priv;
> +

if (!afe_priv->vlp_clk) {
	dev_warn...
	return;
}

regmap_write......

> +	if (afe_priv->vlp_ck) {
> +		regmap_write(afe_priv->vlp_ck, VLP_APLL1_TUNER_CON0, VLP_APLL1_TUNER_CON0_VALUE);
> +		regmap_write(afe_priv->vlp_ck, VLP_APLL2_TUNER_CON0, VLP_APLL2_TUNER_CON0_VALUE);
> +	} else {
> +		dev_warn(afe->dev, "vlp_ck regmap is null ptr\n");
> +	}
> +}
> +
> +int mt8196_apll1_enable(struct mtk_base_afe *afe)
> +{
> +	struct mt8196_afe_private *afe_priv = afe->platform_priv;
> +	int ret;
> +
> +	/* setting for APLL */
> +	apll1_mux_setting(afe, true);
> +
> +	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL1]);
> +	if (ret)
> +		goto ERR_CLK_APLL1;
> +
> +	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER1]);
> +	if (ret)
> +		goto ERR_CLK_APLL1_TUNER;
> +
> +	/* sel 44.1kHz:1, apll_div:7, upper bound:3 */
> +	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
> +			   XTAL_EN_128FS_SEL_MASK_SFT | APLL_DIV_MASK_SFT | UPPER_BOUND_MASK_SFT,
> +			   (0x1 << XTAL_EN_128FS_SEL_SFT) | (7 << APLL_DIV_SFT) |
> +			   (3 << UPPER_BOUND_SFT));
> +
> +	/* apll1 freq tuner enable */
> +	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
> +			   FREQ_TUNER_EN_MASK_SFT,
> +			   0x1 << FREQ_TUNER_EN_SFT);
> +
> +	/* audio apll1 on */
> +	mt8196_afe_enable_top_cg(afe, MT8196_AUDIO_APLL1_EN_ON);
> +
> +	return 0;
> +
> +ERR_CLK_APLL1_TUNER:

lower case for labels please

> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER1]);
> +ERR_CLK_APLL1:

^^^^^^^^^

> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL1]);
> +	return ret;
> +}
> +
> +void mt8196_apll1_disable(struct mtk_base_afe *afe)
> +{
> +	struct mt8196_afe_private *afe_priv = afe->platform_priv;
> +
> +	/* audio apll1 off */
> +	mt8196_afe_disable_top_cg(afe, MT8196_AUDIO_APLL1_EN_ON);
> +
> +	/* apll1 freq tuner disable */
> +	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
> +			   FREQ_TUNER_EN_MASK_SFT,
> +			   0x0);
> +
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER1]);
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL1]);
> +	apll1_mux_setting(afe, false);
> +}
> +
> +int mt8196_apll2_enable(struct mtk_base_afe *afe)
> +{
> +	struct mt8196_afe_private *afe_priv = afe->platform_priv;
> +	int ret;
> +
> +	/* setting for APLL */
> +	apll2_mux_setting(afe, true);
> +
> +	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL2]);
> +	if (ret)
> +		goto ERR_CLK_APLL2;
> +
> +	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER2]);
> +	if (ret)
> +		goto ERR_CLK_APLL2_TUNER;
> +
> +	/* sel 48kHz: 2, apll_div: 7, upper bound: 3*/
> +	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
> +			   XTAL_EN_128FS_SEL_MASK_SFT | APLL_DIV_MASK_SFT | UPPER_BOUND_MASK_SFT,
> +			   (0x2 << XTAL_EN_128FS_SEL_SFT) | (7 << APLL_DIV_SFT) |
> +			   (3 << UPPER_BOUND_SFT));
> +
> +	/* apll2 freq tuner enable */
> +	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
> +			   FREQ_TUNER_EN_MASK_SFT,
> +			   0x1 << FREQ_TUNER_EN_SFT);
> +
> +	/* audio apll2 on */
> +	mt8196_afe_enable_top_cg(afe, MT8196_AUDIO_APLL2_EN_ON);
> +	return 0;
> +
> +ERR_CLK_APLL2_TUNER:

lower case for labels please

> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER2]);
> +ERR_CLK_APLL2:

ditto

> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL2]);
> +	return ret;
> +
> +	return 0;
> +}
> +
> +void mt8196_apll2_disable(struct mtk_base_afe *afe)
> +{
> +	struct mt8196_afe_private *afe_priv = afe->platform_priv;
> +
> +	/* audio apll2 off */
> +	mt8196_afe_disable_top_cg(afe, MT8196_AUDIO_APLL2_EN_ON);
> +
> +	/* apll2 freq tuner disable */
> +	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
> +			   FREQ_TUNER_EN_MASK_SFT,
> +			   0x0);
> +
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER2]);
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL2]);
> +	apll2_mux_setting(afe, false);
> +}
> +
> +int mt8196_get_apll_rate(struct mtk_base_afe *afe, int apll)
> +{
> +	struct mt8196_afe_private *afe_priv = afe->platform_priv;
> +	int clk_id = 0;
> +
> +	if (apll < MT8196_APLL1 || apll > MT8196_APLL2) {
> +		dev_warn(afe->dev, "invalid clk id\n");

("invalid clk id %d\n", clk_id)

...otherwise it makes no sense, as it gives no useful information.
Alternatively, just drop the print.

> +		return 0;
> +	}
> +
> +	if (apll == MT8196_APLL1)
> +		clk_id = MT8196_CLK_TOP_APLL1_CK;
> +	else
> +		clk_id = MT8196_CLK_TOP_APLL2_CK;
> +
> +	return clk_get_rate(afe_priv->clk[clk_id]);
> +}
> +
> +int mt8196_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
> +{
> +	return ((rate % 8000) == 0) ? MT8196_APLL2 : MT8196_APLL1;

	return (rate % 8000) ? MT8196_APLL1 : MT8196_APLL2;

> +}
> +
> +int mt8196_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
> +{
> +	if (strcmp(name, APLL1_W_NAME) == 0)
> +		return MT8196_APLL1;
> +	else
> +		return MT8196_APLL2;

	if (strcmp ....)
		return MT8196_APLL1;

	return MT8196_APLL2;

> +}
> +
> +/* mck */
> +struct mt8196_mck_div {
> +	int m_sel_id;
> +	int div_clk_id;
> +};
> +
> +static const struct mt8196_mck_div mck_div[MT8196_MCK_NUM] = {
> +	[MT8196_I2SIN0_MCK] = {
> +		.m_sel_id = MT8196_CLK_TOP_I2SIN0_M_SEL,
> +		.div_clk_id = MT8196_CLK_TOP_APLL12_DIV_I2SIN0,
> +	},
> +	[MT8196_I2SIN1_MCK] = {
> +		.m_sel_id = MT8196_CLK_TOP_I2SIN1_M_SEL,
> +		.div_clk_id = MT8196_CLK_TOP_APLL12_DIV_I2SIN1,
> +	},
> +	[MT8196_FMI2S_MCK] = {
> +		.m_sel_id = MT8196_CLK_TOP_FMI2S_M_SEL,
> +		.div_clk_id = MT8196_CLK_TOP_APLL12_DIV_FMI2S,
> +	},
> +	[MT8196_TDMOUT_MCK] = {
> +		.m_sel_id = MT8196_CLK_TOP_TDMOUT_M_SEL,
> +		.div_clk_id = MT8196_CLK_TOP_APLL12_DIV_TDMOUT_M,
> +	},
> +	[MT8196_TDMOUT_BCK] = {
> +		.m_sel_id = -1,
> +		.div_clk_id = MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B,
> +	},
> +};
> +
> +int mt8196_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
> +{
> +	struct mt8196_afe_private *afe_priv = afe->platform_priv;
> +	int apll = mt8196_get_apll_by_rate(afe, rate);
> +	int apll_clk_id = apll == MT8196_APLL1 ?
> +			  MT8196_CLK_TOP_MUX_AUD_1 : MT8196_CLK_TOP_MUX_AUD_2;
> +	int m_sel_id = 0;
> +	int div_clk_id = 0;
> +	int ret = 0;

this gives double initialzation of all m_sel_id, div_clk_id and ret as you are
initializing the first two immediately after the mck_id check, and ret later;
just go for

int m_sel_id, div_clk_id, ret;

or just

int ret;

> +
> +	dev_dbg(afe->dev, "mck_id: %d, rate: %d\n", mck_id, rate);
> +
> +	if (mck_id >= MT8196_MCK_NUM || mck_id < 0)
> +		return -EINVAL;
> +
> +	m_sel_id = mck_div[mck_id].m_sel_id;
> +	div_clk_id = mck_div[mck_id].div_clk_id;
> +
> +	/* select apll */
> +	if (m_sel_id >= 0) {

...because then I don't understand why don't you just use mck_div[mck_id] directly.

	if (mck_div[mck_id].m_sel_id >= 0) {

> +		ret = mt8196_afe_enable_clk(afe, afe_priv->clk[m_sel_id]);
> +		if (ret)
> +			return ret;
> +
> +		ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[m_sel_id],
> +						afe_priv->clk[apll_clk_id]);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	/* enable div, set rate */
> +	if (div_clk_id < 0) {

if (mck_div[mck_id].div_clk_id == MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B) {
	rate ...
} else if (mck_div[mck_id].div_clk_id < 0) {
	....
}


> +		dev_err(afe->dev, "invalid div_clk_id %d\n", div_clk_id);
> +		return -EINVAL;
> +	}
> +	if (div_clk_id == MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B)
> +		rate = rate * 16;
> +
> +	ret = mt8196_afe_enable_clk(afe, afe_priv->clk[div_clk_id]);
> +	if (ret)
> +		return ret;
> +
> +	ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[div_clk_id], rate);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +int mt8196_mck_disable(struct mtk_base_afe *afe, int mck_id)
> +{
> +	struct mt8196_afe_private *afe_priv = afe->platform_priv;
> +	int m_sel_id = 0;
> +	int div_clk_id = 0;

Double init again....

> +
> +	dev_dbg(afe->dev, "mck_id: %d.\n", mck_id);
> +
> +	if (mck_id < 0) {
> +		dev_err(afe->dev, "mck_id = %d < 0\n", mck_id);
> +		return -EINVAL;
> +	}
> +
> +	m_sel_id = mck_div[mck_id].m_sel_id;
> +	div_clk_id = mck_div[mck_id].div_clk_id;
> +
> +	if (div_clk_id < 0) {
> +		dev_err(afe->dev, "div_clk_id = %d < 0\n",
> +			div_clk_id);
> +		return -EINVAL;
> +	}
> +
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[div_clk_id]);
> +
> +	if (m_sel_id >= 0)
> +		mt8196_afe_disable_clk(afe, afe_priv->clk[m_sel_id]);
> +
> +	return 0;
> +}
> +
> +int mt8196_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
> +{
> +	struct mt8196_afe_private *afe_priv = afe->platform_priv;
> +
> +	/* bus clock for AFE external access, like DRAM */
> +	mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_ADSP_SEL]);
> +
> +	/* bus clock for AFE internal access, like AFE SRAM */
> +	mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIOINTBUS]);
> +	mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIOINTBUS],
> +				  afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
> +	/* enable audio vlp clock source */
> +	mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
> +	mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
> +				  afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
> +
> +	/* AFE hw clock */
> +	/* IPM2.0: USE HOPPING & 26M */
> +	mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_AUDIO_HOPPING]);
> +	mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_AUDIO_F26M]);
> +	return 0;
> +}
> +
> +int mt8196_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
> +{
> +	struct mt8196_afe_private *afe_priv = afe->platform_priv;
> +
> +	/* IPM2.0: Use HOPPING & 26M */
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_AUDIO_HOPPING]);
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_AUDIO_F26M]);
> +	mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
> +				  afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
> +
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
> +	mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIOINTBUS],
> +				  afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIOINTBUS]);
> +	mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_ADSP_SEL]);
> +	return 0;
> +}
> +
> +int mt8196_afe_enable_main_clock(struct mtk_base_afe *afe)
> +{

Just directly call

	mt8196_afe_enable_top_cg(afe, MT8196_AUDIO_26M_EN_ON);

...and drop mt8196_afe_enable_afe_on()

> +	mt8196_afe_enable_afe_on(afe);
> +	return 0;
> +}
> +
> +int mt8196_afe_disable_main_clock(struct mtk_base_afe *afe)
> +{
> +	mt8196_afe_disable_afe_on(afe);

mt8196_afe_disable_top_cg(afe, MT8196_AUDIO_26M_EN_ON);


> +	return 0;
> +}
> +
> +int mt8196_init_clock(struct mtk_base_afe *afe)
> +{
> +	struct mt8196_afe_private *afe_priv = afe->platform_priv;
> +	int ret = 0;
> +	int i = 0;
> +
> +	ret = mt8196_audsys_clk_register(afe);
> +	if (ret) {
> +		dev_err(afe->dev, "register audsys clk fail %d\n", ret);
> +		return ret;
> +	}
> +
> +	afe_priv->clk = devm_kcalloc(afe->dev, MT8196_CLK_NUM, sizeof(*afe_priv->clk),
> +				     GFP_KERNEL);
> +	if (!afe_priv->clk)
> +		return -ENOMEM;
> +
> +	for (i = 0; i < MT8196_CLK_NUM; i++) {
> +		afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
> +		if (IS_ERR(afe_priv->clk[i])) {
> +			dev_err(afe->dev, "devm_clk_get %s fail\n", aud_clks[i]);
> +			return PTR_ERR(afe_priv->clk[i]);
> +		}
> +	}
> +
> +	afe_priv->vlp_ck = syscon_regmap_lookup_by_phandle(afe->dev->of_node,
> +							   "vlpcksys");
> +	if (IS_ERR(afe_priv->vlp_ck)) {
> +		dev_err(afe->dev, "Cannot find vlpcksys\n");
> +		return PTR_ERR(afe_priv->vlp_ck);
> +	}
> +
> +	mt8196_afe_apll_init(afe);
> +
> +	ret = mt8196_afe_disable_apll(afe);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-clk.h b/sound/soc/mediatek/mt8196/mt8196-afe-clk.h
> new file mode 100644
> index 000000000000..60f5e5a157d5
> --- /dev/null
> +++ b/sound/soc/mediatek/mt8196/mt8196-afe-clk.h
> @@ -0,0 +1,142 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * mt8196-afe-clk.h  --  Mediatek 8196 afe clock ctrl definition

mt8196-afe-clk.h - MediaTek MT8195 AFE Clock Control definitions

> + *
> + * Copyright (c) 2024 MediaTek Inc.
> + *  Author: Darren Ye <darren.ye at mediatek.com>
> + */
> +

..snip..

> diff --git a/sound/soc/mediatek/mt8196/mt8196-audsys-clk.c b/sound/soc/mediatek/mt8196/mt8196-audsys-clk.c
> new file mode 100644
> index 000000000000..aa40f02698ac
> --- /dev/null
> +++ b/sound/soc/mediatek/mt8196/mt8196-audsys-clk.c
> @@ -0,0 +1,252 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * mt8196-audsys-clk.c  --  MediaTek 8196 audsys clock control
> + *
> + * Copyright (c) 2025 MediaTek Inc.
> + * Author: Darren Ye <darren.ye at mediatek.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include "mt8196-afe-common.h"
> +#include "mt8196-audsys-clk.h"
> +#include "mt8196-audsys-clkid.h"
> +#include "mt8196-reg.h"
> +
..snip..


> +};
> +
> +static void mt8196_audsys_clk_unregister(void *data)
> +{
> +	struct mtk_base_afe *afe = data;
> +	struct mt8196_afe_private *afe_priv = afe->platform_priv;
> +	struct clk *clk;
> +	struct clk_lookup *cl;
> +	int i;
> +
> +	if (!afe_priv)
> +		return;
> +
> +	for (i = 0; i < CLK_AFE_NR_CLK; i++) {
> +		cl = afe_priv->lookup[i];
> +		if (!cl)
> +			continue;
> +
> +		clk = cl->clk;
> +		clk_unregister_gate(clk);
> +
> +		clkdev_drop(cl);
> +	}
> +}
> +
> +int mt8196_audsys_clk_register(struct mtk_base_afe *afe)
> +{
> +	struct mt8196_afe_private *afe_priv = afe->platform_priv;
> +	struct clk *clk;
> +	struct clk_lookup *cl;
> +	int i;
> +
> +	afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AFE_NR_CLK,
> +					sizeof(*afe_priv->lookup),
> +					GFP_KERNEL);
> +
> +	if (!afe_priv->lookup)
> +		return -ENOMEM;
> +
> +	for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
> +		const struct afe_gate *gate = &aud_clks[i];
> +
> +		clk = clk_register_gate(afe->dev, gate->name, gate->parent_name,
> +					gate->flags, afe->base_addr + gate->reg,
> +					gate->bit, gate->cg_flags, NULL);
> +
> +		if (IS_ERR(clk)) {
> +			dev_err(afe->dev, "Failed to register clk %s: %ld\n",
> +				gate->name, PTR_ERR(clk));
> +			continue;
> +		}
> +

All of the above, until...

> +		/* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */
> +		cl = kzalloc(sizeof(*cl), GFP_KERNEL);
> +		if (!cl)
> +			return -ENOMEM;
> +
> +		cl->clk = clk;
> +		cl->con_id = gate->name;
> +		cl->dev_id = dev_name(afe->dev);
> +		cl->clk_hw = NULL;
> +		clkdev_add(cl);


...here, can be simplified with a single call to

clk_register_clkdev(clk, gate->name, dev_name(afe->dev))

or alternatively, you could simplify it even more:


static void mt8196_audsys_clk_unregister(void *data)
{
	/* nothing to do here, remove this function */
}

int mt8196_audsys_clk_register(struct mtk_base_afe *afe)
{
	struct mt8196_afe_private *afe_priv = afe->platform_priv;
	int i, ret;

	for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
		const struct afe_gate *gate = &aud_clks[i];
		struct clk_hw *hw;

		hw = devm_clk_hw_register_gate(afe->dev, gate->name, gate->parent_name,
					       gate->flags, afe->base_addr + gate->reg,
					       gate->bit, gate->cg_flags, NULL);
		if (IS_ERR(clk)) {
			dev_err(afe->dev, "Failed to register clk %s: %ld\n",
				gate->name, PTR_ERR(clk));
			continue;
		}

		ret = devm_clk_hw_register_clkdev(afe->dev, hw, gate->name, dev_name(afe->dev));
		if (ret)
			return ret;
	}

	return 0;
}



> +
> +		afe_priv->lookup[i] = cl;
> +	}
> +
> +	return devm_add_action_or_reset(afe->dev, mt8196_audsys_clk_unregister, afe);
> +}

Cheers,
Angelo


From wenst at chromium.org  Thu May 15 01:50:33 2025
From: wenst at chromium.org (Chen-Yu Tsai)
Date: Thu, 15 May 2025 16:50:33 +0800
Subject: [PATCH v3 03/10] ASoC: mediatek: mt8196: support audio clock control
In-Reply-To: <be75ac83-5421-4bb0-a28a-57be639f427c@collabora.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
 <20250514081125.24475-4-darren.ye@mediatek.com> <be75ac83-5421-4bb0-a28a-57be639f427c@collabora.com>
Message-ID: <CAGXv+5Hj358gOBomY=KdwYojgpwxFP-tiM38Z18b63ie=922mg@mail.gmail.com>

On Thu, May 15, 2025 at 4:40?PM AngeloGioacchino Del Regno
<angelogioacchino.delregno at collabora.com> wrote:
>
> Il 14/05/25 10:11, Darren.Ye ha scritto:
> > From: Darren Ye <darren.ye at mediatek.com>
> >
> > Add audio clock wrapper and audio tuner control.
> >
> > Signed-off-by: Darren Ye <darren.ye at mediatek.com>
> > ---
> >   sound/soc/mediatek/mt8196/mt8196-afe-clk.c    | 723 ++++++++++++++++++
> >   sound/soc/mediatek/mt8196/mt8196-afe-clk.h    | 142 ++++
> >   sound/soc/mediatek/mt8196/mt8196-audsys-clk.c | 252 ++++++
> >   sound/soc/mediatek/mt8196/mt8196-audsys-clk.h |  14 +
> >   .../soc/mediatek/mt8196/mt8196-audsys-clkid.h |  78 ++
> >   5 files changed, 1209 insertions(+)
> >   create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-clk.c
> >   create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-clk.h
> >   create mode 100644 sound/soc/mediatek/mt8196/mt8196-audsys-clk.c
> >   create mode 100644 sound/soc/mediatek/mt8196/mt8196-audsys-clk.h
> >   create mode 100644 sound/soc/mediatek/mt8196/mt8196-audsys-clkid.h
> >
> > diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-clk.c b/sound/soc/mediatek/mt8196/mt8196-afe-clk.c
> > new file mode 100644
> > index 000000000000..83b5ee9d30ef
> > --- /dev/null
> > +++ b/sound/soc/mediatek/mt8196/mt8196-afe-clk.c
> > @@ -0,0 +1,723 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + *  mt8196-afe-clk.c  --  Mediatek 8196 afe clock ctrl
>
> mt8196-afe-clk.c - MediaTek MT8196 AFE Clock Control
>
> > + *
> > + *  Copyright (c) 2024 MediaTek Inc.
> > + *  Author: Darren Ye <darren.ye at mediatek.com>
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/regmap.h>
> > +#include <linux/mfd/syscon.h>
> > +#include "mt8196-afe-common.h"
> > +#include "mt8196-audsys-clk.h"
> > +#include "mt8196-afe-clk.h"
> > +
>
> ..snip..
>
> > +
> > +static int mt8196_afe_disable_apll(struct mtk_base_afe *afe)
> > +{
> > +     struct mt8196_afe_private *afe_priv = afe->platform_priv;
> > +     int ret = 0;
> > +
> > +     ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
> > +     if (ret)
> > +             return ret;
> > +
> > +     ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1]);
> > +     if (ret)
> > +             goto clk_ck_mux_aud1_err;
> > +
> > +     ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1],
> > +                                     afe_priv->clk[MT8196_CLK_TOP_CLK26M]);
> > +     if (ret)
> > +             goto clk_ck_mux_aud1_parent_err;
> > +
> > +     ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2]);
> > +     if (ret)
> > +             goto clk_ck_mux_aud2_err;
> > +
> > +     ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2],
> > +                                     afe_priv->clk[MT8196_CLK_TOP_CLK26M]);
> > +     if (ret)
> > +             goto clk_ck_mux_aud2_parent_err;
> > +
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1]);
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2]);
> > +     mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
> > +                               afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
> > +     return 0;
> > +
> > +clk_ck_mux_aud2_parent_err:
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_2]);
> > +clk_ck_mux_aud2_err:
> > +     mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1],
> > +                               afe_priv->clk[MT8196_CLK_TOP_APLL1_CK]);
> > +clk_ck_mux_aud1_parent_err:
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_MUX_AUD_1]);
> > +clk_ck_mux_aud1_err:
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
> > +
> > +     return ret;
> > +}
> > +
> > +static void mt8196_afe_apll_init(struct mtk_base_afe *afe)
> > +{
> > +     struct mt8196_afe_private *afe_priv = afe->platform_priv;
> > +
>
> if (!afe_priv->vlp_clk) {
>         dev_warn...
>         return;
> }
>
> regmap_write......
>
> > +     if (afe_priv->vlp_ck) {
> > +             regmap_write(afe_priv->vlp_ck, VLP_APLL1_TUNER_CON0, VLP_APLL1_TUNER_CON0_VALUE);
> > +             regmap_write(afe_priv->vlp_ck, VLP_APLL2_TUNER_CON0, VLP_APLL2_TUNER_CON0_VALUE);
> > +     } else {
> > +             dev_warn(afe->dev, "vlp_ck regmap is null ptr\n");
> > +     }
> > +}
> > +
> > +int mt8196_apll1_enable(struct mtk_base_afe *afe)
> > +{
> > +     struct mt8196_afe_private *afe_priv = afe->platform_priv;
> > +     int ret;
> > +
> > +     /* setting for APLL */
> > +     apll1_mux_setting(afe, true);
> > +
> > +     ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL1]);
> > +     if (ret)
> > +             goto ERR_CLK_APLL1;
> > +
> > +     ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER1]);
> > +     if (ret)
> > +             goto ERR_CLK_APLL1_TUNER;
> > +
> > +     /* sel 44.1kHz:1, apll_div:7, upper bound:3 */
> > +     regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
> > +                        XTAL_EN_128FS_SEL_MASK_SFT | APLL_DIV_MASK_SFT | UPPER_BOUND_MASK_SFT,
> > +                        (0x1 << XTAL_EN_128FS_SEL_SFT) | (7 << APLL_DIV_SFT) |
> > +                        (3 << UPPER_BOUND_SFT));
> > +
> > +     /* apll1 freq tuner enable */
> > +     regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
> > +                        FREQ_TUNER_EN_MASK_SFT,
> > +                        0x1 << FREQ_TUNER_EN_SFT);
> > +
> > +     /* audio apll1 on */
> > +     mt8196_afe_enable_top_cg(afe, MT8196_AUDIO_APLL1_EN_ON);
> > +
> > +     return 0;
> > +
> > +ERR_CLK_APLL1_TUNER:
>
> lower case for labels please
>
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER1]);
> > +ERR_CLK_APLL1:
>
> ^^^^^^^^^
>
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL1]);
> > +     return ret;
> > +}
> > +
> > +void mt8196_apll1_disable(struct mtk_base_afe *afe)
> > +{
> > +     struct mt8196_afe_private *afe_priv = afe->platform_priv;
> > +
> > +     /* audio apll1 off */
> > +     mt8196_afe_disable_top_cg(afe, MT8196_AUDIO_APLL1_EN_ON);
> > +
> > +     /* apll1 freq tuner disable */
> > +     regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
> > +                        FREQ_TUNER_EN_MASK_SFT,
> > +                        0x0);
> > +
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER1]);
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL1]);
> > +     apll1_mux_setting(afe, false);
> > +}
> > +
> > +int mt8196_apll2_enable(struct mtk_base_afe *afe)
> > +{
> > +     struct mt8196_afe_private *afe_priv = afe->platform_priv;
> > +     int ret;
> > +
> > +     /* setting for APLL */
> > +     apll2_mux_setting(afe, true);
> > +
> > +     ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL2]);
> > +     if (ret)
> > +             goto ERR_CLK_APLL2;
> > +
> > +     ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER2]);
> > +     if (ret)
> > +             goto ERR_CLK_APLL2_TUNER;
> > +
> > +     /* sel 48kHz: 2, apll_div: 7, upper bound: 3*/
> > +     regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
> > +                        XTAL_EN_128FS_SEL_MASK_SFT | APLL_DIV_MASK_SFT | UPPER_BOUND_MASK_SFT,
> > +                        (0x2 << XTAL_EN_128FS_SEL_SFT) | (7 << APLL_DIV_SFT) |
> > +                        (3 << UPPER_BOUND_SFT));
> > +
> > +     /* apll2 freq tuner enable */
> > +     regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
> > +                        FREQ_TUNER_EN_MASK_SFT,
> > +                        0x1 << FREQ_TUNER_EN_SFT);
> > +
> > +     /* audio apll2 on */
> > +     mt8196_afe_enable_top_cg(afe, MT8196_AUDIO_APLL2_EN_ON);
> > +     return 0;
> > +
> > +ERR_CLK_APLL2_TUNER:
>
> lower case for labels please
>
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER2]);
> > +ERR_CLK_APLL2:
>
> ditto
>
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL2]);
> > +     return ret;
> > +
> > +     return 0;
> > +}
> > +
> > +void mt8196_apll2_disable(struct mtk_base_afe *afe)
> > +{
> > +     struct mt8196_afe_private *afe_priv = afe->platform_priv;
> > +
> > +     /* audio apll2 off */
> > +     mt8196_afe_disable_top_cg(afe, MT8196_AUDIO_APLL2_EN_ON);
> > +
> > +     /* apll2 freq tuner disable */
> > +     regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
> > +                        FREQ_TUNER_EN_MASK_SFT,
> > +                        0x0);
> > +
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL_TUNER2]);
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_APLL2]);
> > +     apll2_mux_setting(afe, false);
> > +}
> > +
> > +int mt8196_get_apll_rate(struct mtk_base_afe *afe, int apll)
> > +{
> > +     struct mt8196_afe_private *afe_priv = afe->platform_priv;
> > +     int clk_id = 0;
> > +
> > +     if (apll < MT8196_APLL1 || apll > MT8196_APLL2) {
> > +             dev_warn(afe->dev, "invalid clk id\n");
>
> ("invalid clk id %d\n", clk_id)
>
> ...otherwise it makes no sense, as it gives no useful information.
> Alternatively, just drop the print.
>
> > +             return 0;
> > +     }
> > +
> > +     if (apll == MT8196_APLL1)
> > +             clk_id = MT8196_CLK_TOP_APLL1_CK;
> > +     else
> > +             clk_id = MT8196_CLK_TOP_APLL2_CK;
> > +
> > +     return clk_get_rate(afe_priv->clk[clk_id]);
> > +}
> > +
> > +int mt8196_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
> > +{
> > +     return ((rate % 8000) == 0) ? MT8196_APLL2 : MT8196_APLL1;
>
>         return (rate % 8000) ? MT8196_APLL1 : MT8196_APLL2;
>
> > +}
> > +
> > +int mt8196_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
> > +{
> > +     if (strcmp(name, APLL1_W_NAME) == 0)
> > +             return MT8196_APLL1;
> > +     else
> > +             return MT8196_APLL2;
>
>         if (strcmp ....)
>                 return MT8196_APLL1;
>
>         return MT8196_APLL2;
>
> > +}
> > +
> > +/* mck */
> > +struct mt8196_mck_div {
> > +     int m_sel_id;
> > +     int div_clk_id;
> > +};
> > +
> > +static const struct mt8196_mck_div mck_div[MT8196_MCK_NUM] = {
> > +     [MT8196_I2SIN0_MCK] = {
> > +             .m_sel_id = MT8196_CLK_TOP_I2SIN0_M_SEL,
> > +             .div_clk_id = MT8196_CLK_TOP_APLL12_DIV_I2SIN0,
> > +     },
> > +     [MT8196_I2SIN1_MCK] = {
> > +             .m_sel_id = MT8196_CLK_TOP_I2SIN1_M_SEL,
> > +             .div_clk_id = MT8196_CLK_TOP_APLL12_DIV_I2SIN1,
> > +     },
> > +     [MT8196_FMI2S_MCK] = {
> > +             .m_sel_id = MT8196_CLK_TOP_FMI2S_M_SEL,
> > +             .div_clk_id = MT8196_CLK_TOP_APLL12_DIV_FMI2S,
> > +     },
> > +     [MT8196_TDMOUT_MCK] = {
> > +             .m_sel_id = MT8196_CLK_TOP_TDMOUT_M_SEL,
> > +             .div_clk_id = MT8196_CLK_TOP_APLL12_DIV_TDMOUT_M,
> > +     },
> > +     [MT8196_TDMOUT_BCK] = {
> > +             .m_sel_id = -1,
> > +             .div_clk_id = MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B,
> > +     },
> > +};
> > +
> > +int mt8196_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
> > +{
> > +     struct mt8196_afe_private *afe_priv = afe->platform_priv;
> > +     int apll = mt8196_get_apll_by_rate(afe, rate);
> > +     int apll_clk_id = apll == MT8196_APLL1 ?
> > +                       MT8196_CLK_TOP_MUX_AUD_1 : MT8196_CLK_TOP_MUX_AUD_2;
> > +     int m_sel_id = 0;
> > +     int div_clk_id = 0;
> > +     int ret = 0;
>
> this gives double initialzation of all m_sel_id, div_clk_id and ret as you are
> initializing the first two immediately after the mck_id check, and ret later;
> just go for
>
> int m_sel_id, div_clk_id, ret;
>
> or just
>
> int ret;
>
> > +
> > +     dev_dbg(afe->dev, "mck_id: %d, rate: %d\n", mck_id, rate);
> > +
> > +     if (mck_id >= MT8196_MCK_NUM || mck_id < 0)
> > +             return -EINVAL;
> > +
> > +     m_sel_id = mck_div[mck_id].m_sel_id;
> > +     div_clk_id = mck_div[mck_id].div_clk_id;
> > +
> > +     /* select apll */
> > +     if (m_sel_id >= 0) {
>
> ...because then I don't understand why don't you just use mck_div[mck_id] directly.
>
>         if (mck_div[mck_id].m_sel_id >= 0) {
>
> > +             ret = mt8196_afe_enable_clk(afe, afe_priv->clk[m_sel_id]);
> > +             if (ret)
> > +                     return ret;
> > +
> > +             ret = mt8196_afe_set_clk_parent(afe, afe_priv->clk[m_sel_id],
> > +                                             afe_priv->clk[apll_clk_id]);
> > +             if (ret)
> > +                     return ret;
> > +     }
> > +
> > +     /* enable div, set rate */
> > +     if (div_clk_id < 0) {
>
> if (mck_div[mck_id].div_clk_id == MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B) {
>         rate ...
> } else if (mck_div[mck_id].div_clk_id < 0) {
>         ....
> }
>
>
> > +             dev_err(afe->dev, "invalid div_clk_id %d\n", div_clk_id);
> > +             return -EINVAL;
> > +     }
> > +     if (div_clk_id == MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B)
> > +             rate = rate * 16;
> > +
> > +     ret = mt8196_afe_enable_clk(afe, afe_priv->clk[div_clk_id]);
> > +     if (ret)
> > +             return ret;
> > +
> > +     ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[div_clk_id], rate);
> > +     if (ret)
> > +             return ret;
> > +
> > +     return 0;
> > +}
> > +
> > +int mt8196_mck_disable(struct mtk_base_afe *afe, int mck_id)
> > +{
> > +     struct mt8196_afe_private *afe_priv = afe->platform_priv;
> > +     int m_sel_id = 0;
> > +     int div_clk_id = 0;
>
> Double init again....
>
> > +
> > +     dev_dbg(afe->dev, "mck_id: %d.\n", mck_id);
> > +
> > +     if (mck_id < 0) {
> > +             dev_err(afe->dev, "mck_id = %d < 0\n", mck_id);
> > +             return -EINVAL;
> > +     }
> > +
> > +     m_sel_id = mck_div[mck_id].m_sel_id;
> > +     div_clk_id = mck_div[mck_id].div_clk_id;
> > +
> > +     if (div_clk_id < 0) {
> > +             dev_err(afe->dev, "div_clk_id = %d < 0\n",
> > +                     div_clk_id);
> > +             return -EINVAL;
> > +     }
> > +
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[div_clk_id]);
> > +
> > +     if (m_sel_id >= 0)
> > +             mt8196_afe_disable_clk(afe, afe_priv->clk[m_sel_id]);
> > +
> > +     return 0;
> > +}
> > +
> > +int mt8196_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
> > +{
> > +     struct mt8196_afe_private *afe_priv = afe->platform_priv;
> > +
> > +     /* bus clock for AFE external access, like DRAM */
> > +     mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_ADSP_SEL]);
> > +
> > +     /* bus clock for AFE internal access, like AFE SRAM */
> > +     mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIOINTBUS]);
> > +     mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIOINTBUS],
> > +                               afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
> > +     /* enable audio vlp clock source */
> > +     mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
> > +     mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
> > +                               afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
> > +
> > +     /* AFE hw clock */
> > +     /* IPM2.0: USE HOPPING & 26M */
> > +     mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_AUDIO_HOPPING]);
> > +     mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_AUDIO_F26M]);
> > +     return 0;
> > +}
> > +
> > +int mt8196_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
> > +{
> > +     struct mt8196_afe_private *afe_priv = afe->platform_priv;
> > +
> > +     /* IPM2.0: Use HOPPING & 26M */
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_AUDIO_HOPPING]);
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_AFE_AUDIO_F26M]);
> > +     mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
> > +                               afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
> > +
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
> > +     mt8196_afe_set_clk_parent(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIOINTBUS],
> > +                               afe_priv->clk[MT8196_CLK_VLP_CLK26M]);
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIOINTBUS]);
> > +     mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_ADSP_SEL]);
> > +     return 0;
> > +}
> > +
> > +int mt8196_afe_enable_main_clock(struct mtk_base_afe *afe)
> > +{
>
> Just directly call
>
>         mt8196_afe_enable_top_cg(afe, MT8196_AUDIO_26M_EN_ON);
>
> ...and drop mt8196_afe_enable_afe_on()
>
> > +     mt8196_afe_enable_afe_on(afe);
> > +     return 0;
> > +}
> > +
> > +int mt8196_afe_disable_main_clock(struct mtk_base_afe *afe)
> > +{
> > +     mt8196_afe_disable_afe_on(afe);
>
> mt8196_afe_disable_top_cg(afe, MT8196_AUDIO_26M_EN_ON);
>
>
> > +     return 0;
> > +}
> > +
> > +int mt8196_init_clock(struct mtk_base_afe *afe)
> > +{
> > +     struct mt8196_afe_private *afe_priv = afe->platform_priv;
> > +     int ret = 0;
> > +     int i = 0;
> > +
> > +     ret = mt8196_audsys_clk_register(afe);
> > +     if (ret) {
> > +             dev_err(afe->dev, "register audsys clk fail %d\n", ret);
> > +             return ret;
> > +     }
> > +
> > +     afe_priv->clk = devm_kcalloc(afe->dev, MT8196_CLK_NUM, sizeof(*afe_priv->clk),
> > +                                  GFP_KERNEL);
> > +     if (!afe_priv->clk)
> > +             return -ENOMEM;
> > +
> > +     for (i = 0; i < MT8196_CLK_NUM; i++) {
> > +             afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
> > +             if (IS_ERR(afe_priv->clk[i])) {
> > +                     dev_err(afe->dev, "devm_clk_get %s fail\n", aud_clks[i]);
> > +                     return PTR_ERR(afe_priv->clk[i]);
> > +             }
> > +     }
> > +
> > +     afe_priv->vlp_ck = syscon_regmap_lookup_by_phandle(afe->dev->of_node,
> > +                                                        "vlpcksys");
> > +     if (IS_ERR(afe_priv->vlp_ck)) {
> > +             dev_err(afe->dev, "Cannot find vlpcksys\n");
> > +             return PTR_ERR(afe_priv->vlp_ck);
> > +     }
> > +
> > +     mt8196_afe_apll_init(afe);
> > +
> > +     ret = mt8196_afe_disable_apll(afe);
> > +     if (ret)
> > +             return ret;
> > +
> > +     return 0;
> > +}
> > +
> > diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-clk.h b/sound/soc/mediatek/mt8196/mt8196-afe-clk.h
> > new file mode 100644
> > index 000000000000..60f5e5a157d5
> > --- /dev/null
> > +++ b/sound/soc/mediatek/mt8196/mt8196-afe-clk.h
> > @@ -0,0 +1,142 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * mt8196-afe-clk.h  --  Mediatek 8196 afe clock ctrl definition
>
> mt8196-afe-clk.h - MediaTek MT8195 AFE Clock Control definitions
>
> > + *
> > + * Copyright (c) 2024 MediaTek Inc.
> > + *  Author: Darren Ye <darren.ye at mediatek.com>
> > + */
> > +
>
> ..snip..
>
> > diff --git a/sound/soc/mediatek/mt8196/mt8196-audsys-clk.c b/sound/soc/mediatek/mt8196/mt8196-audsys-clk.c
> > new file mode 100644
> > index 000000000000..aa40f02698ac
> > --- /dev/null
> > +++ b/sound/soc/mediatek/mt8196/mt8196-audsys-clk.c
> > @@ -0,0 +1,252 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * mt8196-audsys-clk.c  --  MediaTek 8196 audsys clock control
> > + *
> > + * Copyright (c) 2025 MediaTek Inc.
> > + * Author: Darren Ye <darren.ye at mediatek.com>
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> > +#include <linux/clkdev.h>
> > +#include "mt8196-afe-common.h"
> > +#include "mt8196-audsys-clk.h"
> > +#include "mt8196-audsys-clkid.h"
> > +#include "mt8196-reg.h"
> > +
> ..snip..
>
>
> > +};
> > +
> > +static void mt8196_audsys_clk_unregister(void *data)
> > +{
> > +     struct mtk_base_afe *afe = data;
> > +     struct mt8196_afe_private *afe_priv = afe->platform_priv;
> > +     struct clk *clk;
> > +     struct clk_lookup *cl;
> > +     int i;
> > +
> > +     if (!afe_priv)
> > +             return;
> > +
> > +     for (i = 0; i < CLK_AFE_NR_CLK; i++) {
> > +             cl = afe_priv->lookup[i];
> > +             if (!cl)
> > +                     continue;
> > +
> > +             clk = cl->clk;
> > +             clk_unregister_gate(clk);
> > +
> > +             clkdev_drop(cl);
> > +     }
> > +}
> > +
> > +int mt8196_audsys_clk_register(struct mtk_base_afe *afe)
> > +{
> > +     struct mt8196_afe_private *afe_priv = afe->platform_priv;
> > +     struct clk *clk;
> > +     struct clk_lookup *cl;
> > +     int i;
> > +
> > +     afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AFE_NR_CLK,
> > +                                     sizeof(*afe_priv->lookup),
> > +                                     GFP_KERNEL);
> > +
> > +     if (!afe_priv->lookup)
> > +             return -ENOMEM;
> > +
> > +     for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
> > +             const struct afe_gate *gate = &aud_clks[i];
> > +
> > +             clk = clk_register_gate(afe->dev, gate->name, gate->parent_name,
> > +                                     gate->flags, afe->base_addr + gate->reg,
> > +                                     gate->bit, gate->cg_flags, NULL);
> > +
> > +             if (IS_ERR(clk)) {
> > +                     dev_err(afe->dev, "Failed to register clk %s: %ld\n",
> > +                             gate->name, PTR_ERR(clk));
> > +                     continue;
> > +             }
> > +
>
> All of the above, until...
>
> > +             /* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */
> > +             cl = kzalloc(sizeof(*cl), GFP_KERNEL);
> > +             if (!cl)
> > +                     return -ENOMEM;
> > +
> > +             cl->clk = clk;
> > +             cl->con_id = gate->name;
> > +             cl->dev_id = dev_name(afe->dev);
> > +             cl->clk_hw = NULL;
> > +             clkdev_add(cl);
>
>
> ...here, can be simplified with a single call to
>
> clk_register_clkdev(clk, gate->name, dev_name(afe->dev))
>
> or alternatively, you could simplify it even more:
>
>
> static void mt8196_audsys_clk_unregister(void *data)
> {
>         /* nothing to do here, remove this function */
> }
>
> int mt8196_audsys_clk_register(struct mtk_base_afe *afe)
> {
>         struct mt8196_afe_private *afe_priv = afe->platform_priv;
>         int i, ret;
>
>         for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
>                 const struct afe_gate *gate = &aud_clks[i];
>                 struct clk_hw *hw;
>
>                 hw = devm_clk_hw_register_gate(afe->dev, gate->name, gate->parent_name,
>                                                gate->flags, afe->base_addr + gate->reg,
>                                                gate->bit, gate->cg_flags, NULL);
>                 if (IS_ERR(clk)) {
>                         dev_err(afe->dev, "Failed to register clk %s: %ld\n",
>                                 gate->name, PTR_ERR(clk));
>                         continue;
>                 }
>
>                 ret = devm_clk_hw_register_clkdev(afe->dev, hw, gate->name, dev_name(afe->dev));
>                 if (ret)
>                         return ret;
>         }
>
>         return 0;
> }

There is no need to involve the clk subsystem. These are simply supply
gates, be them for power or clks, one per bit. Simply model them as ASoC
supply widgets, add appropriate routes for each so that the dependencies
are correct, and ASoC will deal with them for you. No code is needed,
just descriptions.

_That_ is why I asked for he audio clocks to be integrated into the
AFE driver.

ChenYu

> > +
> > +             afe_priv->lookup[i] = cl;
> > +     }
> > +
> > +     return devm_add_action_or_reset(afe->dev, mt8196_audsys_clk_unregister, afe);
> > +}
>
> Cheers,
> Angelo
>


From broonie at kernel.org  Thu May 15 01:54:56 2025
From: broonie at kernel.org (Mark Brown)
Date: Thu, 15 May 2025 10:54:56 +0200
Subject: [PATCH v3 03/10] ASoC: mediatek: mt8196: support audio clock
 control
In-Reply-To: <CAGXv+5Hj358gOBomY=KdwYojgpwxFP-tiM38Z18b63ie=922mg@mail.gmail.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
 <20250514081125.24475-4-darren.ye@mediatek.com>
 <be75ac83-5421-4bb0-a28a-57be639f427c@collabora.com>
 <CAGXv+5Hj358gOBomY=KdwYojgpwxFP-tiM38Z18b63ie=922mg@mail.gmail.com>
Message-ID: <aCWr4HDpEOr_jn3C@finisterre.sirena.org.uk>

On Thu, May 15, 2025 at 04:50:33PM +0800, Chen-Yu Tsai wrote:
> On Thu, May 15, 2025 at 4:40?PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno at collabora.com> wrote:
> >
> > Il 14/05/25 10:11, Darren.Ye ha scritto:
> > > From: Darren Ye <darren.ye at mediatek.com>
> > >
> > > Add audio clock wrapper and audio tuner control.

Please delete unneeded context from mails when replying.  Doing this
makes it much easier to find your reply in the message, helping ensure
it won't be missed by people scrolling through the irrelevant quoted
material.
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From Darren.Ye at mediatek.com  Thu May 15 02:31:35 2025
From: Darren.Ye at mediatek.com (=?utf-8?B?RGFycmVuIFllICjlj7bpo54p?=)
Date: Thu, 15 May 2025 09:31:35 +0000
Subject: [PATCH v3 03/10] ASoC: mediatek: mt8196: support audio clock
 control
In-Reply-To: <CAGXv+5Hj358gOBomY=KdwYojgpwxFP-tiM38Z18b63ie=922mg@mail.gmail.com>
References: <20250514081125.24475-1-darren.ye@mediatek.com>
	 <20250514081125.24475-4-darren.ye@mediatek.com>
	 <be75ac83-5421-4bb0-a28a-57be639f427c@collabora.com>
	 <CAGXv+5Hj358gOBomY=KdwYojgpwxFP-tiM38Z18b63ie=922mg@mail.gmail.com>
Message-ID: <5556933f34858b50e5077dee62d430fc9a37f74b.camel@mediatek.com>

On Thu, 2025-05-15 at 16:50 +0800, Chen-Yu Tsai wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On Thu, May 15, 2025 at 4:40?PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno at collabora.com> wrote:
> > 
> > Il 14/05/25 10:11, Darren.Ye ha scritto:
> > > From: Darren Ye <darren.ye at mediatek.com>
> > > 
> > > Add audio clock wrapper and audio tuner control.
> > > 
> > > Signed-off-by: Darren Ye <darren.ye at mediatek.com>
> > > ---
> > >   sound/soc/mediatek/mt8196/mt8196-afe-clk.c    | 723
> > > ++++++++++++++++++
> > >   sound/soc/mediatek/mt8196/mt8196-afe-clk.h    | 142 ++++
> > >   sound/soc/mediatek/mt8196/mt8196-audsys-clk.c | 252 ++++++
> > >   sound/soc/mediatek/mt8196/mt8196-audsys-clk.h |  14 +
> > >   .../soc/mediatek/mt8196/mt8196-audsys-clkid.h |  78 ++
> > >   5 files changed, 1209 insertions(+)
> > >   create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-clk.c
> > >   create mode 100644 sound/soc/mediatek/mt8196/mt8196-afe-clk.h
> > >   create mode 100644 sound/soc/mediatek/mt8196/mt8196-audsys-
> > > clk.c
> > >   create mode 100644 sound/soc/mediatek/mt8196/mt8196-audsys-
> > > clk.h
> > >   create mode 100644 sound/soc/mediatek/mt8196/mt8196-audsys-
> > > clkid.h
> > > 
> > > diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-clk.c
> > > b/sound/soc/mediatek/mt8196/mt8196-afe-clk.c
> > > new file mode 100644
> > > index 000000000000..83b5ee9d30ef
> > > --- /dev/null
> > > +++ b/sound/soc/mediatek/mt8196/mt8196-afe-clk.c
> > > @@ -0,0 +1,723 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + *  mt8196-afe-clk.c  --  Mediatek 8196 afe clock ctrl
> > 
> > mt8196-afe-clk.c - MediaTek MT8196 AFE Clock Control
> > 
> > > + *
> > > + *  Copyright (c) 2024 MediaTek Inc.
> > > + *  Author: Darren Ye <darren.ye at mediatek.com>
> > > + */
> > > +
> > > +#include <linux/clk.h>
> > > +#include <linux/regmap.h>
> > > +#include <linux/mfd/syscon.h>
> > > +#include "mt8196-afe-common.h"
> > > +#include "mt8196-audsys-clk.h"
> > > +#include "mt8196-afe-clk.h"
> > > +
> > 
> > > +int mt8196_audsys_clk_register(struct mtk_base_afe *afe)
> > > +{
> > > +     struct mt8196_afe_private *afe_priv = afe->platform_priv;
> > > +     struct clk *clk;
> > > +     struct clk_lookup *cl;
> > > +     int i;
> > > +
> > > +     afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AFE_NR_CLK,
> > > +                                     sizeof(*afe_priv->lookup),
> > > +                                     GFP_KERNEL);
> > > +
> > > +     if (!afe_priv->lookup)
> > > +             return -ENOMEM;
> > > +
> > > +     for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
> > > +             const struct afe_gate *gate = &aud_clks[i];
> > > +
> > > +             clk = clk_register_gate(afe->dev, gate->name, gate-
> > > >parent_name,
> > > +                                     gate->flags, afe->base_addr 
> > > + gate->reg,
> > > +                                     gate->bit, gate->cg_flags,
> > > NULL);
> > > +
> > > +             if (IS_ERR(clk)) {
> > > +                     dev_err(afe->dev, "Failed to register clk
> > > %s: %ld\n",
> > > +                             gate->name, PTR_ERR(clk));
> > > +                     continue;
> > > +             }
> > > +
> > 
> > All of the above, until...
> > 
> > > +             /* add clk_lookup for
> > > devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */
> > > +             cl = kzalloc(sizeof(*cl), GFP_KERNEL);
> > > +             if (!cl)
> > > +                     return -ENOMEM;
> > > +
> > > +             cl->clk = clk;
> > > +             cl->con_id = gate->name;
> > > +             cl->dev_id = dev_name(afe->dev);
> > > +             cl->clk_hw = NULL;
> > > +             clkdev_add(cl);
> > 
> > 
> > ...here, can be simplified with a single call to
> > 
> > clk_register_clkdev(clk, gate->name, dev_name(afe->dev))
> > 
> > or alternatively, you could simplify it even more:
> > 
> > 
> > static void mt8196_audsys_clk_unregister(void *data)
> > {
> >         /* nothing to do here, remove this function */
> > }
> > 
> > int mt8196_audsys_clk_register(struct mtk_base_afe *afe)
> > {
> >         struct mt8196_afe_private *afe_priv = afe->platform_priv;
> >         int i, ret;
> > 
> >         for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
> >                 const struct afe_gate *gate = &aud_clks[i];
> >                 struct clk_hw *hw;
> > 
> >                 hw = devm_clk_hw_register_gate(afe->dev, gate-
> > >name, gate->parent_name,
> >                                                gate->flags, afe-
> > >base_addr + gate->reg,
> >                                                gate->bit, gate-
> > >cg_flags, NULL);
> >                 if (IS_ERR(clk)) {
> >                         dev_err(afe->dev, "Failed to register clk
> > %s: %ld\n",
> >                                 gate->name, PTR_ERR(clk));
> >                         continue;
> >                 }
> > 
> >                 ret = devm_clk_hw_register_clkdev(afe->dev, hw,
> > gate->name, dev_name(afe->dev));
> >                 if (ret)
> >                         return ret;
> >         }
> > 
> >         return 0;
> > }
> 
> There is no need to involve the clk subsystem. These are simply
> supply
> gates, be them for power or clks, one per bit. Simply model them as
> ASoC
> supply widgets, add appropriate routes for each so that the
> dependencies
> are correct, and ASoC will deal with them for you. No code is needed,
> just descriptions.
> 
> _That_ is why I asked for he audio clocks to be integrated into the
> AFE driver.
> 
> ChenYu
> 

OK, I misunderstood. The next version will use widgets and route to
control the afe clk gate.

Best regards,
Darren

> > > +
> > > +             afe_priv->lookup[i] = cl;
> > > +     }
> > > +
> > > +     return devm_add_action_or_reset(afe->dev,
> > > mt8196_audsys_clk_unregister, afe);
> > > +}
> > 
> > Cheers,
> > Angelo
> > 

From paul-pl.chen at mediatek.com  Thu May 15 02:34:12 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:12 +0800
Subject: [PATCH v3 00/17] Add MediaTek SoC DRM support for MT8196
Message-ID: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>

From: Paul-pl Chen <paul-pl.chen at mediatek.com>

This patch series adds support for the MediaTek MT8196 SoC's display
subsystem in the DRM driver.

Changes in v3:

- [PATCH v3 06/17] 
  Refine runtime PM, top clocks and async controls for MMSYS 
- [PATCH v3 08/17]
  Refactor SOF settings by adding mtk_mutex_get_output_comp_sof() and
  extracting SOF logic from mtk_mutex_add_comp() 
  and mtk_mutex_remove_comp()
- [PATCH v3 10/17]
  Export OVL format definitions and format 
  conversion API
- [PATCH v3 11/17]
  Export OVL ignore pixel alpha logic
- [PATCH v3 12/17] 
  Refactor exdma_config setup to reduce complexity 
  and consolidate duplicate settings in exdma_layer_config()
- [PATCH v3 13/17]
  Refine blender's layer_config driver for improved efficiency
- [PATCH v3 14/17] Refine outproc driver: use readl() and writel() to 
  replace mtk_ddp_write_mask() for normal mode settings
- [PATCH v3 15/17]
  Refine ovlsys_adaptor driver:Use path instead of ovl_adaptor_comp for 
  searching component type. Improve efficiency of config, start, stop, 
  and layer_config functions
- [PATCH v3 16/17] 
  Refine mtk_find_possible_crtcs() function

Changes in v2:
- add support for MT8196's new hardware components (EXDMA, BLENDER, 
  OUTPROC) following the previous MTK OVL software architecture.
- reuse mtk_ovl drivers in MediaTek DRM display to support the new 
  MT8196 SoC.
- implement support for multiple mmsys instances within a single 
  mediatek-drm driver, improving flexibility and scalability.
- refactor existing components (mutex, OVL) to accommodate the new 
  architecture and improve code reusability.
- update component matching, binding logic, and data structures to 
  support the new multi-mmsys design.
Nancy Lin (10):
  dt-bindings: soc: mediatek: add mutex yaml for MT8196
  soc: mediatek: Add runtime PM and top clocks and async controls for
    MMSYS
  soc: mediatek: add mmsys support for MT8196
  soc: mediatek: mutex: add mutex support for MT8196
  drm/mediatek: Export OVL formats definitions and format conversion API
  drm/mediatek: drm/mediatek: Export OVL ignore pixel alpha function
  drm/mediatek: add EXDMA support for MT8196
  drm/mediatek: add OUTPROC support for MT8196
  drm/mediatek: add ovlsys_adaptor support for MT8196
  drm/mediatek: Add support for MT8196 multiple mmsys

Paul-pl Chen (7):
  dt-bindings: display: mediatek: add EXDMA yaml for MT8196
  dt-bindings: display: mediatek: add BLENDER yaml for MT8196
  dt-bindings: display: mediatek: add OUTPROC yaml for MT8196
  soc: mediatek: mutex: Reused the switch case for SOF ID
  soc: mediatek: mutex: refactor SOF settings for output components
  drm/mediatek: add BLENDER support for MT8196
  drm/mediatek: Add support for multiple mmsys in the one mediatek-drm
    driver

 .../display/mediatek/mediatek,blender.yaml    |  47 ++
 .../display/mediatek/mediatek,outproc.yaml    |  54 ++
 .../bindings/dma/mediatek,exdma.yaml          |  68 ++
 .../bindings/soc/mediatek/mediatek,mutex.yaml |   2 +
 drivers/gpu/drm/mediatek/Makefile             |   4 +
 drivers/gpu/drm/mediatek/mtk_crtc.c           | 342 ++++++--
 drivers/gpu/drm/mediatek/mtk_crtc.h           |   6 +-
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c       | 136 +++-
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h       |   6 +
 drivers/gpu/drm/mediatek/mtk_disp_blender.c   | 264 +++++++
 drivers/gpu/drm/mediatek/mtk_disp_blender.h   |  10 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |  67 ++
 drivers/gpu/drm/mediatek/mtk_disp_exdma.c     | 349 +++++++++
 drivers/gpu/drm/mediatek/mtk_disp_outproc.c   | 240 ++++++
 drivers/gpu/drm/mediatek/mtk_disp_outproc.h   |  22 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c       | 238 +++---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.h       |  29 +
 .../drm/mediatek/mtk_disp_ovlsys_adaptor.c    | 729 ++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        | 277 +++++--
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |  27 +-
 drivers/soc/mediatek/mt8196-mmsys.h           | 396 ++++++++++
 drivers/soc/mediatek/mtk-mmsys.c              | 206 ++++-
 drivers/soc/mediatek/mtk-mmsys.h              |  18 +
 drivers/soc/mediatek/mtk-mutex.c              | 257 ++++--
 include/linux/soc/mediatek/mtk-mmsys.h        |  60 ++
 include/linux/soc/mediatek/mtk-mutex.h        |   4 +
 26 files changed, 3555 insertions(+), 303 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,blender.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml
 create mode 100644 Documentation/devicetree/bindings/dma/mediatek,exdma.yaml
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_blender.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_blender.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_exdma.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_outproc.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_outproc.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovlsys_adaptor.c
 create mode 100644 drivers/soc/mediatek/mt8196-mmsys.h

-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:13 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:13 +0800
Subject: [PATCH v3 01/17] dt-bindings: soc: mediatek: add mutex yaml for MT8196
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-2-paul-pl.chen@mediatek.com>

From: Nancy Lin <nancy.lin at mediatek.com>

Add compatible string to support mutex for MT8196.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 .../devicetree/bindings/soc/mediatek/mediatek,mutex.yaml        | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
index a10326a9683d..1be4e139a8b5 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
@@ -36,6 +36,7 @@ properties:
       - mediatek,mt8188-vpp-mutex
       - mediatek,mt8192-disp-mutex
       - mediatek,mt8195-disp-mutex
+      - mediatek,mt8196-disp-mutex
       - mediatek,mt8195-vpp-mutex
       - mediatek,mt8365-disp-mutex
 
@@ -87,6 +88,7 @@ allOf:
               - mediatek,mt8186-mdp3-mutex
               - mediatek,mt8192-disp-mutex
               - mediatek,mt8195-disp-mutex
+              - mediatek,mt8196-disp-mutex
     then:
       required:
         - clocks
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:14 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:14 +0800
Subject: [PATCH v3 02/17] dt-bindings: display: mediatek: add EXDMA yaml for MT8196
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-3-paul-pl.chen@mediatek.com>

From: Paul-pl Chen <paul-pl.chen at mediatek.com>

Add mediatek,exdma.yaml to support EXDMA for MT8196.
The MediaTek display overlap extended DMA engine, namely
OVL_EXDMA or EXDMA, primarily functions as a DMA engine
for reading data from DRAM with various DRAM footprints
and data formats.

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 .../bindings/dma/mediatek,exdma.yaml          | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/mediatek,exdma.yaml

diff --git a/Documentation/devicetree/bindings/dma/mediatek,exdma.yaml b/Documentation/devicetree/bindings/dma/mediatek,exdma.yaml
new file mode 100644
index 000000000000..eabf0cfc839e
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mediatek,exdma.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/mediatek,exdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek display overlap extended DMA engine
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu at kernel.org>
+  - Philipp Zabel <p.zabel at pengutronix.de>
+
+description:
+  The MediaTek display overlap extended DMA engine, namely OVL_EXDMA or EXDMA,
+  primarily functions as a DMA engine for reading data from DRAM with various
+  DRAM footprints and data formats. For input sources in certain color formats
+  and color domains, OVL_EXDMA also includes a color transfer function
+  to process pixels into a consistent color domain.
+
+properties:
+  compatible:
+    const: mediatek,mt8196-exdma
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  mediatek,larb:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: |
+      A phandle to the local arbiters node in the current SoCs.
+      Refer to bindings/memory-controllers/mediatek,smi-larb.yaml.
+
+  iommus:
+    maxItems: 1
+
+  '#dma-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - power-domains
+  - mediatek,larb
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        exdma: dma-controller at 32850000 {
+            compatible = "mediatek,mt8196-exdma";
+            reg = <0 0x32850000 0 0x1000>;
+            clocks = <&ovlsys_config_clk 13>;
+            power-domains = <&hfrpsys 12>;
+            iommus = <&mm_smmu 144>;
+            #dma-cells = <1>;
+        };
+    };
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:15 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:15 +0800
Subject: [PATCH v3 03/17] dt-bindings: display: mediatek: add BLENDER yaml for MT8196
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-4-paul-pl.chen@mediatek.com>

From: Paul-pl Chen <paul-pl.chen at mediatek.com>

Add mediatek,blender.yaml to support BLENDER for MT8196.
MediaTek display overlap blender, namely OVL_BLENDER or BLENDER,
executes the alpha blending function for overlapping layers
from different sources.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 .../display/mediatek/mediatek,blender.yaml    | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,blender.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,blender.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,blender.yaml
new file mode 100644
index 000000000000..4b85f6ac40a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,blender.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,blender.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Display Overlap Blender
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu at kernel.org>
+  - Philipp Zabel <p.zabel at pengutronix.de>
+
+description:
+  MediaTek display overlap blender, namely OVL_BLENDER or BLENDER,
+  executes the alpha blending function for overlapping layers
+  from different sources. This is the primary function of the
+  overlapping system.
+
+properties:
+  compatible:
+    const: mediatek,mt8196-blender
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        blender0: blender at 328d0000 {
+            compatible = "mediatek,mt8196-blender";
+            reg = <0 0x328d0000 0 0x1000>;
+            clocks = <&ovlsys_config_clk 29>;
+        };
+    };
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:16 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:16 +0800
Subject: [PATCH v3 04/17] dt-bindings: display: mediatek: add OUTPROC yaml for MT8196
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-5-paul-pl.chen@mediatek.com>

From: Paul-pl Chen <paul-pl.chen at mediatek.com>

Add mediate,outproc.yaml to support OUTPROC for MT8196.
MediaTek display overlap output processor, namely OVL_OUTPROC
or OUTPROC,handles the post-stage of pixel processing in the
overlapping procedure.

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 .../display/mediatek/mediatek,outproc.yaml    | 54 +++++++++++++++++++
 1 file changed, 54 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml
new file mode 100644
index 000000000000..1292e394faaa
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,outproc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek display overlap output processor
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu at kernel.org>
+  - Philipp Zabel <p.zabel at pengutronix.de>
+
+description:
+  MediaTek display overlap output processor, namely OVL_OUTPROC or OUTPROC,
+  handles the post-stage of pixel processing in the overlapping procedure.
+  OVL_OUTPROC manages pixels for gamma correction and ensures that pixel
+  values are within the correct range.
+
+properties:
+  compatible:
+    const: mediatek,mt8196-outproc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        outproc0: outproc at 32970000 {
+            compatible = "mediatek,mt8196-outproc";
+            reg = <0 0x32970000 0 0x1000>;
+            clocks = <&ovlsys_config_clk 49>;
+            interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH 0>;
+        };
+    };
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:18 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:18 +0800
Subject: [PATCH v3 06/17] soc: mediatek: add mmsys support for MT8196
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-7-paul-pl.chen@mediatek.com>

From: Nancy Lin <nancy.lin at mediatek.com>

Add driver data for MT8196 and add the routing table for each mmsys.

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 drivers/soc/mediatek/mt8196-mmsys.h    | 396 +++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c       |  54 ++++
 include/linux/soc/mediatek/mtk-mmsys.h |  52 ++++
 3 files changed, 502 insertions(+)
 create mode 100644 drivers/soc/mediatek/mt8196-mmsys.h

diff --git a/drivers/soc/mediatek/mt8196-mmsys.h b/drivers/soc/mediatek/mt8196-mmsys.h
new file mode 100644
index 000000000000..63b14b446d08
--- /dev/null
+++ b/drivers/soc/mediatek/mt8196-mmsys.h
@@ -0,0 +1,396 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Nancy Lin <nancy.lin at mediatek.com>
+ */
+
+#ifndef __SOC_MEDIATEK_MT8196_MMSYS_H
+#define __SOC_MEDIATEK_MT8196_MMSYS_H
+
+/* DISPSYS1 */
+#define MT8196_COMP_OUT_CB6_MOUT_EN			0xd30
+#define MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB0		BIT(0)
+#define MT8196_COMP_OUT_CB7_MOUT_EN			0xd38
+#define MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB1		BIT(1)
+#define MT8196_COMP_OUT_CB8_MOUT_EN			0xd40
+#define MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB2		BIT(2)
+#define MT8196_MERGE_OUT_CB0_MOUT_EN			0xdcc
+#define MT8196_DISP_COMP_OUT_CB_TO_DVO0				BIT(9)
+#define MT8196_MERGE_OUT_CB1_MOUT_EN			0xdd4
+#define MT8196_MERGE_OUT_CB2_MOUT_EN			0xddc
+#define MT8196_DISP_COMP_OUT_CB_TO_DSI0				BIT(0)
+#define MT8196_DISP_COMP_OUT_CB_TO_DP_INTF0			BIT(10)
+#define MT8196_DISP_COMP_OUT_CB_TO_DP_INTF1			BIT(11)
+#define MT8196_SPLITTER_IN_CB1_MOUT_EN			0xeac
+#define MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB9		BIT(5)
+#define MT8196_SPLITTER_IN_CB2_MOUT_EN			0xeb4
+#define MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB10		BIT(6)
+#define MT8196_SPLITTER_IN_CB3_MOUT_EN			0xebc
+#define MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB11		BIT(7)
+#define MT8196_SPLITTER_OUT_CB9_MOUT_EN			0xf64
+#define MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB6		BIT(10)
+#define MT8196_SPLITTER_OUT_CB10_MOUT_EN		0xf6c
+#define MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB7		BIT(11)
+#define MT8196_SPLITTER_OUT_CB11_MOUT_EN		0xf74
+#define MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB8		BIT(12)
+#define MT8196_OVL_RSZ_IN_CB2_MOUT_EN			0xf70
+#define MT8196_DISP_OVL_EXDMA2_1_TO_OVL_EXDMA_OUT_CB3		BIT(1)
+
+/* OVLSYS */
+#define MT8196_OVL_BLENDER_OUT_CB4_MOUT_EN		0xe10
+#define MT8196_OVL_BLENDER_OUT_CB8_MOUT_EN		0xe20
+#define MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC0		BIT(0)
+#define MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC1		BIT(1)
+#define MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC2		BIT(2)
+#define MT8196_OVL_EXDMA_OUT_CB2_MOUT_EN		0xe60
+#define MT8196_OVL_EXDMA_OUT_CB3_MOUT_EN		0xe68
+#define MT8196_OVL_EXDMA_OUT_CB4_MOUT_EN		0xe70
+#define MT8196_OVL_EXDMA_OUT_CB5_MOUT_EN		0xe78
+#define MT8196_OVL_EXDMA_OUT_CB6_MOUT_EN		0xe80
+#define MT8196_OVL_EXDMA_OUT_CB7_MOUT_EN		0xe88
+#define MT8196_OVL_EXDMA_OUT_CB8_MOUT_EN		0xe90
+#define MT8196_OVL_EXDMA_OUT_CB9_MOUT_EN		0xe98
+#define MT8196_OVL_EXDMA_OUT_CB10_MOUT_EN		0xea0
+#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER1		BIT(2)
+#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER2		BIT(3)
+#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER3		BIT(4)
+#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER4		BIT(5)
+#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER5		BIT(6)
+#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER6		BIT(7)
+#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER7		BIT(8)
+#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER8		BIT(9)
+#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER9		BIT(10)
+#define MT8196_OVL_OUTPROC_OUT_CB0_MOUT_EN		0xf10
+#define MT8196_OVL_OUTPROC_OUT_CB1_MOUT_EN		0xf14
+#define MT8196_OVL_OUTPROC_OUT_CB2_MOUT_EN		0xf18
+#define MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY5		BIT(0)
+#define MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY6		BIT(1)
+#define MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY7		BIT(2)
+
+/* DISPSYS0 */
+#define MT8196_PANEL_COMP_OUT_CB1_MOUT_EN		0xd84
+#define MT8196_DISP_TO_DLO_RELAY1				BIT(1)
+#define MT8196_PANEL_COMP_OUT_CB2_MOUT_EN		0xd88
+#define MT8196_DISP_TO_DLO_RELAY2				BIT(2)
+#define MT8196_PANEL_COMP_OUT_CB3_MOUT_EN		0xd8c
+#define MT8196_DISP_TO_DLO_RELAY3				BIT(3)
+#define MT8196_PQ_IN_CB0_MOUT_EN			0xdd0
+#define MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6				BIT(2)
+
+#define MT8196_PQ_IN_CB1_MOUT_EN			0xdd4
+#define MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7				BIT(3)
+#define MT8196_PQ_IN_CB8_MOUT_EN			0xdf0
+#define MT8196_PQ_IN_CB8_TO_PQ_OUT_CB_8				BIT(4)
+#define MT8196_PQ_OUT_CB6_MOUT_EN			0xe54
+#define MT8196_PQ_OUT_CB6_TO_PANEL0_COMP_OUT_CB1		BIT(1)
+#define MT8196_PQ_OUT_CB7_MOUT_EN			0xe58
+#define MT8196_PQ_OUT_CB7_TO_PANEL0_COMP_OUT_CB2		BIT(2)
+#define MT8196_PQ_OUT_CB8_MOUT_EN			0xe5c
+#define MT8196_PQ_OUT_CB8_TO_PANEL0_COMP_OUT_CB3		BIT(3)
+
+/* OVLSYS config */
+#define MT8196_OVL_INT_MERGE				0x008
+#define MT8196_OVL_DL_OUT_RELAY5_SIZE			0x29c
+#define MT8196_OVL_DL_OUT_RELAY6_SIZE			0x2a0
+#define MT8196_OVLSYS_GCE_EVENT_SEL			0x408
+#define MT8196_OVLSYS_BYPASS_MUX_SHADOW			0xca0
+#define MT8196_OVLSYS_CB_CON				0xcac
+#define MT8196_CB_BYPASS_MUX_SHADOW				(0xff << 16)
+#define MT8196_EVENT_GCE_EN					(BIT(0) | BIT(1))
+
+/* DISPSYS config */
+#define MT8196_DISP0_DLI_RELAY0				0x200
+#define MT8196_DISP0_DLI_RELAY1				0x204
+#define MT8196_DISP0_DLI_RELAY8				0x220
+#define MT8196_DISP0_DLO_RELAY1				0x268
+#define MT8196_DISP0_DLO_RELAY2				0x26c
+#define MT8196_DISP0_DLO_RELAY3				0x270
+#define MT8196_DLI_RELAY_1T2P					BIT(30)
+#define MT8196_DISP0_BYPASS_MUX_SHADOW			0xc30
+#define MT8196_BYPASS_MUX_SHADOW				BIT(0)
+#define MT8196_OVLSYS_CB_BYPASS_MUX_SHADOW			(0xff << 16)
+
+/* DISPSYS1 config */
+#define MT8196_DISP1_INT_MERGE				0x008
+#define MT8196_DISP1_DLI_RELAY21			0x204
+#define MT8196_DISP1_DLI_RELAY22			0x208
+#define MT8196_DISP1_DLI_RELAY23			0x20c
+#define MT8196_DISP1_GCE_FRAME_DONE_SEL0		0xa10
+#define MT8196_DISP1_GCE_FRAME_DONE_SEL1		0xa14
+#define MT8196_FRAME_DONE_DVO					25
+#define MT8196_FRAME_DONE_DP_INTF0				41
+#define MT8196_DISP1_BYPASS_MUX_SHADOW			0xcf8
+
+/* VDISP_AO config */
+#define MT8196_VDISP_AO_REG_INTEN			0x000
+#define MT8196_CPU_INTEN					BIT(0)
+#define MT8196_CPU_INT_MERGE					BIT(4)
+#define MT8196_VDISP_AO_REG_INT_SEL_G0			0x020
+#define MT8196_VDISP_AO_REG_INT_SEL_G1			0x024
+#define MT8196_VDISP_AO_REG_INT_SEL_G2			0x028
+#define MT8196_VDISP_AO_REG_INT_SEL_G3			0x02c
+#define MT8196_VDISP_AO_REG_INT_SEL_G4			0x030
+#define MT8196_VDISP_AO_REG_INT_SEL_G5			0x034
+#define MT8196_VDISP_AO_REG_INT_SEL_G6			0x038
+#define MT8196_IRQ_TABLE_OVL0_OUTPROC0				(0xa6) /* GIC 450 */
+#define MT8196_IRQ_TABLE_OVL0_OUTPROC1				(0xa7) /* GIC 451 */
+#define MT8196_IRQ_TABLE_OVL1_OUTPROC0				(0xd6) /* GIC 452 */
+#define MT8196_IRQ_TABLE_DSI0					(0x35) /* GIC 453 */
+
+static const struct mtk_mmsys_async_info mmsys_mt8196_ovl0_async_comp_table[] = {
+	{DDP_COMPONENT_OVL0_DLO_ASYNC5, 0, MT8196_OVL_DL_OUT_RELAY5_SIZE, GENMASK(29, 0)},
+	{DDP_COMPONENT_OVL0_DLO_ASYNC6, 1, MT8196_OVL_DL_OUT_RELAY6_SIZE, GENMASK(29, 0)},
+};
+
+static const struct mtk_mmsys_async_info mmsys_mt8196_ovl1_async_comp_table[] = {
+	{DDP_COMPONENT_OVL1_DLO_ASYNC5, 0, MT8196_OVL_DL_OUT_RELAY5_SIZE, GENMASK(29, 0)},
+	{DDP_COMPONENT_OVL1_DLO_ASYNC6, 1, MT8196_OVL_DL_OUT_RELAY6_SIZE, GENMASK(29, 0)},
+};
+
+static const struct mtk_mmsys_async_info mmsys_mt8196_disp0_async_comp_table[] = {
+	{DDP_COMPONENT_DLI_ASYNC0, 0, MT8196_DISP0_DLI_RELAY0, GENMASK(29, 0)},
+	{DDP_COMPONENT_DLI_ASYNC1, 1, MT8196_DISP0_DLI_RELAY1, GENMASK(29, 0)},
+	{DDP_COMPONENT_DLI_ASYNC8, 2, MT8196_DISP0_DLI_RELAY8, GENMASK(29, 0)},
+	{DDP_COMPONENT_DLO_ASYNC1, 3, MT8196_DISP0_DLO_RELAY1, GENMASK(29, 0)},
+	{DDP_COMPONENT_DLO_ASYNC2, 4, MT8196_DISP0_DLO_RELAY2, GENMASK(29, 0)},
+	{DDP_COMPONENT_DLO_ASYNC3, 5, MT8196_DISP0_DLO_RELAY3, GENMASK(29, 0)},
+};
+
+static const struct mtk_mmsys_async_info mmsys_mt8196_disp1_async_comp_table[] = {
+	{DDP_COMPONENT_DLI_ASYNC21, 0, MT8196_DISP1_DLI_RELAY21, GENMASK(29, 0)},
+	{DDP_COMPONENT_DLI_ASYNC22, 1, MT8196_DISP1_DLI_RELAY22, GENMASK(29, 0)},
+	{DDP_COMPONENT_DLI_ASYNC23, 2, MT8196_DISP1_DLI_RELAY23, GENMASK(29, 0)},
+};
+
+static const struct mtk_mmsys_default mmsys_mt8196_vdisp_ao_default_table[] = {
+	{MT8196_VDISP_AO_REG_INTEN, MT8196_CPU_INTEN, MT8196_CPU_INT_MERGE | MT8196_CPU_INTEN},
+	{MT8196_VDISP_AO_REG_INT_SEL_G0, MT8196_IRQ_TABLE_OVL0_OUTPROC0, GENMASK(7, 0)},
+	{MT8196_VDISP_AO_REG_INT_SEL_G0, MT8196_IRQ_TABLE_OVL0_OUTPROC1 << 8, GENMASK(15, 8)},
+	{MT8196_VDISP_AO_REG_INT_SEL_G0, MT8196_IRQ_TABLE_OVL1_OUTPROC0 << 16, GENMASK(23, 16)},
+	{MT8196_VDISP_AO_REG_INT_SEL_G0, MT8196_IRQ_TABLE_DSI0 << 24, GENMASK(31, 24)}
+};
+
+static const struct mtk_mmsys_default mmsys_mt8196_ovl0_default_table[] = {
+	{MT8196_OVLSYS_GCE_EVENT_SEL, MT8196_EVENT_GCE_EN, GENMASK(1, 0)},
+	{MT8196_OVL_INT_MERGE, 0, BIT(0)},
+	{MT8196_OVLSYS_BYPASS_MUX_SHADOW,
+	 MT8196_BYPASS_MUX_SHADOW, MT8196_BYPASS_MUX_SHADOW},
+	{MT8196_OVLSYS_CB_CON, MT8196_OVLSYS_CB_BYPASS_MUX_SHADOW,
+	 MT8196_OVLSYS_CB_BYPASS_MUX_SHADOW},
+};
+
+static const struct mtk_mmsys_default mmsys_mt8196_disp0_default_table[] = {
+	{MT8196_OVLSYS_GCE_EVENT_SEL, MT8196_EVENT_GCE_EN, GENMASK(1, 0)},
+	{MT8196_DISP0_BYPASS_MUX_SHADOW,
+	 MT8196_CB_BYPASS_MUX_SHADOW | MT8196_BYPASS_MUX_SHADOW,
+	 MT8196_CB_BYPASS_MUX_SHADOW | MT8196_BYPASS_MUX_SHADOW},
+	{MT8196_DISP0_DLI_RELAY0, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)},
+	{MT8196_DISP0_DLI_RELAY1, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)},
+	{MT8196_DISP0_DLI_RELAY8, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)},
+	{MT8196_DISP0_DLO_RELAY1, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)},
+	{MT8196_DISP0_DLO_RELAY2, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)},
+	{MT8196_DISP0_DLO_RELAY3, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)},
+};
+
+static const struct mtk_mmsys_default mmsys_mt8196_disp1_default_table[] = {
+	{MT8196_OVLSYS_GCE_EVENT_SEL, MT8196_EVENT_GCE_EN, GENMASK(1, 0)},
+	{MT8196_DISP1_INT_MERGE, 0, BIT(0)},
+	{MT8196_DISP1_BYPASS_MUX_SHADOW,
+	 MT8196_CB_BYPASS_MUX_SHADOW | MT8196_BYPASS_MUX_SHADOW,
+	 MT8196_CB_BYPASS_MUX_SHADOW | MT8196_BYPASS_MUX_SHADOW},
+	{MT8196_DISP1_DLI_RELAY21, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)},
+	{MT8196_DISP1_DLI_RELAY22, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)},
+	{MT8196_DISP1_DLI_RELAY23, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)},
+	{MT8196_DISP1_GCE_FRAME_DONE_SEL0, MT8196_FRAME_DONE_DVO, GENMASK(5, 0)},
+	{MT8196_DISP1_GCE_FRAME_DONE_SEL1, MT8196_FRAME_DONE_DP_INTF0, GENMASK(5, 0)},
+};
+
+static const struct mtk_mmsys_routes mmsys_mt8196_ovl0_routing_table[] = {
+	MMSYS_ROUTE(OVL0_EXDMA2, OVL0_BLENDER1,
+		    MT8196_OVL_RSZ_IN_CB2_MOUT_EN, MT8196_DISP_OVL_EXDMA2_1_TO_OVL_EXDMA_OUT_CB3,
+		    MT8196_DISP_OVL_EXDMA2_1_TO_OVL_EXDMA_OUT_CB3),
+	MMSYS_ROUTE(OVL0_EXDMA2, OVL0_BLENDER1,
+		    MT8196_OVL_EXDMA_OUT_CB3_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER1,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER1),
+	MMSYS_ROUTE(OVL0_EXDMA3, OVL0_BLENDER2,
+		    MT8196_OVL_EXDMA_OUT_CB4_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER2,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER2),
+	MMSYS_ROUTE(OVL0_EXDMA4, OVL0_BLENDER3,
+		    MT8196_OVL_EXDMA_OUT_CB5_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER3,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER3),
+	MMSYS_ROUTE(OVL0_EXDMA5, OVL0_BLENDER4,
+		    MT8196_OVL_EXDMA_OUT_CB6_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER4,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER4),
+	MMSYS_ROUTE(OVL0_EXDMA6, OVL0_BLENDER5,
+		    MT8196_OVL_EXDMA_OUT_CB7_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER5,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER5),
+	MMSYS_ROUTE(OVL0_EXDMA7, OVL0_BLENDER6,
+		    MT8196_OVL_EXDMA_OUT_CB8_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER6,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER6),
+	MMSYS_ROUTE(OVL0_EXDMA8, OVL0_BLENDER7,
+		    MT8196_OVL_EXDMA_OUT_CB9_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER7,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER7),
+	MMSYS_ROUTE(OVL0_EXDMA9, OVL0_BLENDER8,
+		    MT8196_OVL_EXDMA_OUT_CB10_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER8,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER8),
+	MMSYS_ROUTE(OVL0_BLENDER4, OVL0_OUTPROC0,
+		    MT8196_OVL_BLENDER_OUT_CB4_MOUT_EN, MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC0,
+		    MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC0),
+	MMSYS_ROUTE(OVL0_BLENDER8, OVL0_OUTPROC1,
+		    MT8196_OVL_BLENDER_OUT_CB8_MOUT_EN, MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC1,
+		    MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC1),
+	MMSYS_ROUTE(OVL0_OUTPROC0, OVL0_DLO_ASYNC5,
+		    MT8196_OVL_OUTPROC_OUT_CB0_MOUT_EN,
+		    MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY5,
+		    MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY5),
+	MMSYS_ROUTE(OVL0_OUTPROC1, OVL0_DLO_ASYNC6,
+		    MT8196_OVL_OUTPROC_OUT_CB1_MOUT_EN,
+		    MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY6,
+		    MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY6)
+};
+
+static const struct mtk_mmsys_routes mmsys_mt8196_ovl1_routing_table[] = {
+	MMSYS_ROUTE(OVL1_EXDMA2, OVL1_BLENDER1,
+		    MT8196_OVL_RSZ_IN_CB2_MOUT_EN, MT8196_DISP_OVL_EXDMA2_1_TO_OVL_EXDMA_OUT_CB3,
+		    MT8196_DISP_OVL_EXDMA2_1_TO_OVL_EXDMA_OUT_CB3),
+	MMSYS_ROUTE(OVL1_EXDMA2, OVL1_BLENDER1,
+		    MT8196_OVL_EXDMA_OUT_CB3_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER1,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER1),
+	MMSYS_ROUTE(OVL1_EXDMA3, OVL1_BLENDER2,
+		    MT8196_OVL_EXDMA_OUT_CB4_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER2,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER2),
+	MMSYS_ROUTE(OVL1_EXDMA4, OVL1_BLENDER3,
+		    MT8196_OVL_EXDMA_OUT_CB5_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER3,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER3),
+	MMSYS_ROUTE(OVL1_EXDMA5, OVL1_BLENDER4,
+		    MT8196_OVL_EXDMA_OUT_CB6_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER4,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER4),
+	MMSYS_ROUTE(OVL1_EXDMA6, OVL1_BLENDER5,
+		    MT8196_OVL_EXDMA_OUT_CB7_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER5,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER5),
+	MMSYS_ROUTE(OVL1_EXDMA7, OVL1_BLENDER6,
+		    MT8196_OVL_EXDMA_OUT_CB8_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER6,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER6),
+	MMSYS_ROUTE(OVL1_EXDMA8, OVL1_BLENDER7,
+		    MT8196_OVL_EXDMA_OUT_CB9_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER7,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER7),
+	MMSYS_ROUTE(OVL1_EXDMA9, OVL1_BLENDER8,
+		    MT8196_OVL_EXDMA_OUT_CB10_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER8,
+		    MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER8),
+	MMSYS_ROUTE(OVL1_BLENDER4, OVL1_OUTPROC0,
+		    MT8196_OVL_BLENDER_OUT_CB4_MOUT_EN, MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC0,
+		    MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC0),
+	MMSYS_ROUTE(OVL1_BLENDER8, OVL1_OUTPROC1,
+		    MT8196_OVL_BLENDER_OUT_CB8_MOUT_EN, MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC1,
+		    MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC1),
+	MMSYS_ROUTE(OVL1_OUTPROC0, OVL1_DLO_ASYNC5,
+		    MT8196_OVL_OUTPROC_OUT_CB0_MOUT_EN,
+		    MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY5,
+		    MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY5),
+	MMSYS_ROUTE(OVL1_OUTPROC1, OVL1_DLO_ASYNC6,
+		    MT8196_OVL_OUTPROC_OUT_CB1_MOUT_EN,
+		    MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY6,
+		    MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY6)
+};
+
+/*
+ * main: DLI_ASYNC0-> PQ_IN_CB0 -> PQ_OUT_CB6 -> PANEL_COMP_OUT_CB1 -> DLO_ASYNC1
+ * ext:  DLI_ASYNC1-> PQ_IN_CB1 -> PQ_OUT_CB7 -> PANEL_COMP_OUT_CB2 -> DLO_ASYNC2
+ */
+static const struct mtk_mmsys_routes mmsys_mt8196_disp0_routing_table[] = {
+	MMSYS_ROUTE(DLI_ASYNC0, DLO_ASYNC1,
+		    MT8196_PQ_IN_CB0_MOUT_EN, MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6,
+		    MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6),
+	MMSYS_ROUTE(DLI_ASYNC0, DLO_ASYNC1,
+		    MT8196_PQ_OUT_CB6_MOUT_EN, MT8196_PQ_OUT_CB6_TO_PANEL0_COMP_OUT_CB1,
+		    MT8196_PQ_OUT_CB6_TO_PANEL0_COMP_OUT_CB1),
+	MMSYS_ROUTE(DLI_ASYNC0, DLO_ASYNC1,
+		    MT8196_PANEL_COMP_OUT_CB1_MOUT_EN, MT8196_DISP_TO_DLO_RELAY1,
+		    MT8196_DISP_TO_DLO_RELAY1),
+	MMSYS_ROUTE(DLI_ASYNC1, DLO_ASYNC2,
+		    MT8196_PQ_IN_CB1_MOUT_EN, MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7,
+		    MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7),
+	MMSYS_ROUTE(DLI_ASYNC1, DLO_ASYNC2,
+		    MT8196_PQ_OUT_CB7_MOUT_EN, MT8196_PQ_OUT_CB7_TO_PANEL0_COMP_OUT_CB2,
+		    MT8196_PQ_OUT_CB7_TO_PANEL0_COMP_OUT_CB2),
+	MMSYS_ROUTE(DLI_ASYNC1, DLO_ASYNC2,
+		    MT8196_PANEL_COMP_OUT_CB2_MOUT_EN, MT8196_DISP_TO_DLO_RELAY2,
+		    MT8196_DISP_TO_DLO_RELAY2),
+	MMSYS_ROUTE(DLI_ASYNC8, DLO_ASYNC3,
+		    MT8196_PQ_IN_CB8_MOUT_EN, MT8196_PQ_IN_CB8_TO_PQ_OUT_CB_8,
+		    MT8196_PQ_IN_CB8_TO_PQ_OUT_CB_8),
+	MMSYS_ROUTE(DLI_ASYNC8, DLO_ASYNC3,
+		    MT8196_PQ_OUT_CB8_MOUT_EN, MT8196_PQ_OUT_CB8_TO_PANEL0_COMP_OUT_CB3,
+		    MT8196_PQ_OUT_CB8_TO_PANEL0_COMP_OUT_CB3),
+	MMSYS_ROUTE(DLI_ASYNC8, DLO_ASYNC3,
+		    MT8196_PANEL_COMP_OUT_CB3_MOUT_EN, MT8196_DISP_TO_DLO_RELAY3,
+		    MT8196_DISP_TO_DLO_RELAY3)
+};
+
+/*
+ * main: DLI_ASYNC21-> SPLITTER_IN_CB1-> SPLITTER_OUT_CB9-> COMP_OUT_CB6-> MERGE_OUT_CB0 -> DVO
+ * ext: DLI_ASYNC22-> SPLITTER_IN_CB2-> SPLITTER_OUT_CB10-> COMP_OUT_CB7-> MERGE_OUT_CB1 -> DP_INTF0
+ */
+static const struct mtk_mmsys_routes mmsys_mt8196_disp1_routing_table[] = {
+	MMSYS_ROUTE(DLI_ASYNC21, DVO0,
+		    MT8196_SPLITTER_IN_CB1_MOUT_EN, MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB9,
+		    MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB9),
+	MMSYS_ROUTE(DLI_ASYNC21, DVO0,
+		    MT8196_SPLITTER_OUT_CB9_MOUT_EN, MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB6,
+		    MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB6),
+	MMSYS_ROUTE(DLI_ASYNC21, DVO0,
+		    MT8196_COMP_OUT_CB6_MOUT_EN, MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB0,
+		    MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB0),
+	MMSYS_ROUTE(DLI_ASYNC21, DVO0,
+		    MT8196_MERGE_OUT_CB0_MOUT_EN, MT8196_DISP_COMP_OUT_CB_TO_DVO0,
+		    MT8196_DISP_COMP_OUT_CB_TO_DVO0),
+	MMSYS_ROUTE(DLI_ASYNC22, DP_INTF0,
+		    MT8196_SPLITTER_IN_CB2_MOUT_EN, MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB10,
+		    MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB10),
+	MMSYS_ROUTE(DLI_ASYNC22, DP_INTF0,
+		    MT8196_SPLITTER_OUT_CB10_MOUT_EN, MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB7,
+		    MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB7),
+	MMSYS_ROUTE(DLI_ASYNC22, DP_INTF0,
+		    MT8196_COMP_OUT_CB7_MOUT_EN, MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB1,
+		    MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB1),
+	MMSYS_ROUTE(DLI_ASYNC22, DP_INTF0,
+		    MT8196_MERGE_OUT_CB1_MOUT_EN, MT8196_DISP_COMP_OUT_CB_TO_DP_INTF0,
+		    MT8196_DISP_COMP_OUT_CB_TO_DP_INTF0),
+	MMSYS_ROUTE(DLI_ASYNC23, DVO0,
+		    MT8196_SPLITTER_IN_CB3_MOUT_EN, MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB11,
+		    MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB11),
+	MMSYS_ROUTE(DLI_ASYNC23, DVO0,
+		    MT8196_SPLITTER_OUT_CB11_MOUT_EN, MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB8,
+		    MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB8),
+	MMSYS_ROUTE(DLI_ASYNC23, DVO0,
+		    MT8196_COMP_OUT_CB8_MOUT_EN, MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB2,
+		    MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB2),
+	MMSYS_ROUTE(DLI_ASYNC23, DVO0,
+		    MT8196_MERGE_OUT_CB2_MOUT_EN, MT8196_DISP_COMP_OUT_CB_TO_DVO0,
+		    MT8196_DISP_COMP_OUT_CB_TO_DVO0),
+	MMSYS_ROUTE(DLI_ASYNC23, DP_INTF1,
+		    MT8196_SPLITTER_IN_CB3_MOUT_EN, MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB11,
+		    MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB11),
+	MMSYS_ROUTE(DLI_ASYNC23, DP_INTF1,
+		    MT8196_SPLITTER_OUT_CB11_MOUT_EN, MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB8,
+		    MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB8),
+	MMSYS_ROUTE(DLI_ASYNC23, DP_INTF1,
+		    MT8196_COMP_OUT_CB8_MOUT_EN, MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB2,
+		    MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB2),
+	MMSYS_ROUTE(DLI_ASYNC23, DP_INTF1,
+		    MT8196_MERGE_OUT_CB2_MOUT_EN, MT8196_DISP_COMP_OUT_CB_TO_DP_INTF1,
+		    MT8196_DISP_COMP_OUT_CB_TO_DP_INTF1),
+	MMSYS_ROUTE(DLI_ASYNC23, DSI0,
+		    MT8196_SPLITTER_IN_CB3_MOUT_EN, MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB11,
+		    MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB11),
+	MMSYS_ROUTE(DLI_ASYNC23, DSI0,
+		    MT8196_SPLITTER_OUT_CB11_MOUT_EN, MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB8,
+		    MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB8),
+	MMSYS_ROUTE(DLI_ASYNC23, DSI0,
+		    MT8196_COMP_OUT_CB8_MOUT_EN, MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB2,
+		    MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB2),
+	MMSYS_ROUTE(DLI_ASYNC23, DSI0,
+		    MT8196_MERGE_OUT_CB2_MOUT_EN, MT8196_DISP_COMP_OUT_CB_TO_DSI0,
+		    MT8196_DISP_COMP_OUT_CB_TO_DSI0)
+};
+#endif /* __SOC_MEDIATEK_MT8196_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index f448cc09ce19..3b490b993549 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -24,6 +24,7 @@
 #include "mt8188-mmsys.h"
 #include "mt8192-mmsys.h"
 #include "mt8195-mmsys.h"
+#include "mt8196-mmsys.h"
 #include "mt8365-mmsys.h"
 
 #define MMSYS_SW_RESET_PER_REG 32
@@ -147,6 +148,54 @@ static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = {
 	.is_vppsys = true,
 };
 
+static const struct mtk_mmsys_driver_data mt8196_dispsys0_driver_data = {
+	.clk_driver = "clk-mt8196-disp0",
+	.routes = mmsys_mt8196_disp0_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8196_disp0_routing_table),
+	.async_info = mmsys_mt8196_disp0_async_comp_table,
+	.num_async_info = ARRAY_SIZE(mmsys_mt8196_disp0_async_comp_table),
+	.def_config = mmsys_mt8196_disp0_default_table,
+	.num_def_config = ARRAY_SIZE(mmsys_mt8196_disp0_default_table),
+	.num_top_clk = 1,
+};
+
+static const struct mtk_mmsys_driver_data mt8196_dispsys1_driver_data = {
+	.clk_driver = "clk-mt8196-disp1",
+	.routes = mmsys_mt8196_disp1_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8196_disp1_routing_table),
+	.async_info = mmsys_mt8196_disp1_async_comp_table,
+	.num_async_info = ARRAY_SIZE(mmsys_mt8196_disp1_async_comp_table),
+	.def_config = mmsys_mt8196_disp1_default_table,
+	.num_def_config = ARRAY_SIZE(mmsys_mt8196_disp1_default_table),
+	.num_top_clk = 1,
+};
+
+static const struct mtk_mmsys_driver_data mt8196_ovlsys0_driver_data = {
+	.clk_driver = "clk-mt8196-ovl0",
+	.routes = mmsys_mt8196_ovl0_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8196_ovl0_routing_table),
+	.async_info = mmsys_mt8196_ovl0_async_comp_table,
+	.num_async_info = ARRAY_SIZE(mmsys_mt8196_ovl0_async_comp_table),
+	.def_config = mmsys_mt8196_ovl0_default_table,
+	.num_def_config = ARRAY_SIZE(mmsys_mt8196_ovl0_default_table),
+};
+
+static const struct mtk_mmsys_driver_data mt8196_ovlsys1_driver_data = {
+	.clk_driver = "clk-mt8196-ovl1",
+	.routes = mmsys_mt8196_ovl1_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8196_ovl1_routing_table),
+	.async_info = mmsys_mt8196_ovl1_async_comp_table,
+	.num_async_info = ARRAY_SIZE(mmsys_mt8196_ovl1_async_comp_table),
+	.def_config = mmsys_mt8196_ovl0_default_table,
+	.num_def_config = ARRAY_SIZE(mmsys_mt8196_ovl0_default_table),
+};
+
+static const struct mtk_mmsys_driver_data mt8196_vdisp_ao_driver_data = {
+	.clk_driver = "clk-mt8196-vdisp_ao",
+	.def_config = mmsys_mt8196_vdisp_ao_default_table,
+	.num_def_config = ARRAY_SIZE(mmsys_mt8196_vdisp_ao_default_table),
+};
+
 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
 	.clk_driver = "clk-mt8365-mm",
 	.routes = mt8365_mmsys_routing_table,
@@ -626,6 +675,11 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
 	{ .compatible = "mediatek,mt8195-vdosys1", .data = &mt8195_vdosys1_driver_data },
 	{ .compatible = "mediatek,mt8195-vppsys0", .data = &mt8195_vppsys0_driver_data },
 	{ .compatible = "mediatek,mt8195-vppsys1", .data = &mt8195_vppsys1_driver_data },
+	{ .compatible = "mediatek,mt8196-dispsys0", .data = &mt8196_dispsys0_driver_data },
+	{ .compatible = "mediatek,mt8196-dispsys1", .data = &mt8196_dispsys1_driver_data },
+	{ .compatible = "mediatek,mt8196-ovlsys0", .data = &mt8196_ovlsys0_driver_data },
+	{ .compatible = "mediatek,mt8196-ovlsys1", .data = &mt8196_ovlsys1_driver_data },
+	{ .compatible = "mediatek,mt8196-vdisp-ao", .data = &mt8196_vdisp_ao_driver_data },
 	{ .compatible = "mediatek,mt8365-mmsys", .data = &mt8365_mmsys_driver_data },
 	{ /* sentinel */ }
 };
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index f50f626e1840..4a0b10567581 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -29,6 +29,15 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_COLOR1,
 	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DITHER1,
+	DDP_COMPONENT_DLI_ASYNC0,
+	DDP_COMPONENT_DLI_ASYNC1,
+	DDP_COMPONENT_DLI_ASYNC8,
+	DDP_COMPONENT_DLI_ASYNC21,
+	DDP_COMPONENT_DLI_ASYNC22,
+	DDP_COMPONENT_DLI_ASYNC23,
+	DDP_COMPONENT_DLO_ASYNC1,
+	DDP_COMPONENT_DLO_ASYNC2,
+	DDP_COMPONENT_DLO_ASYNC3,
 	DDP_COMPONENT_DP_INTF0,
 	DDP_COMPONENT_DP_INTF1,
 	DDP_COMPONENT_DPI0,
@@ -39,6 +48,7 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_DSI1,
 	DDP_COMPONENT_DSI2,
 	DDP_COMPONENT_DSI3,
+	DDP_COMPONENT_DVO0,
 	DDP_COMPONENT_ETHDR_MIXER,
 	DDP_COMPONENT_GAMMA,
 	DDP_COMPONENT_MDP_RDMA0,
@@ -58,10 +68,52 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_OD0,
 	DDP_COMPONENT_OD1,
 	DDP_COMPONENT_OVL0,
+	DDP_COMPONENT_OVL0_BLENDER1,
+	DDP_COMPONENT_OVL0_BLENDER2,
+	DDP_COMPONENT_OVL0_BLENDER3,
+	DDP_COMPONENT_OVL0_BLENDER4,
+	DDP_COMPONENT_OVL0_BLENDER5,
+	DDP_COMPONENT_OVL0_BLENDER6,
+	DDP_COMPONENT_OVL0_BLENDER7,
+	DDP_COMPONENT_OVL0_BLENDER8,
+	DDP_COMPONENT_OVL0_BLENDER9,
+	DDP_COMPONENT_OVL0_DLO_ASYNC5,
+	DDP_COMPONENT_OVL0_DLO_ASYNC6,
+	DDP_COMPONENT_OVL0_EXDMA2,
+	DDP_COMPONENT_OVL0_EXDMA3,
+	DDP_COMPONENT_OVL0_EXDMA4,
+	DDP_COMPONENT_OVL0_EXDMA5,
+	DDP_COMPONENT_OVL0_EXDMA6,
+	DDP_COMPONENT_OVL0_EXDMA7,
+	DDP_COMPONENT_OVL0_EXDMA8,
+	DDP_COMPONENT_OVL0_EXDMA9,
+	DDP_COMPONENT_OVL0_OUTPROC0,
+	DDP_COMPONENT_OVL0_OUTPROC1,
 	DDP_COMPONENT_OVL_2L0,
 	DDP_COMPONENT_OVL_2L1,
 	DDP_COMPONENT_OVL_2L2,
 	DDP_COMPONENT_OVL1,
+	DDP_COMPONENT_OVL1_BLENDER1,
+	DDP_COMPONENT_OVL1_BLENDER2,
+	DDP_COMPONENT_OVL1_BLENDER3,
+	DDP_COMPONENT_OVL1_BLENDER4,
+	DDP_COMPONENT_OVL1_BLENDER5,
+	DDP_COMPONENT_OVL1_BLENDER6,
+	DDP_COMPONENT_OVL1_BLENDER7,
+	DDP_COMPONENT_OVL1_BLENDER8,
+	DDP_COMPONENT_OVL1_BLENDER9,
+	DDP_COMPONENT_OVL1_DLO_ASYNC5,
+	DDP_COMPONENT_OVL1_DLO_ASYNC6,
+	DDP_COMPONENT_OVL1_EXDMA2,
+	DDP_COMPONENT_OVL1_EXDMA3,
+	DDP_COMPONENT_OVL1_EXDMA4,
+	DDP_COMPONENT_OVL1_EXDMA5,
+	DDP_COMPONENT_OVL1_EXDMA6,
+	DDP_COMPONENT_OVL1_EXDMA7,
+	DDP_COMPONENT_OVL1_EXDMA8,
+	DDP_COMPONENT_OVL1_EXDMA9,
+	DDP_COMPONENT_OVL1_OUTPROC0,
+	DDP_COMPONENT_OVL1_OUTPROC1,
 	DDP_COMPONENT_PADDING0,
 	DDP_COMPONENT_PADDING1,
 	DDP_COMPONENT_PADDING2,
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:17 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:17 +0800
Subject: [PATCH v3 05/17] soc: mediatek: Add runtime PM and top clocks and async controls for MMSYS
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-6-paul-pl.chen@mediatek.com>

From: Nancy Lin <nancy.lin at mediatek.com>

- Add initialization of top clocks and async clocks for each MMSYS.
- Add PM runtime control and new functions to manage these clocks.
- Add functions to set these clocks according to the default
  configuration of the corresponding MMSYS.

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 drivers/soc/mediatek/mtk-mmsys.c       | 152 ++++++++++++++++++++++++-
 drivers/soc/mediatek/mtk-mmsys.h       |  18 +++
 include/linux/soc/mediatek/mtk-mmsys.h |   8 ++
 3 files changed, 177 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index bb4639ca0b8c..f448cc09ce19 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -4,12 +4,15 @@
  * Author: James Liao <jamesjj.liao at mediatek.com>
  */
 
+#include <linux/bitfield.h>
+#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 #include <linux/reset-controller.h>
 #include <linux/soc/mediatek/mtk-mmsys.h>
 
@@ -158,6 +161,9 @@ struct mtk_mmsys {
 	spinlock_t lock; /* protects mmsys_sw_rst_b reg */
 	struct reset_controller_dev rcdev;
 	struct cmdq_client_reg cmdq_base;
+	struct clk **async_clk;
+	int num_async_clk;
+	struct clk **top_clk;
 };
 
 static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val,
@@ -180,6 +186,101 @@ static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask,
 	writel_relaxed(tmp, mmsys->regs + offset);
 }
 
+int mtk_mmsys_top_clk_enable(struct device *dev)
+{
+	struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+	int ret, i;
+
+	if (!mmsys->data->num_top_clk)
+		return 0;
+
+	for (i = 0; i < mmsys->data->num_top_clk; i++)
+		ret = clk_prepare_enable(mmsys->top_clk[i]);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_top_clk_enable);
+
+void mtk_mmsys_top_clk_disable(struct device *dev)
+{
+	struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < mmsys->data->num_top_clk; i++)
+		clk_disable_unprepare(mmsys->top_clk[i]);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_top_clk_disable);
+
+int mtk_mmsys_ddp_clk_enable(struct device *dev, enum mtk_ddp_comp_id comp_id)
+{
+	struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+	const struct mtk_mmsys_async_info *async = mmsys->data->async_info;
+
+	int i;
+
+	if (!mmsys->data->num_async_info)
+		return 0;
+
+	for (i = 0; i < mmsys->data->num_async_info; i++)
+		if (comp_id == async[i].comp_id)
+			return clk_prepare_enable(mmsys->async_clk[async[i].index]);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_clk_enable);
+
+void mtk_mmsys_ddp_clk_disable(struct device *dev, enum mtk_ddp_comp_id comp_id)
+{
+	struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+	const struct mtk_mmsys_async_info *async = mmsys->data->async_info;
+	int i;
+
+	if (!mmsys->data->num_async_info)
+		return;
+
+	for (i = 0; i < mmsys->data->num_async_info; i++)
+		if (comp_id == async[i].comp_id)
+			clk_disable_unprepare(mmsys->async_clk[async[i].index]);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_clk_disable);
+
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_ddp_comp_id comp_id,
+			  int width, int height, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+	const struct mtk_mmsys_async_info *async = mmsys->data->async_info;
+	int i;
+	u32 val;
+
+	if (!mmsys->data->num_async_info)
+		return;
+
+	for (i = 0; i < mmsys->data->num_async_info; i++)
+		if (comp_id == async[i].comp_id)
+			break;
+
+	if (i == mmsys->data->num_async_info)
+		return;
+
+	val = FIELD_PREP(GENMASK(31, 16), height);
+	val |= FIELD_PREP(GENMASK(15, 0), width);
+	mtk_mmsys_update_bits(mmsys, async[i].offset, async[i].mask, val, cmdq_pkt);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+
+void mtk_mmsys_default_config(struct device *dev)
+{
+	struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+	const struct mtk_mmsys_default *def_config = mmsys->data->def_config;
+	int i;
+
+	if (!mmsys->data->num_def_config)
+		return;
+
+	for (i = 0; i < mmsys->data->num_def_config; i++)
+		mtk_mmsys_update_bits(mmsys, def_config[i].offset, def_config[i].mask,
+				      def_config[i].val, NULL);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_default_config);
+
 void mtk_mmsys_ddp_connect(struct device *dev,
 			   enum mtk_ddp_comp_id cur,
 			   enum mtk_ddp_comp_id next)
@@ -390,7 +491,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 	struct platform_device *clks;
 	struct platform_device *drm;
 	struct mtk_mmsys *mmsys;
-	int ret;
+	int ret, i;
 
 	mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
 	if (!mmsys)
@@ -432,6 +533,49 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		return PTR_ERR(clks);
 	mmsys->clks_pdev = clks;
 
+	if (mmsys->data->num_top_clk) {
+		struct device_node *node;
+
+		node = of_get_child_by_name(dev->of_node, "top");
+		if (!node) {
+			dev_err(&pdev->dev, "Couldn't find top node\n");
+			return -EINVAL;
+		}
+
+		mmsys->top_clk = devm_kmalloc_array(dev, mmsys->data->num_top_clk,
+						    sizeof(*mmsys->top_clk), GFP_KERNEL);
+		if (!mmsys->top_clk)
+			return -ENOMEM;
+
+		for (i = 0; i < mmsys->data->num_top_clk; i++) {
+			mmsys->top_clk[i] = of_clk_get(node, i);
+			if (IS_ERR(mmsys->top_clk[i]))
+				return PTR_ERR(mmsys->top_clk[i]);
+		}
+	}
+
+	if (mmsys->data->num_async_info) {
+		struct device_node *node;
+
+		node = of_get_child_by_name(dev->of_node, "async");
+		if (!node) {
+			dev_err(&pdev->dev, "Couldn't find async node\n");
+			return -EINVAL;
+		}
+
+		mmsys->async_clk = devm_kmalloc_array(dev, mmsys->data->num_async_info,
+						      sizeof(*mmsys->async_clk), GFP_KERNEL);
+		if (!mmsys->async_clk)
+			return -ENOMEM;
+		mmsys->num_async_clk = mmsys->data->num_async_info;
+
+		for (i = 0; i < mmsys->num_async_clk; i++) {
+			mmsys->async_clk[i] = of_clk_get(node, i);
+			if (IS_ERR(mmsys->async_clk[i]))
+				return PTR_ERR(mmsys->async_clk[i]);
+		}
+	}
+
 	if (mmsys->data->is_vppsys)
 		goto out_probe_done;
 
@@ -443,6 +587,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 	}
 	mmsys->drm_pdev = drm;
 
+	if (of_property_present(dev->of_node, "power-domains"))
+		pm_runtime_enable(dev);
+
 out_probe_done:
 	return 0;
 }
@@ -453,6 +600,9 @@ static void mtk_mmsys_remove(struct platform_device *pdev)
 
 	platform_device_unregister(mmsys->drm_pdev);
 	platform_device_unregister(mmsys->clks_pdev);
+
+	if (of_property_present(pdev->dev.of_node, "power-domains"))
+		pm_runtime_disable(&pdev->dev);
 }
 
 static const struct of_device_id of_match_mtk_mmsys[] = {
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index fe628d5f5198..bbc03ef5b025 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -102,6 +102,19 @@ struct mtk_mmsys_routes {
 	u32 val;
 };
 
+struct mtk_mmsys_async_info {
+	u32 comp_id;
+	u32 index;
+	u32 offset;
+	u32 mask;
+};
+
+struct mtk_mmsys_default {
+	u32 offset;
+	u32 val;
+	u32 mask;
+};
+
 /**
  * struct mtk_mmsys_driver_data - Settings of the mmsys
  * @clk_driver: Clock driver name that the mmsys is using
@@ -139,6 +152,11 @@ struct mtk_mmsys_driver_data {
 	const u32 num_resets;
 	const bool is_vppsys;
 	const u8 vsync_len;
+	const struct mtk_mmsys_async_info *async_info;
+	const unsigned int num_async_info;
+	const struct mtk_mmsys_default *def_config;
+	const unsigned int num_def_config;
+	const unsigned int num_top_clk;
 };
 
 /*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4885b065b849..f50f626e1840 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -84,6 +84,14 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_ID_MAX,
 };
 
+int mtk_mmsys_top_clk_enable(struct device *dev);
+void mtk_mmsys_top_clk_disable(struct device *dev);
+int mtk_mmsys_ddp_clk_enable(struct device *dev, enum mtk_ddp_comp_id comp_id);
+void mtk_mmsys_ddp_clk_disable(struct device *dev, enum mtk_ddp_comp_id comp_id);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_ddp_comp_id comp_id,
+			  int width, int height, struct cmdq_pkt *cmdq_pkt);
+void mtk_mmsys_default_config(struct device *dev);
+
 void mtk_mmsys_ddp_connect(struct device *dev,
 			   enum mtk_ddp_comp_id cur,
 			   enum mtk_ddp_comp_id next);
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:29 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:29 +0800
Subject: [PATCH v3 17/17] drm/mediatek: Add support for MT8196 multiple mmsys
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-18-paul-pl.chen@mediatek.com>

From: Nancy Lin <nancy.lin at mediatek.com>

Add code to support MT8196 SOC Multi MMSYS Driver

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 119 ++++++++++++++++++++++++-
 1 file changed, 115 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 1e49ca3fef80..229f84a4e59c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -193,6 +193,10 @@ static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = {
 	{0, DDP_COMPONENT_DSI0},
 };
 
+static const struct mtk_drm_route mt8196_mtk_ddp_routes[] = {
+	{2, DDP_COMPONENT_DSI0},
+};
+
 static const unsigned int mt8192_mtk_ddp_main[] = {
 	DDP_COMPONENT_OVL0,
 	DDP_COMPONENT_OVL_2L0,
@@ -231,6 +235,50 @@ static const unsigned int mt8195_mtk_ddp_ext[] = {
 	DDP_COMPONENT_DP_INTF1,
 };
 
+static const unsigned int mt8196_mtk_ddp_ovl0_main[] = {
+	DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0,
+	DDP_COMPONENT_OVL0_DLO_ASYNC5,
+};
+
+static const unsigned int mt8196_mtk_ddp_disp0_main[] = {
+	DDP_COMPONENT_DLI_ASYNC0,
+	DDP_COMPONENT_DLO_ASYNC1,
+};
+
+static const unsigned int mt8196_mtk_ddp_disp1_main[] = {
+	DDP_COMPONENT_DLI_ASYNC21,
+	DDP_COMPONENT_DVO0,
+};
+
+static const unsigned int mt8196_mtk_ddp_ovl0_ext[] = {
+	DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1,
+	DDP_COMPONENT_OVL0_DLO_ASYNC6,
+};
+
+static const unsigned int mt8196_mtk_ddp_disp0_ext[] = {
+	DDP_COMPONENT_DLI_ASYNC1,
+	DDP_COMPONENT_DLO_ASYNC2,
+};
+
+static const unsigned int mt8196_mtk_ddp_disp1_ext[] = {
+	DDP_COMPONENT_DLI_ASYNC22,
+	DDP_COMPONENT_DP_INTF0,
+};
+
+static const unsigned int mt8196_mtk_ddp_ovl1_third[] = {
+	DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2,
+	DDP_COMPONENT_OVL1_DLO_ASYNC5,
+};
+
+static const unsigned int mt8196_mtk_ddp_disp0_third[] = {
+	DDP_COMPONENT_DLI_ASYNC8,
+	DDP_COMPONENT_DLO_ASYNC3,
+};
+
+static const unsigned int mt8196_mtk_ddp_disp1_third[] = {
+	DDP_COMPONENT_DLI_ASYNC23,
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.main_path = mt2701_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -327,8 +375,65 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
 	.min_height = 1,
 };
 
-static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
-	.mmsys_dev_num = 1,
+static const struct mtk_mmsys_driver_data mt8196_dispsys0_driver_data = {
+	.main_path = mt8196_mtk_ddp_disp0_main,
+	.main_len = ARRAY_SIZE(mt8196_mtk_ddp_disp0_main),
+	.main_order = 1,
+	.ext_path = mt8196_mtk_ddp_disp0_ext,
+	.ext_len = ARRAY_SIZE(mt8196_mtk_ddp_disp0_ext),
+	.ext_order = 1,
+	.third_path = mt8196_mtk_ddp_disp0_third,
+	.third_len = ARRAY_SIZE(mt8196_mtk_ddp_disp0_third),
+	.third_order = 1,
+	.mmsys_id = DISPSYS0,
+	.mmsys_dev_num = 4,
+	.max_width = 8191,
+	.min_width = 2, /* 2-pixel align when ethdr is bypassed */
+	.min_height = 1,
+};
+
+static const struct mtk_mmsys_driver_data mt8196_dispsys1_driver_data = {
+	.main_path = mt8196_mtk_ddp_disp1_main,
+	.main_len = ARRAY_SIZE(mt8196_mtk_ddp_disp1_main),
+	.main_order = 2,
+	.ext_path = mt8196_mtk_ddp_disp1_ext,
+	.ext_len = ARRAY_SIZE(mt8196_mtk_ddp_disp1_ext),
+	.ext_order = 2,
+	.third_path = mt8196_mtk_ddp_disp1_third,
+	.third_len = ARRAY_SIZE(mt8196_mtk_ddp_disp1_third),
+	.conn_routes = mt8196_mtk_ddp_routes,
+	.num_conn_routes = ARRAY_SIZE(mt8196_mtk_ddp_routes),
+	.third_order = 2,
+	.mmsys_id = DISPSYS1,
+	.mmsys_dev_num = 4,
+	.max_width = 8191,
+	.min_width = 2, /* 2-pixel align when ethdr is bypassed */
+	.min_height = 1,
+};
+
+static const struct mtk_mmsys_driver_data mt8196_ovlsys0_driver_data = {
+	.main_path = mt8196_mtk_ddp_ovl0_main,
+	.main_len = ARRAY_SIZE(mt8196_mtk_ddp_ovl0_main),
+	.main_order = 0,
+	.ext_path = mt8196_mtk_ddp_ovl0_ext,
+	.ext_len = ARRAY_SIZE(mt8196_mtk_ddp_ovl0_ext),
+	.ext_order = 0,
+	.mmsys_id = OVLSYS0,
+	.mmsys_dev_num = 4,
+	.max_width = 8191,
+	.min_width = 2, /* 2-pixel align when ethdr is bypassed */
+	.min_height = 1,
+};
+
+static const struct mtk_mmsys_driver_data mt8196_ovlsys1_driver_data = {
+	.third_path = mt8196_mtk_ddp_ovl1_third,
+	.third_len = ARRAY_SIZE(mt8196_mtk_ddp_ovl1_third),
+	.third_order = 0,
+	.mmsys_id = OVLSYS1,
+	.mmsys_dev_num = 4,
+	.max_width = 8191,
+	.min_width = 2, /* 2-pixel align when ethdr is bypassed */
+	.min_height = 1,
 };
 
 static const struct of_device_id mtk_drm_of_ids[] = {
@@ -358,8 +463,14 @@ static const struct of_device_id mtk_drm_of_ids[] = {
 	  .data = &mt8195_vdosys0_driver_data},
 	{ .compatible = "mediatek,mt8195-vdosys1",
 	  .data = &mt8195_vdosys1_driver_data},
-	{ .compatible = "mediatek,mt8365-mmsys",
-	  .data = &mt8365_mmsys_driver_data},
+	{ .compatible = "mediatek,mt8196-dispsys0",
+	  .data = &mt8196_dispsys0_driver_data},
+	{ .compatible = "mediatek,mt8196-dispsys1",
+	  .data = &mt8196_dispsys1_driver_data},
+	{ .compatible = "mediatek,mt8196-ovlsys0",
+	  .data = &mt8196_ovlsys0_driver_data},
+	{ .compatible = "mediatek,mt8196-ovlsys1",
+	  .data = &mt8196_ovlsys1_driver_data},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:27 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:27 +0800
Subject: [PATCH v3 15/17] drm/mediatek: add ovlsys_adaptor support for MT8196
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-16-paul-pl.chen@mediatek.com>

From: Nancy Lin <nancy.lin at mediatek.com>

Ovlsys_adaptor is an encapsulated module designed to
simplify the DRM control flow. This module is composed
of 20 EXDMAs, 20 BLENDERs, and 12 OUTPROCs.
Two EXDMAs merge into one layer, allowing the module
to support 20 layers for 3 display paths.
Ovlsys_adaptor driver is integrated within the
mtk_ddp_comp framework.

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile             |   1 +
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c       |  28 +
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h       |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |  32 +
 .../drm/mediatek/mtk_disp_ovlsys_adaptor.c    | 729 ++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  69 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |  10 +-
 7 files changed, 846 insertions(+), 24 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovlsys_adaptor.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 9546bc6b7b2e..dedf50860d3f 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -9,6 +9,7 @@ mediatek-drm-y := mtk_crtc.o \
 		  mtk_disp_exdma.o \
 		  mtk_disp_gamma.o \
 		  mtk_disp_merge.o \
+		  mtk_disp_ovlsys_adaptor.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_outproc.o \
 		  mtk_disp_ovl_adaptor.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index cc780744f060..c96e027359ac 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -368,6 +368,31 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
 	.get_num_formats = mtk_ovl_get_num_formats,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_ovlsys_adaptor = {
+	.power_on = mtk_ovlsys_adaptor_power_on,
+	.power_off = mtk_ovlsys_adaptor_power_off,
+	.clk_enable = mtk_ovlsys_adaptor_clk_enable,
+	.clk_disable = mtk_ovlsys_adaptor_clk_disable,
+	.config = mtk_ovlsys_adaptor_config,
+	.start = mtk_ovlsys_adaptor_start,
+	.stop = mtk_ovlsys_adaptor_stop,
+	.layer_check = mtk_ovlsys_adaptor_layer_check,
+	.layer_nr = mtk_ovlsys_adaptor_layer_nr,
+	.layer_config = mtk_ovlsys_adaptor_layer_config,
+	.register_vblank_cb = mtk_ovlsys_adaptor_register_vblank_cb,
+	.unregister_vblank_cb = mtk_ovlsys_adaptor_unregister_vblank_cb,
+	.enable_vblank = mtk_ovlsys_adaptor_enable_vblank,
+	.disable_vblank = mtk_ovlsys_adaptor_disable_vblank,
+	.dma_dev_get = mtk_ovlsys_adaptor_dma_dev_get,
+	.connect = mtk_ovlsys_adaptor_connect,
+	.disconnect = mtk_ovlsys_adaptor_disconnect,
+	.add = mtk_ovlsys_adaptor_add_comp,
+	.remove = mtk_ovlsys_adaptor_remove_comp,
+	.get_blend_modes = mtk_ovlsys_adaptor_get_blend_modes,
+	.get_formats = mtk_ovlsys_adaptor_get_formats,
+	.get_num_formats = mtk_ovlsys_adaptor_get_num_formats,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_postmask = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -437,6 +462,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_OVL] = "ovl",
 	[MTK_DISP_OVL_2L] = "ovl-2l",
 	[MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor",
+	[MTK_DISP_OVLSYS_ADAPTOR] = "ovlsys_adaptor",
 	[MTK_DISP_POSTMASK] = "postmask",
 	[MTK_DISP_PWM] = "pwm",
 	[MTK_DISP_RDMA] = "rdma",
@@ -469,6 +495,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
 	[DDP_COMPONENT_DPI0]		= { MTK_DPI,			0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]		= { MTK_DPI,			1, &ddp_dpi },
 	[DDP_COMPONENT_DRM_OVL_ADAPTOR]	= { MTK_DISP_OVL_ADAPTOR,	0, &ddp_ovl_adaptor },
+	[DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0] = { MTK_DISP_OVLSYS_ADAPTOR, 0, &ddp_ovlsys_adaptor},
+	[DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1] = { MTK_DISP_OVLSYS_ADAPTOR, 1, &ddp_ovlsys_adaptor},
 	[DDP_COMPONENT_DSC0]		= { MTK_DISP_DSC,		0, &ddp_dsc },
 	[DDP_COMPONENT_DSC1]		= { MTK_DISP_DSC,		1, &ddp_dsc },
 	[DDP_COMPONENT_DSI0]		= { MTK_DSI,			0, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index b33d3289b8b6..ef64ce7a071f 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -33,6 +33,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
 	MTK_DISP_OVL,
+	MTK_DISP_OVLSYS_ADAPTOR,
 	MTK_DISP_OVL_2L,
 	MTK_DISP_OVL_ADAPTOR,
 	MTK_DISP_POSTMASK,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 3c519a662074..1ff8c4593fc1 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -174,6 +174,38 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev);
 enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct device *dev,
 						const struct drm_display_mode *mode);
 
+int mtk_ovlsys_adaptor_power_on(struct device *dev);
+void mtk_ovlsys_adaptor_power_off(struct device *dev);
+void mtk_ovlsys_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex);
+void mtk_ovlsys_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex);
+void mtk_ovlsys_adaptor_connect(struct device *dev, struct device *mmsys_dev,
+				unsigned int next);
+void mtk_ovlsys_adaptor_disconnect(struct device *dev, struct device *mmsys_dev,
+				   unsigned int next);
+int mtk_ovlsys_adaptor_clk_enable(struct device *dev);
+void mtk_ovlsys_adaptor_clk_disable(struct device *dev);
+void mtk_ovlsys_adaptor_config(struct device *dev, unsigned int w,
+			       unsigned int h, unsigned int vrefresh,
+			       unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ovlsys_adaptor_layer_config(struct device *dev, unsigned int idx,
+				     struct mtk_plane_state *state,
+				     struct cmdq_pkt *cmdq_pkt);
+int mtk_ovlsys_adaptor_layer_check(struct device *dev,
+				   unsigned int idx,
+				   struct mtk_plane_state *mtk_state);
+void mtk_ovlsys_adaptor_register_vblank_cb(struct device *dev, void (*vblank_cb)(void *),
+					   void *vblank_cb_data);
+void mtk_ovlsys_adaptor_unregister_vblank_cb(struct device *dev);
+void mtk_ovlsys_adaptor_enable_vblank(struct device *dev);
+void mtk_ovlsys_adaptor_disable_vblank(struct device *dev);
+void mtk_ovlsys_adaptor_start(struct device *dev);
+void mtk_ovlsys_adaptor_stop(struct device *dev);
+unsigned int mtk_ovlsys_adaptor_layer_nr(struct device *dev);
+struct device *mtk_ovlsys_adaptor_dma_dev_get(struct device *dev);
+u32 mtk_ovlsys_adaptor_get_blend_modes(struct device *dev);
+const u32 *mtk_ovlsys_adaptor_get_formats(struct device *dev);
+size_t mtk_ovlsys_adaptor_get_num_formats(struct device *dev);
+
 void mtk_rdma_bypass_shadow(struct device *dev);
 int mtk_rdma_clk_enable(struct device *dev);
 void mtk_rdma_clk_disable(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovlsys_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovlsys_adaptor.c
new file mode 100644
index 000000000000..465184190bc2
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovlsys_adaptor.c
@@ -0,0 +1,729 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <drm/drm_of.h>
+#include <drm/drm_print.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-mutex.h>
+
+#include "mtk_crtc.h"
+#include "mtk_ddp_comp.h"
+#include "mtk_disp_blender.h"
+#include "mtk_disp_drv.h"
+#include "mtk_disp_outproc.h"
+#include "mtk_drm_drv.h"
+
+#define OVLSYS_ADAPTOR_DRIVER_DATA_MAX_SIZE 8191
+
+enum mtk_ovlsys_adaptor_comp_type {
+	OVLSYS_ADAPTOR_TYPE_EXDMA = 0,
+	OVLSYS_ADAPTOR_TYPE_BLENDER,
+	OVLSYS_ADAPTOR_TYPE_OUTPROC,
+	OVLSYS_ADAPTOR_TYPE_NUM,
+};
+
+enum mtk_ovlsys_adaptor_comp_id {
+	OVLSYS_ADAPTOR_EXDMA0,
+	OVLSYS_ADAPTOR_EXDMA1,
+	OVLSYS_ADAPTOR_EXDMA2,
+	OVLSYS_ADAPTOR_EXDMA3,
+	OVLSYS_ADAPTOR_EXDMA4,
+	OVLSYS_ADAPTOR_EXDMA5,
+	OVLSYS_ADAPTOR_EXDMA6,
+	OVLSYS_ADAPTOR_EXDMA7,
+	OVLSYS_ADAPTOR_EXDMA8,
+	OVLSYS_ADAPTOR_EXDMA9,
+	OVLSYS_ADAPTOR_EXDMA10,
+	OVLSYS_ADAPTOR_EXDMA11,
+	OVLSYS_ADAPTOR_EXDMA12,
+	OVLSYS_ADAPTOR_EXDMA13,
+	OVLSYS_ADAPTOR_EXDMA14,
+	OVLSYS_ADAPTOR_EXDMA15,
+	OVLSYS_ADAPTOR_EXDMA16,
+	OVLSYS_ADAPTOR_EXDMA17,
+	OVLSYS_ADAPTOR_EXDMA18,
+	OVLSYS_ADAPTOR_EXDMA19,
+	OVLSYS_ADAPTOR_BLENDER0,
+	OVLSYS_ADAPTOR_BLENDER1,
+	OVLSYS_ADAPTOR_BLENDER2,
+	OVLSYS_ADAPTOR_BLENDER3,
+	OVLSYS_ADAPTOR_BLENDER4,
+	OVLSYS_ADAPTOR_BLENDER5,
+	OVLSYS_ADAPTOR_BLENDER6,
+	OVLSYS_ADAPTOR_BLENDER7,
+	OVLSYS_ADAPTOR_BLENDER8,
+	OVLSYS_ADAPTOR_BLENDER9,
+	OVLSYS_ADAPTOR_BLENDER10,
+	OVLSYS_ADAPTOR_BLENDER11,
+	OVLSYS_ADAPTOR_BLENDER12,
+	OVLSYS_ADAPTOR_BLENDER13,
+	OVLSYS_ADAPTOR_BLENDER14,
+	OVLSYS_ADAPTOR_BLENDER15,
+	OVLSYS_ADAPTOR_BLENDER16,
+	OVLSYS_ADAPTOR_BLENDER17,
+	OVLSYS_ADAPTOR_BLENDER18,
+	OVLSYS_ADAPTOR_BLENDER19,
+	OVLSYS_ADAPTOR_OUTPROC0,
+	OVLSYS_ADAPTOR_OUTPROC1,
+	OVLSYS_ADAPTOR_OUTPROC2,
+	OVLSYS_ADAPTOR_OUTPROC3,
+	OVLSYS_ADAPTOR_OUTPROC4,
+	OVLSYS_ADAPTOR_OUTPROC5,
+	OVLSYS_ADAPTOR_OUTPROC6,
+	OVLSYS_ADAPTOR_OUTPROC7,
+	OVLSYS_ADAPTOR_OUTPROC8,
+	OVLSYS_ADAPTOR_OUTPROC9,
+	OVLSYS_ADAPTOR_OUTPROC10,
+	OVLSYS_ADAPTOR_OUTPROC11,
+	OVLSYS_ADAPTOR_ID_MAX
+};
+
+struct ovlsys_adaptor_comp_match {
+	enum mtk_ovlsys_adaptor_comp_type type;
+	int alias_id;
+	enum mtk_ddp_comp_id comp_id;
+};
+
+struct mtk_disp_ovlsys_adaptor {
+	struct device *ovl_adaptor_comp[OVLSYS_ADAPTOR_ID_MAX];
+	struct device *mmsys_dev;
+	const unsigned int *path;
+	unsigned int path_size;
+	unsigned int layer_nr;
+	bool children_bound;
+};
+
+static const char * const private_comp_stem[OVLSYS_ADAPTOR_TYPE_NUM] = {
+	[OVLSYS_ADAPTOR_TYPE_EXDMA]	= "exdma",
+	[OVLSYS_ADAPTOR_TYPE_BLENDER]	= "blender",
+	[OVLSYS_ADAPTOR_TYPE_OUTPROC]	= "outproc",
+};
+
+static const struct ovlsys_adaptor_comp_match comp_matches[OVLSYS_ADAPTOR_ID_MAX] = {
+	[OVLSYS_ADAPTOR_EXDMA2]	  = { OVLSYS_ADAPTOR_TYPE_EXDMA, 2, DDP_COMPONENT_OVL0_EXDMA2},
+	[OVLSYS_ADAPTOR_EXDMA3]	  = { OVLSYS_ADAPTOR_TYPE_EXDMA, 3, DDP_COMPONENT_OVL0_EXDMA3},
+	[OVLSYS_ADAPTOR_EXDMA4]	  = { OVLSYS_ADAPTOR_TYPE_EXDMA, 4, DDP_COMPONENT_OVL0_EXDMA4},
+	[OVLSYS_ADAPTOR_EXDMA5]	  = { OVLSYS_ADAPTOR_TYPE_EXDMA, 5, DDP_COMPONENT_OVL0_EXDMA5},
+	[OVLSYS_ADAPTOR_EXDMA6]	  = { OVLSYS_ADAPTOR_TYPE_EXDMA, 6, DDP_COMPONENT_OVL0_EXDMA6},
+	[OVLSYS_ADAPTOR_EXDMA7]	  = { OVLSYS_ADAPTOR_TYPE_EXDMA, 7, DDP_COMPONENT_OVL0_EXDMA7},
+	[OVLSYS_ADAPTOR_EXDMA8]	  = { OVLSYS_ADAPTOR_TYPE_EXDMA, 8, DDP_COMPONENT_OVL0_EXDMA8},
+	[OVLSYS_ADAPTOR_EXDMA9]	  = { OVLSYS_ADAPTOR_TYPE_EXDMA, 9, DDP_COMPONENT_OVL0_EXDMA9},
+	[OVLSYS_ADAPTOR_EXDMA12]   = { OVLSYS_ADAPTOR_TYPE_EXDMA, 12, DDP_COMPONENT_OVL1_EXDMA2},
+	[OVLSYS_ADAPTOR_EXDMA13]   = { OVLSYS_ADAPTOR_TYPE_EXDMA, 13, DDP_COMPONENT_OVL1_EXDMA3},
+	[OVLSYS_ADAPTOR_EXDMA14]   = { OVLSYS_ADAPTOR_TYPE_EXDMA, 14, DDP_COMPONENT_OVL1_EXDMA4},
+	[OVLSYS_ADAPTOR_EXDMA15]   = { OVLSYS_ADAPTOR_TYPE_EXDMA, 15, DDP_COMPONENT_OVL1_EXDMA5},
+	[OVLSYS_ADAPTOR_EXDMA16]   = { OVLSYS_ADAPTOR_TYPE_EXDMA, 16, DDP_COMPONENT_OVL1_EXDMA6},
+	[OVLSYS_ADAPTOR_EXDMA17]   = { OVLSYS_ADAPTOR_TYPE_EXDMA, 17, DDP_COMPONENT_OVL1_EXDMA7},
+	[OVLSYS_ADAPTOR_EXDMA18]   = { OVLSYS_ADAPTOR_TYPE_EXDMA, 18, DDP_COMPONENT_OVL1_EXDMA8},
+	[OVLSYS_ADAPTOR_EXDMA19]   = { OVLSYS_ADAPTOR_TYPE_EXDMA, 19, DDP_COMPONENT_OVL1_EXDMA9},
+	[OVLSYS_ADAPTOR_BLENDER1] = { OVLSYS_ADAPTOR_TYPE_BLENDER, 1, DDP_COMPONENT_OVL0_BLENDER1},
+	[OVLSYS_ADAPTOR_BLENDER2] = { OVLSYS_ADAPTOR_TYPE_BLENDER, 2, DDP_COMPONENT_OVL0_BLENDER2},
+	[OVLSYS_ADAPTOR_BLENDER3] = { OVLSYS_ADAPTOR_TYPE_BLENDER, 3, DDP_COMPONENT_OVL0_BLENDER3},
+	[OVLSYS_ADAPTOR_BLENDER4] = { OVLSYS_ADAPTOR_TYPE_BLENDER, 4, DDP_COMPONENT_OVL0_BLENDER4},
+	[OVLSYS_ADAPTOR_BLENDER5] = { OVLSYS_ADAPTOR_TYPE_BLENDER, 5, DDP_COMPONENT_OVL0_BLENDER5},
+	[OVLSYS_ADAPTOR_BLENDER6] = { OVLSYS_ADAPTOR_TYPE_BLENDER, 6, DDP_COMPONENT_OVL0_BLENDER6},
+	[OVLSYS_ADAPTOR_BLENDER7] = { OVLSYS_ADAPTOR_TYPE_BLENDER, 7, DDP_COMPONENT_OVL0_BLENDER7},
+	[OVLSYS_ADAPTOR_BLENDER8] = { OVLSYS_ADAPTOR_TYPE_BLENDER, 8, DDP_COMPONENT_OVL0_BLENDER8},
+	[OVLSYS_ADAPTOR_BLENDER9] = { OVLSYS_ADAPTOR_TYPE_BLENDER, 9, DDP_COMPONENT_OVL0_BLENDER9},
+	[OVLSYS_ADAPTOR_BLENDER11] = {
+		OVLSYS_ADAPTOR_TYPE_BLENDER, 11, DDP_COMPONENT_OVL1_BLENDER1},
+	[OVLSYS_ADAPTOR_BLENDER12] = {
+		OVLSYS_ADAPTOR_TYPE_BLENDER, 12, DDP_COMPONENT_OVL1_BLENDER2},
+	[OVLSYS_ADAPTOR_BLENDER13] = {
+		OVLSYS_ADAPTOR_TYPE_BLENDER, 13, DDP_COMPONENT_OVL1_BLENDER3},
+	[OVLSYS_ADAPTOR_BLENDER14] = {
+		OVLSYS_ADAPTOR_TYPE_BLENDER, 14, DDP_COMPONENT_OVL1_BLENDER4},
+	[OVLSYS_ADAPTOR_BLENDER15] = {
+		OVLSYS_ADAPTOR_TYPE_BLENDER, 15, DDP_COMPONENT_OVL1_BLENDER5},
+	[OVLSYS_ADAPTOR_BLENDER16] = {
+		OVLSYS_ADAPTOR_TYPE_BLENDER, 16, DDP_COMPONENT_OVL1_BLENDER6},
+	[OVLSYS_ADAPTOR_BLENDER17] = {
+		OVLSYS_ADAPTOR_TYPE_BLENDER, 17, DDP_COMPONENT_OVL1_BLENDER7},
+	[OVLSYS_ADAPTOR_BLENDER18] = {
+		OVLSYS_ADAPTOR_TYPE_BLENDER, 18, DDP_COMPONENT_OVL1_BLENDER8},
+	[OVLSYS_ADAPTOR_BLENDER19] = {
+		OVLSYS_ADAPTOR_TYPE_BLENDER, 19, DDP_COMPONENT_OVL1_BLENDER9},
+	[OVLSYS_ADAPTOR_OUTPROC0] = { OVLSYS_ADAPTOR_TYPE_OUTPROC, 0, DDP_COMPONENT_OVL0_OUTPROC0},
+	[OVLSYS_ADAPTOR_OUTPROC1] = { OVLSYS_ADAPTOR_TYPE_OUTPROC, 1, DDP_COMPONENT_OVL0_OUTPROC1},
+	[OVLSYS_ADAPTOR_OUTPROC6] = { OVLSYS_ADAPTOR_TYPE_OUTPROC, 6, DDP_COMPONENT_OVL1_OUTPROC0},
+};
+
+static const unsigned int mt8196_mtk_ovl_main[] = {
+	OVLSYS_ADAPTOR_EXDMA2,
+	OVLSYS_ADAPTOR_BLENDER1,
+	OVLSYS_ADAPTOR_EXDMA3,
+	OVLSYS_ADAPTOR_BLENDER2,
+	OVLSYS_ADAPTOR_EXDMA4,
+	OVLSYS_ADAPTOR_BLENDER3,
+	OVLSYS_ADAPTOR_EXDMA5,
+	OVLSYS_ADAPTOR_BLENDER4,
+	OVLSYS_ADAPTOR_OUTPROC0,
+};
+
+static const unsigned int mt8196_mtk_ovl_ext[] = {
+	OVLSYS_ADAPTOR_EXDMA6,
+	OVLSYS_ADAPTOR_BLENDER5,
+	OVLSYS_ADAPTOR_EXDMA7,
+	OVLSYS_ADAPTOR_BLENDER6,
+	OVLSYS_ADAPTOR_EXDMA8,
+	OVLSYS_ADAPTOR_BLENDER7,
+	OVLSYS_ADAPTOR_EXDMA9,
+	OVLSYS_ADAPTOR_BLENDER8,
+	OVLSYS_ADAPTOR_OUTPROC1,
+};
+
+static const unsigned int mt8196_mtk_ovl_third[] = {
+	OVLSYS_ADAPTOR_EXDMA12,
+	OVLSYS_ADAPTOR_BLENDER11,
+	OVLSYS_ADAPTOR_EXDMA13,
+	OVLSYS_ADAPTOR_BLENDER12,
+	OVLSYS_ADAPTOR_EXDMA14,
+	OVLSYS_ADAPTOR_BLENDER13,
+	OVLSYS_ADAPTOR_EXDMA15,
+	OVLSYS_ADAPTOR_BLENDER14,
+	OVLSYS_ADAPTOR_OUTPROC6,
+};
+
+static enum mtk_ovlsys_adaptor_comp_type get_type(enum mtk_ovlsys_adaptor_comp_id id)
+{
+	return comp_matches[id].type;
+}
+
+static enum mtk_ddp_comp_id get_ddp_comp_id(enum mtk_ovlsys_adaptor_comp_id id)
+{
+	return comp_matches[id].comp_id;
+}
+
+int mtk_ovlsys_adaptor_power_on(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+	struct device *comp;
+	int ret = 0;
+	int i;
+
+	for (i = 0; i < priv->path_size; i++) {
+		comp = priv->ovl_adaptor_comp[priv->path[i]];
+		if (!comp || get_type(priv->path[i]) != OVLSYS_ADAPTOR_TYPE_EXDMA)
+			continue;
+
+		ret = pm_runtime_get_sync(comp);
+		if (ret < 0) {
+			dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret);
+			goto pwr_err;
+		}
+	}
+
+	return ret;
+
+pwr_err:
+	while (--i >= 0) {
+		comp = priv->ovl_adaptor_comp[i];
+		if (!comp || get_type(priv->path[i]) != OVLSYS_ADAPTOR_TYPE_EXDMA)
+			continue;
+
+		pm_runtime_put(priv->ovl_adaptor_comp[i]);
+	}
+
+	return ret;
+}
+
+void mtk_ovlsys_adaptor_power_off(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+	struct device *comp;
+	int i;
+
+	for (i = 0; i < priv->path_size; i++) {
+		comp = priv->ovl_adaptor_comp[priv->path[i]];
+		if (!comp || get_type(priv->path[i]) != OVLSYS_ADAPTOR_TYPE_EXDMA)
+			continue;
+
+		pm_runtime_put(comp);
+	}
+}
+
+void mtk_ovlsys_adaptor_layer_config(struct device *dev, unsigned int idx,
+				     struct mtk_plane_state *state,
+				     struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_plane_pending_state *pending = &state->pending;
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+	struct device *exdma;
+	struct device *blender;
+	const struct drm_format_info *fmt_info = drm_format_info(pending->format);
+
+	DRM_DEV_DEBUG_DRIVER(dev, "idx:%d enable:%d fmt:0x%x addr:0x%pad fb_w:%d {%d,%d,%d,%d}\n",
+			     idx, pending->enable, pending->format,
+			     &pending->addr, (pending->pitch / fmt_info->cpp[0]),
+			     pending->x, pending->y, pending->width, pending->height);
+
+	exdma = priv->ovl_adaptor_comp[priv->path[idx * 2]];
+	if (!exdma) {
+		dev_err(dev, "%s: exdma%d comp not found\n", __func__, idx);
+		return;
+	}
+
+	blender = priv->ovl_adaptor_comp[priv->path[idx * 2 + 1]];
+	if (!blender) {
+		dev_err(dev, "%s: blender%d comp not found\n", __func__, idx);
+		return;
+	}
+
+	if (pending->height == 0 || pending->width == 0 ||
+	    pending->x > OVLSYS_ADAPTOR_DRIVER_DATA_MAX_SIZE ||
+	    pending->y > OVLSYS_ADAPTOR_DRIVER_DATA_MAX_SIZE)
+		pending->enable = false;
+
+	mtk_disp_exdma_layer_config(exdma, state, cmdq_pkt);
+	mtk_disp_blender_layer_config(blender, state, cmdq_pkt);
+}
+
+void mtk_ovlsys_adaptor_config(struct device *dev, unsigned int w,
+			       unsigned int h, unsigned int vrefresh,
+			       unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+	int i;
+	int blender_idx = 0;
+
+	for (i = 0; i < priv->path_size; i++) {
+		if (get_type(priv->path[i]) == OVLSYS_ADAPTOR_TYPE_BLENDER) {
+			blender_idx++;
+
+			mtk_disp_blender_config(priv->ovl_adaptor_comp[priv->path[i]], w, h,
+						vrefresh, bpc, blender_idx == priv->layer_nr,
+						blender_idx == 1, cmdq_pkt);
+		} else if (get_type(priv->path[i]) == OVLSYS_ADAPTOR_TYPE_OUTPROC) {
+			mtk_disp_outproc_config(priv->ovl_adaptor_comp[priv->path[i]], w, h,
+						vrefresh, bpc, cmdq_pkt);
+		}
+	}
+}
+
+int mtk_ovlsys_adaptor_layer_check(struct device *dev,
+				   unsigned int idx,
+				   struct mtk_plane_state *mtk_state)
+{
+	struct drm_plane_state *state = &mtk_state->base;
+
+	/* Check if any unsupported rotation is set */
+	if (state->rotation & ~DRM_MODE_ROTATE_0)
+		return -EINVAL;
+
+	return 0;
+}
+
+void mtk_ovlsys_adaptor_start(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < (priv->path_size - 1); i += 2) {
+		mtk_disp_exdma_start(priv->ovl_adaptor_comp[priv->path[i]], NULL);
+		mtk_disp_blender_start(priv->ovl_adaptor_comp[priv->path[i + 1]], NULL);
+	}
+
+	mtk_disp_outproc_start(priv->ovl_adaptor_comp[priv->path[i]]);
+}
+
+void mtk_ovlsys_adaptor_stop(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < (priv->path_size - 1); i += 2) {
+		mtk_disp_exdma_start(priv->ovl_adaptor_comp[priv->path[i]], NULL);
+		mtk_disp_blender_start(priv->ovl_adaptor_comp[priv->path[i + 1]], NULL);
+	}
+
+	mtk_disp_outproc_start(priv->ovl_adaptor_comp[priv->path[i]]);
+}
+
+int mtk_ovlsys_adaptor_clk_enable(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+	struct device *comp;
+	int ret = 0;
+	int i;
+
+	for (i = 0; i < priv->path_size; i++) {
+		comp = priv->ovl_adaptor_comp[priv->path[i]];
+		if (!comp)
+			continue;
+
+		if (get_type(priv->path[i]) == OVLSYS_ADAPTOR_TYPE_EXDMA)
+			ret = mtk_disp_exdma_clk_enable(comp);
+		else if (get_type(priv->path[i]) == OVLSYS_ADAPTOR_TYPE_BLENDER)
+			ret = mtk_disp_blender_clk_enable(comp);
+		else
+			ret = mtk_disp_outproc_clk_enable(comp);
+
+		if (ret) {
+			dev_err(dev, "Failed to enable clock %d, err %d\n", i, ret);
+			goto clk_err;
+		}
+	}
+
+	return ret;
+
+clk_err:
+	while (--i >= 0) {
+		comp = priv->ovl_adaptor_comp[priv->path[i]];
+		if (!comp)
+			continue;
+
+		if (get_type(priv->path[i]) == OVLSYS_ADAPTOR_TYPE_EXDMA)
+			mtk_disp_exdma_clk_disable(comp);
+		else if (get_type(priv->path[i]) == OVLSYS_ADAPTOR_TYPE_BLENDER)
+			mtk_disp_blender_clk_disable(comp);
+		else
+			mtk_disp_outproc_clk_disable(comp);
+	}
+
+	return ret;
+}
+
+void mtk_ovlsys_adaptor_clk_disable(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+	struct device *comp;
+	int i;
+
+	for (i = 0; i < priv->path_size; i++) {
+		comp = priv->ovl_adaptor_comp[priv->path[i]];
+		if (!comp)
+			continue;
+
+		if (get_type(priv->path[i]) == OVLSYS_ADAPTOR_TYPE_EXDMA)
+			mtk_disp_exdma_clk_disable(comp);
+		else if (get_type(priv->path[i]) == OVLSYS_ADAPTOR_TYPE_BLENDER)
+			mtk_disp_blender_clk_disable(comp);
+		else
+			mtk_disp_outproc_clk_disable(comp);
+	}
+}
+
+unsigned int mtk_ovlsys_adaptor_layer_nr(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+
+	return priv->layer_nr;
+}
+
+struct device *mtk_ovlsys_adaptor_dma_dev_get(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+
+	return priv->ovl_adaptor_comp[priv->path[0]];
+}
+
+void mtk_ovlsys_adaptor_register_vblank_cb(struct device *dev, void (*vblank_cb)(void *),
+					   void *vblank_cb_data)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+
+	mtk_disp_outproc_register_vblank_cb(priv->ovl_adaptor_comp[priv->path[priv->path_size - 1]],
+					    vblank_cb, vblank_cb_data);
+}
+
+void mtk_ovlsys_adaptor_unregister_vblank_cb(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+	struct device *comp = priv->ovl_adaptor_comp[priv->path[priv->path_size - 1]];
+
+	mtk_disp_outproc_unregister_vblank_cb(comp);
+}
+
+void mtk_ovlsys_adaptor_enable_vblank(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+
+	mtk_disp_outproc_enable_vblank(priv->ovl_adaptor_comp[priv->path[priv->path_size - 1]]);
+}
+
+void mtk_ovlsys_adaptor_disable_vblank(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+
+	mtk_disp_outproc_disable_vblank(priv->ovl_adaptor_comp[priv->path[priv->path_size - 1]]);
+}
+
+u32 mtk_ovlsys_adaptor_get_blend_modes(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+
+	return mtk_disp_blender_get_blend_modes(priv->ovl_adaptor_comp[priv->path[1]]);
+}
+
+const u32 *mtk_ovlsys_adaptor_get_formats(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+
+	return mtk_disp_exdma_get_formats(priv->ovl_adaptor_comp[priv->path[0]]);
+}
+
+size_t mtk_ovlsys_adaptor_get_num_formats(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+
+	return mtk_disp_exdma_get_num_formats(priv->ovl_adaptor_comp[priv->path[0]]);
+}
+
+void mtk_ovlsys_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < priv->path_size; i++)
+		mtk_mutex_add_comp(mutex, get_ddp_comp_id(priv->path[i]));
+}
+
+void mtk_ovlsys_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < priv->path_size; i++)
+		mtk_mutex_remove_comp(mutex, get_ddp_comp_id(priv->path[i]));
+}
+
+void mtk_ovlsys_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < priv->path_size - 1; i++)
+		mtk_mmsys_ddp_connect(mmsys_dev, get_ddp_comp_id(priv->path[i]),
+				      get_ddp_comp_id(priv->path[i + 1]));
+
+	mtk_mmsys_ddp_connect(mmsys_dev, get_ddp_comp_id(priv->path[i]), next);
+}
+
+void mtk_ovlsys_adaptor_disconnect(struct device *dev, struct device *mmsys_dev, unsigned int next)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < priv->path_size - 1; i++)
+		mtk_mmsys_ddp_disconnect(mmsys_dev, get_ddp_comp_id(priv->path[i]),
+					 get_ddp_comp_id(priv->path[i + 1]));
+
+	mtk_mmsys_ddp_disconnect(mmsys_dev, get_ddp_comp_id(priv->path[i]), next);
+}
+
+static int ovlsys_adaptor_comp_get_id(struct device *dev, struct device_node *node,
+				      enum mtk_ovlsys_adaptor_comp_type type)
+{
+	int alias_id = of_alias_get_id(node, private_comp_stem[type]);
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
+		if (comp_matches[i].type == type &&
+		    comp_matches[i].alias_id == alias_id)
+			return i;
+
+	dev_warn(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
+	return -EINVAL;
+}
+
+static const struct of_device_id mtk_ovlsys_adaptor_comp_dt_ids[] = {
+	{
+		.compatible = "mediatek,mt8196-exdma",
+		.data = (void *)OVLSYS_ADAPTOR_TYPE_EXDMA,
+	}, {
+		.compatible = "mediatek,mt8196-blender",
+		.data = (void *)OVLSYS_ADAPTOR_TYPE_BLENDER,
+	}, {
+		.compatible = "mediatek,mt8196-outproc",
+		.data = (void *)OVLSYS_ADAPTOR_TYPE_OUTPROC,
+	},
+	{},
+};
+
+static int ovlsys_adaptor_comp_init(struct device *dev, struct component_match **match)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+	struct device_node *parent;
+	struct platform_device *comp_pdev;
+	int i;
+
+	parent = dev->parent->parent->of_node->parent;
+
+	for_each_child_of_node_scoped(parent, node) {
+		enum mtk_ovlsys_adaptor_comp_type type;
+		const struct of_device_id *of_id;
+		int id;
+		bool found = false;
+
+		of_id = of_match_node(mtk_ovlsys_adaptor_comp_dt_ids, node);
+		if (!of_id)
+			continue;
+
+		if (!of_device_is_available(node)) {
+			dev_dbg(dev, "Skipping disabled component %pOF\n",
+				node);
+			continue;
+		}
+
+		type = (enum mtk_ovlsys_adaptor_comp_type)(uintptr_t)of_id->data;
+
+		id = ovlsys_adaptor_comp_get_id(dev, node, type);
+		if (id < 0) {
+			dev_warn(dev, "Skipping unknown component %pOF\n",
+				 node);
+			continue;
+		}
+
+		for (i = 0; i < priv->path_size; i++)
+			if (priv->path[i] == id)
+				found = true;
+
+		if (!found)
+			continue;
+
+		comp_pdev = of_find_device_by_node(node);
+		if (!comp_pdev)
+			return -EPROBE_DEFER;
+
+		priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
+
+		drm_of_component_match_add(dev, match, component_compare_of, node);
+		dev_dbg(dev, "Adding component match for %pOF\n", node);
+	}
+
+	if (!*match) {
+		dev_err(dev, "No match device for ovlsys_adaptor\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int mtk_disp_ovlsys_adaptor_comp_bind(struct device *dev, struct device *master,
+					     void *data)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+
+	if (!priv->children_bound)
+		return -EPROBE_DEFER;
+
+	return 0;
+}
+
+static void mtk_disp_ovlsys_adaptor_comp_unbind(struct device *dev, struct device *master,
+						void *data)
+{
+}
+
+static const struct component_ops mtk_disp_ovlsys_adaptor_comp_ops = {
+	.bind	= mtk_disp_ovlsys_adaptor_comp_bind,
+	.unbind = mtk_disp_ovlsys_adaptor_comp_unbind,
+};
+
+static int mtk_disp_ovlsys_adaptor_master_bind(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+	int ret, i;
+
+	ret = component_bind_all(dev, priv->mmsys_dev);
+
+	if (ret)
+		return dev_err_probe(dev, ret, "component_bind_all failed!\n");
+
+	priv->children_bound = true;
+	priv->layer_nr = 0;
+
+	for (i = 0; i < priv->path_size; i++)
+		if (comp_matches[priv->path[i]].type == OVLSYS_ADAPTOR_TYPE_BLENDER)
+			priv->layer_nr++;
+
+	return 0;
+}
+
+static void mtk_disp_ovlsys_adaptor_master_unbind(struct device *dev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv = dev_get_drvdata(dev);
+
+	priv->children_bound = false;
+}
+
+static const struct component_master_ops mtk_disp_ovlsys_adaptor_master_ops = {
+	.bind		= mtk_disp_ovlsys_adaptor_master_bind,
+	.unbind		= mtk_disp_ovlsys_adaptor_master_unbind,
+};
+
+static int mtk_disp_ovlsys_adaptor_probe(struct platform_device *pdev)
+{
+	struct mtk_disp_ovlsys_adaptor *priv;
+	struct device *dev = &pdev->dev;
+	struct component_match *match = NULL;
+	struct mtk_ovlsys_platform_data *ovlsys_priv;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, priv);
+
+	ovlsys_priv = pdev->dev.platform_data;
+	priv->mmsys_dev = ovlsys_priv->mmsys_dev;
+
+	if (ovlsys_priv->use_path == CRTC_MAIN) {
+		priv->path = mt8196_mtk_ovl_main;
+		priv->path_size = ARRAY_SIZE(mt8196_mtk_ovl_main);
+	} else if (ovlsys_priv->use_path == CRTC_EXT) {
+		priv->path = mt8196_mtk_ovl_ext;
+		priv->path_size = ARRAY_SIZE(mt8196_mtk_ovl_ext);
+	} else if (ovlsys_priv->use_path == CRTC_THIRD) {
+		priv->path = mt8196_mtk_ovl_third;
+		priv->path_size = ARRAY_SIZE(mt8196_mtk_ovl_third);
+	}
+
+	ret = ovlsys_adaptor_comp_init(dev, &match);
+	if (ret < 0)
+		return ret;
+
+	component_master_add_with_match(dev, &mtk_disp_ovlsys_adaptor_master_ops, match);
+
+	pm_runtime_enable(dev);
+
+	ret = component_add(dev, &mtk_disp_ovlsys_adaptor_comp_ops);
+	if (ret != 0) {
+		pm_runtime_disable(dev);
+		dev_err(dev, "Failed to add component: %d\n", ret);
+	}
+
+	return ret;
+}
+
+static void mtk_disp_ovlsys_adaptor_remove(struct platform_device *pdev)
+{
+	component_master_del(&pdev->dev, &mtk_disp_ovlsys_adaptor_master_ops);
+	pm_runtime_disable(&pdev->dev);
+}
+
+struct platform_driver mtk_disp_ovlsys_adaptor_driver = {
+	.probe		= mtk_disp_ovlsys_adaptor_probe,
+	.remove		= mtk_disp_ovlsys_adaptor_remove,
+	.driver		= {
+		.name	= "mediatek-disp-ovlsys-adaptor",
+		.owner	= THIS_MODULE,
+	},
+};
+
+MODULE_AUTHOR("Nancy Lin <nancy.lin at mediatek.com>");
+MODULE_DESCRIPTION("MediaTek Ovlsys Adaptor Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index f7b9c7a982a7..4cf48fe7f0f1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -429,32 +429,41 @@ static bool mtk_drm_get_all_drm_priv(struct device *dev)
 	return false;
 }
 
-static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
+static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id, int *use_path)
 {
 	const struct mtk_mmsys_driver_data *drv_data = private->data;
-	int i;
+	int i, path = MAX_CRTC;
 
 	if (drv_data->main_path)
 		for (i = 0; i < drv_data->main_len; i++)
-			if (drv_data->main_path[i] == comp_id)
-				return true;
+			if (drv_data->main_path[i] == comp_id) {
+				path = CRTC_MAIN;
+				goto found;
+			}
 
 	if (drv_data->ext_path)
 		for (i = 0; i < drv_data->ext_len; i++)
-			if (drv_data->ext_path[i] == comp_id)
-				return true;
-
+			if (drv_data->ext_path[i] == comp_id) {
+				path = CRTC_EXT;
+				goto found;
+			}
 	if (drv_data->third_path)
 		for (i = 0; i < drv_data->third_len; i++)
-			if (drv_data->third_path[i] == comp_id)
-				return true;
+			if (drv_data->third_path[i] == comp_id) {
+				path = CRTC_THIRD;
+				goto found;
+			}
 
 	if (drv_data->num_conn_routes)
 		for (i = 0; i < drv_data->num_conn_routes; i++)
 			if (drv_data->conn_routes[i].route_ddp == comp_id)
-				return true;
+				goto found;
 
 	return false;
+found:
+	if (use_path)
+		*use_path = path;
+	return true;
 }
 
 static int mtk_drm_kms_init(struct drm_device *drm)
@@ -1055,6 +1064,26 @@ static int mtk_drm_of_ddp_path_build(struct device *dev, struct device_node *nod
 	return 0;
 }
 
+static void mtk_drm_ovl_adaptor_probe(struct device *dev, struct mtk_drm_private *private,
+				      struct component_match **match, enum mtk_ddp_comp_id id)
+{
+	struct platform_device *ovl_adaptor;
+	struct mtk_drm_ovlsys_private ovlsys_priv;
+	bool is_ovlsys = (id != DDP_COMPONENT_DRM_OVL_ADAPTOR);
+	char *dev_name = is_ovlsys ? "mediatek-disp-ovlsys-adaptor" : "mediatek-disp-ovl-adaptor";
+	void *drv_data = is_ovlsys ? (void *)&ovlsys_priv : (void *)private->mmsys_dev;
+	size_t data_size = is_ovlsys ? sizeof(ovlsys_priv) : sizeof(*private->mmsys_dev);
+
+	if (mtk_drm_find_mmsys_comp(private, id, &ovlsys_priv.use_path)) {
+		ovlsys_priv.mmsys_dev = private->mmsys_dev;
+		ovl_adaptor = platform_device_register_data(dev, dev_name, PLATFORM_DEVID_AUTO,
+							    drv_data, data_size);
+		private->ddp_comp[id].dev = &ovl_adaptor->dev;
+		mtk_ddp_comp_init(NULL, &private->ddp_comp[id], id);
+		component_match_add(dev, match, compare_dev, &ovl_adaptor->dev);
+	}
+}
+
 static int mtk_drm_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -1064,7 +1093,6 @@ static int mtk_drm_probe(struct platform_device *pdev)
 	struct mtk_mmsys_driver_data *mtk_drm_data;
 	struct device_node *node;
 	struct component_match *match = NULL;
-	struct platform_device *ovl_adaptor;
 	int ret;
 	int i;
 
@@ -1110,17 +1138,11 @@ static int mtk_drm_probe(struct platform_device *pdev)
 	if (!private->all_drm_private)
 		return -ENOMEM;
 
-	/* Bringup ovl_adaptor */
-	if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) {
-		ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",
-							    PLATFORM_DEVID_AUTO,
-							    (void *)private->mmsys_dev,
-							    sizeof(*private->mmsys_dev));
-		private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev;
-		mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR],
-				  DDP_COMPONENT_DRM_OVL_ADAPTOR);
-		component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev);
-	}
+	/* Bringup ovl_adaptor and ovlsys_adaptor*/
+	mtk_drm_ovl_adaptor_probe(dev, private, &match, DDP_COMPONENT_DRM_OVL_ADAPTOR);
+	mtk_drm_ovl_adaptor_probe(dev, private, &match, DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0);
+	mtk_drm_ovl_adaptor_probe(dev, private, &match, DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1);
+	mtk_drm_ovl_adaptor_probe(dev, private, &match, DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2);
 
 	/* Iterate over sibling DISP function blocks */
 	for_each_child_of_node(phandle->parent, node) {
@@ -1155,7 +1177,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 			continue;
 		}
 
-		if (!mtk_drm_find_mmsys_comp(private, comp_id))
+		if (!mtk_drm_find_mmsys_comp(private, comp_id, NULL))
 			continue;
 
 		private->comp_node[comp_id] = of_node_get(node);
@@ -1283,6 +1305,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_outproc_driver,
 	&mtk_disp_ovl_adaptor_driver,
 	&mtk_disp_ovl_driver,
+	&mtk_disp_ovlsys_adaptor_driver,
 	&mtk_disp_rdma_driver,
 	&mtk_dpi_driver,
 	&mtk_drm_platform_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c4717c37b0f1..54f320244511 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -11,7 +11,9 @@
 
 #define MAX_CONNECTOR	2
 #define DDP_COMPONENT_DRM_OVL_ADAPTOR (DDP_COMPONENT_ID_MAX + 1)
-#define DDP_COMPONENT_DRM_ID_MAX (DDP_COMPONENT_DRM_OVL_ADAPTOR + 1)
+#define DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0 (DDP_COMPONENT_DRM_OVL_ADAPTOR + 1)
+#define DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1 (DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0 + 1)
+#define DDP_COMPONENT_DRM_ID_MAX (DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1 + 1)
 
 enum mtk_crtc_path {
 	CRTC_MAIN,
@@ -69,6 +71,11 @@ struct mtk_drm_private {
 	struct mtk_drm_private **all_drm_private;
 };
 
+struct mtk_ovlsys_platform_data {
+	struct device *mmsys_dev;
+	unsigned int use_path;
+};
+
 extern struct platform_driver mtk_disp_aal_driver;
 extern struct platform_driver mtk_disp_blender_driver;
 extern struct platform_driver mtk_disp_ccorr_driver;
@@ -79,6 +86,7 @@ extern struct platform_driver mtk_disp_merge_driver;
 extern struct platform_driver mtk_disp_outproc_driver;
 extern struct platform_driver mtk_disp_ovl_adaptor_driver;
 extern struct platform_driver mtk_disp_ovl_driver;
+extern struct platform_driver mtk_disp_ovlsys_adaptor_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
 extern struct platform_driver mtk_dpi_driver;
 extern struct platform_driver mtk_dsi_driver;
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:22 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:22 +0800
Subject: [PATCH v3 10/17] drm/mediatek: Export OVL formats definitions and format conversion API
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-11-paul-pl.chen@mediatek.com>

From: Nancy Lin <nancy.lin at mediatek.com>

In upcoming SoCs, the OVL component will be divided into multiple
smaller hardware units to enhance flexibility. To facilitate this
transition, the OVL format definitions and format conversion API
should be exported for reuse across these units.

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 214 ++++++++++++++----------
 drivers/gpu/drm/mediatek/mtk_disp_ovl.h |  28 ++++
 2 files changed, 150 insertions(+), 92 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl.h

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index d0581c4e3c99..a516b7c82b5a 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -3,8 +3,6 @@
  * Copyright (c) 2015 MediaTek Inc.
  */
 
-#include <drm/drm_blend.h>
-#include <drm/drm_fourcc.h>
 #include <drm/drm_framebuffer.h>
 
 #include <linux/clk.h>
@@ -18,6 +16,7 @@
 #include "mtk_crtc.h"
 #include "mtk_ddp_comp.h"
 #include "mtk_disp_drv.h"
+#include "mtk_disp_ovl.h"
 #include "mtk_drm_drv.h"
 
 #define DISP_REG_OVL_INTEN			0x0004
@@ -62,22 +61,15 @@
 /* OVL_CON_RGB_SWAP works only if OVL_CON_CLRFMT_MAN is enabled */
 #define OVL_CON_RGB_SWAP	BIT(25)
 
-#define OVL_CON_CLRFMT_RGB	(1 << 12)
-#define OVL_CON_CLRFMT_ARGB8888	(2 << 12)
-#define OVL_CON_CLRFMT_RGBA8888	(3 << 12)
-#define OVL_CON_CLRFMT_ABGR8888	(OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP)
-#define OVL_CON_CLRFMT_BGRA8888	(OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP)
-#define OVL_CON_CLRFMT_UYVY	(4 << 12)
-#define OVL_CON_CLRFMT_YUYV	(5 << 12)
-#define OVL_CON_MTX_YUV_TO_RGB	(6 << 16)
-#define OVL_CON_CLRFMT_PARGB8888 ((3 << 12) | OVL_CON_CLRFMT_MAN)
-#define OVL_CON_CLRFMT_PABGR8888 (OVL_CON_CLRFMT_PARGB8888 | OVL_CON_RGB_SWAP)
-#define OVL_CON_CLRFMT_PBGRA8888 (OVL_CON_CLRFMT_PARGB8888 | OVL_CON_BYTE_SWAP)
-#define OVL_CON_CLRFMT_PRGBA8888 (OVL_CON_CLRFMT_PABGR8888 | OVL_CON_BYTE_SWAP)
-#define OVL_CON_CLRFMT_RGB565(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \
-					0 : OVL_CON_CLRFMT_RGB)
-#define OVL_CON_CLRFMT_RGB888(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \
-					OVL_CON_CLRFMT_RGB : 0)
+#define OVL_CON_CLRFMT_RGB565(shift)	(0 << (shift))
+#define OVL_CON_CLRFMT_RGB888(shift)	(1 << (shift))
+#define OVL_CON_CLRFMT_ARGB8888(shift)	(2 << (shift))
+#define OVL_CON_CLRFMT_RGBA8888(shift)	(3 << (shift))
+#define OVL_CON_CLRFMT_UYVY(shift)	(4 << (shift))
+#define OVL_CON_CLRFMT_YUYV(shift)	(5 << (shift))
+#define OVL_CON_MTX_YUV_TO_RGB		(6 << 16)
+#define OVL_CON_CLRFMT_PARGB8888(shift, man) ((3 << (shift)) | (man))
+
 #define	OVL_CON_AEN		BIT(8)
 #define	OVL_CON_ALPHA		0xff
 #define	OVL_CON_VIRT_FLIP	BIT(9)
@@ -85,23 +77,7 @@
 
 #define OVL_COLOR_ALPHA		GENMASK(31, 24)
 
-static inline bool is_10bit_rgb(u32 fmt)
-{
-	switch (fmt) {
-	case DRM_FORMAT_XRGB2101010:
-	case DRM_FORMAT_ARGB2101010:
-	case DRM_FORMAT_RGBX1010102:
-	case DRM_FORMAT_RGBA1010102:
-	case DRM_FORMAT_XBGR2101010:
-	case DRM_FORMAT_ABGR2101010:
-	case DRM_FORMAT_BGRX1010102:
-	case DRM_FORMAT_BGRA1010102:
-		return true;
-	}
-	return false;
-}
-
-static const u32 mt8173_formats[] = {
+const u32 mt8173_ovl_formats[] = {
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_ARGB8888,
 	DRM_FORMAT_BGRX8888,
@@ -115,7 +91,9 @@ static const u32 mt8173_formats[] = {
 	DRM_FORMAT_YUYV,
 };
 
-static const u32 mt8195_formats[] = {
+const size_t mt8173_ovl_formats_len = ARRAY_SIZE(mt8173_ovl_formats);
+
+const u32 mt8195_ovl_formats[] = {
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_ARGB8888,
 	DRM_FORMAT_XRGB2101010,
@@ -139,6 +117,8 @@ static const u32 mt8195_formats[] = {
 	DRM_FORMAT_YUYV,
 };
 
+const size_t mt8195_ovl_formats_len = ARRAY_SIZE(mt8195_ovl_formats);
+
 struct mtk_disp_ovl_data {
 	unsigned int addr;
 	unsigned int gmc_bits;
@@ -167,6 +147,22 @@ struct mtk_disp_ovl {
 	void				*vblank_cb_data;
 };
 
+bool mtk_ovl_is_10bit_rgb(unsigned int fmt)
+{
+	switch (fmt) {
+	case DRM_FORMAT_XRGB2101010:
+	case DRM_FORMAT_ARGB2101010:
+	case DRM_FORMAT_RGBX1010102:
+	case DRM_FORMAT_RGBA1010102:
+	case DRM_FORMAT_XBGR2101010:
+	case DRM_FORMAT_ABGR2101010:
+	case DRM_FORMAT_BGRX1010102:
+	case DRM_FORMAT_BGRA1010102:
+		return true;
+	}
+	return false;
+}
+
 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
 {
 	struct mtk_disp_ovl *priv = dev_id;
@@ -295,7 +291,7 @@ static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format,
 	if (!ovl->data->supports_clrfmt_ext)
 		return;
 
-	if (is_10bit_rgb(format))
+	if (mtk_ovl_is_10bit_rgb(format))
 		bit_depth = OVL_CON_CLRFMT_10_BIT;
 
 	mtk_ddp_write_mask(cmdq_pkt, OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx),
@@ -394,10 +390,8 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int idx,
 		      DISP_REG_OVL_RDMA_CTRL(idx));
 }
 
-static unsigned int mtk_ovl_fmt_convert(struct mtk_disp_ovl *ovl,
-					struct mtk_plane_state *state)
+unsigned int mtk_ovl_get_blend_mode(struct mtk_plane_state *state, unsigned int blend_modes)
 {
-	unsigned int fmt = state->pending.format;
 	unsigned int blend_mode = DRM_MODE_BLEND_COVERAGE;
 
 	/*
@@ -412,52 +406,102 @@ static unsigned int mtk_ovl_fmt_convert(struct mtk_disp_ovl *ovl,
 	 * will get an error return from drm_plane_create_blend_mode_property() and
 	 * state->base.pixel_blend_mode should not be used.
 	 */
-	if (ovl->data->blend_modes & BIT(DRM_MODE_BLEND_PREMULTI))
+	if (blend_modes & BIT(DRM_MODE_BLEND_PREMULTI))
 		blend_mode = state->base.pixel_blend_mode;
 
+	return blend_mode;
+}
+
+unsigned int mtk_ovl_fmt_convert(unsigned int fmt, unsigned int blend_mode,
+				 bool fmt_rgb565_is_0, bool color_convert,
+				 u8 clrfmt_shift, u32 clrfmt_man, u32 byte_swap, u32 rgb_swap)
+{
+	unsigned int con = 0;
+	bool need_byte_swap = false, need_rgb_swap = false;
+
 	switch (fmt) {
 	default:
 	case DRM_FORMAT_RGB565:
-		return OVL_CON_CLRFMT_RGB565(ovl);
+		con = fmt_rgb565_is_0 ?
+			OVL_CON_CLRFMT_RGB565(clrfmt_shift) : OVL_CON_CLRFMT_RGB888(clrfmt_shift);
+	break;
 	case DRM_FORMAT_BGR565:
-		return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP;
+		con = fmt_rgb565_is_0 ?
+			OVL_CON_CLRFMT_RGB565(clrfmt_shift) : OVL_CON_CLRFMT_RGB888(clrfmt_shift);
+		need_byte_swap = true;	/* RGB565 -> BGR565 */
+	break;
 	case DRM_FORMAT_RGB888:
-		return OVL_CON_CLRFMT_RGB888(ovl);
+		con = fmt_rgb565_is_0 ?
+			OVL_CON_CLRFMT_RGB888(clrfmt_shift) : OVL_CON_CLRFMT_RGB565(clrfmt_shift);
+	break;
 	case DRM_FORMAT_BGR888:
-		return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
+		con = fmt_rgb565_is_0 ?
+			OVL_CON_CLRFMT_RGB888(clrfmt_shift) : OVL_CON_CLRFMT_RGB565(clrfmt_shift);
+		need_byte_swap = true;	/* RGB888 -> BGR888 */
+	break;
 	case DRM_FORMAT_RGBX8888:
 	case DRM_FORMAT_RGBA8888:
 	case DRM_FORMAT_RGBX1010102:
 	case DRM_FORMAT_RGBA1010102:
-		return blend_mode == DRM_MODE_BLEND_COVERAGE ?
-		       OVL_CON_CLRFMT_RGBA8888 :
-		       OVL_CON_CLRFMT_PRGBA8888;
+		if (blend_mode == DRM_MODE_BLEND_COVERAGE) {
+			con = OVL_CON_CLRFMT_RGBA8888(clrfmt_shift);
+		} else {
+			con = OVL_CON_CLRFMT_PARGB8888(clrfmt_shift, clrfmt_man);
+			need_byte_swap = true;	/* PARGB8888 -> PBGRA8888 */
+			need_rgb_swap = true;	/* PBGRA8888 -> PRGBA8888 */
+		}
+	break;
 	case DRM_FORMAT_BGRX8888:
 	case DRM_FORMAT_BGRA8888:
 	case DRM_FORMAT_BGRX1010102:
 	case DRM_FORMAT_BGRA1010102:
-		return blend_mode == DRM_MODE_BLEND_COVERAGE ?
-		       OVL_CON_CLRFMT_BGRA8888 :
-		       OVL_CON_CLRFMT_PBGRA8888;
+		if (blend_mode == DRM_MODE_BLEND_COVERAGE) {
+			con = OVL_CON_CLRFMT_RGBA8888(clrfmt_shift);
+			need_byte_swap = true;	/* RGB8888 -> BGR8888 */
+		} else {
+			con = OVL_CON_CLRFMT_PARGB8888(clrfmt_shift, clrfmt_man);
+			need_byte_swap = true;	/* PARGB8888 -> PBGRA8888 */
+		}
+	break;
 	case DRM_FORMAT_XRGB8888:
 	case DRM_FORMAT_ARGB8888:
 	case DRM_FORMAT_XRGB2101010:
 	case DRM_FORMAT_ARGB2101010:
-		return blend_mode == DRM_MODE_BLEND_COVERAGE ?
-		       OVL_CON_CLRFMT_ARGB8888 :
-		       OVL_CON_CLRFMT_PARGB8888;
+		if (blend_mode == DRM_MODE_BLEND_COVERAGE)
+			con = OVL_CON_CLRFMT_ARGB8888(clrfmt_shift);
+		else
+			con = OVL_CON_CLRFMT_PARGB8888(clrfmt_shift, clrfmt_man);
+	break;
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_ABGR8888:
 	case DRM_FORMAT_XBGR2101010:
 	case DRM_FORMAT_ABGR2101010:
-		return blend_mode == DRM_MODE_BLEND_COVERAGE ?
-		       OVL_CON_CLRFMT_ABGR8888 :
-		       OVL_CON_CLRFMT_PABGR8888;
+		if (blend_mode == DRM_MODE_BLEND_COVERAGE) {
+			con = OVL_CON_CLRFMT_ARGB8888(clrfmt_shift);
+			need_rgb_swap = true;	/* ARGB8888 -> ABGR8888 */
+		} else {
+			con = OVL_CON_CLRFMT_PARGB8888(clrfmt_shift, clrfmt_man);
+			need_rgb_swap = true;	/* PARGB8888 -> PABGR8888 */
+		}
+	break;
 	case DRM_FORMAT_UYVY:
-		return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB;
+		con = OVL_CON_CLRFMT_UYVY(clrfmt_shift);
+	break;
 	case DRM_FORMAT_YUYV:
-		return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB;
+		con = OVL_CON_CLRFMT_YUYV(clrfmt_shift);
+	break;
 	}
+
+	if (color_convert)
+		con |= OVL_CON_MTX_YUV_TO_RGB;
+
+	if (need_byte_swap)
+		con |= byte_swap;
+
+	if (need_rgb_swap)
+		con |= rgb_swap;
+
+	return con;
 }
 
 static void mtk_ovl_afbc_layer_config(struct mtk_disp_ovl *ovl,
@@ -504,7 +548,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
 		return;
 	}
 
-	con = mtk_ovl_fmt_convert(ovl, state);
+	con = mtk_ovl_fmt_convert(fmt, blend_mode, ovl->data->fmt_rgb565_is_0, true,
+				  12, OVL_CON_CLRFMT_MAN, OVL_CON_BYTE_SWAP, OVL_CON_RGB_SWAP);
 	if (state->base.fb) {
 		con |= state->base.alpha & OVL_CON_ALPHA;
 
@@ -514,15 +559,6 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
 		 */
 		if (blend_mode || state->base.fb->format->has_alpha)
 			con |= OVL_CON_AEN;
-
-		/*
-		 * Although the alpha channel can be ignored, CONST_BLD must be enabled
-		 * for XRGB format, otherwise OVL will still read the value from memory.
-		 * For RGB888 related formats, whether CONST_BLD is enabled or not won't
-		 * affect the result. Therefore we use !has_alpha as the condition.
-		 */
-		if (blend_mode == DRM_MODE_BLEND_PIXEL_NONE || !state->base.fb->format->has_alpha)
-			ignore_pixel_alpha = OVL_CONST_BLEND;
 	}
 
 	/*
@@ -660,8 +696,8 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
 	.gmc_bits = 8,
 	.layer_nr = 4,
 	.fmt_rgb565_is_0 = false,
-	.formats = mt8173_formats,
-	.num_formats = ARRAY_SIZE(mt8173_formats),
+	.formats = mt8173_ovl_formats,
+	.num_formats = mt8173_ovl_formats_len,
 };
 
 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
@@ -669,8 +705,8 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
 	.gmc_bits = 8,
 	.layer_nr = 4,
 	.fmt_rgb565_is_0 = true,
-	.formats = mt8173_formats,
-	.num_formats = ARRAY_SIZE(mt8173_formats),
+	.formats = mt8173_ovl_formats,
+	.num_formats = mt8173_ovl_formats_len,
 };
 
 static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
@@ -678,8 +714,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
 	.gmc_bits = 10,
 	.layer_nr = 4,
 	.fmt_rgb565_is_0 = true,
-	.formats = mt8173_formats,
-	.num_formats = ARRAY_SIZE(mt8173_formats),
+	.formats = mt8173_ovl_formats,
+	.num_formats = mt8173_ovl_formats_len,
 };
 
 static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
@@ -687,8 +723,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
 	.gmc_bits = 10,
 	.layer_nr = 2,
 	.fmt_rgb565_is_0 = true,
-	.formats = mt8173_formats,
-	.num_formats = ARRAY_SIZE(mt8173_formats),
+	.formats = mt8173_ovl_formats,
+	.num_formats = mt8173_ovl_formats_len,
 };
 
 static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
@@ -697,11 +733,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
 	.layer_nr = 4,
 	.fmt_rgb565_is_0 = true,
 	.smi_id_en = true,
-	.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
-		       BIT(DRM_MODE_BLEND_COVERAGE) |
-		       BIT(DRM_MODE_BLEND_PIXEL_NONE),
-	.formats = mt8173_formats,
-	.num_formats = ARRAY_SIZE(mt8173_formats),
+	.blend_modes = MTK_OVL_SUPPORT_BLEND_MODES,
+	.formats = mt8173_ovl_formats,
+	.num_formats = mt8173_ovl_formats_len,
 };
 
 static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
@@ -710,11 +744,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
 	.layer_nr = 2,
 	.fmt_rgb565_is_0 = true,
 	.smi_id_en = true,
-	.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
-		       BIT(DRM_MODE_BLEND_COVERAGE) |
-		       BIT(DRM_MODE_BLEND_PIXEL_NONE),
-	.formats = mt8173_formats,
-	.num_formats = ARRAY_SIZE(mt8173_formats),
+	.blend_modes = MTK_OVL_SUPPORT_BLEND_MODES,
+	.formats = mt8173_ovl_formats,
+	.num_formats = mt8173_ovl_formats_len,
 };
 
 static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
@@ -724,11 +756,9 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
 	.fmt_rgb565_is_0 = true,
 	.smi_id_en = true,
 	.supports_afbc = true,
-	.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
-		       BIT(DRM_MODE_BLEND_COVERAGE) |
-		       BIT(DRM_MODE_BLEND_PIXEL_NONE),
-	.formats = mt8195_formats,
-	.num_formats = ARRAY_SIZE(mt8195_formats),
+	.blend_modes = MTK_OVL_SUPPORT_BLEND_MODES,
+	.formats = mt8195_ovl_formats,
+	.num_formats = mt8195_ovl_formats_len,
 	.supports_clrfmt_ext = true,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
new file mode 100644
index 000000000000..3f7d7d54479d
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#ifndef __MTK_DISP_OVL_H__
+#define __MTK_DISP_OVL_H__
+
+#include <drm/drm_blend.h>
+#include <drm/drm_fourcc.h>
+
+#define MTK_OVL_SUPPORT_BLEND_MODES \
+	(BIT(DRM_MODE_BLEND_PREMULTI) | \
+	 BIT(DRM_MODE_BLEND_COVERAGE) | \
+	 BIT(DRM_MODE_BLEND_PIXEL_NONE))
+
+extern const u32 mt8173_ovl_formats[];
+extern const size_t mt8173_ovl_formats_len;
+extern const u32 mt8195_ovl_formats[];
+extern const size_t mt8195_ovl_formats_len;
+
+bool mtk_ovl_is_10bit_rgb(unsigned int fmt);
+unsigned int mtk_ovl_get_blend_mode(struct mtk_plane_state *state, unsigned int blend_modes);
+unsigned int mtk_ovl_fmt_convert(unsigned int fmt, unsigned int blend_mode,
+				 bool fmt_rgb565_is_0, bool color_convert,
+				 u8 clrfmt_shift, u32 clrfmt_man, u32 byte_swap, u32 rgb_swap);
+
+#endif
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:25 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:25 +0800
Subject: [PATCH v3 13/17] drm/mediatek: add BLENDER support for MT8196
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-14-paul-pl.chen@mediatek.com>

From: Paul-pl Chen <paul-pl.chen at mediatek.com>

BLENDER executes the alpha blending function for overlapping
layers from different sources, which is the primary function
of the overlapping system.

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c     |   1 +
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h     |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_blender.c | 264 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_blender.h |  10 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |  12 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 8 files changed, 291 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_blender.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_blender.h

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index db92f4fb353d..a7b9ebe27f68 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -3,6 +3,7 @@
 mediatek-drm-y := mtk_crtc.o \
 		  mtk_ddp_comp.o \
 		  mtk_disp_aal.o \
+		  mtk_disp_blender.o \
 		  mtk_disp_ccorr.o \
 		  mtk_disp_color.o \
 		  mtk_disp_exdma.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index 3e0739d8e6f1..e65c6df987f2 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -445,6 +445,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DP_INTF] = "dp-intf",
 	[MTK_DPI] = "dpi",
 	[MTK_DSI] = "dsi",
+	[MTK_OVL_BLENDER] = "blender",
 	[MTK_OVL_EXDMA] = "exdma",
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index 86dc0ee3924c..075ba5683f93 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -43,6 +43,7 @@ enum mtk_ddp_comp_type {
 	MTK_DPI,
 	MTK_DP_INTF,
 	MTK_DSI,
+	MTK_OVL_BLENDER,
 	MTK_OVL_EXDMA,
 	MTK_DDP_COMP_TYPE_MAX,
 };
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_blender.c b/drivers/gpu/drm/mediatek/mtk_disp_blender.c
new file mode 100644
index 000000000000..7c73bce99592
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_blender.c
@@ -0,0 +1,264 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <drm/drm_blend.h>
+#include <drm/drm_framebuffer.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#include "mtk_crtc.h"
+#include "mtk_ddp_comp.h"
+#include "mtk_disp_drv.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_blender.h"
+#include "mtk_disp_ovl.h"
+
+#define DISP_REG_OVL_BLD_DATAPATH_CON			0x010
+#define OVL_BLD_BGCLR_IN_SEL					BIT(0)
+#define OVL_BLD_BGCLR_OUT_TO_PROC				BIT(4)
+#define OVL_BLD_BGCLR_OUT_TO_NEXT_LAYER				BIT(5)
+#define DISP_REG_OVL_BLD_EN				0x020
+#define OVL_BLD_EN						BIT(0)
+#define OVL_BLD_FORCE_RELAY_MODE				BIT(4)
+#define OVL_BLD_RELAY_MODE					BIT(5)
+#define DISP_REG_OVL_BLD_RST				0x024
+#define OVL_BLD_RST						BIT(0)
+#define DISP_REG_OVL_BLD_SHADOW_CTRL			0x028
+#define OVL_BLD_BYPASS_SHADOW					BIT(2)
+#define DISP_REG_OVL_BLD_BGCLR_BALCK			0xff000000
+#define DISP_REG_OVL_BLD_ROI_SIZE			0x030
+#define DISP_REG_OVL_BLD_L_EN				0x040
+#define OVL_BLD_L_EN						BIT(0)
+#define DISP_REG_OVL_BLD_OFFSET				0x044
+#define DISP_REG_OVL_BLD_SRC_SIZE			0x048
+#define DISP_REG_OVL_BLD_L0_CLRFMT			0x050
+#define OVL_BLD_CON_FLD_CLRFMT					GENMASK(3, 0)
+#define OVL_BLD_CON_CLRFMT_MAN					BIT(4)
+#define OVL_BLD_CON_FLD_CLRFMT_NB				GENMASK(9, 8)
+#define OVL_BLD_CON_CLRFMT_NB_10_BIT				BIT(8)
+#define OVL_BLD_CON_BYTE_SWAP					BIT(16)
+#define OVL_BLD_CON_RGB_SWAP					BIT(17)
+#define DISP_REG_OVL_BLD_BGCLR_CLR			0x104
+#define DISP_REG_OVL_BLD_L_CON2				0x200
+#define OVL_BLD_L_ALPHA						GENMASK(7, 0)
+#define OVL_BLD_L_ALPHA_EN					BIT(12)
+#define DISP_REG_OVL_BLD_L0_ALPHA_SEL			0x208
+#define OVL_BLD_L0_CONST					BIT(24)
+#define DISP_REG_OVL_BLD_L0_CLR				0x20c
+#define OVL_BLD_CON_CLRFMT_MAN					BIT(4)
+
+struct mtk_disp_blender {
+	void __iomem		*regs;
+	struct clk		*clk;
+	struct cmdq_client_reg	cmdq_reg;
+};
+
+void mtk_disp_blender_layer_config(struct device *dev, struct mtk_plane_state *state,
+				   struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_blender *priv = dev_get_drvdata(dev);
+	struct mtk_plane_pending_state *pending = &state->pending;
+	u32 alpha, clrfmt, ignore_pixel_alpha = 0;
+	u32 blend_mode = mtk_ovl_get_blend_mode(state, MTK_OVL_SUPPORT_BLEND_MODES);
+
+	if (!pending->enable) {
+		mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_REG_OVL_BLD_L_EN);
+		return;
+	}
+
+	mtk_ddp_write(cmdq_pkt, pending->y << 16 | pending->x, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_OVL_BLD_OFFSET);
+
+	mtk_ddp_write(cmdq_pkt, pending->height << 16 | pending->width, &priv->cmdq_reg,
+		      priv->regs, DISP_REG_OVL_BLD_SRC_SIZE);
+
+	clrfmt = mtk_ovl_fmt_convert(pending->format, blend_mode, true, false, 0,
+				     OVL_BLD_CON_CLRFMT_MAN, OVL_BLD_CON_BYTE_SWAP,
+				     OVL_BLD_CON_RGB_SWAP);
+	clrfmt |= mtk_ovl_is_10bit_rgb(pending->format) ? OVL_BLD_CON_CLRFMT_NB_10_BIT : 0;
+	mtk_ddp_write_mask(cmdq_pkt, clrfmt, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_BLD_L0_CLRFMT, OVL_BLD_CON_CLRFMT_MAN |
+			   OVL_BLD_CON_RGB_SWAP |  OVL_BLD_CON_BYTE_SWAP |
+			   OVL_BLD_CON_FLD_CLRFMT | OVL_BLD_CON_FLD_CLRFMT_NB);
+
+	if (mtk_ovl_is_ignore_pixel_alpha(state, blend_mode))
+		ignore_pixel_alpha = OVL_BLD_L0_CONST;
+	mtk_ddp_write_mask(cmdq_pkt, ignore_pixel_alpha, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_BLD_L0_ALPHA_SEL, OVL_BLD_L0_CONST);
+
+	alpha = (OVL_BLD_L_ALPHA & (state->base.alpha >> 8)) | OVL_BLD_L_ALPHA_EN;
+	mtk_ddp_write_mask(cmdq_pkt, alpha, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_BLD_L_CON2, OVL_BLD_L_ALPHA_EN | OVL_BLD_L_ALPHA);
+
+	mtk_ddp_write(cmdq_pkt, OVL_BLD_L_EN, &priv->cmdq_reg, priv->regs, DISP_REG_OVL_BLD_L_EN);
+}
+
+void mtk_disp_blender_config(struct device *dev, unsigned int w,
+			     unsigned int h, unsigned int vrefresh,
+			     unsigned int bpc, bool most_top,
+			     bool most_bottom, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_blender *priv = dev_get_drvdata(dev);
+	u32 datapath;
+
+	dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_OVL_BLD_ROI_SIZE);
+	mtk_ddp_write(cmdq_pkt, DISP_REG_OVL_BLD_BGCLR_BALCK, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_OVL_BLD_BGCLR_CLR);
+
+	/*
+	 * The input source of blender layer can be EXDMA layer output or
+	 * the blender constant layer itself.
+	 * This color setting is configured for the blender constant layer.
+	 */
+	mtk_ddp_write(cmdq_pkt, DISP_REG_OVL_BLD_BGCLR_BALCK, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_OVL_BLD_L0_CLR);
+
+	if (most_top)
+		datapath = OVL_BLD_BGCLR_OUT_TO_PROC;
+	else
+		datapath = OVL_BLD_BGCLR_OUT_TO_NEXT_LAYER;
+	/*
+	 * The primary input is from EXDMA and the second input
+	 * is optionally from another blender
+	 */
+	if (!most_bottom)
+		datapath |= OVL_BLD_BGCLR_IN_SEL;
+
+	mtk_ddp_write_mask(cmdq_pkt, datapath,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_OVL_BLD_DATAPATH_CON,
+			   OVL_BLD_BGCLR_OUT_TO_PROC | OVL_BLD_BGCLR_OUT_TO_NEXT_LAYER |
+			   OVL_BLD_BGCLR_IN_SEL);
+}
+
+void mtk_disp_blender_start(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_blender *priv = dev_get_drvdata(dev);
+
+	mtk_ddp_write_mask(cmdq_pkt, OVL_BLD_BYPASS_SHADOW, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_BLD_SHADOW_CTRL, OVL_BLD_BYPASS_SHADOW);
+	mtk_ddp_write_mask(cmdq_pkt, OVL_BLD_EN, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_BLD_EN, OVL_BLD_EN);
+}
+
+void mtk_disp_blender_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_blender *priv = dev_get_drvdata(dev);
+
+	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_BLD_EN, OVL_BLD_EN);
+
+	mtk_ddp_write_mask(cmdq_pkt, OVL_BLD_RST, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_BLD_RST, OVL_BLD_RST);
+	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_BLD_RST, OVL_BLD_RST);
+}
+
+int mtk_disp_blender_clk_enable(struct device *dev)
+{
+	struct mtk_disp_blender *priv = dev_get_drvdata(dev);
+
+	return clk_prepare_enable(priv->clk);
+}
+
+void mtk_disp_blender_clk_disable(struct device *dev)
+{
+	struct mtk_disp_blender *priv = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(priv->clk);
+}
+
+u32 mtk_disp_blender_get_blend_modes(struct device *dev)
+{
+	return MTK_OVL_SUPPORT_BLEND_MODES;
+}
+
+static int mtk_disp_blender_bind(struct device *dev, struct device *master,
+				 void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_blender_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_disp_blender_component_ops = {
+	.bind	= mtk_disp_blender_bind,
+	.unbind = mtk_disp_blender_unbind,
+};
+
+static int mtk_disp_blender_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct mtk_disp_blender *priv;
+	int ret = 0;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap blender\n");
+		return PTR_ERR(priv->regs);
+	}
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get blender clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "No mediatek,gce-client-reg\n");
+#endif
+	platform_set_drvdata(pdev, priv);
+
+	ret = component_add(dev, &mtk_disp_blender_component_ops);
+	if (ret)
+		dev_notice(dev, "Failed to add component: %d\n", ret);
+
+	return ret;
+}
+
+static void mtk_disp_blender_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_blender_component_ops);
+}
+
+static const struct of_device_id mtk_disp_blender_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8196-blender"},
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_blender_driver_dt_match);
+
+struct platform_driver mtk_disp_blender_driver = {
+	.probe		= mtk_disp_blender_probe,
+	.remove		= mtk_disp_blender_remove,
+	.driver		= {
+		.name	= "mediatek-disp-blender",
+		.owner	= THIS_MODULE,
+		.of_match_table = mtk_disp_blender_driver_dt_match,
+	},
+};
+
+MODULE_AUTHOR("Nancy Lin <nancy.lin at mediatek.com>");
+MODULE_DESCRIPTION("MediaTek Blender Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_blender.h b/drivers/gpu/drm/mediatek/mtk_disp_blender.h
new file mode 100644
index 000000000000..a47ab128649d
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_blender.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#ifndef __MTK_DISP_BLENDER_H__
+#define __MTK_DISP_BLENDER_H__
+
+u32 mtk_disp_blender_get_blend_modes(struct device *dev);
+#endif // __MTK_DISP_BLENDER_H__
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 4e3d2510bef5..39e3af1e2b16 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -9,6 +9,7 @@
 #include <linux/soc/mediatek/mtk-cmdq.h>
 #include <linux/soc/mediatek/mtk-mmsys.h>
 #include <linux/soc/mediatek/mtk-mutex.h>
+#include "mtk_disp_blender.h"
 #include "mtk_mdp_rdma.h"
 #include "mtk_plane.h"
 
@@ -39,6 +40,17 @@ void mtk_color_config(struct device *dev, unsigned int w,
 		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
 void mtk_color_start(struct device *dev);
 
+void mtk_disp_blender_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_disp_blender_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+int mtk_disp_blender_clk_enable(struct device *dev);
+void mtk_disp_blender_clk_disable(struct device *dev);
+void mtk_disp_blender_config(struct device *dev, unsigned int w,
+			     unsigned int h, unsigned int vrefresh,
+			     unsigned int bpc, bool most_top, bool most_bottom,
+			     struct cmdq_pkt *cmdq_pkt);
+void mtk_disp_blender_layer_config(struct device *dev, struct mtk_plane_state *state,
+				   struct cmdq_pkt *cmdq_pkt);
+
 int mtk_disp_exdma_clk_enable(struct device *dev);
 void mtk_disp_exdma_clk_disable(struct device *dev);
 void mtk_disp_exdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index bb7306a942ff..7a14f45d5f97 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -1274,6 +1274,7 @@ static struct platform_driver mtk_drm_platform_driver = {
 
 static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_aal_driver,
+	&mtk_disp_blender_driver,
 	&mtk_disp_ccorr_driver,
 	&mtk_disp_color_driver,
 	&mtk_disp_exdma_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 898a75898775..89178de1478f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -70,6 +70,7 @@ struct mtk_drm_private {
 };
 
 extern struct platform_driver mtk_disp_aal_driver;
+extern struct platform_driver mtk_disp_blender_driver;
 extern struct platform_driver mtk_disp_ccorr_driver;
 extern struct platform_driver mtk_disp_color_driver;
 extern struct platform_driver mtk_disp_exdma_driver;
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:26 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:26 +0800
Subject: [PATCH v3 14/17] drm/mediatek: add OUTPROC support for MT8196
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-15-paul-pl.chen@mediatek.com>

From: Nancy Lin <nancy.lin at mediatek.com>

OUTPROC handles the post-stage of pixel processing in
the overlapping procedure.OUTPROC manages pixels for
gamma correction and ensures that pixel values are
within the correct range.

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c     |   1 +
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h     |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |  14 ++
 drivers/gpu/drm/mediatek/mtk_disp_outproc.c | 240 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_outproc.h |  22 ++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 8 files changed, 281 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_outproc.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_outproc.h

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index a7b9ebe27f68..9546bc6b7b2e 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -10,6 +10,7 @@ mediatek-drm-y := mtk_crtc.o \
 		  mtk_disp_gamma.o \
 		  mtk_disp_merge.o \
 		  mtk_disp_ovl.o \
+		  mtk_disp_outproc.o \
 		  mtk_disp_ovl_adaptor.o \
 		  mtk_disp_rdma.o \
 		  mtk_drm_drv.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index e65c6df987f2..cc780744f060 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -447,6 +447,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DSI] = "dsi",
 	[MTK_OVL_BLENDER] = "blender",
 	[MTK_OVL_EXDMA] = "exdma",
+	[MTK_OVL_OUTPROC] = "outproc",
 };
 
 struct mtk_ddp_comp_match {
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index 075ba5683f93..b33d3289b8b6 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -45,6 +45,7 @@ enum mtk_ddp_comp_type {
 	MTK_DSI,
 	MTK_OVL_BLENDER,
 	MTK_OVL_EXDMA,
+	MTK_OVL_OUTPROC,
 	MTK_DDP_COMP_TYPE_MAX,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 39e3af1e2b16..3c519a662074 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -64,6 +64,20 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
 			   unsigned int bpc, unsigned int cfg,
 			   unsigned int dither_en, struct cmdq_pkt *cmdq_pkt);
 
+void mtk_disp_outproc_start(struct device *dev);
+void mtk_disp_outproc_stop(struct device *dev);
+int mtk_disp_outproc_clk_enable(struct device *dev);
+void mtk_disp_outproc_clk_disable(struct device *dev);
+void mtk_disp_outproc_config(struct device *dev, unsigned int w,
+			     unsigned int h, unsigned int vrefresh,
+			     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_disp_outproc_register_vblank_cb(struct device *dev,
+					 void (*vblank_cb)(void *),
+					 void *vblank_cb_data);
+void mtk_disp_outproc_unregister_vblank_cb(struct device *dev);
+void mtk_disp_outproc_enable_vblank(struct device *dev);
+void mtk_disp_outproc_disable_vblank(struct device *dev);
+
 void mtk_dpi_start(struct device *dev);
 void mtk_dpi_stop(struct device *dev);
 unsigned int mtk_dpi_encoder_index(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_outproc.c b/drivers/gpu/drm/mediatek/mtk_disp_outproc.c
new file mode 100644
index 000000000000..bc0b2388e9d6
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_outproc.c
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <drm/drm_framebuffer.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#include "mtk_crtc.h"
+#include "mtk_ddp_comp.h"
+#include "mtk_disp_outproc.h"
+#include "mtk_drm_drv.h"
+
+#define DISP_REG_OVL_OUTPROC_INTEN				0x004
+#define OVL_OUTPROC_FME_CPL_INTEN					BIT(1)
+#define DISP_REG_OVL_OUTPROC_INTSTA				0x008
+#define DISP_REG_OVL_OUTPROC_DATAPATH_CON			0x010
+#define OVL_OUTPROC_DATAPATH_CON_OUTPUT_CLAMP				BIT(26)
+
+#define DISP_REG_OVL_OUTPROC_EN					0x020
+#define OVL_OUTPROC_OVL_EN						BIT(0)
+#define DISP_REG_OVL_OUTPROC_RST				0x024
+#define OVL_OUTPROC_RST							BIT(0)
+#define DISP_REG_OVL_OUTPROC_SHADOW_CTRL			0x028
+#define OVL_OUTPROC_BYPASS_SHADOW					BIT(2)
+#define DISP_REG_OVL_OUTPROC_ROI_SIZE				0x030
+
+struct mtk_disp_outproc {
+	void __iomem		*regs;
+	struct clk		*clk;
+	void			(*vblank_cb)(void *data);
+	void			*vblank_cb_data;
+	int			irq;
+	struct cmdq_client_reg	cmdq_reg;
+};
+
+void mtk_disp_outproc_register_vblank_cb(struct device *dev,
+					 void (*vblank_cb)(void *),
+					 void *vblank_cb_data)
+{
+	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
+
+	priv->vblank_cb = vblank_cb;
+	priv->vblank_cb_data = vblank_cb_data;
+}
+
+void mtk_disp_outproc_unregister_vblank_cb(struct device *dev)
+{
+	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
+
+	priv->vblank_cb = NULL;
+	priv->vblank_cb_data = NULL;
+}
+
+void mtk_disp_outproc_enable_vblank(struct device *dev)
+{
+	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
+
+	writel(OVL_OUTPROC_FME_CPL_INTEN, priv->regs + DISP_REG_OVL_OUTPROC_INTEN);
+}
+
+void mtk_disp_outproc_disable_vblank(struct device *dev)
+{
+	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
+
+	writel(0x0, priv->regs + DISP_REG_OVL_OUTPROC_INTEN);
+}
+
+static irqreturn_t mtk_disp_outproc_irq_handler(int irq, void *dev_id)
+{
+	struct mtk_disp_outproc *priv = dev_id;
+	u32 val;
+
+	val = readl(priv->regs + DISP_REG_OVL_OUTPROC_INTSTA);
+	if (!val)
+		return IRQ_NONE;
+
+	writel(0x0, priv->regs + DISP_REG_OVL_OUTPROC_INTSTA);
+
+	if (priv->vblank_cb)
+		priv->vblank_cb(priv->vblank_cb_data);
+
+	return IRQ_HANDLED;
+}
+
+void mtk_disp_outproc_config(struct device *dev, unsigned int w,
+			     unsigned int h, unsigned int vrefresh,
+			     unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
+	u32 tmp;
+
+	dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
+
+	writel((h << 16) | w, priv->regs + DISP_REG_OVL_OUTPROC_ROI_SIZE);
+
+	tmp = readl(priv->regs + DISP_REG_OVL_OUTPROC_DATAPATH_CON);
+	tmp = (tmp & ~OVL_OUTPROC_DATAPATH_CON_OUTPUT_CLAMP) |
+		  (OVL_OUTPROC_DATAPATH_CON_OUTPUT_CLAMP & OVL_OUTPROC_DATAPATH_CON_OUTPUT_CLAMP);
+	writel(tmp, priv->regs + DISP_REG_OVL_OUTPROC_DATAPATH_CON);
+}
+
+void mtk_disp_outproc_start(struct device *dev)
+{
+	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
+	unsigned int tmp;
+
+	tmp = readl(priv->regs + DISP_REG_OVL_OUTPROC_SHADOW_CTRL);
+	tmp = tmp | OVL_OUTPROC_BYPASS_SHADOW;
+	writel(tmp, priv->regs + DISP_REG_OVL_OUTPROC_SHADOW_CTRL);
+
+	writel(0, priv->regs + DISP_REG_OVL_OUTPROC_INTSTA);
+
+	tmp = readl(priv->regs + DISP_REG_OVL_OUTPROC_EN);
+	tmp = (tmp & ~OVL_OUTPROC_OVL_EN) | (OVL_OUTPROC_OVL_EN & OVL_OUTPROC_OVL_EN);
+	writel(tmp, priv->regs + DISP_REG_OVL_OUTPROC_EN);
+}
+
+void mtk_disp_outproc_stop(struct device *dev)
+{
+	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
+
+	writel(0, priv->regs + DISP_REG_OVL_OUTPROC_EN);
+	writel(OVL_OUTPROC_RST, priv->regs + DISP_REG_OVL_OUTPROC_RST);
+	writel(0, priv->regs + DISP_REG_OVL_OUTPROC_RST);
+}
+
+int mtk_disp_outproc_clk_enable(struct device *dev)
+{
+	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
+
+	return clk_prepare_enable(priv->clk);
+}
+
+void mtk_disp_outproc_clk_disable(struct device *dev)
+{
+	struct mtk_disp_outproc *priv = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_outproc_bind(struct device *dev, struct device *master,
+				 void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_outproc_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_disp_outproc_component_ops = {
+	.bind	= mtk_disp_outproc_bind,
+	.unbind = mtk_disp_outproc_unbind,
+};
+
+static int mtk_disp_outproc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mtk_disp_outproc *priv;
+	int ret = 0;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(priv->regs))
+		return dev_err_probe(dev, PTR_ERR(priv->regs), "failed to ioremap outproc\n");
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk))
+		return dev_err_probe(dev, PTR_ERR(priv->clk), "failed to get outproc clk\n");
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "No mediatek,gce-client-reg\n");
+#endif
+
+	if (of_property_read_u32_index(dev->of_node, "interrupts", 0, &ret)) {
+		dev_dbg(dev, "interrupts not defined\n");
+	} else {
+		priv->irq = platform_get_irq(pdev, 0);
+		if (priv->irq < 0)
+			priv->irq = 0;
+
+		if (priv->irq) {
+			ret = devm_request_irq(dev, priv->irq, mtk_disp_outproc_irq_handler,
+					       IRQF_TRIGGER_NONE, dev_name(dev), priv);
+			if (ret < 0) {
+				dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret);
+				return ret;
+			}
+		}
+	}
+
+	platform_set_drvdata(pdev, priv);
+
+	ret = component_add(dev, &mtk_disp_outproc_component_ops);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to add component\n");
+
+	return ret;
+}
+
+static void mtk_disp_outproc_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_outproc_component_ops);
+}
+
+static const struct of_device_id mtk_disp_outproc_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8196-outproc"},
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_outproc_driver_dt_match);
+
+struct platform_driver mtk_disp_outproc_driver = {
+	.probe		= mtk_disp_outproc_probe,
+	.remove		= mtk_disp_outproc_remove,
+	.driver		= {
+		.name	= "mediatek-disp-outproc",
+		.owner	= THIS_MODULE,
+		.of_match_table = mtk_disp_outproc_driver_dt_match,
+	},
+};
+
+MODULE_AUTHOR("Nancy Lin <nancy.lin at mediatek.com>");
+MODULE_DESCRIPTION("MediaTek Output processing Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_outproc.h b/drivers/gpu/drm/mediatek/mtk_disp_outproc.h
new file mode 100644
index 000000000000..abb101979521
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_outproc.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#ifndef __MTK_DISP_OUTPROC_H__
+#define __MTK_DISP_OUTPROC_H__
+
+void mtk_disp_outproc_start(struct device *dev);
+void mtk_disp_outproc_stop(struct device *dev);
+int mtk_disp_outproc_clk_enable(struct device *dev);
+void mtk_disp_outproc_clk_disable(struct device *dev);
+void mtk_disp_outproc_config(struct device *dev, unsigned int w,
+			     unsigned int h, unsigned int vrefresh,
+			     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_disp_outproc_register_vblank_cb(struct device *dev,
+					 void (*vblank_cb)(void *),
+					 void *vblank_cb_data);
+void mtk_disp_outproc_unregister_vblank_cb(struct device *dev);
+void mtk_disp_outproc_enable_vblank(struct device *dev);
+void mtk_disp_outproc_disable_vblank(struct device *dev);
+#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 7a14f45d5f97..f7b9c7a982a7 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -1280,6 +1280,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_exdma_driver,
 	&mtk_disp_gamma_driver,
 	&mtk_disp_merge_driver,
+	&mtk_disp_outproc_driver,
 	&mtk_disp_ovl_adaptor_driver,
 	&mtk_disp_ovl_driver,
 	&mtk_disp_rdma_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 89178de1478f..c4717c37b0f1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -76,6 +76,7 @@ extern struct platform_driver mtk_disp_color_driver;
 extern struct platform_driver mtk_disp_exdma_driver;
 extern struct platform_driver mtk_disp_gamma_driver;
 extern struct platform_driver mtk_disp_merge_driver;
+extern struct platform_driver mtk_disp_outproc_driver;
 extern struct platform_driver mtk_disp_ovl_adaptor_driver;
 extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:20 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:20 +0800
Subject: [PATCH v3 08/17] soc: mediatek: mutex: refactor SOF settings for output components
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-9-paul-pl.chen@mediatek.com>

From: Paul-pl Chen <paul-pl.chen at mediatek.com>

Refactor SOF settings by adding mtk_mutex_get_output_comp_sof()
and extracting SOF logic from mtk_mutex_add_comp()
and mtk_mutex_remove_comp().

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 drivers/soc/mediatek/mtk-mutex.c       | 60 +++++++++++++++++++++-----
 include/linux/soc/mediatek/mtk-mutex.h |  4 ++
 2 files changed, 53 insertions(+), 11 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 47f4d9ae4bfc..b2a9992fb232 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -879,19 +879,57 @@ static int mtk_mutex_get_output_comp_sof(enum mtk_ddp_comp_id id)
 	return -EINVAL;
 }
 
+void mtk_mutex_add_comp_sof(struct mtk_mutex *mutex, enum mtk_ddp_comp_id id)
+{
+	struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+						 mutex[mutex->id]);
+	int sof_id = mtk_mutex_get_output_comp_sof(id);
+	unsigned int offset;
+
+	if (sof_id < 0 || sof_id >= DDP_MUTEX_SOF_MAX)
+		return;
+
+	WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+	offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id);
+
+	writel_relaxed(mtx->data->mutex_sof[sof_id], mtx->regs + offset);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_add_comp_sof);
+
+void mtk_mutex_remove_comp_sof(struct mtk_mutex *mutex, enum mtk_ddp_comp_id id)
+{
+	struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+						 mutex[mutex->id]);
+	unsigned int reg;
+	int sof_id = mtk_mutex_get_output_comp_sof(id);
+	unsigned int offset;
+
+	if (sof_id < 0 || sof_id >= DDP_MUTEX_SOF_MAX)
+		return;
+
+	WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+	offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id);
+	reg = readl_relaxed(mtx->regs + offset);
+	reg &= ~(1 << mtx->data->mutex_sof[id]);
+
+	writel_relaxed(reg, mtx->regs + offset);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp_sof);
+
 void mtk_mutex_add_comp(struct mtk_mutex *mutex,
 			enum mtk_ddp_comp_id id)
 {
 	struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
 						 mutex[mutex->id]);
 	unsigned int reg;
-	unsigned int sof_id;
 	unsigned int offset;
-	int sof_id = mtk_mutex_get_output_comp_sof(id);
+	bool is_output_comp = (mtk_mutex_get_output_comp_sof(id) > 0);
 
 	WARN_ON(&mtx->mutex[mutex->id] != mutex);
 
-	if (sof_id < 0) {
+	if (!is_output_comp) {
 		if (mtx->data->mutex_mod[id] < 32) {
 			offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
 						    mutex->id);
@@ -904,11 +942,10 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
 			reg |= 1 << (mtx->data->mutex_mod[id] - 32);
 			writel_relaxed(reg, mtx->regs + offset);
 		}
-		return;
 	}
 
-	writel_relaxed(mtx->data->mutex_sof[sof_id], mtx->regs +
-		       DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id));
+	if (is_output_comp)
+		mtk_mutex_add_comp_sof(mutex, id);
 }
 EXPORT_SYMBOL_GPL(mtk_mutex_add_comp);
 
@@ -919,10 +956,11 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
 						 mutex[mutex->id]);
 	unsigned int reg;
 	unsigned int offset;
-	int sof_id = mtk_mutex_get_output_comp_sof(id);
+	bool is_output_comp = (mtk_mutex_get_output_comp_sof(id) > 0);
+
 	WARN_ON(&mtx->mutex[mutex->id] != mutex);
 
-	if (sof_id < 0) {
+	if (!is_output_comp) {
 		if (mtx->data->mutex_mod[id] < 32) {
 			offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
 						    mutex->id);
@@ -938,9 +976,9 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
 		return;
 	}
 
-	writel_relaxed(MUTEX_SOF_SINGLE_MODE,
-		       mtx->regs + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
-		       mutex->id));
+	if (is_output_comp)
+		mtk_mutex_remove_comp_sof(mutex, id);
+
 }
 EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
 
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index 635218e3ac68..515e2d8bfc90 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -69,6 +69,10 @@ enum mtk_mutex_sof_index {
 
 struct mtk_mutex *mtk_mutex_get(struct device *dev);
 int mtk_mutex_prepare(struct mtk_mutex *mutex);
+void mtk_mutex_add_comp_sof(struct mtk_mutex *mutex,
+			    enum mtk_ddp_comp_id id);
+void mtk_mutex_remove_comp_sof(struct mtk_mutex *mutex,
+			       enum mtk_ddp_comp_id id);
 void mtk_mutex_add_comp(struct mtk_mutex *mutex,
 			enum mtk_ddp_comp_id id);
 void mtk_mutex_enable(struct mtk_mutex *mutex);
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:24 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:24 +0800
Subject: [PATCH v3 12/17] drm/mediatek: add EXDMA support for MT8196
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-13-paul-pl.chen@mediatek.com>

From: Nancy Lin <nancy.lin at mediatek.com>

EXDMA is a DMA engine for reading data from DRAM with
various DRAM footprints and data formats. For input
sources in certain color formats and color domains,
EXDMA also includes a color transfer function to
process pixels into a consistent color domain.
New Add: 6320385 Fix RG16 and refine RG24

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile         |   1 +
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c   |   1 +
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h   |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h   |   9 +
 drivers/gpu/drm/mediatek/mtk_disp_exdma.c | 349 ++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c    |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h    |   1 +
 7 files changed, 363 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_exdma.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 32a2ed6c0cfe..db92f4fb353d 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -5,6 +5,7 @@ mediatek-drm-y := mtk_crtc.o \
 		  mtk_disp_aal.o \
 		  mtk_disp_ccorr.o \
 		  mtk_disp_color.o \
+		  mtk_disp_exdma.o \
 		  mtk_disp_gamma.o \
 		  mtk_disp_merge.o \
 		  mtk_disp_ovl.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index edc6417639e6..3e0739d8e6f1 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -445,6 +445,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DP_INTF] = "dp-intf",
 	[MTK_DPI] = "dpi",
 	[MTK_DSI] = "dsi",
+	[MTK_OVL_EXDMA] = "exdma",
 };
 
 struct mtk_ddp_comp_match {
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index 39720b27f4e9..86dc0ee3924c 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -43,6 +43,7 @@ enum mtk_ddp_comp_type {
 	MTK_DPI,
 	MTK_DP_INTF,
 	MTK_DSI,
+	MTK_OVL_EXDMA,
 	MTK_DDP_COMP_TYPE_MAX,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 04217a36939c..4e3d2510bef5 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -39,6 +39,15 @@ void mtk_color_config(struct device *dev, unsigned int w,
 		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
 void mtk_color_start(struct device *dev);
 
+int mtk_disp_exdma_clk_enable(struct device *dev);
+void mtk_disp_exdma_clk_disable(struct device *dev);
+void mtk_disp_exdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_disp_exdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_disp_exdma_layer_config(struct device *dev, struct mtk_plane_state *state,
+				 struct cmdq_pkt *cmdq_pkt);
+const u32 *mtk_disp_exdma_get_formats(struct device *dev);
+size_t mtk_disp_exdma_get_num_formats(struct device *dev);
+
 void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
 			   unsigned int bpc, unsigned int cfg,
 			   unsigned int dither_en, struct cmdq_pkt *cmdq_pkt);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_exdma.c b/drivers/gpu/drm/mediatek/mtk_disp_exdma.c
new file mode 100644
index 000000000000..21a60e8f99c4
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_exdma.c
@@ -0,0 +1,349 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <drm/drm_blend.h>
+#include <drm/drm_framebuffer.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_disp_drv.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_ovl.h"
+
+#define DISP_REG_OVL_EXDMA_EN_CON		0xc
+#define OVL_EXDMA_OP_8BIT_MODE				BIT(4)
+#define OVL_EXDMA_HG_FOVL_EXDMA_CK_ON			BIT(8)
+#define OVL_EXDMA_HF_FOVL_EXDMA_CK_ON			BIT(10)
+#define DISP_REG_OVL_EXDMA_DATAPATH_CON		0x014
+#define OVL_EXDMA_DATAPATH_CON_LAYER_SMI_ID_EN		BIT(0)
+#define OVL_EXDMA_DATAPATH_CON_GCLAST_EN		BIT(24)
+#define OVL_EXDMA_DATAPATH_CON_HDR_GCLAST_EN		BIT(25)
+#define DISP_REG_OVL_EXDMA_EN			0x020
+#define OVL_EXDMA_EN					BIT(0)
+#define DISP_REG_OVL_EXDMA_RST			0x024
+#define OVL_EXDMA_RST					BIT(0)
+#define DISP_REG_OVL_EXDMA_ROI_SIZE		0x030
+#define DISP_REG_OVL_EXDMA_L0_EN		0x040
+#define OVL_EXDMA_L0_EN					BIT(0)
+#define DISP_REG_OVL_EXDMA_L0_OFFSET		0x044
+#define DISP_REG_OVL_EXDMA_SRC_SIZE		0x048
+#define DISP_REG_OVL_EXDMA_L0_CLRFMT		0x050
+#define OVL_EXDMA_CON_FLD_CLRFMT			GENMASK(3, 0)
+#define OVL_EXDMA_CON_CLRFMT_MAN			BIT(4)
+#define OVL_EXDMA_CON_FLD_CLRFMT_NB			GENMASK(9, 8)
+#define OVL_EXDMA_CON_CLRFMT_NB_10_BIT			BIT(8)
+#define OVL_EXDMA_CON_BYTE_SWAP				BIT(16)
+#define OVL_EXDMA_CON_RGB_SWAP				BIT(17)
+#define DISP_REG_OVL_EXDMA_RDMA0_CTRL		0x100
+#define OVL_EXDMA_RDMA0_EN				BIT(0)
+#define DISP_REG_OVL_EXDMA_RDMA_BURST_CON1	0x1f4
+#define OVL_EXDMA_RDMA_BURST_CON1_BURST16_EN		BIT(28)
+#define OVL_EXDMA_RDMA_BURST_CON1_DDR_EN		BIT(30)
+#define OVL_EXDMA_RDMA_BURST_CON1_DDR_ACK_EN		BIT(31)
+#define DISP_REG_OVL_EXDMA_DUMMY_REG		0x200
+#define OVL_EXDMA_EXT_DDR_EN_OPT			BIT(2)
+#define OVL_EXDMA_FORCE_EXT_DDR_EN			BIT(3)
+#define DISP_REG_OVL_EXDMA_GDRDY_PRD		0x208
+#define DISP_REG_OVL_EXDMA_PITCH_MSB		0x2f0
+#define OVL_EXDMA_L0_SRC_PITCH_MSB_MASK			GENMASK(3, 0)
+#define DISP_REG_OVL_EXDMA_PITCH		0x2f4
+#define OVL_EXDMA_L0_SRC_PITCH				GENMASK(15, 0)
+#define OVL_EXDMA_L0_CONST_BLD				BIT(28)
+#define OVL_EXDMA_L0_SRC_PITCH_MASK			GENMASK(15, 0)
+#define DISP_REG_OVL_EXDMA_L0_GUSER_EXT		0x2fc
+#define OVL_EXDMA_RDMA0_L0_VCSEL			BIT(5)
+#define OVL_EXDMA_RDMA0_HDR_L0_VCSEL			BIT(21)
+#define DISP_REG_OVL_EXDMA_CON			0x300
+#define OVL_EXDMA_CON_FLD_INT_MTX_SEL			GENMASK(19, 16)
+#define OVL_EXDMA_CON_INT_MTX_BT601_TO_RGB		(6 << 16)
+#define OVL_EXDMA_CON_INT_MTX_BT709_TO_RGB		(7 << 16)
+#define OVL_EXDMA_CON_INT_MTX_EN			BIT(27)
+#define DISP_REG_OVL_EXDMA_ADDR			0xf40
+#define DISP_REG_OVL_EXDMA_MOUT			0xff0
+#define OVL_EXDMA_MOUT_OUT_DATA				BIT(0)
+#define OVL_EXDMA_MOUT_BGCLR_OUT			BIT(1)
+
+struct mtk_disp_exdma {
+	void __iomem		*regs;
+	struct clk		*clk;
+	struct cmdq_client_reg	cmdq_reg;
+	struct device		*larb;
+};
+
+static unsigned int  mtk_disp_exdma_color_convert(unsigned int color_encoding)
+{
+	switch (color_encoding) {
+	default:
+	case DRM_COLOR_YCBCR_BT709:
+		return OVL_EXDMA_CON_INT_MTX_BT709_TO_RGB;
+	case DRM_COLOR_YCBCR_BT601:
+		return OVL_EXDMA_CON_INT_MTX_BT601_TO_RGB;
+	}
+}
+
+void mtk_disp_exdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_exdma *priv = dev_get_drvdata(dev);
+	unsigned int value = 0, mask = 0;
+
+	/*
+	 * This configuration enables dynamic power switching mechanism for EXDMA,
+	 * also known as "SRT mode".
+	 * Such configuration allows the system to achieve better power efficiency.
+	 */
+	value = OVL_EXDMA_RDMA_BURST_CON1_BURST16_EN | OVL_EXDMA_RDMA_BURST_CON1_DDR_ACK_EN;
+	mask = OVL_EXDMA_RDMA_BURST_CON1_BURST16_EN | OVL_EXDMA_RDMA_BURST_CON1_DDR_EN |
+	       OVL_EXDMA_RDMA_BURST_CON1_DDR_ACK_EN;
+	mtk_ddp_write_mask(cmdq_pkt, value, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_EXDMA_RDMA_BURST_CON1, mask);
+
+	/*
+	 * The dummy register is used in the configuration of the EXDMA engine to
+	 * signal ddren_request, and get ddren_ack before accessing the DRAM to
+	 * ensure data transfers occur normally.
+	 * primarily functions as a DMA engine for reading data from DRAM with
+	 * various DRAM footprints and data formats.
+	 */
+	value = OVL_EXDMA_EXT_DDR_EN_OPT | OVL_EXDMA_FORCE_EXT_DDR_EN;
+
+	mtk_ddp_write_mask(cmdq_pkt, value, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_EXDMA_DUMMY_REG, value);
+
+	value = OVL_EXDMA_DATAPATH_CON_LAYER_SMI_ID_EN |
+		OVL_EXDMA_DATAPATH_CON_HDR_GCLAST_EN |
+		OVL_EXDMA_DATAPATH_CON_GCLAST_EN;
+
+	mtk_ddp_write_mask(cmdq_pkt, value, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_EXDMA_DATAPATH_CON, value);
+
+	mtk_ddp_write_mask(cmdq_pkt, OVL_EXDMA_MOUT_BGCLR_OUT, &priv->cmdq_reg,
+			   priv->regs, DISP_REG_OVL_EXDMA_MOUT,
+			   OVL_EXDMA_MOUT_BGCLR_OUT | OVL_EXDMA_MOUT_OUT_DATA);
+
+	mtk_ddp_write(cmdq_pkt, ~0, &priv->cmdq_reg, priv->regs, DISP_REG_OVL_EXDMA_GDRDY_PRD);
+
+	value = OVL_EXDMA_HG_FOVL_EXDMA_CK_ON | OVL_EXDMA_HF_FOVL_EXDMA_CK_ON |
+		OVL_EXDMA_OP_8BIT_MODE;
+	mtk_ddp_write_mask(cmdq_pkt, value, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_EXDMA_EN_CON, value);
+	mtk_ddp_write_mask(cmdq_pkt, OVL_EXDMA_EN, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_EXDMA_EN, OVL_EXDMA_EN);
+}
+
+void mtk_disp_exdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_exdma *priv = dev_get_drvdata(dev);
+	unsigned int mask;
+
+	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_EXDMA_EN, OVL_EXDMA_EN);
+	mask = OVL_EXDMA_HG_FOVL_EXDMA_CK_ON | OVL_EXDMA_HF_FOVL_EXDMA_CK_ON |
+		OVL_EXDMA_OP_8BIT_MODE;
+	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_EXDMA_EN_CON, mask);
+	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_EXDMA_DATAPATH_CON, OVL_EXDMA_DATAPATH_CON_LAYER_SMI_ID_EN);
+	mtk_ddp_write_mask(cmdq_pkt, OVL_EXDMA_RST, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_EXDMA_RST, OVL_EXDMA_RST);
+	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_EXDMA_RST, OVL_EXDMA_RST);
+}
+
+void mtk_disp_exdma_layer_config(struct device *dev, struct mtk_plane_state *state,
+				 struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_exdma *priv = dev_get_drvdata(dev);
+	struct mtk_plane_pending_state *pending = &state->pending;
+	const struct drm_format_info *fmt_info = drm_format_info(pending->format);
+	bool csc_enable = (fmt_info) ? fmt_info->is_yuv : false;
+	u32 blend_mode = mtk_ovl_get_blend_mode(state, MTK_OVL_SUPPORT_BLEND_MODES);
+	u32 val;
+
+	if (!pending->enable) {
+		mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+				   DISP_REG_OVL_EXDMA_RDMA0_CTRL, OVL_EXDMA_RDMA0_EN);
+		mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+				   DISP_REG_OVL_EXDMA_L0_EN, OVL_EXDMA_L0_EN);
+		return;
+	}
+
+	mtk_ddp_write(cmdq_pkt, pending->height << 16 | pending->width, &priv->cmdq_reg,
+		      priv->regs, DISP_REG_OVL_EXDMA_ROI_SIZE);
+
+	mtk_ddp_write(cmdq_pkt, pending->height << 16 | pending->width, &priv->cmdq_reg,
+		      priv->regs, DISP_REG_OVL_EXDMA_SRC_SIZE);
+
+	mtk_ddp_write(cmdq_pkt, pending->y << 16 | pending->x, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_OVL_EXDMA_L0_OFFSET);
+	mtk_ddp_write(cmdq_pkt, pending->addr, &priv->cmdq_reg,
+		      priv->regs, DISP_REG_OVL_EXDMA_ADDR);
+
+	mtk_ddp_write_mask(cmdq_pkt, pending->pitch, &priv->cmdq_reg,
+			   priv->regs, DISP_REG_OVL_EXDMA_PITCH, OVL_EXDMA_L0_SRC_PITCH_MASK);
+	mtk_ddp_write_mask(cmdq_pkt, pending->pitch >> 16, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_EXDMA_PITCH_MSB, OVL_EXDMA_L0_SRC_PITCH_MSB_MASK);
+
+	val = mtk_disp_exdma_color_convert(pending->color_encoding);
+	if (csc_enable)
+		val |= OVL_EXDMA_CON_INT_MTX_EN;
+	mtk_ddp_write_mask(cmdq_pkt, val, &priv->cmdq_reg, priv->regs, DISP_REG_OVL_EXDMA_CON,
+			   OVL_EXDMA_CON_FLD_INT_MTX_SEL | OVL_EXDMA_CON_INT_MTX_EN);
+
+	val = mtk_ovl_fmt_convert(pending->format, blend_mode, true, false, 0,
+				  OVL_EXDMA_CON_CLRFMT_MAN, OVL_EXDMA_CON_BYTE_SWAP,
+				  OVL_EXDMA_CON_RGB_SWAP);
+	if (mtk_ovl_is_10bit_rgb(pending->format))
+		val |= OVL_EXDMA_CON_CLRFMT_NB_10_BIT;
+	mtk_ddp_write_mask(cmdq_pkt, val, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_EXDMA_L0_CLRFMT,
+			   OVL_EXDMA_CON_RGB_SWAP | OVL_EXDMA_CON_BYTE_SWAP |
+			   OVL_EXDMA_CON_CLRFMT_MAN | OVL_EXDMA_CON_FLD_CLRFMT |
+			   OVL_EXDMA_CON_FLD_CLRFMT_NB);
+
+	val = OVL_EXDMA_RDMA0_L0_VCSEL | OVL_EXDMA_RDMA0_HDR_L0_VCSEL;
+	mtk_ddp_write_mask(cmdq_pkt, val, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_EXDMA_L0_GUSER_EXT, val);
+
+	val = pending->pitch;
+	if (mtk_ovl_is_ignore_pixel_alpha(state, blend_mode))
+		val |= OVL_EXDMA_L0_CONST_BLD;
+	mtk_ddp_write_mask(cmdq_pkt, val, &priv->cmdq_reg, priv->regs, DISP_REG_OVL_EXDMA_PITCH,
+			   OVL_EXDMA_L0_CONST_BLD | OVL_EXDMA_L0_SRC_PITCH);
+
+	mtk_ddp_write_mask(cmdq_pkt, OVL_EXDMA_RDMA0_EN, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_EXDMA_RDMA0_CTRL, OVL_EXDMA_RDMA0_EN);
+	mtk_ddp_write_mask(cmdq_pkt, OVL_EXDMA_L0_EN, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_OVL_EXDMA_L0_EN, OVL_EXDMA_L0_EN);
+}
+
+const u32 *mtk_disp_exdma_get_formats(struct device *dev)
+{
+	return mt8195_ovl_formats;
+}
+
+size_t mtk_disp_exdma_get_num_formats(struct device *dev)
+{
+	return mt8195_ovl_formats_len;
+}
+
+int mtk_disp_exdma_clk_enable(struct device *dev)
+{
+	struct mtk_disp_exdma *exdma = dev_get_drvdata(dev);
+
+	return clk_prepare_enable(exdma->clk);
+}
+
+void mtk_disp_exdma_clk_disable(struct device *dev)
+{
+	struct mtk_disp_exdma *exdma = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(exdma->clk);
+}
+
+static int mtk_disp_exdma_bind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_exdma_unbind(struct device *dev, struct device *master,
+				  void *data)
+{
+}
+
+static const struct component_ops mtk_disp_exdma_component_ops = {
+	.bind	= mtk_disp_exdma_bind,
+	.unbind = mtk_disp_exdma_unbind,
+};
+
+static int mtk_disp_exdma_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct platform_device *larb_pdev = NULL;
+	struct device_node *larb_node = NULL;
+	struct resource *res;
+	struct mtk_disp_exdma *priv;
+	int ret = 0;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap exdma\n");
+		return PTR_ERR(priv->regs);
+	}
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get exdma clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	larb_node = of_parse_phandle(dev->of_node, "mediatek,larb", 0);
+	if (larb_node) {
+		larb_pdev = of_find_device_by_node(larb_node);
+		if (larb_pdev)
+			priv->larb = &larb_pdev->dev;
+		of_node_put(larb_node);
+	}
+
+	if (!priv->larb) {
+		dev_dbg(dev, "not find larb dev");
+		return -EPROBE_DEFER;
+	}
+	device_link_add(dev, priv->larb, DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "No mediatek,gce-client-reg\n");
+#endif
+	platform_set_drvdata(pdev, priv);
+
+	pm_runtime_enable(dev);
+
+	ret = component_add(dev, &mtk_disp_exdma_component_ops);
+	if (ret != 0) {
+		pm_runtime_disable(dev);
+		dev_err(dev, "Failed to add component: %d\n", ret);
+	}
+	return ret;
+}
+
+static void mtk_disp_exdma_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_exdma_component_ops);
+	pm_runtime_disable(&pdev->dev);
+}
+
+static const struct of_device_id mtk_disp_exdma_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8196-exdma", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, mtk_disp_exdma_driver_dt_match);
+
+struct platform_driver mtk_disp_exdma_driver = {
+	.probe = mtk_disp_exdma_probe,
+	.remove = mtk_disp_exdma_remove,
+	.driver = {
+		.name = "mediatek-disp-exdma",
+		.owner = THIS_MODULE,
+		.of_match_table = mtk_disp_exdma_driver_dt_match,
+	},
+};
+
+MODULE_AUTHOR("Nancy Lin <nancy.lin at mediatek.com>");
+MODULE_DESCRIPTION("MediaTek Exdma Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 74158b9d6503..bb7306a942ff 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -1276,6 +1276,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_aal_driver,
 	&mtk_disp_ccorr_driver,
 	&mtk_disp_color_driver,
+	&mtk_disp_exdma_driver,
 	&mtk_disp_gamma_driver,
 	&mtk_disp_merge_driver,
 	&mtk_disp_ovl_adaptor_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 675cdc90a440..898a75898775 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -72,6 +72,7 @@ struct mtk_drm_private {
 extern struct platform_driver mtk_disp_aal_driver;
 extern struct platform_driver mtk_disp_ccorr_driver;
 extern struct platform_driver mtk_disp_color_driver;
+extern struct platform_driver mtk_disp_exdma_driver;
 extern struct platform_driver mtk_disp_gamma_driver;
 extern struct platform_driver mtk_disp_merge_driver;
 extern struct platform_driver mtk_disp_ovl_adaptor_driver;
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:19 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:19 +0800
Subject: [PATCH v3 07/17] soc: mediatek: mutex: Reused the switch case for SOF ID
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-8-paul-pl.chen@mediatek.com>

From: Paul-pl Chen <paul-pl.chen at mediatek.com>

Reused the switch case for SOF IDs.

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 drivers/soc/mediatek/mtk-mutex.c | 81 ++++++++++++++------------------
 1 file changed, 36 insertions(+), 45 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index aaa965d4b050..47f4d9ae4bfc 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -853,43 +853,45 @@ void mtk_mutex_unprepare(struct mtk_mutex *mutex)
 }
 EXPORT_SYMBOL_GPL(mtk_mutex_unprepare);
 
-void mtk_mutex_add_comp(struct mtk_mutex *mutex,
-			enum mtk_ddp_comp_id id)
+static int mtk_mutex_get_output_comp_sof(enum mtk_ddp_comp_id id)
 {
-	struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
-						 mutex[mutex->id]);
-	unsigned int reg;
-	unsigned int sof_id;
-	unsigned int offset;
-
-	WARN_ON(&mtx->mutex[mutex->id] != mutex);
-
 	switch (id) {
 	case DDP_COMPONENT_DSI0:
-		sof_id = MUTEX_SOF_DSI0;
-		break;
+		return MUTEX_SOF_DSI0;
 	case DDP_COMPONENT_DSI1:
-		sof_id = MUTEX_SOF_DSI0;
-		break;
+		return MUTEX_SOF_DSI1;
 	case DDP_COMPONENT_DSI2:
-		sof_id = MUTEX_SOF_DSI2;
-		break;
+		return MUTEX_SOF_DSI2;
 	case DDP_COMPONENT_DSI3:
-		sof_id = MUTEX_SOF_DSI3;
-		break;
+		return MUTEX_SOF_DSI3;
 	case DDP_COMPONENT_DPI0:
-		sof_id = MUTEX_SOF_DPI0;
-		break;
+		return MUTEX_SOF_DPI0;
 	case DDP_COMPONENT_DPI1:
-		sof_id = MUTEX_SOF_DPI1;
-		break;
+		return MUTEX_SOF_DPI1;
 	case DDP_COMPONENT_DP_INTF0:
-		sof_id = MUTEX_SOF_DP_INTF0;
-		break;
+		return MUTEX_SOF_DP_INTF0;
 	case DDP_COMPONENT_DP_INTF1:
-		sof_id = MUTEX_SOF_DP_INTF1;
-		break;
+		return MUTEX_SOF_DP_INTF1;
 	default:
+		break;
+	}
+
+	return -EINVAL;
+}
+
+void mtk_mutex_add_comp(struct mtk_mutex *mutex,
+			enum mtk_ddp_comp_id id)
+{
+	struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+						 mutex[mutex->id]);
+	unsigned int reg;
+	unsigned int sof_id;
+	unsigned int offset;
+	int sof_id = mtk_mutex_get_output_comp_sof(id);
+
+	WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+	if (sof_id < 0) {
 		if (mtx->data->mutex_mod[id] < 32) {
 			offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
 						    mutex->id);
@@ -905,8 +907,7 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
 		return;
 	}
 
-	writel_relaxed(mtx->data->mutex_sof[sof_id],
-		       mtx->regs +
+	writel_relaxed(mtx->data->mutex_sof[sof_id], mtx->regs +
 		       DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id));
 }
 EXPORT_SYMBOL_GPL(mtk_mutex_add_comp);
@@ -918,24 +919,10 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
 						 mutex[mutex->id]);
 	unsigned int reg;
 	unsigned int offset;
-
+	int sof_id = mtk_mutex_get_output_comp_sof(id);
 	WARN_ON(&mtx->mutex[mutex->id] != mutex);
 
-	switch (id) {
-	case DDP_COMPONENT_DSI0:
-	case DDP_COMPONENT_DSI1:
-	case DDP_COMPONENT_DSI2:
-	case DDP_COMPONENT_DSI3:
-	case DDP_COMPONENT_DPI0:
-	case DDP_COMPONENT_DPI1:
-	case DDP_COMPONENT_DP_INTF0:
-	case DDP_COMPONENT_DP_INTF1:
-		writel_relaxed(MUTEX_SOF_SINGLE_MODE,
-			       mtx->regs +
-			       DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
-						  mutex->id));
-		break;
-	default:
+	if (sof_id < 0) {
 		if (mtx->data->mutex_mod[id] < 32) {
 			offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
 						    mutex->id);
@@ -948,8 +935,12 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
 			reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
 			writel_relaxed(reg, mtx->regs + offset);
 		}
-		break;
+		return;
 	}
+
+	writel_relaxed(MUTEX_SOF_SINGLE_MODE,
+		       mtx->regs + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
+		       mutex->id));
 }
 EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
 
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:21 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:21 +0800
Subject: [PATCH v3 09/17] soc: mediatek: mutex: add mutex support for MT8196
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-10-paul-pl.chen@mediatek.com>

From: Nancy Lin <nancy.lin at mediatek.com>

Add mutex support for the main and external displays in MT8196:
- Introduce a new DVO0 output component for the new mutex
  settings of MT8196.
- Add a need_sof_mof flag to configure both SOF and MOD settings
  for the output component.

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 drivers/soc/mediatek/mtk-mutex.c | 140 ++++++++++++++++++++++++++++++-
 1 file changed, 138 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index b2a9992fb232..183f3abcd7dd 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -19,6 +19,7 @@
 #define MT2701_MUTEX0_SOF0			0x30
 #define MT8183_MUTEX0_MOD0			0x30
 #define MT8183_MUTEX0_SOF0			0x2c
+#define MT8196_MUTEX0_MOD0			0x34
 
 #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
@@ -237,6 +238,47 @@
 #define MT8195_MUTEX_MOD_MDP_WROT2             32
 #define MT8195_MUTEX_MOD_MDP_WROT3             33
 
+/* OVLSYS */
+#define MT8196_MUTEX_MOD0_OVL_EXDMA2		2
+#define MT8196_MUTEX_MOD0_OVL_EXDMA3		3
+#define MT8196_MUTEX_MOD0_OVL_EXDMA4		4
+#define MT8196_MUTEX_MOD0_OVL_EXDMA5		5
+#define MT8196_MUTEX_MOD0_OVL_EXDMA6		6
+#define MT8196_MUTEX_MOD0_OVL_EXDMA7		7
+#define MT8196_MUTEX_MOD0_OVL_EXDMA8		8
+#define MT8196_MUTEX_MOD0_OVL_EXDMA9		9
+#define MT8196_MUTEX_MOD0_OVL_BLENDER1		11
+#define MT8196_MUTEX_MOD0_OVL_BLENDER2		12
+#define MT8196_MUTEX_MOD0_OVL_BLENDER3		13
+#define MT8196_MUTEX_MOD0_OVL_BLENDER4		14
+#define MT8196_MUTEX_MOD0_OVL_BLENDER5		15
+#define MT8196_MUTEX_MOD0_OVL_BLENDER6		16
+#define MT8196_MUTEX_MOD0_OVL_BLENDER7		17
+#define MT8196_MUTEX_MOD0_OVL_BLENDER8		18
+#define MT8196_MUTEX_MOD0_OVL_BLENDER9		19
+#define MT8196_MUTEX_MOD0_OVL_OUTPROC0		20
+#define MT8196_MUTEX_MOD0_OVL_OUTPROC1		21
+#define MT8196_MUTEX_MOD0_OVL_OUTPROC2		22
+#define MT8196_MUTEX_MOD1_OVL_DLO_ASYNC5	(32 + 16)
+#define MT8196_MUTEX_MOD1_OVL_DLO_ASYNC6	(32 + 17)
+
+/* DISP0 */
+#define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC0	16
+#define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC1	17
+#define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC8	24
+#define MT8196_MUTEX_MOD1_DISP_DLO_ASYNC1	(32 + 1)
+#define MT8196_MUTEX_MOD1_DISP_DLO_ASYNC2	(32 + 2)
+#define MT8196_MUTEX_MOD1_DISP_DLO_ASYNC3	(32 + 3)
+
+/* DISP1 */
+#define MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC21	1
+#define MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC22	2
+#define MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC23	3
+#define MT8196_MUTEX_MOD0_DISP1_DP_INTF0	13
+#define MT8196_MUTEX_MOD0_DISP1_DP_INTF1	14
+#define MT8196_MUTEX_MOD0_DISP1_DSI0		23
+#define MT8196_MUTEX_MOD0_DISP1_DVO		29
+
 #define MT8365_MUTEX_MOD_DISP_OVL0		7
 #define MT8365_MUTEX_MOD_DISP_OVL0_2L		8
 #define MT8365_MUTEX_MOD_DISP_RDMA0		9
@@ -297,6 +339,12 @@
 #define MT8195_MUTEX_SOF_DP_INTF1		4
 #define MT8195_MUTEX_SOF_DPI0			6 /* for HDMI_TX */
 #define MT8195_MUTEX_SOF_DPI1			5 /* for digital video out */
+#define MT8196_MUTEX_SOF_DSI0			1
+#define MT8196_MUTEX_SOF_DSI1			2
+#define MT8196_MUTEX_SOF_DSI2			4
+#define MT8196_MUTEX_SOF_DPI0			5
+#define MT8196_MUTEX_SOF_DPI1			6
+#define MT8196_MUTEX_SOF_DVO0			7
 
 #define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)
 #define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
@@ -310,6 +358,12 @@
 #define MT8195_MUTEX_EOF_DP_INTF1		(MT8195_MUTEX_SOF_DP_INTF1 << 7)
 #define MT8195_MUTEX_EOF_DPI0			(MT8195_MUTEX_SOF_DPI0 << 7)
 #define MT8195_MUTEX_EOF_DPI1			(MT8195_MUTEX_SOF_DPI1 << 7)
+#define MT8196_MUTEX_EOF_DSI0			(MT8196_MUTEX_SOF_DSI0 << 7)
+#define MT8196_MUTEX_EOF_DSI1			(MT8196_MUTEX_SOF_DSI1 << 7)
+#define MT8196_MUTEX_EOF_DSI2			(MT8196_MUTEX_SOF_DSI2 << 7)
+#define MT8196_MUTEX_EOF_DPI0			(MT8196_MUTEX_SOF_DPI0 << 7)
+#define MT8196_MUTEX_EOF_DPI1			(MT8196_MUTEX_SOF_DPI1 << 7)
+#define MT8196_MUTEX_EOF_DVO0			(MT8196_MUTEX_SOF_DVO0 << 7)
 
 struct mtk_mutex {
 	u8 id;
@@ -326,6 +380,7 @@ enum mtk_mutex_sof_id {
 	MUTEX_SOF_DSI3,
 	MUTEX_SOF_DP_INTF0,
 	MUTEX_SOF_DP_INTF1,
+	MUTEX_SOF_DVO0,
 	DDP_MUTEX_SOF_MAX,
 };
 
@@ -336,6 +391,7 @@ struct mtk_mutex_data {
 	const u16 mutex_mod_reg;
 	const u16 mutex_sof_reg;
 	const bool no_clk;
+	const bool need_sof_mod;
 };
 
 struct mtk_mutex_ctx {
@@ -625,6 +681,64 @@ static const u8 mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
 	[MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3,
 };
 
+static const u8 mt8196_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+	[DDP_COMPONENT_OVL0_EXDMA2] = MT8196_MUTEX_MOD0_OVL_EXDMA2,
+	[DDP_COMPONENT_OVL0_EXDMA3] = MT8196_MUTEX_MOD0_OVL_EXDMA3,
+	[DDP_COMPONENT_OVL0_EXDMA4] = MT8196_MUTEX_MOD0_OVL_EXDMA4,
+	[DDP_COMPONENT_OVL0_EXDMA5] = MT8196_MUTEX_MOD0_OVL_EXDMA5,
+	[DDP_COMPONENT_OVL0_EXDMA6] = MT8196_MUTEX_MOD0_OVL_EXDMA6,
+	[DDP_COMPONENT_OVL0_EXDMA7] = MT8196_MUTEX_MOD0_OVL_EXDMA7,
+	[DDP_COMPONENT_OVL0_EXDMA8] = MT8196_MUTEX_MOD0_OVL_EXDMA8,
+	[DDP_COMPONENT_OVL0_EXDMA9] = MT8196_MUTEX_MOD0_OVL_EXDMA9,
+	[DDP_COMPONENT_OVL0_BLENDER1] = MT8196_MUTEX_MOD0_OVL_BLENDER1,
+	[DDP_COMPONENT_OVL0_BLENDER2] = MT8196_MUTEX_MOD0_OVL_BLENDER2,
+	[DDP_COMPONENT_OVL0_BLENDER3] = MT8196_MUTEX_MOD0_OVL_BLENDER3,
+	[DDP_COMPONENT_OVL0_BLENDER4] = MT8196_MUTEX_MOD0_OVL_BLENDER4,
+	[DDP_COMPONENT_OVL0_BLENDER5] = MT8196_MUTEX_MOD0_OVL_BLENDER5,
+	[DDP_COMPONENT_OVL0_BLENDER6] = MT8196_MUTEX_MOD0_OVL_BLENDER6,
+	[DDP_COMPONENT_OVL0_BLENDER7] = MT8196_MUTEX_MOD0_OVL_BLENDER7,
+	[DDP_COMPONENT_OVL0_BLENDER8] = MT8196_MUTEX_MOD0_OVL_BLENDER8,
+	[DDP_COMPONENT_OVL0_BLENDER9] = MT8196_MUTEX_MOD0_OVL_BLENDER9,
+	[DDP_COMPONENT_OVL0_OUTPROC0] = MT8196_MUTEX_MOD0_OVL_OUTPROC0,
+	[DDP_COMPONENT_OVL0_OUTPROC1] = MT8196_MUTEX_MOD0_OVL_OUTPROC1,
+	[DDP_COMPONENT_OVL0_DLO_ASYNC5] = MT8196_MUTEX_MOD1_OVL_DLO_ASYNC5,
+	[DDP_COMPONENT_OVL0_DLO_ASYNC6] = MT8196_MUTEX_MOD1_OVL_DLO_ASYNC6,
+	[DDP_COMPONENT_OVL1_EXDMA2] = MT8196_MUTEX_MOD0_OVL_EXDMA2,
+	[DDP_COMPONENT_OVL1_EXDMA3] = MT8196_MUTEX_MOD0_OVL_EXDMA3,
+	[DDP_COMPONENT_OVL1_EXDMA4] = MT8196_MUTEX_MOD0_OVL_EXDMA4,
+	[DDP_COMPONENT_OVL1_EXDMA5] = MT8196_MUTEX_MOD0_OVL_EXDMA5,
+	[DDP_COMPONENT_OVL1_EXDMA6] = MT8196_MUTEX_MOD0_OVL_EXDMA6,
+	[DDP_COMPONENT_OVL1_EXDMA7] = MT8196_MUTEX_MOD0_OVL_EXDMA7,
+	[DDP_COMPONENT_OVL1_EXDMA8] = MT8196_MUTEX_MOD0_OVL_EXDMA8,
+	[DDP_COMPONENT_OVL1_EXDMA9] = MT8196_MUTEX_MOD0_OVL_EXDMA9,
+	[DDP_COMPONENT_OVL1_BLENDER1] = MT8196_MUTEX_MOD0_OVL_BLENDER1,
+	[DDP_COMPONENT_OVL1_BLENDER2] = MT8196_MUTEX_MOD0_OVL_BLENDER2,
+	[DDP_COMPONENT_OVL1_BLENDER3] = MT8196_MUTEX_MOD0_OVL_BLENDER3,
+	[DDP_COMPONENT_OVL1_BLENDER4] = MT8196_MUTEX_MOD0_OVL_BLENDER4,
+	[DDP_COMPONENT_OVL1_BLENDER5] = MT8196_MUTEX_MOD0_OVL_BLENDER5,
+	[DDP_COMPONENT_OVL1_BLENDER6] = MT8196_MUTEX_MOD0_OVL_BLENDER6,
+	[DDP_COMPONENT_OVL1_BLENDER7] = MT8196_MUTEX_MOD0_OVL_BLENDER7,
+	[DDP_COMPONENT_OVL1_BLENDER8] = MT8196_MUTEX_MOD0_OVL_BLENDER8,
+	[DDP_COMPONENT_OVL1_BLENDER9] = MT8196_MUTEX_MOD0_OVL_BLENDER9,
+	[DDP_COMPONENT_OVL1_OUTPROC0] = MT8196_MUTEX_MOD0_OVL_OUTPROC0,
+	[DDP_COMPONENT_OVL1_OUTPROC1] = MT8196_MUTEX_MOD0_OVL_OUTPROC1,
+	[DDP_COMPONENT_OVL1_DLO_ASYNC5] = MT8196_MUTEX_MOD1_OVL_DLO_ASYNC5,
+	[DDP_COMPONENT_OVL1_DLO_ASYNC6] = MT8196_MUTEX_MOD1_OVL_DLO_ASYNC6,
+	[DDP_COMPONENT_DLI_ASYNC0] = MT8196_MUTEX_MOD0_DISP_DLI_ASYNC0,
+	[DDP_COMPONENT_DLI_ASYNC1] = MT8196_MUTEX_MOD0_DISP_DLI_ASYNC1,
+	[DDP_COMPONENT_DLI_ASYNC8] = MT8196_MUTEX_MOD0_DISP_DLI_ASYNC8,
+	[DDP_COMPONENT_DLO_ASYNC1] = MT8196_MUTEX_MOD1_DISP_DLO_ASYNC1,
+	[DDP_COMPONENT_DLO_ASYNC2] = MT8196_MUTEX_MOD1_DISP_DLO_ASYNC2,
+	[DDP_COMPONENT_DLO_ASYNC3] = MT8196_MUTEX_MOD1_DISP_DLO_ASYNC3,
+	[DDP_COMPONENT_DLI_ASYNC21] = MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC21,
+	[DDP_COMPONENT_DLI_ASYNC22] = MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC22,
+	[DDP_COMPONENT_DLI_ASYNC23] = MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC23,
+	[DDP_COMPONENT_DVO0] = MT8196_MUTEX_MOD0_DISP1_DVO,
+	[DDP_COMPONENT_DP_INTF0] = MT8196_MUTEX_MOD0_DISP1_DP_INTF0,
+	[DDP_COMPONENT_DP_INTF1] = MT8196_MUTEX_MOD0_DISP1_DP_INTF1,
+	[DDP_COMPONENT_DSI0] = MT8196_MUTEX_MOD0_DISP1_DSI0,
+};
+
 static const u8 mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL,
 	[DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR,
@@ -710,6 +824,17 @@ static const u16 mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 		MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
 };
 
+static const u16 mt8196_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+	[MUTEX_SOF_DSI0] = MT8196_MUTEX_SOF_DSI0 | MT8196_MUTEX_EOF_DSI0,
+	[MUTEX_SOF_DSI1] = MT8196_MUTEX_SOF_DSI1 | MT8196_MUTEX_EOF_DSI1,
+	[MUTEX_SOF_DP_INTF0] =
+		MT8196_MUTEX_SOF_DPI0 | MT8196_MUTEX_EOF_DPI0,
+	[MUTEX_SOF_DP_INTF1] =
+		MT8196_MUTEX_SOF_DPI1 | MT8196_MUTEX_EOF_DPI1,
+	[MUTEX_SOF_DVO0] = MT8196_MUTEX_SOF_DVO0 | MT8196_MUTEX_EOF_DVO0,
+};
+
 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
 	.mutex_mod = mt2701_mutex_mod,
 	.mutex_sof = mt2712_mutex_sof,
@@ -803,6 +928,14 @@ static const struct mtk_mutex_data mt8195_vpp_mutex_driver_data = {
 	.mutex_table_mod = mt8195_mutex_table_mod,
 };
 
+static const struct mtk_mutex_data mt8196_mutex_driver_data = {
+	.mutex_mod = mt8196_mutex_mod,
+	.mutex_sof = mt8196_mutex_sof,
+	.mutex_mod_reg = MT8196_MUTEX0_MOD0,
+	.mutex_sof_reg = MT2701_MUTEX0_SOF0,
+	.need_sof_mod = true,
+};
+
 static const struct mtk_mutex_data mt8365_mutex_driver_data = {
 	.mutex_mod = mt8365_mutex_mod,
 	.mutex_sof = mt8183_mutex_sof,
@@ -872,6 +1005,8 @@ static int mtk_mutex_get_output_comp_sof(enum mtk_ddp_comp_id id)
 		return MUTEX_SOF_DP_INTF0;
 	case DDP_COMPONENT_DP_INTF1:
 		return MUTEX_SOF_DP_INTF1;
+	case DDP_COMPONENT_DVO0:
+		return MUTEX_SOF_DVO0;
 	default:
 		break;
 	}
@@ -929,7 +1064,7 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
 
 	WARN_ON(&mtx->mutex[mutex->id] != mutex);
 
-	if (!is_output_comp) {
+	if (!is_output_comp || mtx->data->need_sof_mod) {
 		if (mtx->data->mutex_mod[id] < 32) {
 			offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
 						    mutex->id);
@@ -960,7 +1095,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
 
 	WARN_ON(&mtx->mutex[mutex->id] != mutex);
 
-	if (!is_output_comp) {
+	if (!is_output_comp || mtx->data->need_sof_mod) {
 		if (mtx->data->mutex_mod[id] < 32) {
 			offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
 						    mutex->id);
@@ -1169,6 +1304,7 @@ static const struct of_device_id mutex_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data },
 	{ .compatible = "mediatek,mt8195-disp-mutex", .data = &mt8195_mutex_driver_data },
 	{ .compatible = "mediatek,mt8195-vpp-mutex",  .data = &mt8195_vpp_mutex_driver_data },
+	{ .compatible = "mediatek,mt8196-disp-mutex", .data = &mt8196_mutex_driver_data },
 	{ .compatible = "mediatek,mt8365-disp-mutex", .data = &mt8365_mutex_driver_data },
 	{ /* sentinel */ },
 };
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:23 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:23 +0800
Subject: [PATCH v3 11/17] drm/mediatek: drm/mediatek: Export OVL ignore pixel alpha function
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-12-paul-pl.chen@mediatek.com>

From: Nancy Lin <nancy.lin at mediatek.com>

For the new BLENDER component, the OVL ignore pixel alpha logic
should be exported as a function and reused it.

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 24 ++++++++++++++++++++++--
 drivers/gpu/drm/mediatek/mtk_disp_ovl.h |  1 +
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index a516b7c82b5a..747898a574da 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -211,6 +211,23 @@ void mtk_ovl_disable_vblank(struct device *dev)
 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);
 }
 
+bool mtk_ovl_is_ignore_pixel_alpha(struct mtk_plane_state *state, unsigned int blend_mode)
+{
+	if (!state->base.fb)
+		return false;
+	/*
+	 * Although the alpha channel can be ignored, CONST_BLD must be enabled
+	 * for XRGB format, otherwise OVL will still read the value from memory.
+	 * For RGB888 related formats, whether CONST_BLD is enabled or not won't
+	 * affect the result. Therefore we use !has_alpha as the condition.
+	 */
+
+	if (blend_mode == DRM_MODE_BLEND_PIXEL_NONE || !state->base.fb->format->has_alpha)
+		return true;
+
+	return false;
+}
+
 u32 mtk_ovl_get_blend_modes(struct device *dev)
 {
 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
@@ -539,7 +556,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
 	unsigned int rotation = pending->rotation;
 	unsigned int offset = (pending->y << 16) | pending->x;
 	unsigned int src_size = (pending->height << 16) | pending->width;
-	unsigned int blend_mode = state->base.pixel_blend_mode;
+	unsigned int blend_mode = mtk_ovl_get_blend_mode(state, ovl->data->blend_modes);
 	unsigned int ignore_pixel_alpha = 0;
 	unsigned int con;
 
@@ -557,7 +574,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
 		 * For blend_modes supported SoCs, always enable alpha blending.
 		 * For blend_modes unsupported SoCs, enable alpha blending when has_alpha is set.
 		 */
-		if (blend_mode || state->base.fb->format->has_alpha)
+		if (state->base.pixel_blend_mode || state->base.fb->format->has_alpha)
 			con |= OVL_CON_AEN;
 	}
 
@@ -584,6 +601,9 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
 
 	mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
 			      DISP_REG_OVL_CON(idx));
+
+	if (mtk_ovl_is_ignore_pixel_alpha(state, blend_mode))
+		ignore_pixel_alpha = OVL_CONST_BLEND;
 	mtk_ddp_write_relaxed(cmdq_pkt, pitch_lsb | ignore_pixel_alpha,
 			      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx));
 	mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
index 3f7d7d54479d..431567538eb5 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
@@ -20,6 +20,7 @@ extern const u32 mt8195_ovl_formats[];
 extern const size_t mt8195_ovl_formats_len;
 
 bool mtk_ovl_is_10bit_rgb(unsigned int fmt);
+bool mtk_ovl_is_ignore_pixel_alpha(struct mtk_plane_state *state, unsigned int blend_mode);
 unsigned int mtk_ovl_get_blend_mode(struct mtk_plane_state *state, unsigned int blend_modes);
 unsigned int mtk_ovl_fmt_convert(unsigned int fmt, unsigned int blend_mode,
 				 bool fmt_rgb565_is_0, bool color_convert,
-- 
2.45.2



From paul-pl.chen at mediatek.com  Thu May 15 02:34:28 2025
From: paul-pl.chen at mediatek.com (paul-pl.chen)
Date: Thu, 15 May 2025 17:34:28 +0800
Subject: [PATCH v3 16/17] drm/mediatek: Add support for multiple mmsys in the one mediatek-drm driver
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
Message-ID: <20250515093454.1729720-17-paul-pl.chen@mediatek.com>

From: Paul-pl Chen <paul-pl.chen at mediatek.com>

To support multiple mmsys instances in the one mediatek-drm instance,
providing improved flexibility and scalability by the following changes:

1. Add DDP_COMPONENT_DRM_OVLSYS_ADAPTOR* to probe the
  ovlsys_adaptor drivers and support different mmsys composition.
2. Added new component types MTK_DISP_VIRTUAL to support the
  routing to virtual display components.
3. Added and adjusted the existed structure or interface to extend
  the support of multiple mmsys instances.
4. Modified the component matching and binding logic to support
  multiple mmsys instances.

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_crtc.c     | 342 +++++++++++++++++++-----
 drivers/gpu/drm/mediatek/mtk_crtc.h     |   6 +-
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 105 +++++---
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h |   2 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  86 +++---
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |  16 +-
 6 files changed, 422 insertions(+), 135 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c
index 8f6fba4217ec..4f91ffdd08ae 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.c
@@ -58,13 +58,17 @@ struct mtk_crtc {
 	wait_queue_head_t		cb_blocking_queue;
 #endif
 
-	struct device			*mmsys_dev;
+	struct device			*mmsys_dev[MAX_MMSYS];
 	struct device			*dma_dev;
-	struct mtk_mutex		*mutex;
+	struct device			*vdisp_ao_dev;
+	struct mtk_mutex		*mutex[MAX_MMSYS];
 	unsigned int			ddp_comp_nr;
 	struct mtk_ddp_comp		**ddp_comp;
+	enum mtk_drm_mmsys		*ddp_comp_sys;
+	bool				exist[MAX_MMSYS];
 	unsigned int			num_conn_routes;
 	const struct mtk_drm_route	*conn_routes;
+	enum mtk_drm_mmsys		conn_routes_sys;
 
 	/* lock for display hardware access */
 	struct mutex			hw_lock;
@@ -82,6 +86,11 @@ struct mtk_crtc_state {
 	unsigned int			pending_vrefresh;
 };
 
+struct mtk_crtc_comp_info {
+	enum mtk_drm_mmsys sys;
+	unsigned int comp_id;
+};
+
 static inline struct mtk_crtc *to_mtk_crtc(struct drm_crtc *c)
 {
 	return container_of(c, struct mtk_crtc, base);
@@ -130,7 +139,10 @@ static void mtk_crtc_destroy(struct drm_crtc *crtc)
 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 	int i;
 
-	mtk_mutex_put(mtk_crtc->mutex);
+	for (i = 0; i < MAX_MMSYS; i++)
+		if (mtk_crtc->mutex[i])
+			mtk_mutex_put(mtk_crtc->mutex[i]);
+
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	if (mtk_crtc->cmdq_client.chan) {
 		cmdq_pkt_destroy(&mtk_crtc->cmdq_client, &mtk_crtc->cmdq_handle);
@@ -228,7 +240,14 @@ static int mtk_crtc_ddp_clk_enable(struct mtk_crtc *mtk_crtc)
 	int i;
 
 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
+		enum mtk_drm_mmsys mmsys;
+
 		ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]);
+		if (mtk_ddp_comp_get_type(mtk_crtc->ddp_comp[i]->id) == MTK_DISP_VIRTUAL) {
+			mmsys = mtk_crtc->ddp_comp_sys[i];
+			ret = mtk_mmsys_ddp_clk_enable(mtk_crtc->mmsys_dev[mmsys],
+						       mtk_crtc->ddp_comp[i]->id);
+		}
 		if (ret) {
 			DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
 			goto err;
@@ -237,17 +256,28 @@ static int mtk_crtc_ddp_clk_enable(struct mtk_crtc *mtk_crtc)
 
 	return 0;
 err:
-	while (--i >= 0)
+	while (--i >= 0) {
 		mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
+		if (mtk_ddp_comp_get_type(mtk_crtc->ddp_comp[i]->id) == MTK_DISP_VIRTUAL)
+			mtk_mmsys_ddp_clk_disable(mtk_crtc->mmsys_dev[mtk_crtc->ddp_comp_sys[i]],
+						  mtk_crtc->ddp_comp[i]->id);
+	}
 	return ret;
 }
 
 static void mtk_crtc_ddp_clk_disable(struct mtk_crtc *mtk_crtc)
 {
 	int i;
+	enum mtk_drm_mmsys mmsys;
 
-	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
+	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 		mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
+		if (mtk_ddp_comp_get_type(mtk_crtc->ddp_comp[i]->id) == MTK_DISP_VIRTUAL) {
+			mmsys = mtk_crtc->ddp_comp_sys[i];
+			mtk_mmsys_ddp_clk_disable(mtk_crtc->mmsys_dev[mmsys],
+						  mtk_crtc->ddp_comp[i]->id);
+		}
+	}
 }
 
 static
@@ -340,7 +370,8 @@ static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_crtc)
 	struct drm_connector_list_iter conn_iter;
 	unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
 	int ret;
-	int i;
+	int i, j;
+	enum mtk_drm_mmsys mmsys;
 
 	if (WARN_ON(!crtc->state))
 		return -EINVAL;
@@ -370,10 +401,18 @@ static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_crtc)
 		return ret;
 	}
 
-	ret = mtk_mutex_prepare(mtk_crtc->mutex);
-	if (ret < 0) {
-		DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
-		goto err_pm_runtime_put;
+	for (i = 0; i < MAX_MMSYS; i++)
+		if (mtk_crtc->exist[i])
+			mtk_mmsys_top_clk_enable(mtk_crtc->mmsys_dev[i]);
+
+	for (i = 0; i < MAX_MMSYS; i++) {
+		if (!mtk_crtc->mutex[i] || !mtk_crtc->exist[i])
+			continue;
+		ret = mtk_mutex_prepare(mtk_crtc->mutex[i]);
+		if (ret < 0) {
+			DRM_ERROR("Failed to enable mmsys%d mutex clock: %d\n", i, ret);
+			goto err_pm_runtime_put;
+		}
 	}
 
 	ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
@@ -382,19 +421,36 @@ static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_crtc)
 		goto err_mutex_unprepare;
 	}
 
+	if (mtk_crtc->vdisp_ao_dev)
+		mtk_mmsys_default_config(mtk_crtc->vdisp_ao_dev);
+
+	for (i = 0; i < MAX_MMSYS; i++)
+		if (mtk_crtc->exist[i])
+			mtk_mmsys_default_config(mtk_crtc->mmsys_dev[i]);
+
 	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
-		if (!mtk_ddp_comp_connect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev,
+		mmsys = mtk_crtc->ddp_comp_sys[i];
+		if (!mtk_ddp_comp_connect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev[mmsys],
 					  mtk_crtc->ddp_comp[i + 1]->id))
-			mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
+			mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev[mmsys],
 					      mtk_crtc->ddp_comp[i]->id,
 					      mtk_crtc->ddp_comp[i + 1]->id);
-		if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
-			mtk_mutex_add_comp(mtk_crtc->mutex,
+		if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex[mmsys]))
+			mtk_mutex_add_comp(mtk_crtc->mutex[mmsys],
 					   mtk_crtc->ddp_comp[i]->id);
 	}
-	if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
-		mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
-	mtk_mutex_enable(mtk_crtc->mutex);
+	mmsys = mtk_crtc->ddp_comp_sys[i];
+	if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex[mmsys]))
+		mtk_mutex_add_comp(mtk_crtc->mutex[mmsys], mtk_crtc->ddp_comp[i]->id);
+
+	/* Need to set sof source for all mmsys mutexes in this crtc */
+	for (j = 0; j < MAX_MMSYS; j++)
+		if (mtk_crtc->exist[j] && mtk_crtc->mutex[j])
+			mtk_mutex_add_comp_sof(mtk_crtc->mutex[j], mtk_crtc->ddp_comp[i]->id);
+
+	for (i = 0; i < MAX_MMSYS; i++)
+		if (mtk_crtc->exist[i] && mtk_crtc->mutex[i])
+			mtk_mutex_enable(mtk_crtc->mutex[i]);
 
 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 		struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
@@ -402,7 +458,11 @@ static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_crtc)
 		if (i == 1)
 			mtk_ddp_comp_bgclr_in_on(comp);
 
-		mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
+		if (mtk_ddp_comp_get_type(comp->id) == MTK_DISP_VIRTUAL)
+			mtk_mmsys_ddp_config(mtk_crtc->mmsys_dev[mtk_crtc->ddp_comp_sys[i]],
+					     comp->id, width, height, NULL);
+		else
+			mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
 		mtk_ddp_comp_start(comp);
 	}
 
@@ -426,7 +486,10 @@ static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_crtc)
 	return 0;
 
 err_mutex_unprepare:
-	mtk_mutex_unprepare(mtk_crtc->mutex);
+	while (--i >= 0)
+		if (mtk_crtc->exist[i] && mtk_crtc->mutex[i])
+			mtk_mutex_unprepare(mtk_crtc->mutex[i]);
+
 err_pm_runtime_put:
 	pm_runtime_put(crtc->dev->dev);
 	return ret;
@@ -437,7 +500,8 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_crtc *mtk_crtc)
 	struct drm_device *drm = mtk_crtc->base.dev;
 	struct drm_crtc *crtc = &mtk_crtc->base;
 	unsigned long flags;
-	int i;
+	int i, j;
+	enum mtk_drm_mmsys mmsys;
 
 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 		mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
@@ -445,27 +509,47 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_crtc *mtk_crtc)
 			mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
 	}
 
-	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
-		if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
-			mtk_mutex_remove_comp(mtk_crtc->mutex,
+	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
+		mmsys = mtk_crtc->ddp_comp_sys[i];
+		if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex[mmsys]))
+			mtk_mutex_remove_comp(mtk_crtc->mutex[mtk_crtc->ddp_comp_sys[i]],
 					      mtk_crtc->ddp_comp[i]->id);
-	mtk_mutex_disable(mtk_crtc->mutex);
+	}
 	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
-		if (!mtk_ddp_comp_disconnect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev,
-					     mtk_crtc->ddp_comp[i + 1]->id))
-			mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
-						 mtk_crtc->ddp_comp[i]->id,
-						 mtk_crtc->ddp_comp[i + 1]->id);
-		if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
-			mtk_mutex_remove_comp(mtk_crtc->mutex,
+		struct mtk_ddp_comp *comp;
+		unsigned int curr, next;
+
+		comp = mtk_crtc->ddp_comp[i];
+		curr = mtk_crtc->ddp_comp[i]->id;
+		next = mtk_crtc->ddp_comp[i + 1]->id;
+		mmsys = mtk_crtc->ddp_comp_sys[i];
+		if (!mtk_ddp_comp_disconnect(comp, mtk_crtc->mmsys_dev[mmsys], next))
+			mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev[mmsys], curr, next);
+		if (!mtk_ddp_comp_remove(comp, mtk_crtc->mutex[mmsys]))
+			mtk_mutex_remove_comp(mtk_crtc->mutex[mtk_crtc->ddp_comp_sys[i]],
 					      mtk_crtc->ddp_comp[i]->id);
+
 	}
-	if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
-		mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
+
+	mmsys = mtk_crtc->ddp_comp_sys[i];
+	if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex[mmsys]))
+		mtk_mutex_remove_comp(mtk_crtc->mutex[mmsys], mtk_crtc->ddp_comp[i]->id);
+
+	/* Need to remove sof source for all mmsys mutexes in this crtc */
+	for (j = 0; j < MAX_MMSYS; j++)
+		if (mtk_crtc->exist[j] && mtk_crtc->mutex[j])
+			mtk_mutex_remove_comp_sof(mtk_crtc->mutex[j], mtk_crtc->ddp_comp[i]->id);
+
 	mtk_crtc_ddp_clk_disable(mtk_crtc);
-	mtk_mutex_unprepare(mtk_crtc->mutex);
+	for (i = 0; i < MAX_MMSYS; i++)
+		if (mtk_crtc->exist[i] && mtk_crtc->mutex[i])
+			mtk_mutex_unprepare(mtk_crtc->mutex[i]);
 
-	pm_runtime_put(drm->dev);
+	for (i = 0; i < MAX_MMSYS; i++)
+		if (mtk_crtc->exist[i])
+			mtk_mmsys_top_clk_disable(mtk_crtc->mmsys_dev[i]);
+
+	pm_runtime_put_sync(drm->dev);
 
 	if (crtc->state->event && !crtc->state->active) {
 		spin_lock_irqsave(&crtc->dev->event_lock, flags);
@@ -589,9 +673,15 @@ static void mtk_crtc_update_config(struct mtk_crtc *mtk_crtc, bool needs_vblank)
 		mtk_crtc->pending_async_planes = true;
 
 	if (priv->data->shadow_register) {
-		mtk_mutex_acquire(mtk_crtc->mutex);
+		for (i = 0; i < MAX_MMSYS; i++)
+			if (mtk_crtc->exist[i] && mtk_crtc->mutex[i])
+				mtk_mutex_acquire(mtk_crtc->mutex[i]);
+
 		mtk_crtc_ddp_config(crtc, NULL);
-		mtk_mutex_release(mtk_crtc->mutex);
+
+		for (i = 0; i < MAX_MMSYS; i++)
+			if (mtk_crtc->exist[i] && mtk_crtc->mutex[i])
+				mtk_mutex_release(mtk_crtc->mutex[i]);
 	}
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	if (mtk_crtc->cmdq_client.chan) {
@@ -675,6 +765,7 @@ static void mtk_crtc_update_output(struct drm_crtc *crtc,
 {
 	int crtc_index = drm_crtc_index(crtc);
 	int i;
+	unsigned int mmsys;
 	struct device *dev;
 	struct drm_crtc_state *crtc_state = state->crtcs[crtc_index].new_state;
 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
@@ -687,7 +778,8 @@ static void mtk_crtc_update_output(struct drm_crtc *crtc,
 	if (!mtk_crtc->num_conn_routes)
 		return;
 
-	priv = ((struct mtk_drm_private *)crtc->dev->dev_private)->all_drm_private[crtc_index];
+	mmsys = mtk_crtc->conn_routes_sys;
+	priv = ((struct mtk_drm_private *)crtc->dev->dev_private)->all_drm_private[mmsys];
 	dev = priv->dev;
 
 	dev_dbg(dev, "connector change:%d, encoder mask:0x%x for crtc:%d\n",
@@ -700,6 +792,8 @@ static void mtk_crtc_update_output(struct drm_crtc *crtc,
 		if (comp->encoder_index >= 0 &&
 		    (encoder_mask & BIT(comp->encoder_index))) {
 			mtk_crtc->ddp_comp[mtk_crtc->ddp_comp_nr - 1] = comp;
+			mtk_crtc->ddp_comp_sys[mtk_crtc->ddp_comp_nr - 1] = mmsys;
+			mtk_crtc->exist[mmsys] = true;
 			dev_dbg(dev, "Add comp_id: %d at path index %d\n",
 				comp->id, mtk_crtc->ddp_comp_nr - 1);
 			break;
@@ -736,9 +830,31 @@ static void mtk_crtc_atomic_enable(struct drm_crtc *crtc,
 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 	int ret;
+	int i, j;
+	int mmsys_cnt = 0;
 
 	DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 
+	for (i = 0; i < MAX_MMSYS; i++)
+		if (mtk_crtc->exist[i])
+			mmsys_cnt++;
+
+	if (mmsys_cnt > 1) {
+		for (i = 0; i < MAX_MMSYS; i++) {
+			if (!mtk_crtc->exist[i])
+				continue;
+			ret = pm_runtime_resume_and_get(mtk_crtc->mmsys_dev[i]);
+			if (ret < 0) {
+				DRM_DEV_ERROR(mtk_crtc->mmsys_dev[i],
+					      "Failed to enable power domain: %d\n", ret);
+				for (j = i - 1; j >= 0; j--)
+					if (mtk_crtc->exist[i])
+						pm_runtime_put(mtk_crtc->mmsys_dev[j]);
+				return;
+			}
+		}
+	}
+
 	ret = mtk_ddp_comp_power_on(comp);
 	if (ret < 0) {
 		DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret);
@@ -762,7 +878,8 @@ static void mtk_crtc_atomic_disable(struct drm_crtc *crtc,
 {
 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
-	int i;
+	int i, ret;
+	int mmsys_cnt = 0;
 
 	DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 	if (!mtk_crtc->enabled)
@@ -794,6 +911,22 @@ static void mtk_crtc_atomic_disable(struct drm_crtc *crtc,
 	mtk_crtc_ddp_hw_fini(mtk_crtc);
 	mtk_ddp_comp_power_off(comp);
 
+	for (i = 0; i < MAX_MMSYS; i++)
+		if (mtk_crtc->exist[i])
+			mmsys_cnt++;
+
+	if (mmsys_cnt > 1) {
+		for (i = 0; i < MAX_MMSYS; i++) {
+			if (mtk_crtc->exist[i]) {
+				ret = pm_runtime_put(mtk_crtc->mmsys_dev[i]);
+				if (ret < 0)
+					DRM_DEV_ERROR(mtk_crtc->mmsys_dev[i],
+						      "Failed to disable power domain: %d\n",
+						      ret);
+			}
+		}
+	}
+
 	mtk_crtc->enabled = false;
 }
 
@@ -953,49 +1086,108 @@ struct device *mtk_crtc_dma_dev_get(struct drm_crtc *crtc)
 	return mtk_crtc->dma_dev;
 }
 
-int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
-		    unsigned int path_len, int priv_data_index,
-		    const struct mtk_drm_route *conn_routes,
-		    unsigned int num_conn_routes)
+int mtk_crtc_create(struct drm_device *drm_dev, enum mtk_crtc_path path_sel)
 {
 	struct mtk_drm_private *priv = drm_dev->dev_private;
 	struct device *dev = drm_dev->dev;
 	struct mtk_crtc *mtk_crtc;
 	unsigned int num_comp_planes = 0;
 	int ret;
-	int i;
+	int i, j, k;
 	bool has_ctm = false;
 	uint gamma_lut_size = 0;
 	struct drm_crtc *tmp;
 	int crtc_i = 0;
-
-	if (!path)
-		return 0;
-
-	priv = priv->all_drm_private[priv_data_index];
+	struct mtk_drm_private *subsys_priv;
+	struct mtk_crtc_comp_info path[DDP_COMPONENT_ID_MAX];
+	unsigned int path_len = 0;
+	const struct mtk_drm_route *conn_routes = NULL;
+	unsigned int num_conn_routes = 0;
+	enum mtk_drm_mmsys conn_mmsys;
 
 	drm_for_each_crtc(tmp, drm_dev)
 		crtc_i++;
 
+	for (j = 0; j < priv->data->mmsys_dev_num; j++) {
+		for (k = 0; k < MAX_MMSYS; k++) {
+			const unsigned int *subsys_path;
+			unsigned int subsys_path_len = 0;
+			unsigned int order = 0;
+
+			subsys_priv = priv->all_drm_private[k];
+			if (!subsys_priv)
+				continue;
+
+			if (path_sel == CRTC_MAIN) {
+				subsys_path = subsys_priv->data->main_path;
+				subsys_path_len = subsys_priv->data->main_len;
+				order = subsys_priv->data->main_order;
+			} else if (path_sel == CRTC_EXT) {
+				subsys_path = subsys_priv->data->ext_path;
+				subsys_path_len = subsys_priv->data->ext_len;
+				order = subsys_priv->data->ext_order;
+			} else if (path_sel == CRTC_THIRD) {
+				subsys_path = subsys_priv->data->third_path;
+				subsys_path_len = subsys_priv->data->third_len;
+				order = subsys_priv->data->third_order;
+			}
+
+			if (subsys_priv->data->num_conn_routes) {
+				conn_routes = subsys_priv->data->conn_routes;
+				num_conn_routes = subsys_priv->data->num_conn_routes;
+				conn_mmsys = subsys_priv->data->mmsys_id;
+			}
+
+			if (j != order)
+				continue;
+			if (!subsys_path_len)
+				continue;
+
+			for (i = 0; i < subsys_path_len; i++) {
+				path[path_len].sys = subsys_priv->data->mmsys_id;
+				path[path_len].comp_id = subsys_path[i];
+				path_len++;
+			}
+		}
+	}
+
+	if (!path_len)
+		return 0;
+
+	if (num_conn_routes) {
+		for (i = 0; i < num_conn_routes; i++)
+			if (conn_routes->crtc_id == crtc_i)
+				break;
+		if (i == num_conn_routes) {
+			num_conn_routes = 0;
+			conn_routes = NULL;
+		}
+	}
+
 	for (i = 0; i < path_len; i++) {
-		enum mtk_ddp_comp_id comp_id = path[i];
+		enum mtk_ddp_comp_id comp_id = path[i].comp_id;
 		struct device_node *node;
 		struct mtk_ddp_comp *comp;
 
+		priv = priv->all_drm_private[path[i].sys];
 		node = priv->comp_node[comp_id];
 		comp = &priv->ddp_comp[comp_id];
 
 		/* Not all drm components have a DTS device node, such as ovl_adaptor,
 		 * which is the drm bring up sub driver
 		 */
-		if (!node && comp_id != DDP_COMPONENT_DRM_OVL_ADAPTOR) {
+		if (!node && comp_id != DDP_COMPONENT_DRM_OVL_ADAPTOR &&
+		    comp_id != DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0 &&
+		    comp_id != DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1 &&
+		    comp_id != DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2 &&
+		    mtk_ddp_comp_get_type(comp_id) != MTK_DISP_VIRTUAL) {
 			dev_info(dev,
 				"Not creating crtc %d because component %d is disabled or missing\n",
 				crtc_i, comp_id);
 			return 0;
 		}
 
-		if (!comp->dev) {
+		if (!comp->dev && mtk_ddp_comp_get_type(comp_id) != MTK_DISP_VIRTUAL) {
 			dev_err(dev, "Component %pOF not initialized\n", node);
 			return -ENODEV;
 		}
@@ -1005,7 +1197,9 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
 	if (!mtk_crtc)
 		return -ENOMEM;
 
-	mtk_crtc->mmsys_dev = priv->mmsys_dev;
+	for (i = 0; i < MAX_MMSYS; i++)
+		if (priv->all_drm_private[i])
+			mtk_crtc->mmsys_dev[i] = priv->all_drm_private[i]->mmsys_dev;
 	mtk_crtc->ddp_comp_nr = path_len;
 	mtk_crtc->ddp_comp = devm_kcalloc(dev,
 					  mtk_crtc->ddp_comp_nr + (conn_routes ? 1 : 0),
@@ -1014,19 +1208,36 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
 	if (!mtk_crtc->ddp_comp)
 		return -ENOMEM;
 
-	mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev);
-	if (IS_ERR(mtk_crtc->mutex)) {
-		ret = PTR_ERR(mtk_crtc->mutex);
-		dev_err(dev, "Failed to get mutex: %d\n", ret);
-		return ret;
+	mtk_crtc->ddp_comp_sys = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr +
+						    (conn_routes ? 1 : 0),
+						    sizeof(*mtk_crtc->ddp_comp_sys), GFP_KERNEL);
+	if (!mtk_crtc->ddp_comp_sys)
+		return -ENOMEM;
+
+	for (i = 0; i < MAX_MMSYS; i++) {
+		if (!priv->all_drm_private[i])
+			continue;
+
+		priv = priv->all_drm_private[i];
+		mtk_crtc->mutex[i] = mtk_mutex_get(priv->mutex_dev);
+		if (IS_ERR(mtk_crtc->mutex[i])) {
+			ret = PTR_ERR(mtk_crtc->mutex[i]);
+			dev_err(dev, "Failed to get mutex: %d\n", ret);
+			return ret;
+		}
 	}
 
 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
-		unsigned int comp_id = path[i];
+		unsigned int comp_id = path[i].comp_id;
 		struct mtk_ddp_comp *comp;
 
+		priv = priv->all_drm_private[path[i].sys];
 		comp = &priv->ddp_comp[comp_id];
+		if (mtk_ddp_comp_get_type(comp_id) == MTK_DISP_VIRTUAL)
+			comp->id = comp_id;
 		mtk_crtc->ddp_comp[i] = comp;
+		mtk_crtc->ddp_comp_sys[i] = path[i].sys;
+		mtk_crtc->exist[path[i].sys] = true;
 
 		if (comp->funcs) {
 			if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) {
@@ -1063,8 +1274,10 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
 	 * In the case of ovl_adaptor sub driver, it needs to use the
 	 * dma_dev_get function to get representative dma dev.
 	 */
-	mtk_crtc->dma_dev = mtk_ddp_comp_dma_dev_get(&priv->ddp_comp[path[0]]);
+	priv = priv->all_drm_private[path[0].sys];
+	mtk_crtc->dma_dev = mtk_ddp_comp_dma_dev_get(&priv->ddp_comp[path[0].comp_id]);
 
+	mtk_crtc->vdisp_ao_dev = priv->vdisp_ao_dev;
 	ret = mtk_crtc_init(drm_dev, mtk_crtc, crtc_i);
 	if (ret < 0)
 		return ret;
@@ -1077,7 +1290,7 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
 
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	i = priv->mbox_index++;
-	mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev;
+	mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev[priv->data->mmsys_id];
 	mtk_crtc->cmdq_client.client.tx_block = false;
 	mtk_crtc->cmdq_client.client.knows_txdone = true;
 	mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb;
@@ -1117,6 +1330,7 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
 #endif
 
 	if (conn_routes) {
+		priv = priv->all_drm_private[conn_mmsys];
 		for (i = 0; i < num_conn_routes; i++) {
 			unsigned int comp_id = conn_routes[i].route_ddp;
 			struct device_node *node = priv->comp_node[comp_id];
@@ -1133,6 +1347,7 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
 			mtk_ddp_comp_encoder_index_set(&priv->ddp_comp[comp_id]);
 		}
 
+		mtk_crtc->conn_routes_sys = conn_mmsys;
 		mtk_crtc->num_conn_routes = num_conn_routes;
 		mtk_crtc->conn_routes = conn_routes;
 
@@ -1140,5 +1355,10 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
 		mtk_crtc->ddp_comp_nr++;
 	}
 
+	for (i = 0; i < MAX_MMSYS; i++)
+		if (mtk_crtc->exist[i])
+			device_link_add(mtk_crtc->base.dev->dev,
+					priv->all_drm_private[i]->mutex_dev, 0);
+
 	return 0;
 }
diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.h b/drivers/gpu/drm/mediatek/mtk_crtc.h
index 388e900b6f4d..255f2823d17a 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.h
@@ -15,10 +15,8 @@
 #define MTK_MIN_BPC	3
 
 void mtk_crtc_commit(struct drm_crtc *crtc);
-int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
-		    unsigned int path_len, int priv_data_index,
-		    const struct mtk_drm_route *conn_routes,
-		    unsigned int num_conn_routes);
+int mtk_crtc_create(struct drm_device *drm_dev,
+		    enum mtk_crtc_path path_sel);
 int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
 			 struct mtk_plane_state *state);
 void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index c96e027359ac..505edee09cb9 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -467,6 +467,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_PWM] = "pwm",
 	[MTK_DISP_RDMA] = "rdma",
 	[MTK_DISP_UFOE] = "ufoe",
+	[MTK_DISP_VIRTUAL] = "virtual",
 	[MTK_DISP_WDMA] = "wdma",
 	[MTK_DP_INTF] = "dp-intf",
 	[MTK_DPI] = "dpi",
@@ -490,6 +491,15 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
 	[DDP_COMPONENT_COLOR0]		= { MTK_DISP_COLOR,		0, &ddp_color },
 	[DDP_COMPONENT_COLOR1]		= { MTK_DISP_COLOR,		1, &ddp_color },
 	[DDP_COMPONENT_DITHER0]		= { MTK_DISP_DITHER,		0, &ddp_dither },
+	[DDP_COMPONENT_DLI_ASYNC0]      = { MTK_DISP_VIRTUAL,           -1, NULL },
+	[DDP_COMPONENT_DLI_ASYNC1]      = { MTK_DISP_VIRTUAL,           -1, NULL },
+	[DDP_COMPONENT_DLI_ASYNC8]      = { MTK_DISP_VIRTUAL,           -1, NULL },
+	[DDP_COMPONENT_DLI_ASYNC21]     = { MTK_DISP_VIRTUAL,           -1, NULL },
+	[DDP_COMPONENT_DLI_ASYNC22]     = { MTK_DISP_VIRTUAL,           -1, NULL },
+	[DDP_COMPONENT_DLI_ASYNC23]     = { MTK_DISP_VIRTUAL,           -1, NULL },
+	[DDP_COMPONENT_DLO_ASYNC1]      = { MTK_DISP_VIRTUAL,           -1, NULL },
+	[DDP_COMPONENT_DLO_ASYNC2]      = { MTK_DISP_VIRTUAL,           -1, NULL },
+	[DDP_COMPONENT_DLO_ASYNC3]      = { MTK_DISP_VIRTUAL,           -1, NULL },
 	[DDP_COMPONENT_DP_INTF0]	= { MTK_DP_INTF,		0, &ddp_dpi },
 	[DDP_COMPONENT_DP_INTF1]	= { MTK_DP_INTF,		1, &ddp_dpi },
 	[DDP_COMPONENT_DPI0]		= { MTK_DPI,			0, &ddp_dpi },
@@ -497,6 +507,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
 	[DDP_COMPONENT_DRM_OVL_ADAPTOR]	= { MTK_DISP_OVL_ADAPTOR,	0, &ddp_ovl_adaptor },
 	[DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0] = { MTK_DISP_OVLSYS_ADAPTOR, 0, &ddp_ovlsys_adaptor},
 	[DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1] = { MTK_DISP_OVLSYS_ADAPTOR, 1, &ddp_ovlsys_adaptor},
+	[DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2] = { MTK_DISP_OVLSYS_ADAPTOR, 2, &ddp_ovlsys_adaptor},
 	[DDP_COMPONENT_DSC0]		= { MTK_DISP_DSC,		0, &ddp_dsc },
 	[DDP_COMPONENT_DSC1]		= { MTK_DISP_DSC,		1, &ddp_dsc },
 	[DDP_COMPONENT_DSI0]		= { MTK_DSI,			0, &ddp_dsi },
@@ -513,7 +524,10 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
 	[DDP_COMPONENT_OD0]		= { MTK_DISP_OD,		0, &ddp_od },
 	[DDP_COMPONENT_OD1]		= { MTK_DISP_OD,		1, &ddp_od },
 	[DDP_COMPONENT_OVL0]		= { MTK_DISP_OVL,		0, &ddp_ovl },
+	[DDP_COMPONENT_OVL0_DLO_ASYNC5] = { MTK_DISP_VIRTUAL,           -1, NULL },
+	[DDP_COMPONENT_OVL0_DLO_ASYNC6] = { MTK_DISP_VIRTUAL,           -1, NULL },
 	[DDP_COMPONENT_OVL1]		= { MTK_DISP_OVL,		1, &ddp_ovl },
+	[DDP_COMPONENT_OVL1_DLO_ASYNC5] = { MTK_DISP_VIRTUAL,           -1, NULL },
 	[DDP_COMPONENT_OVL_2L0]		= { MTK_DISP_OVL_2L,		0, &ddp_ovl },
 	[DDP_COMPONENT_OVL_2L1]		= { MTK_DISP_OVL_2L,		1, &ddp_ovl },
 	[DDP_COMPONENT_OVL_2L2]		= { MTK_DISP_OVL_2L,		2, &ddp_ovl },
@@ -564,18 +578,24 @@ static int mtk_ddp_comp_find_in_route(struct device *dev,
 	return -ENODEV;
 }
 
+enum mtk_ddp_comp_type mtk_ddp_comp_get_type(unsigned int comp_id)
+{
+	return mtk_ddp_matches[comp_id].type;
+}
+
 static bool mtk_ddp_path_available(const unsigned int *path,
 				   unsigned int path_len,
 				   struct device_node **comp_node)
 {
 	unsigned int i;
 
-	if (!path || !path_len)
-		return false;
-
 	for (i = 0U; i < path_len; i++) {
 		/* OVL_ADAPTOR doesn't have a device node */
-		if (path[i] == DDP_COMPONENT_DRM_OVL_ADAPTOR)
+		if (path[i] == DDP_COMPONENT_DRM_OVL_ADAPTOR ||
+		    path[i] == DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0 ||
+		    path[i] == DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1 ||
+		    path[i] == DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2 ||
+		    mtk_ddp_comp_get_type(path[i]) == MTK_DISP_VIRTUAL)
 			continue;
 
 		if (!comp_node[path[i]])
@@ -605,39 +625,52 @@ int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev)
 	struct mtk_drm_private *private = drm->dev_private;
 	const struct mtk_mmsys_driver_data *data;
 	struct mtk_drm_private *priv_n;
-	int i = 0, j;
-	int ret;
+	int i, j, count = 0, ret;
+
+	/* search each path in private data */
+	for (i = 0; i < MAX_CRTC; i++) {
+		bool found = false;
+		int avail_mmsys_num = 0;
+
+		for (j = 0; j < private->data->mmsys_dev_num; j++) {
+			const unsigned int *path = NULL;
+			unsigned int path_len = 0;
+
+			priv_n = private->all_drm_private[j];
+			data = priv_n->data;
+
+			if (i == CRTC_MAIN) {
+				path = data->main_path;
+				path_len = data->main_len;
+			} else if (i == CRTC_EXT) {
+				path = data->ext_path;
+				path_len = data->ext_len;
+			} else if (i == CRTC_THIRD) {
+				path = data->third_path;
+				path_len = data->third_len;
+			}
+
+			/* skip if no path data in current mmsys */
+			if (path_len == 0 || !path) {
+				avail_mmsys_num++;
+				continue;
+			}
+
+			if (mtk_ddp_path_available(path, path_len, priv_n->comp_node))
+				avail_mmsys_num++;
+
+			if (mtk_ddp_comp_find(dev, path, path_len, priv_n->ddp_comp))
+				found = true;
+	}
+
+		/* skip invalid path */
+		if (avail_mmsys_num != private->data->mmsys_dev_num)
+			continue;
+
+		if (found)
+			return BIT(count);
 
-	for (j = 0; j < private->data->mmsys_dev_num; j++) {
-		priv_n = private->all_drm_private[j];
-		data = priv_n->data;
-
-		if (mtk_ddp_path_available(data->main_path, data->main_len,
-					   priv_n->comp_node)) {
-			if (mtk_ddp_comp_find(dev, data->main_path,
-					      data->main_len,
-					      priv_n->ddp_comp))
-				return BIT(i);
-			i++;
-		}
-
-		if (mtk_ddp_path_available(data->ext_path, data->ext_len,
-					   priv_n->comp_node)) {
-			if (mtk_ddp_comp_find(dev, data->ext_path,
-					      data->ext_len,
-					      priv_n->ddp_comp))
-				return BIT(i);
-			i++;
-		}
-
-		if (mtk_ddp_path_available(data->third_path, data->third_len,
-					   priv_n->comp_node)) {
-			if (mtk_ddp_comp_find(dev, data->third_path,
-					      data->third_len,
-					      priv_n->ddp_comp))
-				return BIT(i);
-			i++;
-		}
+			count++;
 	}
 
 	ret = mtk_ddp_comp_find_in_route(dev,
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index ef64ce7a071f..badb42bd4f7c 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -40,6 +40,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_PWM,
 	MTK_DISP_RDMA,
 	MTK_DISP_UFOE,
+	MTK_DISP_VIRTUAL,
 	MTK_DISP_WDMA,
 	MTK_DPI,
 	MTK_DP_INTF,
@@ -47,6 +48,7 @@ enum mtk_ddp_comp_type {
 	MTK_OVL_BLENDER,
 	MTK_OVL_EXDMA,
 	MTK_OVL_OUTPROC,
+	MTK_VDISP_AO,
 	MTK_DDP_COMP_TYPE_MAX,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 4cf48fe7f0f1..1e49ca3fef80 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -374,7 +374,7 @@ static int mtk_drm_match(struct device *dev, const void *data)
 static bool mtk_drm_get_all_drm_priv(struct device *dev)
 {
 	struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
-	struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+	struct mtk_drm_private *all_drm_priv[MAX_MMSYS] = {NULL};
 	struct mtk_drm_private *temp_drm_priv;
 	struct device_node *phandle = dev->parent->of_node;
 	const struct of_device_id *of_id;
@@ -402,26 +402,22 @@ static bool mtk_drm_get_all_drm_priv(struct device *dev)
 		if (!temp_drm_priv)
 			continue;
 
-		if (temp_drm_priv->data->main_len)
-			all_drm_priv[CRTC_MAIN] = temp_drm_priv;
-		else if (temp_drm_priv->data->ext_len)
-			all_drm_priv[CRTC_EXT] = temp_drm_priv;
-		else if (temp_drm_priv->data->third_len)
-			all_drm_priv[CRTC_THIRD] = temp_drm_priv;
+		all_drm_priv[temp_drm_priv->data->mmsys_id] = temp_drm_priv;
 
 		if (temp_drm_priv->mtk_drm_bound)
 			cnt++;
 
-		if (cnt == MAX_CRTC) {
+		if (cnt == temp_drm_priv->data->mmsys_dev_num) {
 			of_node_put(node);
 			break;
 		}
 	}
 
 	if (drm_priv->data->mmsys_dev_num == cnt) {
-		for (i = 0; i < cnt; i++)
-			for (j = 0; j < cnt; j++)
-				all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
+		for (i = 0; i < MAX_MMSYS; i++)
+			for (j = 0; j < MAX_MMSYS; j++)
+				if (all_drm_priv[j])
+					all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
 
 		return true;
 	}
@@ -494,7 +490,10 @@ static int mtk_drm_kms_init(struct drm_device *drm)
 	drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
 	drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
 
-	for (i = 0; i < private->data->mmsys_dev_num; i++) {
+	for (i = 0; i < MAX_MMSYS; i++) {
+		if (!private->all_drm_private[i])
+			continue;
+
 		drm->dev_private = private->all_drm_private[i];
 		ret = component_bind_all(private->all_drm_private[i]->dev, drm);
 		if (ret)
@@ -517,8 +516,10 @@ static int mtk_drm_kms_init(struct drm_device *drm)
 	 *    third path.
 	 */
 	for (i = 0; i < MAX_CRTC; i++) {
-		for (j = 0; j < private->data->mmsys_dev_num; j++) {
+		for (j = 0; j < MAX_MMSYS; j++) {
 			priv_n = private->all_drm_private[j];
+			if (!priv_n)
+				continue;
 
 			if (priv_n->data->max_width)
 				drm->mode_config.max_width = priv_n->data->max_width;
@@ -530,28 +531,23 @@ static int mtk_drm_kms_init(struct drm_device *drm)
 				drm->mode_config.min_height = priv_n->data->min_height;
 
 			if (i == CRTC_MAIN && priv_n->data->main_len) {
-				ret = mtk_crtc_create(drm, priv_n->data->main_path,
-						      priv_n->data->main_len, j,
-						      priv_n->data->conn_routes,
-						      priv_n->data->num_conn_routes);
+				ret = mtk_crtc_create(drm, CRTC_MAIN);
 				if (ret)
 					goto err_component_unbind;
 
-				continue;
+				break;
 			} else if (i == CRTC_EXT && priv_n->data->ext_len) {
-				ret = mtk_crtc_create(drm, priv_n->data->ext_path,
-						      priv_n->data->ext_len, j, NULL, 0);
+				ret = mtk_crtc_create(drm, CRTC_EXT);
 				if (ret)
 					goto err_component_unbind;
 
-				continue;
+				break;
 			} else if (i == CRTC_THIRD && priv_n->data->third_len) {
-				ret = mtk_crtc_create(drm, priv_n->data->third_path,
-						      priv_n->data->third_len, j, NULL, 0);
+				ret = mtk_crtc_create(drm, CRTC_THIRD);
 				if (ret)
 					goto err_component_unbind;
 
-				continue;
+				break;
 			}
 		}
 	}
@@ -570,8 +566,9 @@ static int mtk_drm_kms_init(struct drm_device *drm)
 		goto err_component_unbind;
 	}
 
-	for (i = 0; i < private->data->mmsys_dev_num; i++)
-		private->all_drm_private[i]->dma_dev = dma_dev;
+	for (i = 0; i < MAX_MMSYS; i++)
+		if (private->all_drm_private[i])
+			private->all_drm_private[i]->dma_dev = dma_dev;
 
 	/*
 	 * Configure the DMA segment size to make sure we get contiguous IOVA
@@ -589,11 +586,13 @@ static int mtk_drm_kms_init(struct drm_device *drm)
 	return 0;
 
 err_component_unbind:
-	for (i = 0; i < private->data->mmsys_dev_num; i++)
-		component_unbind_all(private->all_drm_private[i]->dev, drm);
+	for (i = 0; i < MAX_MMSYS; i++)
+		if (private->all_drm_private[i])
+			component_unbind_all(private->all_drm_private[i]->dev, drm);
 put_mutex_dev:
-	for (i = 0; i < private->data->mmsys_dev_num; i++)
-		put_device(private->all_drm_private[i]->mutex_dev);
+	for (i = 0; i < MAX_MMSYS; i++)
+		if (private->all_drm_private[i])
+			put_device(private->all_drm_private[i]->mutex_dev);
 
 	return ret;
 }
@@ -657,6 +656,19 @@ static int mtk_drm_bind(struct device *dev)
 	}
 
 	private->mutex_dev = &pdev->dev;
+
+	if (private->vdisp_ao_node) {
+		pdev = of_find_device_by_node(private->vdisp_ao_node);
+		if (!pdev) {
+			dev_err(dev, "Waiting for vdisp_ao device %pOF\n",
+				private->vdisp_ao_node);
+			of_node_put(private->mutex_node);
+			of_node_put(private->vdisp_ao_node);
+			return -EPROBE_DEFER;
+		}
+		private->vdisp_ao_dev = &pdev->dev;
+	}
+
 	private->mtk_drm_bound = true;
 	private->dev = dev;
 
@@ -669,8 +681,9 @@ static int mtk_drm_bind(struct device *dev)
 
 	private->drm_master = true;
 	drm->dev_private = private;
-	for (i = 0; i < private->data->mmsys_dev_num; i++)
-		private->all_drm_private[i]->drm = drm;
+	for (i = 0; i < MAX_MMSYS; i++)
+		if (private->all_drm_private[i])
+			private->all_drm_private[i]->drm = drm;
 
 	ret = mtk_drm_kms_init(drm);
 	if (ret < 0)
@@ -1132,7 +1145,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		private->data = mtk_drm_data;
 	}
 
-	private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num,
+	private->all_drm_private = devm_kmalloc_array(dev, MAX_MMSYS,
 						      sizeof(*private->all_drm_private),
 						      GFP_KERNEL);
 	if (!private->all_drm_private)
@@ -1170,6 +1183,12 @@ static int mtk_drm_probe(struct platform_device *pdev)
 			continue;
 		}
 
+		if (comp_type == MTK_VDISP_AO) {
+			private->vdisp_ao_node = of_node_get(node);
+			dev_dbg(dev, "get vdisp_ao node");
+			continue;
+		}
+
 		comp_id = mtk_ddp_comp_get_id(node, comp_type);
 		if (comp_id < 0) {
 			dev_warn(dev, "Skipping unknown component %pOF\n",
@@ -1245,6 +1264,7 @@ static void mtk_drm_remove(struct platform_device *pdev)
 	component_master_del(&pdev->dev, &mtk_drm_ops);
 	pm_runtime_disable(&pdev->dev);
 	of_node_put(private->mutex_node);
+	of_node_put(private->vdisp_ao_node);
 	for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
 		of_node_put(private->comp_node[i]);
 }
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 54f320244511..bdd4dc5cefeb 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -13,7 +13,8 @@
 #define DDP_COMPONENT_DRM_OVL_ADAPTOR (DDP_COMPONENT_ID_MAX + 1)
 #define DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0 (DDP_COMPONENT_DRM_OVL_ADAPTOR + 1)
 #define DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1 (DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0 + 1)
-#define DDP_COMPONENT_DRM_ID_MAX (DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1 + 1)
+#define DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2 (DDP_COMPONENT_DRM_OVLSYS_ADAPTOR1 + 1)
+#define DDP_COMPONENT_DRM_ID_MAX (DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2 + 1)
 
 enum mtk_crtc_path {
 	CRTC_MAIN,
@@ -22,6 +23,14 @@ enum mtk_crtc_path {
 	MAX_CRTC,
 };
 
+enum mtk_drm_mmsys {
+	DISPSYS0,
+	DISPSYS1,
+	OVLSYS0,
+	OVLSYS1,
+	MAX_MMSYS,
+};
+
 struct device;
 struct device_node;
 struct drm_crtc;
@@ -38,10 +47,13 @@ struct mtk_drm_route {
 struct mtk_mmsys_driver_data {
 	const unsigned int *main_path;
 	unsigned int main_len;
+	unsigned int main_order;
 	const unsigned int *ext_path;
 	unsigned int ext_len;
+	unsigned int ext_order;
 	const unsigned int *third_path;
 	unsigned int third_len;
+	unsigned int third_order;
 	const struct mtk_drm_route *conn_routes;
 	unsigned int num_conn_routes;
 
@@ -63,6 +75,8 @@ struct mtk_drm_private {
 	struct device_node *mutex_node;
 	struct device *mutex_dev;
 	struct device *mmsys_dev;
+	struct device_node *vdisp_ao_node;
+	struct device *vdisp_ao_dev;
 	struct device_node *comp_node[DDP_COMPONENT_DRM_ID_MAX];
 	struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_DRM_ID_MAX];
 	struct mtk_mmsys_driver_data *data;
-- 
2.45.2



From louisalexis.eyraud at collabora.com  Thu May 15 03:04:11 2025
From: louisalexis.eyraud at collabora.com (Louis-Alexis Eyraud)
Date: Thu, 15 May 2025 12:04:11 +0200
Subject: [PATCH] arm64: dts: mt8365-evk: Add goodix touchscreen support
Message-ID: <20250515-mt8365-evk-enable-touchscreen-v1-1-7ba3c87b2a71@collabora.com>

The Mediatek Genio 350-EVK board has on the DSI0 connector a StarTek
KD070FHFID015 display panel that uses a Goodix GT9271 I2C capacitive
touch controller.

The mt8365-evk devicetree already have the display panel support but
lacks the touchscreen support, so add it.

Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>
---
Tested on a Mediatek Genio 350-EVK board with a kernel
based on linux-next (tag: next-20250514).
---
 arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 40 +++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index 1f8584bd66c33744c3a2f29ae9bb19c934588ce0..ea75f87acf746d61a982dadf0d96cff9076c06a6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -69,6 +69,21 @@ memory at 40000000 {
 		reg = <0 0x40000000 0 0xc0000000>;
 	};
 
+	reg_vsys: regulator-vsys {
+		compatible = "regulator-fixed";
+		regulator-name = "vsys";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	touch0_fixed_3v3: regulator-5 {
+		compatible = "regulator-fixed";
+		regulator-name = "vio33_tp";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&reg_vsys>;
+	};
+
 	usb_otg_vbus: regulator-0 {
 		compatible = "regulator-fixed";
 		regulator-name = "otg_vbus";
@@ -324,6 +339,18 @@ hdmi_connector_out: endpoint at 0 {
 			};
 		};
 	};
+
+	touchscreen at 5d {
+		compatible = "goodix,gt9271";
+		reg = <0x5d>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touch_pins>;
+		interrupts-extended = <&pio 78 IRQ_TYPE_EDGE_FALLING>;
+		irq-gpios = <&pio 78 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&pio 79 GPIO_ACTIVE_LOW>;
+		AVDD28-supply = <&touch0_fixed_3v3>;
+		VDDIO-supply = <&mt6357_vrf12_reg>;
+	};
 };
 
 &mmc0 {
@@ -650,6 +677,19 @@ cmd-dat-pins {
 		};
 	};
 
+	touch_pins: touch-pins {
+		ctp-int1-pins {
+			pinmux = <MT8365_PIN_78_CMHSYNC__FUNC_GPIO78>;
+			input-enable;
+			bias-disable;
+		};
+
+		rst-pins {
+			pinmux = <MT8365_PIN_79_CMVSYNC__FUNC_GPIO79>;
+			output-low;
+		};
+	};
+
 	uart0_pins: uart0-pins {
 		pins {
 			pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,

---
base-commit: ccb396cc1664a9a367831fb43de67776547354f4
change-id: 20250513-mt8365-evk-enable-touchscreen-a2652cfdf85e

Best regards,
-- 
Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>



From robh at kernel.org  Thu May 15 03:48:30 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Thu, 15 May 2025 05:48:30 -0500
Subject: [PATCH v3 02/17] dt-bindings: display: mediatek: add EXDMA
 yaml for MT8196
In-Reply-To: <20250515093454.1729720-3-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
 <20250515093454.1729720-3-paul-pl.chen@mediatek.com>
Message-ID: <174730611044.164934.18396756831118218280.robh@kernel.org>


On Thu, 15 May 2025 17:34:14 +0800, paul-pl.chen wrote:
> From: Paul-pl Chen <paul-pl.chen at mediatek.com>
> 
> Add mediatek,exdma.yaml to support EXDMA for MT8196.
> The MediaTek display overlap extended DMA engine, namely
> OVL_EXDMA or EXDMA, primarily functions as a DMA engine
> for reading data from DRAM with various DRAM footprints
> and data formats.
> 
> Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
> Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
> ---
>  .../bindings/dma/mediatek,exdma.yaml          | 68 +++++++++++++++++++
>  1 file changed, 68 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/mediatek,exdma.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/dma/mediatek,exdma.example.dtb: dma-controller at 32850000 (mediatek,mt8196-exdma): 'mediatek,larb' is a required property
	from schema $id: http://devicetree.org/schemas/dma/mediatek,exdma.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250515093454.1729720-3-paul-pl.chen at mediatek.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.



From SkyLake.Huang at mediatek.com  Thu May 15 05:16:50 2025
From: SkyLake.Huang at mediatek.com (=?utf-8?B?U2t5TGFrZSBIdWFuZyAo6buD5ZWf5r6kKQ==?=)
Date: Thu, 15 May 2025 12:16:50 +0000
Subject: [PATCH net-next v3 1/2] net: phy: mediatek: Sort config and file
 names in Kconfig and Makefile
In-Reply-To: <2147e0e3-44c0-4fd8-916d-53291dc86a6a@lunn.ch>
References: <20250514105738.1438421-1-SkyLake.Huang@mediatek.com>
	 <20250514105738.1438421-2-SkyLake.Huang@mediatek.com>
	 <2147e0e3-44c0-4fd8-916d-53291dc86a6a@lunn.ch>
Message-ID: <ccbe276a0e04b4ac6d001cd7b32a65e268be8382.camel@mediatek.com>

On Wed, 2025-05-14 at 14:09 +0200, Andrew Lunn wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On Wed, May 14, 2025 at 06:57:37PM +0800, Sky Huang wrote:
> > From: Sky Huang <skylake.huang at mediatek.com>
> > 
> > Sort config and file names in Kconfig and Makefile in
> > drivers/net/phy/mediatek/ according to sequence in MAINTAINERS.
> 
> If you use "make menuconfig" you will notice PHYs are sorted by
> tristate string. So having Gigabit before Soc is correct.
> 
> > --- a/drivers/net/phy/mediatek/Makefile
> > +++ b/drivers/net/phy/mediatek/Makefile
> > @@ -1,4 +1,4 @@
> > ?# SPDX-License-Identifier: GPL-2.0
> > +obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)??? += mtk-ge-soc.o
> > ?obj-$(CONFIG_MTK_NET_PHYLIB)???????? += mtk-phy-lib.o
> > ?obj-$(CONFIG_MEDIATEK_GE_PHY)??????????????? += mtk-ge.o
> > -obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)??? += mtk-ge-soc.o
> 
> These should be in alphabetic order based on CONFIG_. So
> CONFIG_MTK_NET_PHYLIB is what should move.
> 
> ??? Andrew
> 
> ---
> pw-bot: crq:

Oops. I misunderstood what you said in previous patchset.
I'll rearrange this to:
obj-$(CONFIG_MEDIATEK_GE_PHY)        += mtk-ge.o
obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)    += mtk-ge-soc.o
obj-$(CONFIG_MTK_NET_PHYLIB)         += mtk-phy-lib.o

BRs,
Sky


From SkyLake.Huang at mediatek.com  Thu May 15 05:25:15 2025
From: SkyLake.Huang at mediatek.com (=?utf-8?B?U2t5TGFrZSBIdWFuZyAo6buD5ZWf5r6kKQ==?=)
Date: Thu, 15 May 2025 12:25:15 +0000
Subject: [PATCH net-next v3 2/2] net: phy: mediatek: add driver for
 built-in 2.5G ethernet PHY on MT7988
In-Reply-To: <aCSI5k7uUgAlpSsy@shell.armlinux.org.uk>
References: <20250514105738.1438421-1-SkyLake.Huang@mediatek.com>
	 <20250514105738.1438421-3-SkyLake.Huang@mediatek.com>
	 <aCSI5k7uUgAlpSsy@shell.armlinux.org.uk>
Message-ID: <cbf06762c32abd39a309a125f8c4ce678a8e6afd.camel@mediatek.com>

On Wed, 2025-05-14 at 13:13 +0100, Russell King (Oracle) wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Hi,
> 
> On Wed, May 14, 2025 at 06:57:38PM +0800, Sky Huang wrote:
> > +#define MTK_2P5GPHY_ID_MT7988??????????????? (0x00339c11)
> > +
> > +#define MT7988_2P5GE_PMB_FW????????? "mediatek/mt7988/i2p5ge-phy-
> > pmb.bin"
> > +#define MT7988_2P5GE_PMB_FW_SIZE???? (0x20000)
> > +#define MT7988_2P5GE_PMB_FW_BASE???? (0x0f100000)
> > +#define MT7988_2P5GE_PMB_FW_LEN????????????? (0x20000)
> > +#define MTK_2P5GPHY_MCU_CSR_BASE???? (0x0f0f0000)
> > +#define MTK_2P5GPHY_MCU_CSR_LEN????????????? (0x20)
> > +#define MD32_EN_CFG????????????????? (0x18)
> 
> These parens are all unnecessary, as are ones below around a simple
> number.
> 
I'll clean this up in v4.

> > +#define?? MD32_EN??????????????????? BIT(0)
> > +
> > +#define BASE100T_STATUS_EXTEND?????????????? (0x10)
> > +#define BASE1000T_STATUS_EXTEND????????????? (0x11)
> > +#define EXTEND_CTRL_AND_STATUS?????????????? (0x16)
> > +
> > +#define PHY_AUX_CTRL_STATUS????????? (0x1d)
> > +#define?? PHY_AUX_DPX_MASK?????????? GENMASK(5, 5)
> > +#define?? PHY_AUX_SPEED_MASK???????? GENMASK(4, 2)
> > +
> > +/* Registers on MDIO_MMD_VEND1 */
> > +#define MTK_PHY_LPI_PCS_DSP_CTRL???????????? (0x121)
> 
> ...
> 
> > +static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev)
> > +{
> > +???? void __iomem *mcu_csr_base, *pmb_addr;
> > +???? struct device *dev = &phydev->mdio.dev;
> 
> This will attract a comment about reverse christmas tree.
> 
Thanks. I missed this part. I'll fix it in v4.

> > +???? const struct firmware *fw;
> > +???? int ret, i;
> > +???? u32 reg;
> 
> ...
> 
> > +static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
> > +{
> > +???? struct pinctrl *pinctrl;
> > +
> > +???? /* Check if PHY interface type is compatible */
> > +???? if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL)
> > +???????????? return -ENODEV;
> > +
> > +???? /* Setup LED */
> > +???? phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
> > MTK_PHY_LED0_ON_CTRL,
> > +????????????????????? MTK_PHY_LED_ON_POLARITY |
> > MTK_PHY_LED_ON_LINK10 |
> > +????????????????????? MTK_PHY_LED_ON_LINK100 |
> > MTK_PHY_LED_ON_LINK1000 |
> > +????????????????????? MTK_PHY_LED_ON_LINK2500);
> > +???? phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
> > MTK_PHY_LED1_ON_CTRL,
> > +????????????????????? MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX);
> > +
> > +???? /* Switch pinctrl after setting polarity to avoid bogus
> > blinking */
> > +???? pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev,
> > "i2p5gbe-led");
> > +???? if (IS_ERR(pinctrl))
> > +???????????? dev_err(&phydev->mdio.dev, "Fail to set LED
> > pins!\n");
> 
> No, don't do this. config_init() can be called multiple times during
> the lifetime of the driver bound to the device, and each time it is,
> a new managed-dev structure will be allocated to release this action
> each time, thus consuming more and more memory, or possibly failing
> after the first depending on the pinctrl_get_select() behaviour.
> Please find a different way.
> 
I'll move this part (LED initialization) to .probe then.

> ...
> 
> > +static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
> > +{
> > +???? bool changed = false;
> > +???? u32 adv;
> > +???? int ret;
> > +
> > +???? ret = genphy_c45_an_config_aneg(phydev);
> > +???? if (ret < 0)
> > +???????????? return ret;
> > +???? if (ret > 0)
> > +???????????? changed = true;
> > +
> > +???? /* Clause 45 doesn't define 1000BaseT support. Use Clause 22
> > instead in
> > +????? * our design.
> > +????? */
> > +???? adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
> > +???? ret = phy_modify_changed(phydev, MII_CTRL1000,
> > ADVERTISE_1000FULL, adv);
> > +???? if (ret < 0)
> > +???????????? return ret;
> > +???? if (ret > 0)
> > +???????????? changed = true;
> > +
> > +???? return __genphy_config_aneg(phydev, changed);
> 
> Do you want this (which will program EEE and the 10/100 advert) or do
> you want genphy_check_and_restart_aneg() here? Note that
> genphy_c45_an_config_aneg() will already have programmed both the EEE
> and 10/100 adverts via the C45 registers.
> 
> Thanks.
> 
I'll replace "return __genphy_config_aneg(phydev, changed);" with
"return genphy_c45_check_and_restart_aneg(phydev, changed);".

BRs,
Sky

> --
> RMK's Patch system:
> https://urldefense.com/v3/__https://www.armlinux.org.uk/developer/patches/__;!!CTRNKA9wMg0ARbw!iEpNINN4map9ydq6phOk034MHxZo6vhBJJn7U5XFcEMHthdxJrjhgfHUdsH5R3wJAUyyPe_DlFIiuRWE0GE3Uz0$
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!


From julien.massot at collabora.com  Thu May 15 06:31:42 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Thu, 15 May 2025 15:31:42 +0200
Subject: [PATCH 0/3] mt8188: Fix missing reset and clock-names DT
 properties
Message-ID: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>

Hi all,

This patch series addresses some issues found in the MediaTek MT8188 device tree
and its corresponding bindings:

The #reset-cells property was missing in the MT8188 clock controller binding and
device tree nodes. This causes DT validation errors.

The clock-names property was missing from the Global Command Engine (GCE) mailbox node,
which also triggers a dtb-check failure.

Patch 1 updates the binding to declare #reset-cells as a valid property.
Patch 2 adds #reset-cells to all affected nodes in mt8188.dtsi.
Patch 3 fixes the missing clock-names property in the GCE node.

To: kernel at collabora.com
To: Michael Turquette <mturquette at baylibre.com>
To: Stephen Boyd <sboyd at kernel.org>
To: Rob Herring <robh at kernel.org>
To: Krzysztof Kozlowski <krzk+dt at kernel.org>
To: Conor Dooley <conor+dt at kernel.org>
To: Matthias Brugger <matthias.bgg at gmail.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
To: Garmin Chang <garmin.chang at mediatek.com>
To: Friday Yang <friday.yang at mediatek.com>
Cc: Conor Dooley <conor.dooley at microchip.com>
Cc: linux-clk at vger.kernel.org
Cc: devicetree at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-mediatek at lists.infradead.org

Signed-off-by: Julien Massot <julien.massot at collabora.com>
---
Julien Massot (3):
      dt-bindings: clock: mediatek: Add #reset-cells property for MT8188
      arm64: dts: mediatek: mt8188: Add missing #reset-cells property
      arm64: dts: mediatek: mt8188: gce: add missing 'clock-names'

 .../devicetree/bindings/clock/mediatek,mt8188-clock.yaml     |  3 +++
 arch/arm64/boot/dts/mediatek/mt8188.dtsi                     | 12 ++++++++++++
 2 files changed, 15 insertions(+)
---
base-commit: bdd609656ff5573db9ba1d26496a528bdd297cf2
change-id: 20250515-dtb-check-mt8188-5af50d5d5c93

Best regards,
-- 
Julien Massot <julien.massot at collabora.com>



From julien.massot at collabora.com  Thu May 15 06:31:43 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Thu, 15 May 2025 15:31:43 +0200
Subject: [PATCH 1/3] dt-bindings: clock: mediatek: Add #reset-cells
 property for MT8188
In-Reply-To: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>
References: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>
Message-ID: <20250515-dtb-check-mt8188-v1-1-cda383cbeb4f@collabora.com>

The '#reset-cells' property is required for some of the MT8188
clock controllers, but not listed as a valid property.

Fixes: 9a5cd59640ac ("dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188")
Signed-off-by: Julien Massot <julien.massot at collabora.com>
---
 Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
index 2985c8c717d72888dd49f1f6249a9e2594d8a38d..5403242545ab12a7736ed4fbac26008aa955c724 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
@@ -52,6 +52,9 @@ properties:
   '#clock-cells':
     const: 1
 
+  '#reset-cells':
+    const: 1
+
 required:
   - compatible
   - reg

-- 
2.49.0



From julien.massot at collabora.com  Thu May 15 06:31:44 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Thu, 15 May 2025 15:31:44 +0200
Subject: [PATCH 2/3] arm64: dts: mediatek: mt8188: Add missing #reset-cells
 property
In-Reply-To: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>
References: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>
Message-ID: <20250515-dtb-check-mt8188-v1-2-cda383cbeb4f@collabora.com>

The binding now require the '#reset-cells' property but the
devicetree has not been updated which trigger dtb-check errors.

Fixes: 9a5cd59640ac ("dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188")
Signed-off-by: Julien Massot <julien.massot at collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 296090fbaf4953db8075f72073509b731dc41e51..dec6ce3e94e92c8e1e2c3680cb3584394d9058bd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -2647,36 +2647,42 @@ imgsys1_dip_top: clock-controller at 15110000 {
 			compatible = "mediatek,mt8188-imgsys1-dip-top";
 			reg = <0 0x15110000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		imgsys1_dip_nr: clock-controller at 15130000 {
 			compatible = "mediatek,mt8188-imgsys1-dip-nr";
 			reg = <0 0x15130000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		imgsys_wpe1: clock-controller at 15220000 {
 			compatible = "mediatek,mt8188-imgsys-wpe1";
 			reg = <0 0x15220000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		ipesys: clock-controller at 15330000 {
 			compatible = "mediatek,mt8188-ipesys";
 			reg = <0 0x15330000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		imgsys_wpe2: clock-controller at 15520000 {
 			compatible = "mediatek,mt8188-imgsys-wpe2";
 			reg = <0 0x15520000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		imgsys_wpe3: clock-controller at 15620000 {
 			compatible = "mediatek,mt8188-imgsys-wpe3";
 			reg = <0 0x15620000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		camsys: clock-controller at 16000000 {
@@ -2689,24 +2695,28 @@ camsys_rawa: clock-controller at 1604f000 {
 			compatible = "mediatek,mt8188-camsys-rawa";
 			reg = <0 0x1604f000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		camsys_yuva: clock-controller at 1606f000 {
 			compatible = "mediatek,mt8188-camsys-yuva";
 			reg = <0 0x1606f000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		camsys_rawb: clock-controller at 1608f000 {
 			compatible = "mediatek,mt8188-camsys-rawb";
 			reg = <0 0x1608f000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		camsys_yuvb: clock-controller at 160af000 {
 			compatible = "mediatek,mt8188-camsys-yuvb";
 			reg = <0 0x160af000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		ccusys: clock-controller at 17200000 {

-- 
2.49.0



From julien.massot at collabora.com  Thu May 15 06:31:45 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Thu, 15 May 2025 15:31:45 +0200
Subject: [PATCH 3/3] arm64: dts: mediatek: mt8188: gce: add missing
 'clock-names'
In-Reply-To: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>
References: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>
Message-ID: <20250515-dtb-check-mt8188-v1-3-cda383cbeb4f@collabora.com>

The 'clock-names' property is required by the dt binding.

Fix the following dtb-check error:
arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dtb: mailbox at 10320000: 'clock-names' is a required property
from schema $id: http://devicetree.org/schemas/mailbox/mediatek,gce-mailbox.yaml#

Fixes: 45682a4fffdd ("arm64: dts: mediatek: mt8188: Add Global Command Engine mailboxes")
Signed-off-by: Julien Massot <julien.massot at collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index dec6ce3e94e92c8e1e2c3680cb3584394d9058bd..d5892ca35bc29f830d7894ba592aca3f58dc3bdc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1372,6 +1372,7 @@ gce0: mailbox at 10320000 {
 			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
 			#mbox-cells = <2>;
 			clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
+			clock-names = "gce";
 		};
 
 		gce1: mailbox at 10330000 {
@@ -1380,6 +1381,7 @@ gce1: mailbox at 10330000 {
 			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
 			#mbox-cells = <2>;
 			clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
+			clock-names = "gce";
 		};
 
 		scp_cluster: scp at 10720000 {

-- 
2.49.0



From broonie at kernel.org  Thu May 15 07:24:29 2025
From: broonie at kernel.org (Mark Brown)
Date: Thu, 15 May 2025 16:24:29 +0200
Subject: [PATCH 0/3] ASoC: mediatek: mt8183-afe-pcm: Shorten source
 code
In-Reply-To: <20250425082551.1467042-1-wenst@chromium.org>
References: <20250425082551.1467042-1-wenst@chromium.org>
Message-ID: <174731906955.355366.5967151829535099714.b4-ty@kernel.org>

On Fri, 25 Apr 2025 16:25:47 +0800, Chen-Yu Tsai wrote:
> This series is meant as an example on how to use macros and range cases
> to shorten the MediaTek audio frontend drivers. The drivers have large
> tables describing the registers and register fields for every supported
> audio DMA interface. (Some are actually skipped!) There's a lot of
> duplication which can be eliminated using macros. This should serve as
> a reference for the MT8196 AFE driver that I had commented on.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[1/3] ASoC: mediatek: mt8183-afe-pcm: Shorten memif_data table using macros
      commit: 91c2685430f217ae8f2866e4372948eaf123b5c4
[2/3] ASoC: mediatek: mt8183-afe-pcm: Shorten irq_data table using macros
      commit: 0be889823f93429dab396cb7ac061d02046bd962
[3/3] ASoC: mediatek: mt8183-afe-pcm: shorten mt8183_is_volatile_reg()
      commit: 29552dcc044a233be84ab9b64539fdc7d8f4314e

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark



From broonie at kernel.org  Thu May 15 07:24:33 2025
From: broonie at kernel.org (Mark Brown)
Date: Thu, 15 May 2025 16:24:33 +0200
Subject: [PATCH v2 0/3] ASoC: mediatek: mt8183-afe-pcm: Shorten source
 code
In-Reply-To: <20250515073825.4155297-1-wenst@chromium.org>
References: <20250515073825.4155297-1-wenst@chromium.org>
Message-ID: <174731907367.355366.17373014449076976140.b4-ty@kernel.org>

On Thu, 15 May 2025 15:38:20 +0800, Chen-Yu Tsai wrote:
> Changes since v1:
> - Rebased on top of -next, dropping changes that cover the DMA address
>   MSB registers
> 
> This series is meant as an example on how to use macros and range cases
> to shorten the MediaTek audio frontend drivers. The drivers have large
> tables describing the registers and register fields for every supported
> audio DMA interface. (Some are actually skipped!) There's a lot of
> duplication which can be eliminated using macros. This should serve as
> a reference for the MT8196 AFE driver that I had commented on.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[1/3] ASoC: mediatek: mt8183-afe-pcm: Shorten memif_data table using macros
      commit: 91c2685430f217ae8f2866e4372948eaf123b5c4
[2/3] ASoC: mediatek: mt8183-afe-pcm: Shorten irq_data table using macros
      commit: 0be889823f93429dab396cb7ac061d02046bd962
[3/3] ASoC: mediatek: mt8183-afe-pcm: shorten mt8183_is_volatile_reg()
      commit: 29552dcc044a233be84ab9b64539fdc7d8f4314e

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark



From angelogioacchino.delregno at collabora.com  Thu May 15 07:52:27 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Thu, 15 May 2025 16:52:27 +0200
Subject: [PATCH 3/3] arm64: dts: mediatek: mt8188: gce: add missing
 'clock-names'
In-Reply-To: <20250515-dtb-check-mt8188-v1-3-cda383cbeb4f@collabora.com>
References: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>
 <20250515-dtb-check-mt8188-v1-3-cda383cbeb4f@collabora.com>
Message-ID: <89234201-9315-41f5-ab13-68272f62c53d@collabora.com>

Il 15/05/25 15:31, Julien Massot ha scritto:
> The 'clock-names' property is required by the dt binding.
> 

I just remembered something....


...care to respin this patch instead?
https://lore.kernel.org/all/20240911104327.123602-1-angelogioacchino.delregno at collabora.com/

Cheers,
Angelo




From angelogioacchino.delregno at collabora.com  Thu May 15 07:52:44 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Thu, 15 May 2025 16:52:44 +0200
Subject: [PATCH 1/3] dt-bindings: clock: mediatek: Add #reset-cells
 property for MT8188
In-Reply-To: <20250515-dtb-check-mt8188-v1-1-cda383cbeb4f@collabora.com>
References: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>
 <20250515-dtb-check-mt8188-v1-1-cda383cbeb4f@collabora.com>
Message-ID: <cf86023a-3dd9-4205-9643-89924114e85c@collabora.com>

Il 15/05/25 15:31, Julien Massot ha scritto:
> The '#reset-cells' property is required for some of the MT8188
> clock controllers, but not listed as a valid property.
> 
> Fixes: 9a5cd59640ac ("dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188")
> Signed-off-by: Julien Massot <julien.massot at collabora.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>




From angelogioacchino.delregno at collabora.com  Thu May 15 07:53:24 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Thu, 15 May 2025 16:53:24 +0200
Subject: [PATCH 2/3] arm64: dts: mediatek: mt8188: Add missing
 #reset-cells property
In-Reply-To: <20250515-dtb-check-mt8188-v1-2-cda383cbeb4f@collabora.com>
References: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>
 <20250515-dtb-check-mt8188-v1-2-cda383cbeb4f@collabora.com>
Message-ID: <b693991a-db50-4871-91a4-20d9859a2f43@collabora.com>

Il 15/05/25 15:31, Julien Massot ha scritto:
> The binding now require the '#reset-cells' property but the
> devicetree has not been updated which trigger dtb-check errors.
> 
> Fixes: 9a5cd59640ac ("dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188")

That's not really a fix though, so after you drop the Fixes tag.....

> Signed-off-by: Julien Massot <julien.massot at collabora.com>

....you can get my:

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>




From conor at kernel.org  Thu May 15 08:03:18 2025
From: conor at kernel.org (Conor Dooley)
Date: Thu, 15 May 2025 16:03:18 +0100
Subject: [PATCH 1/3] dt-bindings: clock: mediatek: Add #reset-cells
 property for MT8188
In-Reply-To: <20250515-dtb-check-mt8188-v1-1-cda383cbeb4f@collabora.com>
References: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>
 <20250515-dtb-check-mt8188-v1-1-cda383cbeb4f@collabora.com>
Message-ID: <20250515-playpen-dislodge-80245fb8b7a9@spud>

On Thu, May 15, 2025 at 03:31:43PM +0200, Julien Massot wrote:
> The '#reset-cells' property is required for some of the MT8188
> clock controllers, but not listed as a valid property.

"required for some" but not marked required on those platforms.
Why not?

> 
> Fixes: 9a5cd59640ac ("dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188")
> Signed-off-by: Julien Massot <julien.massot at collabora.com>
> ---
>  Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
> index 2985c8c717d72888dd49f1f6249a9e2594d8a38d..5403242545ab12a7736ed4fbac26008aa955c724 100644
> --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
> @@ -52,6 +52,9 @@ properties:
>    '#clock-cells':
>      const: 1
>  
> +  '#reset-cells':
> +    const: 1
> +
>  required:
>    - compatible
>    - reg
> 
> -- 
> 2.49.0
> 
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From angelogioacchino.delregno at collabora.com  Thu May 15 08:11:13 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Thu, 15 May 2025 17:11:13 +0200
Subject: [PATCH 1/3] dt-bindings: clock: mediatek: Add #reset-cells
 property for MT8188
In-Reply-To: <20250515-playpen-dislodge-80245fb8b7a9@spud>
References: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>
 <20250515-dtb-check-mt8188-v1-1-cda383cbeb4f@collabora.com>
 <20250515-playpen-dislodge-80245fb8b7a9@spud>
Message-ID: <cbd170a3-cbfe-4b4f-a059-efe33fed0e5d@collabora.com>

Il 15/05/25 17:03, Conor Dooley ha scritto:
> On Thu, May 15, 2025 at 03:31:43PM +0200, Julien Massot wrote:
>> The '#reset-cells' property is required for some of the MT8188
>> clock controllers, but not listed as a valid property.
> 
> "required for some" but not marked required on those platforms.
> Why not?
> 

Yeah now that I read that for the third time, the wording is a bit incorrect.

It's not "required", some clock controllers do have reset controllers, but it
is facultative to actually use the latter.

I'm not sure if the ones that do have reset controllers inside should have the
#reset-cells property as required...

Conor, what do you think?

Cheers,
Angelo

>>
>> Fixes: 9a5cd59640ac ("dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188")
>> Signed-off-by: Julien Massot <julien.massot at collabora.com>
>> ---
>>   Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
>> index 2985c8c717d72888dd49f1f6249a9e2594d8a38d..5403242545ab12a7736ed4fbac26008aa955c724 100644
>> --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
>> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
>> @@ -52,6 +52,9 @@ properties:
>>     '#clock-cells':
>>       const: 1
>>   
>> +  '#reset-cells':
>> +    const: 1
>> +
>>   required:
>>     - compatible
>>     - reg
>>
>> -- 
>> 2.49.0
>>



From conor at kernel.org  Thu May 15 09:17:11 2025
From: conor at kernel.org (Conor Dooley)
Date: Thu, 15 May 2025 17:17:11 +0100
Subject: [PATCH 1/3] dt-bindings: clock: mediatek: Add #reset-cells
 property for MT8188
In-Reply-To: <cbd170a3-cbfe-4b4f-a059-efe33fed0e5d@collabora.com>
References: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>
 <20250515-dtb-check-mt8188-v1-1-cda383cbeb4f@collabora.com>
 <20250515-playpen-dislodge-80245fb8b7a9@spud>
 <cbd170a3-cbfe-4b4f-a059-efe33fed0e5d@collabora.com>
Message-ID: <20250515-deploy-wiring-5829acc3d82e@spud>

On Thu, May 15, 2025 at 05:11:13PM +0200, AngeloGioacchino Del Regno wrote:
> Il 15/05/25 17:03, Conor Dooley ha scritto:
> > On Thu, May 15, 2025 at 03:31:43PM +0200, Julien Massot wrote:
> > > The '#reset-cells' property is required for some of the MT8188
> > > clock controllers, but not listed as a valid property.
> > 
> > "required for some" but not marked required on those platforms.
> > Why not?
> > 
> 
> Yeah now that I read that for the third time, the wording is a bit incorrect.
> 
> It's not "required", some clock controllers do have reset controllers, but it
> is facultative to actually use the latter.

I don't think I've ever seen this word before.

> I'm not sure if the ones that do have reset controllers inside should have the
> #reset-cells property as required...
> 
> Conor, what do you think?

If "required for some" in the OP was meant as "permitted for some",
change the wording to that and it is fine.
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From will at kernel.org  Thu May 15 09:33:07 2025
From: will at kernel.org (Will Deacon)
Date: Thu, 15 May 2025 17:33:07 +0100
Subject: [PATCH 0/7] Remove ops.pgsize_bitmap
In-Reply-To: <0-v1-7c5282b0c334+2db-iommu_rm_ops_pgsize_jgg@nvidia.com>
References: <0-v1-7c5282b0c334+2db-iommu_rm_ops_pgsize_jgg@nvidia.com>
Message-ID: <20250515163307.GA12396@willie-the-truck>

On Tue, Apr 29, 2025 at 11:34:10AM -0300, Jason Gunthorpe wrote:
> Now that all drivers are using domain_alloc_paging() and dev is never
> NULL, we can have all drivers correctly set domain.pgsize_bitmap during
> their allocation function.
> 
> There are a few oddities that have accumulated here over past changes:
> 
>  - Some drivers always set domain.pgsize_bitmap during their
>    domain_alloc_paging() call but still provide a value in ops. This is dead
>    code, delete it.
> 
>  - Some drivers calculate a system global pgsize_bitmap in the ops, but
>    it is now trivial to use the per-instance value instead. In several
>    cases this is dead code, delete it. This also allows
>    constifying the ops in these drivers as a hardening measure
> 
>  - Some drivers have a fixed pgsize_bitmap, put it next to setting up the
>    geometry in their domain_alloc_paging() functions.
> 
>  - Finally a few drivers still use ops because they have a delayed
>    finalize operation. Set the constant pgsize_bitmap in the
>    domain_alloc_paging().
> 
> Then remove ops.pgsize_bitmap.
> 
> This is based on iommu next, and must go after the virtio
> domain_alloc_paging() conversion.
> 
> Jason Gunthorpe (7):
>   iommu/arm-smmu-v3: Remove iommu_ops pgsize_bitmap
>   iommu/arm-smmu: Remove iommu_ops pgsize_bitmap

These two SMMU changes look correct to me:

Acked-by: Will Deacon <will at kernel.org>

Please yell if you'd like me to pick them up separately from the rest
of the series.

Will


From christophe.jaillet at wanadoo.fr  Thu May 15 12:59:35 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Thu, 15 May 2025 21:59:35 +0200
Subject: [PATCH v3 1/4] net: airoha: Fix an error handling path in airoha_alloc_gdm_port()
Message-ID: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>

If register_netdev() fails, the error handling path of the probe will not
free the memory allocated by the previous airoha_metadata_dst_alloc() call
because port->dev->reg_state will not be NETREG_REGISTERED.

So, an explicit airoha_metadata_dst_free() call is needed in this case to
avoid a memory leak.

Fixes: af3cf757d5c9 ("net: airoha: Move DSA tag in DMA descriptor")
Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
---
Changes in v3:
  - None

Changes in v2:
  - New patch
v2: https://lore.kernel.org/all/5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet at wanadoo.fr/

Compile tested only.
---
 drivers/net/ethernet/airoha/airoha_eth.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 16c7896f931f..af8c4015938c 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2873,7 +2873,15 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
 	if (err)
 		return err;
 
-	return register_netdev(dev);
+	err = register_netdev(dev);
+	if (err)
+		goto free_metadata_dst;
+
+	return 0;
+
+free_metadata_dst:
+	airoha_metadata_dst_free(port);
+	return err;
 }
 
 static int airoha_probe(struct platform_device *pdev)
-- 
2.49.0



From christophe.jaillet at wanadoo.fr  Thu May 15 12:59:36 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Thu, 15 May 2025 21:59:36 +0200
Subject: [PATCH v3 2/4] net: airoha: Fix an error handling path in airoha_probe()
In-Reply-To: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <47910951a3fa3c3bd2a942210e821d9301362128.1746715755.git.christophe.jaillet@wanadoo.fr>

If an error occurs after a successful airoha_hw_init() call,
airoha_ppe_deinit() needs to be called as already done in the remove
function.

Fixes: 00a7678310fe ("net: airoha: Introduce flowtable offload support")
Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
---
Changes in v3:
  - call airoha_ppe_deinit() and not airoha_ppe_init()   [Lorenzo Bianconi]

Changes in v2:
  - Call airoha_ppe_init() at the right place in the error handling path
    of the probe   [Lorenzo Bianconi]
v2: https://lore.kernel.org/all/3791c95da3fa3c3bd2a942210e821d9301362128.1746715755.git.christophe.jaillet at wanadoo.fr/

v1: https://lore.kernel.org/all/f4a420f3a8b4a6fe72798f9774ec9aff2291522d.1744977434.git.christophe.jaillet at wanadoo.fr/

Compile tested only.
---
 drivers/net/ethernet/airoha/airoha_eth.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index af8c4015938c..d435179875df 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2967,6 +2967,7 @@ static int airoha_probe(struct platform_device *pdev)
 error_napi_stop:
 	for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
 		airoha_qdma_stop_napi(&eth->qdma[i]);
+	airoha_ppe_deinit(eth);
 error_hw_cleanup:
 	for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
 		airoha_hw_cleanup(&eth->qdma[i]);
-- 
2.49.0



From christophe.jaillet at wanadoo.fr  Thu May 15 12:59:37 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Thu, 15 May 2025 21:59:37 +0200
Subject: [PATCH v3 3/4] net: airoha: Use for_each_child_of_node_scoped()
In-Reply-To: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <38143a6af2fb32046c92b5ba81d8e08c55426ebe.1746715755.git.christophe.jaillet@wanadoo.fr>

Use for_each_child_of_node_scoped() to slightly simplify the code.

Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
---
Changes in v3:
  - None

Changes in v2:
  - New patch
v2: https://lore.kernel.org/all/88143d6af26b32066c92b5ba81d8e08c55426ebe.1746715755.git.christophe.jaillet at wanadoo.fr/

Compile tested only.
---
 drivers/net/ethernet/airoha/airoha_eth.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index d435179875df..2335aa59b06f 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2886,7 +2886,6 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
 
 static int airoha_probe(struct platform_device *pdev)
 {
-	struct device_node *np;
 	struct airoha_eth *eth;
 	int i, err;
 
@@ -2948,7 +2947,7 @@ static int airoha_probe(struct platform_device *pdev)
 		airoha_qdma_start_napi(&eth->qdma[i]);
 
 	i = 0;
-	for_each_child_of_node(pdev->dev.of_node, np) {
+	for_each_child_of_node_scoped(pdev->dev.of_node, np) {
 		if (!of_device_is_compatible(np, "airoha,eth-mac"))
 			continue;
 
@@ -2956,10 +2955,8 @@ static int airoha_probe(struct platform_device *pdev)
 			continue;
 
 		err = airoha_alloc_gdm_port(eth, np, i++);
-		if (err) {
-			of_node_put(np);
+		if (err)
 			goto error_napi_stop;
-		}
 	}
 
 	return 0;
-- 
2.49.0



From christophe.jaillet at wanadoo.fr  Thu May 15 12:59:38 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Thu, 15 May 2025 21:59:38 +0200
Subject: [PATCH v3 4/4] net: airoha: Use dev_err_probe()
In-Reply-To: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <bb64aa1ea0205329c377ad32dde46cdf5c232db9.1746715755.git.christophe.jaillet@wanadoo.fr>

Use dev_err_probe() to slightly simplify the code.
It is less verbose, more informational and makes error logging more
consistent in the probe.

Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
---
Changes in v3:
  - None

Changes in v2:
  - New patch
v2: https://lore.kernel.org/all/1b67aa9ea0245325c3779d32dde46cdf5c232db9.1746715755.git.christophe.jaillet at wanadoo.fr/

Compile tested only.
---
 drivers/net/ethernet/airoha/airoha_eth.c | 21 +++++++++------------
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 2335aa59b06f..7404ee894467 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2896,10 +2896,9 @@ static int airoha_probe(struct platform_device *pdev)
 	eth->dev = &pdev->dev;
 
 	err = dma_set_mask_and_coherent(eth->dev, DMA_BIT_MASK(32));
-	if (err) {
-		dev_err(eth->dev, "failed configuring DMA mask\n");
-		return err;
-	}
+	if (err)
+		return dev_err_probe(eth->dev, err,
+				     "failed configuring DMA mask\n");
 
 	eth->fe_regs = devm_platform_ioremap_resource_byname(pdev, "fe");
 	if (IS_ERR(eth->fe_regs))
@@ -2912,10 +2911,9 @@ static int airoha_probe(struct platform_device *pdev)
 	err = devm_reset_control_bulk_get_exclusive(eth->dev,
 						    ARRAY_SIZE(eth->rsts),
 						    eth->rsts);
-	if (err) {
-		dev_err(eth->dev, "failed to get bulk reset lines\n");
-		return err;
-	}
+	if (err)
+		return dev_err_probe(eth->dev, err,
+				     "failed to get bulk reset lines\n");
 
 	eth->xsi_rsts[0].id = "xsi-mac";
 	eth->xsi_rsts[1].id = "hsi0-mac";
@@ -2925,10 +2923,9 @@ static int airoha_probe(struct platform_device *pdev)
 	err = devm_reset_control_bulk_get_exclusive(eth->dev,
 						    ARRAY_SIZE(eth->xsi_rsts),
 						    eth->xsi_rsts);
-	if (err) {
-		dev_err(eth->dev, "failed to get bulk xsi reset lines\n");
-		return err;
-	}
+	if (err)
+		return dev_err_probe(eth->dev, err,
+				     "failed to get bulk xsi reset lines\n");
 
 	eth->napi_dev = alloc_netdev_dummy(0);
 	if (!eth->napi_dev)
-- 
2.49.0



From lorenzo at kernel.org  Thu May 15 14:16:56 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Thu, 15 May 2025 23:16:56 +0200
Subject: [PATCH v3 1/4] net: airoha: Fix an error handling path in
 airoha_alloc_gdm_port()
In-Reply-To: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <aCZZyDvp-TZ7AFwS@lore-desk>

> If register_netdev() fails, the error handling path of the probe will not
> free the memory allocated by the previous airoha_metadata_dst_alloc() call
> because port->dev->reg_state will not be NETREG_REGISTERED.
> 
> So, an explicit airoha_metadata_dst_free() call is needed in this case to
> avoid a memory leak.
> 
> Fixes: af3cf757d5c9 ("net: airoha: Move DSA tag in DMA descriptor")
> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>

Acked-by: Lorenzo Bianconi <lorenzo at kernel.org>

> ---
> Changes in v3:
>   - None
> 
> Changes in v2:
>   - New patch
> v2: https://lore.kernel.org/all/5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet at wanadoo.fr/
> 
> Compile tested only.
> ---
>  drivers/net/ethernet/airoha/airoha_eth.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index 16c7896f931f..af8c4015938c 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -2873,7 +2873,15 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
>  	if (err)
>  		return err;
>  
> -	return register_netdev(dev);
> +	err = register_netdev(dev);
> +	if (err)
> +		goto free_metadata_dst;
> +
> +	return 0;
> +
> +free_metadata_dst:
> +	airoha_metadata_dst_free(port);
> +	return err;
>  }
>  
>  static int airoha_probe(struct platform_device *pdev)
> -- 
> 2.49.0
> 
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From kuba at kernel.org  Thu May 15 17:52:51 2025
From: kuba at kernel.org (Jakub Kicinski)
Date: Thu, 15 May 2025 17:52:51 -0700
Subject: [net v1] net: wwan: t7xx: Fix napi rx poll issue
In-Reply-To: <20250515031743.246178-1-jinjian.song@fibocom.com>
References: <20250515031743.246178-1-jinjian.song@fibocom.com>
Message-ID: <20250515175251.58b5123f@kernel.org>

On Thu, 15 May 2025 11:17:42 +0800 Jinjian Song wrote:
> diff --git a/drivers/net/wwan/t7xx/t7xx_netdev.c b/drivers/net/wwan/t7xx/t7xx_netdev.c
> index 91fa082e9cab..2116ff81728b 100644
> --- a/drivers/net/wwan/t7xx/t7xx_netdev.c
> +++ b/drivers/net/wwan/t7xx/t7xx_netdev.c
> @@ -324,6 +324,7 @@ static void t7xx_ccmni_wwan_dellink(void *ctxt, struct net_device *dev, struct l
>  	if (WARN_ON(ctlb->ccmni_inst[if_id] != ccmni))
>  		return;
>  
> +	ctlb->ccmni_inst[if_id] = NULL;
>  	unregister_netdevice(dev);

I don't see any synchronization between this write and NAPI processing.
Is this safe? NAPI can be at any point of processing as we set the ptr
to NULL
-- 
pw-bot: cr


From kuba at kernel.org  Thu May 15 18:08:58 2025
From: kuba at kernel.org (Jakub Kicinski)
Date: Thu, 15 May 2025 18:08:58 -0700
Subject: [net-next v1] net: wwan: t7xx: Parameterize data plane RX BAT
 and FAG count
In-Reply-To: <20250514104728.10869-1-jinjian.song@fibocom.com>
References: <20250514104728.10869-1-jinjian.song@fibocom.com>
Message-ID: <20250515180858.2568d930@kernel.org>

On Wed, 14 May 2025 18:47:28 +0800 Jinjian Song wrote:
> The DMA buffer for data plane RX is currently fixed, being parameterized
> to allow configuration.

Module parameters are discouraged, they are pretty poor as an API since
they apply to all devices in the system. Can you describe what "frg"
and "bat" are ? One of the existing APIs likely covers them.
Please also describe the scope (are they per netdev or some sort of
device level params)?
-- 
pw-bot: cr


From kuba at kernel.org  Thu May 15 18:13:57 2025
From: kuba at kernel.org (Jakub Kicinski)
Date: Thu, 15 May 2025 18:13:57 -0700
Subject: [PATCH net-next 2/2] net: airoha: Add FLOW_CLS_STATS callback
 support
In-Reply-To: <20250514-airoha-en7581-flowstats-v1-2-c00ede12a2ca@kernel.org>
References: <20250514-airoha-en7581-flowstats-v1-0-c00ede12a2ca@kernel.org>
	<20250514-airoha-en7581-flowstats-v1-2-c00ede12a2ca@kernel.org>
Message-ID: <20250515181357.73f98a18@kernel.org>

On Wed, 14 May 2025 19:09:58 +0200 Lorenzo Bianconi wrote:
> Introduce per-flow stats accounting to the flowtable hw offload in
> the airoha_eth driver. Flow stats are split in the PPE and NPU modules:
> - PPE: accounts for high 32bit of per-flow stats
> - NPU: accounts for low 32bit of per-flow stats
> 
> FLOW_CLS_STATS can be enabled or disabled at compile time.

sparse isn't happy:

drivers/net/ethernet/airoha/airoha_npu.c:382:15: warning: incorrect type in assignment (different address spaces)
drivers/net/ethernet/airoha/airoha_npu.c:382:15:    expected void *stats
drivers/net/ethernet/airoha/airoha_npu.c:382:15:    got void [noderef] __iomem *
-- 
pw-bot: cr


From nico at fluxnic.net  Thu May 15 20:34:49 2025
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 15 May 2025 23:34:49 -0400 (EDT)
Subject: [PATCH] dts: arm64: mediatek: thermal adjustments for MT8186,
 MT8188 and MT8195
In-Reply-To: <prp38558-r53s-756p-o6n8-795o7q87sssr@onlyvoer.pbz>
References: <prp38558-r53s-756p-o6n8-795o7q87sssr@onlyvoer.pbz>
Message-ID: <590n1r09-s4pp-0nnq-1oo6-20sos6os63op@syhkavp.arg>

Gentle ping.

On Fri, 18 Apr 2025, Nicolas Pitre wrote:

> Adjust temperature threshold values. Provide the "switch on" thermal 
> trip point to be used by the power allocator governor.
> 
> All numbers were provided by Mediatek.
> 
> Signed-off-by: Nicolas Pitre <npitre at baylibre.com>
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index b91f88ffae..bfea811491 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -2229,22 +2229,23 @@ cpu-little0-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <150>;
>  			thermal-sensors = <&lvts MT8186_LITTLE_CPU0>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> -				cpu_little0_alert0: trip-alert0 {
> -					temperature = <85000>;
> +				cpu_little0_pa_switch_on: trip_pa_switch_on {
> +					temperature = <58000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
> -				cpu_little0_alert1: trip-alert1 {
> -					temperature = <95000>;
> +				cpu_little0_alert0: trip-alert {
> +					temperature = <82000>;
>  					hysteresis = <2000>;
> -					type = "hot";
> +					type = "passive";
>  				};
>  
>  				cpu_little0_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <103000>;
>  					hysteresis = <0>;
>  					type = "critical";
>  				};
> @@ -2267,22 +2268,23 @@ cpu-little1-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <150>;
>  			thermal-sensors = <&lvts MT8186_LITTLE_CPU1>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> -				cpu_little1_alert0: trip-alert0 {
> -					temperature = <85000>;
> +				cpu_little1_pa_switch_on: trip_pa_switch_on {
> +					temperature = <58000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
> -				cpu_little1_alert1: trip-alert1 {
> -					temperature = <95000>;
> +				cpu_little1_alert0: trip-alert {
> +					temperature = <82000>;
>  					hysteresis = <2000>;
> -					type = "hot";
> +					type = "passive";
>  				};
>  
>  				cpu_little1_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <103000>;
>  					hysteresis = <0>;
>  					type = "critical";
>  				};
> @@ -2305,22 +2307,23 @@ cpu-little2-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <150>;
>  			thermal-sensors = <&lvts MT8186_LITTLE_CPU2>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> -				cpu_little2_alert0: trip-alert0 {
> -					temperature = <85000>;
> +				cpu_little2_pa_switch_on: trip_pa_switch_on {
> +					temperature = <58000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
> -				cpu_little2_alert1: trip-alert1 {
> -					temperature = <95000>;
> +				cpu_little2_alert0: trip-alert {
> +					temperature = <82000>;
>  					hysteresis = <2000>;
> -					type = "hot";
> +					type = "passive";
>  				};
>  
>  				cpu_little2_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <103000>;
>  					hysteresis = <0>;
>  					type = "critical";
>  				};
> @@ -2454,22 +2457,23 @@ cpu-big0-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <100>;
>  			thermal-sensors = <&lvts MT8186_BIG_CPU0>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> -				cpu_big0_alert0: trip-alert0 {
> -					temperature = <85000>;
> +				cpu_big0_pa_switch_on: trip_pa_switch_on {
> +					temperature = <58000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
> -				cpu_big0_alert1: trip-alert1 {
> -					temperature = <95000>;
> +				cpu_big0_alert0: trip-alert {
> +					temperature = <82000>;
>  					hysteresis = <2000>;
> -					type = "hot";
> +					type = "passive";
>  				};
>  
>  				cpu_big0_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <103000>;
>  					hysteresis = <0>;
>  					type = "critical";
>  				};
> @@ -2488,22 +2492,23 @@ cpu-big1-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <100>;
>  			thermal-sensors = <&lvts MT8186_BIG_CPU1>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> -				cpu_big1_alert0: trip-alert0 {
> -					temperature = <85000>;
> +				cpu_big1_pa_switch_on: trip_pa_switch_on {
> +					temperature = <58000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
> -				cpu_big1_alert1: trip-alert1 {
> -					temperature = <95000>;
> +				cpu_big1_alert0: trip-alert {
> +					temperature = <82000>;
>  					hysteresis = <2000>;
> -					type = "hot";
> +					type = "passive";
>  				};
>  
>  				cpu_big1_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <103000>;
>  					hysteresis = <0>;
>  					type = "critical";
>  				};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> index 69a8423d38..c2ac47c77c 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> @@ -472,22 +472,23 @@ cpu-little0-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <150>;
>  			thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU0>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> -				cpu_little0_alert0: trip-alert0 {
> -					temperature = <85000>;
> +				cpu_little0_pa_switch_on: trip-pa-switch_on {
> +					temperature = <68000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
> -				cpu_little0_alert1: trip-alert1 {
> -					temperature = <95000>;
> +				cpu_little0_alert0: trip-alert {
> +					temperature = <85000>;
>  					hysteresis = <2000>;
> -					type = "hot";
> +					type = "passive";
>  				};
>  
>  				cpu_little0_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <115000>;
>  					hysteresis = <0>;
>  					type = "critical";
>  				};
> @@ -510,22 +511,23 @@ cpu-little1-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <150>;
>  			thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU1>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> -				cpu_little1_alert0: trip-alert0 {
> -					temperature = <85000>;
> +				cpu_little1_pa_switch_on: trip-pa-switch_on {
> +					temperature = <68000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
> -				cpu_little1_alert1: trip-alert1 {
> -					temperature = <95000>;
> +				cpu_little1_alert0: trip-alert {
> +					temperature = <85000>;
>  					hysteresis = <2000>;
> -					type = "hot";
> +					type = "passive";
>  				};
>  
>  				cpu_little1_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <115000>;
>  					hysteresis = <0>;
>  					type = "critical";
>  				};
> @@ -548,22 +550,23 @@ cpu-little2-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <150>;
>  			thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU2>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> -				cpu_little2_alert0: trip-alert0 {
> -					temperature = <85000>;
> +				cpu_little2_pa_switch_on: trip-pa-switch_on {
> +					temperature = <68000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
> -				cpu_little2_alert1: trip-alert1 {
> -					temperature = <95000>;
> +				cpu_little2_alert0: trip-alert {
> +					temperature = <85000>;
>  					hysteresis = <2000>;
> -					type = "hot";
> +					type = "passive";
>  				};
>  
>  				cpu_little2_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <115000>;
>  					hysteresis = <0>;
>  					type = "critical";
>  				};
> @@ -586,22 +589,23 @@ cpu-little3-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <150>;
>  			thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU3>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> -				cpu_little3_alert0: trip-alert0 {
> -					temperature = <85000>;
> +				cpu_little3_pa_switch_on: trip-pa-switch_on {
> +					temperature = <68000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
> -				cpu_little3_alert1: trip-alert1 {
> -					temperature = <95000>;
> +				cpu_little3_alert0: trip-alert {
> +					temperature = <85000>;
>  					hysteresis = <2000>;
> -					type = "hot";
> +					type = "passive";
>  				};
>  
>  				cpu_little3_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <115000>;
>  					hysteresis = <0>;
>  					type = "critical";
>  				};
> @@ -624,22 +628,23 @@ cpu-big0-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <100>;
>  			thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU0>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> -				cpu_big0_alert0: trip-alert0 {
> -					temperature = <85000>;
> +				cpu_big0_pa_switch_on: trip-pa-switch_on {
> +					temperature = <68000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
> -				cpu_big0_alert1: trip-alert1 {
> -					temperature = <95000>;
> +				cpu_big0_alert0: trip-alert {
> +					temperature = <85000>;
>  					hysteresis = <2000>;
> -					type = "hot";
> +					type = "passive";
>  				};
>  
>  				cpu_big0_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <115000>;
>  					hysteresis = <0>;
>  					type = "critical";
>  				};
> @@ -658,22 +663,23 @@ cpu-big1-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <100>;
>  			thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU1>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> -				cpu_big1_alert0: trip-alert0 {
> -					temperature = <85000>;
> +				cpu_big1_pa_switch_on: trip-pa-switch_on {
> +					temperature = <68000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
> -				cpu_big1_alert1: trip-alert1 {
> -					temperature = <95000>;
> +				cpu_big1_alert0: trip-alert {
> +					temperature = <85000>;
>  					hysteresis = <2000>;
> -					type = "hot";
> +					type = "passive";
>  				};
>  
>  				cpu_big1_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <115000>;
>  					hysteresis = <0>;
>  					type = "critical";
>  				};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 4f2dc0a755..06631760c2 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -3729,16 +3729,23 @@ cpu0-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <250>;
>  			thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> +				cpu0_pa_switch_on: trip_pa_switch_on {
> +						temperature = <68000>;
> +						hysteresis = <2000>;
> +						type = "passive";
> +				};
> +
>  				cpu0_alert: trip-alert {
> -					temperature = <85000>;
> +					temperature = <90000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
>  				cpu0_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <115000>;
>  					hysteresis = <2000>;
>  					type = "critical";
>  				};
> @@ -3759,16 +3766,23 @@ cpu1-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <250>;
>  			thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> +				cpu1_pa_switch_on: trip_pa_switch_on {
> +						temperature = <68000>;
> +						hysteresis = <2000>;
> +						type = "passive";
> +				};
> +
>  				cpu1_alert: trip-alert {
> -					temperature = <85000>;
> +					temperature = <90000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
>  				cpu1_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <115000>;
>  					hysteresis = <2000>;
>  					type = "critical";
>  				};
> @@ -3789,16 +3803,23 @@ cpu2-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <250>;
>  			thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> +				cpu2_pa_switch_on: trip_pa_switch_on {
> +						temperature = <68000>;
> +						hysteresis = <2000>;
> +						type = "passive";
> +				};
> +
>  				cpu2_alert: trip-alert {
> -					temperature = <85000>;
> +					temperature = <90000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
>  				cpu2_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <115000>;
>  					hysteresis = <2000>;
>  					type = "critical";
>  				};
> @@ -3819,16 +3840,23 @@ cpu3-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <250>;
>  			thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> +				cpu3_pa_switch_on: trip_pa_switch_on {
> +						temperature = <68000>;
> +						hysteresis = <2000>;
> +						type = "passive";
> +				};
> +
>  				cpu3_alert: trip-alert {
> -					temperature = <85000>;
> +					temperature = <90000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
>  				cpu3_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <115000>;
>  					hysteresis = <2000>;
>  					type = "critical";
>  				};
> @@ -3849,16 +3877,23 @@ cpu4-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <250>;
>  			thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> +				cpu4_pa_switch_on: trip_pa_switch_on {
> +						temperature = <68000>;
> +						hysteresis = <2000>;
> +						type = "passive";
> +				};
> +
>  				cpu4_alert: trip-alert {
> -					temperature = <85000>;
> +					temperature = <90000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
>  				cpu4_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <115000>;
>  					hysteresis = <2000>;
>  					type = "critical";
>  				};
> @@ -3879,16 +3914,23 @@ cpu5-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <250>;
>  			thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> +				cpu5_pa_switch_on: trip_pa_switch_on {
> +						temperature = <68000>;
> +						hysteresis = <2000>;
> +						type = "passive";
> +				};
> +
>  				cpu5_alert: trip-alert {
> -					temperature = <85000>;
> +					temperature = <90000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
>  				cpu5_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <115000>;
>  					hysteresis = <2000>;
>  					type = "critical";
>  				};
> @@ -3909,16 +3951,23 @@ cpu6-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <250>;
>  			thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> +				cpu6_pa_switch_on: trip_pa_switch_on {
> +						temperature = <68000>;
> +						hysteresis = <2000>;
> +						type = "passive";
> +				};
> +
>  				cpu6_alert: trip-alert {
> -					temperature = <85000>;
> +					temperature = <90000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
>  				cpu6_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <115000>;
>  					hysteresis = <2000>;
>  					type = "critical";
>  				};
> @@ -3939,16 +3988,23 @@ cpu7-thermal {
>  			polling-delay = <1000>;
>  			polling-delay-passive = <250>;
>  			thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
> +			sustainable-power = <1500>;
>  
>  			trips {
> +				cpu7_pa_switch_on: trip_pa_switch_on {
> +						temperature = <68000>;
> +						hysteresis = <2000>;
> +						type = "passive";
> +				};
> +
>  				cpu7_alert: trip-alert {
> -					temperature = <85000>;
> +					temperature = <90000>;
>  					hysteresis = <2000>;
>  					type = "passive";
>  				};
>  
>  				cpu7_crit: trip-crit {
> -					temperature = <100000>;
> +					temperature = <115000>;
>  					hysteresis = <2000>;
>  					type = "critical";
>  				};
> 


From jinjian.song at fibocom.com  Thu May 15 20:46:57 2025
From: jinjian.song at fibocom.com (Jinjian Song)
Date: Fri, 16 May 2025 11:46:57 +0800
Subject: [net-next v1] net: wwan: t7xx: Parameterize data plane RX BAT and FAG count
In-Reply-To: <20250515180858.2568d930@kernel.org>
References: <20250514104728.10869-1-jinjian.song@fibocom.com>
Message-ID: <20250515180858.2568d930@kernel.org>

>On Wed, 14 May 2025 18:47:28 +0800 Jinjian Song wrote:
>> The DMA buffer for data plane RX is currently fixed, being parameterized
>> to allow configuration.
>
>Module parameters are discouraged, they are pretty poor as an API since
>they apply to all devices in the system. Can you describe what "frg"
>and "bat" are ? One of the existing APIs likely covers them.
>Please also describe the scope (are they per netdev or some sort of
>device level params)?

MTK t7xx data plane hardware use BAT (Buffer Address Table) and FRG (Fragment) BAT
to describle and manager RX buffer, these buffers will apply for a fixed size after
the driver probe, and accompany the life cycle of the driver.

On some platforms, especially those that use swiotlb to manager buffers, without
changing the buffer pool provided by swiotlb, it's needed to adjust the buffers
used by the driver to meet the requirements.
So parameterize these buffers applicable to the MTK t7xx driver to facilitate
different platforms to work with different configurations. 

These prameters are only used for MTK t7xx driver.

Jinjian,
Best Regards.



From wenst at chromium.org  Thu May 15 22:05:48 2025
From: wenst at chromium.org (Chen-Yu Tsai)
Date: Fri, 16 May 2025 13:05:48 +0800
Subject: [PATCH] ASoC: soc-utils: Check string pointer validity in snd_soc_dlc_is_dummy()
Message-ID: <20250516050549.407133-1-wenst@chromium.org>

In the recently added snd_soc_dlc_is_dummy(), the helper uses the .name
and .dai_name fields without checking their validity.

For .name, this field is NULL if the component is matched by .of_node
instead. In fact, only one of these fields may be set. This caused a
NULL pointer dereference on MediaTek MT8195 and MT8188 platforms with
the subsequent conversion to snd_soc_dlc_is_dummy() in their machine
drivers. The codecs are all matches through the device tree, so their
.name fields are empty.

For .dai_name, there are cases where this field is empty, such as for
the following component definitions:

	#define COMP_EMPTY()                    { }
	#define COMP_PLATFORM(_name)            { .name = _name }
	#define COMP_AUX(_name)                 { .name = _name }
	#define COMP_CODEC_CONF(_name)          { .name = _name }

Or the single link CPU DAI case in the simple audio card family, as
covered by simple_util_canonicalize_cpu(), in which the .dai_name
field is explicitly cleared.

To fix this, check the validity of the fields before using them in
string comparison.

Fixes: 3e021f3b8115 ("ASoC: soc-utils: add snd_soc_dlc_is_dummy()")
Cc: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Chen-Yu Tsai <wenst at chromium.org>
---
 sound/soc/soc-utils.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/soc-utils.c b/sound/soc/soc-utils.c
index a1bcc852a6de..c8adfff826bd 100644
--- a/sound/soc/soc-utils.c
+++ b/sound/soc/soc-utils.c
@@ -267,8 +267,8 @@ int snd_soc_dlc_is_dummy(struct snd_soc_dai_link_component *dlc)
 	if (dlc == &snd_soc_dummy_dlc)
 		return true;
 
-	if (strcmp(dlc->name,	  snd_soc_dummy_dlc.name)	== 0 ||
-	    strcmp(dlc->dai_name, snd_soc_dummy_dlc.dai_name)	== 0)
+	if ((dlc->name     && strcmp(dlc->name,     snd_soc_dummy_dlc.name)     == 0) ||
+	    (dlc->dai_name && strcmp(dlc->dai_name, snd_soc_dummy_dlc.dai_name) == 0))
 		return true;
 
 	return false;
-- 
2.49.0.1101.gccaa498523-goog



From kuninori.morimoto.gx at renesas.com  Thu May 15 22:19:09 2025
From: kuninori.morimoto.gx at renesas.com (Kuninori Morimoto)
Date: Fri, 16 May 2025 05:19:09 +0000
Subject: [PATCH] ASoC: soc-utils: Check string pointer validity in snd_soc_dlc_is_dummy()
In-Reply-To: <20250516050549.407133-1-wenst@chromium.org>
References: <20250516050549.407133-1-wenst@chromium.org>
Message-ID: <87v7q1rv3m.wl-kuninori.morimoto.gx@renesas.com>


Hi Chen-Yu

> In the recently added snd_soc_dlc_is_dummy(), the helper uses the .name
> and .dai_name fields without checking their validity.
> 
> For .name, this field is NULL if the component is matched by .of_node
> instead. In fact, only one of these fields may be set. This caused a
> NULL pointer dereference on MediaTek MT8195 and MT8188 platforms with
> the subsequent conversion to snd_soc_dlc_is_dummy() in their machine
> drivers. The codecs are all matches through the device tree, so their
> .name fields are empty.
> 
> For .dai_name, there are cases where this field is empty, such as for
> the following component definitions:
> 
> 	#define COMP_EMPTY()                    { }
> 	#define COMP_PLATFORM(_name)            { .name = _name }
> 	#define COMP_AUX(_name)                 { .name = _name }
> 	#define COMP_CODEC_CONF(_name)          { .name = _name }
> 
> Or the single link CPU DAI case in the simple audio card family, as
> covered by simple_util_canonicalize_cpu(), in which the .dai_name
> field is explicitly cleared.
> 
> To fix this, check the validity of the fields before using them in
> string comparison.
> 
> Fixes: 3e021f3b8115 ("ASoC: soc-utils: add snd_soc_dlc_is_dummy()")
> Cc: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
> Signed-off-by: Chen-Yu Tsai <wenst at chromium.org>
> ---

Yes, indeed

Acked-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

Thank you for your help !!

Best regards
---
Kuninori Morimoto


From lorenzo at kernel.org  Thu May 15 23:28:57 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Fri, 16 May 2025 08:28:57 +0200
Subject: [PATCH net-next v2 1/2] dt-bindings: net: airoha: Add EN7581
 memory-region property
In-Reply-To: <20250514200816.GA2934563-robh@kernel.org>
References: <20250509-airopha-desc-sram-v2-0-9dc3d8076dfb@kernel.org>
 <20250509-airopha-desc-sram-v2-1-9dc3d8076dfb@kernel.org>
 <20250514200816.GA2934563-robh@kernel.org>
Message-ID: <aCbbKfpsKoDK8cuW@lore-desk>

> On Fri, May 09, 2025 at 04:51:33PM +0200, Lorenzo Bianconi wrote:
> > Introduce the memory-region and memory-region-names properties for the
> > ethernet node available on EN7581 SoC. In order to improve performances,
> > EN7581 SoC supports allocating buffers for hw forwarding queues in SRAM
> > instead of DRAM if available on the system.
> 
> But 'reserved-memory' is generally for system memory which is DRAM 
> though we unfortunately don't enforce that. For small onchip SRAM, you 
> should be using the mmio-sram binding and the 'sram' property.

ack, thx for pointing this out, I will look into it.

Regards,
Lorenzo

> 
> > 
> > Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
> > ---
> >  .../devicetree/bindings/net/airoha,en7581-eth.yaml          | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
> > index 0fdd1126541774acacc783d98e4c089b2d2b85e2..6d22131ac2f9e28390b9e785ce33e8d983eafd0f 100644
> > --- a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
> > +++ b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
> > @@ -57,6 +57,16 @@ properties:
> >        - const: hsi-mac
> >        - const: xfp-mac
> >  
> > +  memory-region:
> > +    items:
> > +      - description: QDMA0 buffer memory
> > +      - description: QDMA1 buffer memory
> > +
> > +  memory-region-names:
> > +    items:
> > +      - const: qdma0-buf
> > +      - const: qdma1-buf
> > +
> >    "#address-cells":
> >      const: 1
> >  
> > @@ -140,6 +150,9 @@ examples:
> >                       <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
> >                       <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> >  
> > +        memory-region = <&qdma0_buf>, <&qdma1_buf>;
> > +        memory-region-names = "qdma0-buf", "qdma1-buf";
> > +
> >          airoha,npu = <&npu>;
> >  
> >          #address-cells = <1>;
> > 
> > -- 
> > 2.49.0
> > 
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From lorenzo at kernel.org  Thu May 15 23:29:28 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Fri, 16 May 2025 08:29:28 +0200
Subject: [PATCH net-next 2/2] net: airoha: Add FLOW_CLS_STATS callback
 support
In-Reply-To: <20250515181357.73f98a18@kernel.org>
References: <20250514-airoha-en7581-flowstats-v1-0-c00ede12a2ca@kernel.org>
 <20250514-airoha-en7581-flowstats-v1-2-c00ede12a2ca@kernel.org>
 <20250515181357.73f98a18@kernel.org>
Message-ID: <aCbbSHkBRrm4yM1f@lore-desk>

On May 15, Jakub Kicinski wrote:
> On Wed, 14 May 2025 19:09:58 +0200 Lorenzo Bianconi wrote:
> > Introduce per-flow stats accounting to the flowtable hw offload in
> > the airoha_eth driver. Flow stats are split in the PPE and NPU modules:
> > - PPE: accounts for high 32bit of per-flow stats
> > - NPU: accounts for low 32bit of per-flow stats
> > 
> > FLOW_CLS_STATS can be enabled or disabled at compile time.
> 
> sparse isn't happy:
> 
> drivers/net/ethernet/airoha/airoha_npu.c:382:15: warning: incorrect type in assignment (different address spaces)
> drivers/net/ethernet/airoha/airoha_npu.c:382:15:    expected void *stats
> drivers/net/ethernet/airoha/airoha_npu.c:382:15:    got void [noderef] __iomem *

ack, I will fix it in v2.

Regards,
Lorenzo

> -- 
> pw-bot: cr
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From lkp at intel.com  Thu May 15 23:34:47 2025
From: lkp at intel.com (kernel test robot)
Date: Fri, 16 May 2025 14:34:47 +0800
Subject: [PATCH v3 15/17] drm/mediatek: add ovlsys_adaptor support for
 MT8196
In-Reply-To: <20250515093454.1729720-16-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-16-paul-pl.chen@mediatek.com>
Message-ID: <202505161422.JeAeW3Pd-lkp@intel.com>

Hi paul-pl.chen,

kernel test robot noticed the following build errors:

[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v6.15-rc6 next-20250515]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/paul-pl-chen/dt-bindings-soc-mediatek-add-mutex-yaml-for-MT8196/20250515-173733
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/20250515093454.1729720-16-paul-pl.chen%40mediatek.com
patch subject: [PATCH v3 15/17] drm/mediatek: add ovlsys_adaptor support for MT8196
config: arm64-randconfig-001-20250516 (https://download.01.org/0day-ci/archive/20250516/202505161422.JeAeW3Pd-lkp at intel.com/config)
compiler: aarch64-linux-gcc (GCC) 9.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250516/202505161422.JeAeW3Pd-lkp at intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505161422.JeAeW3Pd-lkp at intel.com/

All error/warnings (new ones prefixed by >>):

   drivers/gpu/drm/mediatek/mtk_drm_drv.c: In function 'mtk_drm_ovl_adaptor_probe':
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:1071:32: error: storage size of 'ovlsys_priv' isn't known
    1071 |  struct mtk_drm_ovlsys_private ovlsys_priv;
         |                                ^~~~~~~~~~~
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:1071:32: warning: unused variable 'ovlsys_priv' [-Wunused-variable]
   drivers/gpu/drm/mediatek/mtk_drm_drv.c: In function 'mtk_drm_probe':
   drivers/gpu/drm/mediatek/mtk_drm_drv.c:1145:50: error: 'DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2' undeclared (first use in this function); did you mean 'DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0'?
    1145 |  mtk_drm_ovl_adaptor_probe(dev, private, &match, DDP_COMPONENT_DRM_OVLSYS_ADAPTOR2);
         |                                                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
         |                                                  DDP_COMPONENT_DRM_OVLSYS_ADAPTOR0
   drivers/gpu/drm/mediatek/mtk_drm_drv.c:1145:50: note: each undeclared identifier is reported only once for each function it appears in


vim +1071 drivers/gpu/drm/mediatek/mtk_drm_drv.c

  1066	
  1067	static void mtk_drm_ovl_adaptor_probe(struct device *dev, struct mtk_drm_private *private,
  1068					      struct component_match **match, enum mtk_ddp_comp_id id)
  1069	{
  1070		struct platform_device *ovl_adaptor;
> 1071		struct mtk_drm_ovlsys_private ovlsys_priv;
  1072		bool is_ovlsys = (id != DDP_COMPONENT_DRM_OVL_ADAPTOR);
  1073		char *dev_name = is_ovlsys ? "mediatek-disp-ovlsys-adaptor" : "mediatek-disp-ovl-adaptor";
  1074		void *drv_data = is_ovlsys ? (void *)&ovlsys_priv : (void *)private->mmsys_dev;
  1075		size_t data_size = is_ovlsys ? sizeof(ovlsys_priv) : sizeof(*private->mmsys_dev);
  1076	
  1077		if (mtk_drm_find_mmsys_comp(private, id, &ovlsys_priv.use_path)) {
  1078			ovlsys_priv.mmsys_dev = private->mmsys_dev;
  1079			ovl_adaptor = platform_device_register_data(dev, dev_name, PLATFORM_DEVID_AUTO,
  1080								    drv_data, data_size);
  1081			private->ddp_comp[id].dev = &ovl_adaptor->dev;
  1082			mtk_ddp_comp_init(NULL, &private->ddp_comp[id], id);
  1083			component_match_add(dev, match, compare_dev, &ovl_adaptor->dev);
  1084		}
  1085	}
  1086	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki


From xiangzhi.tang at mediatek.com  Thu May 15 23:49:33 2025
From: xiangzhi.tang at mediatek.com (Xiangzhi Tang)
Date: Fri, 16 May 2025 14:49:33 +0800
Subject: [PATCH] mediatek: Add mt8196 VCP firmware
Message-ID: <20250516064950.19175-1-xiangzhi.tang@mediatek.com>

MediaTek's Video Companion Processor(VCP) is an RISC-V
processor in MediaTek MT8196 SoC.
It supports vedio encode/decode, vmm and vdisp feature.

Release version: v1.0.0

Signed-off-by: Xiangzhi Tang <xiangzhi.tang at mediatek.com>
---
 WHENCE                  |   9 +++++++++
 mediatek/mt8196/vcp.img | Bin 0 -> 5756016 bytes
 2 files changed, 9 insertions(+)
 create mode 100755 mediatek/mt8196/vcp.img

diff --git a/WHENCE b/WHENCE
index 29beba1b..57fd0d52 100644
--- a/WHENCE
+++ b/WHENCE
@@ -5926,6 +5926,15 @@ Licence: Redistributable. See LICENCE.mediatek for details.
 
 --------------------------------------------------------------------------
 
+Driver: mt8196 - MediaTek MT8196 Video Controller Processor
+
+File: mediatek/mt8196/vcp.img
+Version: v1.0.0
+
+Licence: Redistributable. See LICENCE.mediatek for details.
+
+--------------------------------------------------------------------------
+
 Driver: mtk_scp - MediaTek SCP System Control Processing Driver
 
 File: mediatek/mt8183/scp.img
diff --git a/mediatek/mt8196/vcp.img b/mediatek/mt8196/vcp.img
new file mode 100755
index 0000000000000000000000000000000000000000..7246d486ebd36f5acb3cb1b77cdec39c49d81364
GIT binary patch
literal 5756016
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z5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*
zAOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}
l0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq68O^y{C{?}YWx5I

literal 0
HcmV?d00001

-- 
2.46.0



From jinjian.song at fibocom.com  Fri May 16 00:30:38 2025
From: jinjian.song at fibocom.com (Jinjian Song)
Date: Fri, 16 May 2025 15:30:38 +0800
Subject: [net v1] net: wwan: t7xx: Fix napi rx poll issue
In-Reply-To: <20250515031743.246178-1-jinjian.song@fibocom.com>
References: <20250515031743.246178-1-jinjian.song@fibocom.com>
Message-ID: <20250515175251.58b5123f@kernel.org>

>On Thu, 15 May 2025 11:17:42 +0800 Jinjian Song wrote:
>> diff --git a/drivers/net/wwan/t7xx/t7xx_netdev.c b/drivers/net/wwan/t7xx/t7xx_netdev.c
>> index 91fa082e9cab..2116ff81728b 100644
>> --- a/drivers/net/wwan/t7xx/t7xx_netdev.c
>> +++ b/drivers/net/wwan/t7xx/t7xx_netdev.c
>> @@ -324,6 +324,7 @@ static void t7xx_ccmni_wwan_dellink(void *ctxt, struct net_device *dev, struct l
>>  	if (WARN_ON(ctlb->ccmni_inst[if_id] != ccmni))
>>  		return;
>>  
>> +	ctlb->ccmni_inst[if_id] = NULL;
>>  	unregister_netdevice(dev);
>
>I don't see any synchronization between this write and NAPI processing.
>Is this safe? NAPI can be at any point of processing as we set the ptr
>to NULL

This panic occured in the scenario where there are frequent disconnect
and connect WWAN cellular on UI.
I debug the panic with gdb and found it as caused by an invalid net_device
during this process:
1.-> t7xx_dpmaif_napi_rx_poll
2.-> t7xx_ccmni_recv_skb 
3.-> napi_gro_receive
4.-> dev_gro_receive
5.-> netif_elide_gro
One way, the net_device using in step 5 is valid, so "dev->features .." panic,
this net_device pass from t7xx_ccmni_recv_skb:
void t7xx_ccmni_recv_skb(...) {
  [...]
  
  ccmni = ccmni_ctlb->ccmni_inst[netif_id];
  if (!ccmni) {
    dev_kfree_skb(skb);
    return;
  }
  
  net_dev = ccmni->dev;
  skb->dev = net_dev;
  [...]
  napi_gro_receive(napi, skb);
  [...]
}

Another way, WWAN disconnect -> wwan_ops.dellink -> t7xx_ccmni_wwan_dellink
-> unregister_netdevice(dev).
netdevice has been invalid, so t7xx_dpmaif_napi_rx_poll can't use it any more.
I mark ccmni_inst[if_id] = NULL with netdevice invalid at the same time.
It seems that a judgment is made every time ccmni_inst[x] is used in the driver,
and the synchronization on the 2 way might have been done when NAPI triggers
polling by napi_schedule and when WWAN trigger dellink. 
So this should be safe.

Jinjian,
Best Regards.




From lkp at intel.com  Fri May 16 00:36:58 2025
From: lkp at intel.com (kernel test robot)
Date: Fri, 16 May 2025 15:36:58 +0800
Subject: [PATCH v3 16/17] drm/mediatek: Add support for multiple mmsys in
 the one mediatek-drm driver
In-Reply-To: <20250515093454.1729720-17-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-17-paul-pl.chen@mediatek.com>
Message-ID: <202505161512.PmRwb8Li-lkp@intel.com>

Hi paul-pl.chen,

kernel test robot noticed the following build warnings:

[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v6.15-rc6 next-20250515]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/paul-pl-chen/dt-bindings-soc-mediatek-add-mutex-yaml-for-MT8196/20250515-173733
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/20250515093454.1729720-17-paul-pl.chen%40mediatek.com
patch subject: [PATCH v3 16/17] drm/mediatek: Add support for multiple mmsys in the one mediatek-drm driver
config: arm64-randconfig-001-20250516 (https://download.01.org/0day-ci/archive/20250516/202505161512.PmRwb8Li-lkp at intel.com/config)
compiler: aarch64-linux-gcc (GCC) 9.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250516/202505161512.PmRwb8Li-lkp at intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505161512.PmRwb8Li-lkp at intel.com/

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/mediatek/mtk_ddp_comp.c: In function 'mtk_find_possible_crtcs':
>> drivers/gpu/drm/mediatek/mtk_ddp_comp.c:670:3: warning: this 'if' clause does not guard... [-Wmisleading-indentation]
     670 |   if (found)
         |   ^~
   drivers/gpu/drm/mediatek/mtk_ddp_comp.c:673:4: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if'
     673 |    count++;
         |    ^~~~~


vim +/if +670 drivers/gpu/drm/mediatek/mtk_ddp_comp.c

   622	
   623	int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev)
   624	{
   625		struct mtk_drm_private *private = drm->dev_private;
   626		const struct mtk_mmsys_driver_data *data;
   627		struct mtk_drm_private *priv_n;
   628		int i, j, count = 0, ret;
   629	
   630		/* search each path in private data */
   631		for (i = 0; i < MAX_CRTC; i++) {
   632			bool found = false;
   633			int avail_mmsys_num = 0;
   634	
   635			for (j = 0; j < private->data->mmsys_dev_num; j++) {
   636				const unsigned int *path = NULL;
   637				unsigned int path_len = 0;
   638	
   639				priv_n = private->all_drm_private[j];
   640				data = priv_n->data;
   641	
   642				if (i == CRTC_MAIN) {
   643					path = data->main_path;
   644					path_len = data->main_len;
   645				} else if (i == CRTC_EXT) {
   646					path = data->ext_path;
   647					path_len = data->ext_len;
   648				} else if (i == CRTC_THIRD) {
   649					path = data->third_path;
   650					path_len = data->third_len;
   651				}
   652	
   653				/* skip if no path data in current mmsys */
   654				if (path_len == 0 || !path) {
   655					avail_mmsys_num++;
   656					continue;
   657				}
   658	
   659				if (mtk_ddp_path_available(path, path_len, priv_n->comp_node))
   660					avail_mmsys_num++;
   661	
   662				if (mtk_ddp_comp_find(dev, path, path_len, priv_n->ddp_comp))
   663					found = true;
   664		}
   665	
   666			/* skip invalid path */
   667			if (avail_mmsys_num != private->data->mmsys_dev_num)
   668				continue;
   669	
 > 670			if (found)
   671				return BIT(count);
   672	
   673				count++;
   674		}
   675	
   676		ret = mtk_ddp_comp_find_in_route(dev,
   677						 private->data->conn_routes,
   678						 private->data->num_conn_routes,
   679						 private->ddp_comp);
   680	
   681		if (ret < 0)
   682			DRM_INFO("Failed to find comp in ddp table, ret = %d\n", ret);
   683	
   684		return ret;
   685	}
   686	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki


From lorenzo at kernel.org  Fri May 16 00:59:58 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Fri, 16 May 2025 09:59:58 +0200
Subject: [PATCH net-next v2 0/3] net: airoha: Add per-flow stats support to
 hw flowtable offloading
Message-ID: <20250516-airoha-en7581-flowstats-v2-0-06d5fbf28984@kernel.org>

Introduce per-flow stats accounting to the flowtable hw offload in the
airoha_eth driver. Flow stats are split in the PPE and NPU modules:
- PPE: accounts for high 32bit of per-flow stats
- NPU: accounts for low 32bit of per-flow stats

---
Changes in v2:
- fix memory leaks in airoha_npu_stats_setup() and in
  airoha_npu_foe_commit_entry()
- disable hw keepalive
- fix sparse warnings
- Link to v1: https://lore.kernel.org/r/20250514-airoha-en7581-flowstats-v1-0-c00ede12a2ca at kernel.org

---
Lorenzo Bianconi (3):
      net: airoha: npu: Move memory allocation in airoha_npu_send_msg() caller
      net: airoha: Add FLOW_CLS_STATS callback support
      net: airoha: ppe: Disable packet keepalive

 drivers/net/ethernet/airoha/Kconfig              |   7 +
 drivers/net/ethernet/airoha/airoha_eth.h         |  33 +++
 drivers/net/ethernet/airoha/airoha_npu.c         | 178 ++++++++++-----
 drivers/net/ethernet/airoha/airoha_npu.h         |   4 +-
 drivers/net/ethernet/airoha/airoha_ppe.c         | 270 +++++++++++++++++++++--
 drivers/net/ethernet/airoha/airoha_ppe_debugfs.c |   9 +-
 6 files changed, 427 insertions(+), 74 deletions(-)
---
base-commit: 894fbb55e60cab4ea740f6c65a08b5f8155221f4
change-id: 20250415-airoha-en7581-flowstats-7e69cf3fd94d

Best regards,
-- 
Lorenzo Bianconi <lorenzo at kernel.org>



From lorenzo at kernel.org  Fri May 16 00:59:59 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Fri, 16 May 2025 09:59:59 +0200
Subject: [PATCH net-next v2 1/3] net: airoha: npu: Move memory allocation
 in airoha_npu_send_msg() caller
In-Reply-To: <20250516-airoha-en7581-flowstats-v2-0-06d5fbf28984@kernel.org>
References: <20250516-airoha-en7581-flowstats-v2-0-06d5fbf28984@kernel.org>
Message-ID: <20250516-airoha-en7581-flowstats-v2-1-06d5fbf28984@kernel.org>

Move ppe_mbox_data struct memory allocation from airoha_npu_send_msg
routine to the caller one. This is a preliminary patch to enable wlan NPU
offloading and flow counter stats support.

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 drivers/net/ethernet/airoha/airoha_npu.c | 126 ++++++++++++++++++-------------
 1 file changed, 72 insertions(+), 54 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_npu.c b/drivers/net/ethernet/airoha/airoha_npu.c
index ead0625e781f57cd7c5883b6dd3d441db62292d3..51c6fbd7b7b772baf8e05b10250d37416fa36f39 100644
--- a/drivers/net/ethernet/airoha/airoha_npu.c
+++ b/drivers/net/ethernet/airoha/airoha_npu.c
@@ -124,17 +124,12 @@ static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,
 	u16 core = 0; /* FIXME */
 	u32 val, offset = core << 4;
 	dma_addr_t dma_addr;
-	void *addr;
 	int ret;
 
-	addr = kmemdup(p, size, GFP_ATOMIC);
-	if (!addr)
-		return -ENOMEM;
-
-	dma_addr = dma_map_single(npu->dev, addr, size, DMA_TO_DEVICE);
+	dma_addr = dma_map_single(npu->dev, p, size, DMA_TO_DEVICE);
 	ret = dma_mapping_error(npu->dev, dma_addr);
 	if (ret)
-		goto out;
+		return ret;
 
 	spin_lock_bh(&npu->cores[core].lock);
 
@@ -155,8 +150,6 @@ static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,
 	spin_unlock_bh(&npu->cores[core].lock);
 
 	dma_unmap_single(npu->dev, dma_addr, size, DMA_TO_DEVICE);
-out:
-	kfree(addr);
 
 	return ret;
 }
@@ -261,76 +254,101 @@ static irqreturn_t airoha_npu_wdt_handler(int irq, void *core_instance)
 
 static int airoha_npu_ppe_init(struct airoha_npu *npu)
 {
-	struct ppe_mbox_data ppe_data = {
-		.func_type = NPU_OP_SET,
-		.func_id = PPE_FUNC_SET_WAIT_HWNAT_INIT,
-		.init_info = {
-			.ppe_type = PPE_TYPE_L2B_IPV4_IPV6,
-			.wan_mode = QDMA_WAN_ETHER,
-		},
-	};
+	struct ppe_mbox_data *ppe_data;
+	int err;
+
+	ppe_data = kzalloc(sizeof(*ppe_data), GFP_KERNEL);
+	if (!ppe_data)
+		return -ENOMEM;
 
-	return airoha_npu_send_msg(npu, NPU_FUNC_PPE, &ppe_data,
-				   sizeof(struct ppe_mbox_data));
+	ppe_data->func_type = NPU_OP_SET;
+	ppe_data->func_id = PPE_FUNC_SET_WAIT_HWNAT_INIT;
+	ppe_data->init_info.ppe_type = PPE_TYPE_L2B_IPV4_IPV6;
+	ppe_data->init_info.wan_mode = QDMA_WAN_ETHER;
+
+	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
+				  sizeof(*ppe_data));
+	kfree(ppe_data);
+
+	return err;
 }
 
 static int airoha_npu_ppe_deinit(struct airoha_npu *npu)
 {
-	struct ppe_mbox_data ppe_data = {
-		.func_type = NPU_OP_SET,
-		.func_id = PPE_FUNC_SET_WAIT_HWNAT_DEINIT,
-	};
+	struct ppe_mbox_data *ppe_data;
+	int err;
+
+	ppe_data = kzalloc(sizeof(*ppe_data), GFP_KERNEL);
+	if (!ppe_data)
+		return -ENOMEM;
+
+	ppe_data->func_type = NPU_OP_SET;
+	ppe_data->func_id = PPE_FUNC_SET_WAIT_HWNAT_DEINIT;
 
-	return airoha_npu_send_msg(npu, NPU_FUNC_PPE, &ppe_data,
-				   sizeof(struct ppe_mbox_data));
+	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
+				  sizeof(*ppe_data));
+	kfree(ppe_data);
+
+	return err;
 }
 
 static int airoha_npu_ppe_flush_sram_entries(struct airoha_npu *npu,
 					     dma_addr_t foe_addr,
 					     int sram_num_entries)
 {
-	struct ppe_mbox_data ppe_data = {
-		.func_type = NPU_OP_SET,
-		.func_id = PPE_FUNC_SET_WAIT_API,
-		.set_info = {
-			.func_id = PPE_SRAM_RESET_VAL,
-			.data = foe_addr,
-			.size = sram_num_entries,
-		},
-	};
+	struct ppe_mbox_data *ppe_data;
+	int err;
+
+	ppe_data = kzalloc(sizeof(*ppe_data), GFP_KERNEL);
+	if (!ppe_data)
+		return -ENOMEM;
+
+	ppe_data->func_type = NPU_OP_SET;
+	ppe_data->func_id = PPE_FUNC_SET_WAIT_API;
+	ppe_data->set_info.func_id = PPE_SRAM_RESET_VAL;
+	ppe_data->set_info.data = foe_addr;
+	ppe_data->set_info.size = sram_num_entries;
+
+	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
+				  sizeof(*ppe_data));
+	kfree(ppe_data);
 
-	return airoha_npu_send_msg(npu, NPU_FUNC_PPE, &ppe_data,
-				   sizeof(struct ppe_mbox_data));
+	return err;
 }
 
 static int airoha_npu_foe_commit_entry(struct airoha_npu *npu,
 				       dma_addr_t foe_addr,
 				       u32 entry_size, u32 hash, bool ppe2)
 {
-	struct ppe_mbox_data ppe_data = {
-		.func_type = NPU_OP_SET,
-		.func_id = PPE_FUNC_SET_WAIT_API,
-		.set_info = {
-			.data = foe_addr,
-			.size = entry_size,
-		},
-	};
+	struct ppe_mbox_data *ppe_data;
 	int err;
 
-	ppe_data.set_info.func_id = ppe2 ? PPE2_SRAM_SET_ENTRY
-					 : PPE_SRAM_SET_ENTRY;
+	ppe_data = kzalloc(sizeof(*ppe_data), GFP_ATOMIC);
+	if (!ppe_data)
+		return -ENOMEM;
+
+	ppe_data->func_type = NPU_OP_SET;
+	ppe_data->func_id = PPE_FUNC_SET_WAIT_API;
+	ppe_data->set_info.data = foe_addr;
+	ppe_data->set_info.size = entry_size;
+	ppe_data->set_info.func_id = ppe2 ? PPE2_SRAM_SET_ENTRY
+					  : PPE_SRAM_SET_ENTRY;
 
-	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, &ppe_data,
-				  sizeof(struct ppe_mbox_data));
+	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
+				  sizeof(*ppe_data));
 	if (err)
-		return err;
+		goto out;
+
+	ppe_data->set_info.func_id = PPE_SRAM_SET_VAL;
+	ppe_data->set_info.data = hash;
+	ppe_data->set_info.size = sizeof(u32);
 
-	ppe_data.set_info.func_id = PPE_SRAM_SET_VAL;
-	ppe_data.set_info.data = hash;
-	ppe_data.set_info.size = sizeof(u32);
+	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
+				  sizeof(*ppe_data));
+out:
+	kfree(ppe_data);
 
-	return airoha_npu_send_msg(npu, NPU_FUNC_PPE, &ppe_data,
-				   sizeof(struct ppe_mbox_data));
+	return err;
 }
 
 struct airoha_npu *airoha_npu_get(struct device *dev)

-- 
2.49.0



From lorenzo at kernel.org  Fri May 16 01:00:00 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Fri, 16 May 2025 10:00:00 +0200
Subject: [PATCH net-next v2 2/3] net: airoha: Add FLOW_CLS_STATS callback
 support
In-Reply-To: <20250516-airoha-en7581-flowstats-v2-0-06d5fbf28984@kernel.org>
References: <20250516-airoha-en7581-flowstats-v2-0-06d5fbf28984@kernel.org>
Message-ID: <20250516-airoha-en7581-flowstats-v2-2-06d5fbf28984@kernel.org>

Introduce per-flow stats accounting to the flowtable hw offload in
the airoha_eth driver. Flow stats are split in the PPE and NPU modules:
- PPE: accounts for high 32bit of per-flow stats
- NPU: accounts for low 32bit of per-flow stats

FLOW_CLS_STATS can be enabled or disabled at compile time.

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 drivers/net/ethernet/airoha/Kconfig              |   7 +
 drivers/net/ethernet/airoha/airoha_eth.h         |  33 +++
 drivers/net/ethernet/airoha/airoha_npu.c         |  52 ++++-
 drivers/net/ethernet/airoha/airoha_npu.h         |   4 +-
 drivers/net/ethernet/airoha/airoha_ppe.c         | 269 +++++++++++++++++++++--
 drivers/net/ethernet/airoha/airoha_ppe_debugfs.c |   9 +-
 6 files changed, 354 insertions(+), 20 deletions(-)

diff --git a/drivers/net/ethernet/airoha/Kconfig b/drivers/net/ethernet/airoha/Kconfig
index 1a4cf6a259f67adf9c6115e05de16b0585092573..ad3ce501e7a577b839b674406900ddaea88a9b83 100644
--- a/drivers/net/ethernet/airoha/Kconfig
+++ b/drivers/net/ethernet/airoha/Kconfig
@@ -24,4 +24,11 @@ config NET_AIROHA
 	  This driver supports the gigabit ethernet MACs in the
 	  Airoha SoC family.
 
+config NET_AIROHA_FLOW_STATS
+	default y
+	bool "Airoha flow stats"
+	depends on NET_AIROHA && NET_AIROHA_NPU
+	help
+	  Enable Aiorha flowtable statistic counters.
+
 endif #NET_VENDOR_AIROHA
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index 53f39083a8b05f365056f5d063f801c03e777953..531a3c49c1562a986111a1ce1c215c8751c16e09 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -50,6 +50,14 @@
 #define PPE_NUM				2
 #define PPE1_SRAM_NUM_ENTRIES		(8 * 1024)
 #define PPE_SRAM_NUM_ENTRIES		(2 * PPE1_SRAM_NUM_ENTRIES)
+#ifdef CONFIG_NET_AIROHA_FLOW_STATS
+#define PPE1_STATS_NUM_ENTRIES		(4 * 1024)
+#else
+#define PPE1_STATS_NUM_ENTRIES		0
+#endif /* CONFIG_NET_AIROHA_FLOW_STATS */
+#define PPE_STATS_NUM_ENTRIES		(2 * PPE1_STATS_NUM_ENTRIES)
+#define PPE1_SRAM_NUM_DATA_ENTRIES	(PPE1_SRAM_NUM_ENTRIES - PPE1_STATS_NUM_ENTRIES)
+#define PPE_SRAM_NUM_DATA_ENTRIES	(2 * PPE1_SRAM_NUM_DATA_ENTRIES)
 #define PPE_DRAM_NUM_ENTRIES		(16 * 1024)
 #define PPE_NUM_ENTRIES			(PPE_SRAM_NUM_ENTRIES + PPE_DRAM_NUM_ENTRIES)
 #define PPE_HASH_MASK			(PPE_NUM_ENTRIES - 1)
@@ -261,6 +269,8 @@ struct airoha_foe_mac_info {
 
 	u16 pppoe_id;
 	u16 src_mac_lo;
+
+	u32 meter;
 };
 
 #define AIROHA_FOE_IB1_UNBIND_PREBIND		BIT(24)
@@ -296,6 +306,11 @@ struct airoha_foe_mac_info {
 #define AIROHA_FOE_TUNNEL			BIT(6)
 #define AIROHA_FOE_TUNNEL_ID			GENMASK(5, 0)
 
+#define AIROHA_FOE_TUNNEL_MTU			GENMASK(31, 16)
+#define AIROHA_FOE_ACNT_GRP3			GENMASK(15, 9)
+#define AIROHA_FOE_METER_GRP3			GENMASK(8, 5)
+#define AIROHA_FOE_METER_GRP2			GENMASK(4, 0)
+
 struct airoha_foe_bridge {
 	u32 dest_mac_hi;
 
@@ -379,6 +394,8 @@ struct airoha_foe_ipv6 {
 	u32 ib2;
 
 	struct airoha_foe_mac_info_common l2;
+
+	u32 meter;
 };
 
 struct airoha_foe_entry {
@@ -397,6 +414,16 @@ struct airoha_foe_entry {
 	};
 };
 
+struct airoha_foe_stats {
+	u32 bytes;
+	u32 packets;
+};
+
+struct airoha_foe_stats64 {
+	u64 bytes;
+	u64 packets;
+};
+
 struct airoha_flow_data {
 	struct ethhdr eth;
 
@@ -447,6 +474,7 @@ struct airoha_flow_table_entry {
 	struct hlist_node l2_subflow_node; /* PPE L2 subflow entry */
 	u32 hash;
 
+	struct airoha_foe_stats64 stats;
 	enum airoha_flow_entry_type type;
 
 	struct rhash_head node;
@@ -523,6 +551,9 @@ struct airoha_ppe {
 	struct hlist_head *foe_flow;
 	u16 foe_check_time[PPE_NUM_ENTRIES];
 
+	struct airoha_foe_stats *foe_stats;
+	dma_addr_t foe_stats_dma;
+
 	struct dentry *debugfs_dir;
 };
 
@@ -582,6 +613,8 @@ int airoha_ppe_init(struct airoha_eth *eth);
 void airoha_ppe_deinit(struct airoha_eth *eth);
 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe,
 						  u32 hash);
+void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash,
+				    struct airoha_foe_stats64 *stats);
 
 #ifdef CONFIG_DEBUG_FS
 int airoha_ppe_debugfs_init(struct airoha_ppe *ppe);
diff --git a/drivers/net/ethernet/airoha/airoha_npu.c b/drivers/net/ethernet/airoha/airoha_npu.c
index 51c6fbd7b7b772baf8e05b10250d37416fa36f39..0e5b8c21b9aa8bacdfb2e1572afe4324003e8279 100644
--- a/drivers/net/ethernet/airoha/airoha_npu.c
+++ b/drivers/net/ethernet/airoha/airoha_npu.c
@@ -12,6 +12,7 @@
 #include <linux/of_reserved_mem.h>
 #include <linux/regmap.h>
 
+#include "airoha_eth.h"
 #include "airoha_npu.h"
 
 #define NPU_EN7581_FIRMWARE_DATA		"airoha/en7581_npu_data.bin"
@@ -72,6 +73,7 @@ enum {
 	PPE_FUNC_SET_WAIT_HWNAT_INIT,
 	PPE_FUNC_SET_WAIT_HWNAT_DEINIT,
 	PPE_FUNC_SET_WAIT_API,
+	PPE_FUNC_SET_WAIT_FLOW_STATS_SETUP,
 };
 
 enum {
@@ -115,6 +117,10 @@ struct ppe_mbox_data {
 			u32 size;
 			u32 data;
 		} set_info;
+		struct {
+			u32 npu_stats_addr;
+			u32 foe_stats_addr;
+		} stats_info;
 	};
 };
 
@@ -351,7 +357,40 @@ static int airoha_npu_foe_commit_entry(struct airoha_npu *npu,
 	return err;
 }
 
-struct airoha_npu *airoha_npu_get(struct device *dev)
+static int airoha_npu_stats_setup(struct airoha_npu *npu,
+				  dma_addr_t foe_stats_addr)
+{
+	int err, size = PPE_STATS_NUM_ENTRIES * sizeof(*npu->stats);
+	struct ppe_mbox_data *ppe_data;
+
+	if (!size) /* flow stats are disabled */
+		return 0;
+
+	ppe_data = kzalloc(sizeof(*ppe_data), GFP_ATOMIC);
+	if (!ppe_data)
+		return -ENOMEM;
+
+	ppe_data->func_type = NPU_OP_SET;
+	ppe_data->func_id = PPE_FUNC_SET_WAIT_FLOW_STATS_SETUP;
+	ppe_data->stats_info.foe_stats_addr = foe_stats_addr;
+
+	err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
+				  sizeof(*ppe_data));
+	if (err)
+		goto out;
+
+	npu->stats = devm_ioremap(npu->dev,
+				  ppe_data->stats_info.npu_stats_addr,
+				  size);
+	if (!npu->stats)
+		err = -ENOMEM;
+out:
+	kfree(ppe_data);
+
+	return err;
+}
+
+struct airoha_npu *airoha_npu_get(struct device *dev, dma_addr_t *stats_addr)
 {
 	struct platform_device *pdev;
 	struct device_node *np;
@@ -389,6 +428,17 @@ struct airoha_npu *airoha_npu_get(struct device *dev)
 		goto error_module_put;
 	}
 
+	if (stats_addr) {
+		int err;
+
+		err = airoha_npu_stats_setup(npu, *stats_addr);
+		if (err) {
+			dev_err(dev, "failed to allocate npu stats buffer\n");
+			npu = ERR_PTR(err);
+			goto error_module_put;
+		}
+	}
+
 	return npu;
 
 error_module_put:
diff --git a/drivers/net/ethernet/airoha/airoha_npu.h b/drivers/net/ethernet/airoha/airoha_npu.h
index a2b8ae4d947398c1a4f1bb40c2b5118298e40481..98ec3be74ce450bf4fa8bc771d19d174e8c157e5 100644
--- a/drivers/net/ethernet/airoha/airoha_npu.h
+++ b/drivers/net/ethernet/airoha/airoha_npu.h
@@ -17,6 +17,8 @@ struct airoha_npu {
 		struct work_struct wdt_work;
 	} cores[NPU_NUM_CORES];
 
+	struct airoha_foe_stats __iomem *stats;
+
 	struct {
 		int (*ppe_init)(struct airoha_npu *npu);
 		int (*ppe_deinit)(struct airoha_npu *npu);
@@ -30,5 +32,5 @@ struct airoha_npu {
 	} ops;
 };
 
-struct airoha_npu *airoha_npu_get(struct device *dev);
+struct airoha_npu *airoha_npu_get(struct device *dev, dma_addr_t *stats_addr);
 void airoha_npu_put(struct airoha_npu *npu);
diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
index 6e9787c2843bc4f09240a0bbbd1f506c099d615e..70598ba9f5ad1d30c1e408d3d97c6fa4cb0f4f4d 100644
--- a/drivers/net/ethernet/airoha/airoha_ppe.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe.c
@@ -102,7 +102,7 @@ static void airoha_ppe_hw_init(struct airoha_ppe *ppe)
 
 	if (airoha_ppe2_is_enabled(eth)) {
 		sram_num_entries =
-			PPE_RAM_NUM_ENTRIES_SHIFT(PPE1_SRAM_NUM_ENTRIES);
+			PPE_RAM_NUM_ENTRIES_SHIFT(PPE1_SRAM_NUM_DATA_ENTRIES);
 		airoha_fe_rmw(eth, REG_PPE_TB_CFG(0),
 			      PPE_SRAM_TB_NUM_ENTRY_MASK |
 			      PPE_DRAM_TB_NUM_ENTRY_MASK,
@@ -119,7 +119,7 @@ static void airoha_ppe_hw_init(struct airoha_ppe *ppe)
 					 dram_num_entries));
 	} else {
 		sram_num_entries =
-			PPE_RAM_NUM_ENTRIES_SHIFT(PPE_SRAM_NUM_ENTRIES);
+			PPE_RAM_NUM_ENTRIES_SHIFT(PPE_SRAM_NUM_DATA_ENTRIES);
 		airoha_fe_rmw(eth, REG_PPE_TB_CFG(0),
 			      PPE_SRAM_TB_NUM_ENTRY_MASK |
 			      PPE_DRAM_TB_NUM_ENTRY_MASK,
@@ -417,6 +417,77 @@ static u32 airoha_ppe_foe_get_entry_hash(struct airoha_foe_entry *hwe)
 	return hash;
 }
 
+static u32 airoha_ppe_foe_get_flow_stats_index(struct airoha_ppe *ppe, u32 hash)
+{
+	if (!airoha_ppe2_is_enabled(ppe->eth))
+		return hash;
+
+	return hash >= PPE_STATS_NUM_ENTRIES ? hash - PPE1_STATS_NUM_ENTRIES
+					     : hash;
+}
+
+static void airoha_ppe_foe_flow_stat_entry_reset(struct airoha_ppe *ppe,
+						 struct airoha_npu *npu,
+						 int index)
+{
+	memset_io(&npu->stats[index], 0, sizeof(*npu->stats));
+	memset(&ppe->foe_stats[index], 0, sizeof(*ppe->foe_stats));
+}
+
+static void airoha_ppe_foe_flow_stats_reset(struct airoha_ppe *ppe,
+					    struct airoha_npu *npu)
+{
+	int i;
+
+	for (i = 0; i < PPE_STATS_NUM_ENTRIES; i++)
+		airoha_ppe_foe_flow_stat_entry_reset(ppe, npu, i);
+}
+
+static void airoha_ppe_foe_flow_stats_update(struct airoha_ppe *ppe,
+					     struct airoha_npu *npu,
+					     struct airoha_foe_entry *hwe,
+					     u32 hash)
+{
+	int type = FIELD_GET(AIROHA_FOE_IB1_BIND_PACKET_TYPE, hwe->ib1);
+	u32 index, pse_port, val, *data, *ib2, *meter;
+	u8 nbq;
+
+	index = airoha_ppe_foe_get_flow_stats_index(ppe, hash);
+	if (index >= PPE_STATS_NUM_ENTRIES)
+		return;
+
+	if (type == PPE_PKT_TYPE_BRIDGE) {
+		data = &hwe->bridge.data;
+		ib2 = &hwe->bridge.ib2;
+		meter = &hwe->bridge.l2.meter;
+	} else if (type >= PPE_PKT_TYPE_IPV6_ROUTE_3T) {
+		data = &hwe->ipv6.data;
+		ib2 = &hwe->ipv6.ib2;
+		meter = &hwe->ipv6.meter;
+	} else {
+		data = &hwe->ipv4.data;
+		ib2 = &hwe->ipv4.ib2;
+		meter = &hwe->ipv4.l2.meter;
+	}
+
+	airoha_ppe_foe_flow_stat_entry_reset(ppe, npu, index);
+
+	val = FIELD_GET(AIROHA_FOE_CHANNEL | AIROHA_FOE_QID, *data);
+	*data = (*data & ~AIROHA_FOE_ACTDP) |
+		FIELD_PREP(AIROHA_FOE_ACTDP, val);
+
+	val = *ib2 & (AIROHA_FOE_IB2_NBQ | AIROHA_FOE_IB2_PSE_PORT |
+		      AIROHA_FOE_IB2_PSE_QOS | AIROHA_FOE_IB2_FAST_PATH);
+	*meter |= FIELD_PREP(AIROHA_FOE_TUNNEL_MTU, val);
+
+	pse_port = FIELD_GET(AIROHA_FOE_IB2_PSE_PORT, *ib2);
+	nbq = pse_port == 1 ? 6 : 5;
+	*ib2 &= ~(AIROHA_FOE_IB2_NBQ | AIROHA_FOE_IB2_PSE_PORT |
+		  AIROHA_FOE_IB2_PSE_QOS);
+	*ib2 |= FIELD_PREP(AIROHA_FOE_IB2_PSE_PORT, 6) |
+		FIELD_PREP(AIROHA_FOE_IB2_NBQ, nbq);
+}
+
 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe,
 						  u32 hash)
 {
@@ -470,6 +541,8 @@ static int airoha_ppe_foe_commit_entry(struct airoha_ppe *ppe,
 	struct airoha_foe_entry *hwe = ppe->foe + hash * sizeof(*hwe);
 	u32 ts = airoha_ppe_get_timestamp(ppe);
 	struct airoha_eth *eth = ppe->eth;
+	struct airoha_npu *npu;
+	int err = 0;
 
 	memcpy(&hwe->d, &e->d, sizeof(*hwe) - sizeof(hwe->ib1));
 	wmb();
@@ -478,25 +551,28 @@ static int airoha_ppe_foe_commit_entry(struct airoha_ppe *ppe,
 	e->ib1 |= FIELD_PREP(AIROHA_FOE_IB1_BIND_TIMESTAMP, ts);
 	hwe->ib1 = e->ib1;
 
+	rcu_read_lock();
+
+	npu = rcu_dereference(eth->npu);
+	if (!npu) {
+		err = -ENODEV;
+		goto unlock;
+	}
+
+	airoha_ppe_foe_flow_stats_update(ppe, npu, hwe, hash);
+
 	if (hash < PPE_SRAM_NUM_ENTRIES) {
 		dma_addr_t addr = ppe->foe_dma + hash * sizeof(*hwe);
 		bool ppe2 = airoha_ppe2_is_enabled(eth) &&
 			    hash >= PPE1_SRAM_NUM_ENTRIES;
-		struct airoha_npu *npu;
-		int err = -ENODEV;
 
-		rcu_read_lock();
-		npu = rcu_dereference(eth->npu);
-		if (npu)
-			err = npu->ops.ppe_foe_commit_entry(npu, addr,
-							    sizeof(*hwe), hash,
-							    ppe2);
-		rcu_read_unlock();
-
-		return err;
+		err = npu->ops.ppe_foe_commit_entry(npu, addr, sizeof(*hwe),
+						    hash, ppe2);
 	}
+unlock:
+	rcu_read_unlock();
 
-	return 0;
+	return err;
 }
 
 static void airoha_ppe_foe_remove_flow(struct airoha_ppe *ppe,
@@ -582,6 +658,7 @@ airoha_ppe_foe_commit_subflow_entry(struct airoha_ppe *ppe,
 		l2->common.etype = ETH_P_IPV6;
 
 	hwe.bridge.ib2 = e->data.bridge.ib2;
+	hwe.bridge.data = e->data.bridge.data;
 	airoha_ppe_foe_commit_entry(ppe, &hwe, hash);
 
 	return 0;
@@ -681,6 +758,98 @@ static int airoha_ppe_foe_flow_commit_entry(struct airoha_ppe *ppe,
 	return 0;
 }
 
+static int airoha_ppe_get_entry_idle_time(struct airoha_ppe *ppe, u32 ib1)
+{
+	u32 state = FIELD_GET(AIROHA_FOE_IB1_BIND_STATE, ib1);
+	u32 ts, ts_mask, now = airoha_ppe_get_timestamp(ppe);
+	int idle;
+
+	if (state == AIROHA_FOE_STATE_BIND) {
+		ts = FIELD_GET(AIROHA_FOE_IB1_BIND_TIMESTAMP, ib1);
+		ts_mask = AIROHA_FOE_IB1_BIND_TIMESTAMP;
+	} else {
+		ts = FIELD_GET(AIROHA_FOE_IB1_UNBIND_TIMESTAMP, ib1);
+		now = FIELD_GET(AIROHA_FOE_IB1_UNBIND_TIMESTAMP, now);
+		ts_mask = AIROHA_FOE_IB1_UNBIND_TIMESTAMP;
+	}
+	idle = now - ts;
+
+	return idle < 0 ? idle + ts_mask + 1 : idle;
+}
+
+static void
+airoha_ppe_foe_flow_l2_entry_update(struct airoha_ppe *ppe,
+				    struct airoha_flow_table_entry *e)
+{
+	int min_idle = airoha_ppe_get_entry_idle_time(ppe, e->data.ib1);
+	struct airoha_flow_table_entry *iter;
+	struct hlist_node *n;
+
+	lockdep_assert_held(&ppe_lock);
+
+	hlist_for_each_entry_safe(iter, n, &e->l2_flows, l2_subflow_node) {
+		struct airoha_foe_entry *hwe;
+		u32 ib1, state;
+		int idle;
+
+		hwe = airoha_ppe_foe_get_entry(ppe, iter->hash);
+		ib1 = READ_ONCE(hwe->ib1);
+
+		state = FIELD_GET(AIROHA_FOE_IB1_BIND_STATE, ib1);
+		if (state != AIROHA_FOE_STATE_BIND) {
+			iter->hash = 0xffff;
+			airoha_ppe_foe_remove_flow(ppe, iter);
+			continue;
+		}
+
+		idle = airoha_ppe_get_entry_idle_time(ppe, ib1);
+		if (idle >= min_idle)
+			continue;
+
+		min_idle = idle;
+		e->data.ib1 &= ~AIROHA_FOE_IB1_BIND_TIMESTAMP;
+		e->data.ib1 |= ib1 & AIROHA_FOE_IB1_BIND_TIMESTAMP;
+	}
+}
+
+static void airoha_ppe_foe_flow_entry_update(struct airoha_ppe *ppe,
+					     struct airoha_flow_table_entry *e)
+{
+	struct airoha_foe_entry *hwe_p, hwe = {};
+
+	spin_lock_bh(&ppe_lock);
+
+	if (e->type == FLOW_TYPE_L2) {
+		airoha_ppe_foe_flow_l2_entry_update(ppe, e);
+		goto unlock;
+	}
+
+	if (e->hash == 0xffff)
+		goto unlock;
+
+	hwe_p = airoha_ppe_foe_get_entry(ppe, e->hash);
+	if (!hwe_p)
+		goto unlock;
+
+	memcpy(&hwe, hwe_p, sizeof(*hwe_p));
+	if (!airoha_ppe_foe_compare_entry(e, &hwe)) {
+		e->hash = 0xffff;
+		goto unlock;
+	}
+
+	e->data.ib1 = hwe.ib1;
+unlock:
+	spin_unlock_bh(&ppe_lock);
+}
+
+static int airoha_ppe_entry_idle_time(struct airoha_ppe *ppe,
+				      struct airoha_flow_table_entry *e)
+{
+	airoha_ppe_foe_flow_entry_update(ppe, e);
+
+	return airoha_ppe_get_entry_idle_time(ppe, e->data.ib1);
+}
+
 static int airoha_ppe_flow_offload_replace(struct airoha_gdm_port *port,
 					   struct flow_cls_offload *f)
 {
@@ -896,6 +1065,60 @@ static int airoha_ppe_flow_offload_destroy(struct airoha_gdm_port *port,
 	return 0;
 }
 
+void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash,
+				    struct airoha_foe_stats64 *stats)
+{
+	u32 index = airoha_ppe_foe_get_flow_stats_index(ppe, hash);
+	struct airoha_eth *eth = ppe->eth;
+	struct airoha_npu *npu;
+
+	if (index >= PPE_STATS_NUM_ENTRIES)
+		return;
+
+	rcu_read_lock();
+
+	npu = rcu_dereference(eth->npu);
+	if (npu) {
+		u64 packets = ppe->foe_stats[index].packets;
+		u64 bytes = ppe->foe_stats[index].bytes;
+		struct airoha_foe_stats npu_stats;
+
+		memcpy_fromio(&npu_stats, &npu->stats[index],
+			      sizeof(*npu->stats));
+		stats->packets = packets << 32 | npu_stats.packets;
+		stats->bytes = bytes << 32 | npu_stats.bytes;
+	}
+
+	rcu_read_unlock();
+}
+
+static int airoha_ppe_flow_offload_stats(struct airoha_gdm_port *port,
+					 struct flow_cls_offload *f)
+{
+	struct airoha_eth *eth = port->qdma->eth;
+	struct airoha_flow_table_entry *e;
+	u32 idle;
+
+	e = rhashtable_lookup(&eth->flow_table, &f->cookie,
+			      airoha_flow_table_params);
+	if (!e)
+		return -ENOENT;
+
+	idle = airoha_ppe_entry_idle_time(eth->ppe, e);
+	f->stats.lastused = jiffies - idle * HZ;
+
+	if (e->hash != 0xffff) {
+		struct airoha_foe_stats64 stats = {};
+
+		airoha_ppe_foe_entry_get_stats(eth->ppe, e->hash, &stats);
+		f->stats.pkts += (stats.packets - e->stats.packets);
+		f->stats.bytes += (stats.bytes - e->stats.bytes);
+		e->stats = stats;
+	}
+
+	return 0;
+}
+
 static int airoha_ppe_flow_offload_cmd(struct airoha_gdm_port *port,
 				       struct flow_cls_offload *f)
 {
@@ -904,6 +1127,8 @@ static int airoha_ppe_flow_offload_cmd(struct airoha_gdm_port *port,
 		return airoha_ppe_flow_offload_replace(port, f);
 	case FLOW_CLS_DESTROY:
 		return airoha_ppe_flow_offload_destroy(port, f);
+	case FLOW_CLS_STATS:
+		return airoha_ppe_flow_offload_stats(port, f);
 	default:
 		break;
 	}
@@ -929,11 +1154,12 @@ static int airoha_ppe_flush_sram_entries(struct airoha_ppe *ppe,
 
 static struct airoha_npu *airoha_ppe_npu_get(struct airoha_eth *eth)
 {
-	struct airoha_npu *npu = airoha_npu_get(eth->dev);
+	struct airoha_npu *npu = airoha_npu_get(eth->dev,
+						&eth->ppe->foe_stats_dma);
 
 	if (IS_ERR(npu)) {
 		request_module("airoha-npu");
-		npu = airoha_npu_get(eth->dev);
+		npu = airoha_npu_get(eth->dev, &eth->ppe->foe_stats_dma);
 	}
 
 	return npu;
@@ -956,6 +1182,8 @@ static int airoha_ppe_offload_setup(struct airoha_eth *eth)
 	if (err)
 		goto error_npu_put;
 
+	airoha_ppe_foe_flow_stats_reset(eth->ppe, npu);
+
 	rcu_assign_pointer(eth->npu, npu);
 	synchronize_rcu();
 
@@ -1027,6 +1255,15 @@ int airoha_ppe_init(struct airoha_eth *eth)
 	if (!ppe->foe_flow)
 		return -ENOMEM;
 
+	foe_size = PPE_STATS_NUM_ENTRIES * sizeof(*ppe->foe_stats);
+	if (foe_size) {
+		ppe->foe_stats = dmam_alloc_coherent(eth->dev, foe_size,
+						     &ppe->foe_stats_dma,
+						     GFP_KERNEL);
+		if (!ppe->foe_stats)
+			return -ENOMEM;
+	}
+
 	err = rhashtable_init(&eth->flow_table, &airoha_flow_table_params);
 	if (err)
 		return err;
diff --git a/drivers/net/ethernet/airoha/airoha_ppe_debugfs.c b/drivers/net/ethernet/airoha/airoha_ppe_debugfs.c
index 3cdc6fd53fc751235d65c277a35c69ab6935ceec..05a756233f6a44fa51d1c57dd39d89c8ea488054 100644
--- a/drivers/net/ethernet/airoha/airoha_ppe_debugfs.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe_debugfs.c
@@ -61,6 +61,7 @@ static int airoha_ppe_debugfs_foe_show(struct seq_file *m, void *private,
 		u16 *src_port = NULL, *dest_port = NULL;
 		struct airoha_foe_mac_info_common *l2;
 		unsigned char h_source[ETH_ALEN] = {};
+		struct airoha_foe_stats64 stats = {};
 		unsigned char h_dest[ETH_ALEN];
 		struct airoha_foe_entry *hwe;
 		u32 type, state, ib2, data;
@@ -144,14 +145,18 @@ static int airoha_ppe_debugfs_foe_show(struct seq_file *m, void *private,
 				cpu_to_be16(hwe->ipv4.l2.src_mac_lo);
 		}
 
+		airoha_ppe_foe_entry_get_stats(ppe, i, &stats);
+
 		*((__be32 *)h_dest) = cpu_to_be32(l2->dest_mac_hi);
 		*((__be16 *)&h_dest[4]) = cpu_to_be16(l2->dest_mac_lo);
 		*((__be32 *)h_source) = cpu_to_be32(l2->src_mac_hi);
 
 		seq_printf(m, " eth=%pM->%pM etype=%04x data=%08x"
-			      " vlan=%d,%d ib1=%08x ib2=%08x\n",
+			      " vlan=%d,%d ib1=%08x ib2=%08x"
+			      " packets=%llu bytes=%llu\n",
 			   h_source, h_dest, l2->etype, data,
-			   l2->vlan1, l2->vlan2, hwe->ib1, ib2);
+			   l2->vlan1, l2->vlan2, hwe->ib1, ib2,
+			   stats.packets, stats.bytes);
 	}
 
 	return 0;

-- 
2.49.0



From lorenzo at kernel.org  Fri May 16 01:00:01 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Fri, 16 May 2025 10:00:01 +0200
Subject: [PATCH net-next v2 3/3] net: airoha: ppe: Disable packet keepalive
In-Reply-To: <20250516-airoha-en7581-flowstats-v2-0-06d5fbf28984@kernel.org>
References: <20250516-airoha-en7581-flowstats-v2-0-06d5fbf28984@kernel.org>
Message-ID: <20250516-airoha-en7581-flowstats-v2-3-06d5fbf28984@kernel.org>

Since netfilter flowtable entries are now refreshed by flow-stats
polling, we can disable hw packet keepalive used to periodically send
packets belonging to offloaded flows to the kernel in order to refresh
flowtable entries.

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 drivers/net/ethernet/airoha/airoha_ppe.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
index 70598ba9f5ad1d30c1e408d3d97c6fa4cb0f4f4d..2d273937f19cf304ab4b821241fdc3ea93604f0e 100644
--- a/drivers/net/ethernet/airoha/airoha_ppe.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe.c
@@ -84,6 +84,7 @@ static void airoha_ppe_hw_init(struct airoha_ppe *ppe)
 
 		airoha_fe_rmw(eth, REG_PPE_TB_CFG(i),
 			      PPE_TB_CFG_SEARCH_MISS_MASK |
+			      PPE_TB_CFG_KEEPALIVE_MASK |
 			      PPE_TB_ENTRY_SIZE_MASK,
 			      FIELD_PREP(PPE_TB_CFG_SEARCH_MISS_MASK, 3) |
 			      FIELD_PREP(PPE_TB_ENTRY_SIZE_MASK, 0));

-- 
2.49.0



From SkyLake.Huang at mediatek.com  Fri May 16 03:23:25 2025
From: SkyLake.Huang at mediatek.com (Sky Huang)
Date: Fri, 16 May 2025 18:23:25 +0800
Subject: [PATCH net-next v4 0/2] Add built-in 2.5G ethernet phy support on MT7988
Message-ID: <20250516102327.2014531-1-SkyLake.Huang@mediatek.com>

From: Sky Huang <skylake.huang at mediatek.com>

This patchset adds support for built-in 2.5Gphy on MT7988, sort file
and config sequence in related Kconfig and Makefile.

---
Change in v2:
- Add missing dt-bindings and dts node.
- Remove mtk_phy_leds_state_init() temporarily. I'm going to add LED support
later.
- Remove "Firmware loading/trigger ok" log.
- Add macro define for 0x800e & 0x800f

Change in v3:
1. Remove unnecessary headers and unnecessary print log.
2. ioremap IO space (MT7988_2P5GE_PMB_FW_BASE/MTK_2P5GPHY_MCU_CSR_BASE)
directly instead of of_iomap() compatible node (mediatek,2p5gphy-fw) from dtsi
3. Call mt798x_2p5ge_phy_load_fw() from .probe instead of .config_init. This is
tested ok with openWRT-24.10 and "mediatek/mt7988/i2p5ge-phy-pmb.bin" firmware
is embedded into kernel image instead of rootfs image.
4. Use request_firmware_direct instead of request_firmware. We don't want sysfs
fallback in this driver to avoid blocking.
5. Remove mtk_i2p5ge_phy_priv sturct since it's not used anymore.

Change in v4:
1. Sort file and config in alphabetical order.
2. Remove unncessary parens around macros.
3. Arrange vars in reversed Christmas tree.
4. Move LED settings and pinctrl request to .probe to avoid
managed-dev structure reallocation.
5. Replace "return __genphy_config_aneg(phydev, changed);" with
"return genphy_c45_check_and_restart_aneg(phydev, changed);" in
mt798x_2p5ge_phy_config_aneg()
---
Sky Huang (2):
  net: phy: mediatek: Sort config and file names in Kconfig and Makefile
  net: phy: mediatek: add driver for built-in 2.5G ethernet PHY on
    MT7988

 MAINTAINERS                          |   1 +
 drivers/net/phy/mediatek/Kconfig     |  15 +-
 drivers/net/phy/mediatek/Makefile    |   3 +-
 drivers/net/phy/mediatek/mtk-2p5ge.c | 321 +++++++++++++++++++++++++++
 4 files changed, 337 insertions(+), 3 deletions(-)
 create mode 100644 drivers/net/phy/mediatek/mtk-2p5ge.c

-- 
2.45.2



From SkyLake.Huang at mediatek.com  Fri May 16 03:23:26 2025
From: SkyLake.Huang at mediatek.com (Sky Huang)
Date: Fri, 16 May 2025 18:23:26 +0800
Subject: [PATCH net-next v4 1/2] net: phy: mediatek: Sort config and file names in Kconfig and Makefile
In-Reply-To: <20250516102327.2014531-1-SkyLake.Huang@mediatek.com>
References: <20250516102327.2014531-1-SkyLake.Huang@mediatek.com>
Message-ID: <20250516102327.2014531-2-SkyLake.Huang@mediatek.com>

From: Sky Huang <skylake.huang at mediatek.com>

Sort config and file names in Kconfig and Makefile in
drivers/net/phy/mediatek/ in alphabetical order.

Signed-off-by: Sky Huang <skylake.huang at mediatek.com>
---
 drivers/net/phy/mediatek/Kconfig  | 6 +++---
 drivers/net/phy/mediatek/Makefile | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/phy/mediatek/Kconfig b/drivers/net/phy/mediatek/Kconfig
index 2a8ac5aed0f8..29a09d39ff6f 100644
--- a/drivers/net/phy/mediatek/Kconfig
+++ b/drivers/net/phy/mediatek/Kconfig
@@ -1,7 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
-config MTK_NET_PHYLIB
-	tristate
-
 config MEDIATEK_GE_PHY
 	tristate "MediaTek Gigabit Ethernet PHYs"
 	select MTK_NET_PHYLIB
@@ -25,3 +22,6 @@ config MEDIATEK_GE_SOC_PHY
 	  the MT7981 and MT7988 SoCs. These PHYs need calibration data
 	  present in the SoCs efuse and will dynamically calibrate VCM
 	  (common-mode voltage) during startup.
+
+config MTK_NET_PHYLIB
+	tristate
diff --git a/drivers/net/phy/mediatek/Makefile b/drivers/net/phy/mediatek/Makefile
index 814879d0abe5..14b2c17b3f8f 100644
--- a/drivers/net/phy/mediatek/Makefile
+++ b/drivers/net/phy/mediatek/Makefile
@@ -1,4 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_MTK_NET_PHYLIB)		+= mtk-phy-lib.o
 obj-$(CONFIG_MEDIATEK_GE_PHY)		+= mtk-ge.o
 obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)	+= mtk-ge-soc.o
+obj-$(CONFIG_MTK_NET_PHYLIB)		+= mtk-phy-lib.o
-- 
2.45.2



From SkyLake.Huang at mediatek.com  Fri May 16 03:23:27 2025
From: SkyLake.Huang at mediatek.com (Sky Huang)
Date: Fri, 16 May 2025 18:23:27 +0800
Subject: [PATCH net-next v4 2/2] net: phy: mediatek: add driver for built-in 2.5G ethernet PHY on MT7988
In-Reply-To: <20250516102327.2014531-1-SkyLake.Huang@mediatek.com>
References: <20250516102327.2014531-1-SkyLake.Huang@mediatek.com>
Message-ID: <20250516102327.2014531-3-SkyLake.Huang@mediatek.com>

From: Sky Huang <skylake.huang at mediatek.com>

Add support for internal 2.5Gphy on MT7988. This driver will load
necessary firmware and add appropriate time delay to make sure
that firmware works stably. The firmware loading procedure takes
about 11ms in this driver.

Signed-off-by: Sky Huang <skylake.huang at mediatek.com>
---
 MAINTAINERS                          |   1 +
 drivers/net/phy/mediatek/Kconfig     |  11 +
 drivers/net/phy/mediatek/Makefile    |   1 +
 drivers/net/phy/mediatek/mtk-2p5ge.c | 321 +++++++++++++++++++++++++++
 4 files changed, 334 insertions(+)
 create mode 100644 drivers/net/phy/mediatek/mtk-2p5ge.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 241ca9e260a2..be0787810834 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14726,6 +14726,7 @@ M:	Qingfang Deng <dqfext at gmail.com>
 M:	SkyLake Huang <SkyLake.Huang at mediatek.com>
 L:	netdev at vger.kernel.org
 S:	Maintained
+F:	drivers/net/phy/mediatek/mtk-2p5ge.c
 F:	drivers/net/phy/mediatek/mtk-ge-soc.c
 F:	drivers/net/phy/mediatek/mtk-phy-lib.c
 F:	drivers/net/phy/mediatek/mtk-ge.c
diff --git a/drivers/net/phy/mediatek/Kconfig b/drivers/net/phy/mediatek/Kconfig
index 29a09d39ff6f..fbefa2aa41ed 100644
--- a/drivers/net/phy/mediatek/Kconfig
+++ b/drivers/net/phy/mediatek/Kconfig
@@ -1,4 +1,15 @@
 # SPDX-License-Identifier: GPL-2.0-only
+config MEDIATEK_2P5GE_PHY
+	tristate "MediaTek 2.5Gb Ethernet PHYs"
+	depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
+	select MTK_NET_PHYLIB
+	help
+	  Supports MediaTek SoC built-in 2.5Gb Ethernet PHYs.
+
+	  This will load necessary firmware and add appropriate time delay.
+	  Accelerate this procedure through internal pbus instead of MDIO
+	  bus. Certain link-up issues will also be fixed here.
+
 config MEDIATEK_GE_PHY
 	tristate "MediaTek Gigabit Ethernet PHYs"
 	select MTK_NET_PHYLIB
diff --git a/drivers/net/phy/mediatek/Makefile b/drivers/net/phy/mediatek/Makefile
index 14b2c17b3f8f..ac57ecc799fc 100644
--- a/drivers/net/phy/mediatek/Makefile
+++ b/drivers/net/phy/mediatek/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_MEDIATEK_2P5GE_PHY)	+= mtk-2p5ge.o
 obj-$(CONFIG_MEDIATEK_GE_PHY)		+= mtk-ge.o
 obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)	+= mtk-ge-soc.o
 obj-$(CONFIG_MTK_NET_PHYLIB)		+= mtk-phy-lib.o
diff --git a/drivers/net/phy/mediatek/mtk-2p5ge.c b/drivers/net/phy/mediatek/mtk-2p5ge.c
new file mode 100644
index 000000000000..e147eab523ef
--- /dev/null
+++ b/drivers/net/phy/mediatek/mtk-2p5ge.c
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <linux/bitfield.h>
+#include <linux/firmware.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/phy.h>
+
+#include "mtk.h"
+
+#define MTK_2P5GPHY_ID_MT7988		0x00339c11
+
+#define MT7988_2P5GE_PMB_FW		"mediatek/mt7988/i2p5ge-phy-pmb.bin"
+#define MT7988_2P5GE_PMB_FW_SIZE	0x20000
+#define MT7988_2P5GE_PMB_FW_BASE	0x0f100000
+#define MT7988_2P5GE_PMB_FW_LEN		0x20000
+#define MTK_2P5GPHY_MCU_CSR_BASE	0x0f0f0000
+#define MTK_2P5GPHY_MCU_CSR_LEN		0x20
+#define MD32_EN_CFG			0x18
+#define   MD32_EN			BIT(0)
+
+#define BASE100T_STATUS_EXTEND		0x10
+#define BASE1000T_STATUS_EXTEND		0x11
+#define EXTEND_CTRL_AND_STATUS		0x16
+
+#define PHY_AUX_CTRL_STATUS		0x1d
+#define   PHY_AUX_DPX_MASK		GENMASK(5, 5)
+#define   PHY_AUX_SPEED_MASK		GENMASK(4, 2)
+
+/* Registers on MDIO_MMD_VEND1 */
+#define MTK_PHY_LPI_PCS_DSP_CTRL		0x121
+#define   MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK	GENMASK(12, 8)
+
+#define MTK_PHY_HOST_CMD1		0x800e
+#define MTK_PHY_HOST_CMD2		0x800f
+/* Registers on Token Ring debug nodes */
+/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
+#define AUTO_NP_10XEN				BIT(6)
+
+enum {
+	PHY_AUX_SPD_10 = 0,
+	PHY_AUX_SPD_100,
+	PHY_AUX_SPD_1000,
+	PHY_AUX_SPD_2500,
+};
+
+static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev)
+{
+	struct device *dev = &phydev->mdio.dev;
+	void __iomem *mcu_csr_base, *pmb_addr;
+	const struct firmware *fw;
+	int ret, i;
+	u32 reg;
+
+	pmb_addr = ioremap(MT7988_2P5GE_PMB_FW_BASE, MT7988_2P5GE_PMB_FW_LEN);
+	if (!pmb_addr)
+		return -ENOMEM;
+	mcu_csr_base = ioremap(MTK_2P5GPHY_MCU_CSR_BASE,
+			       MTK_2P5GPHY_MCU_CSR_LEN);
+	if (!mcu_csr_base) {
+		ret = -ENOMEM;
+		goto free_pmb;
+	}
+
+	ret = request_firmware_direct(&fw, MT7988_2P5GE_PMB_FW, dev);
+	if (ret) {
+		dev_err(dev, "failed to load firmware: %s, ret: %d\n",
+			MT7988_2P5GE_PMB_FW, ret);
+		goto free;
+	}
+
+	if (fw->size != MT7988_2P5GE_PMB_FW_SIZE) {
+		dev_err(dev, "Firmware size 0x%zx != 0x%x\n",
+			fw->size, MT7988_2P5GE_PMB_FW_SIZE);
+		ret = -EINVAL;
+		goto release_fw;
+	}
+
+	reg = readw(mcu_csr_base + MD32_EN_CFG);
+	if (reg & MD32_EN) {
+		phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
+		usleep_range(10000, 11000);
+	}
+	phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
+
+	/* Write magic number to safely stall MCU */
+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD1, 0x1100);
+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD2, 0x00df);
+
+	for (i = 0; i < MT7988_2P5GE_PMB_FW_SIZE - 1; i += 4)
+		writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
+
+	writew(reg & ~MD32_EN, mcu_csr_base + MD32_EN_CFG);
+	writew(reg | MD32_EN, mcu_csr_base + MD32_EN_CFG);
+	phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
+	/* We need a delay here to stabilize initialization of MCU */
+	usleep_range(7000, 8000);
+
+	dev_info(dev, "Firmware date code: %x/%x/%x, version: %x.%x\n",
+		 be16_to_cpu(*((__be16 *)(fw->data +
+					  MT7988_2P5GE_PMB_FW_SIZE - 8))),
+		 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 6),
+		 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 5),
+		 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 2),
+		 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 1));
+
+release_fw:
+	release_firmware(fw);
+free:
+	iounmap(mcu_csr_base);
+free_pmb:
+	iounmap(pmb_addr);
+
+	return ret;
+}
+
+static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
+{
+	/* Check if PHY interface type is compatible */
+	if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL)
+		return -ENODEV;
+
+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL,
+		       MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0);
+
+	/* Enable 16-bit next page exchange bit if 1000-BT isn't advertising */
+	mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, AUTO_NP_10XEN,
+		      FIELD_PREP(AUTO_NP_10XEN, 0x1));
+
+	/* Enable HW auto downshift */
+	phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
+			 MTK_PHY_AUX_CTRL_AND_STATUS,
+			 0, MTK_PHY_ENABLE_DOWNSHIFT);
+
+	return 0;
+}
+
+static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
+{
+	bool changed = false;
+	u32 adv;
+	int ret;
+
+	ret = genphy_c45_an_config_aneg(phydev);
+	if (ret < 0)
+		return ret;
+	if (ret > 0)
+		changed = true;
+
+	/* Clause 45 doesn't define 1000BaseT support. Use Clause 22 instead in
+	 * our design.
+	 */
+	adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
+	ret = phy_modify_changed(phydev, MII_CTRL1000, ADVERTISE_1000FULL, adv);
+	if (ret < 0)
+		return ret;
+	if (ret > 0)
+		changed = true;
+
+	return genphy_c45_check_and_restart_aneg(phydev, changed);
+}
+
+static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
+{
+	int ret;
+
+	ret = genphy_c45_pma_read_abilities(phydev);
+	if (ret)
+		return ret;
+
+	/* This phy can't handle collision, and neither can (XFI)MAC it's
+	 * connected to. Although it can do HDX handshake, it doesn't support
+	 * CSMA/CD that HDX requires.
+	 */
+	linkmode_clear_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
+			   phydev->supported);
+
+	return 0;
+}
+
+static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
+{
+	int ret;
+
+	/* When MDIO_STAT1_LSTATUS is raised genphy_c45_read_link(), this phy
+	 * actually hasn't finished AN. So use CL22's link update function
+	 * instead.
+	 */
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	phydev->speed = SPEED_UNKNOWN;
+	phydev->duplex = DUPLEX_UNKNOWN;
+	phydev->pause = 0;
+	phydev->asym_pause = 0;
+
+	/* We'll read link speed through vendor specific registers down below.
+	 * So remove phy_resolve_aneg_linkmode (AN on) & genphy_c45_read_pma
+	 * (AN off).
+	 */
+	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
+		ret = genphy_c45_read_lpa(phydev);
+		if (ret < 0)
+			return ret;
+
+		/* Clause 45 doesn't define 1000BaseT support. Read the link
+		 * partner's 1G advertisement via Clause 22.
+		 */
+		ret = phy_read(phydev, MII_STAT1000);
+		if (ret < 0)
+			return ret;
+		mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
+	} else if (phydev->autoneg == AUTONEG_DISABLE) {
+		linkmode_zero(phydev->lp_advertising);
+	}
+
+	if (phydev->link) {
+		ret = phy_read(phydev, PHY_AUX_CTRL_STATUS);
+		if (ret < 0)
+			return ret;
+
+		switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
+		case PHY_AUX_SPD_10:
+			phydev->speed = SPEED_10;
+			break;
+		case PHY_AUX_SPD_100:
+			phydev->speed = SPEED_100;
+			break;
+		case PHY_AUX_SPD_1000:
+			phydev->speed = SPEED_1000;
+			break;
+		case PHY_AUX_SPD_2500:
+			phydev->speed = SPEED_2500;
+			break;
+		}
+
+		phydev->duplex = DUPLEX_FULL;
+		phydev->rate_matching = RATE_MATCH_PAUSE;
+	}
+
+	return 0;
+}
+
+static int mt798x_2p5ge_phy_get_rate_matching(struct phy_device *phydev,
+					      phy_interface_t iface)
+{
+	return RATE_MATCH_PAUSE;
+}
+
+static int mt798x_2p5ge_phy_probe(struct phy_device *phydev)
+{
+	struct pinctrl *pinctrl;
+	int ret;
+
+	switch (phydev->drv->phy_id) {
+	case MTK_2P5GPHY_ID_MT7988:
+		/* This built-in 2.5GbE hardware only sets MDIO_DEVS_PMAPMD.
+		 * Set the rest by this driver since PCS/AN/VEND1/VEND2 MDIO
+		 * manageable devices actually exist.
+		 */
+		phydev->c45_ids.mmds_present |= MDIO_DEVS_PCS |
+						MDIO_DEVS_AN |
+						MDIO_DEVS_VEND1 |
+						MDIO_DEVS_VEND2;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ret = mt798x_2p5ge_phy_load_fw(phydev);
+	if (ret < 0)
+		return ret;
+
+	/* Setup LED */
+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
+			 MTK_PHY_LED_ON_POLARITY | MTK_PHY_LED_ON_LINK10 |
+			 MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK1000 |
+			 MTK_PHY_LED_ON_LINK2500);
+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
+			 MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX);
+
+	/* Switch pinctrl after setting polarity to avoid bogus blinking */
+	pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
+	if (IS_ERR(pinctrl))
+		dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
+
+	return 0;
+}
+
+static struct phy_driver mtk_2p5gephy_driver[] = {
+	{
+		PHY_ID_MATCH_MODEL(MTK_2P5GPHY_ID_MT7988),
+		.name = "MediaTek MT7988 2.5GbE PHY",
+		.probe = mt798x_2p5ge_phy_probe,
+		.config_init = mt798x_2p5ge_phy_config_init,
+		.config_aneg = mt798x_2p5ge_phy_config_aneg,
+		.get_features = mt798x_2p5ge_phy_get_features,
+		.read_status = mt798x_2p5ge_phy_read_status,
+		.get_rate_matching = mt798x_2p5ge_phy_get_rate_matching,
+		.suspend = genphy_suspend,
+		.resume = genphy_resume,
+		.read_page = mtk_phy_read_page,
+		.write_page = mtk_phy_write_page,
+	},
+};
+
+module_phy_driver(mtk_2p5gephy_driver);
+
+static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
+	{ PHY_ID_MATCH_VENDOR(0x00339c00) },
+	{ }
+};
+
+MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
+MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang at mediatek.com>");
+MODULE_LICENSE("GPL");
+
+MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
+MODULE_FIRMWARE(MT7988_2P5GE_PMB_FW);
-- 
2.45.2



From amergnat at baylibre.com  Fri May 16 05:47:09 2025
From: amergnat at baylibre.com (Alexandre Mergnat)
Date: Fri, 16 May 2025 14:47:09 +0200
Subject: [PATCH v8 1/3] arm64: defconfig: enable display support for
 mt8365-evk
In-Reply-To: <20231023-display-support-v8-1-c2dd7b0fb2bd@baylibre.com>
References: <20231023-display-support-v8-0-c2dd7b0fb2bd@baylibre.com>
 <20231023-display-support-v8-1-c2dd7b0fb2bd@baylibre.com>
Message-ID: <70da4bf0-a36b-474c-8057-1ad056573e01@baylibre.com>

Hello

On 20/03/2025 09:48, Alexandre Mergnat wrote:
> Enable the DRM HDMI connector support and the MIPI-DSI display
> Startek KD070FHFID015 panel to have HDMI and DSI display working
> on the mt8365-evk board.
> 
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> Signed-off-by: Alexandre Mergnat <amergnat at baylibre.com>
> ---
>   arch/arm64/configs/defconfig | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index c62831e615863..1e2963a13500b 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -897,9 +897,11 @@ CONFIG_DRM_PANEL_NOVATEK_NT36672E=m
>   CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
>   CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
>   CONFIG_DRM_PANEL_SITRONIX_ST7703=m
> +CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m
>   CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
>   CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
>   CONFIG_DRM_FSL_LDB=m
> +CONFIG_DRM_DISPLAY_CONNECTOR=m
>   CONFIG_DRM_LONTIUM_LT8912B=m
>   CONFIG_DRM_LONTIUM_LT9611=m
>   CONFIG_DRM_LONTIUM_LT9611UXC=m
> 

Gentle ping.
Is that patch can be applied please ? The remaining patches in this serie
do cleanup only, then shouldn't block this one.

-- 
Regards,
Alexandre


From amergnat at baylibre.com  Fri May 16 05:51:59 2025
From: amergnat at baylibre.com (Alexandre Mergnat)
Date: Fri, 16 May 2025 14:51:59 +0200
Subject: [PATCH v8 2/3] drm/panel: startek-kd070fhfid015: add another init
 step
In-Reply-To: <d38921cc-a565-4a79-9ecb-bfba85c3ab25@collabora.com>
References: <20231023-display-support-v8-0-c2dd7b0fb2bd@baylibre.com>
 <20231023-display-support-v8-2-c2dd7b0fb2bd@baylibre.com>
 <d70b62f8-e24e-4a10-8c6b-18d2e19f1337@collabora.com>
 <fb72f1f5-dc94-4e33-a20c-d46a081091bc@baylibre.com>
 <1ed38e6b-8d43-4cbc-9c27-58ec3c0e4dbc@baylibre.com>
 <d38921cc-a565-4a79-9ecb-bfba85c3ab25@collabora.com>
Message-ID: <94982f07-504e-439a-89b4-02a73d69bf7c@baylibre.com>

Hi Angelo,

On 15/04/2025 16:46, AngeloGioacchino Del Regno wrote:
> Il 15/04/25 16:13, Alexandre Mergnat ha scritto:
>> Hi Angelo,
>>
>> Gentle ping
>>
>> Let me shortly summarize my problem: I see the panel driver sending commands to the display before 
>> it is ready. My approach to prevent that is to delay sending commands until bridge enable. Your 
>> concern was that during the panel's .prepare() the panel driver should already be able to send 
>> commands through the bridge. Can you please clarify what you think should be the approach to fix 
>> that?
>>
> 
> Please don't top post.
> 
> Anyway - sorry but I missed your reply, that wasn't intentional - thanks for the
> ping (or I wouldn't have replied, duh!).
> 
> What is not ready? The Startek display or the MediaTek display controller?
> 

MediaTek display controller (DSI)

> The display controller shall be able to send commands when the *panel*'s .prepare()
> callback gets executed - if not, there's something wrong at the display controller
> side (driver).
> 

It's explained at the end.

> You're probably getting confused by the bridge en/disable callbacks, btw... please
> check include/drm/drm_panel.h, struct drm_panel_funcs.
> 

panel_bridge_atomic_pre_enable => drm_panel_prepare => (drm_panel_funcs.prepare) stk_panel_prepare
panel_bridge_atomic_enable => drm_panel_enable => (drm_panel_funcs.enable) stk_panel_enable

The bridge en/disable callbacks call panel and DSI enable/disable callbacks, they are linked.

> In short, the panel's prepare() should be used for whatever setup is required by
> the panel to become available to *receive the video transmission* from the display
> controller: this implies that if the panel needs DSI commands for setup, this is
> allowed and it's a perfectly fine case.
> 
> So, if you are unable to "turn the panel on and wait for it to become ready" in
> the panel's .prepare() callback, there's something wrong either in your panel
> driver, on in the display controller (the DSI driver) instead.
> 
> Since this wasn't happening before your mtk_dsi cleanup, this probably means that
> the cleanup is done wrong - and that removing the .start/.stop custom callbacks
> from that driver needs you to do something more than just that in order to avoid
> regressions.
> 

Here the current call order:
[   13.715959] mtk_dsi_ddp_start ( => dsi poweron)
[   13.716797] stk_panel_prepare ( => panel poweron + enable)
[   13.939473] mtk_dsi_bridge_atomic_pre_enable ( => dsi poweron)
[   13.939488] mtk_output_dsi_enable ( => dsi enable)

As you can see, dsi poweron is called twice. According to your comment [1] asking me to remove
custom init function in favor of DRM API call, I've removed "mtk_dsi_ddp_start". Since I don't
find any API to poweron DSI before stk_panel_prepare call, it has been split to do enable
sequence after DSI poweron+enable, because it requiere mipi dsi interface enabled to do
panel enable.

Patched solution:
[   14.164136] stk_panel_prepare ( => panel poweron)
[   14.213300] mtk_dsi_bridge_atomic_pre_enable ( => dsi poweron)
[   14.213623] mtk_output_dsi_enable ( => dsi enable)
[   14.215116] stk_panel_enable ( => panel enable)

The prepare/enable order is fixed by the DRM framework [2]

We still misaligned about the panel's prepare() should be, but even if I try to implement
whatever setup is required by the panel to become available to *receive the video
transmission* from the display controller, the DRM init order doesn't allow it.
I can move stk_panel_prepare content into stk_panel_enable if you prefer, but it's less clean
IMHO because I like to have a first callback for HW/power setup, and a second callback for SW
setup, which fit with bridge callback descriptions.
I don't see a better way to cleanup custom init, and my apologies for your time if I missed something.

[1]: https://lore.kernel.org/all/c2154240-efa1-4c73-aabe-74e938a75af1 at collabora.com/
[2]: 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/drm_bridge.c#n769

> Unfortunately, I'm pretty busy these days, otherwise I would've gladly made some
> research to try and give you some more hints.. but eh :-)
> 
> Cheers,
> Angelo
> 
>> Regards,
>> Alexandre
>>
>> On 21/03/2025 10:19, Alexandre Mergnat wrote:
>>> Hi Angelo,
>>> Thanks for the fast feedback :)
>>>
>>> On 20/03/2025 13:37, AngeloGioacchino Del Regno wrote:
>>>> Il 20/03/25 09:48, Alexandre Mergnat ha scritto:
>>>>> Currently, the panel set power, set gpio and enable the display link
>>>>> in stk_panel_prepare, pointed by drm_panel_funcs.prepare, called by
>>>>> panel_bridge_atomic_pre_enable, pointed by
>>>>> drm_bridge_funcs.atomic_pre_enable. According to the drm_bridge.h,
>>>>> atomic_pre_enable must not enable the display link
>>>>>
>>>>> Since the DSI driver is properly inited by the DRM, the panel try to
>>>>> communicate with the panel before DSI is powered on.
>>>>>
>>>>
>>>> The panel driver shall still be able to send commands in the .prepare() callback
>>>> and if this is not happening anymore... well, there's a problem!
>>>
>>> Sorry I don't think so, according to that def:
>>> ?????/**
>>> ????? * @pre_enable:
>>> ????? *
>>> ????? * This callback should enable the bridge. It is called right before
>>> ????? * the preceding element in the display pipe is enabled. If the
>>> ????? * preceding element is a bridge this means it's called before that
>>> ????? * bridge's @pre_enable function. If the preceding element is a
>>> ????? * &drm_encoder it's called right before the encoder's
>>> ????? * &drm_encoder_helper_funcs.enable, &drm_encoder_helper_funcs.commit or
>>> ????? * &drm_encoder_helper_funcs.dpms hook.
>>> ????? *
>>> ????? * The display pipe (i.e. clocks and timing signals) feeding this bridge
>>> ????? * will not yet be running when this callback is called. The bridge must
>>> ????? * not enable the display link feeding the next bridge in the chain (if
>>> ????? * there is one) when this callback is called.
>>> ????? *
>>> ????? * The @pre_enable callback is optional.
>>> ????? *
>>> ????? * NOTE:
>>> ????? *
>>> ????? * This is deprecated, do not use!
>>> ????? * New drivers shall use &drm_bridge_funcs.atomic_pre_enable.
>>> ????? */
>>> ?????void (*pre_enable)(struct drm_bridge *bridge);
>>>
>>> ?????/**
>>> ????? * @enable:
>>> ????? *
>>> ????? * This callback should enable the bridge. It is called right after
>>> ????? * the preceding element in the display pipe is enabled. If the
>>> ????? * preceding element is a bridge this means it's called after that
>>> ????? * bridge's @enable function. If the preceding element is a
>>> ????? * &drm_encoder it's called right after the encoder's
>>> ????? * &drm_encoder_helper_funcs.enable, &drm_encoder_helper_funcs.commit or
>>> ????? * &drm_encoder_helper_funcs.dpms hook.
>>> ????? *
>>> ????? * The bridge can assume that the display pipe (i.e. clocks and timing
>>> ????? * signals) feeding it is running when this callback is called. This
>>> ????? * callback must enable the display link feeding the next bridge in the
>>> ????? * chain if there is one.
>>> ????? *
>>> ????? * The @enable callback is optional.
>>> ????? *
>>> ????? * NOTE:
>>> ????? *
>>> ????? * This is deprecated, do not use!
>>> ????? * New drivers shall use &drm_bridge_funcs.atomic_enable.
>>> ????? */
>>> ?????void (*enable)(struct drm_bridge *bridge);
>>>
>>> => "The bridge must not enable the display link feeding the next bridge in the
>>> => chain (if there is one) when this callback is called."
>>>
>>> Additionally, you ask for something impossible because here is the init order
>>> fixed by the framework:
>>>
>>> [?? 10.753139] panel_bridge_atomic_pre_enable
>>> [?? 10.963505] mtk_dsi_bridge_atomic_pre_enable
>>> [?? 10.963518] mtk_dsi_bridge_atomic_enable
>>> [?? 10.963527] panel_bridge_atomic_enable
>>> [?? 10.963532] drm_panel_enable
>>>
>>> If panel want to use the DSI link in panel_bridge_atomic_pre_enable, nothing
>>> will happen and? you will get a timeout.
>>>
>>> So, IMHO, this patch make sense.
>>>
>>>>
>>>>> To solve that, use stk_panel_enable to enable the display link because
>>>>> it's called after the mtk_dsi_bridge_atomic_pre_enable which is power
>>>>> on the DSI.
>>>>>
>>>>> Signed-off-by: Alexandre Mergnat <amergnat at baylibre.com>
>>>>> ---
>>>>> ? .../gpu/drm/panel/panel-startek-kd070fhfid015.c??? | 25 +++++++++++++---------
>>>>> ? 1 file changed, 15 insertions(+), 10 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/panel/panel-startek-kd070fhfid015.c b/drivers/gpu/ 
>>>>> drm/panel/panel-startek-kd070fhfid015.c
>>>>> index c0c95355b7435..bc3c4038bf4f5 100644
>>>>> --- a/drivers/gpu/drm/panel/panel-startek-kd070fhfid015.c
>>>>> +++ b/drivers/gpu/drm/panel/panel-startek-kd070fhfid015.c
>>>>> @@ -135,19 +135,9 @@ static int stk_panel_prepare(struct drm_panel *panel)
>>>>> ????? gpiod_set_value(stk->enable_gpio, 1);
>>>>> ????? mdelay(20);
>>>>> ????? gpiod_set_value(stk->reset_gpio, 1);
>>>>> -??? mdelay(10);
>>>>> -??? ret = stk_panel_init(stk);
>>>>> -??? if (ret < 0)
>>>>> -??????? goto poweroff;
>>>>
>>>> Also, you're moving both init and set_display_on to the enable callback...
>>>> this is suboptimal.
>>>>
>>>> You should do the DrIC setup in .prepare() (can include SLEEP OUT), and then you
>>>> should have a .enable() callback that calls DISP ON, a .disable() callback that
>>>> calls DISP OFF, and .unprepare() that turns everything off.
>>>
>>> This is not what I understand from the pre_enable's definition above, and also
>>> the function call order by the framework. :)
>>>
>>>>
>>>> Cheers,
>>>> Angelo
>>>>
>>>>> -
>>>>> -??? ret = stk_panel_on(stk);
>>>>> -??? if (ret < 0)
>>>>> -??????? goto poweroff;
>>>>> ????? return 0;
>>>>> -poweroff:
>>>>> -??? regulator_disable(stk->supplies[POWER].consumer);
>>>>> ? iovccoff:
>>>>> ????? regulator_disable(stk->supplies[IOVCC].consumer);
>>>>> ????? gpiod_set_value(stk->reset_gpio, 0);
>>>>> @@ -156,6 +146,20 @@ static int stk_panel_prepare(struct drm_panel *panel)
>>>>> ????? return ret;
>>>>> ? }
>>>>> +static int stk_panel_enable(struct drm_panel *panel)
>>>>> +{
>>>>> +??? struct stk_panel *stk = to_stk_panel(panel);
>>>>> +??? int ret;
>>>>> +
>>>>> +??? ret = stk_panel_init(stk);
>>>>> +??? if (ret < 0)
>>>>> +??????? return ret;
>>>>> +
>>>>> +??? ret = stk_panel_on(stk);
>>>>> +
>>>>> +??? return ret;
>>>>> +}
>>>>> +
>>>>> ? static const struct drm_display_mode default_mode = {
>>>>> ????????? .clock = 163204,
>>>>> ????????? .hdisplay = 1200,
>>>>> @@ -239,6 +243,7 @@ drm_panel_create_dsi_backlight(struct mipi_dsi_device *dsi)
>>>>> ? }
>>>>> ? static const struct drm_panel_funcs stk_panel_funcs = {
>>>>> +??? .enable = stk_panel_enable,
>>>>> ????? .unprepare = stk_panel_unprepare,
>>>>> ????? .prepare = stk_panel_prepare,
>>>>> ????? .get_modes = stk_panel_get_modes,
>>>>>
>>>>
>>>>
>>>>
>>>
>>
> 

-- 
Regards,
Alexandre


From julien.massot at collabora.com  Fri May 16 07:12:12 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Fri, 16 May 2025 16:12:12 +0200
Subject: [PATCH v2 0/2] mt8188: Fix missing reset DT property
Message-ID: <20250516-dtb-check-mt8188-v2-0-fb60bef1b8e1@collabora.com>

Hi all,

This patch series addresses some issues found in the MediaTek MT8188 device tree
and its corresponding bindings:

The #reset-cells property was missing in the MT8188 clock controller binding and
device tree nodes. This causes DT validation errors.

Patch 1 updates the binding to declare #reset-cells as a valid property.
Patch 2 adds #reset-cells to all affected nodes in mt8188.dtsi.

To: kernel at collabora.com
To: Michael Turquette <mturquette at baylibre.com>
To: Stephen Boyd <sboyd at kernel.org>
To: Rob Herring <robh at kernel.org>
To: Krzysztof Kozlowski <krzk+dt at kernel.org>
To: Conor Dooley <conor+dt at kernel.org>
To: Matthias Brugger <matthias.bgg at gmail.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
To: Garmin Chang <garmin.chang at mediatek.com>
To: Friday Yang <friday.yang at mediatek.com>
Cc: Conor Dooley <conor.dooley at microchip.com>
Cc: linux-clk at vger.kernel.org
Cc: devicetree at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-mediatek at lists.infradead.org

Signed-off-by: Julien Massot <julien.massot at collabora.com>
---
Changes in v2:
- Change the wording for patch 1/2
- Drop the fix tag on patch 2/2
- Drop the former 3/3 patch in favour of another solution:
https://lore.kernel.org/all/20240911104327.123602-1-angelogioacchino.delregno at collabora.com
- Link to v1: https://lore.kernel.org/r/20250515-dtb-check-mt8188-v1-0-cda383cbeb4f at collabora.com

---
Julien Massot (2):
      dt-bindings: clock: mediatek: Add #reset-cells property for MT8188
      arm64: dts: mediatek: mt8188: Add missing #reset-cells property

 .../devicetree/bindings/clock/mediatek,mt8188-clock.yaml       |  3 +++
 arch/arm64/boot/dts/mediatek/mt8188.dtsi                       | 10 ++++++++++
 2 files changed, 13 insertions(+)
---
base-commit: bdd609656ff5573db9ba1d26496a528bdd297cf2
change-id: 20250515-dtb-check-mt8188-5af50d5d5c93

Best regards,
-- 
Julien Massot <julien.massot at collabora.com>



From julien.massot at collabora.com  Fri May 16 07:12:14 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Fri, 16 May 2025 16:12:14 +0200
Subject: [PATCH v2 2/2] arm64: dts: mediatek: mt8188: Add missing
 #reset-cells property
In-Reply-To: <20250516-dtb-check-mt8188-v2-0-fb60bef1b8e1@collabora.com>
References: <20250516-dtb-check-mt8188-v2-0-fb60bef1b8e1@collabora.com>
Message-ID: <20250516-dtb-check-mt8188-v2-2-fb60bef1b8e1@collabora.com>

The binding now require the '#reset-cells' property but the
devicetree has not been updated which trigger dtb-check errors.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: Julien Massot <julien.massot at collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 296090fbaf4953db8075f72073509b731dc41e51..dec6ce3e94e92c8e1e2c3680cb3584394d9058bd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -2647,36 +2647,42 @@ imgsys1_dip_top: clock-controller at 15110000 {
 			compatible = "mediatek,mt8188-imgsys1-dip-top";
 			reg = <0 0x15110000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		imgsys1_dip_nr: clock-controller at 15130000 {
 			compatible = "mediatek,mt8188-imgsys1-dip-nr";
 			reg = <0 0x15130000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		imgsys_wpe1: clock-controller at 15220000 {
 			compatible = "mediatek,mt8188-imgsys-wpe1";
 			reg = <0 0x15220000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		ipesys: clock-controller at 15330000 {
 			compatible = "mediatek,mt8188-ipesys";
 			reg = <0 0x15330000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		imgsys_wpe2: clock-controller at 15520000 {
 			compatible = "mediatek,mt8188-imgsys-wpe2";
 			reg = <0 0x15520000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		imgsys_wpe3: clock-controller at 15620000 {
 			compatible = "mediatek,mt8188-imgsys-wpe3";
 			reg = <0 0x15620000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		camsys: clock-controller at 16000000 {
@@ -2689,24 +2695,28 @@ camsys_rawa: clock-controller at 1604f000 {
 			compatible = "mediatek,mt8188-camsys-rawa";
 			reg = <0 0x1604f000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		camsys_yuva: clock-controller at 1606f000 {
 			compatible = "mediatek,mt8188-camsys-yuva";
 			reg = <0 0x1606f000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		camsys_rawb: clock-controller at 1608f000 {
 			compatible = "mediatek,mt8188-camsys-rawb";
 			reg = <0 0x1608f000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		camsys_yuvb: clock-controller at 160af000 {
 			compatible = "mediatek,mt8188-camsys-yuvb";
 			reg = <0 0x160af000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		ccusys: clock-controller at 17200000 {

-- 
2.49.0



From julien.massot at collabora.com  Fri May 16 07:12:13 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Fri, 16 May 2025 16:12:13 +0200
Subject: [PATCH v2 1/2] dt-bindings: clock: mediatek: Add #reset-cells
 property for MT8188
In-Reply-To: <20250516-dtb-check-mt8188-v2-0-fb60bef1b8e1@collabora.com>
References: <20250516-dtb-check-mt8188-v2-0-fb60bef1b8e1@collabora.com>
Message-ID: <20250516-dtb-check-mt8188-v2-1-fb60bef1b8e1@collabora.com>

The '#reset-cells' property is permitted for some of the MT8188
clock controllers, but not listed as a valid property.

Fixes: 9a5cd59640ac ("dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: Julien Massot <julien.massot at collabora.com>
---
 Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
index 2985c8c717d72888dd49f1f6249a9e2594d8a38d..5403242545ab12a7736ed4fbac26008aa955c724 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
@@ -52,6 +52,9 @@ properties:
   '#clock-cells':
     const: 1
 
+  '#reset-cells':
+    const: 1
+
 required:
   - compatible
   - reg

-- 
2.49.0



From julien.massot at collabora.com  Fri May 16 07:13:32 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Fri, 16 May 2025 16:13:32 +0200
Subject: [PATCH 2/3] arm64: dts: mediatek: mt8188: Add missing
 #reset-cells property
In-Reply-To: <b693991a-db50-4871-91a4-20d9859a2f43@collabora.com>
References: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>
	 <20250515-dtb-check-mt8188-v1-2-cda383cbeb4f@collabora.com>
	 <b693991a-db50-4871-91a4-20d9859a2f43@collabora.com>
Message-ID: <057041d03651f3e6af572f326c128c8aea217143.camel@collabora.com>

Hi Angelo,


On Thu, 2025-05-15 at 16:53 +0200, AngeloGioacchino Del Regno wrote:
> Il 15/05/25 15:31, Julien Massot ha scritto:
> > The binding now require the '#reset-cells' property but the
> > devicetree has not been updated which trigger dtb-check errors.
> > 
> > Fixes: 9a5cd59640ac ("dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188")
> 
> That's not really a fix though, so after you drop the Fixes tag.....
> 
> > Signed-off-by: Julien Massot <julien.massot at collabora.com>
> 
> ....you can get my:
> 
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

Thanks dropped the fix tag in the v2

Regards,
Julien


From julien.massot at collabora.com  Fri May 16 07:14:54 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Fri, 16 May 2025 16:14:54 +0200
Subject: [PATCH 1/3] dt-bindings: clock: mediatek: Add #reset-cells
 property for MT8188
In-Reply-To: <20250515-deploy-wiring-5829acc3d82e@spud>
References: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>
	 <20250515-dtb-check-mt8188-v1-1-cda383cbeb4f@collabora.com>
	 <20250515-playpen-dislodge-80245fb8b7a9@spud>
	 <cbd170a3-cbfe-4b4f-a059-efe33fed0e5d@collabora.com>
	 <20250515-deploy-wiring-5829acc3d82e@spud>
Message-ID: <dcc085b131ec0b8769630bee6ee89ca0b6eacc73.camel@collabora.com>


Hi Conor, Angelo,
On Thu, 2025-05-15 at 17:17 +0100, Conor Dooley wrote:
> On Thu, May 15, 2025 at 05:11:13PM +0200, AngeloGioacchino Del Regno wrote:
> > Il 15/05/25 17:03, Conor Dooley ha scritto:
> > > On Thu, May 15, 2025 at 03:31:43PM +0200, Julien Massot wrote:
> > > > The '#reset-cells' property is required for some of the MT8188
> > > > clock controllers, but not listed as a valid property.
> > > 
> > > "required for some" but not marked required on those platforms.
> > > Why not?
> > > 
> > 
> > Yeah now that I read that for the third time, the wording is a bit incorrect.
> > 
> > It's not "required", some clock controllers do have reset controllers, but it
> > is facultative to actually use the latter.
> 
> I don't think I've ever seen this word before.
> 
> > I'm not sure if the ones that do have reset controllers inside should have the
> > #reset-cells property as required...
> > 
> > Conor, what do you think?
> 
> If "required for some" in the OP was meant as "permitted for some",
> change the wording to that and it is fine.
Changed 'required' by 'permitted' in v2.

Thanks,
Julien


From julien.massot at collabora.com  Fri May 16 07:16:12 2025
From: julien.massot at collabora.com (Julien Massot)
Date: Fri, 16 May 2025 16:16:12 +0200
Subject: [PATCH 3/3] arm64: dts: mediatek: mt8188: gce: add missing
 'clock-names'
In-Reply-To: <89234201-9315-41f5-ab13-68272f62c53d@collabora.com>
References: <20250515-dtb-check-mt8188-v1-0-cda383cbeb4f@collabora.com>
	 <20250515-dtb-check-mt8188-v1-3-cda383cbeb4f@collabora.com>
	 <89234201-9315-41f5-ab13-68272f62c53d@collabora.com>
Message-ID: <2646b1358d1d141cbb5988a3bb2bbf4177f4ce4f.camel@collabora.com>

On Thu, 2025-05-15 at 16:52 +0200, AngeloGioacchino Del Regno wrote:
> Il 15/05/25 15:31, Julien Massot ha scritto:
> > The 'clock-names' property is required by the dt binding.
> > 
> 
> I just remembered something....
> 
> 
> ...care to respin this patch instead?
> https://lore.kernel.org/all/20240911104327.123602-1-angelogioacchino.delregno at collabora.com/
> 

Ok, we will resend this patch instead, I dropped the patch 3/3 in the v2.

Regards,
Julien


From kuba at kernel.org  Fri May 16 08:43:20 2025
From: kuba at kernel.org (Jakub Kicinski)
Date: Fri, 16 May 2025 08:43:20 -0700
Subject: [net-next v1] net: wwan: t7xx: Parameterize data plane RX BAT
 and FAG count
In-Reply-To: <20250515180858.2568d930@kernel.org>
References: <20250514104728.10869-1-jinjian.song@fibocom.com>
	<20250515180858.2568d930@kernel.org>
Message-ID: <20250516084320.66998caf@kernel.org>

On Fri, 16 May 2025 11:46:57 +0800 Jinjian Song wrote:
> >Module parameters are discouraged, they are pretty poor as an API since
> >they apply to all devices in the system. Can you describe what "frg"
> >and "bat" are ? One of the existing APIs likely covers them.
> >Please also describe the scope (are they per netdev or some sort of
> >device level params)?  
> 
> MTK t7xx data plane hardware use BAT (Buffer Address Table) and FRG (Fragment) BAT
> to describle and manager RX buffer, these buffers will apply for a fixed size after
> the driver probe, and accompany the life cycle of the driver.
> 
> On some platforms, especially those that use swiotlb to manager buffers, without
> changing the buffer pool provided by swiotlb, it's needed to adjust the buffers
> used by the driver to meet the requirements.
> So parameterize these buffers applicable to the MTK t7xx driver to facilitate
> different platforms to work with different configurations. 

Have you looked at
https://docs.kernel.org/networking/ethtool-netlink.html#rings-set 
?


From kuba at kernel.org  Fri May 16 08:48:42 2025
From: kuba at kernel.org (Jakub Kicinski)
Date: Fri, 16 May 2025 08:48:42 -0700
Subject: [net v1] net: wwan: t7xx: Fix napi rx poll issue
In-Reply-To: <20250515175251.58b5123f@kernel.org>
References: <20250515031743.246178-1-jinjian.song@fibocom.com>
	<20250515175251.58b5123f@kernel.org>
Message-ID: <20250516084842.26c80cb5@kernel.org>

On Fri, 16 May 2025 15:30:38 +0800 Jinjian Song wrote:
> It seems that a judgment is made every time ccmni_inst[x] is used in the driver,
> and the synchronization on the 2 way might have been done when NAPI triggers
> polling by napi_schedule and when WWAN trigger dellink. 

Synchronization is about ensuring that the condition validating
by the if() remains true for as long as necessary.
You need to wrap the read with READ_ONCE() and write with WRITE_ONCE().
The rest if fine because netdev unregister sync against NAPIs in flight.


From frank-w at public-files.de  Fri May 16 10:20:32 2025
From: frank-w at public-files.de (Frank Wunderlich)
Date: Fri, 16 May 2025 17:20:32 +0000
Subject: Aw: [net-next, PATCH v2] net: phy: mediatek: do not require syscon
 compatible for pio property
In-Reply-To: <20250510174933.154589-1-linux@fw-web.de>
References: <20250510174933.154589-1-linux@fw-web.de>
Message-ID: <trinity-925f0b56-c8b6-493e-8d13-e732b3e95f48-1747416032428@trinity-msg-rest-gmx-gmx-live-f4858f84-lcsp7>

Hi,

i noticed my patch is in state "under review" for 2 days now without any comment and i want to make sure, 
it is not missed somehow.
Imho it is a trivial patch (not much complex), unlike many other net patches :)

maybe it still has a chance to get into net-next.

regards Frank


From linux at fw-web.de  Fri May 16 11:01:32 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:32 +0200
Subject: [net-next, PATCH v2] net: phy: mediatek: do not require syscon compatible for pio property
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <20250516180147.10416-3-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Current implementation requires syscon compatible for pio property
which is used for driving the switch leds on mt7988.

Replace syscon_regmap_lookup_by_phandle with of_parse_phandle and
device_node_to_regmap to get the regmap already assigned by pinctrl
driver.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---

v2:
- out of RFC

---
 drivers/net/phy/mediatek/mtk-ge-soc.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediatek/mtk-ge-soc.c
index 175cf5239bba..21975ef946d5 100644
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -7,6 +7,7 @@
 #include <linux/pinctrl/consumer.h>
 #include <linux/phy.h>
 #include <linux/regmap.h>
+#include <linux/of.h>
 
 #include "../phylib.h"
 #include "mtk.h"
@@ -1319,6 +1320,7 @@ static int mt7988_phy_probe_shared(struct phy_device *phydev)
 {
 	struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
 	struct mtk_socphy_shared *shared = phy_package_get_priv(phydev);
+	struct device_node *pio_np;
 	struct regmap *regmap;
 	u32 reg;
 	int ret;
@@ -1336,7 +1338,13 @@ static int mt7988_phy_probe_shared(struct phy_device *phydev)
 	 * The 4 bits in TPBANK0 are kept as package shared data and are used to
 	 * set LED polarity for each of the LED0.
 	 */
-	regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
+	pio_np = of_parse_phandle(np, "mediatek,pio", 0);
+	if (!pio_np)
+		return -ENODEV;
+
+	regmap = device_node_to_regmap(pio_np);
+	of_node_put(pio_np);
+
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
-- 
2.43.0



From linux at fw-web.de  Fri May 16 11:01:33 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:33 +0200
Subject: [PATCH v2 02/14] dt-bindings: net: dsa: mediatek,mt7530: add dsa-port definition for mt7988
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <20250516180147.10416-4-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Add own dsa-port binding for SoC with internal switch where only phy-mode
'internal' is valid.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
Reviewed-by: Rob Herring (Arm) <robh at kernel.org>
---
 .../bindings/net/dsa/mediatek,mt7530.yaml          | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
index ea979bcae1d6..bb22c36749fc 100644
--- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
+++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
@@ -186,6 +186,18 @@ required:
   - reg
 
 $defs:
+  builtin-dsa-port:
+    patternProperties:
+      "^(ethernet-)?ports$":
+        patternProperties:
+          "^(ethernet-)?port@[0-6]$":
+            if:
+              required: [ ethernet ]
+            then:
+              properties:
+                phy-mode:
+                  const: internal
+
   mt7530-dsa-port:
     patternProperties:
       "^(ethernet-)?ports$":
@@ -292,7 +304,7 @@ allOf:
             - mediatek,mt7988-switch
             - airoha,en7581-switch
     then:
-      $ref: "#/$defs/mt7530-dsa-port"
+      $ref: "#/$defs/builtin-dsa-port"
       properties:
         gpio-controller: false
         mediatek,mcm: false
-- 
2.43.0



From linux at fw-web.de  Fri May 16 11:01:36 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:36 +0200
Subject: [PATCH v2 05/14] arm64: dts: mediatek: mt7988: move uart0 and spi1 pins to soc dtsi
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <20250516180147.10416-7-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

In order to use uart0 or spi1 there is only 1 possible pin definition
so move them to soc dtsi to reuse them in other boards and avoiding
conflict if defined twice.

Suggested-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi  | 14 --------------
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi      | 18 ++++++++++++++++++
 2 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index 37e541a98ee1..23b267cd47ac 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -328,13 +328,6 @@ mux {
 		};
 	};
 
-	uart0_pins: uart0-pins {
-		mux {
-			function = "uart";
-			groups =  "uart0";
-		};
-	};
-
 	snfi_pins: snfi-pins {
 		mux {
 			function = "flash";
@@ -356,13 +349,6 @@ mux {
 		};
 	};
 
-	spi1_pins: spi1-pins {
-		mux {
-			function = "spi";
-			groups = "spi1";
-		};
-	};
-
 	spi2_pins: spi2-pins {
 		mux {
 			function = "spi";
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 8c31935f4ab0..ab6fc09940b8 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -209,6 +209,20 @@ mux {
 						 "pcie_wake_n3_0";
 				};
 			};
+
+			spi1_pins: spi1-pins {
+				mux {
+					function = "spi";
+					groups = "spi1";
+				};
+			};
+
+			uart0_pins: uart0-pins {
+				mux {
+					function = "uart";
+					groups =  "uart0";
+				};
+			};
 		};
 
 		pwm: pwm at 10048000 {
@@ -244,6 +258,8 @@ serial0: serial at 11000000 {
 			clocks = <&topckgen CLK_TOP_UART_SEL>,
 				 <&infracfg CLK_INFRA_52M_UART0_CK>;
 			clock-names = "baud", "bus";
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_pins>;
 			status = "disabled";
 		};
 
@@ -338,6 +354,8 @@ spi1: spi at 11008000 {
 				      "hclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi1_pins>;
 			status = "disabled";
 		};
 
-- 
2.43.0



From linux at fw-web.de  Fri May 16 11:01:35 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:35 +0200
Subject: [PATCH v2 04/14] arm64: dts: mediatek: mt7988: add spi controllers
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <20250516180147.10416-6-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Add SPI controllers for mt7988.

Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 45 +++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 8f6d1dfae24a..8c31935f4ab0 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -311,6 +311,51 @@ i2c2: i2c at 11005000 {
 			status = "disabled";
 		};
 
+		spi0: spi at 11007000 {
+			compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";
+			reg = <0 0x11007000 0 0x100>;
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&topckgen CLK_TOP_MPLL_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg CLK_INFRA_104M_SPI0>,
+				 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk",
+				      "hclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi1: spi at 11008000 {
+			compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm";
+			reg = <0 0x11008000 0 0x100>;
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&topckgen CLK_TOP_MPLL_D2>,
+				 <&topckgen CLK_TOP_SPIM_MST_SEL>,
+				 <&infracfg CLK_INFRA_104M_SPI1>,
+				 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk",
+				      "hclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi2: spi at 11009000 {
+			compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";
+			reg = <0 0x11009000 0 0x100>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&topckgen CLK_TOP_MPLL_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
+				 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk",
+				      "hclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		lvts: lvts at 1100a000 {
 			compatible = "mediatek,mt7988-lvts-ap";
 			#thermal-sensor-cells = <1>;
-- 
2.43.0



From linux at fw-web.de  Fri May 16 11:01:34 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:34 +0200
Subject: [PATCH v2 03/14] dt-bindings: net: dsa: mediatek,mt7530: add internal mdio bus
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <20250516180147.10416-5-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Mt7988 buildin switch has own mdio bus where ge-phys are connected.
Add related property for this.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
v2:
- change from patternproperty to property
- add unevaluatedProperties and mediatek,pio subproperty
---
 .../devicetree/bindings/net/dsa/mediatek,mt7530.yaml   | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
index bb22c36749fc..1692adcedea3 100644
--- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
+++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
@@ -132,6 +132,16 @@ properties:
       See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for
       details for the regulator setup on these boards.
 
+  mdio:
+    $ref: /schemas/net/mdio.yaml#
+    unevaluatedProperties: false
+
+    properties:
+      mediatek,pio:
+        $ref: /schemas/types.yaml#/definitions/phandle
+        description:
+          Phandle pointing to the mediatek pinctrl node.
+
   mediatek,mcm:
     type: boolean
     description:
-- 
2.43.0



From linux at fw-web.de  Fri May 16 11:01:31 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:31 +0200
Subject: [PATCH v2 01/14] dt-bindings: net: mediatek,net: update for mt7988
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <20250516180147.10416-2-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Update binding for mt7988 which has 3 gmac and 2 reg items.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
v2:
- change reg to list of items
---
 .../devicetree/bindings/net/mediatek,net.yaml          | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml
index 9e02fd80af83..e5dc35cfe4e4 100644
--- a/Documentation/devicetree/bindings/net/mediatek,net.yaml
+++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml
@@ -28,7 +28,10 @@ properties:
       - ralink,rt5350-eth
 
   reg:
-    maxItems: 1
+    items:
+      - description: Register for accessing the MACs.
+      - description: SoC internal SRAM used for DMA operations.
+    minItems: 1
 
   clocks:
     minItems: 2
@@ -381,8 +384,11 @@ allOf:
             - const: xgp2
             - const: xgp3
 
+        reg:
+          minItems: 2
+
 patternProperties:
-  "^mac@[0-1]$":
+  "^mac@[0-2]$":
     type: object
     unevaluatedProperties: false
     allOf:
-- 
2.43.0



From linux at fw-web.de  Fri May 16 11:01:39 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:39 +0200
Subject: [PATCH v2 08/14] arm64: dts: mediatek: mt7988: add basic ethernet-nodes
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <20250516180147.10416-10-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Add basic ethernet related nodes.

Mac1+2 needs pcs (sgmii+usxgmii) to work correctly which will be linked
later when driver is merged.

Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 124 +++++++++++++++++++++-
 1 file changed, 121 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 029699e4eb02..aa0947a555aa 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -680,7 +680,28 @@ xphyu3port0: usb-phy at 11e13000 {
 			};
 		};
 
-		clock-controller at 11f40000 {
+		xfi_tphy0: phy at 11f20000 {
+			compatible = "mediatek,mt7988-xfi-tphy";
+			reg = <0 0x11f20000 0 0x10000>;
+			resets = <&watchdog 14>;
+			clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
+				 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
+			clock-names = "xfipll", "topxtal";
+			mediatek,usxgmii-performance-errata;
+			#phy-cells = <0>;
+		};
+
+		xfi_tphy1: phy at 11f30000 {
+			compatible = "mediatek,mt7988-xfi-tphy";
+			reg = <0 0x11f30000 0 0x10000>;
+			resets = <&watchdog 15>;
+			clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
+				 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
+			clock-names = "xfipll", "topxtal";
+			#phy-cells = <0>;
+		};
+
+		xfi_pll: clock-controller at 11f40000 {
 			compatible = "mediatek,mt7988-xfi-pll";
 			reg = <0 0x11f40000 0 0x1000>;
 			resets = <&watchdog 16>;
@@ -714,19 +735,116 @@ phy_calibration_p3: calib at 97c {
 			};
 		};
 
-		clock-controller at 15000000 {
+		ethsys: clock-controller at 15000000 {
 			compatible = "mediatek,mt7988-ethsys", "syscon";
 			reg = <0 0x15000000 0 0x1000>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
 
-		clock-controller at 15031000 {
+		ethwarp: clock-controller at 15031000 {
 			compatible = "mediatek,mt7988-ethwarp";
 			reg = <0 0x15031000 0 0x1000>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
+
+		eth: ethernet at 15100000 {
+			compatible = "mediatek,mt7988-eth";
+			reg = <0 0x15100000 0 0x80000>,
+			      <0 0x15400000 0 0x200000>;
+			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ethsys CLK_ETHDMA_CRYPT0_EN>,
+				 <&ethsys CLK_ETHDMA_FE_EN>,
+				 <&ethsys CLK_ETHDMA_GP2_EN>,
+				 <&ethsys CLK_ETHDMA_GP1_EN>,
+				 <&ethsys CLK_ETHDMA_GP3_EN>,
+				 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
+				 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
+				 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
+				 <&ethsys CLK_ETHDMA_ESW_EN>,
+				 <&topckgen CLK_TOP_ETH_GMII_SEL>,
+				 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
+				 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
+				 <&topckgen CLK_TOP_ETH_SYS_SEL>,
+				 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
+				 <&topckgen CLK_TOP_ETH_MII_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_WARP_SEL>,
+				 <&ethsys CLK_ETHDMA_XGP1_EN>,
+				 <&ethsys CLK_ETHDMA_XGP2_EN>,
+				 <&ethsys CLK_ETHDMA_XGP3_EN>;
+			clock-names = "crypto", "fe", "gp2", "gp1",
+				      "gp3",
+				      "ethwarp_wocpu2", "ethwarp_wocpu1",
+				      "ethwarp_wocpu0", "esw", "top_eth_gmii_sel",
+				      "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
+				      "top_eth_sys_sel", "top_eth_xgmii_sel",
+				      "top_eth_mii_sel", "top_netsys_sel",
+				      "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
+				      "top_netsys_sync_250m_sel",
+				      "top_netsys_ppefb_250m_sel",
+				      "top_netsys_warp_sel","xgp1", "xgp2", "xgp3";
+			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
+					  <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
+					  <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
+					  <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
+					  <&topckgen CLK_TOP_SGM_0_SEL>,
+					  <&topckgen CLK_TOP_SGM_1_SEL>;
+			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
+						 <&topckgen CLK_TOP_NET1PLL_D4>,
+						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
+						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
+						 <&apmixedsys CLK_APMIXED_SGMPLL>,
+						 <&apmixedsys CLK_APMIXED_SGMPLL>;
+			mediatek,ethsys = <&ethsys>;
+			mediatek,infracfg = <&topmisc>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gmac0: mac at 0 {
+				compatible = "mediatek,eth-mac";
+				reg = <0>;
+				phy-mode = "internal";
+
+				fixed-link {
+					speed = <10000>;
+					full-duplex;
+					pause;
+				};
+			};
+
+			gmac1: mac at 1 {
+				compatible = "mediatek,eth-mac";
+				reg = <1>;
+				status = "disabled";
+			};
+
+			gmac2: mac at 2 {
+				compatible = "mediatek,eth-mac";
+				reg = <2>;
+				status = "disabled";
+			};
+
+			mdio_bus: mdio-bus {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				/* internal 2.5G PHY */
+				int_2p5g_phy: ethernet-phy at f {
+					reg = <15>;
+					compatible = "ethernet-phy-ieee802.3-c45";
+					phy-mode = "internal";
+				};
+			};
+		};
 	};
 
 	thermal-zones {
-- 
2.43.0



From linux at fw-web.de  Fri May 16 11:01:38 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:38 +0200
Subject: [PATCH v2 07/14] arm64: dts: mediatek: mt7988: add phy calibration efuse subnodes
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <20250516180147.10416-9-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

MT7988 contains buildin mt753x switch which needs calibration data from
efuse.

Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 64466acb0e71..029699e4eb02 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -696,6 +696,22 @@ efuse at 11f50000 {
 			lvts_calibration: calib at 918 {
 				reg = <0x918 0x28>;
 			};
+
+			phy_calibration_p0: calib at 940 {
+				reg = <0x940 0x10>;
+			};
+
+			phy_calibration_p1: calib at 954 {
+				reg = <0x954 0x10>;
+			};
+
+			phy_calibration_p2: calib at 968 {
+				reg = <0x968 0x10>;
+			};
+
+			phy_calibration_p3: calib at 97c {
+				reg = <0x97c 0x10>;
+			};
 		};
 
 		clock-controller at 15000000 {
-- 
2.43.0



From linux at fw-web.de  Fri May 16 11:01:30 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:30 +0200
Subject: [PATCH v2 00/14] further mt7988 devicetree work
Message-ID: <20250516180147.10416-1-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

This series continues mt7988 devicetree work

- Add SPI with BPI-R4 nand to reach eMMC
- Add thermal protection (fan+cooling-points)
- Extend cpu frequency scaling with CCI
- Basic network-support (ethernet controller + builtin switch + SFP Cages)

depencies (i hope this list is complete and latest patches/series linked):

"Add Bananapi R4 variants and add xsphy" (reviewed, partially applied):
https://patchwork.kernel.org/project/linux-mediatek/list/?series=955733

"net: phy: mediatek: do not require syscon compatible for pio property":
https://patchwork.kernel.org/project/netdevbpf/patch/20250510174933.154589-1-linux at fw-web.de/
for phy led function (RFC not yet reviewed, resent without RFC)

for 2.5g phy function (currently disabled):
- net: ethernet: mtk_eth_soc: add support for MT7988 internal 2.5G PHY (already merged to 6.15-net-next)
- net: phy: mediatek: add driver for built-in 2.5G ethernet PHY on MT7988
  https://patchwork.kernel.org/project/netdevbpf/patch/20250516102327.2014531-3-SkyLake.Huang at mediatek.com/ (v4)

for SFP-Function (macs currently disabled):

PCS clearance which is a 1.5 year discussion currently ongoing

e.g. something like this (one of):
* https://patchwork.kernel.org/project/netdevbpf/patch/20250511201250.3789083-4-ansuelsmth at gmail.com/ (v4)
* https://patchwork.kernel.org/project/netdevbpf/patch/20250512161013.731955-4-sean.anderson at linux.dev/ (v4)
* https://patchwork.kernel.org/project/netdevbpf/patch/ba4e359584a6b3bc4b3470822c42186d5b0856f9.1721910728.git.daniel at makrotopia.org/

full usxgmii driver:
https://patchwork.kernel.org/project/netdevbpf/patch/07845ec900ba41ff992875dce12c622277592c32.1702352117.git.daniel at makrotopia.org/

first PCS-discussion is here:
https://patchwork.kernel.org/project/netdevbpf/patch/8aa905080bdb6760875d62cb3b2b41258837f80e.1702352117.git.daniel at makrotopia.org/

and then dts nodes for sgmiisys+usxgmii

when above depencies are solved the mac1/2 can be enabled and 2.5G phy/SFP slots will work.

changes:
v2:
  - change reg to list of items in eth binding
  - changed mt7530 binding:
    - unevaluatedProperties=false
    - mediatek,pio subproperty
    - from patternProperty to property
  - board specific properties like led function and labels moved to bpi-r4 dtsi

Frank Wunderlich (14):
  dt-bindings: net: mediatek,net: update for mt7988
  dt-bindings: net: dsa: mediatek,mt7530: add dsa-port definition for
    mt7988
  dt-bindings: net: dsa: mediatek,mt7530: add internal mdio bus
  arm64: dts: mediatek: mt7988: add spi controllers
  arm64: dts: mediatek: mt7988: move uart0 and spi1 pins to soc dtsi
  arm64: dts: mediatek: mt7988: add cci node
  arm64: dts: mediatek: mt7988: add phy calibration efuse subnodes
  arm64: dts: mediatek: mt7988: add basic ethernet-nodes
  arm64: dts: mediatek: mt7988: add switch node
  arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and coolingmaps
  arm64: dts: mediatek: mt7988a-bpi-r4: configure spi-nodes
  arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply for cci
  arm64: dts: mediatek: mt7988a-bpi-r4: add sfp cages and link to gmac
  arm64: dts: mediatek: mt7988a-bpi-r4: configure switch phys and leds

 .../bindings/net/dsa/mediatek,mt7530.yaml     |  24 +-
 .../devicetree/bindings/net/mediatek,net.yaml |  10 +-
 .../mediatek/mt7988a-bananapi-bpi-r4-2g5.dts  |  11 +
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts  |  18 +
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 158 ++++++-
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi     | 389 +++++++++++++++++-
 6 files changed, 590 insertions(+), 20 deletions(-)

-- 
2.43.0



From linux at fw-web.de  Fri May 16 11:01:41 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:41 +0200
Subject: [PATCH v2 10/14] arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and coolingmaps
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <20250516180147.10416-12-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Add Fan and cooling maps for Bananapi-R4 board.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
v2: fix typo
---
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index 23b267cd47ac..c6f84de82a4d 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -12,6 +12,15 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		/* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */
+		cooling-levels = <0 80 128 255>;
+		#cooling-cells = <2>;
+		pwms = <&pwm 0 50000>;
+		status = "okay";
+	};
+
 	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
@@ -73,6 +82,26 @@ cpu_trip_active_low: active-low {
 			type = "active";
 		};
 	};
+
+	cooling-maps {
+		map-cpu-active-high {
+			/* active: set fan to cooling level 2 */
+			cooling-device = <&fan 3 3>;
+			trip = <&cpu_trip_active_high>;
+		};
+
+		map-cpu-active-med {
+			/* active: set fan to cooling level 1 */
+			cooling-device = <&fan 2 2>;
+			trip = <&cpu_trip_active_med>;
+		};
+
+		map-cpu-active-low {
+			/* active: set fan to cooling level 0 */
+			cooling-device = <&fan 1 1>;
+			trip = <&cpu_trip_active_low>;
+		};
+	};
 };
 
 &i2c0 {
-- 
2.43.0



From linux at fw-web.de  Fri May 16 11:01:44 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:44 +0200
Subject: [PATCH v2 13/14] arm64: dts: mediatek: mt7988a-bpi-r4: add sfp cages and link to gmac
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <20250516180147.10416-15-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Add SFP cages to Bananapi-R4 board. The 2.5g phy variant only contains the
wan-SFP, so add this to common dtsi and the lan-sfp only to the dual-SFP
variant.

Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 .../mediatek/mt7988a-bananapi-bpi-r4-2g5.dts   | 11 +++++++++++
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts   | 18 ++++++++++++++++++
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi  | 18 ++++++++++++++++++
 3 files changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts
index 53de9c113f60..574ac1b853a6 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts
@@ -9,3 +9,14 @@ / {
 	model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)";
 	chassis-type = "embedded";
 };
+
+&gmac1 {
+	phy-mode = "internal";
+	phy-connection-type = "internal";
+	phy = <&int_2p5g_phy>;
+};
+
+&int_2p5g_phy {
+	pinctrl-names = "i2p5gbe-led";
+	pinctrl-0 = <&i2p5gbe_led0_pins>;
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
index 36bd1ef2efab..3136dc4ba4cc 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -8,6 +8,24 @@ / {
 	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
 	model = "Banana Pi BPI-R4 (2x SFP+)";
 	chassis-type = "embedded";
+
+	/* SFP2 cage (LAN) */
+	sfp2: sfp2 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp2>;
+		los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>;
+		tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
+		rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
+		maximum-power-milliwatt = <3000>;
+	};
+};
+
+&gmac1 {
+	sfp = <&sfp2>;
+	managed = "in-band-status";
+	phy-mode = "usxgmii";
 };
 
 &pca9545 {
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index afa9e3b2b16a..d40c8dbcd18e 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -38,6 +38,18 @@ reg_3p3v: regulator-3p3v {
 		regulator-boot-on;
 		regulator-always-on;
 	};
+
+	/* SFP1 cage (WAN) */
+	sfp1: sfp1 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp1>;
+		los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
+		tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
+		rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
+		maximum-power-milliwatt = <3000>;
+	};
 };
 
 &cci {
@@ -108,6 +120,12 @@ map-cpu-active-low {
 	};
 };
 
+&gmac2 {
+	sfp = <&sfp1>;
+	managed = "in-band-status";
+	phy-mode = "usxgmii";
+};
+
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_pins>;
-- 
2.43.0



From linux at fw-web.de  Fri May 16 11:01:37 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:37 +0200
Subject: [PATCH v2 06/14] arm64: dts: mediatek: mt7988: add cci node
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <20250516180147.10416-8-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Add cci devicetree node for cpu frequency scaling.

Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index ab6fc09940b8..64466acb0e71 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -12,6 +12,35 @@ / {
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	cci: cci {
+		compatible = "mediatek,mt8183-cci";
+		clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
+			 <&topckgen CLK_TOP_XTAL>;
+		clock-names = "cci", "intermediate";
+		operating-points-v2 = <&cci_opp>;
+	};
+
+	cci_opp: opp-table-cci {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp-480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <850000>;
+		};
+		opp-660000000 {
+			opp-hz = /bits/ 64 <660000000>;
+			opp-microvolt = <850000>;
+		};
+		opp-900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = <850000>;
+		};
+		opp-1080000000 {
+			opp-hz = /bits/ 64 <1080000000>;
+			opp-microvolt = <900000>;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -25,6 +54,7 @@ cpu0: cpu at 0 {
 				 <&topckgen CLK_TOP_XTAL>;
 			clock-names = "cpu", "intermediate";
 			operating-points-v2 = <&cluster0_opp>;
+			mediatek,cci = <&cci>;
 		};
 
 		cpu1: cpu at 1 {
@@ -36,6 +66,7 @@ cpu1: cpu at 1 {
 				 <&topckgen CLK_TOP_XTAL>;
 			clock-names = "cpu", "intermediate";
 			operating-points-v2 = <&cluster0_opp>;
+			mediatek,cci = <&cci>;
 		};
 
 		cpu2: cpu at 2 {
@@ -47,6 +78,7 @@ cpu2: cpu at 2 {
 				 <&topckgen CLK_TOP_XTAL>;
 			clock-names = "cpu", "intermediate";
 			operating-points-v2 = <&cluster0_opp>;
+			mediatek,cci = <&cci>;
 		};
 
 		cpu3: cpu at 3 {
@@ -58,6 +90,7 @@ cpu3: cpu at 3 {
 				 <&topckgen CLK_TOP_XTAL>;
 			clock-names = "cpu", "intermediate";
 			operating-points-v2 = <&cluster0_opp>;
+			mediatek,cci = <&cci>;
 		};
 
 		cluster0_opp: opp-table-0 {
-- 
2.43.0



From linux at fw-web.de  Fri May 16 11:01:42 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:42 +0200
Subject: [PATCH v2 11/14] arm64: dts: mediatek: mt7988a-bpi-r4: configure spi-nodes
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <20250516180147.10416-13-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Configure and enable SPI nodes on Bananapi R4 board.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index c6f84de82a4d..81ba045e0e0e 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -401,6 +401,38 @@ &serial0 {
 	status = "okay";
 };
 
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+	status = "okay";
+
+	spi_nand: flash at 0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&spi1 {
+	status = "okay";
+};
+
+&spi_nand {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition at 0 {
+			label = "bl2";
+			reg = <0x0 0x200000>;
+			read-only;
+		};
+	};
+};
+
 &ssusb1 {
 	status = "okay";
 };
-- 
2.43.0



From linux at fw-web.de  Fri May 16 11:01:40 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:40 +0200
Subject: [PATCH v2 09/14] arm64: dts: mediatek: mt7988: add switch node
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <20250516180147.10416-11-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Add mt7988 builtin mt753x switch nodes.

Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
v2:
- drop labels and led-function too (have to be in board)
---
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 153 ++++++++++++++++++++++
 1 file changed, 153 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index aa0947a555aa..f738a025b623 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -742,6 +742,159 @@ ethsys: clock-controller at 15000000 {
 			#reset-cells = <1>;
 		};
 
+		switch: switch at 15020000 {
+			compatible = "mediatek,mt7988-switch";
+			reg = <0 0x15020000 0 0x8000>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				gsw_port0: port at 0 {
+					reg = <0>;
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy0>;
+				};
+
+				gsw_port1: port at 1 {
+					reg = <1>;
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy1>;
+				};
+
+				gsw_port2: port at 2 {
+					reg = <2>;
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy2>;
+				};
+
+				gsw_port3: port at 3 {
+					reg = <3>;
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy3>;
+				};
+
+				port at 6 {
+					reg = <6>;
+					ethernet = <&gmac0>;
+					phy-mode = "internal";
+
+					fixed-link {
+						speed = <10000>;
+						full-duplex;
+						pause;
+					};
+				};
+			};
+
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				mediatek,pio = <&pio>;
+
+				gsw_phy0: ethernet-phy at 0 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <0>;
+					interrupts = <0>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p0>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy0_led0: led at 0 {
+							reg = <0>;
+							status = "disabled";
+						};
+
+						gsw_phy0_led1: led at 1 {
+							reg = <1>;
+							status = "disabled";
+						};
+					};
+				};
+
+				gsw_phy1: ethernet-phy at 1 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <1>;
+					interrupts = <1>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p1>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy1_led0: led at 0 {
+							reg = <0>;
+							status = "disabled";
+						};
+
+						gsw_phy1_led1: led at 1 {
+							reg = <1>;
+							status = "disabled";
+						};
+					};
+				};
+
+				gsw_phy2: ethernet-phy at 2 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <2>;
+					interrupts = <2>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p2>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy2_led0: led at 0 {
+							reg = <0>;
+							status = "disabled";
+						};
+
+						gsw_phy2_led1: led at 1 {
+							reg = <1>;
+							status = "disabled";
+						};
+					};
+				};
+
+				gsw_phy3: ethernet-phy at 3 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <3>;
+					interrupts = <3>;
+					phy-mode = "internal";
+					nvmem-cells = <&phy_calibration_p3>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy3_led0: led at 0 {
+							reg = <0>;
+							status = "disabled";
+						};
+
+						gsw_phy3_led1: led at 1 {
+							reg = <1>;
+							status = "disabled";
+						};
+					};
+				};
+			};
+		};
+
 		ethwarp: clock-controller at 15031000 {
 			compatible = "mediatek,mt7988-ethwarp";
 			reg = <0 0x15031000 0 0x1000>;
-- 
2.43.0



From linux at fw-web.de  Fri May 16 11:01:45 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:45 +0200
Subject: [PATCH v2 14/14] arm64: dts: mediatek: mt7988a-bpi-r4: configure switch phys and leds
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <20250516180147.10416-16-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Assign pinctrl to switch phys and leds.

Signed-off-by: Daniel Golle <daniel at makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
v2:
- add labels and led-function and include after dropping from soc dtsi
---
 .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 61 +++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index d40c8dbcd18e..9e4ae4c4ea17 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+#include <dt-bindings/leds/common.h>
 
 #include "mt7988a.dtsi"
 
@@ -126,6 +127,66 @@ &gmac2 {
 	phy-mode = "usxgmii";
 };
 
+&gsw_phy0 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe0_led0_pins>;
+};
+
+&gsw_phy0_led0 {
+	status = "okay";
+	function = LED_FUNCTION_WAN;
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_port0 {
+	label = "wan";
+};
+
+&gsw_phy1 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe1_led0_pins>;
+};
+
+&gsw_phy1_led0 {
+	status = "okay";
+	function = LED_FUNCTION_LAN;
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_port1 {
+	label = "lan1";
+};
+
+&gsw_phy2 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe2_led0_pins>;
+};
+
+&gsw_phy2_led0 {
+	status = "okay";
+	function = LED_FUNCTION_LAN;
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_port2 {
+	label = "lan2";
+};
+
+&gsw_phy3 {
+	pinctrl-names = "gbe-led";
+	function = LED_FUNCTION_LAN;
+	pinctrl-0 = <&gbe3_led0_pins>;
+};
+
+&gsw_phy3_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_port3 {
+	label = "lan3";
+};
+
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_pins>;
-- 
2.43.0



From linux at fw-web.de  Fri May 16 11:01:43 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:01:43 +0200
Subject: [PATCH v2 12/14] arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply for cci
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <20250516180147.10416-14-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

CCI requires proc-supply. Add it on board level.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index 81ba045e0e0e..afa9e3b2b16a 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -40,6 +40,10 @@ reg_3p3v: regulator-3p3v {
 	};
 };
 
+&cci {
+	proc-supply = <&rt5190_buck3>;
+};
+
 &cpu0 {
 	proc-supply = <&rt5190_buck3>;
 };
-- 
2.43.0



From broonie at kernel.org  Fri May 16 11:09:00 2025
From: broonie at kernel.org (Mark Brown)
Date: Fri, 16 May 2025 19:09:00 +0100
Subject: [PATCH] ASoC: soc-utils: Check string pointer validity in
 snd_soc_dlc_is_dummy()
In-Reply-To: <20250516050549.407133-1-wenst@chromium.org>
References: <20250516050549.407133-1-wenst@chromium.org>
Message-ID: <174741894022.384649.9583972742635774457.b4-ty@kernel.org>

On Fri, 16 May 2025 13:05:48 +0800, Chen-Yu Tsai wrote:
> In the recently added snd_soc_dlc_is_dummy(), the helper uses the .name
> and .dai_name fields without checking their validity.
> 
> For .name, this field is NULL if the component is matched by .of_node
> instead. In fact, only one of these fields may be set. This caused a
> NULL pointer dereference on MediaTek MT8195 and MT8188 platforms with
> the subsequent conversion to snd_soc_dlc_is_dummy() in their machine
> drivers. The codecs are all matches through the device tree, so their
> .name fields are empty.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[1/1] ASoC: soc-utils: Check string pointer validity in snd_soc_dlc_is_dummy()
      commit: 628479afc7a157bca3430a75e759ed06c1a81c66

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark



From frank-w at public-files.de  Fri May 16 11:08:47 2025
From: frank-w at public-files.de (Frank Wunderlich)
Date: Fri, 16 May 2025 20:08:47 +0200
Subject: =?US-ASCII?Q?Re=3A_=5Bnet-next=2C_PATCH_v2?=
 =?US-ASCII?Q?=5D_net=3A_phy=3A_mediatek=3A_do?=
 =?US-ASCII?Q?_not_require_syscon_compatible_for_pio_property?=
In-Reply-To: <20250516180147.10416-3-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de> <20250516180147.10416-3-linux@fw-web.de>
Message-ID: <D997C4DB-1B03-4AFD-B48C-BFA19AB6194D@public-files.de>

Sorry, resent it by accident while sending v2 of my dts series.
regards Frank


From horms at kernel.org  Fri May 16 13:16:06 2025
From: horms at kernel.org (Simon Horman)
Date: Fri, 16 May 2025 21:16:06 +0100
Subject: [PATCH v3 1/4] net: airoha: Fix an error handling path in
 airoha_alloc_gdm_port()
In-Reply-To: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <20250516201606.GH3339421@horms.kernel.org>

On Thu, May 15, 2025 at 09:59:35PM +0200, Christophe JAILLET wrote:
> If register_netdev() fails, the error handling path of the probe will not
> free the memory allocated by the previous airoha_metadata_dst_alloc() call
> because port->dev->reg_state will not be NETREG_REGISTERED.
> 
> So, an explicit airoha_metadata_dst_free() call is needed in this case to
> avoid a memory leak.
> 
> Fixes: af3cf757d5c9 ("net: airoha: Move DSA tag in DMA descriptor")
> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
> ---
> Changes in v3:
>   - None
> 
> Changes in v2:
>   - New patch
> v2: https://lore.kernel.org/all/5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet at wanadoo.fr/
> 
> Compile tested only.

Reviewed-by: Simon Horman <horms at kernel.org>



From horms at kernel.org  Fri May 16 13:16:25 2025
From: horms at kernel.org (Simon Horman)
Date: Fri, 16 May 2025 21:16:25 +0100
Subject: [PATCH v3 2/4] net: airoha: Fix an error handling path in
 airoha_probe()
In-Reply-To: <47910951a3fa3c3bd2a942210e821d9301362128.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
 <47910951a3fa3c3bd2a942210e821d9301362128.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <20250516201625.GI3339421@horms.kernel.org>

On Thu, May 15, 2025 at 09:59:36PM +0200, Christophe JAILLET wrote:
> If an error occurs after a successful airoha_hw_init() call,
> airoha_ppe_deinit() needs to be called as already done in the remove
> function.
> 
> Fixes: 00a7678310fe ("net: airoha: Introduce flowtable offload support")
> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>

Reviewed-by: Simon Horman <horms at kernel.org>



From horms at kernel.org  Fri May 16 13:16:48 2025
From: horms at kernel.org (Simon Horman)
Date: Fri, 16 May 2025 21:16:48 +0100
Subject: [PATCH v3 4/4] net: airoha: Use dev_err_probe()
In-Reply-To: <bb64aa1ea0205329c377ad32dde46cdf5c232db9.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
 <bb64aa1ea0205329c377ad32dde46cdf5c232db9.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <20250516201648.GJ3339421@horms.kernel.org>

On Thu, May 15, 2025 at 09:59:38PM +0200, Christophe JAILLET wrote:
> Use dev_err_probe() to slightly simplify the code.
> It is less verbose, more informational and makes error logging more
> consistent in the probe.
> 
> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>

Reviewed-by: Simon Horman <horms at kernel.org>



From horms at kernel.org  Fri May 16 13:17:11 2025
From: horms at kernel.org (Simon Horman)
Date: Fri, 16 May 2025 21:17:11 +0100
Subject: [PATCH v3 1/4] net: airoha: Fix an error handling path in
 airoha_alloc_gdm_port()
In-Reply-To: <aCZZyDvp-TZ7AFwS@lore-desk>
References: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
 <aCZZyDvp-TZ7AFwS@lore-desk>
Message-ID: <20250516201711.GK3339421@horms.kernel.org>

On Thu, May 15, 2025 at 11:16:56PM +0200, Lorenzo Bianconi wrote:
> > If register_netdev() fails, the error handling path of the probe will not
> > free the memory allocated by the previous airoha_metadata_dst_alloc() call
> > because port->dev->reg_state will not be NETREG_REGISTERED.
> > 
> > So, an explicit airoha_metadata_dst_free() call is needed in this case to
> > avoid a memory leak.
> > 
> > Fixes: af3cf757d5c9 ("net: airoha: Move DSA tag in DMA descriptor")
> > Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
> 
> Acked-by: Lorenzo Bianconi <lorenzo at kernel.org>

Reviewed-by: Simon Horman <horms at kernel.org>




From horms at kernel.org  Fri May 16 13:21:49 2025
From: horms at kernel.org (Simon Horman)
Date: Fri, 16 May 2025 21:21:49 +0100
Subject: [PATCH v3 1/4] net: airoha: Fix an error handling path in
 airoha_alloc_gdm_port()
In-Reply-To: <20250516201606.GH3339421@horms.kernel.org>
References: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
 <20250516201606.GH3339421@horms.kernel.org>
Message-ID: <20250516202149.GL3339421@horms.kernel.org>

On Fri, May 16, 2025 at 09:16:13PM +0100, Simon Horman wrote:
> On Thu, May 15, 2025 at 09:59:35PM +0200, Christophe JAILLET wrote:
> > If register_netdev() fails, the error handling path of the probe will not
> > free the memory allocated by the previous airoha_metadata_dst_alloc() call
> > because port->dev->reg_state will not be NETREG_REGISTERED.
> > 
> > So, an explicit airoha_metadata_dst_free() call is needed in this case to
> > avoid a memory leak.
> > 
> > Fixes: af3cf757d5c9 ("net: airoha: Move DSA tag in DMA descriptor")
> > Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
> > ---
> > Changes in v3:
> >   - None
> > 
> > Changes in v2:
> >   - New patch
> > v2: https://lore.kernel.org/all/5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet at wanadoo.fr/
> > 
> > Compile tested only.
> 
> Reviewed-by: Simon Horman <horms at kernel.org>

Sorry, I was a little too hasty.

This patch looks good to me, but as this is a fix for change
present in net it should be targeted at net.

  Subject: [PATCH v4 net] ...

And it should be split out from the patchset comprising the remaining
patches in this series, which appear to be clean-ups (or at least not
but fixes). This rump patch-set should be targeted at net-next.
And ideally, IMHO, have a cover letter.

  Subject: [PATCH v4 net-next 0/3] ...

Thanks!

-- 
pw-bot: changes-requested


From patchwork-bot+netdevbpf at kernel.org  Fri May 16 15:50:37 2025
From: patchwork-bot+netdevbpf at kernel.org (patchwork-bot+netdevbpf at kernel.org)
Date: Fri, 16 May 2025 22:50:37 +0000
Subject: [net-next,
 PATCH v2] net: phy: mediatek: do not require syscon compatible for pio
 property
In-Reply-To: <20250510174933.154589-1-linux@fw-web.de>
References: <20250510174933.154589-1-linux@fw-web.de>
Message-ID: <174743583700.4084431.5953049222658087870.git-patchwork-notify@kernel.org>

Hello:

This patch was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba at kernel.org>:

On Sat, 10 May 2025 19:49:32 +0200 you wrote:
> From: Frank Wunderlich <frank-w at public-files.de>
> 
> Current implementation requires syscon compatible for pio property
> which is used for driving the switch leds on mt7988.
> 
> Replace syscon_regmap_lookup_by_phandle with of_parse_phandle and
> device_node_to_regmap to get the regmap already assigned by pinctrl
> driver.
> 
> [...]

Here is the summary with links:
  - [net-next,v2] net: phy: mediatek: do not require syscon compatible for pio property
    https://git.kernel.org/netdev/net-next/c/15d7b3dfafa9

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html




From kuba at kernel.org  Fri May 16 16:31:05 2025
From: kuba at kernel.org (Jakub Kicinski)
Date: Fri, 16 May 2025 16:31:05 -0700
Subject: [net-next, PATCH v2] net: phy: mediatek: do not require syscon
 compatible for pio property
In-Reply-To: <D997C4DB-1B03-4AFD-B48C-BFA19AB6194D@public-files.de>
References: <20250516180147.10416-1-linux@fw-web.de>
	<20250516180147.10416-3-linux@fw-web.de>
	<D997C4DB-1B03-4AFD-B48C-BFA19AB6194D@public-files.de>
Message-ID: <20250516163105.12088849@kernel.org>

On Fri, 16 May 2025 20:08:47 +0200 Frank Wunderlich wrote:
> Sorry, resent it by accident while sending v2 of my dts series.
> regards Frank

Unfortunately patchwork thought this is patch 1 of the series instead
of the bindings patch :(

Let's wait for binding reviews and maybe you could repost patches 1-3
for net-next without the dts ones? 


From patchwork-bot+netdevbpf at kernel.org  Fri May 16 16:50:28 2025
From: patchwork-bot+netdevbpf at kernel.org (patchwork-bot+netdevbpf at kernel.org)
Date: Fri, 16 May 2025 23:50:28 +0000
Subject: [PATCH net v2] net: airoha: Fix page recycling in
 airoha_qdma_rx_process()
In-Reply-To: <20250515-airoha-fix-rx-process-error-condition-v2-1-657e92c894b9@kernel.org>
References: <20250515-airoha-fix-rx-process-error-condition-v2-1-657e92c894b9@kernel.org>
Message-ID: <174743942851.4098936.12041671721533040373.git-patchwork-notify@kernel.org>

Hello:

This patch was applied to netdev/net.git (main)
by Jakub Kicinski <kuba at kernel.org>:

On Thu, 15 May 2025 08:33:06 +0200 you wrote:
> Do not recycle the page twice in airoha_qdma_rx_process routine in case
> of error. Just run dev_kfree_skb() if the skb has been allocated and marked
> for recycling. Run page_pool_put_full_page() directly if the skb has not
> been allocated yet.
> Moreover, rely on DMA address from queue entry element instead of reading
> it from the DMA descriptor for DMA syncing in airoha_qdma_rx_process().
> 
> [...]

Here is the summary with links:
  - [net,v2] net: airoha: Fix page recycling in airoha_qdma_rx_process()
    https://git.kernel.org/netdev/net/c/d6d2b0e1538d

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html




From lorenzo at kernel.org  Sat May 17 07:07:35 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Sat, 17 May 2025 16:07:35 +0200
Subject: [PATCH v3 2/4] net: airoha: Fix an error handling path in
 airoha_probe()
In-Reply-To: <47910951a3fa3c3bd2a942210e821d9301362128.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
 <47910951a3fa3c3bd2a942210e821d9301362128.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <aCiYJ98sE0FCcKql@lore-desk>

> If an error occurs after a successful airoha_hw_init() call,
> airoha_ppe_deinit() needs to be called as already done in the remove
> function.
> 
> Fixes: 00a7678310fe ("net: airoha: Introduce flowtable offload support")
> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>

Acked-by: Lorenzo Bianconi <lorenzo at kernel.org>

> ---
> Changes in v3:
>   - call airoha_ppe_deinit() and not airoha_ppe_init()   [Lorenzo Bianconi]
> 
> Changes in v2:
>   - Call airoha_ppe_init() at the right place in the error handling path
>     of the probe   [Lorenzo Bianconi]
> v2: https://lore.kernel.org/all/3791c95da3fa3c3bd2a942210e821d9301362128.1746715755.git.christophe.jaillet at wanadoo.fr/
> 
> v1: https://lore.kernel.org/all/f4a420f3a8b4a6fe72798f9774ec9aff2291522d.1744977434.git.christophe.jaillet at wanadoo.fr/
> 
> Compile tested only.
> ---
>  drivers/net/ethernet/airoha/airoha_eth.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index af8c4015938c..d435179875df 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -2967,6 +2967,7 @@ static int airoha_probe(struct platform_device *pdev)
>  error_napi_stop:
>  	for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
>  		airoha_qdma_stop_napi(&eth->qdma[i]);
> +	airoha_ppe_deinit(eth);
>  error_hw_cleanup:
>  	for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
>  		airoha_hw_cleanup(&eth->qdma[i]);
> -- 
> 2.49.0
> 
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From lorenzo at kernel.org  Sat May 17 07:09:40 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Sat, 17 May 2025 16:09:40 +0200
Subject: [PATCH v3 4/4] net: airoha: Use dev_err_probe()
In-Reply-To: <bb64aa1ea0205329c377ad32dde46cdf5c232db9.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
 <bb64aa1ea0205329c377ad32dde46cdf5c232db9.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <aCiYpEVR6LqimFR9@lore-desk>

> Use dev_err_probe() to slightly simplify the code.
> It is less verbose, more informational and makes error logging more
> consistent in the probe.
> 
> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>

Reviewed-by: Lorenzo Bianconi <lorenzo at kernel.org>

> ---
> Changes in v3:
>   - None
> 
> Changes in v2:
>   - New patch
> v2: https://lore.kernel.org/all/1b67aa9ea0245325c3779d32dde46cdf5c232db9.1746715755.git.christophe.jaillet at wanadoo.fr/
> 
> Compile tested only.
> ---
>  drivers/net/ethernet/airoha/airoha_eth.c | 21 +++++++++------------
>  1 file changed, 9 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index 2335aa59b06f..7404ee894467 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -2896,10 +2896,9 @@ static int airoha_probe(struct platform_device *pdev)
>  	eth->dev = &pdev->dev;
>  
>  	err = dma_set_mask_and_coherent(eth->dev, DMA_BIT_MASK(32));
> -	if (err) {
> -		dev_err(eth->dev, "failed configuring DMA mask\n");
> -		return err;
> -	}
> +	if (err)
> +		return dev_err_probe(eth->dev, err,
> +				     "failed configuring DMA mask\n");
>  
>  	eth->fe_regs = devm_platform_ioremap_resource_byname(pdev, "fe");
>  	if (IS_ERR(eth->fe_regs))
> @@ -2912,10 +2911,9 @@ static int airoha_probe(struct platform_device *pdev)
>  	err = devm_reset_control_bulk_get_exclusive(eth->dev,
>  						    ARRAY_SIZE(eth->rsts),
>  						    eth->rsts);
> -	if (err) {
> -		dev_err(eth->dev, "failed to get bulk reset lines\n");
> -		return err;
> -	}
> +	if (err)
> +		return dev_err_probe(eth->dev, err,
> +				     "failed to get bulk reset lines\n");
>  
>  	eth->xsi_rsts[0].id = "xsi-mac";
>  	eth->xsi_rsts[1].id = "hsi0-mac";
> @@ -2925,10 +2923,9 @@ static int airoha_probe(struct platform_device *pdev)
>  	err = devm_reset_control_bulk_get_exclusive(eth->dev,
>  						    ARRAY_SIZE(eth->xsi_rsts),
>  						    eth->xsi_rsts);
> -	if (err) {
> -		dev_err(eth->dev, "failed to get bulk xsi reset lines\n");
> -		return err;
> -	}
> +	if (err)
> +		return dev_err_probe(eth->dev, err,
> +				     "failed to get bulk xsi reset lines\n");
>  
>  	eth->napi_dev = alloc_netdev_dummy(0);
>  	if (!eth->napi_dev)
> -- 
> 2.49.0
> 
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From lorenzo at kernel.org  Sat May 17 08:19:42 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Sat, 17 May 2025 17:19:42 +0200
Subject: [PATCH 0/2] Add PCIe nodes to Airoha EN7581 SoC evaluation board
Message-ID: <20250517-en7581-evb-pcie-v1-0-97297eb063bb@kernel.org>

Introduce PCIe controller nodes to EN7581 SoC and EN7581 evaluation
board.

---
Lorenzo Bianconi (2):
      arm64: dts: airoha: en7581: Add gpio-ranges property for gpio controller
      arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board

 arch/arm64/boot/dts/airoha/en7581-evb.dts |  30 +++++++++
 arch/arm64/boot/dts/airoha/en7581.dtsi    | 105 ++++++++++++++++++++++++++++++
 2 files changed, 135 insertions(+)
---
base-commit: 6df944d2cf586213c48428223ab0e6b9c7c0b94e
change-id: 20250517-en7581-evb-pcie-0b8a301a5916

Best regards,
-- 
Lorenzo Bianconi <lorenzo at kernel.org>



From lorenzo at kernel.org  Sat May 17 08:19:43 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Sat, 17 May 2025 17:19:43 +0200
Subject: [PATCH 1/2] arm64: dts: airoha: en7581: Add gpio-ranges property
 for gpio controller
In-Reply-To: <20250517-en7581-evb-pcie-v1-0-97297eb063bb@kernel.org>
References: <20250517-en7581-evb-pcie-v1-0-97297eb063bb@kernel.org>
Message-ID: <20250517-en7581-evb-pcie-v1-1-97297eb063bb@kernel.org>

Introduce missing gpio-ranges property for Airoha EN7581 gpio controller

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 arch/arm64/boot/dts/airoha/en7581-evb.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts
index d53b72d18242e3cee8b37c7b1b719d662fd6db8d..a8f8a9f0b807a2ee4fd11f8418b8e810a6945d73 100644
--- a/arch/arm64/boot/dts/airoha/en7581-evb.dts
+++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts
@@ -65,6 +65,10 @@ reserved_bmt at 7e00000 {
 	};
 };
 
+&en7581_pinctrl {
+	gpio-ranges = <&en7581_pinctrl 0 13 47>;
+};
+
 &i2c0 {
 	status = "okay";
 };

-- 
2.49.0



From lorenzo at kernel.org  Sat May 17 08:19:44 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Sat, 17 May 2025 17:19:44 +0200
Subject: [PATCH 2/2] arm64: dts: airoha: en7581: Add PCIe nodes to EN7581
 SoC evaluation board
In-Reply-To: <20250517-en7581-evb-pcie-v1-0-97297eb063bb@kernel.org>
References: <20250517-en7581-evb-pcie-v1-0-97297eb063bb@kernel.org>
Message-ID: <20250517-en7581-evb-pcie-v1-2-97297eb063bb@kernel.org>

Introduce PCIe controller nodes to EN7581 SoC and EN7581 evaluation
board.

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 arch/arm64/boot/dts/airoha/en7581-evb.dts |  26 ++++++++
 arch/arm64/boot/dts/airoha/en7581.dtsi    | 105 ++++++++++++++++++++++++++++++
 2 files changed, 131 insertions(+)

diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts
index a8f8a9f0b807a2ee4fd11f8418b8e810a6945d73..99d2c4f1fc5a9638f551c6d725eeea568943cc68 100644
--- a/arch/arm64/boot/dts/airoha/en7581-evb.dts
+++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts
@@ -67,6 +67,32 @@ reserved_bmt at 7e00000 {
 
 &en7581_pinctrl {
 	gpio-ranges = <&en7581_pinctrl 0 13 47>;
+
+	pcie0_rst_pins: pcie0-rst-pins {
+		conf {
+			pins = "pcie_reset0";
+			drive-open-drain = <1>;
+		};
+	};
+
+	pcie1_rst_pins: pcie1-rst-pins {
+		conf {
+			pins = "pcie_reset1";
+			drive-open-drain = <1>;
+		};
+	};
+};
+
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_rst_pins>;
+	status = "okay";
+};
+
+&pcie1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie1_rst_pins>;
+	status = "okay";
 };
 
 &i2c0 {
diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index 26b13694091735da7af977e42f8f546d7d5cb078..536ece69b935add88fb73ca6bd3f1ecd842cad7a 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -180,6 +180,111 @@ scuclk: clock-controller at 1fb00000 {
 			#reset-cells = <1>;
 		};
 
+		pbus_csr: syscon at 1fbe3400 {
+			compatible = "airoha,en7581-pbus-csr", "syscon";
+			reg = <0x0 0x1fbe3400 0x0 0xff>;
+		};
+
+		pciephy: phy at 1fa5a000 {
+			compatible = "airoha,en7581-pcie-phy";
+			reg = <0x0 0x1fa5a000 0x0 0xfff>,
+			      <0x0 0x1fa5b000 0x0 0xfff>,
+			      <0x0 0x1fa5c000 0x0 0xfff>,
+			      <0x0 0x1fc10044 0x0 0x4>,
+			      <0x0 0x1fc30044 0x0 0x4>,
+			      <0x0 0x1fc15030 0x0 0x104>;
+			reg-names = "csr-2l", "pma0", "pma1",
+				    "p0-xr-dtime", "p1-xr-dtime",
+				    "rx-aeq";
+			#phy-cells = <0>;
+		};
+
+		pcie0: pcie at 1fc00000 {
+			compatible = "airoha,en7581-pcie";
+			device_type = "pci";
+			linux,pci-domain = <0>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			reg = <0x0 0x1fc00000 0x0 0x1670>;
+			reg-names = "pcie-mac";
+
+			clocks = <&scuclk EN7523_CLK_PCIE>;
+			clock-names = "sys-ck";
+
+			phys = <&pciephy>;
+			phy-names = "pcie-phy";
+
+			ranges = <0x02000000 0 0x20000000 0x0 0x20000000 0 0x4000000>;
+
+			resets = <&scuclk EN7581_PCIE0_RST>,
+				 <&scuclk EN7581_PCIE1_RST>,
+				 <&scuclk EN7581_PCIE2_RST>;
+			reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
+
+			mediatek,pbus-csr = <&pbus_csr 0x0 0x4>;
+
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+					<0 0 0 2 &pcie_intc0 1>,
+					<0 0 0 3 &pcie_intc0 2>,
+					<0 0 0 4 &pcie_intc0 3>;
+
+			status = "disabled";
+
+			pcie_intc0: interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		pcie1: pcie at 1fc20000 {
+			compatible = "airoha,en7581-pcie";
+			device_type = "pci";
+			linux,pci-domain = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			reg = <0x0 0x1fc20000 0x0 0x1670>;
+			reg-names = "pcie-mac";
+
+			clocks = <&scuclk EN7523_CLK_PCIE>;
+			clock-names = "sys-ck";
+
+			phys = <&pciephy>;
+			phy-names = "pcie-phy";
+
+			ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>;
+
+			resets = <&scuclk EN7581_PCIE0_RST>,
+				 <&scuclk EN7581_PCIE1_RST>,
+				 <&scuclk EN7581_PCIE2_RST>;
+			reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
+
+			mediatek,pbus-csr = <&pbus_csr 0x8 0xc>;
+
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+					<0 0 0 2 &pcie_intc1 1>,
+					<0 0 0 3 &pcie_intc1 2>,
+					<0 0 0 4 &pcie_intc1 3>;
+
+			status = "disabled";
+
+			pcie_intc1: interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+
 		uart1: serial at 1fbf0000 {
 			compatible = "ns16550";
 			reg = <0x0 0x1fbf0000 0x0 0x30>;

-- 
2.49.0



From wiagn233 at outlook.com  Sun May 18 07:41:59 2025
From: wiagn233 at outlook.com (Shengyu Qu)
Date: Sun, 18 May 2025 22:41:59 +0800
Subject: [PATCH v10 RESEND] wifi: mt76: mt7915: add wds support when wed
 is enabled
In-Reply-To: <OSZPR01MB84342A0E21AAD111ED7AF6B198B82@OSZPR01MB8434.jpnprd01.prod.outlook.com>
References: <OSZPR01MB84342A0E21AAD111ED7AF6B198B82@OSZPR01MB8434.jpnprd01.prod.outlook.com>
Message-ID: <TYCPR01MB84376DAD94940BEAFD483C44989DA@TYCPR01MB8437.jpnprd01.prod.outlook.com>

Hi Felix,

Do you think this patch is ok to merge?

Best regards,
Shengyu

? 2025/4/21 22:04, Shengyu Qu ??:
> The current WED only supports 256 wcid, whereas mt7986 can support up to
> 512 entries, so firmware provides a rule to get sta_info by DA when wcid
> is set to 0x3ff by txd. Also, WED provides a register to overwrite txd
> wcid, that is, wcid[9:8] can be overwritten by 0x3 and wcid[7:0] is set
> to 0xff by host driver.
> 
> However, firmware is unable to get sta_info from DA as DA != RA for
> 4addr cases, so firmware and wifi host driver both use wcid (256 - 271)
> and (768 ~ 783) for sync up to get correct sta_info.
> 
> Currently WDS+WED config is completely broken on MT7986/7981 devices if
> without this patch.
> 
> Reviewed-by: Ping-Ke Shih <pkshih at realtek.com>
> Tested-by: Sujuan Chen <sujuan.chen at mediatek.com>
> Co-developed-by: Bo Jiao <bo.jiao at mediatek.com>
> Signed-off-by: Bo Jiao <bo.jiao at mediatek.com>
> Signed-off-by: Sujuan Chen <sujuan.chen at mediatek.com>
> Signed-off-by: Shengyu Qu <wiagn233 at outlook.com>
> ---
> Changes since v1:
>   - Drop duplicate setting in mmio
>   - Reduce the patch size by redefining mt76_wcid_alloc
> Changes since v2:
>   - Rework wds wcid getting flow
> Changes since v3:
>   - Rebase to next-20240703
>   - Sync with downstream patch
> Changes since v4:
>   - Rebase to next-20240802
> Changes since v5:
>   - Fixed build test error reported by robot
>   - Rebase to next-20240805
> Changes since v6:
>   - Fix potential race conditions on tx/rx packets during the transition
>   - Rebase to Felix's newest codebase
> Changes since v7:
>   - Fix build fail
> Changes since v8:
>   - Changed code as Shih advised
> Changes since v9:
>   - Changed code as Shih advised
>   - Moved mt76_wcid_alloc to mt76.h
> ---
>   drivers/net/wireless/mediatek/mt76/mt76.h     | 15 ++++++
>   .../net/wireless/mediatek/mt76/mt7915/main.c  | 53 +++++++++++++++++--
>   .../net/wireless/mediatek/mt76/mt7915/mcu.c   | 18 +++++--
>   .../net/wireless/mediatek/mt76/mt7915/mcu.h   |  1 +
>   drivers/net/wireless/mediatek/mt76/util.c     | 37 +++++++++++--
>   drivers/net/wireless/mediatek/mt76/util.h     |  2 +-
>   6 files changed, 115 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/net/wireless/mediatek/mt76/mt76.h b/drivers/net/wireless/mediatek/mt76/mt76.h
> index d7cd467b812f..7f590854959e 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt76.h
> +++ b/drivers/net/wireless/mediatek/mt76/mt76.h
> @@ -28,6 +28,9 @@
>   
>   #define MT76_TOKEN_FREE_THR	64
>   
> +#define MT76_WED_WDS_MIN    256
> +#define MT76_WED_WDS_MAX    272
> +
>   #define MT_QFLAG_WED_RING	GENMASK(1, 0)
>   #define MT_QFLAG_WED_TYPE	GENMASK(4, 2)
>   #define MT_QFLAG_WED		BIT(5)
> @@ -73,6 +76,12 @@ enum mt76_wed_type {
>   	MT76_WED_RRO_Q_IND,
>   };
>   
> +enum mt76_wed_state {
> +	MT76_WED_DEFAULT,
> +	MT76_WED_ACTIVE,
> +	MT76_WED_WDS_ACTIVE,
> +};
> +
>   struct mt76_bus_ops {
>   	u32 (*rr)(struct mt76_dev *dev, u32 offset);
>   	void (*wr)(struct mt76_dev *dev, u32 offset, u32 val);
> @@ -1169,6 +1178,12 @@ void mt76_wed_dma_reset(struct mt76_dev *dev);
>   int mt76_wed_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
>   			  struct net_device *netdev, enum tc_setup_type type,
>   			  void *type_data);
> +
> +static inline int mt76_wcid_alloc(u32 *mask, int size)
> +{
> +	return __mt76_wcid_alloc(mask, size, MT76_WED_DEFAULT);
> +}
> +
>   #ifdef CONFIG_NET_MEDIATEK_SOC_WED
>   u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size);
>   int mt76_wed_offload_enable(struct mtk_wed_device *wed);
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/main.c b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
> index 3aa31c5cefa6..fcbf4f971026 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7915/main.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
> @@ -744,9 +744,16 @@ int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
>   	struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
>   	struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
>   	bool ext_phy = mvif->phy != &dev->phy;
> +	u8 flags = MT76_WED_DEFAULT;
>   	int idx;
>   
> -	idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA);
> +	if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
> +	    !is_mt7915(&dev->mt76)) {
> +		flags = test_bit(MT_WCID_FLAG_4ADDR, &msta->wcid.flags) ?
> +		       MT76_WED_WDS_ACTIVE : MT76_WED_ACTIVE;
> +	}
> +
> +	idx = __mt76_wcid_alloc(mdev->wcid_mask, MT7915_WTBL_STA, flags);
>   	if (idx < 0)
>   		return -ENOSPC;
>   
> @@ -1271,6 +1278,11 @@ static void mt7915_sta_set_4addr(struct ieee80211_hw *hw,
>   {
>   	struct mt7915_dev *dev = mt7915_hw_dev(hw);
>   	struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
> +	int min = MT76_WED_WDS_MIN, max = MT76_WED_WDS_MAX;
> +	struct ieee80211_sta *pre_sta;
> +	struct mt7915_sta *pre_msta;
> +	u8 flags = MT76_WED_DEFAULT;
> +	int tmp_idx;
>   
>   	if (enabled)
>   		set_bit(MT_WCID_FLAG_4ADDR, &msta->wcid.flags);
> @@ -1280,6 +1292,37 @@ static void mt7915_sta_set_4addr(struct ieee80211_hw *hw,
>   	if (!msta->wcid.sta)
>   		return;
>   
> +	if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
> +	    !is_mt7915(&dev->mt76) &&
> +	    (msta->wcid.idx < min || msta->wcid.idx > max - 1)) {
> +		pre_sta = kmemdup(sta, sizeof(*sta) + sizeof(*msta), GFP_KERNEL | __GFP_ZERO);
> +		if (!pre_sta)
> +			goto error_alloc;
> +		pre_msta = (struct mt7915_sta *)pre_sta->drv_priv;
> +
> +		flags = test_bit(MT_WCID_FLAG_4ADDR, &msta->wcid.flags) ?
> +			MT76_WED_WDS_ACTIVE : MT76_WED_ACTIVE;
> +
> +		tmp_idx = __mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA, flags);
> +		if (tmp_idx < 0)
> +			goto error_wcid;
> +		pre_msta->wcid.idx = (u16)tmp_idx;
> +		mt7915_mac_sta_add(&dev->mt76, vif, pre_sta);
> +		rcu_assign_pointer(dev->mt76.wcid[tmp_idx], &msta->wcid);
> +
> +		tmp_idx = msta->wcid.idx;
> +		msta->wcid.idx = pre_msta->wcid.idx;
> +		pre_msta->wcid.idx = (u16)tmp_idx;
> +		rcu_assign_pointer(dev->mt76.wcid[tmp_idx], NULL);
> +
> +		synchronize_rcu();
> +		mt7915_mac_sta_remove(&dev->mt76, vif, pre_sta);
> +
> +error_wcid:
> +		kfree(pre_sta);
> +	}
> +
> +error_alloc:
>   	mt76_connac_mcu_wtbl_update_hdr_trans(&dev->mt76, vif, sta);
>   }
>   
> @@ -1726,15 +1769,19 @@ mt7915_net_fill_forward_path(struct ieee80211_hw *hw,
>   	if (!mtk_wed_device_active(wed))
>   		return -ENODEV;
>   
> -	if (msta->wcid.idx > 0xff)
> +	if (msta->wcid.idx > MT7915_WTBL_STA)
>   		return -EIO;
>   
>   	path->type = DEV_PATH_MTK_WDMA;
>   	path->dev = ctx->dev;
>   	path->mtk_wdma.wdma_idx = wed->wdma_idx;
>   	path->mtk_wdma.bss = mvif->mt76.idx;
> -	path->mtk_wdma.wcid = is_mt7915(&dev->mt76) ? msta->wcid.idx : 0x3ff;
>   	path->mtk_wdma.queue = phy != &dev->phy;
> +	if (test_bit(MT_WCID_FLAG_4ADDR, &msta->wcid.flags) ||
> +	    is_mt7915(&dev->mt76))
> +		path->mtk_wdma.wcid = msta->wcid.idx;
> +	else
> +		path->mtk_wdma.wcid = 0x3ff;
>   
>   	ctx->dev = NULL;
>   
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
> index 427542777abc..61a854d2c416 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
> @@ -2403,10 +2403,20 @@ int mt7915_mcu_init_firmware(struct mt7915_dev *dev)
>   
>   	mt76_connac_mcu_del_wtbl_all(&dev->mt76);
>   
> -	if ((mtk_wed_device_active(&dev->mt76.mmio.wed) &&
> -	     is_mt7915(&dev->mt76)) ||
> -	    !mtk_wed_get_rx_capa(&dev->mt76.mmio.wed))
> -		mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(CAPABILITY), 0, 0, 0);
> +#if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED)
> +	if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
> +		if (is_mt7915(&dev->mt76) ||
> +		    !mtk_wed_get_rx_capa(&dev->mt76.mmio.wed))
> +			ret = mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(CAPABILITY),
> +						0, 0, 0);
> +		else
> +			ret = mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
> +						MCU_WA_PARAM_WED_VERSION,
> +						dev->mt76.mmio.wed.rev_id, 0);
> +		if (ret)
> +			return ret;
> +	}
> +#endif
>   
>   	ret = mt7915_mcu_set_mwds(dev, 1);
>   	if (ret)
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h
> index 086ad89ecd91..989f24cb49eb 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h
> +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h
> @@ -278,6 +278,7 @@ enum {
>   	MCU_WA_PARAM_PDMA_RX = 0x04,
>   	MCU_WA_PARAM_CPU_UTIL = 0x0b,
>   	MCU_WA_PARAM_RED = 0x0e,
> +	MCU_WA_PARAM_WED_VERSION = 0x32,
>   	MCU_WA_PARAM_RED_SETTING = 0x40,
>   };
>   
> diff --git a/drivers/net/wireless/mediatek/mt76/util.c b/drivers/net/wireless/mediatek/mt76/util.c
> index 95b3dc96e4c4..e80bef2b33a1 100644
> --- a/drivers/net/wireless/mediatek/mt76/util.c
> +++ b/drivers/net/wireless/mediatek/mt76/util.c
> @@ -42,8 +42,10 @@ bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
>   }
>   EXPORT_SYMBOL_GPL(____mt76_poll_msec);
>   
> -int mt76_wcid_alloc(u32 *mask, int size)
> +int __mt76_wcid_alloc(u32 *mask, int size, u8 flag)
>   {
> +	int max = MT76_WED_WDS_MAX;
> +	int min = MT76_WED_WDS_MIN;
>   	int i, idx = 0, cur;
>   
>   	for (i = 0; i < DIV_ROUND_UP(size, 32); i++) {
> @@ -53,16 +55,45 @@ int mt76_wcid_alloc(u32 *mask, int size)
>   
>   		idx--;
>   		cur = i * 32 + idx;
> -		if (cur >= size)
> +
> +		switch (flag) {
> +		case MT76_WED_ACTIVE:
> +			if (cur >= min && cur < max)
> +				continue;
> +
> +			if (cur >= size) {
> +				u32 end = max - min - 1;
> +
> +				i = min / 32;
> +				idx = ffs(~mask[i] & GENMASK(end, 0));
> +				if (!idx)
> +					goto error;
> +				idx--;
> +				cur = min + idx;
> +			}
> +
>   			break;
> +		case MT76_WED_WDS_ACTIVE:
> +			if (cur < min)
> +				continue;
> +			if (cur >= max)
> +				goto error;
> +
> +			break;
> +		default:
> +			if (cur >= size)
> +				goto error;
> +			break;
> +		}
>   
>   		mask[i] |= BIT(idx);
>   		return cur;
>   	}
>   
> +error:
>   	return -1;
>   }
> -EXPORT_SYMBOL_GPL(mt76_wcid_alloc);
> +EXPORT_SYMBOL_GPL(__mt76_wcid_alloc);
>   
>   int mt76_get_min_avg_rssi(struct mt76_dev *dev, u8 phy_idx)
>   {
> diff --git a/drivers/net/wireless/mediatek/mt76/util.h b/drivers/net/wireless/mediatek/mt76/util.h
> index 260965dde94c..fe95a847182e 100644
> --- a/drivers/net/wireless/mediatek/mt76/util.h
> +++ b/drivers/net/wireless/mediatek/mt76/util.h
> @@ -27,7 +27,7 @@ enum {
>   #define MT76_INCR(_var, _size) \
>   	(_var = (((_var) + 1) % (_size)))
>   
> -int mt76_wcid_alloc(u32 *mask, int size);
> +int __mt76_wcid_alloc(u32 *mask, int size, u8 flags);
>   
>   static inline void
>   mt76_wcid_mask_set(u32 *mask, int idx)

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From andrew at lunn.ch  Sun May 18 15:29:18 2025
From: andrew at lunn.ch (Andrew Lunn)
Date: Mon, 19 May 2025 00:29:18 +0200
Subject: [PATCH net-next v4 2/2] net: phy: mediatek: add driver for
 built-in 2.5G ethernet PHY on MT7988
In-Reply-To: <20250516102327.2014531-3-SkyLake.Huang@mediatek.com>
References: <20250516102327.2014531-1-SkyLake.Huang@mediatek.com>
 <20250516102327.2014531-3-SkyLake.Huang@mediatek.com>
Message-ID: <e915e555-acb5-41c5-951a-935f21f357c7@lunn.ch>

On Fri, May 16, 2025 at 06:23:27PM +0800, Sky Huang wrote:
> From: Sky Huang <skylake.huang at mediatek.com>
> 
> Add support for internal 2.5Gphy on MT7988. This driver will load
> necessary firmware and add appropriate time delay to make sure
> that firmware works stably. The firmware loading procedure takes
> about 11ms in this driver.
> 
> Signed-off-by: Sky Huang <skylake.huang at mediatek.com>

Reviewed-by: Andrew Lunn <andrew at lunn.ch>

    Andrew


From andrew at lunn.ch  Sun May 18 15:29:46 2025
From: andrew at lunn.ch (Andrew Lunn)
Date: Mon, 19 May 2025 00:29:46 +0200
Subject: [PATCH net-next v4 1/2] net: phy: mediatek: Sort config and file
 names in Kconfig and Makefile
In-Reply-To: <20250516102327.2014531-2-SkyLake.Huang@mediatek.com>
References: <20250516102327.2014531-1-SkyLake.Huang@mediatek.com>
 <20250516102327.2014531-2-SkyLake.Huang@mediatek.com>
Message-ID: <d38c3678-92f8-4a5e-a1ae-a205e44d99f4@lunn.ch>

On Fri, May 16, 2025 at 06:23:26PM +0800, Sky Huang wrote:
> From: Sky Huang <skylake.huang at mediatek.com>
> 
> Sort config and file names in Kconfig and Makefile in
> drivers/net/phy/mediatek/ in alphabetical order.
> 
> Signed-off-by: Sky Huang <skylake.huang at mediatek.com>

Reviewed-by: Andrew Lunn <andrew at lunn.ch>

    Andrew


From tanghuan at vivo.com  Sun May 18 19:29:12 2025
From: tanghuan at vivo.com (Huan Tang)
Date: Mon, 19 May 2025 10:29:12 +0800
Subject: [PATCH v3] ufs: core: Add HID support
Message-ID: <20250519022912.292-1-tanghuan@vivo.com>

Follow JESD220G, support HID(Host Initiated Defragmentation)
through sysfs, the relevant sysfs nodes are as follows:
	1.analysis_trigger
	2.defrag_trigger
	3.fragmented_size
	4.defrag_size
	5.progress_ratio
	6.state
The detailed definition	of the six nodes can be	found in the sysfs
documentation.

HID's execution policy is given to user-space.

Changelog
===
v2 - > v3:
	1.Remove the "ufs_" prefix from directory name
	2.Remove the "hid_" prefix from node names
	3.Make "ufs" appear only once in the HID group name
	4.Add "is_visible" callback for "ufs_sysfs_hid_group"
v1 - > v2:
	1.Refactor the HID code according to Bart and Peter and
	Arvi's suggestions

v2
	https://lore.kernel.org/all/20250512131519.138-1-tanghuan at vivo.com/
v1
	https://lore.kernel.org/all/20250417125008.123-1-tanghuan at vivo.com/

Signed-off-by: Huan Tang <tanghuan at vivo.com>
Signed-off-by: Wenxing Cheng <wenxing.cheng at vivo.com>
---
 Documentation/ABI/testing/sysfs-driver-ufs |  83 +++++++++
 drivers/ufs/core/ufs-sysfs.c               | 192 +++++++++++++++++++++
 drivers/ufs/core/ufshcd.c                  |   4 +
 include/ufs/ufs.h                          |  25 +++
 4 files changed, 304 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-driver-ufs b/Documentation/ABI/testing/sysfs-driver-ufs
index d4140dc6c5ba..24485df80ccb 100644
--- a/Documentation/ABI/testing/sysfs-driver-ufs
+++ b/Documentation/ABI/testing/sysfs-driver-ufs
@@ -1685,3 +1685,86 @@ Description:
 		================  ========================================
 
 		The file is read only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/analysis_trigger
+What:		/sys/bus/platform/devices/*.ufs/hid/analysis_trigger
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The host can enable or disable HID analysis operation.
+
+		=======  =========================================
+		disable   disable HID analysis operation
+		enable    enable HID analysis operation
+		=======  =========================================
+
+		The file is write only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/defrag_trigger
+What:		/sys/bus/platform/devices/*.ufs/hid/defrag_trigger
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The host can enable or disable HID defragmentation operation.
+
+		=======  =========================================
+		disable   disable HID defragmentation operation
+		enable    enable HID defragmentation operation
+		=======  =========================================
+
+		The attribute is write only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/fragmented_size
+What:		/sys/bus/platform/devices/*.ufs/hid/fragmented_size
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The total fragmented size in the device is reported through
+		this attribute.
+
+		The attribute is read only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/defrag_size
+What:		/sys/bus/platform/devices/*.ufs/hid/defrag_size
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The host sets the size to be defragmented by an HID
+		defragmentation operation.
+
+		The attribute is read/write.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/progress_ratio
+What:		/sys/bus/platform/devices/*.ufs/hid/progress_ratio
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		Defragmentation progress is reported by this attribute,
+		indicateds the ratio of the completed defragmentation size
+		over the requested defragmentation size.
+
+		====  ============================================
+		1     1%
+		...
+		100   100%
+		====  ============================================
+
+		The attribute is read only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/state
+What:		/sys/bus/platform/devices/*.ufs/hid/state
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The HID state is reported by this attribute.
+
+		====================   ===========================
+		idle			Idle(analysis required)
+		analysis_in_progress    Analysis in progress
+		defrag_required      	Defrag required
+		defrag_in_progress      Defrag in progress
+		defrag_completed      	Defrag completed
+		defrag_not_required     Defrag is not required
+		====================   ===========================
+
+		The attribute is read only.
diff --git a/drivers/ufs/core/ufs-sysfs.c b/drivers/ufs/core/ufs-sysfs.c
index de8b6acd4058..ba6371740b30 100644
--- a/drivers/ufs/core/ufs-sysfs.c
+++ b/drivers/ufs/core/ufs-sysfs.c
@@ -87,6 +87,26 @@ static const char *ufs_wb_resize_status_to_string(enum wb_resize_status status)
 	}
 }
 
+static const char *ufs_hid_state_to_string(enum ufs_hid_state state)
+{
+	switch (state) {
+	case HID_IDLE:
+		return "idle";
+	case ANALYSIS_IN_PROGRESS:
+		return "analysis_in_progress";
+	case DEFRAG_REQUIRED:
+		return "defrag_required";
+	case DEFRAG_IN_PROGRESS:
+		return "defrag_in_progress";
+	case DEFRAG_COMPLETED:
+		return "defrag_completed";
+	case DEFRAG_IS_NOT_REQUIRED:
+		return "defrag_not_required";
+	default:
+		return "unknown";
+	}
+}
+
 static const char *ufshcd_uic_link_state_to_string(
 			enum uic_link_state state)
 {
@@ -1763,6 +1783,177 @@ static const struct attribute_group ufs_sysfs_attributes_group = {
 	.attrs = ufs_sysfs_attributes,
 };
 
+static int hid_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
+			enum attr_idn idn, u32 *attr_val)
+{
+	int ret;
+
+	down(&hba->host_sem);
+	if (!ufshcd_is_user_access_allowed(hba)) {
+		up(&hba->host_sem);
+		return -EBUSY;
+	}
+
+	ufshcd_rpm_get_sync(hba);
+	ret = ufshcd_query_attr(hba, opcode, idn, 0, 0, attr_val);
+	ufshcd_rpm_put_sync(hba);
+
+	up(&hba->host_sem);
+	return ret;
+}
+
+static const char * const hid_trigger_mode[] = {"disable", "enable"};
+
+static ssize_t analysis_trigger_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	int mode;
+	int ret;
+
+	mode = sysfs_match_string(hid_trigger_mode, buf);
+	if (mode < 0)
+		return -EINVAL;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_WO(analysis_trigger);
+
+static ssize_t defrag_trigger_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	int mode;
+	int ret;
+
+	mode = sysfs_match_string(hid_trigger_mode, buf);
+	if (mode < 0)
+		return -EINVAL;
+
+	if (mode)
+		mode = HID_ANALYSIS_AND_DEFRAG_ENABLE;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_WO(defrag_trigger);
+
+static ssize_t fragmented_size_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_AVAILABLE_SIZE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%u\n", value);
+}
+
+static DEVICE_ATTR_RO(fragmented_size);
+
+static ssize_t defrag_size_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_SIZE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%u\n", value);
+}
+
+static ssize_t defrag_size_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	if (kstrtou32(buf, 0, &value))
+		return -EINVAL;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_SIZE, &value);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_RW(defrag_size);
+
+static ssize_t progress_ratio_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_PROGRESS_RATIO, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%u\n", value);
+}
+
+static DEVICE_ATTR_RO(progress_ratio);
+
+static ssize_t state_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_STATE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%s\n", ufs_hid_state_to_string(value));
+}
+
+static DEVICE_ATTR_RO(state);
+
+static struct attribute *ufs_sysfs_hid[] = {
+	&dev_attr_analysis_trigger.attr,
+	&dev_attr_defrag_trigger.attr,
+	&dev_attr_fragmented_size.attr,
+	&dev_attr_defrag_size.attr,
+	&dev_attr_progress_ratio.attr,
+	&dev_attr_state.attr,
+	NULL,
+};
+
+static umode_t  ufs_sysfs_hid_is_visible(struct kobject *kobj,
+		struct attribute *attr, int n)
+{
+	struct device *dev = container_of(kobj, struct device, kobj);
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+
+	return	hba->dev_info.hid_sup ? attr->mode : 0;
+}
+
+static const struct attribute_group ufs_sysfs_hid_group = {
+	.name = "hid",
+	.attrs = ufs_sysfs_hid,
+	.is_visible = ufs_sysfs_hid_is_visible,
+};
+
 static const struct attribute_group *ufs_sysfs_groups[] = {
 	&ufs_sysfs_default_group,
 	&ufs_sysfs_capabilities_group,
@@ -1777,6 +1968,7 @@ static const struct attribute_group *ufs_sysfs_groups[] = {
 	&ufs_sysfs_string_descriptors_group,
 	&ufs_sysfs_flags_group,
 	&ufs_sysfs_attributes_group,
+	&ufs_sysfs_hid_group,
 	NULL,
 };
 
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 3e2097e65964..8ccd923a5761 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -8390,6 +8390,10 @@ static int ufs_get_device_desc(struct ufs_hba *hba)
 
 	dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP];
 
+	dev_info->hid_sup = get_unaligned_be32(desc_buf +
+				DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP) &
+				UFS_DEV_HID_SUPPORT;
+
 	model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
 
 	err = ufshcd_read_string_desc(hba, model_index,
diff --git a/include/ufs/ufs.h b/include/ufs/ufs.h
index c0c59a8f7256..e61caa40f7cd 100644
--- a/include/ufs/ufs.h
+++ b/include/ufs/ufs.h
@@ -182,6 +182,11 @@ enum attr_idn {
 	QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE        = 0x1F,
 	QUERY_ATTR_IDN_TIMESTAMP		= 0x30,
 	QUERY_ATTR_IDN_DEV_LVL_EXCEPTION_ID     = 0x34,
+	QUERY_ATTR_IDN_HID_DEFRAG_OPERATION	= 0x35,
+	QUERY_ATTR_IDN_HID_AVAILABLE_SIZE	= 0x36,
+	QUERY_ATTR_IDN_HID_SIZE			= 0x37,
+	QUERY_ATTR_IDN_HID_PROGRESS_RATIO	= 0x38,
+	QUERY_ATTR_IDN_HID_STATE		= 0x39,
 	QUERY_ATTR_IDN_WB_BUF_RESIZE_HINT	= 0x3C,
 	QUERY_ATTR_IDN_WB_BUF_RESIZE_EN		= 0x3D,
 	QUERY_ATTR_IDN_WB_BUF_RESIZE_STATUS	= 0x3E,
@@ -401,6 +406,7 @@ enum {
 	UFS_DEV_HPB_SUPPORT		= BIT(7),
 	UFS_DEV_WRITE_BOOSTER_SUP	= BIT(8),
 	UFS_DEV_LVL_EXCEPTION_SUP       = BIT(12),
+	UFS_DEV_HID_SUPPORT		= BIT(13),
 };
 #define UFS_DEV_HPB_SUPPORT_VERSION		0x310
 
@@ -466,6 +472,23 @@ enum ufs_ref_clk_freq {
 	REF_CLK_FREQ_INVAL	= -1,
 };
 
+/* bDefragOperation attribute values */
+enum ufs_hid_defrag_operation {
+	HID_ANALYSIS_AND_DEFRAG_DISABLE	= 0,
+	HID_ANALYSIS_ENABLE		= 1,
+	HID_ANALYSIS_AND_DEFRAG_ENABLE	= 2,
+};
+
+/* bHIDState attribute values */
+enum ufs_hid_state {
+	HID_IDLE		= 0,
+	ANALYSIS_IN_PROGRESS	= 1,
+	DEFRAG_REQUIRED		= 2,
+	DEFRAG_IN_PROGRESS	= 3,
+	DEFRAG_COMPLETED	= 4,
+	DEFRAG_IS_NOT_REQUIRED	= 5,
+};
+
 /* bWriteBoosterBufferResizeEn attribute */
 enum wb_resize_en {
 	WB_RESIZE_EN_IDLE	= 0,
@@ -625,6 +648,8 @@ struct ufs_dev_info {
 	u32 rtc_update_period;
 
 	u8 rtt_cap; /* bDeviceRTTCap */
+
+	bool hid_sup;
 };
 
 /*
-- 
2.48.1



From tanghuan at vivo.com  Sun May 18 19:38:33 2025
From: tanghuan at vivo.com (Huan Tang)
Date: Mon, 19 May 2025 10:38:33 +0800
Subject: [PATCH v2] ufs: core: Add HID support
In-Reply-To: <88718b2f-0583-4444-8bf0-7ecf9a45329c@acm.org>
References: <88718b2f-0583-4444-8bf0-7ecf9a45329c@acm.org>
Message-ID: <20250519023833.343-1-tanghuan@vivo.com>

Hi bart sir,

Thank you for your comments and guidance???
The v3 patch???
https://lore.kernel.org/all/20250519022912.292-1-tanghuan at vivo.com/

> All HID sysfs attributes occur in the "ufs_hid" directory and have a
> "hid_" prefix. That's two times "hid". Please remove the "hid_" prefix
> from the sysfs attribute names since it is redundant.
OK! It has been modified in the v3 patch.

> Isn't the prefix "ufs_" in "ufs_hid" redundant since this sysfs group
> occurs under a UFS host controller directory?
OK! It has been modified in the v3 patch.

> Regarding the name of this sysfs group, "ufs" occurs twice in that
> name (ufs_sysfs_ufs_hid_group). Please make sure that "ufs" only occurs
> once in that sysfs group name.
OK! It has been modified in the v3 patch.

> Please merge ufs_sysfs_ufs_hid_group into ufs_sysfs_groups, remove the
> new sysfs_create_group() call and add a visibility callback in
> ufs_sysfs_ufs_hid_group that only makes the attributes in this group
> visible if hba->dev_info.hid_sup == true.
OK! It has been modified in the v3 patch.

Thanks
Huan




From herbert at gondor.apana.org.au  Sun May 18 22:59:35 2025
From: herbert at gondor.apana.org.au (Herbert Xu)
Date: Mon, 19 May 2025 13:59:35 +0800
Subject: [PATCH] dt-bindings: crypto: Drop obsolete mediatek,eip97-crypto
In-Reply-To: <20250513184042.3051424-1-robh@kernel.org>
References: <20250513184042.3051424-1-robh@kernel.org>
Message-ID: <aCrIx0LSKFpG-kQj@gondor.apana.org.au>

On Tue, May 13, 2025 at 01:40:41PM -0500, Rob Herring (Arm) wrote:
> The mediatek,eip97-crypto binding is half abandoned. The driver was
> dropped in 2020 as the Mediatek platforms use InsideSecure block and
> the driver for it. All the platforms except MT7623 were updated. A
> patch to update it was submitted, but never addressed the review
> comments.
> 
> Link: https://lore.kernel.org/all/20210303080923.16761-1-vic.wu at mediatek.com/
> Signed-off-by: Rob Herring (Arm) <robh at kernel.org>
> ---
>  .../bindings/crypto/mediatek-crypto.txt       | 25 -------------------
>  1 file changed, 25 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/crypto/mediatek-crypto.txt

Patch applied.  Thanks.
-- 
Email: Herbert Xu <herbert at gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt


From krzysztof.kozlowski at linaro.org  Sun May 18 23:41:01 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Mon, 19 May 2025 08:41:01 +0200
Subject: [PATCH v3 03/17] dt-bindings: display: mediatek: add BLENDER
 yaml for MT8196
In-Reply-To: <20250515093454.1729720-4-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
 <20250515093454.1729720-4-paul-pl.chen@mediatek.com>
Message-ID: <20250519-orthodox-wolf-of-piety-7cecfd@kuoka>

On Thu, May 15, 2025 at 05:34:15PM GMT, paul-pl.chen wrote:
> From: Paul-pl Chen <paul-pl.chen at mediatek.com>
> 
> Add mediatek,blender.yaml to support BLENDER for MT8196.
> MediaTek display overlap blender, namely OVL_BLENDER or BLENDER,
> executes the alpha blending function for overlapping layers
> from different sources.
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> 

No blank line between tags, wrong order of tags.

> Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>

If you are the author, what does this SoB mean? When was this patch
written, by whom and when was the review given?

Can you start using b4?

You did not provide proper lore links to previous versions and tags are
not correctly added.

Best regards,
Krzysztof



From krzk at kernel.org  Sun May 18 23:43:07 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Mon, 19 May 2025 08:43:07 +0200
Subject: [PATCH v3 04/17] dt-bindings: display: mediatek: add OUTPROC
 yaml for MT8196
In-Reply-To: <20250515093454.1729720-5-paul-pl.chen@mediatek.com>
References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
 <20250515093454.1729720-5-paul-pl.chen@mediatek.com>
Message-ID: <20250519-dark-warm-squid-4bdae2@kuoka>

On Thu, May 15, 2025 at 05:34:16PM GMT, paul-pl.chen wrote:
> From: Paul-pl Chen <paul-pl.chen at mediatek.com>
> 
> Add mediate,outproc.yaml to support OUTPROC for MT8196.
> MediaTek display overlap output processor, namely OVL_OUTPROC
> or OUTPROC,handles the post-stage of pixel processing in the
> overlapping procedure.
> 
> Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>

This was not here before. What is happening with this patchset? Why some
random SoBs were added?

Nothing like that was explained in commit msg.


> Signed-off-by: Paul-pl Chen <paul-pl.chen at mediatek.com>
> ---
>  .../display/mediatek/mediatek,outproc.yaml    | 54 +++++++++++++++++++
>  1 file changed, 54 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml
> 

...

> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        outproc0: outproc at 32970000 {

Drop unused label

Best regards,
Krzysztof



From bo.ye at mediatek.com  Mon May 19 00:38:13 2025
From: bo.ye at mediatek.com (Bo Ye)
Date: Mon, 19 May 2025 15:38:13 +0800
Subject: [PATCH] scsi: ufs: preventing bus hang crash during emergency power off
Message-ID: <20250519073814.167264-1-bo.ye@mediatek.com>

From: Qilin Tan <qilin.tan at mediatek.com>

When kernel_power_off is called directly without freezing userspace,
it may cause UFS crashes:

Callback:
    ...... 0xBFFFFFC080C6156C()
    vmlinux readl() + 52
    vmlinux ufshcd_add_command_trace() + 552
    vmlinux ufshcd_send_command() + 84

When kernel_power_off is executed, ufshcd_wl_shutdown is also called
to turn off the UFS reference clock, VCC, and VCCQ. If I/O requests
are still being sent to the UFS host and accessing the interrupt
status register at this time, AP read timeouts may occur, causing bus
hang crashes.

The root cause is that scsi_device_quiesce and blk_mq_freeze_queue
only drain the requests in the request queue but don't guarantee that
all requests have been dispatched to the UFS host and completed.
Requests may remain pending in the hardware dispatch queue and be
rescheduled later. If the UFS reference clock has already been turned
off at this point, a bus hang crash will occur.

Example of the race condition:
Thread 1                                                   Thread 2
kernel_power_off
-> ufshcd_wl_shutdown
 -> scsi_device_quiesce(sdev)
  -> blk_mq_freeze_queue(q)
   -> blk_mq_run_hw_queue(htx, false)
    -> blk_mq_delay_run_hw_queue(hctx, 0)                blk_mq_run_work_fn
 -> ufshcd_suspend(hba) // disable ref clk                -> blk_mq_dispatch_rq_list
                                                           -> blk_mq_run_hw_queue()
                                                            -> ufshcd_send_command()
                                                             -> ufshcd_add_command_trace()
                                                              -> ufshcd_readl(hba, REG_INTERRUPT_STATUS)

When Thread-2's dispatch request is delayed due to heavy CPU load,
the interrupt status register may be read after the reference clock
is disabled, resulting in a bus hang crash.

To avoid this issue, call ufshcd_wait_for_doorbell_clr to wait until
all requests are processed before disabling the reference clock.

Signed-off-by: Qilin Tan <qilin.tan at mediatek.com>
Signed-off-by: Bosser Ye <bo.ye at mediatek.com>
---
 drivers/ufs/core/ufshcd.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 7735421e3991..a1013aea8e90 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -10262,6 +10262,7 @@ static void ufshcd_wl_shutdown(struct device *dev)
 		scsi_device_set_state(sdev, SDEV_OFFLINE);
 		mutex_unlock(&sdev->state_mutex);
 	}
+	ufshcd_wait_for_doorbell_clr(hba, 5 * USEC_PER_SEC);
 	__ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
 
 	/*
-- 
2.17.0



From horms at kernel.org  Mon May 19 02:46:37 2025
From: horms at kernel.org (Simon Horman)
Date: Mon, 19 May 2025 10:46:37 +0100
Subject: [PATCH net-next v2 2/3] net: airoha: Add FLOW_CLS_STATS callback
 support
In-Reply-To: <20250516-airoha-en7581-flowstats-v2-2-06d5fbf28984@kernel.org>
References: <20250516-airoha-en7581-flowstats-v2-0-06d5fbf28984@kernel.org>
 <20250516-airoha-en7581-flowstats-v2-2-06d5fbf28984@kernel.org>
Message-ID: <20250519094637.GE365796@horms.kernel.org>

On Fri, May 16, 2025 at 10:00:00AM +0200, Lorenzo Bianconi wrote:

...

> @@ -1027,6 +1255,15 @@ int airoha_ppe_init(struct airoha_eth *eth)
>  	if (!ppe->foe_flow)
>  		return -ENOMEM;
>  
> +	foe_size = PPE_STATS_NUM_ENTRIES * sizeof(*ppe->foe_stats);
> +	if (foe_size) {

Hi Lorenzo,

It's unclear to me how foe_size can be zero.

> +		ppe->foe_stats = dmam_alloc_coherent(eth->dev, foe_size,
> +						     &ppe->foe_stats_dma,
> +						     GFP_KERNEL);
> +		if (!ppe->foe_stats)
> +			return -ENOMEM;
> +	}
> +
>  	err = rhashtable_init(&eth->flow_table, &airoha_flow_table_params);
>  	if (err)
>  		return err;

...


From lorenzo at kernel.org  Mon May 19 02:55:46 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Mon, 19 May 2025 11:55:46 +0200
Subject: [PATCH net-next v2 2/3] net: airoha: Add FLOW_CLS_STATS callback
 support
In-Reply-To: <20250519094637.GE365796@horms.kernel.org>
References: <20250516-airoha-en7581-flowstats-v2-0-06d5fbf28984@kernel.org>
 <20250516-airoha-en7581-flowstats-v2-2-06d5fbf28984@kernel.org>
 <20250519094637.GE365796@horms.kernel.org>
Message-ID: <aCsAItPcz_9CuxaP@lore-desk>

On May 19, Simon Horman wrote:
> On Fri, May 16, 2025 at 10:00:00AM +0200, Lorenzo Bianconi wrote:
> 
> ...
> 
> > @@ -1027,6 +1255,15 @@ int airoha_ppe_init(struct airoha_eth *eth)
> >  	if (!ppe->foe_flow)
> >  		return -ENOMEM;
> >  
> > +	foe_size = PPE_STATS_NUM_ENTRIES * sizeof(*ppe->foe_stats);
> > +	if (foe_size) {
> 
> Hi Lorenzo,
> 
> It's unclear to me how foe_size can be zero.

Hi Simon,

foe_size will be 0 if you disable CONFIG_NET_AIROHA_FLOW_STATS since in this
case PPE_STATS_NUM_ENTRIES will be 0.

Regards,
Lorenzo

> 
> > +		ppe->foe_stats = dmam_alloc_coherent(eth->dev, foe_size,
> > +						     &ppe->foe_stats_dma,
> > +						     GFP_KERNEL);
> > +		if (!ppe->foe_stats)
> > +			return -ENOMEM;
> > +	}
> > +
> >  	err = rhashtable_init(&eth->flow_table, &airoha_flow_table_params);
> >  	if (err)
> >  		return err;
> 
> ...
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From jwboyer at kernel.org  Mon May 19 04:57:30 2025
From: jwboyer at kernel.org (Josh Boyer)
Date: Mon, 19 May 2025 07:57:30 -0400
Subject: [PATCH] mediatek: Add mt8196 VCP firmware
In-Reply-To: <20250516064950.19175-1-xiangzhi.tang@mediatek.com>
References: <20250516064950.19175-1-xiangzhi.tang@mediatek.com>
Message-ID: <CA+5PVA4+LL0__tvi8Zujz3ERLyq+_eAphdy3c3omNt=JwQ+WCA@mail.gmail.com>

I dropped the executable bit and merged this.

https://gitlab.com/kernel-firmware/linux-firmware/-/merge_requests/554

josh

On Fri, May 16, 2025 at 2:51?AM Xiangzhi Tang
<xiangzhi.tang at mediatek.com> wrote:
>
> MediaTek's Video Companion Processor(VCP) is an RISC-V
> processor in MediaTek MT8196 SoC.
> It supports vedio encode/decode, vmm and vdisp feature.
>
> Release version: v1.0.0
>
> Signed-off-by: Xiangzhi Tang <xiangzhi.tang at mediatek.com>
> ---
>  WHENCE                  |   9 +++++++++
>  mediatek/mt8196/vcp.img | Bin 0 -> 5756016 bytes
>  2 files changed, 9 insertions(+)
>  create mode 100755 mediatek/mt8196/vcp.img
>
> diff --git a/WHENCE b/WHENCE
> index 29beba1b..57fd0d52 100644
> --- a/WHENCE
> +++ b/WHENCE
> @@ -5926,6 +5926,15 @@ Licence: Redistributable. See LICENCE.mediatek for details.
>
>  --------------------------------------------------------------------------
>
> +Driver: mt8196 - MediaTek MT8196 Video Controller Processor
> +
> +File: mediatek/mt8196/vcp.img
> +Version: v1.0.0
> +
> +Licence: Redistributable. See LICENCE.mediatek for details.
> +
> +--------------------------------------------------------------------------
> +
>  Driver: mtk_scp - MediaTek SCP System Control Processing Driver
>
>  File: mediatek/mt8183/scp.img
> diff --git a/mediatek/mt8196/vcp.img b/mediatek/mt8196/vcp.img
> new file mode 100755
> index 0000000000000000000000000000000000000000..7246d486ebd36f5acb3cb1b77cdec39c49d81364
> GIT binary patch
> literal 5756016
> zcmeFaeSA|@wm-bjIXQVLMN&=!Rz;JhX=$r95K2V_66`5$MWzVFQ9&uOWSAKRrWVJS
> zj!l!(HbAvC1Z8{+rNt5*1VZWHy^al%3J6Z|ig%nDwTvR;%s44R at wN2%?sJm1pm*-Q
> z&mYh4`F%d>=k)CCv-jF-ueJ8tYp=ccqH#jwkI7D!+`sa^2df^ex at N6&^)<IH&d<Nw
> zK`!`jDE^;sg73$KC4?FERX-}7DEGtr{|*Xt21j#p6eHuwvcx+Grpy0zUrESlj>oe{
> zy}H;O6StKm{&9L at bDm+$!R5qNOGs6p_SNGBU2K-gU$<Z7X=RDP8A<r_<;1y;B~RkF
> zr}Z!2IK3>1F@!mjZa?kZNYl%vOdMc{z*i2?JpU8v#KxD~1x`=Q#!B+!ctZSje>vm-
> z%Xm`Ne5<v}Vm~byqU6cX8RRcN9j<G&S2eTK{A?|$+R0k|EYVg4S!-81Fv5Fc3-Dl0
> z6v*urmXTP$ez70D5kMF}9swOk9pH*L9zlgS9)ZUjkD$gIkD$RDkD$dHkD$XFkC22n
> z9$^gLc!XrU at d#t_#v@#UHy&Xe-guro4ZPhaR`^*f`olg)+pf~<pR3Xv at mTTL@s#0N
> z_FNZBjI<9`dh$5R;4$K{;<4i?!?O&}YCN at gf_Qe~X?`5_WE#ZE`Yxe;T}Vj(f8bfj
> z;EiV?i#MKy9Nu^qs_ at 3MkjER(LN(ra7HaUuvrvmSo`pKR at hnWj8_&Wqc;i`^j5nTz
> zWAVnb at DjZ7EF6b79)<Vmf2O=&)!SSy^P;$nooE1W`1YbF^C3-=<vmJk!(>GoqVGHj
> zsqjnUJ2ZF3<OJX2{JhM at Y_YE@J2p!||C|qWLRO-HC6eQ>QCXz9Pg2g-)%8+I^pEQ&
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> z5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*
> zAOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}
> z0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq
> z5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*
> zAOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}
> l0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq68O^y{C{?}YWx5I
>
> literal 0
> HcmV?d00001
>
> --
> 2.46.0
>


From horms at kernel.org  Mon May 19 05:10:32 2025
From: horms at kernel.org (Simon Horman)
Date: Mon, 19 May 2025 13:10:32 +0100
Subject: [PATCH net-next v2 2/3] net: airoha: Add FLOW_CLS_STATS callback
 support
In-Reply-To: <aCsAItPcz_9CuxaP@lore-desk>
References: <20250516-airoha-en7581-flowstats-v2-0-06d5fbf28984@kernel.org>
 <20250516-airoha-en7581-flowstats-v2-2-06d5fbf28984@kernel.org>
 <20250519094637.GE365796@horms.kernel.org>
 <aCsAItPcz_9CuxaP@lore-desk>
Message-ID: <20250519121032.GF365796@horms.kernel.org>

On Mon, May 19, 2025 at 11:55:46AM +0200, Lorenzo Bianconi wrote:
> On May 19, Simon Horman wrote:
> > On Fri, May 16, 2025 at 10:00:00AM +0200, Lorenzo Bianconi wrote:
> > 
> > ...
> > 
> > > @@ -1027,6 +1255,15 @@ int airoha_ppe_init(struct airoha_eth *eth)
> > >  	if (!ppe->foe_flow)
> > >  		return -ENOMEM;
> > >  
> > > +	foe_size = PPE_STATS_NUM_ENTRIES * sizeof(*ppe->foe_stats);
> > > +	if (foe_size) {
> > 
> > Hi Lorenzo,
> > 
> > It's unclear to me how foe_size can be zero.
> 
> Hi Simon,
> 
> foe_size will be 0 if you disable CONFIG_NET_AIROHA_FLOW_STATS since in this
> case PPE_STATS_NUM_ENTRIES will be 0.

Thanks,

I see that now but for some reason it escaped me earlier.

With that cleared up this patch looks good to me.

Reviewed-by: Simon Horman <horms at kernel.org>




From horms at kernel.org  Mon May 19 05:13:41 2025
From: horms at kernel.org (Simon Horman)
Date: Mon, 19 May 2025 13:13:41 +0100
Subject: [PATCH net-next v2 1/3] net: airoha: npu: Move memory allocation
 in airoha_npu_send_msg() caller
In-Reply-To: <20250516-airoha-en7581-flowstats-v2-1-06d5fbf28984@kernel.org>
References: <20250516-airoha-en7581-flowstats-v2-0-06d5fbf28984@kernel.org>
 <20250516-airoha-en7581-flowstats-v2-1-06d5fbf28984@kernel.org>
Message-ID: <20250519121341.GG365796@horms.kernel.org>

On Fri, May 16, 2025 at 09:59:59AM +0200, Lorenzo Bianconi wrote:
> Move ppe_mbox_data struct memory allocation from airoha_npu_send_msg
> routine to the caller one. This is a preliminary patch to enable wlan NPU
> offloading and flow counter stats support.
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>

Reviewed-by: Simon Horman <horms at kernel.org>



From horms at kernel.org  Mon May 19 05:13:54 2025
From: horms at kernel.org (Simon Horman)
Date: Mon, 19 May 2025 13:13:54 +0100
Subject: [PATCH net-next v2 3/3] net: airoha: ppe: Disable packet
 keepalive
In-Reply-To: <20250516-airoha-en7581-flowstats-v2-3-06d5fbf28984@kernel.org>
References: <20250516-airoha-en7581-flowstats-v2-0-06d5fbf28984@kernel.org>
 <20250516-airoha-en7581-flowstats-v2-3-06d5fbf28984@kernel.org>
Message-ID: <20250519121354.GH365796@horms.kernel.org>

On Fri, May 16, 2025 at 10:00:01AM +0200, Lorenzo Bianconi wrote:
> Since netfilter flowtable entries are now refreshed by flow-stats
> polling, we can disable hw packet keepalive used to periodically send
> packets belonging to offloaded flows to the kernel in order to refresh
> flowtable entries.
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>

Reviewed-by: Simon Horman <horms at kernel.org>



From wsa+renesas at sang-engineering.com  Mon May 19 05:15:00 2025
From: wsa+renesas at sang-engineering.com (Wolfram Sang)
Date: Mon, 19 May 2025 14:15:00 +0200
Subject: [PATCH 0/7] archs: use proper node names for GPIO based I2C busses
Message-ID: <20250519121512.5657-1-wsa+renesas@sang-engineering.com>

A lot of boards across various archs have a superfluous '-' in their
node name for GPIO based I2C busses. 'dtbs_check' complains, so fix
them.

Based on linux-next as of 20250516. Build bots are happy. ARM patches
depend on another cleanup series[1], the rest has no dependencies. I
suggest that patches go via their subsystem trees.

Tested on Calao USB boards using AT91 chipsets and a Renesas Lager board
using R-Car H2.

[1] "[PATCH 0/4] ARM: dts: use recent scl/sda gpio bindings"
    https://lore.kernel.org/r/20250519112107.2980-1-wsa+renesas at sang-engineering.com

Wolfram Sang (7):
  arm64: dts: exynos: use proper node names for GPIO based I2C busses
  arm64: dts: mediatek: use proper node names for GPIO based I2C busses
  ARM: dts: microchip: use proper node names for GPIO based I2C busses
  ARM: dts: samsung: use proper node names for GPIO based I2C busses
  ARM: dts: stm32: use proper node names for GPIO based I2C busses
  LoongArch: dts: use proper node names for GPIO based I2C busses
  riscv: dts: allwinner: use proper node names for GPIO based I2C busses

 arch/arm/boot/dts/microchip/at91-foxg20.dts      |  2 +-
 arch/arm/boot/dts/microchip/at91-qil_a9260.dts   |  2 +-
 arch/arm/boot/dts/microchip/at91-sam9_l9260.dts  |  2 +-
 arch/arm/boot/dts/microchip/at91rm9200.dtsi      |  2 +-
 arch/arm/boot/dts/microchip/at91sam9260.dtsi     |  2 +-
 arch/arm/boot/dts/microchip/at91sam9260ek.dts    |  2 +-
 arch/arm/boot/dts/microchip/at91sam9261.dtsi     |  2 +-
 arch/arm/boot/dts/microchip/at91sam9263.dtsi     |  2 +-
 arch/arm/boot/dts/microchip/at91sam9263ek.dts    |  2 +-
 .../boot/dts/microchip/at91sam9g20ek_common.dtsi |  2 +-
 arch/arm/boot/dts/microchip/at91sam9g45.dtsi     |  2 +-
 arch/arm/boot/dts/microchip/at91sam9n12.dtsi     |  2 +-
 arch/arm/boot/dts/microchip/at91sam9rl.dtsi      |  4 ++--
 arch/arm/boot/dts/microchip/at91sam9rlek.dts     |  4 ++--
 arch/arm/boot/dts/microchip/at91sam9x5.dtsi      |  6 +++---
 arch/arm/boot/dts/microchip/ethernut5.dts        |  2 +-
 arch/arm/boot/dts/microchip/evk-pro3.dts         |  2 +-
 arch/arm/boot/dts/microchip/mpa1600.dts          |  2 +-
 arch/arm/boot/dts/microchip/tny_a9263.dts        |  2 +-
 .../arm/boot/dts/microchip/usb_a9260_common.dtsi |  2 +-
 arch/arm/boot/dts/microchip/usb_a9263.dts        |  2 +-
 arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts    |  2 +-
 arch/arm/boot/dts/samsung/exynos3250-monk.dts    |  2 +-
 arch/arm/boot/dts/samsung/exynos3250-rinato.dts  |  2 +-
 arch/arm/boot/dts/samsung/exynos4210-i9100.dts   |  6 +++---
 arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi   | 10 +++++-----
 .../boot/dts/samsung/exynos4412-galaxy-s3.dtsi   |  4 ++--
 arch/arm/boot/dts/samsung/exynos4412-midas.dtsi  |  6 +++---
 arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi |  8 ++++----
 arch/arm/boot/dts/samsung/s5pv210-aries.dtsi     | 16 ++++++++--------
 arch/arm/boot/dts/samsung/s5pv210-galaxys.dts    |  2 +-
 .../boot/dts/st/ste-ux500-samsung-codina-tmo.dts |  8 ++++----
 .../arm/boot/dts/st/ste-ux500-samsung-codina.dts |  8 ++++----
 .../arm/boot/dts/st/ste-ux500-samsung-gavini.dts | 12 ++++++------
 .../arm/boot/dts/st/ste-ux500-samsung-golden.dts |  8 ++++----
 .../arm/boot/dts/st/ste-ux500-samsung-janice.dts | 16 ++++++++--------
 arch/arm/boot/dts/st/ste-ux500-samsung-kyle.dts  |  8 ++++----
 .../arm/boot/dts/st/ste-ux500-samsung-skomer.dts |  8 ++++----
 .../boot/dts/exynos/exynos5433-tm2-common.dtsi   |  2 +-
 .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts     |  4 ++--
 arch/loongarch/boot/dts/loongson-2k1000.dtsi     |  4 ++--
 .../dts/allwinner/sun20i-d1-devterm-v3.14.dts    |  2 +-
 42 files changed, 94 insertions(+), 94 deletions(-)

-- 
2.47.2



From wsa+renesas at sang-engineering.com  Mon May 19 05:15:02 2025
From: wsa+renesas at sang-engineering.com (Wolfram Sang)
Date: Mon, 19 May 2025 14:15:02 +0200
Subject: [PATCH 2/7] arm64: dts: mediatek: use proper node names for GPIO based I2C busses
In-Reply-To: <20250519121512.5657-1-wsa+renesas@sang-engineering.com>
References: <20250519121512.5657-1-wsa+renesas@sang-engineering.com>
Message-ID: <20250519121512.5657-3-wsa+renesas@sang-engineering.com>

There shall not be a '-' before the number.

Signed-off-by: Wolfram Sang <wsa+renesas at sang-engineering.com>
---
 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
index ed79ad1ae871..d0e1d8f064c4 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
@@ -64,7 +64,7 @@ wps-key {
 	};
 
 	/* i2c of the left SFP cage (wan) */
-	i2c_sfp1: i2c-gpio-0 {
+	i2c_sfp1: i2c-gpio0 {
 		compatible = "i2c-gpio";
 		sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 		scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
@@ -74,7 +74,7 @@ i2c_sfp1: i2c-gpio-0 {
 	};
 
 	/* i2c of the right SFP cage (lan) */
-	i2c_sfp2: i2c-gpio-1 {
+	i2c_sfp2: i2c-gpio1 {
 		compatible = "i2c-gpio";
 		sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 		scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-- 
2.47.2



From geert at linux-m68k.org  Mon May 19 05:54:00 2025
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Mon, 19 May 2025 14:54:00 +0200
Subject: [PATCH 0/7] archs: use proper node names for GPIO based I2C busses
In-Reply-To: <20250519121512.5657-1-wsa+renesas@sang-engineering.com>
References: <20250519121512.5657-1-wsa+renesas@sang-engineering.com>
Message-ID: <CAMuHMdUOXZOe++Zpk_fGnPuGtQARN1fLQvTr0YX108OzZi4YmA@mail.gmail.com>

Hi Wolfram,

On Mon, 19 May 2025 at 14:15, Wolfram Sang
<wsa+renesas at sang-engineering.com> wrote:
> A lot of boards across various archs have a superfluous '-' in their
> node name for GPIO based I2C busses. 'dtbs_check' complains, so fix
> them.
>
> Based on linux-next as of 20250516. Build bots are happy. ARM patches
> depend on another cleanup series[1], the rest has no dependencies. I
> suggest that patches go via their subsystem trees.
>
> Tested on Calao USB boards using AT91 chipsets and a Renesas Lager board
> using R-Car H2.

Thanks for your series!

>   arm64: dts: exynos: use proper node names for GPIO based I2C busses
>   arm64: dts: mediatek: use proper node names for GPIO based I2C busses
>   ARM: dts: microchip: use proper node names for GPIO based I2C busses
>   ARM: dts: samsung: use proper node names for GPIO based I2C busses
>   ARM: dts: stm32: use proper node names for GPIO based I2C busses
>   LoongArch: dts: use proper node names for GPIO based I2C busses
>   riscv: dts: allwinner: use proper node names for GPIO based I2C busses

Hmmm... which of these changes affect the R-Car board? ;-)
Am I missing something?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From Zoie.Lin at mediatek.com  Mon May 19 06:26:36 2025
From: Zoie.Lin at mediatek.com (=?utf-8?B?Wm9pZSBMaW4gKOael+emueWmoSk=?=)
Date: Mon, 19 May 2025 13:26:36 +0000
Subject: [PATCH v5 1/1] i2c: mediatek: add runtime PM operations and bus
 regulator control
In-Reply-To: <em2y3tkiwlxc45f4sjtzdd3oy4v5zpqgdpqfppyzah2ilzidg2@wn6cnrezygpl>
References: <20250314145407.2900190-1-zoie.lin@mediatek.com>
	 <fqicrglyug7gmkmysok7hilhmkyhxmnkztzv4iffgry6xce6t3@2i6b2ihfu4rb>
	 <Z9yR6pyg1mtqKynh@makrotopia.org>
	 <em2y3tkiwlxc45f4sjtzdd3oy4v5zpqgdpqfppyzah2ilzidg2@wn6cnrezygpl>
Message-ID: <8874a29ba42eb828d70deb73d4b84a59126b84c8.camel@mediatek.com>

Hi Andi,
Hi Daniel,
 
1. The i2c_transfer function uses a completion mechanism
for interrupt handling, so i2c_transfer cannot be used in
interrupt context.

2. From the crash log, it was found that rt5190a_probe -->
irqreturn_t rt5190a_irq_handler (in interrupt context) -->
regmap_raw_read --> i2c_transfer, which indicates that i2c_transfer is
being used in interrupt context. This usage is incorrect.
 
Based on the reason above, it appears that the issue is related to
the rt5190a calling context rather than this patch.
 
Could you please review and consider to merge this patch again?
 
Thanks,
Zoie


On Fri, 2025-03-21 at 01:34 +0100, Andi Shyti wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Hi Daniel,
> 
> On Thu, Mar 20, 2025 at 10:08:42PM +0000, Daniel Golle wrote:
> > On Wed, Mar 19, 2025 at 12:34:53AM +0100, Andi Shyti wrote:
> > > On Fri, Mar 14, 2025 at 10:53:43PM +0800, Zoie Lin wrote:
> > > > Introduce support for runtime PM operations in
> > > > the I2C driver, enabling runtime suspend and resume
> > > > functionality.
> > > > 
> > > > Although in most platforms, the bus power of i2c is always
> > > > on, some platforms disable the i2c bus power in order to meet
> > > > low power request.
> > > > 
> > > > This implementation includes bus regulator control to
> > > > facilitate
> > > > proper handling of the bus power based on platform
> > > > requirements.
> > > > 
> > > > Signed-off-by: Zoie Lin <zoie.lin at mediatek.com>
> > > 
> > > merged to i2c/i2c-host.
> > 
> > the change causes a crash during boot on MT7988 which typically
> > uses
> > one of its I2C busses to connect a Richtek RT5190A PMIC.
> 
> Thanks a lot for testing it. I removed the commit.
> 
> Andi


From wsa+renesas at sang-engineering.com  Mon May 19 07:47:30 2025
From: wsa+renesas at sang-engineering.com (Wolfram Sang)
Date: Mon, 19 May 2025 16:47:30 +0200
Subject: [PATCH 0/7] archs: use proper node names for GPIO based I2C
 busses
In-Reply-To: <CAMuHMdUOXZOe++Zpk_fGnPuGtQARN1fLQvTr0YX108OzZi4YmA@mail.gmail.com>
References: <20250519121512.5657-1-wsa+renesas@sang-engineering.com>
 <CAMuHMdUOXZOe++Zpk_fGnPuGtQARN1fLQvTr0YX108OzZi4YmA@mail.gmail.com>
Message-ID: <aCtEgg55uuXQ87HP@shikoro>


> Hmmm... which of these changes affect the R-Car board? ;-)

Right, in this series, none :)

> Am I missing something?

I tested another series on top of this series with Lager. After the
EmbeddedRecipes break, I forgot that only the next series affects Lager.
Sorry for the confusion!

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From conor at kernel.org  Mon May 19 08:13:47 2025
From: conor at kernel.org (Conor Dooley)
Date: Mon, 19 May 2025 16:13:47 +0100
Subject: [PATCH v2 1/2] dt-bindings: clock: mediatek: Add #reset-cells
 property for MT8188
In-Reply-To: <20250516-dtb-check-mt8188-v2-1-fb60bef1b8e1@collabora.com>
References: <20250516-dtb-check-mt8188-v2-0-fb60bef1b8e1@collabora.com>
 <20250516-dtb-check-mt8188-v2-1-fb60bef1b8e1@collabora.com>
Message-ID: <20250519-amaze-sloped-9e7d9a63a1db@spud>

On Fri, May 16, 2025 at 04:12:13PM +0200, Julien Massot wrote:
> The '#reset-cells' property is permitted for some of the MT8188
> clock controllers, but not listed as a valid property.
> 
> Fixes: 9a5cd59640ac ("dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188")
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Signed-off-by: Julien Massot <julien.massot at collabora.com>

Acked-by: Conor Dooley <conor.dooley at microchip.com>
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From bvanassche at acm.org  Mon May 19 08:31:56 2025
From: bvanassche at acm.org (Bart Van Assche)
Date: Mon, 19 May 2025 08:31:56 -0700
Subject: [PATCH] scsi: ufs: preventing bus hang crash during emergency
 power off
In-Reply-To: <20250519073814.167264-1-bo.ye@mediatek.com>
References: <20250519073814.167264-1-bo.ye@mediatek.com>
Message-ID: <60c20e1f-ab07-4af9-b7ea-b199364c66d0@acm.org>

On 5/19/25 12:38 AM, Bo Ye wrote:
> diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
> index 7735421e3991..a1013aea8e90 100644
> --- a/drivers/ufs/core/ufshcd.c
> +++ b/drivers/ufs/core/ufshcd.c
> @@ -10262,6 +10262,7 @@ static void ufshcd_wl_shutdown(struct device *dev)
>   		scsi_device_set_state(sdev, SDEV_OFFLINE);
>   		mutex_unlock(&sdev->state_mutex);
>   	}
> +	ufshcd_wait_for_doorbell_clr(hba, 5 * USEC_PER_SEC);
>   	__ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
>   
>   	/*

UFS driver kernel patches should be prepared against Martin's for-next
branch. Commit a3a951064f7e ("scsi: ufs: Rework 
ufshcd_clock_scaling_prepare()") removed ufshcd_wait_for_doorbell_clr().

Please fix the build failure introduced by this patch.

Bart.


From sean.anderson at linux.dev  Mon May 19 11:10:12 2025
From: sean.anderson at linux.dev (Sean Anderson)
Date: Mon, 19 May 2025 14:10:12 -0400
Subject: [net-next PATCH v4 03/11] net: phylink: introduce internal
 phylink PCS handling
In-Reply-To: <aCQHZnAstBXbYzgy@makrotopia.org>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-4-ansuelsmth@gmail.com>
 <5d004048-ef8f-42ad-8f17-d1e4d495f57f@linux.dev>
 <aCOXfw-krDZo9phk@makrotopia.org>
 <7b50d202-e7f6-41cb-b868-6e6b33d4a2b9@linux.dev>
 <aCQHZnAstBXbYzgy@makrotopia.org>
Message-ID: <cdfbbdca-001b-4ed5-92ff-40fd3a8e3341@linux.dev>

On 5/13/25 23:00, Daniel Golle wrote:
> On Tue, May 13, 2025 at 03:23:32PM -0400, Sean Anderson wrote:
>> On 5/13/25 15:03, Daniel Golle wrote:
>> > just instead of having many
>> > more or less identical implementations of .mac_select_pcs, this
>> > functionality is moved into phylink. As a nice side-effect that also
>> > makes managing the life-cycle of the PCS more easy, so we won't need all
>> > the wrappers for all the PCS OPs.
>> 
>> I think the wrapper approach is very obviously correct. This way has me
>> worried about exciting new concurrency bugs.
> 
> You may not be surprised to read that this was also our starting point 2
> months ago, I had implemented support for standalone PCS very similar to
> the approach you have published now, using refcnt'ed instances and
> locked wrapper functions for all OPs. My approach, like yours, was to
> create a new subsystem for standalone PCS drivers which is orthogonal to
> phylink and only requires very few very small changes to phylink itself.
> It was a draft and not as complete and well-documented like your series
> now, of course.
> 
> I've then shared that implementation with Christian and some other
> experienced OpenWrt developers and we concluded that having phylink handle
> the PCS lifecycle and PCS selection would be the better and more elegant
> approach for multiple reasons:
>  - The lifetime management of the wrapper instances becomes tricky:
>    We would either have to live with them being allocated by the
>    MAC-driver (imagine test-case doing unbind and then bind in a loop
>    for a while -- we would end up oom). Or we need some kind of garbage
>    collecting mechanism which frees the wrapper once refcnt is zero --
>    and as .select_pcs would 'get' the PCS (ie. bump refcnt) we'd need a
>    'put' equivalent (eg. a .pcs_destroy() OP) in phylink.
> 
>    Russell repeatedly pointed me to the possibility of a PCS
>    "disappearing" (and potentially "reappearing" some time later), and
>    in this case it is unclear who would then ever call pcs_put(), or
>    even notify the Ethernet driver or phylink about the PCS now being
>    available (again). Using device_link_add(), like it is done in
>    pcs-rzn1-miic.c, prevents the worst (ie. use-after-free), but also
>    impacts all other netdevs exposed by the same Ethernet driver
>    instance, and has a few other rather ugly implications.

SRCU neatly solves the lifetime management issues. The wrapper lives as
long as anyone (provider or user) holds a reference. A PCS can disappear
at any point and everything still works (although the link goes down).
Device links are only an optimization; they cannot be relied on for
correctness.

>  - phylink currently expects .mac_select_pcs to never fail. But we may
>    need a mechanism similar to probe deferral in case the PCS is not
>    yet available.

Which is why you grab the PCS in probe. If you want to be more dynamic,
you can do it in netdev open like is done for PHYs.

>    Your series partially solves this in patch 11/11 "of: property: Add
>    device link support for PCS", but also that still won't make the link
>    come back in case of a PCS showing up late to the party, eg. due to
>    constraints such as phy drivers (drivers/phy, not drivers/net/phy)
>    waiting for nvmem providers, or PCS instances "going away" and
>    "coming back" later.

This all works correctly due to device links. The only case that doesn't
work automatically is something like

MAC built-in
  MDIO built-in
    PCS module

where the PCS module gets loaded late. In that case you have to manually
re-probe the MAC. I think the best way to address this would be to grab
the PCS in netdev open so that the MAC can probe without the PCS.

>  - removal of a PCS instance (eg. via sysfs unbind) would still
>    require changes to phylink. there is no phylink function to
>    impair the link in this case, and using dev_close() is a bit ugly,
>    and also won't bring the link back up once the PCS (re-)appears.

This works just fine. There are two cases:

- If the PCS has an IRQ, we notify phylink and then it polls the PCS
  (see below).
- If the PCS is polled, phylink will call pcs_get_state and see that the
  link is down.

Either way, the link goes down. But bringing the link back up is pretty
unusual anyway. Unlike PHYs (which theoretically can be on removable
busses) PCSs are generally permanently attached to their MACs. The only
removable scenario I can think of is if the PCS is on an FPGA and the
MAC is not.

So if the PCS goes away, the MAC is likely to follow shortly after
(since the whole thing is on a removable bus). Or someone has manually
removed the PCS, in which case I think it's reasonable to have them
manually remove the MAC as well. If you really want to support this,
then just grab the PCS in netdev open.

>  - phylink anyway is the only user of PCS drivers, and will very likely
>    always be. So why create another subsystem?

To avoid adding overhead for the majority of PCSs where the PCS is built
into the MAC and literally can't be removed. We only pay the price for
dynamicism on the drivers where it matters.

> All that being said I also see potential problems with Christians
> current implementation as it doesn't prevent the Ethernet driver to
> still store a pointer to struct phylink_pcs (returned eg. from
> fwnode_pcs_get()).
> 
> Hence I would like to see an even more tight integration with phylink,
> in the sense that pointers to 'struct phylink_pcs' should never be
> exposed to the MAC driver, as only in that way we can be sure that
> phylink, and only phylink, is responsible for reacting to a PCS "going
> away".

OK, but then how does the MAC select the PCS? If there are multiple PCSs
then ultimately someone has to configure a mux somewhere.

> Ie. instead of fwnode_phylink_pcs_parse() handing pointers to struct
> phylink_pcs to the Ethernet driver, so it can use it to populate struct
> phylink_config available_pcs member, this should be the responsibility
> of phylink alltogether, directly populating the list of available PCS in
> phylink's private structure.
> 
> Similarly, there should not be fwnode_pcs_get() but rather phylink
> providing a function fwnode_phylink_pcs_register(phylink, fwnode) which
> directly adds the PCS referenced to the internal list of available PCS.

This is difficult to work with for existing drivers. Many of them have
non-standard ways of looking up their PCS that they need to support for
backwards-compatibility. And some of them create the PCS themselves
(such as if they are PCI devices with internal MDIO busses). It's much
easier for the MAC to create or look up the PCS itself and then hand it
off to phylink.

> I hope we can pick the best of all the suggested implementations, and
> together come up with something even better.

Sure. And I think we were starting from a clean slate then this would be
the obvious way to do things. But we must support existing drivers and
provide an upgrade path for them. This is why I favor an incremental
approach.

--Sean


From wsa+renesas at sang-engineering.com  Mon May 19 11:59:41 2025
From: wsa+renesas at sang-engineering.com (Wolfram Sang)
Date: Mon, 19 May 2025 20:59:41 +0200
Subject: [PATCH 0/7] archs: use proper node names for GPIO based I2C
 busses
In-Reply-To: <20250519121512.5657-1-wsa+renesas@sang-engineering.com>
References: <20250519121512.5657-1-wsa+renesas@sang-engineering.com>
Message-ID: <aCt_nTLapk0XdI4E@shikoro>

On Mon, May 19, 2025 at 02:15:00PM +0200, Wolfram Sang wrote:
> A lot of boards across various archs have a superfluous '-' in their
> node name for GPIO based I2C busses. 'dtbs_check' complains, so fix
> them.

Please drop this series. We found out that upstream dt-schema is broken
instead. I sent a fix.

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From nfraprado at collabora.com  Mon May 19 12:38:42 2025
From: nfraprado at collabora.com (=?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?=)
Date: Mon, 19 May 2025 15:38:42 -0400
Subject: [PATCH] pinctrl: mediatek: eint: Fix invalid pointer dereference
 for v1 platforms
Message-ID: <20250519-genio-350-eint-null-ptr-deref-fix-v1-1-07445d6d22c3@collabora.com>

Commit 3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple
addresses") introduced an access to the 'soc' field of struct
mtk_pinctrl in mtk_eint_do_init() and for that an include of
pinctrl-mtk-common-v2.h.

However, pinctrl drivers relying on the v1 common driver include
pinctrl-mtk-common.h instead, which provides another definition of
struct mtk_pinctrl that does not contain an 'soc' field.

Since mtk_eint_do_init() can be called both by v1 and v2 drivers, it
will now try to dereference an invalid pointer when called on v1
platforms. This has been observed on Genio 350 EVK (MT8365), which
crashes very early in boot (the kernel trace can only be seen with
earlycon).

In order to fix this, given that this if code block is only relevant for
platforms with multiple EINT bases, and the previous if block already
handles the single base case, add an else statement so this if condition
will never even be evaluated on platforms with a single EINT base, which
covers all v1 platforms following commit fe412e3a6c97 ("pinctrl:
mediatek: common-v1: Fix EINT breakage on older controllers").

Fixes: 3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple addresses")
Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
---
 drivers/pinctrl/mediatek/mtk-eint.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c
index 16af6a47028e67bb53db4041a37ebbbb8b9a1e43..9114e0cd9def1bc65558c67317abe67ba63ef1f6 100644
--- a/drivers/pinctrl/mediatek/mtk-eint.c
+++ b/drivers/pinctrl/mediatek/mtk-eint.c
@@ -531,9 +531,7 @@ int mtk_eint_do_init(struct mtk_eint *eint)
 			eint->pins[i].index = i;
 			eint->pins[i].debounce = (i < eint->hw->db_cnt) ? 1 : 0;
 		}
-	}
-
-	if (hw && hw->soc && hw->soc->eint_pin) {
+	} else if (hw && hw->soc && hw->soc->eint_pin) {
 		eint->pins = hw->soc->eint_pin;
 		for (i = 0; i < eint->hw->ap_num; i++) {
 			inst = eint->pins[i].instance;

---
base-commit: 8566fc3b96539e3235909d6bdda198e1282beaed
change-id: 20250519-genio-350-eint-null-ptr-deref-fix-1a163aa9ad84

Best regards,
-- 
N?colas F. R. A. Prado <nfraprado at collabora.com>



From bvanassche at acm.org  Mon May 19 14:02:41 2025
From: bvanassche at acm.org (Bart Van Assche)
Date: Mon, 19 May 2025 14:02:41 -0700
Subject: [PATCH v3] ufs: core: Add HID support
In-Reply-To: <20250519022912.292-1-tanghuan@vivo.com>
References: <20250519022912.292-1-tanghuan@vivo.com>
Message-ID: <08e67735-d5b0-47d0-b476-c22a3b5acdda@acm.org>

On 5/18/25 7:29 PM, Huan Tang wrote:
> Follow JESD220G, support HID(Host Initiated Defragmentation)
> through sysfs, the relevant sysfs nodes are as follows:
> 	1.analysis_trigger
> 	2.defrag_trigger
> 	3.fragmented_size
> 	4.defrag_size
> 	5.progress_ratio
> 	6.state
> The detailed definition	of the six nodes can be	found in the sysfs
> documentation.
> 
> HID's execution policy is given to user-space.
> 
> Changelog
> ===
> v2 - > v3:
> 	1.Remove the "ufs_" prefix from directory name
> 	2.Remove the "hid_" prefix from node names
> 	3.Make "ufs" appear only once in the HID group name
> 	4.Add "is_visible" callback for "ufs_sysfs_hid_group"
> v1 - > v2:
> 	1.Refactor the HID code according to Bart and Peter and
> 	Arvi's suggestions
> 
> v2
> 	https://lore.kernel.org/all/20250512131519.138-1-tanghuan at vivo.com/
> v1
> 	https://lore.kernel.org/all/20250417125008.123-1-tanghuan at vivo.com/
> 
> Signed-off-by: Huan Tang <tanghuan at vivo.com>
> Signed-off-by: Wenxing Cheng <wenxing.cheng at vivo.com>
> ---

The patch changelog should occur below the three hyphens (---) such that
it doesn't end up in the kernel changelog. Otherwise this patch looks
good to me. Hence:

Reviewed-by: Bart Van Assche <bvanassche at acm.org>


From sean.anderson at linux.dev  Mon May 19 16:28:34 2025
From: sean.anderson at linux.dev (Sean Anderson)
Date: Mon, 19 May 2025 19:28:34 -0400
Subject: [net-next PATCH v4 03/11] net: phylink: introduce internal
 phylink PCS handling
In-Reply-To: <cdfbbdca-001b-4ed5-92ff-40fd3a8e3341@linux.dev>
References: <20250511201250.3789083-1-ansuelsmth@gmail.com>
 <20250511201250.3789083-4-ansuelsmth@gmail.com>
 <5d004048-ef8f-42ad-8f17-d1e4d495f57f@linux.dev>
 <aCOXfw-krDZo9phk@makrotopia.org>
 <7b50d202-e7f6-41cb-b868-6e6b33d4a2b9@linux.dev>
 <aCQHZnAstBXbYzgy@makrotopia.org>
 <cdfbbdca-001b-4ed5-92ff-40fd3a8e3341@linux.dev>
Message-ID: <7bb37bea-917c-4082-9eaa-063c4d97833b@linux.dev>

On 5/19/25 14:10, Sean Anderson wrote:
> On 5/13/25 23:00, Daniel Golle wrote:
>> On Tue, May 13, 2025 at 03:23:32PM -0400, Sean Anderson wrote:
>>> On 5/13/25 15:03, Daniel Golle wrote:
>>> > just instead of having many
>>> > more or less identical implementations of .mac_select_pcs, this
>>> > functionality is moved into phylink. As a nice side-effect that also
>>> > makes managing the life-cycle of the PCS more easy, so we won't need all
>>> > the wrappers for all the PCS OPs.
>>> 
>>> I think the wrapper approach is very obviously correct. This way has me
>>> worried about exciting new concurrency bugs.
>> 
>> You may not be surprised to read that this was also our starting point 2
>> months ago, I had implemented support for standalone PCS very similar to
>> the approach you have published now, using refcnt'ed instances and
>> locked wrapper functions for all OPs. My approach, like yours, was to
>> create a new subsystem for standalone PCS drivers which is orthogonal to
>> phylink and only requires very few very small changes to phylink itself.
>> It was a draft and not as complete and well-documented like your series
>> now, of course.
>> 
>> I've then shared that implementation with Christian and some other
>> experienced OpenWrt developers and we concluded that having phylink handle
>> the PCS lifecycle and PCS selection would be the better and more elegant
>> approach for multiple reasons:
>>  - The lifetime management of the wrapper instances becomes tricky:
>>    We would either have to live with them being allocated by the
>>    MAC-driver (imagine test-case doing unbind and then bind in a loop
>>    for a while -- we would end up oom). Or we need some kind of garbage
>>    collecting mechanism which frees the wrapper once refcnt is zero --
>>    and as .select_pcs would 'get' the PCS (ie. bump refcnt) we'd need a
>>    'put' equivalent (eg. a .pcs_destroy() OP) in phylink.
>> 
>>    Russell repeatedly pointed me to the possibility of a PCS
>>    "disappearing" (and potentially "reappearing" some time later), and
>>    in this case it is unclear who would then ever call pcs_put(), or
>>    even notify the Ethernet driver or phylink about the PCS now being
>>    available (again). Using device_link_add(), like it is done in
>>    pcs-rzn1-miic.c, prevents the worst (ie. use-after-free), but also
>>    impacts all other netdevs exposed by the same Ethernet driver
>>    instance, and has a few other rather ugly implications.
> 
> SRCU neatly solves the lifetime management issues. The wrapper lives as
> long as anyone (provider or user) holds a reference. A PCS can disappear
> at any point and everything still works (although the link goes down).
> Device links are only an optimization; they cannot be relied on for
> correctness.
> 
>>  - phylink currently expects .mac_select_pcs to never fail. But we may
>>    need a mechanism similar to probe deferral in case the PCS is not
>>    yet available.
> 
> Which is why you grab the PCS in probe. If you want to be more dynamic,
> you can do it in netdev open like is done for PHYs.
> 
>>    Your series partially solves this in patch 11/11 "of: property: Add
>>    device link support for PCS", but also that still won't make the link
>>    come back in case of a PCS showing up late to the party, eg. due to
>>    constraints such as phy drivers (drivers/phy, not drivers/net/phy)
>>    waiting for nvmem providers, or PCS instances "going away" and
>>    "coming back" later.
> 
> This all works correctly due to device links. The only case that doesn't
> work automatically is something like
> 
> MAC built-in
>   MDIO built-in
>     PCS module
> 
> where the PCS module gets loaded late. In that case you have to manually
> re-probe the MAC. I think the best way to address this would be to grab
> the PCS in netdev open so that the MAC can probe without the PCS.
> 
>>  - removal of a PCS instance (eg. via sysfs unbind) would still
>>    require changes to phylink. there is no phylink function to
>>    impair the link in this case, and using dev_close() is a bit ugly,
>>    and also won't bring the link back up once the PCS (re-)appears.
> 
> This works just fine. There are two cases:
> 
> - If the PCS has an IRQ, we notify phylink and then it polls the PCS
>   (see below).
> - If the PCS is polled, phylink will call pcs_get_state and see that the
>   link is down.
> 
> Either way, the link goes down. But bringing the link back up is pretty
> unusual anyway. Unlike PHYs (which theoretically can be on removable
> busses) PCSs are generally permanently attached to their MACs. The only
> removable scenario I can think of is if the PCS is on an FPGA and the
> MAC is not.
> 
> So if the PCS goes away, the MAC is likely to follow shortly after
> (since the whole thing is on a removable bus). Or someone has manually
> removed the PCS, in which case I think it's reasonable to have them
> manually remove the MAC as well. If you really want to support this,
> then just grab the PCS in netdev open.

So I had a closer look at this and unfortunately it isn't as easy as
just grabbing the PCS in ndo_open. The problem is that we need to
know the supported interfaces before phylink_create. The interfaces are
validated and are visible to userspace as soon as the netdev is
registered. And we can't just defer phylink_create to ndo_open because a
lot of the ethtool ops are implemented with phylink. So this would
probably need something like phylink_update_supported_interfaces().

But TBH I don't think this use case is very relevant. As I said above,
it only affects FPGA reconfiguration and people manually unbinding
drivers. Either way I think they are savvy enough to reprobe the netdev.

--Sean

>>  - phylink anyway is the only user of PCS drivers, and will very likely
>>    always be. So why create another subsystem?
> 
> To avoid adding overhead for the majority of PCSs where the PCS is built
> into the MAC and literally can't be removed. We only pay the price for
> dynamicism on the drivers where it matters.
> 
>> All that being said I also see potential problems with Christians
>> current implementation as it doesn't prevent the Ethernet driver to
>> still store a pointer to struct phylink_pcs (returned eg. from
>> fwnode_pcs_get()).
>> 
>> Hence I would like to see an even more tight integration with phylink,
>> in the sense that pointers to 'struct phylink_pcs' should never be
>> exposed to the MAC driver, as only in that way we can be sure that
>> phylink, and only phylink, is responsible for reacting to a PCS "going
>> away".
> 
> OK, but then how does the MAC select the PCS? If there are multiple PCSs
> then ultimately someone has to configure a mux somewhere.
> 
>> Ie. instead of fwnode_phylink_pcs_parse() handing pointers to struct
>> phylink_pcs to the Ethernet driver, so it can use it to populate struct
>> phylink_config available_pcs member, this should be the responsibility
>> of phylink alltogether, directly populating the list of available PCS in
>> phylink's private structure.
>> 
>> Similarly, there should not be fwnode_pcs_get() but rather phylink
>> providing a function fwnode_phylink_pcs_register(phylink, fwnode) which
>> directly adds the PCS referenced to the internal list of available PCS.
> 
> This is difficult to work with for existing drivers. Many of them have
> non-standard ways of looking up their PCS that they need to support for
> backwards-compatibility. And some of them create the PCS themselves
> (such as if they are PCI devices with internal MDIO busses). It's much
> easier for the MAC to create or look up the PCS itself and then hand it
> off to phylink.
> 
>> I hope we can pick the best of all the suggested implementations, and
>> together come up with something even better.
> 
> Sure. And I think we were starting from a clean slate then this would be
> the obvious way to do things. But we must support existing drivers and
> provide an upgrade path for them. This is why I favor an incremental
> approach.
> 
> --Sean


From jinjian.song at fibocom.com  Mon May 19 19:59:34 2025
From: jinjian.song at fibocom.com (Jinjian Song)
Date: Tue, 20 May 2025 10:59:34 +0800
Subject: [net-next v1] net: wwan: t7xx: Parameterize data plane RX BAT and FAG count
In-Reply-To: <20250516084320.66998caf@kernel.org>
References: <20250514104728.10869-1-jinjian.song@fibocom.com> <20250515180858.2568d930@kernel.org>
Message-ID: <20250516084320.66998caf@kernel.org>

>On Fri, 16 May 2025 11:46:57 +0800 Jinjian Song wrote:
>> >Module parameters are discouraged, they are pretty poor as an API since
>> >they apply to all devices in the system. Can you describe what "frg"
>> >and "bat" are ? One of the existing APIs likely covers them.
>> >Please also describe the scope (are they per netdev or some sort of
>> >device level params)?  
>> 
>> MTK t7xx data plane hardware use BAT (Buffer Address Table) and FRG (Fragment) BAT
>> to describle and manager RX buffer, these buffers will apply for a fixed size after
>> the driver probe, and accompany the life cycle of the driver.
>> 
>> On some platforms, especially those that use swiotlb to manager buffers, without
>> changing the buffer pool provided by swiotlb, it's needed to adjust the buffers
>> used by the driver to meet the requirements.
>> So parameterize these buffers applicable to the MTK t7xx driver to facilitate
>> different platforms to work with different configurations. 
>
>Have you looked at
>https://docs.kernel.org/networking/ethtool-netlink.html#rings-set 
>?
>

Hi Jakub,
  Thanks, I've just learned this content.
  I think ETHTOOL_STRINGPARAM is a good summary of the ring parameters and can
be referred to and applied to WWAN. However, it seemes that this can't be configured
when the driver is loaded and requires an application through ioctrl. In addition,
directly using this parameter can't well correspond to the multiple buffer representing
BAT in the t7xx driver.

  If it's not feasible to directly add parameters for configuring this RX buffer(BAT/FAG) to 
the mtk_t7xx driver, would it be allowed to add aparameter for a default configuration 
ratio (1/2, 1/4)? Or is it not recommended to use driver parameters for mtk_t7xx driver.

Thanks,
Best Regards. 


From tanghuan at vivo.com  Mon May 19 23:35:12 2025
From: tanghuan at vivo.com (Huan Tang)
Date: Tue, 20 May 2025 14:35:12 +0800
Subject: [PATCH v4] ufs: core: Add HID support
Message-ID: <20250520063512.213-1-tanghuan@vivo.com>

Follow JESD220G, support HID(Host Initiated Defragmentation)
through sysfs, the relevant sysfs nodes are as follows:
	1.analysis_trigger
	2.defrag_trigger
	3.fragmented_size
	4.defrag_size
	5.progress_ratio
	6.state
The detailed definition	of the six nodes can be	found in the sysfs
documentation.

HID's execution policy is given to user-space.

Signed-off-by: Huan Tang <tanghuan at vivo.com>
Signed-off-by: Wenxing Cheng <wenxing.cheng at vivo.com>
---
Changelog
===
v3 - > v4:
	1.Move the changelog description under "---"
v2 - > v3:
	1.Remove the "ufs_" prefix from directory name
	2.Remove the "hid_" prefix from node names
	3.Make "ufs" appear only once in the HID group name
	4.Add "is_visible" callback for "ufs_sysfs_hid_group"
v1 - > v2:
	1.Refactor the HID code according to Bart and Peter and
	Arvi's suggestions
v3
	https://lore.kernel.org/all/20250519022912.292-1-tanghuan at vivo.com/
v2
	https://lore.kernel.org/all/20250512131519.138-1-tanghuan at vivo.com/
v1
	https://lore.kernel.org/all/20250417125008.123-1-tanghuan at vivo.com/

 Documentation/ABI/testing/sysfs-driver-ufs |  83 +++++++++
 drivers/ufs/core/ufs-sysfs.c               | 192 +++++++++++++++++++++
 drivers/ufs/core/ufshcd.c                  |   4 +
 include/ufs/ufs.h                          |  25 +++
 4 files changed, 304 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-driver-ufs b/Documentation/ABI/testing/sysfs-driver-ufs
index d4140dc6c5ba..490efdf1a0b4 100644
--- a/Documentation/ABI/testing/sysfs-driver-ufs
+++ b/Documentation/ABI/testing/sysfs-driver-ufs
@@ -1685,3 +1685,86 @@ Description:
 		================  ========================================
 
 		The file is read only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/analysis_trigger
+What:		/sys/bus/platform/devices/*.ufs/hid/analysis_trigger
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The host can enable or disable HID analysis operation.
+
+		=======  =========================================
+		disable   disable HID analysis operation
+		enable    enable HID analysis operation
+		=======  =========================================
+
+		The file is write only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/defrag_trigger
+What:		/sys/bus/platform/devices/*.ufs/hid/defrag_trigger
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The host can enable or disable HID defragmentation operation.
+
+		=======  =========================================
+		disable   disable HID defragmentation operation
+		enable    enable HID defragmentation operation
+		=======  =========================================
+
+		The attribute is write only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/fragmented_size
+What:		/sys/bus/platform/devices/*.ufs/hid/fragmented_size
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The total fragmented size in the device is reported through
+		this attribute.
+
+		The attribute is read only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/defrag_size
+What:		/sys/bus/platform/devices/*.ufs/hid/defrag_size
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The host sets the size to be defragmented by an HID
+		defragmentation operation.
+
+		The attribute is read/write.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/progress_ratio
+What:		/sys/bus/platform/devices/*.ufs/hid/progress_ratio
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		Defragmentation progress is reported by this attribute,
+		indicateds the ratio of the completed defragmentation size
+		over the requested defragmentation size.
+
+		====  ============================================
+		1     1%
+		...
+		100   100%
+		====  ============================================
+
+		The attribute is read only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/state
+What:		/sys/bus/platform/devices/*.ufs/hid/state
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The HID state is reported by this attribute.
+
+		====================   ===========================
+		idle			Idle(analysis required)
+		analysis_in_progress    Analysis in progress
+		defrag_required      	Defrag required
+		defrag_in_progress      Defrag in progress
+		defrag_completed      	Defrag completed
+		defrag_not_required     Defrag is not required
+		====================   ===========================
+
+		The attribute is read only.
diff --git a/drivers/ufs/core/ufs-sysfs.c b/drivers/ufs/core/ufs-sysfs.c
index de8b6acd4058..f162eb36f46b 100644
--- a/drivers/ufs/core/ufs-sysfs.c
+++ b/drivers/ufs/core/ufs-sysfs.c
@@ -87,6 +87,26 @@ static const char *ufs_wb_resize_status_to_string(enum wb_resize_status status)
 	}
 }
 
+static const char *ufs_hid_state_to_string(enum ufs_hid_state state)
+{
+	switch (state) {
+	case HID_IDLE:
+		return "idle";
+	case ANALYSIS_IN_PROGRESS:
+		return "analysis_in_progress";
+	case DEFRAG_REQUIRED:
+		return "defrag_required";
+	case DEFRAG_IN_PROGRESS:
+		return "defrag_in_progress";
+	case DEFRAG_COMPLETED:
+		return "defrag_completed";
+	case DEFRAG_IS_NOT_REQUIRED:
+		return "defrag_not_required";
+	default:
+		return "unknown";
+	}
+}
+
 static const char *ufshcd_uic_link_state_to_string(
 			enum uic_link_state state)
 {
@@ -1763,6 +1783,177 @@ static const struct attribute_group ufs_sysfs_attributes_group = {
 	.attrs = ufs_sysfs_attributes,
 };
 
+static int hid_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
+			enum attr_idn idn, u32 *attr_val)
+{
+	int ret;
+
+	down(&hba->host_sem);
+	if (!ufshcd_is_user_access_allowed(hba)) {
+		up(&hba->host_sem);
+		return -EBUSY;
+	}
+
+	ufshcd_rpm_get_sync(hba);
+	ret = ufshcd_query_attr(hba, opcode, idn, 0, 0, attr_val);
+	ufshcd_rpm_put_sync(hba);
+
+	up(&hba->host_sem);
+	return ret;
+}
+
+static const char * const hid_trigger_mode[] = {"disable", "enable"};
+
+static ssize_t analysis_trigger_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	int mode;
+	int ret;
+
+	mode = sysfs_match_string(hid_trigger_mode, buf);
+	if (mode < 0)
+		return -EINVAL;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_WO(analysis_trigger);
+
+static ssize_t defrag_trigger_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	int mode;
+	int ret;
+
+	mode = sysfs_match_string(hid_trigger_mode, buf);
+	if (mode < 0)
+		return -EINVAL;
+
+	if (mode)
+		mode = HID_ANALYSIS_AND_DEFRAG_ENABLE;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_WO(defrag_trigger);
+
+static ssize_t fragmented_size_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_AVAILABLE_SIZE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%u\n", value);
+}
+
+static DEVICE_ATTR_RO(fragmented_size);
+
+static ssize_t defrag_size_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_SIZE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%u\n", value);
+}
+
+static ssize_t defrag_size_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	if (kstrtou32(buf, 0, &value))
+		return -EINVAL;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_SIZE, &value);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_RW(defrag_size);
+
+static ssize_t progress_ratio_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_PROGRESS_RATIO, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%u\n", value);
+}
+
+static DEVICE_ATTR_RO(progress_ratio);
+
+static ssize_t state_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_STATE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%s\n", ufs_hid_state_to_string(value));
+}
+
+static DEVICE_ATTR_RO(state);
+
+static struct attribute *ufs_sysfs_hid[] = {
+	&dev_attr_analysis_trigger.attr,
+	&dev_attr_defrag_trigger.attr,
+	&dev_attr_fragmented_size.attr,
+	&dev_attr_defrag_size.attr,
+	&dev_attr_progress_ratio.attr,
+	&dev_attr_state.attr,
+	NULL,
+};
+
+static umode_t  ufs_sysfs_hid_is_visible(struct kobject *kobj,
+		struct attribute *attr, int n)
+{
+	struct device *dev = container_of(kobj, struct device, kobj);
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+
+	return	hba->dev_info.hid_sup ? attr->mode : 0;
+}
+
+static const struct attribute_group ufs_sysfs_hid_group = {
+	.name = "hid",
+	.attrs = ufs_sysfs_hid,
+	.is_visible = ufs_sysfs_hid_is_visible,
+};
+
 static const struct attribute_group *ufs_sysfs_groups[] = {
 	&ufs_sysfs_default_group,
 	&ufs_sysfs_capabilities_group,
@@ -1777,6 +1968,7 @@ static const struct attribute_group *ufs_sysfs_groups[] = {
 	&ufs_sysfs_string_descriptors_group,
 	&ufs_sysfs_flags_group,
 	&ufs_sysfs_attributes_group,
+	&ufs_sysfs_hid_group,
 	NULL,
 };
 
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 3e2097e65964..8ccd923a5761 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -8390,6 +8390,10 @@ static int ufs_get_device_desc(struct ufs_hba *hba)
 
 	dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP];
 
+	dev_info->hid_sup = get_unaligned_be32(desc_buf +
+				DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP) &
+				UFS_DEV_HID_SUPPORT;
+
 	model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
 
 	err = ufshcd_read_string_desc(hba, model_index,
diff --git a/include/ufs/ufs.h b/include/ufs/ufs.h
index c0c59a8f7256..e61caa40f7cd 100644
--- a/include/ufs/ufs.h
+++ b/include/ufs/ufs.h
@@ -182,6 +182,11 @@ enum attr_idn {
 	QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE        = 0x1F,
 	QUERY_ATTR_IDN_TIMESTAMP		= 0x30,
 	QUERY_ATTR_IDN_DEV_LVL_EXCEPTION_ID     = 0x34,
+	QUERY_ATTR_IDN_HID_DEFRAG_OPERATION	= 0x35,
+	QUERY_ATTR_IDN_HID_AVAILABLE_SIZE	= 0x36,
+	QUERY_ATTR_IDN_HID_SIZE			= 0x37,
+	QUERY_ATTR_IDN_HID_PROGRESS_RATIO	= 0x38,
+	QUERY_ATTR_IDN_HID_STATE		= 0x39,
 	QUERY_ATTR_IDN_WB_BUF_RESIZE_HINT	= 0x3C,
 	QUERY_ATTR_IDN_WB_BUF_RESIZE_EN		= 0x3D,
 	QUERY_ATTR_IDN_WB_BUF_RESIZE_STATUS	= 0x3E,
@@ -401,6 +406,7 @@ enum {
 	UFS_DEV_HPB_SUPPORT		= BIT(7),
 	UFS_DEV_WRITE_BOOSTER_SUP	= BIT(8),
 	UFS_DEV_LVL_EXCEPTION_SUP       = BIT(12),
+	UFS_DEV_HID_SUPPORT		= BIT(13),
 };
 #define UFS_DEV_HPB_SUPPORT_VERSION		0x310
 
@@ -466,6 +472,23 @@ enum ufs_ref_clk_freq {
 	REF_CLK_FREQ_INVAL	= -1,
 };
 
+/* bDefragOperation attribute values */
+enum ufs_hid_defrag_operation {
+	HID_ANALYSIS_AND_DEFRAG_DISABLE	= 0,
+	HID_ANALYSIS_ENABLE		= 1,
+	HID_ANALYSIS_AND_DEFRAG_ENABLE	= 2,
+};
+
+/* bHIDState attribute values */
+enum ufs_hid_state {
+	HID_IDLE		= 0,
+	ANALYSIS_IN_PROGRESS	= 1,
+	DEFRAG_REQUIRED		= 2,
+	DEFRAG_IN_PROGRESS	= 3,
+	DEFRAG_COMPLETED	= 4,
+	DEFRAG_IS_NOT_REQUIRED	= 5,
+};
+
 /* bWriteBoosterBufferResizeEn attribute */
 enum wb_resize_en {
 	WB_RESIZE_EN_IDLE	= 0,
@@ -625,6 +648,8 @@ struct ufs_dev_info {
 	u32 rtc_update_period;
 
 	u8 rtt_cap; /* bDeviceRTTCap */
+
+	bool hid_sup;
 };
 
 /*
-- 
2.48.1



From tsbogend at alpha.franken.de  Mon May 19 23:49:30 2025
From: tsbogend at alpha.franken.de (Thomas Bogendoerfer)
Date: Tue, 20 May 2025 08:49:30 +0200
Subject: [PATCH v5 0/7] Add EcoNet EN751221 MIPS platform support
In-Reply-To: <20250507134500.390547-1-cjd@cjdns.fr>
References: <20250507134500.390547-1-cjd@cjdns.fr>
Message-ID: <aCwl-nAMxjqjxRM6@alpha.franken.de>

On Wed, May 07, 2025 at 01:44:53PM +0000, Caleb James DeLisle wrote:
> EcoNet MIPS SoCs are big endian machines based on 34Kc and 1004Kc
> processors. They are found in xDSL and xPON modems, and contain PCM
> (VoIP), Ethernet, USB, GPIO, I2C, SPI (Flash), UART, and PCIe.
> 
> The EcoNet MIPS SoCs are divided broadly into two families, the
> EN751221 family based on the 34Kc, and the EN751627 family based on
> the 1004Kc. Individual SoCs within a family are very similar, only
> with different peripherals.
> 
> This patchset adds basic "boots to a console" support for the EN751221
> family and adds SmartFiber XP8421-B, a low cost commercially available
> board that is useful for testing and development.
> 
> Note that Airoha (AN7523, AN7581) is similar to EcoNet in terms of
> peripherals, and for historical reasons Airoha chips are sometimes
> referred to with the EN75xx prefix. However this is a different
> platform because Airoha chips are ARM based.
> 
> This patchset is against mips-next.
> 
> v4 -> v5
> * 2/7 clocksource/drivers: Add EcoNet Timer HPT driver:
>   * Improve explanation of HPT timer in changelog
>   * Move pr_info to pr_debug per recommendation
>   * Remove pointless debug on spurious interrupt
>   * Small code-style change
> 
> v3 -> v4
> * Rebase to 3b3704261e851e25983860e4c352f1f73786f4ab
> * Omit already accepted patches (thanks guys!):
>   - https://patchwork.kernel.org/project/linux-mips/patch/20250330170306.2584136-2-cjd at cjdns.fr/
>   - https://patchwork.kernel.org/project/linux-mips/patch/20250330170306.2584136-3-cjd at cjdns.fr/
>   - https://patchwork.kernel.org/project/linux-mips/patch/20250330170306.2584136-4-cjd at cjdns.fr/
> 
> v2 -> v3
> * econet,en751221-timer.yaml -> Improve code style
> * vendor-prefixes.yaml -> Correct alphabetic order
> * en751221.dtsi
>   - interrupt-controller code style
>   - serial: Explain reason for clock-frequency = <1843200>
> * v3->v3 diff provided for reference
>   - https://gist.github.com/cjdelisle/21c9f0cd225f499bdff3c574c7f185f2
> * CC: linux-mediatek at lists.infradead.org who may be interested.
> 
> v1 -> v2
> * Codestyle
>   - Apply codestyle from "The tip tree handbook" and recommendations
>   - Remove "_rai" and "_m" symbol suffixes which are not standard
> * irq-econet-en751221.c
>   - Use cleanup.h _guard() and _free()
>   - Separate irq_domain_ops from irq_chip, eliminating econet_intc struct
>   - Remove irqsave in econet_wreg, irqs are already disabled in mask/unmask
>   - Add explainatory comments
>   - Refactor shadow logic for clarity, e.g. INTC_NO_SHADOW -> NOT_PERCPU
>   - Improve error handling in case of invalid DTS
> * econet,timer-hpt.yaml
>   - Rename to econet,timer-en751221.yaml
>   - Impose rule: "reg" must have 1 item on EN751221 and 2 on EN751627
> * timer-econet-hpt.c
>   - Rename to timer-econet-en751221.c to follow naming scheme from DT
> * econet,en751221-intc.yaml
>   - Fix validation error from required: interrupt-parent
>   - shadow-interrupts -> switch to uint32-matrix for list of pairs
> * MAINTAINERS -> Fixed accidental F: MAINTAINERS
> * Replace "test image" with device SmartFiber-XP8421-B
> * Restructure arch/mips/econet/Kconfig per arch/mips/ralink example
> * v1->v2 diff is offered for reference:
>   - https://gist.github.com/cjdelisle/bb3acab78b5f70dcdfe5dd6338293efe
> 
> 
> Caleb James DeLisle (7):
>   dt-bindings: timer: Add EcoNet EN751221 "HPT" CPU Timer
>   clocksource/drivers: Add EcoNet Timer HPT driver
>   dt-bindings: mips: Add EcoNet platform binding
>   mips: Add EcoNet MIPS platform support
>   dt-bindings: vendor-prefixes: Add SmartFiber
>   mips: dts: Add EcoNet DTS with EN751221 and SmartFiber XP8421-B board
>   MAINTAINERS: Add entry for newly added EcoNet platform.
> 
>  .../devicetree/bindings/mips/econet.yaml      |  26 +++
>  .../bindings/timer/econet,en751221-timer.yaml |  80 +++++++
>  .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
>  MAINTAINERS                                   |  12 +
>  arch/mips/Kbuild.platforms                    |   1 +
>  arch/mips/Kconfig                             |  25 ++
>  arch/mips/boot/compressed/uart-16550.c        |   5 +
>  arch/mips/boot/dts/Makefile                   |   1 +
>  arch/mips/boot/dts/econet/Makefile            |   2 +
>  arch/mips/boot/dts/econet/en751221.dtsi       |  67 ++++++
>  .../econet/en751221_smartfiber_xp8421-b.dts   |  19 ++
>  arch/mips/econet/Kconfig                      |  48 ++++
>  arch/mips/econet/Makefile                     |   2 +
>  arch/mips/econet/Platform                     |   5 +
>  arch/mips/econet/init.c                       |  78 +++++++
>  drivers/clocksource/Kconfig                   |   8 +
>  drivers/clocksource/Makefile                  |   1 +
>  drivers/clocksource/timer-econet-en751221.c   | 216 ++++++++++++++++++
>  18 files changed, 598 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mips/econet.yaml
>  create mode 100644 Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
>  create mode 100644 arch/mips/boot/dts/econet/Makefile
>  create mode 100644 arch/mips/boot/dts/econet/en751221.dtsi
>  create mode 100644 arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts
>  create mode 100644 arch/mips/econet/Kconfig
>  create mode 100644 arch/mips/econet/Makefile
>  create mode 100644 arch/mips/econet/Platform
>  create mode 100644 arch/mips/econet/init.c
>  create mode 100644 drivers/clocksource/timer-econet-en751221.c

applied patches 3-7 to mips-next

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]


From jinjian.song at fibocom.com  Tue May 20 00:05:34 2025
From: jinjian.song at fibocom.com (Jinjian Song)
Date: Tue, 20 May 2025 15:05:34 +0800
Subject: [net v1] net: wwan: t7xx: Fix napi rx poll issue
In-Reply-To: <20250516084842.26c80cb5@kernel.org>
References: <20250515031743.246178-1-jinjian.song@fibocom.com> <20250515175251.58b5123f@kernel.org>
Message-ID: <20250516084842.26c80cb5@kernel.org>

>On Fri, 16 May 2025 15:30:38 +0800 Jinjian Song wrote:
>> It seems that a judgment is made every time ccmni_inst[x] is used in the driver,
>> and the synchronization on the 2 way might have been done when NAPI triggers
>> polling by napi_schedule and when WWAN trigger dellink. 
>
>Synchronization is about ensuring that the condition validating
>by the if() remains true for as long as necessary.
>You need to wrap the read with READ_ONCE() and write with WRITE_ONCE().
>The rest if fine because netdev unregister sync against NAPIs in flight.
>

Hi Jakub,
  I think I got your point.
  I can use the atomic_t usage in struct t7xx_ccmni to synchronization.
  
  static void t7xx_ccmni_wwan_dellink(...) {

  [...]

  if (WARN_ON(ctlb->ccmni_inst[if_id] != ccmni))
    return;

  unregister_netdevice(dev);

  //Add here use this variable(ccmnii->usage) to synchronization

  if (atomic_read(&ccmni->usage) == 0)
     ccmni == NULL;

  }

  How about this modify?

Thanks.

Jinjian,
Best Regards.


From alok.a.tiwari at oracle.com  Tue May 20 00:45:18 2025
From: alok.a.tiwari at oracle.com (ALOK TIWARI)
Date: Tue, 20 May 2025 13:15:18 +0530
Subject: [PATCH v4] ufs: core: Add HID support
In-Reply-To: <20250520063512.213-1-tanghuan@vivo.com>
References: <20250520063512.213-1-tanghuan@vivo.com>
Message-ID: <8faf7a11-b312-4062-89a5-8aff192ee1da@oracle.com>



> +What:		/sys/bus/platform/drivers/ufshcd/*/hid/progress_ratio
> +What:		/sys/bus/platform/devices/*.ufs/hid/progress_ratio
> +Date:		May 2025
> +Contact:	Huan Tang <tanghuan at vivo.com>
> +Description:
> +		Defragmentation progress is reported by this attribute,
> +		indicateds the ratio of the completed defragmentation size

typo indicateds -> indicates

> +		over the requested defragmentation size.
> +
> +		====  ============================================
> +		1     1%
> +		...
> +		100   100%
> +		====  ============================================
> +
> +		The attribute is read only.
> +
> +What:		/sys/bus/platform/drivers/ufshcd/*/hid/state
> +What:		/sys/bus/platform/devices/*.ufs/hid/state
> +Date:		May 2025
> +Contact:	Huan Tang <tanghuan at vivo.com>
> +Description:
> +		The HID state is reported by this attribute.
> +
> +		====================   ===========================
> +		idle			Idle(analysis required)

Idle (analysis required)

> +		analysis_in_progress    Analysis in progress
> +		defrag_required      	Defrag required
> +		defrag_in_progress      Defrag in progress
> +		defrag_completed      	Defrag completed
> +		defrag_not_required     Defrag is not required
> +		====================   ===========================
> +
> +		The attribute is read only.
> diff --git a/drivers/ufs/core/ufs-sysfs.c b/drivers/ufs/core/ufs-sysfs.c
> index de8b6acd4058..f162eb36f46b 100644
> --- a/drivers/ufs/core/ufs-sysfs.c
> +++ b/drivers/ufs/core/ufs-sysfs.c
> @@ -87,6 +87,26 @@ static const char *ufs_wb_resize_status_to_string(enum wb_resize_status status)
>   	}
>   }
>   
> +static const char *ufs_hid_state_to_string(enum ufs_hid_state state)
> +{
> +	switch (state) {
> +	case HID_IDLE:
> +		return "idle";
> +	case ANALYSIS_IN_PROGRESS:
> +		return "analysis_in_progress";
> +	case DEFRAG_REQUIRED:
> +		return "defrag_required";
> +	case DEFRAG_IN_PROGRESS:
> +		return "defrag_in_progress";
> +	case DEFRAG_COMPLETED:
> +		return "defrag_completed";
> +	case DEFRAG_IS_NOT_REQUIRED:
> +		return "defrag_not_required";
> +	default:
> +		return "unknown";
> +	}
> +}
> +
>   static const char *ufshcd_uic_link_state_to_string(
>   			enum uic_link_state state)
>   {
> @@ -1763,6 +1783,177 @@ static const struct attribute_group ufs_sysfs_attributes_group = {
>   	.attrs = ufs_sysfs_attributes,
>   };
>   
> +static int hid_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
> +			enum attr_idn idn, u32 *attr_val)
> +{
> +	int ret;
> +
> +	down(&hba->host_sem);
> +	if (!ufshcd_is_user_access_allowed(hba)) {
> +		up(&hba->host_sem);
> +		return -EBUSY;
> +	}
> +
> +	ufshcd_rpm_get_sync(hba);
> +	ret = ufshcd_query_attr(hba, opcode, idn, 0, 0, attr_val);
> +	ufshcd_rpm_put_sync(hba);
> +
> +	up(&hba->host_sem);
> +	return ret;
> +}
> +
> +static const char * const hid_trigger_mode[] = {"disable", "enable"};
> +
> +static ssize_t analysis_trigger_store(struct device *dev,
> +		struct device_attribute *attr, const char *buf, size_t count)
> +{
> +	struct ufs_hba *hba = dev_get_drvdata(dev);
> +	int mode;
> +	int ret;
> +
> +	mode = sysfs_match_string(hid_trigger_mode, buf);
> +	if (mode < 0)
> +		return -EINVAL;
> +
> +	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
> +			QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
> +
> +	return ret < 0 ? ret : count;
> +}
> +
> +static DEVICE_ATTR_WO(analysis_trigger);
> +
> +static ssize_t defrag_trigger_store(struct device *dev,
> +		struct device_attribute *attr, const char *buf, size_t count)
> +{
> +	struct ufs_hba *hba = dev_get_drvdata(dev);
> +	int mode;
> +	int ret;
> +
> +	mode = sysfs_match_string(hid_trigger_mode, buf);
> +	if (mode < 0)
> +		return -EINVAL;
> +
> +	if (mode)
> +		mode = HID_ANALYSIS_AND_DEFRAG_ENABLE;
> +
> +	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
> +			QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
> +
> +	return ret < 0 ? ret : count;
> +}
> +
> +static DEVICE_ATTR_WO(defrag_trigger);
> +
> +static ssize_t fragmented_size_show(struct device *dev,
> +		struct device_attribute *attr, char *buf)
> +{
> +	struct ufs_hba *hba = dev_get_drvdata(dev);
> +	u32 value;
> +	int ret;
> +
> +	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
> +			QUERY_ATTR_IDN_HID_AVAILABLE_SIZE, &value);
> +	if (ret)
> +		return ret;
> +
> +	return sysfs_emit(buf, "%u\n", value);
> +}
> +
> +static DEVICE_ATTR_RO(fragmented_size);
> +
> +static ssize_t defrag_size_show(struct device *dev,
> +		struct device_attribute *attr, char *buf)
> +{
> +	struct ufs_hba *hba = dev_get_drvdata(dev);
> +	u32 value;
> +	int ret;
> +
> +	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
> +			QUERY_ATTR_IDN_HID_SIZE, &value);
> +	if (ret)
> +		return ret;
> +
> +	return sysfs_emit(buf, "%u\n", value);
> +}
> +
> +static ssize_t defrag_size_store(struct device *dev,
> +		struct device_attribute *attr, const char *buf, size_t count)
> +{
> +	struct ufs_hba *hba = dev_get_drvdata(dev);
> +	u32 value;
> +	int ret;
> +
> +	if (kstrtou32(buf, 0, &value))
> +		return -EINVAL;
> +
> +	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
> +			QUERY_ATTR_IDN_HID_SIZE, &value);
> +
> +	return ret < 0 ? ret : count;
> +}
> +
> +static DEVICE_ATTR_RW(defrag_size);
> +
> +static ssize_t progress_ratio_show(struct device *dev,
> +		struct device_attribute *attr, char *buf)
> +{
> +	struct ufs_hba *hba = dev_get_drvdata(dev);
> +	u32 value;
> +	int ret;
> +
> +	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
> +			QUERY_ATTR_IDN_HID_PROGRESS_RATIO, &value);
> +	if (ret)
> +		return ret;
> +
> +	return sysfs_emit(buf, "%u\n", value);
> +}
> +
> +static DEVICE_ATTR_RO(progress_ratio);
> +
> +static ssize_t state_show(struct device *dev,
> +		struct device_attribute *attr, char *buf)
> +{
> +	struct ufs_hba *hba = dev_get_drvdata(dev);
> +	u32 value;
> +	int ret;
> +
> +	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
> +			QUERY_ATTR_IDN_HID_STATE, &value);
> +	if (ret)
> +		return ret;
> +
> +	return sysfs_emit(buf, "%s\n", ufs_hid_state_to_string(value));
> +}
> +
> +static DEVICE_ATTR_RO(state);
> +
> +static struct attribute *ufs_sysfs_hid[] = {
> +	&dev_attr_analysis_trigger.attr,
> +	&dev_attr_defrag_trigger.attr,
> +	&dev_attr_fragmented_size.attr,
> +	&dev_attr_defrag_size.attr,
> +	&dev_attr_progress_ratio.attr,
> +	&dev_attr_state.attr,
> +	NULL,
> +};
> +
> +static umode_t  ufs_sysfs_hid_is_visible(struct kobject *kobj,

remove extra ' ' after umode_t

> +		struct attribute *attr, int n)
> +{
> +	struct device *dev = container_of(kobj, struct device, kobj);
> +	struct ufs_hba *hba = dev_get_drvdata(dev);
> +
> +	return	hba->dev_info.hid_sup ? attr->mode : 0;
> +}
> +
> +static const struct attribute_group ufs_sysfs_hid_group = {
> +	.name = "hid",
> +	.attrs = ufs_sysfs_hid,
> +	.is_visible = ufs_sysfs_hid_is_visible,
> +};
> +
>   static const struct attribute_group *ufs_sysfs_groups[] = {
>   	&ufs_sysfs_default_group,
>   	&ufs_sysfs_capabilities_group,
> @@ -1777,6 +1968,7 @@ static const struct attribute_group *ufs_sysfs_groups[] = {
>   	&ufs_sysfs_string_descriptors_group,
>   	&ufs_sysfs_flags_group,
>   	&ufs_sysfs_attributes_group,
> +	&ufs_sysfs_hid_group,
>   	NULL,
>   };
>   
> diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
> index 3e2097e65964..8ccd923a5761 100644
> --- a/drivers/ufs/core/ufshcd.c
> +++ b/drivers/ufs/core/ufshcd.c
> @@ -8390,6 +8390,10 @@ static int ufs_get_device_desc(struct ufs_hba *hba)
>   
>   	dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP];
>   
> +	dev_info->hid_sup = get_unaligned_be32(desc_buf +
> +				DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP) &
> +				UFS_DEV_HID_SUPPORT;
> +
>   	model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
>   
>   	err = ufshcd_read_string_desc(hba, model_index,
> diff --git a/include/ufs/ufs.h b/include/ufs/ufs.h
> index c0c59a8f7256..e61caa40f7cd 100644
> --- a/include/ufs/ufs.h
> +++ b/include/ufs/ufs.h
> @@ -182,6 +182,11 @@ enum attr_idn {
>   	QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE        = 0x1F,
>   	QUERY_ATTR_IDN_TIMESTAMP		= 0x30,
>   	QUERY_ATTR_IDN_DEV_LVL_EXCEPTION_ID     = 0x34,
> +	QUERY_ATTR_IDN_HID_DEFRAG_OPERATION	= 0x35,
> +	QUERY_ATTR_IDN_HID_AVAILABLE_SIZE	= 0x36,
> +	QUERY_ATTR_IDN_HID_SIZE			= 0x37,
> +	QUERY_ATTR_IDN_HID_PROGRESS_RATIO	= 0x38,
> +	QUERY_ATTR_IDN_HID_STATE		= 0x39,
>   	QUERY_ATTR_IDN_WB_BUF_RESIZE_HINT	= 0x3C,
>   	QUERY_ATTR_IDN_WB_BUF_RESIZE_EN		= 0x3D,
>   	QUERY_ATTR_IDN_WB_BUF_RESIZE_STATUS	= 0x3E,
> @@ -401,6 +406,7 @@ enum {
>   	UFS_DEV_HPB_SUPPORT		= BIT(7),
>   	UFS_DEV_WRITE_BOOSTER_SUP	= BIT(8),
>   	UFS_DEV_LVL_EXCEPTION_SUP       = BIT(12),
> +	UFS_DEV_HID_SUPPORT		= BIT(13),
>   };
>   #define UFS_DEV_HPB_SUPPORT_VERSION		0x310
>   
> @@ -466,6 +472,23 @@ enum ufs_ref_clk_freq {
>   	REF_CLK_FREQ_INVAL	= -1,
>   };
>   
> +/* bDefragOperation attribute values */
> +enum ufs_hid_defrag_operation {
> +	HID_ANALYSIS_AND_DEFRAG_DISABLE	= 0,
> +	HID_ANALYSIS_ENABLE		= 1,
> +	HID_ANALYSIS_AND_DEFRAG_ENABLE	= 2,
> +};
> +
> +/* bHIDState attribute values */
> +enum ufs_hid_state {
> +	HID_IDLE		= 0,
> +	ANALYSIS_IN_PROGRESS	= 1,
> +	DEFRAG_REQUIRED		= 2,
> +	DEFRAG_IN_PROGRESS	= 3,
> +	DEFRAG_COMPLETED	= 4,
> +	DEFRAG_IS_NOT_REQUIRED	= 5,

_IS_ is extra in an enum label, or sound redundant.
I think DEFRAG_NOT_REQUIRED sounds cleaner, especially since it's used 
with return "defrag_not_required".

> +};
> +
>   /* bWriteBoosterBufferResizeEn attribute */
>   enum wb_resize_en {
>   	WB_RESIZE_EN_IDLE	= 0,
> @@ -625,6 +648,8 @@ struct ufs_dev_info {
>   	u32 rtc_update_period;
>   
>   	u8 rtt_cap; /* bDeviceRTTCap */
> +
> +	bool hid_sup;
>   };
>   
>   /*


Thanks,
Alok


From angelogioacchino.delregno at collabora.com  Tue May 20 02:15:13 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 11:15:13 +0200
Subject: [PATCH] pinctrl: mediatek: eint: Fix invalid pointer dereference
 for v1 platforms
In-Reply-To: <20250519-genio-350-eint-null-ptr-deref-fix-v1-1-07445d6d22c3@collabora.com>
References: <20250519-genio-350-eint-null-ptr-deref-fix-v1-1-07445d6d22c3@collabora.com>
Message-ID: <2f7dffb0-cddd-44c5-a205-30dbc13f9891@collabora.com>

Il 19/05/25 21:38, N?colas F. R. A. Prado ha scritto:
> Commit 3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple
> addresses") introduced an access to the 'soc' field of struct
> mtk_pinctrl in mtk_eint_do_init() and for that an include of
> pinctrl-mtk-common-v2.h.
> 
> However, pinctrl drivers relying on the v1 common driver include
> pinctrl-mtk-common.h instead, which provides another definition of
> struct mtk_pinctrl that does not contain an 'soc' field.
> 
> Since mtk_eint_do_init() can be called both by v1 and v2 drivers, it
> will now try to dereference an invalid pointer when called on v1
> platforms. This has been observed on Genio 350 EVK (MT8365), which
> crashes very early in boot (the kernel trace can only be seen with
> earlycon).
> 
> In order to fix this, given that this if code block is only relevant for
> platforms with multiple EINT bases, and the previous if block already
> handles the single base case, add an else statement so this if condition
> will never even be evaluated on platforms with a single EINT base, which
> covers all v1 platforms following commit fe412e3a6c97 ("pinctrl:
> mediatek: common-v1: Fix EINT breakage on older controllers").
> 
> Fixes: 3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple addresses")
> Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>

I say that this is going to backfire next time.

I would rather propose, instead....

int mtk_eint_do_init(struct mtk_eint *eint, const struct mtk_eint_pin *eint_pin)
{
	...

	[if (or) else if] (eint_pin) {
		eint->pins = eint_pin;
		... etc
	}
}

...so that we avoid having this issue about referencing two different structures
called with the same name (which is bad from the principle anyway), and no more
mistakes around that in the future.

This also means that we can remove the inclusion of pinctrl-mtk-common-v2.h from
the mtk-eint.c file, as that's the right thing to do: eint should be standalone
and should not depend on ambiguous definitions from pinctrl-mtk-common(-v2).h.

Cheers,
Angelo

> ---
>   drivers/pinctrl/mediatek/mtk-eint.c | 4 +---
>   1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c
> index 16af6a47028e67bb53db4041a37ebbbb8b9a1e43..9114e0cd9def1bc65558c67317abe67ba63ef1f6 100644
> --- a/drivers/pinctrl/mediatek/mtk-eint.c
> +++ b/drivers/pinctrl/mediatek/mtk-eint.c
> @@ -531,9 +531,7 @@ int mtk_eint_do_init(struct mtk_eint *eint)
>   			eint->pins[i].index = i;
>   			eint->pins[i].debounce = (i < eint->hw->db_cnt) ? 1 : 0;
>   		}
> -	}
> -
> -	if (hw && hw->soc && hw->soc->eint_pin) {
> +	} else if (hw && hw->soc && hw->soc->eint_pin) {
>   		eint->pins = hw->soc->eint_pin;
>   		for (i = 0; i < eint->hw->ap_num; i++) {
>   			inst = eint->pins[i].instance;
> 
> ---
> base-commit: 8566fc3b96539e3235909d6bdda198e1282beaed
> change-id: 20250519-genio-350-eint-null-ptr-deref-fix-1a163aa9ad84
> 
> Best regards,




From tanghuan at vivo.com  Tue May 20 02:40:54 2025
From: tanghuan at vivo.com (Huan Tang)
Date: Tue, 20 May 2025 17:40:54 +0800
Subject: [PATCH v5] ufs: core: Add HID support
Message-ID: <20250520094054.313-1-tanghuan@vivo.com>

Follow JESD220G, support HID(Host Initiated Defragmentation)
through sysfs, the relevant sysfs nodes are as follows:
	1.analysis_trigger
	2.defrag_trigger
	3.fragmented_size
	4.defrag_size
	5.progress_ratio
	6.state
The detailed definition	of the six nodes can be	found in the sysfs
documentation.

HID's execution policy is given to user-space.

Signed-off-by: Huan Tang <tanghuan at vivo.com>
Signed-off-by: Wenxing Cheng <wenxing.cheng at vivo.com>
---
Changelog
===
v4 - > v5:
	1.Fixed a typo in "indicates"
	2."DEFRAG_IS_NOT_REQUIRED" -> "DEFRAG_NOT_REQUIRED"
	3.Fix some coding style issues
v3 - > v4:
	1.Move the changelog description under "---"
v2 - > v3:
	1.Remove the "ufs_" prefix from directory name
	2.Remove the "hid_" prefix from node names
	3.Make "ufs" appear only once in the HID group name
	4.Add "is_visible" callback for "ufs_sysfs_hid_group"
v1 - > v2:
	1.Refactor the HID code according to Bart and Peter and
	Arvi's suggestions

v4
	https://lore.kernel.org/all/20250520063512.213-1-tanghuan at vivo.com/
v3
	https://lore.kernel.org/all/20250519022912.292-1-tanghuan at vivo.com/
v2
	https://lore.kernel.org/all/20250512131519.138-1-tanghuan at vivo.com/
v1
	https://lore.kernel.org/all/20250417125008.123-1-tanghuan at vivo.com/

 Documentation/ABI/testing/sysfs-driver-ufs |  83 +++++++++
 drivers/ufs/core/ufs-sysfs.c               | 192 +++++++++++++++++++++
 drivers/ufs/core/ufshcd.c                  |   4 +
 include/ufs/ufs.h                          |  25 +++
 4 files changed, 304 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-driver-ufs b/Documentation/ABI/testing/sysfs-driver-ufs
index d4140dc6c5ba..f3de8c521bbd 100644
--- a/Documentation/ABI/testing/sysfs-driver-ufs
+++ b/Documentation/ABI/testing/sysfs-driver-ufs
@@ -1685,3 +1685,86 @@ Description:
 		================  ========================================
 
 		The file is read only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/analysis_trigger
+What:		/sys/bus/platform/devices/*.ufs/hid/analysis_trigger
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The host can enable or disable HID analysis operation.
+
+		=======  =========================================
+		disable   disable HID analysis operation
+		enable    enable HID analysis operation
+		=======  =========================================
+
+		The file is write only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/defrag_trigger
+What:		/sys/bus/platform/devices/*.ufs/hid/defrag_trigger
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The host can enable or disable HID defragmentation operation.
+
+		=======  =========================================
+		disable   disable HID defragmentation operation
+		enable    enable HID defragmentation operation
+		=======  =========================================
+
+		The attribute is write only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/fragmented_size
+What:		/sys/bus/platform/devices/*.ufs/hid/fragmented_size
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The total fragmented size in the device is reported through
+		this attribute.
+
+		The attribute is read only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/defrag_size
+What:		/sys/bus/platform/devices/*.ufs/hid/defrag_size
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The host sets the size to be defragmented by an HID
+		defragmentation operation.
+
+		The attribute is read/write.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/progress_ratio
+What:		/sys/bus/platform/devices/*.ufs/hid/progress_ratio
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		Defragmentation progress is reported by this attribute,
+		indicates the ratio of the completed defragmentation size
+		over the requested defragmentation size.
+
+		====  ============================================
+		1     1%
+		...
+		100   100%
+		====  ============================================
+
+		The attribute is read only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/state
+What:		/sys/bus/platform/devices/*.ufs/hid/state
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The HID state is reported by this attribute.
+
+		====================   ===========================
+		idle			Idle (analysis required)
+		analysis_in_progress    Analysis in progress
+		defrag_required      	Defrag required
+		defrag_in_progress      Defrag in progress
+		defrag_completed      	Defrag completed
+		defrag_not_required     Defrag is not required
+		====================   ===========================
+
+		The attribute is read only.
diff --git a/drivers/ufs/core/ufs-sysfs.c b/drivers/ufs/core/ufs-sysfs.c
index de8b6acd4058..978374b12931 100644
--- a/drivers/ufs/core/ufs-sysfs.c
+++ b/drivers/ufs/core/ufs-sysfs.c
@@ -87,6 +87,26 @@ static const char *ufs_wb_resize_status_to_string(enum wb_resize_status status)
 	}
 }
 
+static const char *ufs_hid_state_to_string(enum ufs_hid_state state)
+{
+	switch (state) {
+	case HID_IDLE:
+		return "idle";
+	case ANALYSIS_IN_PROGRESS:
+		return "analysis_in_progress";
+	case DEFRAG_REQUIRED:
+		return "defrag_required";
+	case DEFRAG_IN_PROGRESS:
+		return "defrag_in_progress";
+	case DEFRAG_COMPLETED:
+		return "defrag_completed";
+	case DEFRAG_NOT_REQUIRED:
+		return "defrag_not_required";
+	default:
+		return "unknown";
+	}
+}
+
 static const char *ufshcd_uic_link_state_to_string(
 			enum uic_link_state state)
 {
@@ -1763,6 +1783,177 @@ static const struct attribute_group ufs_sysfs_attributes_group = {
 	.attrs = ufs_sysfs_attributes,
 };
 
+static int hid_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
+			enum attr_idn idn, u32 *attr_val)
+{
+	int ret;
+
+	down(&hba->host_sem);
+	if (!ufshcd_is_user_access_allowed(hba)) {
+		up(&hba->host_sem);
+		return -EBUSY;
+	}
+
+	ufshcd_rpm_get_sync(hba);
+	ret = ufshcd_query_attr(hba, opcode, idn, 0, 0, attr_val);
+	ufshcd_rpm_put_sync(hba);
+
+	up(&hba->host_sem);
+	return ret;
+}
+
+static const char * const hid_trigger_mode[] = {"disable", "enable"};
+
+static ssize_t analysis_trigger_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	int mode;
+	int ret;
+
+	mode = sysfs_match_string(hid_trigger_mode, buf);
+	if (mode < 0)
+		return -EINVAL;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_WO(analysis_trigger);
+
+static ssize_t defrag_trigger_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	int mode;
+	int ret;
+
+	mode = sysfs_match_string(hid_trigger_mode, buf);
+	if (mode < 0)
+		return -EINVAL;
+
+	if (mode)
+		mode = HID_ANALYSIS_AND_DEFRAG_ENABLE;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_WO(defrag_trigger);
+
+static ssize_t fragmented_size_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_AVAILABLE_SIZE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%u\n", value);
+}
+
+static DEVICE_ATTR_RO(fragmented_size);
+
+static ssize_t defrag_size_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_SIZE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%u\n", value);
+}
+
+static ssize_t defrag_size_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	if (kstrtou32(buf, 0, &value))
+		return -EINVAL;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_SIZE, &value);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_RW(defrag_size);
+
+static ssize_t progress_ratio_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_PROGRESS_RATIO, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%u\n", value);
+}
+
+static DEVICE_ATTR_RO(progress_ratio);
+
+static ssize_t state_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_STATE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%s\n", ufs_hid_state_to_string(value));
+}
+
+static DEVICE_ATTR_RO(state);
+
+static struct attribute *ufs_sysfs_hid[] = {
+	&dev_attr_analysis_trigger.attr,
+	&dev_attr_defrag_trigger.attr,
+	&dev_attr_fragmented_size.attr,
+	&dev_attr_defrag_size.attr,
+	&dev_attr_progress_ratio.attr,
+	&dev_attr_state.attr,
+	NULL,
+};
+
+static umode_t ufs_sysfs_hid_is_visible(struct kobject *kobj,
+		struct attribute *attr, int n)
+{
+	struct device *dev = container_of(kobj, struct device, kobj);
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+
+	return	hba->dev_info.hid_sup ? attr->mode : 0;
+}
+
+static const struct attribute_group ufs_sysfs_hid_group = {
+	.name = "hid",
+	.attrs = ufs_sysfs_hid,
+	.is_visible = ufs_sysfs_hid_is_visible,
+};
+
 static const struct attribute_group *ufs_sysfs_groups[] = {
 	&ufs_sysfs_default_group,
 	&ufs_sysfs_capabilities_group,
@@ -1777,6 +1968,7 @@ static const struct attribute_group *ufs_sysfs_groups[] = {
 	&ufs_sysfs_string_descriptors_group,
 	&ufs_sysfs_flags_group,
 	&ufs_sysfs_attributes_group,
+	&ufs_sysfs_hid_group,
 	NULL,
 };
 
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 3e2097e65964..8ccd923a5761 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -8390,6 +8390,10 @@ static int ufs_get_device_desc(struct ufs_hba *hba)
 
 	dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP];
 
+	dev_info->hid_sup = get_unaligned_be32(desc_buf +
+				DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP) &
+				UFS_DEV_HID_SUPPORT;
+
 	model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
 
 	err = ufshcd_read_string_desc(hba, model_index,
diff --git a/include/ufs/ufs.h b/include/ufs/ufs.h
index c0c59a8f7256..63af47c4e9ed 100644
--- a/include/ufs/ufs.h
+++ b/include/ufs/ufs.h
@@ -182,6 +182,11 @@ enum attr_idn {
 	QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE        = 0x1F,
 	QUERY_ATTR_IDN_TIMESTAMP		= 0x30,
 	QUERY_ATTR_IDN_DEV_LVL_EXCEPTION_ID     = 0x34,
+	QUERY_ATTR_IDN_HID_DEFRAG_OPERATION	= 0x35,
+	QUERY_ATTR_IDN_HID_AVAILABLE_SIZE	= 0x36,
+	QUERY_ATTR_IDN_HID_SIZE			= 0x37,
+	QUERY_ATTR_IDN_HID_PROGRESS_RATIO	= 0x38,
+	QUERY_ATTR_IDN_HID_STATE		= 0x39,
 	QUERY_ATTR_IDN_WB_BUF_RESIZE_HINT	= 0x3C,
 	QUERY_ATTR_IDN_WB_BUF_RESIZE_EN		= 0x3D,
 	QUERY_ATTR_IDN_WB_BUF_RESIZE_STATUS	= 0x3E,
@@ -401,6 +406,7 @@ enum {
 	UFS_DEV_HPB_SUPPORT		= BIT(7),
 	UFS_DEV_WRITE_BOOSTER_SUP	= BIT(8),
 	UFS_DEV_LVL_EXCEPTION_SUP       = BIT(12),
+	UFS_DEV_HID_SUPPORT		= BIT(13),
 };
 #define UFS_DEV_HPB_SUPPORT_VERSION		0x310
 
@@ -466,6 +472,23 @@ enum ufs_ref_clk_freq {
 	REF_CLK_FREQ_INVAL	= -1,
 };
 
+/* bDefragOperation attribute values */
+enum ufs_hid_defrag_operation {
+	HID_ANALYSIS_AND_DEFRAG_DISABLE	= 0,
+	HID_ANALYSIS_ENABLE		= 1,
+	HID_ANALYSIS_AND_DEFRAG_ENABLE	= 2,
+};
+
+/* bHIDState attribute values */
+enum ufs_hid_state {
+	HID_IDLE		= 0,
+	ANALYSIS_IN_PROGRESS	= 1,
+	DEFRAG_REQUIRED		= 2,
+	DEFRAG_IN_PROGRESS	= 3,
+	DEFRAG_COMPLETED	= 4,
+	DEFRAG_NOT_REQUIRED	= 5,
+};
+
 /* bWriteBoosterBufferResizeEn attribute */
 enum wb_resize_en {
 	WB_RESIZE_EN_IDLE	= 0,
@@ -625,6 +648,8 @@ struct ufs_dev_info {
 	u32 rtc_update_period;
 
 	u8 rtt_cap; /* bDeviceRTTCap */
+
+	bool hid_sup;
 };
 
 /*
-- 
2.48.1



From angelogioacchino.delregno at collabora.com  Tue May 20 02:44:04 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 11:44:04 +0200
Subject: [PATCH] arm64: defconfig: Enable configs for MediaTek Genio
 EVK boards
In-Reply-To: <20250513-genio-defconfig-v1-1-c3862f91b6b2@collabora.com>
References: <20250513-genio-defconfig-v1-1-c3862f91b6b2@collabora.com>
Message-ID: <174773424476.2901578.7109647684484482687.b4-ty@collabora.com>

On Tue, 13 May 2025 16:59:41 -0400, N?colas F. R. A. Prado wrote:
> Enable the missing configs to get all devices on the MediaTek Genio
> 1200, 700, 510 and 350 EVK boards probing, as indicated by the DT
> kselftest.
> 
> This includes support for:
> 
> Genio 1200/700/510/350:
> * MT6359/MT6357 PMICs Auxiliary ADC
> 
> [...]

Applied to v6.15-next/dts64, thanks!

[1/1] arm64: defconfig: Enable configs for MediaTek Genio EVK boards
      (no commit info)

Cheers,
Angelo




From angelogioacchino.delregno at collabora.com  Tue May 20 02:44:03 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 11:44:03 +0200
Subject: [PATCH v4] arm64: defconfig: mediatek: enable PHY drivers
In-Reply-To: <20250512131933.1247830-1-vignesh.raman@collabora.com>
References: <20250512131933.1247830-1-vignesh.raman@collabora.com>
Message-ID: <174773424323.2901578.2896521674718860573.b4-ty@collabora.com>

On Mon, 12 May 2025 18:49:24 +0530, Vignesh Raman wrote:
> The mediatek display driver fails to probe on mt8173-elm-hana and
> mt8183-kukui-jacuzzi-juniper-sku16 in v6.14-rc4 due to missing PHY
> configurations.
> 
> Commit 924d66011f24 ("drm/mediatek: stop selecting foreign drivers")
> stopped selecting the MediaTek PHY drivers, requiring them to be
> explicitly enabled in defconfig.
> 
> [...]

Applied to v6.15-next/dts64, thanks!

[1/1] arm64: defconfig: mediatek: enable PHY drivers
      (no commit info)

Cheers,
Angelo




From angelogioacchino.delregno at collabora.com  Tue May 20 02:44:49 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 11:44:49 +0200
Subject: [PATCH] arm64: defconfig: Enable configs for MediaTek Genio EVK
 boards
In-Reply-To: <174773424476.2901578.7109647684484482687.b4-ty@collabora.com>
References: <20250513-genio-defconfig-v1-1-c3862f91b6b2@collabora.com>
 <174773424476.2901578.7109647684484482687.b4-ty@collabora.com>
Message-ID: <c3162ca8-2539-409f-885e-a08696c72e27@collabora.com>

Il 20/05/25 11:44, AngeloGioacchino Del Regno ha scritto:
> On Tue, 13 May 2025 16:59:41 -0400, N?colas F. R. A. Prado wrote:
>> Enable the missing configs to get all devices on the MediaTek Genio
>> 1200, 700, 510 and 350 EVK boards probing, as indicated by the DT
>> kselftest.
>>
>> This includes support for:
>>
>> Genio 1200/700/510/350:
>> * MT6359/MT6357 PMICs Auxiliary ADC
>>
>> [...]
> 
> Applied to v6.15-next/dts64, thanks!

Wrong branch, it's v6.15-next/defconfig, sorry :-)

> 
> [1/1] arm64: defconfig: Enable configs for MediaTek Genio EVK boards
>        (no commit info)
> 
> Cheers,
> Angelo
> 
> 




From angelogioacchino.delregno at collabora.com  Tue May 20 02:47:38 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 11:47:38 +0200
Subject: (subset) [PATCH v4 0/8] Add Bananapi R4 variants and add xsphy
In-Reply-To: <20250422132438.15735-1-linux@fw-web.de>
References: <20250422132438.15735-1-linux@fw-web.de>
Message-ID: <174773445869.2947010.18205156294642701979.b4-ty@collabora.com>

On Tue, 22 Apr 2025 15:24:23 +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w at public-files.de>
> 
> With this series i continue the mt7988/bananapi-r4 dts upstream work
> 
> changes in v4:
> - changes based on review comments in v3 (mostly bindings)
> - changed topmisc unit address to match reg
> 
> [...]

Applied to v6.15-next/dts64, thanks!

[1/8] dt-bindings: arm: mediatek: add bpi-r4 2g5 phy variant
      commit: dedef1ddbd1bb8e36530626f75eaba786a818dfe
[2/8] arm64: dts: mediatek: mt7988a-bpi-r4: allow hw variants of bpi-r4
      commit: 2bec30e8fc935b0868e87c32685e6f04190b1390
[7/8] arm64: dts: mediatek: mt7988: Add xsphy for ssusb0/pcie2
      commit: 45885a2c0bd8a6e91adb2c8897880dca228850e8
[8/8] arm64: dts: mediatek: mt7988a-bpi-r4: enable xsphy
      commit: ba0f084948e1f273c6264b1c8cc3cbed814f3b62

Cheers,
Angelo




From tanghuan at vivo.com  Tue May 20 02:48:01 2025
From: tanghuan at vivo.com (Huan Tang)
Date: Tue, 20 May 2025 17:48:01 +0800
Subject: [PATCH v4] ufs: core: Add HID support
In-Reply-To: <8faf7a11-b312-4062-89a5-8aff192ee1da@oracle.com>
References: <8faf7a11-b312-4062-89a5-8aff192ee1da@oracle.com>
Message-ID: <20250520094801.411-1-tanghuan@vivo.com>

Hi alok sir,

Thank you for your comments and guidance???
The v5 patch???
https://lore.kernel.org/all/20250520094054.313-1-tanghuan at vivo.com/

> typo indicateds -> indicates
>
> Idle (analysis required)
>
> remove extra ' ' after umode_t
>
> _IS_ is extra in an enum label, or sound redundant.
> I think DEFRAG_NOT_REQUIRED sounds cleaner, especially since it's used 
> with return "defrag_not_required".
OK! It has been modified in the v5 patch.

Thanks
Huan




From angelogioacchino.delregno at collabora.com  Tue May 20 03:17:35 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 12:17:35 +0200
Subject: [PATCH 0/2] Add PCIe nodes to Airoha EN7581 SoC evaluation
 board
In-Reply-To: <20250517-en7581-evb-pcie-v1-0-97297eb063bb@kernel.org>
References: <20250517-en7581-evb-pcie-v1-0-97297eb063bb@kernel.org>
Message-ID: <174773625531.3349397.17842206398806297808.b4-ty@collabora.com>

On Sat, 17 May 2025 17:19:42 +0200, Lorenzo Bianconi wrote:
> Introduce PCIe controller nodes to EN7581 SoC and EN7581 evaluation
> board.
> 

Applied to v6.15-next/dts64, thanks!

[1/2] arm64: dts: airoha: en7581: Add gpio-ranges property for gpio controller
      commit: 3893ad42d371352ddc1aee8b28938618f5e06054
[2/2] arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board
      commit: 0e94bee0b40ea99c0c874e99373f58a1b57e7433

Cheers,
Angelo




From angelogioacchino.delregno at collabora.com  Tue May 20 03:17:33 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 12:17:33 +0200
Subject: (subset) [PATCH v2 00/14] further mt7988 devicetree work
In-Reply-To: <20250516180147.10416-1-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
Message-ID: <174773625395.3349397.13086242383163646813.b4-ty@collabora.com>

On Fri, 16 May 2025 20:01:30 +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w at public-files.de>
> 
> This series continues mt7988 devicetree work
> 
> - Add SPI with BPI-R4 nand to reach eMMC
> - Add thermal protection (fan+cooling-points)
> - Extend cpu frequency scaling with CCI
> - Basic network-support (ethernet controller + builtin switch + SFP Cages)
> 
> [...]

Applied to v6.15-next/dts64, thanks!

[04/14] arm64: dts: mediatek: mt7988: add spi controllers
        commit: 21e0977b4c074c393205b601509574820e534122
[05/14] arm64: dts: mediatek: mt7988: move uart0 and spi1 pins to soc dtsi
        commit: 35818d5038e8003745f31d8a535dea245483b61a
[06/14] arm64: dts: mediatek: mt7988: add cci node
        commit: 05c81fe3a6aab2a9df7a067b035ef7f269b66e24
[07/14] arm64: dts: mediatek: mt7988: add phy calibration efuse subnodes
        commit: 22ebf43c4eef099beffc510ec0b2a2549668d8e5
[10/14] arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and coolingmaps
        commit: 1b8747157f8eda93545163f0401d9493780026fe
[11/14] arm64: dts: mediatek: mt7988a-bpi-r4: configure spi-nodes
        commit: 91c09be53d9a66cc93e998d8c3252dc4ef469ae9
[12/14] arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply for cci
        commit: 2bb566a7f04bc775120d016a232d6b69005f3c97

Cheers,
Angelo




From angelogioacchino.delregno at collabora.com  Tue May 20 03:17:35 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 12:17:35 +0200
Subject: (subset) [PATCH v2 0/2] mt8188: Fix missing reset DT property
In-Reply-To: <20250516-dtb-check-mt8188-v2-0-fb60bef1b8e1@collabora.com>
References: <20250516-dtb-check-mt8188-v2-0-fb60bef1b8e1@collabora.com>
Message-ID: <174773625593.3349397.17577929635364837450.b4-ty@collabora.com>

On Fri, 16 May 2025 16:12:12 +0200, Julien Massot wrote:
> This patch series addresses some issues found in the MediaTek MT8188 device tree
> and its corresponding bindings:
> 
> The #reset-cells property was missing in the MT8188 clock controller binding and
> device tree nodes. This causes DT validation errors.
> 
> Patch 1 updates the binding to declare #reset-cells as a valid property.
> Patch 2 adds #reset-cells to all affected nodes in mt8188.dtsi.
> 
> [...]

Applied to v6.15-next/dts64, thanks!

[2/2] arm64: dts: mediatek: mt8188: Add missing #reset-cells property
      commit: fb77e7878bea92e7329b262e728eb6b4ac2d8768

Cheers,
Angelo




From angelogioacchino.delregno at collabora.com  Tue May 20 03:19:07 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 12:19:07 +0200
Subject: [PATCH v2 1/2] dt-bindings: clock: mediatek: Add #reset-cells
 property for MT8188
In-Reply-To: <20250516-dtb-check-mt8188-v2-1-fb60bef1b8e1@collabora.com>
References: <20250516-dtb-check-mt8188-v2-0-fb60bef1b8e1@collabora.com>
 <20250516-dtb-check-mt8188-v2-1-fb60bef1b8e1@collabora.com>
Message-ID: <b751c8d6-58ab-4a34-8d0e-a5300834962e@collabora.com>

Il 16/05/25 16:12, Julien Massot ha scritto:
> The '#reset-cells' property is permitted for some of the MT8188
> clock controllers, but not listed as a valid property.
> 
> Fixes: 9a5cd59640ac ("dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188")
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Signed-off-by: Julien Massot <julien.massot at collabora.com>

Stephen, please don't forget to pick this one, so that we resolve all those
warnings :-)

Thanks!
Angelo

> ---
>   Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
> index 2985c8c717d72888dd49f1f6249a9e2594d8a38d..5403242545ab12a7736ed4fbac26008aa955c724 100644
> --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
> @@ -52,6 +52,9 @@ properties:
>     '#clock-cells':
>       const: 1
>   
> +  '#reset-cells':
> +    const: 1
> +
>   required:
>     - compatible
>     - reg
> 




From angelogioacchino.delregno at collabora.com  Tue May 20 03:25:44 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 12:25:44 +0200
Subject: [PATCH] arm64: dts: mt8365-evk: Add goodix touchscreen support
In-Reply-To: <20250515-mt8365-evk-enable-touchscreen-v1-1-7ba3c87b2a71@collabora.com>
References: <20250515-mt8365-evk-enable-touchscreen-v1-1-7ba3c87b2a71@collabora.com>
Message-ID: <174773674488.3414755.9299343068235578994.b4-ty@collabora.com>

On Thu, 15 May 2025 12:04:11 +0200, Louis-Alexis Eyraud wrote:
> The Mediatek Genio 350-EVK board has on the DSI0 connector a StarTek
> KD070FHFID015 display panel that uses a Goodix GT9271 I2C capacitive
> touch controller.
> 
> The mt8365-evk devicetree already have the display panel support but
> lacks the touchscreen support, so add it.
> 
> [...]

Applied to v6.15-next/dts64, thanks!

[1/1] arm64: dts: mt8365-evk: Add goodix touchscreen support
      commit: a11e6951396613cddac3d7c9119de1a9ed3feaac

Cheers,
Angelo




From angelogioacchino.delregno at collabora.com  Tue May 20 03:25:45 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 12:25:45 +0200
Subject: (subset) [PATCH v2 0/3] mt8395/mt6359: Fix several dtb-check
 errors
In-Reply-To: <20250514-mt8395-dtb-errors-v2-0-d67b9077c59a@collabora.com>
References: <20250514-mt8395-dtb-errors-v2-0-d67b9077c59a@collabora.com>
Message-ID: <174773674561.3414755.11029706067816008255.b4-ty@collabora.com>

On Wed, 14 May 2025 10:19:55 +0200, Julien Massot wrote:
> This patch series addresses several dtb-check errors reported for the mt8395-genio-1200-evk.dtb and mt8395-radxa-nio-12l.dtb device trees.
> 
> The fixes include:
> - Adding the missing #sound-dai-cells property in the mt6397 binding.
> - Allowing 5 interrupts in the MediaTek IOMMU binding to support MT8395 properly.
> - Renaming the rtc node to match expected schema naming.
> 
> [...]

Applied to v6.15-next/dts64, thanks!

[3/3] arm64: dts: mt6359: Rename RTC node to match binding expectations
      commit: e19de38cca6d037bf3ab5b9908d49e230f817062

Cheers,
Angelo




From angelogioacchino.delregno at collabora.com  Tue May 20 03:40:24 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 12:40:24 +0200
Subject: [PATCH] arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes
Message-ID: <20250520104024.3706723-1-angelogioacchino.delregno@collabora.com>

Address various dt-binding warnings for most of the MDP3 nodes by
adding and removing interrupts and power domains where required.

Also, remove the mediatek,mt8195-mdp3-rdma fallback compatible
from the main MDP3 RDMA node as the two have never really been
fully compatible.

Acked-by: Rob Herring (Arm) <robh at kernel.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
---

I have sent a refactored commit to address those issues, but then I
I acknowledged that the first pull request was mistakenly merged in.

This commit is a diff between the commit that originally added the MDP3
nodes and the refactored one at [1] - so that the mt8188.dtsi file ends
up in the very same state as if the refactored one was applied in the
first place: for this reason, I kept the Ack from Rob for this commit.

[1]: https://lore.kernel.org/all/20250514092259.47035-3-angelogioacchino.delregno at collabora.com

 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 76 ++++++++++--------------
 1 file changed, 31 insertions(+), 45 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index dec6ce3e94e9..202478407727 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -2243,27 +2243,17 @@ vppsys0: syscon at 14000000 {
 		};
 
 		dma-controller at 14001000 {
-			compatible = "mediatek,mt8188-mdp3-rdma", "mediatek,mt8195-mdp3-rdma";
+			compatible = "mediatek,mt8188-mdp3-rdma";
 			reg = <0 0x14001000 0 0x1000>;
 			#dma-cells = <1>;
-			clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>,
-				 <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>,
-				 <&topckgen CLK_TOP_CFGREG_F26M_VPP0>,
-				 <&vppsys0 CLK_VPP0_WARP0_ASYNC_TX>,
-				 <&vppsys0 CLK_VPP0_WARP0_RELAY>,
-				 <&vppsys0 CLK_VPP0_WARP0_ASYNC>,
-				 <&vppsys0 CLK_VPP02VPP1_RELAY>,
-				 <&vppsys1 CLK_VPP1_VPP0_DL_ASYNC>,
-				 <&vppsys1 CLK_VPP1_VPP0_DL1_RELAY>,
-				 <&vppsys0 CLK_VPP0_VPP12VPP0_ASYNC>;
+			clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
 			mboxes = <&gce0 13 CMDQ_THR_PRIO_1>,
 				 <&gce0 14 CMDQ_THR_PRIO_1>,
 				 <&gce0 16 CMDQ_THR_PRIO_1>,
-				 <&gce0 21 CMDQ_THR_PRIO_1>;
-			iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>,
-				 <&vpp_iommu M4U_PORT_L4_MDP_WROT>;
-			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>,
-					<&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+				 <&gce0 21 CMDQ_THR_PRIO_1>,
+				 <&gce0 22 CMDQ_THR_PRIO_1>;
+			iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
 			mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
 					      <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
@@ -2274,7 +2264,6 @@ display at 14002000 {
 			compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
 			reg = <0 0x14002000 0 0x1000>;
 			clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
-			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
 		};
 
@@ -2282,13 +2271,13 @@ display at 14004000 {
 			compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
 			reg = <0 0x14004000 0 0x1000>;
 			clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
-			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
 		};
 
 		display at 14005000 {
 			compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
 			reg = <0 0x14005000 0 0x1000>;
+			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
 			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
@@ -2298,21 +2287,22 @@ display at 14006000 {
 			compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
 			reg = <0 0x14006000 0 0x1000>;
 			clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
-			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
+			mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
+					      <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
 		};
 
 		display at 14007000 {
 			compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
 			reg = <0 0x14007000 0 0x1000>;
 			clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
-			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
 		};
 
 		display at 14008000 {
 			compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
 			reg = <0 0x14008000 0 0x1000>;
+			interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
 			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
@@ -2321,9 +2311,11 @@ display at 14008000 {
 		display at 14009000 {
 			compatible = "mediatek,mt8188-mdp3-ovl", "mediatek,mt8195-mdp3-ovl";
 			reg = <0 0x14009000 0 0x1000>;
+			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
 			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
+			iommus = <&vpp_iommu M4U_PORT_L4_MDP_OVL>;
 		};
 
 		display at 1400a000 {
@@ -2338,13 +2330,13 @@ display at 1400b000 {
 			compatible = "mediatek,mt8188-mdp3-tcc", "mediatek,mt8195-mdp3-tcc";
 			reg = <0 0x1400b000 0 0x1000>;
 			clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
-			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
 		};
 
 		display at 1400c000 {
 			compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
 			reg = <0 0x1400c000 0 0x1000>;
+			#dma-cells = <1>;
 			clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
 			iommus = <&vpp_iommu M4U_PORT_L4_MDP_WROT>;
 			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
@@ -2394,14 +2386,11 @@ vpp_iommu: iommu at 14018000 {
 		};
 
 		dma-controller at 14f09000 {
-			compatible = "mediatek,mt8188-mdp3-rdma", "mediatek,mt8195-mdp3-rdma";
+			compatible = "mediatek,mt8188-mdp3-rdma";
 			reg = <0 0x14f09000 0 0x1000>;
 			#dma-cells = <1>;
-			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>,
-				 <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>,
-				 <&topckgen CLK_TOP_CFGREG_F26M_VPP1>;
-			iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>,
-				 <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
+			iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>;
 			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
 			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
@@ -2409,14 +2398,11 @@ dma-controller at 14f09000 {
 		};
 
 		dma-controller at 14f0a000 {
-			compatible = "mediatek,mt8188-mdp3-rdma", "mediatek,mt8195-mdp3-rdma";
+			compatible = "mediatek,mt8188-mdp3-rdma";
 			reg = <0 0x14f0a000 0 0x1000>;
 			#dma-cells = <1>;
-			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>,
-				 <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>,
-				 <&topckgen CLK_TOP_CFGREG_F26M_VPP1>;
-			iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>,
-				 <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
+			iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>;
 			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
 			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
@@ -2427,7 +2413,6 @@ display at 14f0c000 {
 			compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
 			reg = <0 0x14f0c000 0 0x1000>;
 			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
-			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
 		};
 
@@ -2435,7 +2420,6 @@ display at 14f0d000 {
 			compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
 			reg = <0 0x14f0d000 0 0x1000>;
 			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
-			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
 		};
 
@@ -2443,7 +2427,6 @@ display at 14f0f000 {
 			compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
 			reg = <0 0x14f0f000 0 0x1000>;
 			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
-			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
 		};
 
@@ -2451,13 +2434,13 @@ display at 14f10000 {
 			compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
 			reg = <0 0x14f10000 0 0x1000>;
 			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
-			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
 		};
 
 		display at 14f12000 {
 			compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
 			reg = <0 0x14f12000 0 0x1000>;
+			interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
 			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
@@ -2466,6 +2449,7 @@ display at 14f12000 {
 		display at 14f13000 {
 			compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
 			reg = <0 0x14f13000 0 0x1000>;
+			interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
 			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
@@ -2474,26 +2458,25 @@ display at 14f13000 {
 		display at 14f15000 {
 			compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
 			reg = <0 0x14f15000 0 0x1000>;
-			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>,
-				 <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
-			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
+			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
+					      <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
 		};
 
 		display at 14f16000 {
 			compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
 			reg = <0 0x14f16000 0 0x1000>;
-			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>,
-				 <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
-			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
+			mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
+					      <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
 		};
 
 		display at 14f18000 {
 			compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
 			reg = <0 0x14f18000 0 0x1000>;
 			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
-			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
 		};
 
@@ -2501,7 +2484,6 @@ display at 14f19000 {
 			compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
 			reg = <0 0x14f19000 0 0x1000>;
 			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
-			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
 		};
 
@@ -2524,6 +2506,7 @@ display at 14f1b000 {
 		display at 14f1d000 {
 			compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
 			reg = <0 0x14f1d000 0 0x1000>;
+			interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
 			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
@@ -2532,6 +2515,7 @@ display at 14f1d000 {
 		display at 14f1e000 {
 			compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
 			reg = <0 0x14f1e000 0 0x1000>;
+			interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
 			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
 			mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
@@ -2558,6 +2542,7 @@ display at 14f22000 {
 		display at 14f24000 {
 			compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
 			reg = <0 0x14f24000 0 0x1000>;
+			#dma-cells = <1>;
 			clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
 			iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>;
 			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
@@ -2569,6 +2554,7 @@ display at 14f24000 {
 		display at 14f25000 {
 			compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
 			reg = <0 0x14f25000 0 0x1000>;
+			#dma-cells = <1>;
 			clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
 			iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>;
 			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
-- 
2.49.0



From angelogioacchino.delregno at collabora.com  Tue May 20 04:10:02 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 13:10:02 +0200
Subject: [PATCH] Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0"
Message-ID: <20250520111002.282841-1-angelogioacchino.delregno@collabora.com>

As clearly seen on other non-MediaTek platforms, this is known to
eventually produce regressions in the future, as drivers may break
ABI and stop working with older firmware versions.

Although the firmware-name property was used in multiple MediaTek
devicetrees for the System Companion Processor (SCP) node, avoid
doing the same on MT8390 to lessen eventual ABI breakages that may
happen with a driver update to change the firmware retrieval logic
for the SCP.

This reverts commit 2f0066dae66f30386ecd6408410e27a4d6818c15.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
---

As strongly suggested by Arnd, I'm sending this revert. Driver changes
will follow as soon as possible, and most probably not in this cycle as
those should - at this point - be carefully engineered.

 arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
index aa8dd12a84ea..eaf45d42cd34 100644
--- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
@@ -1177,7 +1177,6 @@ &scp_cluster {
 };
 
 &scp_c0 {
-	firmware-name = "mediatek/mt8188/scp.img";
 	memory-region = <&scp_mem>;
 	status = "okay";
 };
-- 
2.49.0



From angelogioacchino.delregno at collabora.com  Tue May 20 04:27:23 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 13:27:23 +0200
Subject: [PATCH v2 06/14] arm64: dts: mediatek: mt7988: add cci node
In-Reply-To: <20250516180147.10416-8-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
 <20250516180147.10416-8-linux@fw-web.de>
Message-ID: <7a563716-a7c6-446d-b66d-bc71c6207ef6@collabora.com>

Il 16/05/25 20:01, Frank Wunderlich ha scritto:
> From: Frank Wunderlich <frank-w at public-files.de>
> 
> Add cci devicetree node for cpu frequency scaling.
> 
> Signed-off-by: Daniel Golle <daniel at makrotopia.org>
> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> ---
>   arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++
>   1 file changed, 33 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> index ab6fc09940b8..64466acb0e71 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> @@ -12,6 +12,35 @@ / {
>   	#address-cells = <2>;
>   	#size-cells = <2>;
>   
> +	cci: cci {
> +		compatible = "mediatek,mt8183-cci";

While you can keep the mediatek,mt8183-cci fallback, this needs its own compatible
as "mediatek,mt7988-cci", therefore, I had to drop this patch from the ones that I
picked.

Please add the new compatible both here and in the binding.

Cheers,
Angelo

> +		clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
> +			 <&topckgen CLK_TOP_XTAL>;
> +		clock-names = "cci", "intermediate";
> +		operating-points-v2 = <&cci_opp>;
> +	};
> +
> +	cci_opp: opp-table-cci {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +		opp-480000000 {
> +			opp-hz = /bits/ 64 <480000000>;
> +			opp-microvolt = <850000>;
> +		};
> +		opp-660000000 {
> +			opp-hz = /bits/ 64 <660000000>;
> +			opp-microvolt = <850000>;
> +		};
> +		opp-900000000 {
> +			opp-hz = /bits/ 64 <900000000>;
> +			opp-microvolt = <850000>;
> +		};
> +		opp-1080000000 {
> +			opp-hz = /bits/ 64 <1080000000>;
> +			opp-microvolt = <900000>;
> +		};
> +	};
> +
>   	cpus {
>   		#address-cells = <1>;
>   		#size-cells = <0>;
> @@ -25,6 +54,7 @@ cpu0: cpu at 0 {
>   				 <&topckgen CLK_TOP_XTAL>;
>   			clock-names = "cpu", "intermediate";
>   			operating-points-v2 = <&cluster0_opp>;
> +			mediatek,cci = <&cci>;
>   		};
>   
>   		cpu1: cpu at 1 {
> @@ -36,6 +66,7 @@ cpu1: cpu at 1 {
>   				 <&topckgen CLK_TOP_XTAL>;
>   			clock-names = "cpu", "intermediate";
>   			operating-points-v2 = <&cluster0_opp>;
> +			mediatek,cci = <&cci>;
>   		};
>   
>   		cpu2: cpu at 2 {
> @@ -47,6 +78,7 @@ cpu2: cpu at 2 {
>   				 <&topckgen CLK_TOP_XTAL>;
>   			clock-names = "cpu", "intermediate";
>   			operating-points-v2 = <&cluster0_opp>;
> +			mediatek,cci = <&cci>;
>   		};
>   
>   		cpu3: cpu at 3 {
> @@ -58,6 +90,7 @@ cpu3: cpu at 3 {
>   				 <&topckgen CLK_TOP_XTAL>;
>   			clock-names = "cpu", "intermediate";
>   			operating-points-v2 = <&cluster0_opp>;
> +			mediatek,cci = <&cci>;
>   		};
>   
>   		cluster0_opp: opp-table-0 {




From raphael.gallais-pou at foss.st.com  Tue May 20 04:37:12 2025
From: raphael.gallais-pou at foss.st.com (Raphael Gallais-Pou)
Date: Tue, 20 May 2025 13:37:12 +0200
Subject: [PATCH v3 15/22] drm/bridge: stm_lvds: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-15-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
 <20250509-drm-bridge-convert-to-alloc-api-v3-15-b8bc1f16d7aa@bootlin.com>
Message-ID: <b1d3f93b-8206-481b-bd8a-d7c0953e0ea5@foss.st.com>

Hi Luca,

On 5/9/25 15:53, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
>
> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
>
> ---
>
> Cc: Alexandre Torgue <alexandre.torgue at foss.st.com>
> Cc: Maxime Coquelin <mcoquelin.stm32 at gmail.com>
> Cc: Philippe Cornu <philippe.cornu at foss.st.com>
> Cc: Raphael Gallais-Pou <raphael.gallais-pou at foss.st.com>
> Cc: Yannick Fertre <yannick.fertre at foss.st.com>
> ---

I went away from keyboard for some time.? Sorry for the delay :

Acked-by: Raphael Gallais-Pou <raphael.gallais-pou at foss.st.com>


Regards,
Rapha?l



From angelogioacchino.delregno at collabora.com  Tue May 20 04:43:51 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 13:43:51 +0200
Subject: [GIT,PULL,1/2] Additional MediaTek ARM64 DTS updates for v6.16
Message-ID: <20250520114356.1194450-1-angelogioacchino.delregno@collabora.com>

The following changes since commit 1fe38d2a19950fa6dbc384ee8967c057aef9faf4:

  arm64: dts: mt6359: Add missing 'compatible' property to regulators node (2025-05-06 10:35:45 +0200)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux.git tags/mtk-dts64-for-v6.16-2

for you to fetch changes up to 99af08feb7fad3df79bda1628e4ee8b6eb1f6a32:

  Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0" (2025-05-20 13:25:02 +0200)

----------------------------------------------------------------
Additional MediaTek ARM64 DTS updates for v6.16

This addresses devicetree binding warnings happening on	the
MDP3 nodes in mt8188 dts, reverts the commit adding the SCP
firmware-name as strongly suggested by Arnd, and also adds
some more late commits.

In particular:
 - MT6359 PMIC
   - Renamed PMIC RTC node to fix dtbs_check warning
 - MT7988(A)
   - Support for SPI controllers was added to SoC and BPI-R4
   - Support for XSPHY, USB and	PCIe2 was added	as well
   - Fan and cooling maps were added to	BPI-R4 machine
   - Added BananaPi R4 2G5 machine variant
 - MT8365
   - Added touchscreen support to MT8365 Genio EVK
 - MT8188
   - Addressed dtbs_check warnings for MDP3 nodes
 - MT8390 (Genio)
   - Reverted SCP firmware-name	addition

----------------------------------------------------------------
AngeloGioacchino Del Regno (2):
      arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes
      Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0"

Frank Wunderlich (9):
      dt-bindings: arm: mediatek: add bpi-r4 2g5 phy variant
      arm64: dts: mediatek: mt7988a-bpi-r4: allow hw variants of bpi-r4
      arm64: dts: mediatek: mt7988: Add xsphy for ssusb0/pcie2
      arm64: dts: mediatek: mt7988a-bpi-r4: enable xsphy
      arm64: dts: mediatek: mt7988: add spi controllers
      arm64: dts: mediatek: mt7988: move uart0 and spi1 pins to soc dtsi
      arm64: dts: mediatek: mt7988: add phy calibration efuse subnodes
      arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and coolingmaps
      arm64: dts: mediatek: mt7988a-bpi-r4: configure spi-nodes

Julien Massot (2):
      arm64: dts: mediatek: mt8188: Add missing #reset-cells property
      arm64: dts: mt6359: Rename RTC node to match binding expectations

Lorenzo Bianconi (2):
      arm64: dts: airoha: en7581: Add gpio-ranges property for gpio controller
      arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board

Louis-Alexis Eyraud (1):
      arm64: dts: mt8365-evk: Add goodix touchscreen support

 Documentation/devicetree/bindings/arm/mediatek.yaml         |   4 +
 arch/arm64/boot/dts/airoha/en7581-evb.dts                   |  30 ++
 arch/arm64/boot/dts/airoha/en7581.dtsi                      | 105 ++++++
 arch/arm64/boot/dts/mediatek/Makefile                       |   2 +
 arch/arm64/boot/dts/mediatek/mt6359.dtsi                    |   2 +-
 .../arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts |  11 +
 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts    | 400 +----------------------
 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi   | 450 ++++++++++++++++++++++++++
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi                   | 115 +++++++
 arch/arm64/boot/dts/mediatek/mt8188.dtsi                    |  86 +++--
 arch/arm64/boot/dts/mediatek/mt8365-evk.dts                 |  40 +++
 arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi       |   1 -
 12 files changed, 804 insertions(+), 442 deletions(-)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi



From angelogioacchino.delregno at collabora.com  Tue May 20 04:43:52 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 13:43:52 +0200
Subject: [GIT,PULL,2/2] MediaTek defconfig updates for v6.16
In-Reply-To: <20250520114356.1194450-1-angelogioacchino.delregno@collabora.com>
References: <20250520114356.1194450-1-angelogioacchino.delregno@collabora.com>
Message-ID: <20250520114356.1194450-2-angelogioacchino.delregno@collabora.com>

The following changes since commit 0af2f6be1b4281385b618cb86ad946eded089ac8:

  Linux 6.15-rc1 (2025-04-06 13:11:33 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux.git tags/mtk-defconfig-for-v6.16

for you to fetch changes up to 543e0ecee19ec6fe7bca894057f7f9ae063dd5a4:

  arm64: defconfig: Enable configs for MediaTek Genio EVK boards (2025-05-14 15:47:58 +0200)

----------------------------------------------------------------
MediaTek ARM64 defconfig updates for v6.16

This enables some drivers as modules to enable fully booting
some of the supported MediaTek boards;

In particular, this enables the following drivers as module:
 - PHYs for PCIe, HDMI, DSI and DisplayPort for all boards
 - MediaTek UART DMA Controller, also for all boards
 - MDP3 driver for MT8186/88/95 (Chromebooks and Genio variants)
 - Auxiliary ADC for the MT6357/58/59 PMICs found on both Genio EVK
   and Chromebooks based on designs with MT8183/86/88/92/95 SoCs
 - iTE IT5205 Type-C USB Alternate Mode Passive MUX, found
   on both Chromebooks and Genio EVKs with MT8188/95
 - Richtek RT1715 Type-C PD Controller, found on all Genio boards
 - Himax HX8279 DSI panel DriverIC and KD070FHFID015 panel, found
   on various revisions of the Genio Evaluation Kit boards.

----------------------------------------------------------------
N?colas F. R. A. Prado (1):
      arm64: defconfig: Enable configs for MediaTek Genio EVK boards

Vignesh Raman (1):
      arm64: defconfig: mediatek: enable PHY drivers

 arch/arm64/configs/defconfig | 12 ++++++++++++
 1 file changed, 12 insertions(+)



From linux at fw-web.de  Tue May 20 04:53:43 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Tue, 20 May 2025 13:53:43 +0200
Subject: [PATCH v2 06/14] arm64: dts: mediatek: mt7988: add cci node
In-Reply-To: <7a563716-a7c6-446d-b66d-bc71c6207ef6@collabora.com>
References: <20250516180147.10416-1-linux@fw-web.de> <20250516180147.10416-8-linux@fw-web.de> <7a563716-a7c6-446d-b66d-bc71c6207ef6@collabora.com>
Message-ID: <4BEF26F3-957D-4BB4-BF7B-69DCFCC513DC@fw-web.de>

Am 20. Mai 2025 13:27:23 MESZ schrieb AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>:
>Il 16/05/25 20:01, Frank Wunderlich ha scritto:
>> From: Frank Wunderlich <frank-w at public-files.de>
>> 
>> Add cci devicetree node for cpu frequency scaling.
>> 
>> Signed-off-by: Daniel Golle <daniel at makrotopia.org>
>> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
>> ---
>>   arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++
>>   1 file changed, 33 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
>> index ab6fc09940b8..64466acb0e71 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
>> @@ -12,6 +12,35 @@ / {
>>   	#address-cells = <2>;
>>   	#size-cells = <2>;
>>   +	cci: cci {
>> +		compatible = "mediatek,mt8183-cci";
>
>While you can keep the mediatek,mt8183-cci fallback, this needs its own compatible
>as "mediatek,mt7988-cci", therefore, I had to drop this patch from the ones that I
>picked.
>
>Please add the new compatible both here and in the binding.

Ok,but you have to drop last one too (add proc-supply) else there are build-errors.

>Cheers,
>Angelo
>


regards Frank


From angelogioacchino.delregno at collabora.com  Tue May 20 04:55:12 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Tue, 20 May 2025 13:55:12 +0200
Subject: [PATCH v2 06/14] arm64: dts: mediatek: mt7988: add cci node
In-Reply-To: <4BEF26F3-957D-4BB4-BF7B-69DCFCC513DC@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
 <20250516180147.10416-8-linux@fw-web.de>
 <7a563716-a7c6-446d-b66d-bc71c6207ef6@collabora.com>
 <4BEF26F3-957D-4BB4-BF7B-69DCFCC513DC@fw-web.de>
Message-ID: <c83aa789-662a-455d-a535-237d42df3eb9@collabora.com>

Il 20/05/25 13:53, Frank Wunderlich ha scritto:
> Am 20. Mai 2025 13:27:23 MESZ schrieb AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>:
>> Il 16/05/25 20:01, Frank Wunderlich ha scritto:
>>> From: Frank Wunderlich <frank-w at public-files.de>
>>>
>>> Add cci devicetree node for cpu frequency scaling.
>>>
>>> Signed-off-by: Daniel Golle <daniel at makrotopia.org>
>>> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++
>>>    1 file changed, 33 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
>>> index ab6fc09940b8..64466acb0e71 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
>>> @@ -12,6 +12,35 @@ / {
>>>    	#address-cells = <2>;
>>>    	#size-cells = <2>;
>>>    +	cci: cci {
>>> +		compatible = "mediatek,mt8183-cci";
>>
>> While you can keep the mediatek,mt8183-cci fallback, this needs its own compatible
>> as "mediatek,mt7988-cci", therefore, I had to drop this patch from the ones that I
>> picked.
>>
>> Please add the new compatible both here and in the binding.
> 
> Ok,but you have to drop last one too (add proc-supply) else there are build-errors.
> 

Many many thanks for the reminder, but yes, I already dropped that one too ;-)

>> Cheers,
>> Angelo
>>
> 
> 
> regards Frank



From peter.wang at mediatek.com  Tue May 20 06:14:37 2025
From: peter.wang at mediatek.com (=?utf-8?B?UGV0ZXIgV2FuZyAo546L5L+h5Y+LKQ==?=)
Date: Tue, 20 May 2025 13:14:37 +0000
Subject: [PATCH v5] ufs: core: Add HID support
In-Reply-To: <20250520094054.313-1-tanghuan@vivo.com>
References: <20250520094054.313-1-tanghuan@vivo.com>
Message-ID: <ab468bb26dafca673d7ffca7dff519b7cf024cdc.camel@mediatek.com>

On Tue, 2025-05-20 at 17:40 +0800, Huan Tang wrote:
> 
> +static const char * const hid_trigger_mode[] = {"disable",
> "enable"};
> +
> +static ssize_t analysis_trigger_store(struct device *dev,
> +?????????????? struct device_attribute *attr, const char *buf,
> size_t count)
> +{
> +?????? struct ufs_hba *hba = dev_get_drvdata(dev);
> +?????? int mode;
> +?????? int ret;
> +
> +?????? mode = sysfs_match_string(hid_trigger_mode, buf);
> +?????? if (mode < 0)
> +?????????????? return -EINVAL;
> 

Hi Haun,

Consider use below coding style for readability.

if (sysfs_streq(buf, "enable"))
    mode = ...;
else if (sysfs_streq(buf, "disable"))
    mode = ...;
else
    return -EINVAL;



> 
> diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
> index 3e2097e65964..8ccd923a5761 100644
> --- a/drivers/ufs/core/ufshcd.c
> +++ b/drivers/ufs/core/ufshcd.c
> @@ -8390,6 +8390,10 @@ static int ufs_get_device_desc(struct ufs_hba
> *hba)
> 
> ??????? dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP];
> 
> +?????? dev_info->hid_sup = get_unaligned_be32(desc_buf +
> +??????????????????????????????
> DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP) &
> +?????????????????????????????? UFS_DEV_HID_SUPPORT;
> +
> 

Could add the double negation (!!) ensures the value is exactly 0 or 1.
dev_info->hid_sup = !!(get_unaligned_be32(desc_buf +
            DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP) &
            UFS_DEV_HID_SUPPORT);

The rest of the parts looks good to me.

Reviewed-by: Peter Wang <peter.wang at mediatek.com>


Thanks
Peter

From lorenzo at kernel.org  Tue May 20 06:41:35 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Tue, 20 May 2025 15:41:35 +0200
Subject: [PATCH] arm64: dts: airoha: en7581: Add ethernet nodes to EN7581
 SoC evaluation board
Message-ID: <20250520-en7581-net-v1-1-5317f8e829ad@kernel.org>

Introduce ethernet controller nodes to EN7581 SoC and EN7581 evaluation
board.

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 arch/arm64/boot/dts/airoha/en7581-evb.dts |  8 +++++
 arch/arm64/boot/dts/airoha/en7581.dtsi    | 49 +++++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+)

diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts
index 99d2c4f1fc5a9638f551c6d725eeea568943cc68..dae9968a4ff68e8b34d02b237a168a80d184bcb0 100644
--- a/arch/arm64/boot/dts/airoha/en7581-evb.dts
+++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts
@@ -98,3 +98,11 @@ &pcie1 {
 &i2c0 {
 	status = "okay";
 };
+
+&eth {
+	status = "okay";
+};
+
+&gdm1 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index 536ece69b935add88fb73ca6bd3f1ecd842cad7a..ff6908a76e8eb6cf91343495d1fe531a868e41fb 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -346,5 +346,54 @@ i2c1: i2c at 1fbf8100 {
 
 			status = "disabled";
 		};
+
+		eth: ethernet at 1fb50000 {
+			compatible = "airoha,en7581-eth";
+			reg = <0 0x1fb50000 0 0x2600>,
+			      <0 0x1fb54000 0 0x2000>,
+			      <0 0x1fb56000 0 0x2000>;
+			reg-names = "fe", "qdma0", "qdma1";
+
+			resets = <&scuclk EN7581_FE_RST>,
+				 <&scuclk EN7581_FE_PDMA_RST>,
+				 <&scuclk EN7581_FE_QDMA_RST>,
+				 <&scuclk EN7581_XSI_MAC_RST>,
+				 <&scuclk EN7581_DUAL_HSI0_MAC_RST>,
+				 <&scuclk EN7581_DUAL_HSI1_MAC_RST>,
+				 <&scuclk EN7581_HSI_MAC_RST>,
+				 <&scuclk EN7581_XFP_MAC_RST>;
+			reset-names = "fe", "pdma", "qdma",
+				      "xsi-mac", "hsi0-mac", "hsi1-mac",
+				      "hsi-mac", "xfp-mac";
+
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gdm1: ethernet at 1 {
+				compatible = "airoha,eth-mac";
+				reg = <1>;
+				phy-mode = "internal";
+				status = "disabled";
+
+				fixed-link {
+					speed = <10000>;
+					full-duplex;
+					pause;
+				};
+			};
+		};
 	};
 };

---
base-commit: 357bbde68e750ea3da2450c0c2076ff2465de559
change-id: 20250520-en7581-net-4d8f2bdcf3b5

Best regards,
-- 
Lorenzo Bianconi <lorenzo at kernel.org>



From horms at kernel.org  Tue May 20 07:33:33 2025
From: horms at kernel.org (Simon Horman)
Date: Tue, 20 May 2025 15:33:33 +0100
Subject: [PATCH net-next] net: ethernet: mtk_eth_soc: Correct spelling
Message-ID: <20250520-mtk-spell-v1-1-2b0d5b4a4528@kernel.org>

Correct spelling of platforms, various, and initial.
As flagged by codespell.

Signed-off-by: Simon Horman <horms at kernel.org>
---
 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++--
 drivers/net/ethernet/mediatek/mtk_wed.c     | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 2d4b9964d3db..6f72a8c8ae1e 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -1178,7 +1178,7 @@ struct mtk_reg_map {
 };
 
 /* struct mtk_eth_data -	This is the structure holding all differences
- *				among various plaforms
+ *				among various platforms
  * @reg_map			Soc register map.
  * @ana_rgc3:                   The offset for register ANA_RGC3 related to
  *				sgmiisys syscon
@@ -1278,7 +1278,7 @@ struct mtk_soc_data {
  * @mii_bus:		If there is a bus we need to create an instance for it
  * @pending_work:	The workqueue used to reset the dma ring
  * @state:		Initialization and runtime state of the device
- * @soc:		Holding specific data among vaious SoCs
+ * @soc:		Holding specific data among various SoCs
  */
 
 struct mtk_eth {
diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c
index e212a4ba9275..351dd152f4f3 100644
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
@@ -2000,7 +2000,7 @@ mtk_wed_configure_irq(struct mtk_wed_device *dev, u32 irq_mask)
 		if (mtk_wed_is_v3_or_greater(dev->hw))
 			wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_TKID_ALI_EN);
 
-		/* initail tx interrupt trigger */
+		/* initial tx interrupt trigger */
 		wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
 			MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
 			MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR |
@@ -2011,7 +2011,7 @@ mtk_wed_configure_irq(struct mtk_wed_device *dev, u32 irq_mask)
 			FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG,
 				   dev->wlan.tx_tbit[1]));
 
-		/* initail txfree interrupt trigger */
+		/* initial txfree interrupt trigger */
 		wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX_FREE,
 			MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN |
 			MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR |



From huobean at gmail.com  Tue May 20 09:01:50 2025
From: huobean at gmail.com (Bean Huo)
Date: Tue, 20 May 2025 18:01:50 +0200
Subject: [PATCH v5] ufs: core: Add HID support
In-Reply-To: <20250520094054.313-1-tanghuan@vivo.com>
References: <20250520094054.313-1-tanghuan@vivo.com>
Message-ID: <32c36b58dcdbb09403fa9dccff28b6bee76882e0.camel@gmail.com>

On Tue, 2025-05-20 at 17:40 +0800, Huan Tang wrote:
> @@ -87,6 +87,26 @@ static const char *ufs_wb_resize_status_to_string(enum wb_resize_status status)
> ????????}
> ?}
> ?
> +static const char *ufs_hid_state_to_string(enum ufs_hid_state state)
> +{
> +???????switch (state) {
> +???????case HID_IDLE:
> +???????????????return "idle";
> +???????case ANALYSIS_IN_PROGRESS:
> +???????????????return "analysis_in_progress";
> +???????case DEFRAG_REQUIRED:
> +???????????????return "defrag_required";
> +???????case DEFRAG_IN_PROGRESS:
> +???????????????return "defrag_in_progress";
> +???????case DEFRAG_COMPLETED:
> +???????????????return "defrag_completed";
> +???????case DEFRAG_NOT_REQUIRED:
> +???????????????return "defrag_not_required";
> +???????default:
> +???????????????return "unknown";
> +???????}
> +}

The enum ufs_hid_state values are contiguous and start from 0, maybe change switch-state to :

#define NUM_UFS_HID_STATES 6
static const char *ufs_hid_states[NUM_UFS_HID_STATES] = {
    "idle",
    "analysis_in_progress",
    "defrag_required",
    "defrag_in_progress",
    "defrag_completed",
    "defrag_not_required"
};

static const char *ufs_hid_state_to_string(enum ufs_hid_state state) {
    if ((unsigned int)state < NUM_UFS_HID_STATES)
        return ufs_hid_states[state];
    return "unknown";
}


From cjd at cjdns.fr  Tue May 20 09:07:28 2025
From: cjd at cjdns.fr (Caleb James DeLisle)
Date: Tue, 20 May 2025 18:07:28 +0200
Subject: [PATCH v5 0/7] Add EcoNet EN751221 MIPS platform support
In-Reply-To: <aCwl-nAMxjqjxRM6@alpha.franken.de>
References: <20250507134500.390547-1-cjd@cjdns.fr>
 <aCwl-nAMxjqjxRM6@alpha.franken.de>
Message-ID: <3e6bb5e4-5f1c-4ff8-9b73-358a89d50b25@cjdns.fr>


On 20/05/2025 08:49, Thomas Bogendoerfer wrote:
> On Wed, May 07, 2025 at 01:44:53PM +0000, Caleb James DeLisle wrote:
>> EcoNet MIPS SoCs are big endian machines based on 34Kc and 1004Kc
>> processors. They are found in xDSL and xPON modems, and contain PCM
>> (VoIP), Ethernet, USB, GPIO, I2C, SPI (Flash), UART, and PCIe.
>>
>> The EcoNet MIPS SoCs are divided broadly into two families, the
>> EN751221 family based on the 34Kc, and the EN751627 family based on
>> the 1004Kc. Individual SoCs within a family are very similar, only
>> with different peripherals.
>>
>> This patchset adds basic "boots to a console" support for the EN751221
>> family and adds SmartFiber XP8421-B, a low cost commercially available
>> board that is useful for testing and development.
>>
>> Note that Airoha (AN7523, AN7581) is similar to EcoNet in terms of
>> peripherals, and for historical reasons Airoha chips are sometimes
>> referred to with the EN75xx prefix. However this is a different
>> platform because Airoha chips are ARM based.
>>
>> This patchset is against mips-next.
>>
>> v4 -> v5
>> * 2/7 clocksource/drivers: Add EcoNet Timer HPT driver:
>>    * Improve explanation of HPT timer in changelog
>>    * Move pr_info to pr_debug per recommendation
>>    * Remove pointless debug on spurious interrupt
>>    * Small code-style change
>>
>> v3 -> v4
>> * Rebase to 3b3704261e851e25983860e4c352f1f73786f4ab
>> * Omit already accepted patches (thanks guys!):
>>    - https://patchwork.kernel.org/project/linux-mips/patch/20250330170306.2584136-2-cjd at cjdns.fr/
>>    - https://patchwork.kernel.org/project/linux-mips/patch/20250330170306.2584136-3-cjd at cjdns.fr/
>>    - https://patchwork.kernel.org/project/linux-mips/patch/20250330170306.2584136-4-cjd at cjdns.fr/
>>
>> v2 -> v3
>> * econet,en751221-timer.yaml -> Improve code style
>> * vendor-prefixes.yaml -> Correct alphabetic order
>> * en751221.dtsi
>>    - interrupt-controller code style
>>    - serial: Explain reason for clock-frequency = <1843200>
>> * v3->v3 diff provided for reference
>>    - https://gist.github.com/cjdelisle/21c9f0cd225f499bdff3c574c7f185f2
>> * CC: linux-mediatek at lists.infradead.org who may be interested.
>>
>> v1 -> v2
>> * Codestyle
>>    - Apply codestyle from "The tip tree handbook" and recommendations
>>    - Remove "_rai" and "_m" symbol suffixes which are not standard
>> * irq-econet-en751221.c
>>    - Use cleanup.h _guard() and _free()
>>    - Separate irq_domain_ops from irq_chip, eliminating econet_intc struct
>>    - Remove irqsave in econet_wreg, irqs are already disabled in mask/unmask
>>    - Add explainatory comments
>>    - Refactor shadow logic for clarity, e.g. INTC_NO_SHADOW -> NOT_PERCPU
>>    - Improve error handling in case of invalid DTS
>> * econet,timer-hpt.yaml
>>    - Rename to econet,timer-en751221.yaml
>>    - Impose rule: "reg" must have 1 item on EN751221 and 2 on EN751627
>> * timer-econet-hpt.c
>>    - Rename to timer-econet-en751221.c to follow naming scheme from DT
>> * econet,en751221-intc.yaml
>>    - Fix validation error from required: interrupt-parent
>>    - shadow-interrupts -> switch to uint32-matrix for list of pairs
>> * MAINTAINERS -> Fixed accidental F: MAINTAINERS
>> * Replace "test image" with device SmartFiber-XP8421-B
>> * Restructure arch/mips/econet/Kconfig per arch/mips/ralink example
>> * v1->v2 diff is offered for reference:
>>    - https://gist.github.com/cjdelisle/bb3acab78b5f70dcdfe5dd6338293efe
>>
>>
>> Caleb James DeLisle (7):
>>    dt-bindings: timer: Add EcoNet EN751221 "HPT" CPU Timer
>>    clocksource/drivers: Add EcoNet Timer HPT driver
>>    dt-bindings: mips: Add EcoNet platform binding
>>    mips: Add EcoNet MIPS platform support
>>    dt-bindings: vendor-prefixes: Add SmartFiber
>>    mips: dts: Add EcoNet DTS with EN751221 and SmartFiber XP8421-B board
>>    MAINTAINERS: Add entry for newly added EcoNet platform.
>>
>>   .../devicetree/bindings/mips/econet.yaml      |  26 +++
>>   .../bindings/timer/econet,en751221-timer.yaml |  80 +++++++
>>   .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
>>   MAINTAINERS                                   |  12 +
>>   arch/mips/Kbuild.platforms                    |   1 +
>>   arch/mips/Kconfig                             |  25 ++
>>   arch/mips/boot/compressed/uart-16550.c        |   5 +
>>   arch/mips/boot/dts/Makefile                   |   1 +
>>   arch/mips/boot/dts/econet/Makefile            |   2 +
>>   arch/mips/boot/dts/econet/en751221.dtsi       |  67 ++++++
>>   .../econet/en751221_smartfiber_xp8421-b.dts   |  19 ++
>>   arch/mips/econet/Kconfig                      |  48 ++++
>>   arch/mips/econet/Makefile                     |   2 +
>>   arch/mips/econet/Platform                     |   5 +
>>   arch/mips/econet/init.c                       |  78 +++++++
>>   drivers/clocksource/Kconfig                   |   8 +
>>   drivers/clocksource/Makefile                  |   1 +
>>   drivers/clocksource/timer-econet-en751221.c   | 216 ++++++++++++++++++
>>   18 files changed, 598 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/mips/econet.yaml
>>   create mode 100644 Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
>>   create mode 100644 arch/mips/boot/dts/econet/Makefile
>>   create mode 100644 arch/mips/boot/dts/econet/en751221.dtsi
>>   create mode 100644 arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts
>>   create mode 100644 arch/mips/econet/Kconfig
>>   create mode 100644 arch/mips/econet/Makefile
>>   create mode 100644 arch/mips/econet/Platform
>>   create mode 100644 arch/mips/econet/init.c
>>   create mode 100644 drivers/clocksource/timer-econet-en751221.c
> applied patches 3-7 to mips-next

Thank you very much, and also thanks to everyone who helped review and 
apply the others.


Thanks,

Caleb


>
> Thomas.
>


From linux at fw-web.de  Tue May 20 10:08:08 2025
From: linux at fw-web.de (Frank Wunderlich (linux))
Date: Tue, 20 May 2025 19:08:08 +0200
Subject: [PATCH v2 06/14] arm64: dts: mediatek: mt7988: add cci node
In-Reply-To: <7a563716-a7c6-446d-b66d-bc71c6207ef6@collabora.com>
References: <20250516180147.10416-1-linux@fw-web.de>
 <20250516180147.10416-8-linux@fw-web.de>
 <7a563716-a7c6-446d-b66d-bc71c6207ef6@collabora.com>
Message-ID: <6c0dd946bdebd8461307a3e08e60a27f@fw-web.de>

Am 2025-05-20 13:27, schrieb AngeloGioacchino Del Regno:
> Il 16/05/25 20:01, Frank Wunderlich ha scritto:
>> From: Frank Wunderlich <frank-w at public-files.de>
>> 
>> Add cci devicetree node for cpu frequency scaling.
>> --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
>> @@ -12,6 +12,35 @@ / {
>>   	#address-cells = <2>;
>>   	#size-cells = <2>;
>>   +	cci: cci {
>> +		compatible = "mediatek,mt8183-cci";
> 
> While you can keep the mediatek,mt8183-cci fallback, this needs its own 
> compatible
> as "mediatek,mt7988-cci", therefore, I had to drop this patch from the 
> ones that I
> picked.
> 
> Please add the new compatible both here and in the binding.

Hi,

should i add the binding with 2 const (like the bpi-r4-2g5 compatible) 
or first as enum
to allow easier addition of further SoC bindings with same fallback?

currently i changed binding like this (2nd variant):

properties:
   compatible:
     oneOf:
       - items:
           - enum:
               - mediatek,mt8183-cci
               - mediatek,mt8186-cci
       - items:
           - enum:
               - mediatek,mt7988-cci
           - const: mediatek,mt8183-cci

but noticed that these boards are missing the required proc-supply:

   DTC [C] arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dtb
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dtb: cci: 'proc-supply' is a 
required property
	from schema $id: 
http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
   DTC [C] arch/arm64/boot/dts/mediatek/mt8186-evb.dtb
arch/arm64/boot/dts/mediatek/mt8186-evb.dtb: cci: 'proc-supply' is a 
required property
	from schema $id: 
http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#

the others are clean so far. But because i do not have these boards i 
cannot fix this without
anyone telling me the proc-supply for them.

In mt7988a.dtsi i can put both compatible on 1 line as there are only 75 
chars, or should i
add linebreak here for better readability?

> Cheers,
> Angelo

regards Frank


From kuba at kernel.org  Tue May 20 12:21:41 2025
From: kuba at kernel.org (Jakub Kicinski)
Date: Tue, 20 May 2025 12:21:41 -0700
Subject: [net-next v1] net: wwan: t7xx: Parameterize data plane RX BAT
 and FAG count
In-Reply-To: <20250516084320.66998caf@kernel.org>
References: <20250514104728.10869-1-jinjian.song@fibocom.com>
	<20250515180858.2568d930@kernel.org>
	<20250516084320.66998caf@kernel.org>
Message-ID: <20250520122141.025616c9@kernel.org>

On Tue, 20 May 2025 10:59:34 +0800 Jinjian Song wrote:
>   If it's not feasible to directly add parameters for configuring this RX buffer(BAT/FAG) to 
> the mtk_t7xx driver, would it be allowed to add aparameter for a default configuration 
> ratio (1/2, 1/4)? Or is it not recommended to use driver parameters for mtk_t7xx driver.

Looks into devlink params then


From bvanassche at acm.org  Tue May 20 13:13:57 2025
From: bvanassche at acm.org (Bart Van Assche)
Date: Tue, 20 May 2025 13:13:57 -0700
Subject: [PATCH v5] ufs: core: Add HID support
In-Reply-To: <ab468bb26dafca673d7ffca7dff519b7cf024cdc.camel@mediatek.com>
References: <20250520094054.313-1-tanghuan@vivo.com>
 <ab468bb26dafca673d7ffca7dff519b7cf024cdc.camel@mediatek.com>
Message-ID: <3ba29109-86d8-4bc1-8f2f-49fa2e56673e@acm.org>

On 5/20/25 6:14 AM, Peter Wang (???) wrote:
> On Tue, 2025-05-20 at 17:40 +0800, Huan Tang wrote:
>> diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
>> index 3e2097e65964..8ccd923a5761 100644
>> --- a/drivers/ufs/core/ufshcd.c
>> +++ b/drivers/ufs/core/ufshcd.c
>> @@ -8390,6 +8390,10 @@ static int ufs_get_device_desc(struct ufs_hba
>> *hba)
>> 
>> ??????? dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP];
>> 
>> +?????? dev_info->hid_sup = get_unaligned_be32(desc_buf +
>> +                              
>> DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP) &
>> +?????????????????????????????? UFS_DEV_HID_SUPPORT;
>> +
>> 
> 
> Could add the double negation (!!) ensures the value is exactly 0 or 1.
> dev_info->hid_sup = !!(get_unaligned_be32(desc_buf +
>              DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP) &
>              UFS_DEV_HID_SUPPORT);

Hi Peter,

I do not agree that this change is required. ufs_dev_info.hid_sup has 
type bool and hence the compiler will convert the result of the binary
and operation implicitly into a boolean value (0/1). From the C23
standard: "When any scalar value is converted to bool, the result is
false if the value is a zero (for arithmetic types), null (for pointer
types), or the scalar has type nullptr_t; otherwise, the result is
true."

A double negation does not occur elsewhere in the kernel if an integer
value is assigned to a boolean variable so I think that it shouldn't be
added here either.

Bart.


From bvanassche at acm.org  Tue May 20 13:22:05 2025
From: bvanassche at acm.org (Bart Van Assche)
Date: Tue, 20 May 2025 13:22:05 -0700
Subject: [PATCH v5] ufs: core: Add HID support
In-Reply-To: <32c36b58dcdbb09403fa9dccff28b6bee76882e0.camel@gmail.com>
References: <20250520094054.313-1-tanghuan@vivo.com>
 <32c36b58dcdbb09403fa9dccff28b6bee76882e0.camel@gmail.com>
Message-ID: <b0ec5b8a-b303-4e5b-bca9-4524eba9fa31@acm.org>

On 5/20/25 9:01 AM, Bean Huo wrote:
> On Tue, 2025-05-20 at 17:40 +0800, Huan Tang wrote:
>> @@ -87,6 +87,26 @@ static const char *ufs_wb_resize_status_to_string(enum wb_resize_status status)
>>  ????????}
>>  ?}
>>   
>> +static const char *ufs_hid_state_to_string(enum ufs_hid_state state)
>> +{
>> +???????switch (state) {
>> +???????case HID_IDLE:
>> +???????????????return "idle";
>> +???????case ANALYSIS_IN_PROGRESS:
>> +???????????????return "analysis_in_progress";
>> +???????case DEFRAG_REQUIRED:
>> +???????????????return "defrag_required";
>> +???????case DEFRAG_IN_PROGRESS:
>> +???????????????return "defrag_in_progress";
>> +???????case DEFRAG_COMPLETED:
>> +???????????????return "defrag_completed";
>> +???????case DEFRAG_NOT_REQUIRED:
>> +???????????????return "defrag_not_required";
>> +???????default:
>> +???????????????return "unknown";
>> +???????}
>> +}
> 
> The enum ufs_hid_state values are contiguous and start from 0, maybe change switch-state to :
> 
> #define NUM_UFS_HID_STATES 6
> static const char *ufs_hid_states[NUM_UFS_HID_STATES] = {
>      "idle",
>      "analysis_in_progress",
>      "defrag_required",
>      "defrag_in_progress",
>      "defrag_completed",
>      "defrag_not_required"
> };

If this change is made, please use the designated initializer syntax
([label] = "text"). This will make it easier to verify that the
enumeration labels and the strings match.

Thanks,

Bart.


From nfraprado at collabora.com  Tue May 20 14:15:58 2025
From: nfraprado at collabora.com (=?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?=)
Date: Tue, 20 May 2025 17:15:58 -0400
Subject: [PATCH v2] pinctrl: mediatek: eint: Fix invalid pointer
 dereference for v1 platforms
Message-ID: <20250520-genio-350-eint-null-ptr-deref-fix-v2-1-6a3ca966a7ba@collabora.com>

Commit 3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple
addresses") introduced an access to the 'soc' field of struct
mtk_pinctrl in mtk_eint_do_init() and for that an include of
pinctrl-mtk-common-v2.h.

However, pinctrl drivers relying on the v1 common driver include
pinctrl-mtk-common.h instead, which provides another definition of
struct mtk_pinctrl that does not contain an 'soc' field.

Since mtk_eint_do_init() can be called both by v1 and v2 drivers, it
will now try to dereference an invalid pointer when called on v1
platforms. This has been observed on Genio 350 EVK (MT8365), which
crashes very early in boot (the kernel trace can only be seen with
earlycon).

In order to fix this, since 'struct mtk_pinctrl' was only needed to get
a 'struct mtk_eint_pin', make 'struct mtk_eint_pin' a parameter
of mtk_eint_do_init() so that callers need to supply it, removing
mtk_eint_do_init()'s dependency on any particular 'struct mtk_pinctrl'.

Fixes: 3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple addresses")
Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
---
Changes in v2:
- Completely changed approach to make mtk_eint_pin a parameter of
  mtk_eint_do_init() as suggested by Angelo
- Link to v1: https://lore.kernel.org/r/20250519-genio-350-eint-null-ptr-deref-fix-v1-1-07445d6d22c3 at collabora.com
---
 drivers/pinctrl/mediatek/mtk-eint.c              | 26 ++++++++++--------------
 drivers/pinctrl/mediatek/mtk-eint.h              |  5 +++--
 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c |  2 +-
 drivers/pinctrl/mediatek/pinctrl-mtk-common.c    |  2 +-
 4 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c
index 16af6a47028e67bb53db4041a37ebbbb8b9a1e43..d906a5e4101fb10968035fc48e9cf4a444d063a9 100644
--- a/drivers/pinctrl/mediatek/mtk-eint.c
+++ b/drivers/pinctrl/mediatek/mtk-eint.c
@@ -22,7 +22,6 @@
 #include <linux/platform_device.h>
 
 #include "mtk-eint.h"
-#include "pinctrl-mtk-common-v2.h"
 
 #define MTK_EINT_EDGE_SENSITIVE           0
 #define MTK_EINT_LEVEL_SENSITIVE          1
@@ -505,10 +504,9 @@ int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
 }
 EXPORT_SYMBOL_GPL(mtk_eint_find_irq);
 
-int mtk_eint_do_init(struct mtk_eint *eint)
+int mtk_eint_do_init(struct mtk_eint *eint, struct mtk_eint_pin *eint_pin)
 {
 	unsigned int size, i, port, virq, inst = 0;
-	struct mtk_pinctrl *hw = (struct mtk_pinctrl *)eint->pctl;
 
 	/* If clients don't assign a specific regs, let's use generic one */
 	if (!eint->regs)
@@ -519,7 +517,15 @@ int mtk_eint_do_init(struct mtk_eint *eint)
 	if (!eint->base_pin_num)
 		return -ENOMEM;
 
-	if (eint->nbase == 1) {
+	if (eint_pin) {
+		eint->pins = eint_pin;
+		for (i = 0; i < eint->hw->ap_num; i++) {
+			inst = eint->pins[i].instance;
+			if (inst >= eint->nbase)
+				continue;
+			eint->base_pin_num[inst]++;
+		}
+	} else {
 		size = eint->hw->ap_num * sizeof(struct mtk_eint_pin);
 		eint->pins = devm_kmalloc(eint->dev, size, GFP_KERNEL);
 		if (!eint->pins)
@@ -533,16 +539,6 @@ int mtk_eint_do_init(struct mtk_eint *eint)
 		}
 	}
 
-	if (hw && hw->soc && hw->soc->eint_pin) {
-		eint->pins = hw->soc->eint_pin;
-		for (i = 0; i < eint->hw->ap_num; i++) {
-			inst = eint->pins[i].instance;
-			if (inst >= eint->nbase)
-				continue;
-			eint->base_pin_num[inst]++;
-		}
-	}
-
 	eint->pin_list = devm_kmalloc(eint->dev, eint->nbase * sizeof(u16 *), GFP_KERNEL);
 	if (!eint->pin_list)
 		goto err_pin_list;
@@ -609,7 +605,7 @@ int mtk_eint_do_init(struct mtk_eint *eint)
 err_wake_mask:
 	devm_kfree(eint->dev, eint->pin_list);
 err_pin_list:
-	if (eint->nbase == 1)
+	if (!eint_pin)
 		devm_kfree(eint->dev, eint->pins);
 err_pins:
 	devm_kfree(eint->dev, eint->base_pin_num);
diff --git a/drivers/pinctrl/mediatek/mtk-eint.h b/drivers/pinctrl/mediatek/mtk-eint.h
index 0c6bf7cbdc3a4f16e35d576535c6cef102962356..fc31a4c0c77bf28b106943e9292d0dcc425c4922 100644
--- a/drivers/pinctrl/mediatek/mtk-eint.h
+++ b/drivers/pinctrl/mediatek/mtk-eint.h
@@ -88,7 +88,7 @@ struct mtk_eint {
 };
 
 #if IS_ENABLED(CONFIG_EINT_MTK)
-int mtk_eint_do_init(struct mtk_eint *eint);
+int mtk_eint_do_init(struct mtk_eint *eint, struct mtk_eint_pin *eint_pin);
 int mtk_eint_do_suspend(struct mtk_eint *eint);
 int mtk_eint_do_resume(struct mtk_eint *eint);
 int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n,
@@ -96,7 +96,8 @@ int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n,
 int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n);
 
 #else
-static inline int mtk_eint_do_init(struct mtk_eint *eint)
+static inline int mtk_eint_do_init(struct mtk_eint *eint,
+				   struct mtk_eint_pin *eint_pin)
 {
 	return -EOPNOTSUPP;
 }
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
index 0884c0700b3ee463c4571f2ac5b0254b5583b54a..4918d38abfc29de1f27ee75bc6a51c32b3ca1ac5 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -419,7 +419,7 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
 	hw->eint->pctl = hw;
 	hw->eint->gpio_xlate = &mtk_eint_xt;
 
-	ret = mtk_eint_do_init(hw->eint);
+	ret = mtk_eint_do_init(hw->eint, hw->soc->eint_pin);
 	if (ret)
 		goto err_free_eint;
 
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index de7bebb9a6cd98cbe7d77982698073f9c8974e3b..a4cb6d511fcdb36f67f30548636a0d64c5278840 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -1044,7 +1044,7 @@ static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev)
 	pctl->eint->pctl = pctl;
 	pctl->eint->gpio_xlate = &mtk_eint_xt;
 
-	return mtk_eint_do_init(pctl->eint);
+	return mtk_eint_do_init(pctl->eint, NULL);
 }
 
 /* This is used as a common probe function */

---
base-commit: 8566fc3b96539e3235909d6bdda198e1282beaed
change-id: 20250519-genio-350-eint-null-ptr-deref-fix-1a163aa9ad84

Best regards,
-- 
N?colas F. R. A. Prado <nfraprado at collabora.com>



From kuba at kernel.org  Tue May 20 15:39:42 2025
From: kuba at kernel.org (Jakub Kicinski)
Date: Tue, 20 May 2025 15:39:42 -0700
Subject: [net v1] net: wwan: t7xx: Fix napi rx poll issue
In-Reply-To: <20250516084842.26c80cb5@kernel.org>
References: <20250515031743.246178-1-jinjian.song@fibocom.com>
	<20250515175251.58b5123f@kernel.org>
	<20250516084842.26c80cb5@kernel.org>
Message-ID: <20250520153942.7cb63bac@kernel.org>

On Tue, 20 May 2025 15:05:34 +0800 Jinjian Song wrote:
> >Synchronization is about ensuring that the condition validating
> >by the if() remains true for as long as necessary.
> >You need to wrap the read with READ_ONCE() and write with WRITE_ONCE().
> >The rest if fine because netdev unregister sync against NAPIs in flight.
> >  
> 
> Hi Jakub,
>   I think I got your point.
>   I can use the atomic_t usage in struct t7xx_ccmni to synchronization.
>   
>   static void t7xx_ccmni_wwan_dellink(...) {
> 
>   [...]
> 
>   if (WARN_ON(ctlb->ccmni_inst[if_id] != ccmni))
>     return;
> 
>   unregister_netdevice(dev);
> 
>   //Add here use this variable(ccmnii->usage) to synchronization
> 
>   if (atomic_read(&ccmni->usage) == 0)
>      ccmni == NULL;
> 
>   }
> 
>   How about this modify?

Just use READ_ONCE() / WRITE_ONCE() on the pointer as I suggested.


From linus.walleij at linaro.org  Tue May 20 15:42:01 2025
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 21 May 2025 00:42:01 +0200
Subject: [PATCH v2] pinctrl: mediatek: eint: Fix invalid pointer
 dereference for v1 platforms
In-Reply-To: <20250520-genio-350-eint-null-ptr-deref-fix-v2-1-6a3ca966a7ba@collabora.com>
References: <20250520-genio-350-eint-null-ptr-deref-fix-v2-1-6a3ca966a7ba@collabora.com>
Message-ID: <CACRpkdYor2+rCZGsZLw=_Wna=0KnyXBaVtx-VahmN6Ky-zZ-Dg@mail.gmail.com>

On Tue, May 20, 2025 at 11:16?PM N?colas F. R. A. Prado
<nfraprado at collabora.com> wrote:

> Commit 3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple
> addresses") introduced an access to the 'soc' field of struct
> mtk_pinctrl in mtk_eint_do_init() and for that an include of
> pinctrl-mtk-common-v2.h.
>
> However, pinctrl drivers relying on the v1 common driver include
> pinctrl-mtk-common.h instead, which provides another definition of
> struct mtk_pinctrl that does not contain an 'soc' field.
>
> Since mtk_eint_do_init() can be called both by v1 and v2 drivers, it
> will now try to dereference an invalid pointer when called on v1
> platforms. This has been observed on Genio 350 EVK (MT8365), which
> crashes very early in boot (the kernel trace can only be seen with
> earlycon).
>
> In order to fix this, since 'struct mtk_pinctrl' was only needed to get
> a 'struct mtk_eint_pin', make 'struct mtk_eint_pin' a parameter
> of mtk_eint_do_init() so that callers need to supply it, removing
> mtk_eint_do_init()'s dependency on any particular 'struct mtk_pinctrl'.
>
> Fixes: 3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple addresses")
> Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>

Patch applied for v6.16.

If it is needed for v6.15- then I think at this point it will need to
be backported to stable. It also does not apply cleanly on Torvald's
tree, just on my devel branch.

Yours,
Linus Walleij


From shannon.nelson at amd.com  Tue May 20 16:32:47 2025
From: shannon.nelson at amd.com (Nelson, Shannon)
Date: Tue, 20 May 2025 16:32:47 -0700
Subject: [PATCH net-next] net: ethernet: mtk_eth_soc: Correct spelling
In-Reply-To: <20250520-mtk-spell-v1-1-2b0d5b4a4528@kernel.org>
References: <20250520-mtk-spell-v1-1-2b0d5b4a4528@kernel.org>
Message-ID: <d2eef52b-8500-4858-96b4-1b95d533ec8c@amd.com>

On 5/20/2025 7:33 AM, Simon Horman wrote:
> 
> Correct spelling of platforms, various, and initial.
> As flagged by codespell.
> 
> Signed-off-by: Simon Horman <horms at kernel.org>

Thanks,

Reviewed-by: Shannon Nelson <shannon.nelson at amd.com>


> ---
>   drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++--
>   drivers/net/ethernet/mediatek/mtk_wed.c     | 4 ++--
>   2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> index 2d4b9964d3db..6f72a8c8ae1e 100644
> --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> @@ -1178,7 +1178,7 @@ struct mtk_reg_map {
>   };
> 
>   /* struct mtk_eth_data -       This is the structure holding all differences
> - *                             among various plaforms
> + *                             among various platforms
>    * @reg_map                    Soc register map.
>    * @ana_rgc3:                   The offset for register ANA_RGC3 related to
>    *                             sgmiisys syscon
> @@ -1278,7 +1278,7 @@ struct mtk_soc_data {
>    * @mii_bus:           If there is a bus we need to create an instance for it
>    * @pending_work:      The workqueue used to reset the dma ring
>    * @state:             Initialization and runtime state of the device
> - * @soc:               Holding specific data among vaious SoCs
> + * @soc:               Holding specific data among various SoCs
>    */
> 
>   struct mtk_eth {
> diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c
> index e212a4ba9275..351dd152f4f3 100644
> --- a/drivers/net/ethernet/mediatek/mtk_wed.c
> +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
> @@ -2000,7 +2000,7 @@ mtk_wed_configure_irq(struct mtk_wed_device *dev, u32 irq_mask)
>                  if (mtk_wed_is_v3_or_greater(dev->hw))
>                          wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_TKID_ALI_EN);
> 
> -               /* initail tx interrupt trigger */
> +               /* initial tx interrupt trigger */
>                  wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
>                          MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
>                          MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR |
> @@ -2011,7 +2011,7 @@ mtk_wed_configure_irq(struct mtk_wed_device *dev, u32 irq_mask)
>                          FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG,
>                                     dev->wlan.tx_tbit[1]));
> 
> -               /* initail txfree interrupt trigger */
> +               /* initial txfree interrupt trigger */
>                  wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX_FREE,
>                          MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN |
>                          MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR |
> 
> 



From robh at kernel.org  Tue May 20 17:02:11 2025
From: robh at kernel.org (Rob Herring)
Date: Tue, 20 May 2025 19:02:11 -0500
Subject: [PATCH v1 2/2] iommu/mediatek: Add support for Dimensity 1200
 MT6893 MM IOMMU
In-Reply-To: <20250410144008.475888-3-angelogioacchino.delregno@collabora.com>
References: <20250410144008.475888-1-angelogioacchino.delregno@collabora.com>
 <20250410144008.475888-3-angelogioacchino.delregno@collabora.com>
Message-ID: <20250521000211.GA1717916-robh@kernel.org>

On Thu, Apr 10, 2025 at 04:40:08PM +0200, AngeloGioacchino Del Regno wrote:
> Add support for the two MM IOMMUs found in the MediaTek Dimensity
> 1200 (MT6893) SoC, used for display, camera, imgsys and vpu.
> 
> Since the MT6893 SoC is almost fully compatible with MT8192, also
> move the mt8192_larb_region_msk before the newly introduced mt6893
> platform data, as the larb regions from mt8192 are fully reused.
> 
> Note that the only difference with MT8192 is that MT6893 needs the
> SHARE_PGTABLE flag.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> ---
>  drivers/iommu/mtk_iommu.c | 37 ++++++++++++++++++++++++++-----------
>  1 file changed, 26 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index df98d0c65f54..0a54c6521bf5 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -1550,6 +1550,31 @@ static const struct mtk_iommu_plat_data mt6795_data = {
>  	.larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */
>  };
>  
> +static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
> +	[0] = {~0, ~0},				/* Region0: larb0/1 */
> +	[1] = {0, 0, 0, 0, ~0, ~0, 0, ~0},	/* Region1: larb4/5/7 */
> +	[2] = {0, 0, ~0, 0, 0, 0, 0, 0,		/* Region2: larb2/9/11/13/14/16/17/18/19/20 */
> +	       0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), ~(u32)(BIT(4) | BIT(5)), 0,
> +	       ~0, ~0, ~0, ~0, ~0},
> +	[3] = {0},
> +	[4] = {[13] = BIT(9) | BIT(10)},	/* larb13 port9/10 */
> +	[5] = {[14] = BIT(4) | BIT(5)},		/* larb14 port4/5 */
> +};
> +
> +static const struct mtk_iommu_plat_data mt6893_data = {
> +	.m4u_plat     = M4U_MT8192,
> +	.flags        = HAS_BCLK | OUT_ORDER_WR_EN | HAS_SUB_COMM_2BITS |
> +			WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
> +	.inv_sel_reg  = REG_MMU_INV_SEL_GEN2,
> +	.banks_num    = 1,
> +	.banks_enable = {true},
> +	.iova_region  = mt8192_multi_dom,
> +	.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
> +	.iova_region_larb_msk = mt8192_larb_region_msk,
> +	.larbid_remap    = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
> +			    {0, 14, 16}, {0, 13, 18, 17}},
> +};
> +
>  static const struct mtk_iommu_plat_data mt8167_data = {
>  	.m4u_plat     = M4U_MT8167,
>  	.flags        = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM,
> @@ -1673,17 +1698,6 @@ static const struct mtk_iommu_plat_data mt8188_data_vpp = {
>  			   27, 28 /* ccu0 */, MTK_INVALID_LARBID}, {4, 6}},
>  };
>  
> -static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
> -	[0] = {~0, ~0},				/* Region0: larb0/1 */
> -	[1] = {0, 0, 0, 0, ~0, ~0, 0, ~0},	/* Region1: larb4/5/7 */
> -	[2] = {0, 0, ~0, 0, 0, 0, 0, 0,		/* Region2: larb2/9/11/13/14/16/17/18/19/20 */
> -	       0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), ~(u32)(BIT(4) | BIT(5)), 0,
> -	       ~0, ~0, ~0, ~0, ~0},
> -	[3] = {0},
> -	[4] = {[13] = BIT(9) | BIT(10)},	/* larb13 port9/10 */
> -	[5] = {[14] = BIT(4) | BIT(5)},		/* larb14 port4/5 */
> -};
> -
>  static const struct mtk_iommu_plat_data mt8192_data = {
>  	.m4u_plat       = M4U_MT8192,
>  	.flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
> @@ -1777,6 +1791,7 @@ static const struct of_device_id mtk_iommu_of_ids[] = {
>  	{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
>  	{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
>  	{ .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data},
> +	{ .compatible = "mediatek.mt6893-iommu-mm", .data = &mt6893_data},

Are you going to fix the typo>   ^

It is still warning with 'make dt_compatible_check' that it is 
undocumented.

Rob


From patchwork-bot+netdevbpf at kernel.org  Tue May 20 18:20:58 2025
From: patchwork-bot+netdevbpf at kernel.org (patchwork-bot+netdevbpf at kernel.org)
Date: Wed, 21 May 2025 01:20:58 +0000
Subject: [PATCH net-next v4 0/2] Add built-in 2.5G ethernet phy support on
 MT7988
In-Reply-To: <20250516102327.2014531-1-SkyLake.Huang@mediatek.com>
References: <20250516102327.2014531-1-SkyLake.Huang@mediatek.com>
Message-ID: <174779045848.1526198.6198912452247192673.git-patchwork-notify@kernel.org>

Hello:

This series was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba at kernel.org>:

On Fri, 16 May 2025 18:23:25 +0800 you wrote:
> From: Sky Huang <skylake.huang at mediatek.com>
> 
> This patchset adds support for built-in 2.5Gphy on MT7988, sort file
> and config sequence in related Kconfig and Makefile.
> 
> ---
> Change in v2:
> - Add missing dt-bindings and dts node.
> - Remove mtk_phy_leds_state_init() temporarily. I'm going to add LED support
> later.
> - Remove "Firmware loading/trigger ok" log.
> - Add macro define for 0x800e & 0x800f
> 
> [...]

Here is the summary with links:
  - [net-next,v4,1/2] net: phy: mediatek: Sort config and file names in Kconfig and Makefile
    https://git.kernel.org/netdev/net-next/c/6d243c80fe91
  - [net-next,v4,2/2] net: phy: mediatek: add driver for built-in 2.5G ethernet PHY on MT7988
    https://git.kernel.org/netdev/net-next/c/26948c243041

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html




From peter.wang at mediatek.com  Tue May 20 19:22:23 2025
From: peter.wang at mediatek.com (=?utf-8?B?UGV0ZXIgV2FuZyAo546L5L+h5Y+LKQ==?=)
Date: Wed, 21 May 2025 02:22:23 +0000
Subject: [PATCH v5] ufs: core: Add HID support
In-Reply-To: <3ba29109-86d8-4bc1-8f2f-49fa2e56673e@acm.org>
References: <20250520094054.313-1-tanghuan@vivo.com>
	 <ab468bb26dafca673d7ffca7dff519b7cf024cdc.camel@mediatek.com>
	 <3ba29109-86d8-4bc1-8f2f-49fa2e56673e@acm.org>
Message-ID: <8c547bfaf0c4553760e8c4980f1d2b27d43ded3c.camel@mediatek.com>

On Tue, 2025-05-20 at 13:13 -0700, Bart Van Assche wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 5/20/25 6:14 AM, Peter Wang (???) wrote:
> > On Tue, 2025-05-20 at 17:40 +0800, Huan Tang wrote:
> > > diff --git a/drivers/ufs/core/ufshcd.c
> > > b/drivers/ufs/core/ufshcd.c
> > > index 3e2097e65964..8ccd923a5761 100644
> > > --- a/drivers/ufs/core/ufshcd.c
> > > +++ b/drivers/ufs/core/ufshcd.c
> > > @@ -8390,6 +8390,10 @@ static int ufs_get_device_desc(struct
> > > ufs_hba
> > > *hba)
> > > 
> > > ??????? dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP];
> > > 
> > > +?????? dev_info->hid_sup = get_unaligned_be32(desc_buf +
> > > +
> > > DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP) &
> > > +?????????????????????????????? UFS_DEV_HID_SUPPORT;
> > > +
> > > 
> > 
> > Could add the double negation (!!) ensures the value is exactly 0
> > or 1.
> > dev_info->hid_sup = !!(get_unaligned_be32(desc_buf +
> > ???????????? DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP) &
> > ???????????? UFS_DEV_HID_SUPPORT);
> 
> Hi Peter,
> 
> I do not agree that this change is required. ufs_dev_info.hid_sup has
> type bool and hence the compiler will convert the result of the
> binary
> and operation implicitly into a boolean value (0/1). From the C23
> standard: "When any scalar value is converted to bool, the result is
> false if the value is a zero (for arithmetic types), null (for
> pointer
> types), or the scalar has type nullptr_t; otherwise, the result is
> true."
> 
> A double negation does not occur elsewhere in the kernel if an
> integer
> value is assigned to a boolean variable so I think that it shouldn't
> be
> added here either.
> 
> Bart.

Hi Bart,

Yes, this is not strictly necessary.
For me, this just makes it immediately clear that 
hid_sup is a bool. But I understand that you might 
think it redundant and some people will feel confused 
when reading this code.

It doesn't affect the correctness of this patch, and it is 
totally fine even if no changes are made at all. 
Hence I've added my review tag.

Thanks
Peter

From kyrie.wu at mediatek.com  Tue May 20 19:23:12 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Wed, 21 May 2025 10:23:12 +0800
Subject: [PATCH v4 02/12] media: dt-bindings: mediatek,jpeg: Add mediatek, mt8196-jpgenc compatible
In-Reply-To: <20250521022322.27576-1-kyrie.wu@mediatek.com>
References: <20250521022322.27576-1-kyrie.wu@mediatek.com>
Message-ID: <20250521022322.27576-3-kyrie.wu@mediatek.com>

Compared to the previous generation IC, the MT8196 uses SMMU
instead of IOMMU and supports features such as dynamic voltage
and frequency scaling. Therefore, add "mediatek,mt8196-jpgenc"
compatible to the binding document.

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 .../bindings/media/mediatek,mt8195-jpegenc.yaml           | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml
index 596186497b68..e2d772ea0fb0 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml
@@ -14,7 +14,9 @@ description:
 
 properties:
   compatible:
-    const: mediatek,mt8195-jpgenc
+    enum:
+      - mediatek,mt8195-jpgenc
+      - mediatek,mt8196-jpgenc
 
   power-domains:
     maxItems: 1
@@ -44,7 +46,9 @@ patternProperties:
 
     properties:
       compatible:
-        const: mediatek,mt8195-jpgenc-hw
+        enum:
+          - mediatek,mt8195-jpgenc-hw
+          - mediatek,mt8196-jpgenc-hw
 
       reg:
         maxItems: 1
-- 
2.46.0



From kyrie.wu at mediatek.com  Tue May 20 19:23:11 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Wed, 21 May 2025 10:23:11 +0800
Subject: [PATCH v4 01/12] media: dt-bindings: mediatek,jpeg: Add mediatek, mt8196-jpgdec compatible
In-Reply-To: <20250521022322.27576-1-kyrie.wu@mediatek.com>
References: <20250521022322.27576-1-kyrie.wu@mediatek.com>
Message-ID: <20250521022322.27576-2-kyrie.wu@mediatek.com>

Compared to the previous generation IC, the MT8196 uses SMMU
instead of IOMMU and supports features such as dynamic voltage
and frequency scaling. Therefore, add "mediatek,mt8196-jpgdec"
compatible to the binding document.

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 .../bindings/media/mediatek,mt8195-jpegdec.yaml           | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
index e5448c60e3eb..28a9a9bfdbf8 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
@@ -14,7 +14,9 @@ description:
 
 properties:
   compatible:
-    const: mediatek,mt8195-jpgdec
+    enum:
+      - mediatek,mt8195-jpgdec
+      - mediatek,mt8196-jpgdec
 
   power-domains:
     maxItems: 1
@@ -44,7 +46,9 @@ patternProperties:
 
     properties:
       compatible:
-        const: mediatek,mt8195-jpgdec-hw
+        enum:
+          - mediatek,mt8195-jpgdec-hw
+          - mediatek,mt8196-jpgdec-hw
 
       reg:
         maxItems: 1
-- 
2.46.0



From kyrie.wu at mediatek.com  Tue May 20 19:23:13 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Wed, 21 May 2025 10:23:13 +0800
Subject: [PATCH v4 03/12] media: mediatek: jpeg: add jpeg compatible
In-Reply-To: <20250521022322.27576-1-kyrie.wu@mediatek.com>
References: <20250521022322.27576-1-kyrie.wu@mediatek.com>
Message-ID: <20250521022322.27576-4-kyrie.wu@mediatek.com>

Add jpeg dec and enc compatible for mt8196

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 .../platform/mediatek/jpeg/mtk_jpeg_core.c    | 34 +++++++++++++++++++
 .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c  |  3 ++
 .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c  |  3 ++
 3 files changed, 40 insertions(+)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 7eb12449b63a..e89ccb8c904c 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1918,6 +1918,19 @@ static struct mtk_jpeg_variant mtk8195_jpegenc_drvdata = {
 	.jpeg_worker = mtk_jpegenc_worker,
 };
 
+static struct mtk_jpeg_variant mtk8196_jpegenc_drvdata = {
+	.formats = mtk_jpeg_enc_formats,
+	.num_formats = MTK_JPEG_ENC_NUM_FORMATS,
+	.qops = &mtk_jpeg_enc_qops,
+	.m2m_ops = &mtk_jpeg_multicore_enc_m2m_ops,
+	.dev_name = "mtk-jpeg-enc",
+	.ioctl_ops = &mtk_jpeg_enc_ioctl_ops,
+	.out_q_default_fourcc = V4L2_PIX_FMT_YUYV,
+	.cap_q_default_fourcc = V4L2_PIX_FMT_JPEG,
+	.multi_core = true,
+	.jpeg_worker = mtk_jpegenc_worker,
+};
+
 static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata = {
 	.formats = mtk_jpeg_dec_formats,
 	.num_formats = MTK_JPEG_DEC_NUM_FORMATS,
@@ -1931,6 +1944,19 @@ static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata = {
 	.jpeg_worker = mtk_jpegdec_worker,
 };
 
+static const struct mtk_jpeg_variant mtk8196_jpegdec_drvdata = {
+	.formats = mtk_jpeg_dec_formats,
+	.num_formats = MTK_JPEG_DEC_NUM_FORMATS,
+	.qops = &mtk_jpeg_dec_qops,
+	.m2m_ops = &mtk_jpeg_multicore_dec_m2m_ops,
+	.dev_name = "mtk-jpeg-dec",
+	.ioctl_ops = &mtk_jpeg_dec_ioctl_ops,
+	.out_q_default_fourcc = V4L2_PIX_FMT_JPEG,
+	.cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M,
+	.multi_core = true,
+	.jpeg_worker = mtk_jpegdec_worker,
+};
+
 static const struct of_device_id mtk_jpeg_match[] = {
 	{
 		.compatible = "mediatek,mt8173-jpgdec",
@@ -1952,6 +1978,14 @@ static const struct of_device_id mtk_jpeg_match[] = {
 		.compatible = "mediatek,mt8195-jpgdec",
 		.data = &mtk8195_jpegdec_drvdata,
 	},
+	{
+		.compatible = "mediatek,mt8196-jpgenc",
+		.data = &mtk8196_jpegenc_drvdata,
+	},
+	{
+		.compatible = "mediatek,mt8196-jpgdec",
+		.data = &mtk8196_jpegdec_drvdata,
+	},
 	{},
 };
 
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index e78e1d11093c..20553bf541df 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -45,6 +45,9 @@ static const struct of_device_id mtk_jpegdec_hw_ids[] = {
 	{
 		.compatible = "mediatek,mt8195-jpgdec-hw",
 	},
+	{
+		.compatible = "mediatek,mt8196-jpgdec-hw",
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_jpegdec_hw_ids);
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
index 9ab27aee302a..69c95113f205 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
@@ -52,6 +52,9 @@ static const struct of_device_id mtk_jpegenc_drv_ids[] = {
 	{
 		.compatible = "mediatek,mt8195-jpgenc-hw",
 	},
+	{
+		.compatible = "mediatek,mt8196-jpgenc-hw",
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_jpegenc_drv_ids);
-- 
2.46.0



From kyrie.wu at mediatek.com  Tue May 20 19:23:10 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Wed, 21 May 2025 10:23:10 +0800
Subject: [PATCH v4 00/12] Enable jpeg enc & dec multi-hardwares for MT8196
Message-ID: <20250521022322.27576-1-kyrie.wu@mediatek.com>

This series adds support for mt8196 multi-hardwares jpeg enc & dec,
by first adding mt8196 jpegdec and jpegenc compatible to install
kernel driver. Add smmu setting to support smmu and iommu at the
same time.
Secondly refactor buffer and clock setting to support multi-hw jpeg
working.
Lastly, fix some bugs, including resolution change handleing, stop
streaming sw flow and others.

This series has been tested with MT8196 tast test.
Encoding and decoding worked for this chip.

Patches 1-3 Adds jpeg encoder and decoder compatible.
Patches 4 add jpeg smmu sid setting.
Patches 5 fix jpeg hw count setting to support different chips.
Patches 6 refactor jpeg buffer payload setting to handle buffer
size bug while resolution changed.
Patches 7 reconstruct jpeg dst buffer layout.
Patches 8 fix multi-core stop streaming flow
Patches 9 refactor multi-core clk suspend/resume setting
Patches 10 fix decoding buffer number setting timing issue
Patches 11 refactor decoding resolution change operation
Patches 12 fix remove buffer operation

---
This series patches dependent on:
[1]
https://patchwork.linuxtv.org/project/linux-media/patch/20250424090824.5309-1-jianhua.lin at mediatek.com/

Changes compared with v3:
--change patch subject of jpeg encoder and decoder compatible.

Changes compared with v2:
--refactor smmu sid setting function interface
--Some modifications for patch v2's review comments.

Changes compared with v1:
--refine jpeg dt-bindings for MT8196
--optimize software code to manage jpeg HW count
--refactor smmu sid setting function interface
--Some modifications for patch v1's review comments.

Kyrie Wu (12):
  media: dt-bindings: mediatek,jpeg: Add mediatek, mt8196-jpgdec
    compatible
  media: dt-bindings: mediatek,jpeg: Add mediatek, mt8196-jpgenc
    compatible
  media: mediatek: jpeg: add jpeg compatible
  media: mediatek: jpeg: add jpeg smmu sid setting
  media: mediatek: jpeg: fix jpeg hw count setting
  media: mediatek: jpeg: refactor jpeg buffer payload setting
  media: mediatek: jpeg: refactor jpeg dst buffer layout
  media: mediatek: jpeg: fix stop streaming flow for multi-core
  media: mediatek: jpeg: refactor multi-core clk suspend and resume
    setting
  media: mediatek: jpeg: fix decoding buffer number setting timing issue
  media: mediatek: jpeg: refactor decoding resolution change operation
  media: mediatek: jpeg: fix remove buffer operation for multi-core

 .../media/mediatek,mt8195-jpegdec.yaml        |   8 +-
 .../media/mediatek,mt8195-jpegenc.yaml        |   8 +-
 .../platform/mediatek/jpeg/mtk_jpeg_core.c    | 169 +++++++++++++-----
 .../platform/mediatek/jpeg/mtk_jpeg_core.h    |  21 ++-
 .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c  | 112 +++++++++++-
 .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c  | 112 +++++++++++-
 6 files changed, 377 insertions(+), 53 deletions(-)

-- 
2.46.0



From kyrie.wu at mediatek.com  Tue May 20 19:23:14 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Wed, 21 May 2025 10:23:14 +0800
Subject: [PATCH v4 04/12] media: mediatek: jpeg: add jpeg smmu sid setting
In-Reply-To: <20250521022322.27576-1-kyrie.wu@mediatek.com>
References: <20250521022322.27576-1-kyrie.wu@mediatek.com>
Message-ID: <20250521022322.27576-5-kyrie.wu@mediatek.com>

Add a configuration to set jpeg dec & enc smmu sid

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 .../platform/mediatek/jpeg/mtk_jpeg_core.c    | 37 +++++++++++++++++++
 .../platform/mediatek/jpeg/mtk_jpeg_core.h    | 15 ++++++++
 .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c  | 23 ++++++++++++
 .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c  | 23 ++++++++++++
 4 files changed, 98 insertions(+)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index e89ccb8c904c..ea890f01fa9e 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -15,6 +15,7 @@
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/regmap.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <media/v4l2-event.h>
@@ -1584,6 +1585,20 @@ static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg_dev *jpeg)
 	return IRQ_HANDLED;
 }
 
+static void mtk_jpeg_enc_set_smmu_sid(struct mtk_jpegenc_comp_dev *jpeg)
+{
+	struct mtk_jpeg_dev *mjpeg = jpeg->master_dev;
+
+	if (!mjpeg->variant->support_smmu || !jpeg->smmu_regmap)
+		return;
+
+	regmap_update_bits(jpeg->smmu_regmap, JPEG_ENC_SMMU_SID,
+			   JPG_REG_GUSER_ID_MASK <<
+			   JPG_REG_ENC_GUSER_ID_SHIFT,
+			   JPG_REG_GUSER_ID_ENC_SID <<
+			   JPG_REG_ENC_GUSER_ID_SHIFT);
+}
+
 static void mtk_jpegenc_worker(struct work_struct *work)
 {
 	struct mtk_jpegenc_comp_dev *comp_jpeg[MTK_JPEGENC_HW_MAX];
@@ -1655,6 +1670,9 @@ static void mtk_jpegenc_worker(struct work_struct *work)
 	jpeg_dst_buf->frame_num = ctx->total_frame_num;
 	ctx->total_frame_num++;
 	mtk_jpeg_enc_reset(comp_jpeg[hw_id]->reg_base);
+
+	mtk_jpeg_enc_set_smmu_sid(comp_jpeg[hw_id]);
+
 	mtk_jpeg_set_enc_dst(ctx,
 			     comp_jpeg[hw_id]->reg_base,
 			     &dst_buf->vb2_buf);
@@ -1679,6 +1697,20 @@ static void mtk_jpegenc_worker(struct work_struct *work)
 	v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
 }
 
+static void mtk_jpeg_dec_set_smmu_sid(struct mtk_jpegdec_comp_dev *jpeg)
+{
+	struct mtk_jpeg_dev *mjpeg = jpeg->master_dev;
+
+	if (!mjpeg->variant->support_smmu || !jpeg->smmu_regmap)
+		return;
+
+	regmap_update_bits(jpeg->smmu_regmap, JPEG_DEC_SMMU_SID,
+			   JPG_REG_GUSER_ID_MASK <<
+			   JPG_REG_DEC_GUSER_ID_SHIFT,
+			   JPG_REG_GUSER_ID_DEC_SID <<
+			   JPG_REG_DEC_GUSER_ID_SHIFT);
+}
+
 static void mtk_jpegdec_worker(struct work_struct *work)
 {
 	struct mtk_jpeg_ctx *ctx = container_of(work, struct mtk_jpeg_ctx,
@@ -1771,6 +1803,9 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 	spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags);
 	ctx->total_frame_num++;
 	mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base);
+
+	mtk_jpeg_dec_set_smmu_sid(comp_jpeg[hw_id]);
+
 	mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base,
 				jpeg->variant->support_34bit,
 				&jpeg_src_buf->dec_param,
@@ -1929,6 +1964,7 @@ static struct mtk_jpeg_variant mtk8196_jpegenc_drvdata = {
 	.cap_q_default_fourcc = V4L2_PIX_FMT_JPEG,
 	.multi_core = true,
 	.jpeg_worker = mtk_jpegenc_worker,
+	.support_smmu = true,
 };
 
 static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata = {
@@ -1955,6 +1991,7 @@ static const struct mtk_jpeg_variant mtk8196_jpegdec_drvdata = {
 	.cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M,
 	.multi_core = true,
 	.jpeg_worker = mtk_jpegdec_worker,
+	.support_smmu = true,
 };
 
 static const struct of_device_id mtk_jpeg_match[] = {
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
index 02ed0ed5b736..46899512a5e6 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
@@ -11,6 +11,7 @@
 
 #include <linux/clk.h>
 #include <linux/interrupt.h>
+#include <linux/mfd/syscon.h>
 #include <media/v4l2-ctrls.h>
 #include <media/v4l2-device.h>
 #include <media/v4l2-fh.h>
@@ -34,6 +35,14 @@
 
 #define MTK_JPEG_MAX_EXIF_SIZE	(64 * 1024)
 
+#define JPEG_DEC_SMMU_SID				0
+#define JPEG_ENC_SMMU_SID				0
+#define JPG_REG_GUSER_ID_MASK			0x7
+#define JPG_REG_GUSER_ID_DEC_SID		0x4
+#define JPG_REG_GUSER_ID_ENC_SID		0x5
+#define JPG_REG_DEC_GUSER_ID_SHIFT		8
+#define JPG_REG_ENC_GUSER_ID_SHIFT		4
+
 #define MTK_JPEG_ADDR_MASK GENMASK(1, 0)
 
 /**
@@ -65,6 +74,7 @@ enum mtk_jpeg_ctx_state {
  * @multi_core:		mark jpeg hw is multi_core or not
  * @jpeg_worker:		jpeg dec or enc worker
  * @support_34bit:	flag to check support for 34-bit DMA address
+ * @support_smmu:	flag to check if support smmu
  */
 struct mtk_jpeg_variant {
 	struct clk_bulk_data *clks;
@@ -82,6 +92,7 @@ struct mtk_jpeg_variant {
 	bool multi_core;
 	void (*jpeg_worker)(struct work_struct *work);
 	bool support_34bit;
+	bool support_smmu;
 };
 
 struct mtk_jpeg_src_buf {
@@ -150,6 +161,7 @@ struct mtk_jpegdec_clk {
  * @hw_param:		jpeg encode hw parameters
  * @hw_state:		record hw state
  * @hw_lock:		spinlock protecting the hw device resource
+ * @smmu_regmap:	SMMU registers mapping
  */
 struct mtk_jpegenc_comp_dev {
 	struct device *dev;
@@ -163,6 +175,7 @@ struct mtk_jpegenc_comp_dev {
 	enum mtk_jpeg_hw_state hw_state;
 	/* spinlock protecting the hw device resource */
 	spinlock_t hw_lock;
+	struct regmap *smmu_regmap;
 };
 
 /**
@@ -177,6 +190,7 @@ struct mtk_jpegenc_comp_dev {
  * @hw_param:			jpeg decode hw parameters
  * @hw_state:			record hw state
  * @hw_lock:			spinlock protecting hw
+ * @smmu_regmap:		SMMU registers mapping
  */
 struct mtk_jpegdec_comp_dev {
 	struct device *dev;
@@ -190,6 +204,7 @@ struct mtk_jpegdec_comp_dev {
 	enum mtk_jpeg_hw_state hw_state;
 	/* spinlock protecting the hw device resource */
 	spinlock_t hw_lock;
+	struct regmap *smmu_regmap;
 };
 
 /**
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index 20553bf541df..059377805706 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -616,6 +616,25 @@ static int mtk_jpegdec_hw_init_irq(struct mtk_jpegdec_comp_dev *dev)
 	return 0;
 }
 
+static int mtk_jpegdec_smmu_init(struct mtk_jpegdec_comp_dev *dev)
+{
+	struct mtk_jpeg_dev *master_dev = dev->master_dev;
+
+	if (!master_dev->variant->support_smmu)
+		return 0;
+
+	dev->smmu_regmap =
+		syscon_regmap_lookup_by_phandle(dev->plat_dev->dev.of_node,
+						"mediatek,smmu-config");
+	if (IS_ERR(dev->smmu_regmap)) {
+		return dev_err_probe(dev->dev, dev->smmu_regmap,
+				     "mmap smmu_base failed(%ld)\n",
+				     PTR_ERR(dev->smmu_regmap));
+	}
+
+	return 0;
+}
+
 static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
 {
 	struct mtk_jpegdec_clk *jpegdec_clk;
@@ -668,6 +687,10 @@ static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
 	master_dev->reg_decbase[i] = dev->reg_base;
 	dev->master_dev = master_dev;
 
+	ret = mtk_jpegdec_smmu_init(dev);
+	if (ret)
+		return ret;
+
 	platform_set_drvdata(pdev, dev);
 	pm_runtime_enable(&pdev->dev);
 
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
index 69c95113f205..73c55e1546aa 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
@@ -340,6 +340,25 @@ static int mtk_jpegenc_hw_init_irq(struct mtk_jpegenc_comp_dev *dev)
 	return 0;
 }
 
+static int mtk_jpegenc_smmu_init(struct mtk_jpegenc_comp_dev *dev)
+{
+	struct mtk_jpeg_dev *master_dev = dev->master_dev;
+
+	if (!master_dev->variant->support_smmu)
+		return 0;
+
+	dev->smmu_regmap =
+		syscon_regmap_lookup_by_phandle(dev->plat_dev->dev.of_node,
+						"mediatek,smmu-config");
+	if (IS_ERR(dev->smmu_regmap)) {
+		return dev_err_probe(dev->dev, dev->smmu_regmap,
+				     "mmap smmu_base failed(%ld)\n",
+				     PTR_ERR(dev->smmu_regmap));
+	}
+
+	return 0;
+}
+
 static int mtk_jpegenc_hw_probe(struct platform_device *pdev)
 {
 	struct mtk_jpegenc_clk *jpegenc_clk;
@@ -390,6 +409,10 @@ static int mtk_jpegenc_hw_probe(struct platform_device *pdev)
 	master_dev->reg_encbase[i] = dev->reg_base;
 	dev->master_dev = master_dev;
 
+	ret = mtk_jpegenc_smmu_init(dev);
+	if (ret)
+		return ret;
+
 	platform_set_drvdata(pdev, dev);
 	pm_runtime_enable(&pdev->dev);
 
-- 
2.46.0



From kyrie.wu at mediatek.com  Tue May 20 19:23:16 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Wed, 21 May 2025 10:23:16 +0800
Subject: [PATCH v4 06/12] media: mediatek: jpeg: refactor jpeg buffer payload setting
In-Reply-To: <20250521022322.27576-1-kyrie.wu@mediatek.com>
References: <20250521022322.27576-1-kyrie.wu@mediatek.com>
Message-ID: <20250521022322.27576-7-kyrie.wu@mediatek.com>

1. for multi-core jpegdec:
   core0: |<-------- decoding buffer0 and resolution changed to smaller
   core1:  |<-------- decoding buffer1
   core0:   |<- handling resolution changing
   core0:    |<- vb2_set_plane_payload
2. the payload size is changed on the step of set format. Because core1
is running and streaming has not been stopped, the format cannot be
set again, resulting in no change in the payload size.
3. at this time, the payload size is bigger than buffer length,
it will print a warnning call trace
4. set payload size must less than buffer length

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 .../platform/mediatek/jpeg/mtk_jpeg_core.c     | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 0074d1edb534..52d59bb5c9ad 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -720,10 +720,22 @@ static int mtk_jpeg_buf_prepare(struct vb2_buffer *vb)
 		plane_fmt = q_data->pix_mp.plane_fmt[i];
 		if (ctx->enable_exif &&
 		    q_data->fmt->fourcc == V4L2_PIX_FMT_JPEG)
-			vb2_set_plane_payload(vb, i, plane_fmt.sizeimage +
-					      MTK_JPEG_MAX_EXIF_SIZE);
+			if (vb->planes[i].length > (plane_fmt.sizeimage +
+			    MTK_JPEG_MAX_EXIF_SIZE))
+				vb2_set_plane_payload(vb, i,
+						      plane_fmt.sizeimage +
+						      MTK_JPEG_MAX_EXIF_SIZE);
+			else
+				vb2_set_plane_payload(vb, i,
+						      vb->planes[i].length);
+
 		else
-			vb2_set_plane_payload(vb, i,  plane_fmt.sizeimage);
+			if (vb->planes[i].length > plane_fmt.sizeimage)
+				vb2_set_plane_payload(vb, i,
+						      plane_fmt.sizeimage);
+			else
+				vb2_set_plane_payload(vb, i,
+						      vb->planes[i].length);
 	}
 
 	return 0;
-- 
2.46.0



From kyrie.wu at mediatek.com  Tue May 20 19:23:17 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Wed, 21 May 2025 10:23:17 +0800
Subject: [PATCH v4 07/12] media: mediatek: jpeg: refactor jpeg dst buffer layout
In-Reply-To: <20250521022322.27576-1-kyrie.wu@mediatek.com>
References: <20250521022322.27576-1-kyrie.wu@mediatek.com>
Message-ID: <20250521022322.27576-8-kyrie.wu@mediatek.com>

1. change dst buffer size to same as struct mtk_jpeg_src_buf
to make sure all params of mtk_jpeg_src_buf could get a memory.
2. For memory alloc operation:
the v4l2 framework malloc a memory, the base addr is vb2_buffer and
the size is sizeof(struct mtk_jpeg_src_buf), mtk_jpeg_src_buf could get
itself addr by container_of like that:
vb2_buffer -> vb2_v4l2_buffer -> mtk_jpeg_src_buf.
vb2_v4l2_buffer must keep on the top of mtk_jpeg_src_buf.

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c | 2 +-
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 52d59bb5c9ad..7e3509be6f69 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1103,7 +1103,7 @@ static int mtk_jpeg_queue_init(void *priv, struct vb2_queue *src_vq,
 	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
 	dst_vq->io_modes = VB2_DMABUF | VB2_MMAP;
 	dst_vq->drv_priv = ctx;
-	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+	dst_vq->buf_struct_size = sizeof(struct mtk_jpeg_src_buf);
 	dst_vq->ops = jpeg->variant->qops;
 	dst_vq->mem_ops = &vb2_dma_contig_memops;
 	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
index 655dc9c3280c..186cd1862028 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
@@ -96,10 +96,10 @@ struct mtk_jpeg_variant {
 };
 
 struct mtk_jpeg_src_buf {
-	u32 frame_num;
 	struct vb2_v4l2_buffer b;
 	struct list_head list;
 	u32 bs_size;
+	u32 frame_num;
 	struct mtk_jpeg_dec_param dec_param;
 
 	struct mtk_jpeg_ctx *curr_ctx;
-- 
2.46.0



From kyrie.wu at mediatek.com  Tue May 20 19:23:20 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Wed, 21 May 2025 10:23:20 +0800
Subject: [PATCH v4 10/12] media: mediatek: jpeg: fix decoding buffer number setting timing issue
In-Reply-To: <20250521022322.27576-1-kyrie.wu@mediatek.com>
References: <20250521022322.27576-1-kyrie.wu@mediatek.com>
Message-ID: <20250521022322.27576-11-kyrie.wu@mediatek.com>

move decoding buffer increase code into spinlock
protecting aera for multi-core

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c   | 9 +++------
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 1 +
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 1 +
 3 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index c1d2de92f125..795916206c7c 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1782,7 +1782,6 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 
 	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
 	jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(&src_buf->vb2_buf);
-	jpeg_dst_buf = mtk_jpeg_vb2_to_srcbuf(&dst_buf->vb2_buf);
 
 	if (mtk_jpeg_check_resolution_change(ctx,
 					     &jpeg_src_buf->dec_param)) {
@@ -1791,11 +1790,6 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 		goto getbuf_fail;
 	}
 
-	jpeg_src_buf->curr_ctx = ctx;
-	jpeg_src_buf->frame_num = ctx->total_frame_num;
-	jpeg_dst_buf->curr_ctx = ctx;
-	jpeg_dst_buf->frame_num = ctx->total_frame_num;
-
 	mtk_jpegdec_set_hw_param(ctx, hw_id, src_buf, dst_buf);
 	ret = pm_runtime_resume_and_get(comp_jpeg[hw_id]->dev);
 	if (ret < 0) {
@@ -1820,6 +1814,9 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 			      msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC));
 
 	spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags);
+	jpeg_dst_buf = mtk_jpeg_vb2_to_srcbuf(&dst_buf->vb2_buf);
+	jpeg_dst_buf->curr_ctx = ctx;
+	jpeg_dst_buf->frame_num = ctx->total_frame_num;
 	ctx->total_frame_num++;
 	mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base);
 
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index 5d9a247f0360..2dd5543fb02e 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -516,6 +516,7 @@ static void mtk_jpegdec_put_buf(struct mtk_jpegdec_comp_dev *jpeg)
 				v4l2_m2m_buf_done(&tmp_dst_done_buf->b,
 						  VB2_BUF_STATE_DONE);
 				ctx->last_done_frame_num++;
+				break;
 			}
 		}
 	}
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
index 75cd3627c5ae..f5f11ae9c92a 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
@@ -245,6 +245,7 @@ static void mtk_jpegenc_put_buf(struct mtk_jpegenc_comp_dev *jpeg)
 				v4l2_m2m_buf_done(&tmp_dst_done_buf->b,
 						  VB2_BUF_STATE_DONE);
 				ctx->last_done_frame_num++;
+				break;
 			}
 		}
 	}
-- 
2.46.0



From kyrie.wu at mediatek.com  Tue May 20 19:23:21 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Wed, 21 May 2025 10:23:21 +0800
Subject: [PATCH v4 11/12] media: mediatek: jpeg: refactor decoding resolution change operation
In-Reply-To: <20250521022322.27576-1-kyrie.wu@mediatek.com>
References: <20250521022322.27576-1-kyrie.wu@mediatek.com>
Message-ID: <20250521022322.27576-12-kyrie.wu@mediatek.com>

For multi-core:
1.if there are only two src buffers, hw0 and hw1 are decoding
at the same time. When resolution change occurred on one hw,
the src buffer cannot be got in the stop streaming function,
which will cause a crash.
2.When a resolution change occurs, immediately set the new
resolution parameter to save the new resolution;
3.After a resolution change occurred, decoding should not continue,
needs to wait until new buffers are ready and the state machine
changed.

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 795916206c7c..eba9f58b9198 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -891,7 +891,8 @@ static void mtk_jpeg_dec_stop_streaming(struct vb2_queue *q)
 
 		vb = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
 		src_buf = mtk_jpeg_vb2_to_srcbuf(&vb->vb2_buf);
-		mtk_jpeg_set_queue_data(ctx, &src_buf->dec_param);
+		if (!IS_ERR_OR_NULL(src_buf))
+			mtk_jpeg_set_queue_data(ctx, &src_buf->dec_param);
 		ctx->state = MTK_JPEG_RUNNING;
 	} else if (V4L2_TYPE_IS_OUTPUT(q->type)) {
 		ctx->state = MTK_JPEG_INIT;
@@ -1785,11 +1786,15 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 
 	if (mtk_jpeg_check_resolution_change(ctx,
 					     &jpeg_src_buf->dec_param)) {
-		mtk_jpeg_queue_src_chg_event(ctx);
+		mtk_jpeg_set_queue_data(ctx, &jpeg_src_buf->dec_param);
 		ctx->state = MTK_JPEG_SOURCE_CHANGE;
+		mtk_jpeg_queue_src_chg_event(ctx);
 		goto getbuf_fail;
 	}
 
+	if (ctx->state == MTK_JPEG_SOURCE_CHANGE)
+		goto getbuf_fail;
+
 	mtk_jpegdec_set_hw_param(ctx, hw_id, src_buf, dst_buf);
 	ret = pm_runtime_resume_and_get(comp_jpeg[hw_id]->dev);
 	if (ret < 0) {
-- 
2.46.0



From kyrie.wu at mediatek.com  Tue May 20 19:23:19 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Wed, 21 May 2025 10:23:19 +0800
Subject: [PATCH v4 09/12] media: mediatek: jpeg: refactor multi-core clk suspend and resume setting
In-Reply-To: <20250521022322.27576-1-kyrie.wu@mediatek.com>
References: <20250521022322.27576-1-kyrie.wu@mediatek.com>
Message-ID: <20250521022322.27576-10-kyrie.wu@mediatek.com>

refactor jpeg clk suspend and resume setting for multi-core

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 .../platform/mediatek/jpeg/mtk_jpeg_core.c    | 28 +++----
 .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c  | 75 ++++++++++++++++++-
 .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c  | 75 ++++++++++++++++++-
 3 files changed, 151 insertions(+), 27 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 1d3df1230191..c1d2de92f125 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1126,6 +1126,9 @@ static void mtk_jpeg_clk_on(struct mtk_jpeg_dev *jpeg)
 {
 	int ret;
 
+	if (jpeg->variant->multi_core)
+		return;
+
 	ret = clk_bulk_prepare_enable(jpeg->variant->num_clks,
 				      jpeg->variant->clks);
 	if (ret)
@@ -1134,6 +1137,9 @@ static void mtk_jpeg_clk_on(struct mtk_jpeg_dev *jpeg)
 
 static void mtk_jpeg_clk_off(struct mtk_jpeg_dev *jpeg)
 {
+	if (jpeg->variant->multi_core)
+		return;
+
 	clk_bulk_disable_unprepare(jpeg->variant->num_clks,
 				   jpeg->variant->clks);
 }
@@ -1677,13 +1683,6 @@ static void mtk_jpegenc_worker(struct work_struct *work)
 		goto enc_end;
 	}
 
-	ret = clk_prepare_enable(comp_jpeg[hw_id]->venc_clk.clks->clk);
-	if (ret) {
-		dev_err(jpeg->dev, "%s : %d, jpegenc clk_prepare_enable fail\n",
-			__func__, __LINE__);
-		goto enc_end;
-	}
-
 	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
 	v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
 
@@ -1798,20 +1797,13 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 	jpeg_dst_buf->frame_num = ctx->total_frame_num;
 
 	mtk_jpegdec_set_hw_param(ctx, hw_id, src_buf, dst_buf);
-	ret = pm_runtime_get_sync(comp_jpeg[hw_id]->dev);
+	ret = pm_runtime_resume_and_get(comp_jpeg[hw_id]->dev);
 	if (ret < 0) {
 		dev_err(jpeg->dev, "%s : %d, pm_runtime_get_sync fail !!!\n",
 			__func__, __LINE__);
 		goto dec_end;
 	}
 
-	ret = clk_prepare_enable(comp_jpeg[hw_id]->jdec_clk.clks->clk);
-	if (ret) {
-		dev_err(jpeg->dev, "%s : %d, jpegdec clk_prepare_enable fail\n",
-			__func__, __LINE__);
-		goto clk_end;
-	}
-
 	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
 	v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
 
@@ -1821,7 +1813,7 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 				 &dst_buf->vb2_buf, &fb)) {
 		dev_err(jpeg->dev, "%s : %d, mtk_jpeg_set_dec_dst fail\n",
 			__func__, __LINE__);
-		goto setdst_end;
+		goto set_dst_fail;
 	}
 
 	schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work,
@@ -1846,9 +1838,7 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 
 	return;
 
-setdst_end:
-	clk_disable_unprepare(comp_jpeg[hw_id]->jdec_clk.clks->clk);
-clk_end:
+set_dst_fail:
 	pm_runtime_put(comp_jpeg[hw_id]->dev);
 dec_end:
 	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index c1e10af2086b..5d9a247f0360 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -543,14 +543,13 @@ static void mtk_jpegdec_timeout_work(struct work_struct *work)
 	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
 
 	mtk_jpeg_dec_reset(cjpeg->reg_base);
-	clk_disable_unprepare(cjpeg->jdec_clk.clks->clk);
-	pm_runtime_put(cjpeg->dev);
 	cjpeg->hw_state = MTK_JPEG_HW_IDLE;
 	atomic_inc(&master_jpeg->hw_rdy);
 	wake_up(&master_jpeg->hw_wq);
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegdec_put_buf(cjpeg);
 	jpeg_buf_queue_dec(ctx);
+	pm_runtime_put(cjpeg->dev);
 }
 
 static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
@@ -592,12 +591,11 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegdec_put_buf(jpeg);
 	jpeg_buf_queue_dec(ctx);
-	pm_runtime_put(ctx->jpeg->dev);
-	clk_disable_unprepare(jpeg->jdec_clk.clks->clk);
 
 	jpeg->hw_state = MTK_JPEG_HW_IDLE;
 	wake_up(&master_jpeg->hw_wq);
 	atomic_inc(&master_jpeg->hw_rdy);
+	pm_runtime_put(jpeg->dev);
 
 	return IRQ_HANDLED;
 }
@@ -703,15 +701,84 @@ static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, dev);
 	pm_runtime_enable(&pdev->dev);
+	ret = devm_clk_bulk_get(dev->dev,
+				jpegdec_clk->clk_num,
+				jpegdec_clk->clks);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to init clk\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void mtk_jpeg_clk_on(struct mtk_jpegdec_comp_dev *jpeg)
+{
+	int ret;
+
+	ret = clk_bulk_prepare_enable(jpeg->jdec_clk.clk_num,
+				      jpeg->jdec_clk.clks);
+	if (ret)
+		dev_err(jpeg->dev, "%s : %d, jpegdec clk_prepare_enable fail\n",
+			__func__, __LINE__);
+}
+
+static void mtk_jpeg_clk_off(struct mtk_jpegdec_comp_dev *jpeg)
+{
+	clk_bulk_disable_unprepare(jpeg->jdec_clk.clk_num,
+				   jpeg->jdec_clk.clks);
+}
+
+static __maybe_unused int mtk_jpegdec_pm_suspend(struct device *dev)
+{
+	struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev);
+
+	mtk_jpeg_clk_off(jpeg);
 
 	return 0;
 }
 
+static __maybe_unused int mtk_jpegdec_pm_resume(struct device *dev)
+{
+	struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev);
+
+	mtk_jpeg_clk_on(jpeg);
+
+	return 0;
+}
+
+static __maybe_unused int mtk_jpegdec_suspend(struct device *dev)
+{
+	struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev);
+
+	v4l2_m2m_suspend(jpeg->master_dev->m2m_dev);
+	return pm_runtime_force_suspend(dev);
+}
+
+static __maybe_unused int mtk_jpegdec_resume(struct device *dev)
+{
+	struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev);
+	int ret;
+
+	ret = pm_runtime_force_resume(dev);
+	if (ret < 0)
+		return ret;
+
+	v4l2_m2m_resume(jpeg->master_dev->m2m_dev);
+	return ret;
+}
+
+static const struct dev_pm_ops mtk_jpegdec_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(mtk_jpegdec_suspend, mtk_jpegdec_resume)
+	SET_RUNTIME_PM_OPS(mtk_jpegdec_pm_suspend, mtk_jpegdec_pm_resume, NULL)
+};
+
 static struct platform_driver mtk_jpegdec_hw_driver = {
 	.probe = mtk_jpegdec_hw_probe,
 	.driver = {
 		.name = "mtk-jpegdec-hw",
 		.of_match_table = mtk_jpegdec_hw_ids,
+		.pm             = &mtk_jpegdec_pm_ops,
 	},
 };
 
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
index 2d7e72a424c5..75cd3627c5ae 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
@@ -274,14 +274,13 @@ static void mtk_jpegenc_timeout_work(struct work_struct *work)
 	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
 
 	mtk_jpeg_enc_reset(cjpeg->reg_base);
-	clk_disable_unprepare(cjpeg->venc_clk.clks->clk);
-	pm_runtime_put(cjpeg->dev);
 	cjpeg->hw_state = MTK_JPEG_HW_IDLE;
 	atomic_inc(&master_jpeg->hw_rdy);
 	wake_up(&master_jpeg->hw_wq);
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegenc_put_buf(cjpeg);
 	jpeg_buf_queue_dec(ctx);
+	pm_runtime_put(cjpeg->dev);
 }
 
 static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
@@ -316,12 +315,11 @@ static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegenc_put_buf(jpeg);
 	jpeg_buf_queue_dec(ctx);
-	pm_runtime_put(ctx->jpeg->dev);
-	clk_disable_unprepare(jpeg->venc_clk.clks->clk);
 
 	jpeg->hw_state = MTK_JPEG_HW_IDLE;
 	wake_up(&master_jpeg->hw_wq);
 	atomic_inc(&master_jpeg->hw_rdy);
+	pm_runtime_put(jpeg->dev);
 
 	return IRQ_HANDLED;
 }
@@ -425,15 +423,84 @@ static int mtk_jpegenc_hw_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, dev);
 	pm_runtime_enable(&pdev->dev);
+	ret = devm_clk_bulk_get(dev->dev,
+				jpegenc_clk->clk_num,
+				jpegenc_clk->clks);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to init clk\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void mtk_jpeg_clk_on(struct mtk_jpegenc_comp_dev *jpeg)
+{
+	int ret;
+
+	ret = clk_bulk_prepare_enable(jpeg->venc_clk.clk_num,
+				      jpeg->venc_clk.clks);
+	if (ret)
+		dev_err(jpeg->dev, "%s : %d, jpegenc clk_prepare_enable fail\n",
+			__func__, __LINE__);
+}
+
+static void mtk_jpeg_clk_off(struct mtk_jpegenc_comp_dev *jpeg)
+{
+	clk_bulk_disable_unprepare(jpeg->venc_clk.clk_num,
+				   jpeg->venc_clk.clks);
+}
+
+static __maybe_unused int mtk_jpegenc_pm_suspend(struct device *dev)
+{
+	struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev);
+
+	mtk_jpeg_clk_off(jpeg);
 
 	return 0;
 }
 
+static __maybe_unused int mtk_jpegenc_pm_resume(struct device *dev)
+{
+	struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev);
+
+	mtk_jpeg_clk_on(jpeg);
+
+	return 0;
+}
+
+static __maybe_unused int mtk_jpegenc_suspend(struct device *dev)
+{
+	struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev);
+
+	v4l2_m2m_suspend(jpeg->master_dev->m2m_dev);
+	return pm_runtime_force_suspend(dev);
+}
+
+static __maybe_unused int mtk_jpegenc_resume(struct device *dev)
+{
+	struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev);
+	int ret;
+
+	ret = pm_runtime_force_resume(dev);
+	if (ret < 0)
+		return ret;
+
+	v4l2_m2m_resume(jpeg->master_dev->m2m_dev);
+	return ret;
+}
+
+static const struct dev_pm_ops mtk_jpegenc_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(mtk_jpegenc_suspend, mtk_jpegenc_resume)
+	SET_RUNTIME_PM_OPS(mtk_jpegenc_pm_suspend, mtk_jpegenc_pm_resume, NULL)
+};
+
 static struct platform_driver mtk_jpegenc_hw_driver = {
 	.probe = mtk_jpegenc_hw_probe,
 	.driver = {
 		.name = "mtk-jpegenc-hw",
 		.of_match_table = mtk_jpegenc_drv_ids,
+		.pm = &mtk_jpegenc_pm_ops,
 	},
 };
 
-- 
2.46.0



From kyrie.wu at mediatek.com  Tue May 20 19:23:18 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Wed, 21 May 2025 10:23:18 +0800
Subject: [PATCH v4 08/12] media: mediatek: jpeg: fix stop streaming flow for multi-core
In-Reply-To: <20250521022322.27576-1-kyrie.wu@mediatek.com>
References: <20250521022322.27576-1-kyrie.wu@mediatek.com>
Message-ID: <20250521022322.27576-9-kyrie.wu@mediatek.com>

1. For multi-core jpegdec, the all hws may run at the same time,
if one hw decoded firstly, the function of mtk_jpeg_dec_stop_streaming
would be called, but others input buffers are decoding, this will
cause some running buffers to be buffer done, causing errors;
2. add a parameter to calculate the decoding buffer counts, it
wil decrease to 0 until the all buffers decoded and the
mtk_jpeg_dec_stop_streaming could continue to be executed.

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 .../media/platform/mediatek/jpeg/mtk_jpeg_core.c | 16 ++++++++++++++++
 .../media/platform/mediatek/jpeg/mtk_jpeg_core.h |  2 ++
 .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c     |  9 +++++++++
 .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c     |  9 +++++++++
 4 files changed, 36 insertions(+)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 7e3509be6f69..1d3df1230191 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -861,8 +861,12 @@ static struct vb2_v4l2_buffer *mtk_jpeg_buf_remove(struct mtk_jpeg_ctx *ctx,
 static void mtk_jpeg_enc_stop_streaming(struct vb2_queue *q)
 {
 	struct mtk_jpeg_ctx *ctx = vb2_get_drv_priv(q);
+	struct mtk_jpeg_dev *jpeg = ctx->jpeg;
 	struct vb2_v4l2_buffer *vb;
 
+	if (jpeg->variant->multi_core)
+		wait_event(jpeg->hw_wq, (atomic_read(&ctx->buf_list_cnt) == 0));
+
 	while ((vb = mtk_jpeg_buf_remove(ctx, q->type)))
 		v4l2_m2m_buf_done(vb, VB2_BUF_STATE_ERROR);
 }
@@ -870,6 +874,7 @@ static void mtk_jpeg_enc_stop_streaming(struct vb2_queue *q)
 static void mtk_jpeg_dec_stop_streaming(struct vb2_queue *q)
 {
 	struct mtk_jpeg_ctx *ctx = vb2_get_drv_priv(q);
+	struct mtk_jpeg_dev *jpeg = ctx->jpeg;
 	struct vb2_v4l2_buffer *vb;
 
 	/*
@@ -877,6 +882,9 @@ static void mtk_jpeg_dec_stop_streaming(struct vb2_queue *q)
 	 * Before STREAMOFF, we still have to return the old resolution and
 	 * subsampling. Update capture queue when the stream is off.
 	 */
+	if (jpeg->variant->multi_core)
+		wait_event(jpeg->hw_wq, (atomic_read(&ctx->buf_list_cnt) == 0));
+
 	if (ctx->state == MTK_JPEG_SOURCE_CHANGE &&
 	    V4L2_TYPE_IS_CAPTURE(q->type)) {
 		struct mtk_jpeg_src_buf *src_buf;
@@ -1186,6 +1194,7 @@ static int mtk_jpeg_open(struct file *file)
 	v4l2_fh_init(&ctx->fh, vfd);
 	file->private_data = &ctx->fh;
 	v4l2_fh_add(&ctx->fh);
+	atomic_set(&ctx->buf_list_cnt, 0);
 
 	ctx->jpeg = jpeg;
 	ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(jpeg->m2m_dev, ctx,
@@ -1568,6 +1577,11 @@ static int mtk_jpegdec_set_hw_param(struct mtk_jpeg_ctx *ctx,
 	return 0;
 }
 
+static void jpeg_buf_queue_inc(struct mtk_jpeg_ctx *ctx)
+{
+	atomic_inc(&ctx->buf_list_cnt);
+}
+
 static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg_dev *jpeg)
 {
 	struct mtk_jpeg_ctx *ctx;
@@ -1693,6 +1707,7 @@ static void mtk_jpegenc_worker(struct work_struct *work)
 			     &src_buf->vb2_buf);
 	mtk_jpeg_set_enc_params(ctx, comp_jpeg[hw_id]->reg_base);
 	mtk_jpeg_enc_start(comp_jpeg[hw_id]->reg_base);
+	jpeg_buf_queue_inc(ctx);
 	v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
 	spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags);
 
@@ -1825,6 +1840,7 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 				&bs,
 				&fb);
 	mtk_jpeg_dec_start(comp_jpeg[hw_id]->reg_base);
+	jpeg_buf_queue_inc(ctx);
 	v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
 	spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags);
 
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
index 186cd1862028..6e8304680393 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
@@ -303,6 +303,7 @@ struct mtk_jpeg_q_data {
  * @dst_done_queue:		encoded frame buffer queue
  * @done_queue_lock:		encoded frame operation spinlock
  * @last_done_frame_num:	the last encoded frame number
+ * @buf_list_cnt:		the frame buffer count own by jpeg driver
  */
 struct mtk_jpeg_ctx {
 	struct mtk_jpeg_dev		*jpeg;
@@ -321,6 +322,7 @@ struct mtk_jpeg_ctx {
 	/* spinlock protecting the encode done buffer */
 	spinlock_t done_queue_lock;
 	u32 last_done_frame_num;
+	atomic_t buf_list_cnt;
 };
 
 #endif /* _MTK_JPEG_CORE_H */
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index e913f0f899b8..c1e10af2086b 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -522,6 +522,11 @@ static void mtk_jpegdec_put_buf(struct mtk_jpegdec_comp_dev *jpeg)
 	spin_unlock_irqrestore(&ctx->done_queue_lock, flags);
 }
 
+static void jpeg_buf_queue_dec(struct mtk_jpeg_ctx *ctx)
+{
+	atomic_dec(&ctx->buf_list_cnt);
+}
+
 static void mtk_jpegdec_timeout_work(struct work_struct *work)
 {
 	enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
@@ -530,9 +535,11 @@ static void mtk_jpegdec_timeout_work(struct work_struct *work)
 			     job_timeout_work.work);
 	struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev;
 	struct vb2_v4l2_buffer *src_buf, *dst_buf;
+	struct mtk_jpeg_ctx *ctx;
 
 	src_buf = cjpeg->hw_param.src_buffer;
 	dst_buf = cjpeg->hw_param.dst_buffer;
+	ctx = cjpeg->hw_param.curr_ctx;
 	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
 
 	mtk_jpeg_dec_reset(cjpeg->reg_base);
@@ -543,6 +550,7 @@ static void mtk_jpegdec_timeout_work(struct work_struct *work)
 	wake_up(&master_jpeg->hw_wq);
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegdec_put_buf(cjpeg);
+	jpeg_buf_queue_dec(ctx);
 }
 
 static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
@@ -583,6 +591,7 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
 	buf_state = VB2_BUF_STATE_DONE;
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegdec_put_buf(jpeg);
+	jpeg_buf_queue_dec(ctx);
 	pm_runtime_put(ctx->jpeg->dev);
 	clk_disable_unprepare(jpeg->jdec_clk.clks->clk);
 
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
index b92f677359c9..2d7e72a424c5 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
@@ -251,6 +251,11 @@ static void mtk_jpegenc_put_buf(struct mtk_jpegenc_comp_dev *jpeg)
 	spin_unlock_irqrestore(&ctx->done_queue_lock, flags);
 }
 
+static void jpeg_buf_queue_dec(struct mtk_jpeg_ctx *ctx)
+{
+	atomic_dec(&ctx->buf_list_cnt);
+}
+
 static void mtk_jpegenc_timeout_work(struct work_struct *work)
 {
 	struct delayed_work *dly_work = to_delayed_work(work);
@@ -261,9 +266,11 @@ static void mtk_jpegenc_timeout_work(struct work_struct *work)
 	struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev;
 	enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
 	struct vb2_v4l2_buffer *src_buf, *dst_buf;
+	struct mtk_jpeg_ctx *ctx;
 
 	src_buf = cjpeg->hw_param.src_buffer;
 	dst_buf = cjpeg->hw_param.dst_buffer;
+	ctx = cjpeg->hw_param.curr_ctx;
 	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
 
 	mtk_jpeg_enc_reset(cjpeg->reg_base);
@@ -274,6 +281,7 @@ static void mtk_jpegenc_timeout_work(struct work_struct *work)
 	wake_up(&master_jpeg->hw_wq);
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegenc_put_buf(cjpeg);
+	jpeg_buf_queue_dec(ctx);
 }
 
 static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
@@ -307,6 +315,7 @@ static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
 	buf_state = VB2_BUF_STATE_DONE;
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegenc_put_buf(jpeg);
+	jpeg_buf_queue_dec(ctx);
 	pm_runtime_put(ctx->jpeg->dev);
 	clk_disable_unprepare(jpeg->venc_clk.clks->clk);
 
-- 
2.46.0



From kyrie.wu at mediatek.com  Tue May 20 19:23:15 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Wed, 21 May 2025 10:23:15 +0800
Subject: [PATCH v4 05/12] media: mediatek: jpeg: fix jpeg hw count setting
In-Reply-To: <20250521022322.27576-1-kyrie.wu@mediatek.com>
References: <20250521022322.27576-1-kyrie.wu@mediatek.com>
Message-ID: <20250521022322.27576-6-kyrie.wu@mediatek.com>

1. different IC has different hw core;
2. use a parameter to set jpeg hw count.

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c   | 8 ++++----
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h   | 2 ++
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 1 +
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 1 +
 4 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index ea890f01fa9e..0074d1edb534 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1469,7 +1469,7 @@ static int mtk_jpegenc_get_hw(struct mtk_jpeg_ctx *ctx)
 	int i;
 
 	spin_lock_irqsave(&jpeg->hw_lock, flags);
-	for (i = 0; i < MTK_JPEGENC_HW_MAX; i++) {
+	for (i = 0; i < jpeg->max_hw_count; i++) {
 		comp_jpeg = jpeg->enc_hw_dev[i];
 		if (comp_jpeg->hw_state == MTK_JPEG_HW_IDLE) {
 			hw_id = i;
@@ -1516,7 +1516,7 @@ static int mtk_jpegdec_get_hw(struct mtk_jpeg_ctx *ctx)
 	int i;
 
 	spin_lock_irqsave(&jpeg->hw_lock, flags);
-	for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++) {
+	for (i = 0; i < jpeg->max_hw_count; i++) {
 		comp_jpeg = jpeg->dec_hw_dev[i];
 		if (comp_jpeg->hw_state == MTK_JPEG_HW_IDLE) {
 			hw_id = i;
@@ -1613,7 +1613,7 @@ static void mtk_jpegenc_worker(struct work_struct *work)
 		jpeg_work);
 	struct mtk_jpeg_dev *jpeg = ctx->jpeg;
 
-	for (i = 0; i < MTK_JPEGENC_HW_MAX; i++)
+	for (i = 0; i < jpeg->max_hw_count; i++)
 		comp_jpeg[i] = jpeg->enc_hw_dev[i];
 	i = 0;
 
@@ -1725,7 +1725,7 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 	struct mtk_jpeg_fb fb;
 	unsigned long flags;
 
-	for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++)
+	for (i = 0; i < jpeg->max_hw_count; i++)
 		comp_jpeg[i] = jpeg->dec_hw_dev[i];
 	i = 0;
 
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
index 46899512a5e6..655dc9c3280c 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
@@ -227,6 +227,7 @@ struct mtk_jpegdec_comp_dev {
  * @reg_decbase:	jpg decode register base addr
  * @dec_hw_dev:	jpg decode hardware device
  * @hw_index:		jpg hw index
+ * @max_hw_count:	jpeg hw-core count
  */
 struct mtk_jpeg_dev {
 	struct mutex		lock;
@@ -249,6 +250,7 @@ struct mtk_jpeg_dev {
 	void __iomem *reg_decbase[MTK_JPEGDEC_HW_MAX];
 	struct mtk_jpegdec_comp_dev *dec_hw_dev[MTK_JPEGDEC_HW_MAX];
 	atomic_t hw_index;
+	u32 max_hw_count;
 };
 
 /**
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index 059377805706..e913f0f899b8 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -686,6 +686,7 @@ static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
 	master_dev->dec_hw_dev[i] = dev;
 	master_dev->reg_decbase[i] = dev->reg_base;
 	dev->master_dev = master_dev;
+	master_dev->max_hw_count++;
 
 	ret = mtk_jpegdec_smmu_init(dev);
 	if (ret)
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
index 73c55e1546aa..b92f677359c9 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
@@ -408,6 +408,7 @@ static int mtk_jpegenc_hw_probe(struct platform_device *pdev)
 	master_dev->enc_hw_dev[i] = dev;
 	master_dev->reg_encbase[i] = dev->reg_base;
 	dev->master_dev = master_dev;
+	master_dev->max_hw_count++;
 
 	ret = mtk_jpegenc_smmu_init(dev);
 	if (ret)
-- 
2.46.0



From kyrie.wu at mediatek.com  Tue May 20 19:23:22 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Wed, 21 May 2025 10:23:22 +0800
Subject: [PATCH v4 12/12] media: mediatek: jpeg: fix remove buffer operation for multi-core
In-Reply-To: <20250521022322.27576-1-kyrie.wu@mediatek.com>
References: <20250521022322.27576-1-kyrie.wu@mediatek.com>
Message-ID: <20250521022322.27576-13-kyrie.wu@mediatek.com>

move remove buffer code to spinlock protect area for multi-core

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index eba9f58b9198..34fa03bcfdd3 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1684,9 +1684,6 @@ static void mtk_jpegenc_worker(struct work_struct *work)
 		goto enc_end;
 	}
 
-	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
-	v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
-
 	schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work,
 			      msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC));
 
@@ -1707,6 +1704,8 @@ static void mtk_jpegenc_worker(struct work_struct *work)
 			     &src_buf->vb2_buf);
 	mtk_jpeg_set_enc_params(ctx, comp_jpeg[hw_id]->reg_base);
 	mtk_jpeg_enc_start(comp_jpeg[hw_id]->reg_base);
+	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+	v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
 	jpeg_buf_queue_inc(ctx);
 	v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
 	spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags);
@@ -1803,9 +1802,6 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 		goto dec_end;
 	}
 
-	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
-	v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
-
 	mtk_jpeg_set_dec_src(ctx, &src_buf->vb2_buf, &bs);
 	if (mtk_jpeg_set_dec_dst(ctx,
 				 &jpeg_src_buf->dec_param,
@@ -1833,6 +1829,8 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 				jpeg_src_buf->bs_size,
 				&bs,
 				&fb);
+	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+	v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
 	mtk_jpeg_dec_start(comp_jpeg[hw_id]->reg_base);
 	jpeg_buf_queue_inc(ctx);
 	v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
-- 
2.46.0



From patchwork-bot+netdevbpf at kernel.org  Tue May 20 20:10:48 2025
From: patchwork-bot+netdevbpf at kernel.org (patchwork-bot+netdevbpf at kernel.org)
Date: Wed, 21 May 2025 03:10:48 +0000
Subject: [PATCH net-next v2 0/3] net: airoha: Add per-flow stats support to
 hw flowtable offloading
In-Reply-To: <20250516-airoha-en7581-flowstats-v2-0-06d5fbf28984@kernel.org>
References: <20250516-airoha-en7581-flowstats-v2-0-06d5fbf28984@kernel.org>
Message-ID: <174779704873.1552321.963690772773932988.git-patchwork-notify@kernel.org>

Hello:

This series was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba at kernel.org>:

On Fri, 16 May 2025 09:59:58 +0200 you wrote:
> Introduce per-flow stats accounting to the flowtable hw offload in the
> airoha_eth driver. Flow stats are split in the PPE and NPU modules:
> - PPE: accounts for high 32bit of per-flow stats
> - NPU: accounts for low 32bit of per-flow stats
> 
> ---
> Changes in v2:
> - fix memory leaks in airoha_npu_stats_setup() and in
>   airoha_npu_foe_commit_entry()
> - disable hw keepalive
> - fix sparse warnings
> - Link to v1: https://lore.kernel.org/r/20250514-airoha-en7581-flowstats-v1-0-c00ede12a2ca at kernel.org
> 
> [...]

Here is the summary with links:
  - [net-next,v2,1/3] net: airoha: npu: Move memory allocation in airoha_npu_send_msg() caller
    https://git.kernel.org/netdev/net-next/c/c52918744ee1
  - [net-next,v2,2/3] net: airoha: Add FLOW_CLS_STATS callback support
    https://git.kernel.org/netdev/net-next/c/b81e0f2b58be
  - [net-next,v2,3/3] net: airoha: ppe: Disable packet keepalive
    https://git.kernel.org/netdev/net-next/c/a98326c151ea

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html




From friday.yang at mediatek.com  Tue May 20 23:33:34 2025
From: friday.yang at mediatek.com (Friday Yang)
Date: Wed, 21 May 2025 14:33:34 +0800
Subject: [PATCH v8 0/2] Add SMI reset and clamp for MediaTek MT8188 SoC
Message-ID: <20250521063347.31578-1-friday.yang@mediatek.com>

Based on tag: next-20250521, linux-next/master

On the MediaTek MT8188 SoC platform, we encountered power-off failures
and SMI bus hang issues during camera stress tests. The issue arises
because bus glitches are sometimes produced when MTCMOS powers on or
off. While this is fairly normal, the software must handle these
glitches to avoid mistaking them for transaction signals. What's
more, this issue emerged only after the initial upstreaming of SMI
driver.

The software solutions can be summarized as follows:

1. Use CLAMP to disable the SMI sub-common port after turning off the
   LARB CG and before turning off the LARB MTCMOS.
2. Use CLAMP to disable/enable the SMI sub-common port.
3. Implement an AXI reset for SMI LARBs.

Changes v8:
- We replaced 'pm_runtime_enable' with 'devm_pm_runtime_enable' in the
  v6 patch. This changed the order of cleanup, and reviewers expressed
  concerns that it could introduce unexpected issues. So I discard this
  change and continue using 'pm_runtime_enable'. We need to conduct
  further investigation to determine if there are any issues related
  to the cleanup order. This might be resolved in the future, but for
  now, we just maintain the current status.

v7:
https://lore.kernel.org/lkml/20250430094545.23932-2-friday.yang at mediatek.com/
https://lore.kernel.org/lkml/20250430094545.23932-3-friday.yang at mediatek.com/

friday.yang (2):
  dt-bindings: memory: mediatek: Add SMI reset and clamp for MT8188
  memory: mtk-smi: mt8188: Add SMI reset and clamp for MT8188

 .../mediatek,smi-common.yaml                  |   2 +
 .../memory-controllers/mediatek,smi-larb.yaml |  19 +++
 drivers/memory/mtk-smi.c                      | 133 ++++++++++++++++++
 3 files changed, 154 insertions(+)

--
2.46.0



From friday.yang at mediatek.com  Tue May 20 23:33:35 2025
From: friday.yang at mediatek.com (Friday Yang)
Date: Wed, 21 May 2025 14:33:35 +0800
Subject: [PATCH v8 1/2] dt-bindings: memory: mediatek: Add SMI reset and clamp for MT8188
In-Reply-To: <20250521063347.31578-1-friday.yang@mediatek.com>
References: <20250521063347.31578-1-friday.yang@mediatek.com>
Message-ID: <20250521063347.31578-2-friday.yang@mediatek.com>

From: "Friday Yang" <friday.yang at mediatek.com>

Add 'resets' and 'reset-names' properties for SMI LARBs to support
SMI reset operations.
On the MediaTek platform, some SMI LARBs are directly connected to
the SMI Common, while others are connected to the SMI Sub-Common,
which in turn is connected to the SMI Common. The hardware block
diagram can be described as follows.

             SMI-Common(Smart Multimedia Interface Common)
                 |
         +----------------+------------------+
         |                |                  |
         |                |                  |
         |                |                  |
         |                |                  |
         |                |                  |
       larb0       SMI-Sub-Common0     SMI-Sub-Common1
                   |      |     |      |             |
                  larb1  larb2 larb3  larb7       larb9

Signed-off-by: Friday Yang <friday.yang at mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Acked-by: Rob Herring <robh at kernel.org>

---
 .../mediatek,smi-common.yaml                  |  2 ++
 .../memory-controllers/mediatek,smi-larb.yaml | 19 +++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
index 0762e0ff66ef..3d98c08b2149 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
@@ -40,6 +40,7 @@ properties:
           - mediatek,mt8186-smi-common
           - mediatek,mt8188-smi-common-vdo
           - mediatek,mt8188-smi-common-vpp
+          - mediatek,mt8188-smi-sub-common
           - mediatek,mt8192-smi-common
           - mediatek,mt8195-smi-common-vdo
           - mediatek,mt8195-smi-common-vpp
@@ -108,6 +109,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - mediatek,mt8188-smi-sub-common
               - mediatek,mt8195-smi-sub-common
     then:
       required:
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
index 2e7fac4b5094..fc5feb2eac1f 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
@@ -70,6 +70,12 @@ properties:
     description: the hardware id of this larb. It's only required when this
       hardware id is not consecutive from its M4U point of view.

+  resets:
+    maxItems: 1
+
+  reset-names:
+    const: larb
+
 required:
   - compatible
   - reg
@@ -126,6 +132,19 @@ allOf:
       required:
         - mediatek,larb-id

+  - if:  # only for image, camera and ipe subsys
+      properties:
+        compatible:
+          const: mediatek,mt8188-smi-larb
+        mediatek,larb-id:
+          enum:
+            [ 9, 10, 11, 12, 13, 16, 17, 18, 19, 20 ]
+
+    then:
+      required:
+        - resets
+        - reset-names
+
 additionalProperties: false

 examples:
--
2.46.0



From friday.yang at mediatek.com  Tue May 20 23:33:36 2025
From: friday.yang at mediatek.com (Friday Yang)
Date: Wed, 21 May 2025 14:33:36 +0800
Subject: [PATCH v8 2/2] memory: mtk-smi: mt8188: Add SMI reset and clamp for MT8188
In-Reply-To: <20250521063347.31578-1-friday.yang@mediatek.com>
References: <20250521063347.31578-1-friday.yang@mediatek.com>
Message-ID: <20250521063347.31578-3-friday.yang@mediatek.com>

From: "Friday Yang" <friday.yang at mediatek.com>

To prevent handling glitch signals during MTCMOS on/off transitions,
SMI requires clamp and reset operations. Parse the reset settings for
SMI LARBs and the clamp settings for the SMI Sub-Common. Register
genpd callback for the SMI LARBs located in image, camera and IPE
subsystems, and apply reset and clamp operations within the callback.

Signed-off-by: Friday Yang <friday.yang at mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Acked-by: Rob Herring <robh at kernel.org>

---
 drivers/memory/mtk-smi.c | 133 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 133 insertions(+)

diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index c086c22511f7..f3745f549629 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -10,11 +10,15 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
+#include <linux/pm_domain.h>
 #include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
 #include <linux/soc/mediatek/mtk_sip_svc.h>
 #include <soc/mediatek/smi.h>
 #include <dt-bindings/memory/mt2701-larb-port.h>
@@ -36,6 +40,12 @@
 #define SMI_DCM				0x300
 #define SMI_DUMMY			0x444

+#define SMI_COMMON_CLAMP_EN		0x3c0
+#define SMI_COMMON_CLAMP_EN_SET		0x3c4
+#define SMI_COMMON_CLAMP_EN_CLR		0x3c8
+
+#define SMI_SUB_COMM_INPORT_NR		(8)
+
 /* SMI LARB */
 #define SMI_LARB_SLP_CON                0xc
 #define SLP_PROT_EN                     BIT(0)
@@ -134,6 +144,7 @@ struct mtk_smi_larb_gen {
 	unsigned int			larb_direct_to_common_mask;
 	unsigned int			flags_general;
 	const u8			(*ostd)[SMI_LARB_PORT_NR_MAX];
+	const u8			*clamp_port;
 };

 struct mtk_smi {
@@ -150,6 +161,7 @@ struct mtk_smi {
 };

 struct mtk_smi_larb { /* larb: local arbiter */
+	struct device			*dev;
 	struct mtk_smi			smi;
 	void __iomem			*base;
 	struct device			*smi_common_dev; /* common or sub-common dev */
@@ -157,6 +169,10 @@ struct mtk_smi_larb { /* larb: local arbiter */
 	int				larbid;
 	u32				*mmu;
 	unsigned char			*bank;
+	struct regmap			*sub_comm_syscon;
+	u8				sub_comm_inport;
+	struct notifier_block		nb;
+	struct reset_control		*rst_con;
 };

 static int
@@ -446,6 +462,19 @@ static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = {
 	[28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
 };

+static const u8 mtk_smi_larb_clamp_port_mt8188[MTK_LARB_NR_MAX] = {
+	[9]	= BIT(1), /* larb10 */
+	[10]	= BIT(2), /* larb11a */
+	[11]	= BIT(2), /* larb11b */
+	[12]	= BIT(3), /* larb11c */
+	[13]	= BIT(0), /* larb12 */
+	[16]	= BIT(1), /* larb15 */
+	[17]	= BIT(2), /* larb16a */
+	[18]	= BIT(2), /* larb16b */
+	[19]	= BIT(3), /* larb17a */
+	[20]	= BIT(3), /* larb17b */
+};
+
 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
 	.port_in_larb = {
 		LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
@@ -498,6 +527,7 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = {
 	.flags_general	            = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
 				      MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL,
 	.ostd		            = mtk_smi_larb_mt8188_ostd,
+	.clamp_port                 = mtk_smi_larb_clamp_port_mt8188,
 };

 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
@@ -549,6 +579,46 @@ static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb)
 	writel_relaxed(0, larb->base + SMI_LARB_SLP_CON);
 }

+static int mtk_smi_larb_clamp_protect_enable(struct device *dev, bool enable)
+{
+	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
+	u32 reg;
+	int ret;
+
+	/* sub_comm_syscon could be NULL if larb directly linked to SMI common */
+	if (!larb->sub_comm_syscon)
+		return -EINVAL;
+
+	reg = enable ? SMI_COMMON_CLAMP_EN_SET : SMI_COMMON_CLAMP_EN_CLR;
+
+	ret = regmap_write(larb->sub_comm_syscon, reg,
+			   larb->sub_comm_inport);
+	if (ret)
+		dev_err(dev, "Unable to %s clamp for input port %d: %d\n",
+			enable ? "enable" : "disable",
+			larb->sub_comm_inport, ret);
+
+	return ret;
+}
+
+static int mtk_smi_genpd_callback(struct notifier_block *nb,
+				  unsigned long flags, void *data)
+{
+	struct mtk_smi_larb *larb = container_of(nb, struct mtk_smi_larb, nb);
+	struct device *dev = larb->dev;
+
+	if (flags == GENPD_NOTIFY_PRE_ON || flags == GENPD_NOTIFY_PRE_OFF) {
+		/* disable related SMI sub-common port */
+		mtk_smi_larb_clamp_protect_enable(dev, true);
+	} else if (flags == GENPD_NOTIFY_ON) {
+		/* enable related SMI sub-common port */
+		reset_control_reset(larb->rst_con);
+		mtk_smi_larb_clamp_protect_enable(dev, false);
+	}
+
+	return NOTIFY_OK;
+}
+
 static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev)
 {
 	struct platform_device *smi_com_pdev;
@@ -605,6 +675,53 @@ static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi,
 	return ret;
 }

+static int mtk_smi_larb_parse_clamp_optional(struct mtk_smi_larb *larb)
+{
+	struct device *dev = larb->dev;
+	const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
+	u32 larb_id;
+	int ret;
+
+	/*
+	 * Only SMI LARBs in camera, image and IPE subsys need to
+	 * apply clamp and reset operations, others can be skipped.
+	 */
+	ret = of_property_read_u32(dev->of_node, "mediatek,larb-id", &larb_id);
+	if (ret)
+		return -EINVAL;
+	if (!larb_gen->clamp_port || !larb_gen->clamp_port[larb_id])
+		return 0;
+
+	larb->sub_comm_inport = larb_gen->clamp_port[larb_id];
+	larb->sub_comm_syscon = syscon_regmap_lookup_by_phandle(dev->of_node,
+								"mediatek,smi");
+	if (IS_ERR(larb->sub_comm_syscon)) {
+		larb->sub_comm_syscon = NULL;
+		return dev_err_probe(dev, -EINVAL,
+				     "Unknown clamp port for larb %d\n", larb_id);
+	}
+
+	return 0;
+}
+
+static int mtk_smi_larb_parse_reset_optional(struct mtk_smi_larb *larb)
+{
+	struct device *dev = larb->dev;
+	int ret;
+
+	larb->rst_con = devm_reset_control_get_optional_exclusive(dev, "larb");
+	if (!larb->rst_con)
+		return 0;
+
+	larb->nb.notifier_call = mtk_smi_genpd_callback;
+	ret = dev_pm_genpd_add_notifier(dev, &larb->nb);
+	if (ret)
+		return dev_err_probe(dev, -EINVAL,
+				     "Failed to add genpd callback %d\n", ret);
+
+	return 0;
+}
+
 static int mtk_smi_larb_probe(struct platform_device *pdev)
 {
 	struct mtk_smi_larb *larb;
@@ -615,6 +732,7 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
 	if (!larb)
 		return -ENOMEM;

+	larb->dev = dev;
 	larb->larb_gen = of_device_get_match_data(dev);
 	larb->base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(larb->base))
@@ -631,6 +749,14 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
 	if (ret < 0)
 		return ret;

+	ret = mtk_smi_larb_parse_clamp_optional(larb);
+	if (ret)
+		goto err_link_remove;
+
+	ret = mtk_smi_larb_parse_reset_optional(larb);
+	if (ret)
+		goto err_link_remove;
+
 	pm_runtime_enable(dev);
 	platform_set_drvdata(pdev, larb);
 	ret = component_add(dev, &mtk_smi_larb_component_ops);
@@ -640,6 +766,7 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)

 err_pm_disable:
 	pm_runtime_disable(dev);
+err_link_remove:
 	device_link_remove(dev, larb->smi_common_dev);
 	return ret;
 }
@@ -770,6 +897,11 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vpp = {
 	.init     = mtk_smi_common_mt8195_init,
 };

+static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8188 = {
+	.type     = MTK_SMI_GEN2_SUB_COMM,
+	.has_gals = true,
+};
+
 static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
 	.type     = MTK_SMI_GEN2,
 	.has_gals = true,
@@ -814,6 +946,7 @@ static const struct of_device_id mtk_smi_common_of_ids[] = {
 	{.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186},
 	{.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo},
 	{.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp},
+	{.compatible = "mediatek,mt8188-smi-sub-common", .data = &mtk_smi_sub_common_mt8188},
 	{.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192},
 	{.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo},
 	{.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp},
--
2.46.0



From kuyo.chang at mediatek.com  Tue May 20 23:42:18 2025
From: kuyo.chang at mediatek.com (Kuyo Chang)
Date: Wed, 21 May 2025 14:42:18 +0800
Subject: [PATCH 1/1] [Bug] list_add corruption during CPU hotplug stress test
Message-ID: <20250521064238.3173224-1-kuyo.chang@mediatek.com>

From: kuyo chang <kuyo.chang at mediatek.com>

The commit (stop_machine, sched: Fix migrate_swap() vs. active_balance() deadlock)
introduces wake_q_add rather than wake_up_process.
However, it encounters sporadic failures during CPU hotplug stress test.

The kernel log shows list add fail as below
kmemleak: list_add corruption. prev->next should be next (ffffff82812c7a00), but was 0000000000000000. (prev=ffffff82812c3208).
kmemleak: kernel BUG at lib/list_debug.c:34!
kmemleak: Call trace:
kmemleak:  __list_add_valid_or_report+0x11c/0x144
kmemleak:  cpu_stop_queue_work+0x440/0x474
kmemleak:  stop_one_cpu_nowait_rec+0xe4/0x138
kmemleak:  balance_push+0x1f4/0x3e4
kmemleak:  __schedule+0x1adc/0x23bc
kmemleak:  preempt_schedule_common+0x68/0xd0
kmemleak:  preempt_schedule+0x60/0x80
kmemleak:  _raw_spin_unlock_irqrestore+0x9c/0xa0
kmemleak:  scan_gray_list+0x220/0x3e4
kmemleak:  kmemleak_scan+0x410/0x740
kmemleak:  kmemleak_scan_thread+0xb0/0xdc
kmemleak:  kthread+0x2bc/0x494
kmemleak:  ret_from_fork+0x10/0x20

Because the reproduction rate is very low, I designed a simple debug patch to help find the root cause of these sporadic failures.
The purpose of this debug patch is to record the status of push_work at balance_push, cpu_stopper, and cpu_stop_work.
In the regular case, we queue the push_work to stopper->works and set work->exec_state = WORK_QUEUE.
Then, we call wake_q_add for the stopper and set cpu_stopper.stopper_wakeq = WAKEQ_ADD_OK.
Finally, we wake up the stopper, which picks up the work from cpu_stop_work to execute.
We then set stopper->exec_state = WORK_PREP_EXEC to indicate that the push_work has been consumed.

However, in the failure case, by memory dump
cpu_stopper.stopper_wakeq = WAKEQ_ADD_FAIL
stopper->exec_state = WORK_QUEUE.
cpu_stopper.enabled = TRUE

Here is the failure sequence that leads to the bug.
CPU0
1st balance_push
stop_one_cpu_nowait
cpu_stop_queue_work
__cpu_stop_queue_work
list_add_tail  -> fist add work
wake_q_add   -> returns failure
wake_up_q(&wakeq); -> it doesn't wake up the stopper.
2nd balance_push
stop_one_cpu_nowait
cpu_stop_queue_work
__cpu_stop_queue_work
list_add_tail  -> A double list add is detected, which triggers kernel bugs.

Should we add queue status tracking in __cpu_stop_queue_work,
or is there a better place to do this?

Signed-off-by: kuyo chang <kuyo.chang at mediatek.com>
---
 include/linux/sched/wake_q.h |  1 +
 include/linux/stop_machine.h | 20 ++++++++++++++++++++
 kernel/sched/core.c          | 15 ++++++++++++++-
 kernel/stop_machine.c        | 36 ++++++++++++++++++++++++++++++++++--
 4 files changed, 69 insertions(+), 3 deletions(-)

diff --git a/include/linux/sched/wake_q.h b/include/linux/sched/wake_q.h
index 0f28b4623ad4..083ced4bb5dc 100644
--- a/include/linux/sched/wake_q.h
+++ b/include/linux/sched/wake_q.h
@@ -60,6 +60,7 @@ static inline bool wake_q_empty(struct wake_q_head *head)
 }
 
 extern void wake_q_add(struct wake_q_head *head, struct task_struct *task);
+extern bool wake_q_add_ret(struct wake_q_head *head, struct task_struct *task);
 extern void wake_q_add_safe(struct wake_q_head *head, struct task_struct *task);
 extern void wake_up_q(struct wake_q_head *head);
 
diff --git a/include/linux/stop_machine.h b/include/linux/stop_machine.h
index 3132262a404d..6daec44dcb99 100644
--- a/include/linux/stop_machine.h
+++ b/include/linux/stop_machine.h
@@ -21,18 +21,38 @@ typedef int (*cpu_stop_fn_t)(void *arg);
 
 #ifdef CONFIG_SMP
 
+enum work_state {
+	WORK_INIT = 0,
+	WORK_READY,
+	WORK_QUEUE,
+	WORK_PREP_EXEC,
+};
+
+enum stopper_wakeq_state {
+	WAKEQ_ADD_FAIL = 0,
+	WAKEQ_ADD_OK,
+};
+
+enum work_rec {
+	WORK_NO_REC = 0,
+	WORK_REC,
+};
 struct cpu_stop_work {
 	struct list_head	list;		/* cpu_stopper->works */
 	cpu_stop_fn_t		fn;
 	unsigned long		caller;
 	void			*arg;
 	struct cpu_stop_done	*done;
+	enum work_rec		rec;
+	enum work_state exec_state;
 };
 
 int stop_one_cpu(unsigned int cpu, cpu_stop_fn_t fn, void *arg);
 int stop_two_cpus(unsigned int cpu1, unsigned int cpu2, cpu_stop_fn_t fn, void *arg);
 bool stop_one_cpu_nowait(unsigned int cpu, cpu_stop_fn_t fn, void *arg,
 			 struct cpu_stop_work *work_buf);
+bool stop_one_cpu_nowait_rec(unsigned int cpu, cpu_stop_fn_t fn, void *arg,
+			struct cpu_stop_work *work_buf);
 void stop_machine_park(int cpu);
 void stop_machine_unpark(int cpu);
 void stop_machine_yield(const struct cpumask *cpumask);
diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index c81cf642dba0..a617f51d3e5a 100644
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -1037,6 +1037,19 @@ void wake_q_add(struct wake_q_head *head, struct task_struct *task)
 		get_task_struct(task);
 }
 
+/**
+ * wake_q_add_ret() - queue a wakeup for 'later' waking. record status.
+ */
+bool wake_q_add_ret(struct wake_q_head *head, struct task_struct *task)
+{
+	bool ret = false;
+
+	ret = __wake_q_add(head, task);
+	if (ret)
+		get_task_struct(task);
+	return ret;
+}
+
 /**
  * wake_q_add_safe() - safely queue a wakeup for 'later' waking.
  * @head: the wake_q_head to add @task to
@@ -8100,7 +8113,7 @@ static void balance_push(struct rq *rq)
 	 */
 	preempt_disable();
 	raw_spin_rq_unlock(rq);
-	stop_one_cpu_nowait(rq->cpu, __balance_push_cpu_stop, push_task,
+	stop_one_cpu_nowait_rec(rq->cpu, __balance_push_cpu_stop, push_task,
 			    this_cpu_ptr(&push_work));
 	preempt_enable();
 	/*
diff --git a/kernel/stop_machine.c b/kernel/stop_machine.c
index 5d2d0562115b..3a2c48ed2182 100644
--- a/kernel/stop_machine.c
+++ b/kernel/stop_machine.c
@@ -42,6 +42,8 @@ struct cpu_stopper {
 	struct list_head	works;		/* list of pending works */
 
 	struct cpu_stop_work	stop_work;	/* for stop_cpus */
+	enum stopper_wakeq_state stopper_wakeq;		/* for stopper wakeup */
+	enum work_state exec_state;			/* for stopper exec state */
 	unsigned long		caller;
 	cpu_stop_fn_t		fn;
 };
@@ -85,8 +87,18 @@ static void __cpu_stop_queue_work(struct cpu_stopper *stopper,
 					struct cpu_stop_work *work,
 					struct wake_q_head *wakeq)
 {
+	bool wake_flag;
+
 	list_add_tail(&work->list, &stopper->works);
-	wake_q_add(wakeq, stopper->thread);
+	wake_flag = wake_q_add_ret(wakeq, stopper->thread);
+	if (work->rec == WORK_REC) {
+		work->exec_state = WORK_QUEUE;
+		stopper->exec_state = WORK_QUEUE;
+		if (wake_flag)
+			stopper->stopper_wakeq = WAKEQ_ADD_OK;
+		else
+			stopper->stopper_wakeq = WAKEQ_ADD_FAIL;
+	}
 }
 
 /* queue @work to @stopper.  if offline, @work is completed immediately */
@@ -141,6 +153,8 @@ int stop_one_cpu(unsigned int cpu, cpu_stop_fn_t fn, void *arg)
 	struct cpu_stop_done done;
 	struct cpu_stop_work work = { .fn = fn, .arg = arg, .done = &done, .caller = _RET_IP_ };
 
+	work.rec = WORK_NO_REC;
+	work.exec_state = WORK_INIT;
 	cpu_stop_init_done(&done, 1);
 	if (!cpu_stop_queue_work(cpu, &work))
 		return -ENOENT;
@@ -350,6 +364,8 @@ int stop_two_cpus(unsigned int cpu1, unsigned int cpu2, cpu_stop_fn_t fn, void *
 		.arg = &msdata,
 		.done = &done,
 		.caller = _RET_IP_,
+		.rec = WORK_NO_REC,
+		.exec_state = WORK_INIT,
 	};
 
 	cpu_stop_init_done(&done, 2);
@@ -386,6 +402,17 @@ bool stop_one_cpu_nowait(unsigned int cpu, cpu_stop_fn_t fn, void *arg,
 			struct cpu_stop_work *work_buf)
 {
 	*work_buf = (struct cpu_stop_work){ .fn = fn, .arg = arg, .caller = _RET_IP_, };
+	work_buf->rec = WORK_NO_REC;
+	work_buf->exec_state = WORK_INIT;
+	return cpu_stop_queue_work(cpu, work_buf);
+}
+
+bool stop_one_cpu_nowait_rec(unsigned int cpu, cpu_stop_fn_t fn, void *arg,
+			struct cpu_stop_work *work_buf)
+{
+	*work_buf = (struct cpu_stop_work){ .fn = fn, .arg = arg, .caller = _RET_IP_, };
+	work_buf->rec = WORK_REC;
+	work_buf->exec_state = WORK_READY;
 	return cpu_stop_queue_work(cpu, work_buf);
 }
 
@@ -411,6 +438,8 @@ static bool queue_stop_cpus_work(const struct cpumask *cpumask,
 		work->arg = arg;
 		work->done = done;
 		work->caller = _RET_IP_;
+		work->rec = WORK_NO_REC;
+		work->exec_state = WORK_INIT;
 		if (cpu_stop_queue_work(cpu, work))
 			queued = true;
 	}
@@ -496,6 +525,8 @@ static void cpu_stopper_thread(unsigned int cpu)
 		work = list_first_entry(&stopper->works,
 					struct cpu_stop_work, list);
 		list_del_init(&work->list);
+		if (work->rec == WORK_REC)
+			stopper->exec_state = WORK_PREP_EXEC;
 	}
 	raw_spin_unlock_irq(&stopper->lock);
 
@@ -572,7 +603,8 @@ static int __init cpu_stop_init(void)
 
 	for_each_possible_cpu(cpu) {
 		struct cpu_stopper *stopper = &per_cpu(cpu_stopper, cpu);
-
+		stopper->exec_state = WORK_INIT;
+		stopper->stopper_wakeq = WAKEQ_ADD_OK;
 		raw_spin_lock_init(&stopper->lock);
 		INIT_LIST_HEAD(&stopper->works);
 	}
-- 
2.45.2



From krzk at kernel.org  Wed May 21 00:04:42 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Wed, 21 May 2025 09:04:42 +0200
Subject: [PATCH v4 01/12] media: dt-bindings: mediatek,jpeg: Add
 mediatek, mt8196-jpgdec compatible
In-Reply-To: <20250521022322.27576-2-kyrie.wu@mediatek.com>
References: <20250521022322.27576-1-kyrie.wu@mediatek.com>
 <20250521022322.27576-2-kyrie.wu@mediatek.com>
Message-ID: <20250521-friendly-hissing-tuna-a534d6@kuoka>

On Wed, May 21, 2025 at 10:23:11AM GMT, Kyrie Wu wrote:
> Compared to the previous generation IC, the MT8196 uses SMMU
> instead of IOMMU and supports features such as dynamic voltage
> and frequency scaling. Therefore, add "mediatek,mt8196-jpgdec"
> compatible to the binding document.
> 
> Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Best regards,
Krzysztof



From krzk at kernel.org  Wed May 21 00:04:55 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Wed, 21 May 2025 09:04:55 +0200
Subject: [PATCH v4 02/12] media: dt-bindings: mediatek,jpeg: Add
 mediatek, mt8196-jpgenc compatible
In-Reply-To: <20250521022322.27576-3-kyrie.wu@mediatek.com>
References: <20250521022322.27576-1-kyrie.wu@mediatek.com>
 <20250521022322.27576-3-kyrie.wu@mediatek.com>
Message-ID: <20250521-handsome-primitive-goose-1cbbab@kuoka>

On Wed, May 21, 2025 at 10:23:12AM GMT, Kyrie Wu wrote:
> Compared to the previous generation IC, the MT8196 uses SMMU
> instead of IOMMU and supports features such as dynamic voltage
> and frequency scaling. Therefore, add "mediatek,mt8196-jpgenc"
> compatible to the binding document.
> 
> Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
> ---
>  .../bindings/media/mediatek,mt8195-jpegenc.yaml           | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Best regards,
Krzysztof



From lorenzo at kernel.org  Wed May 21 00:07:49 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 21 May 2025 09:07:49 +0200
Subject: [PATCH net-next v2 1/2] dt-bindings: net: airoha: Add EN7581
 memory-region property
In-Reply-To: <20250514200816.GA2934563-robh@kernel.org>
References: <20250509-airopha-desc-sram-v2-0-9dc3d8076dfb@kernel.org>
 <20250509-airopha-desc-sram-v2-1-9dc3d8076dfb@kernel.org>
 <20250514200816.GA2934563-robh@kernel.org>
Message-ID: <aC17xaFuF7-1Sf0F@lore-desk>

> On Fri, May 09, 2025 at 04:51:33PM +0200, Lorenzo Bianconi wrote:
> > Introduce the memory-region and memory-region-names properties for the
> > ethernet node available on EN7581 SoC. In order to improve performances,
> > EN7581 SoC supports allocating buffers for hw forwarding queues in SRAM
> > instead of DRAM if available on the system.
> 
> But 'reserved-memory' is generally for system memory which is DRAM 
> though we unfortunately don't enforce that. For small onchip SRAM, you 
> should be using the mmio-sram binding and the 'sram' property.

Reviewing the vendor sdk my understanding was wrong (sorry for the noise).
Here we just want to add the capability to allocate hw forwarding buffers queue
defining the memory region in the DTS instead of using dmam_alloc_coherent()
since in some configurations QDMA blocks require a contiguous block of
system memory for hwfd buffers queue.
Moreover, EN7581 SoC supports consuming SRAM instead of DRAM for hw forwarding
descriptors queue. This is managed in hw, we just need to request it in the
flowtable entry configuration.
I will fix it in v2.

Regards,
Lorenzo

> 
> > 
> > Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
> > ---
> >  .../devicetree/bindings/net/airoha,en7581-eth.yaml          | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
> > index 0fdd1126541774acacc783d98e4c089b2d2b85e2..6d22131ac2f9e28390b9e785ce33e8d983eafd0f 100644
> > --- a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
> > +++ b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
> > @@ -57,6 +57,16 @@ properties:
> >        - const: hsi-mac
> >        - const: xfp-mac
> >  
> > +  memory-region:
> > +    items:
> > +      - description: QDMA0 buffer memory
> > +      - description: QDMA1 buffer memory
> > +
> > +  memory-region-names:
> > +    items:
> > +      - const: qdma0-buf
> > +      - const: qdma1-buf
> > +
> >    "#address-cells":
> >      const: 1
> >  
> > @@ -140,6 +150,9 @@ examples:
> >                       <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
> >                       <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> >  
> > +        memory-region = <&qdma0_buf>, <&qdma1_buf>;
> > +        memory-region-names = "qdma0-buf", "qdma1-buf";
> > +
> >          airoha,npu = <&npu>;
> >  
> >          #address-cells = <1>;
> > 
> > -- 
> > 2.49.0
> > 
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From lorenzo at kernel.org  Wed May 21 00:16:35 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 21 May 2025 09:16:35 +0200
Subject: [PATCH net-next v3 0/4] Add the capability to consume SRAM for
 hwfd descriptor queue in airoha_eth driver
Message-ID: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>

In order to improve packet processing and packet forwarding
performances, EN7581 SoC supports consuming SRAM instead of DRAM for hw
forwarding descriptors queue. For downlink hw accelerated traffic
request to consume SRAM memory for hw forwarding descriptors queue.
Moreover, in some configurations QDMA blocks require a contiguous block
of system memory for hwfd buffers queue. Introduce the capability to
allocate hw buffers forwarding queue via the reserved-memory DTS
property instead of running dmam_alloc_coherent().

---
Changes in v3:
- Remove hwfd references in airoha_qdma_struct in patch 2/4
- Split patch 2/2 in 3/4 and 4/4
- For downlink hw accelerated traffic request to consume SRAM memory for
  hw forwarding descriptors queue
- Fix comments
- Link to v2: https://lore.kernel.org/r/20250509-airopha-desc-sram-v2-0-9dc3d8076dfb at kernel.org

Changes in v2:
- fix sparse warnings
- Link to v1: https://lore.kernel.org/r/20250507-airopha-desc-sram-v1-0-d42037431bfa at kernel.org

---
Lorenzo Bianconi (4):
      dt-bindings: net: airoha: Add EN7581 memory-region property
      net: airoha: Do not store hfwd references in airoha_qdma struct
      net: airoha: Add the capability to allocate hwfd buffers via reserved-memory
      net: airoha: Add the capability to allocate hfwd descriptors in SRAM

 .../devicetree/bindings/net/airoha,en7581-eth.yaml | 13 ++++++
 drivers/net/ethernet/airoha/airoha_eth.c           | 50 ++++++++++++++--------
 drivers/net/ethernet/airoha/airoha_eth.h           | 15 ++++---
 drivers/net/ethernet/airoha/airoha_ppe.c           |  6 +++
 4 files changed, 60 insertions(+), 24 deletions(-)
---
base-commit: e6b3527c3b0a676c710e91798c2709cc0538d312
change-id: 20250507-airopha-desc-sram-faeb3ea6cbc5

Best regards,
-- 
Lorenzo Bianconi <lorenzo at kernel.org>



From lorenzo at kernel.org  Wed May 21 00:16:36 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 21 May 2025 09:16:36 +0200
Subject: [PATCH net-next v3 1/4] dt-bindings: net: airoha: Add EN7581
 memory-region property
In-Reply-To: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
References: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
Message-ID: <20250521-airopha-desc-sram-v3-1-a6e9b085b4f0@kernel.org>

Introduce memory-region and memory-region-names properties for the
ethernet node available on EN7581 SoC in order to reserve system memory
for hw forwarding buffers queue used by the QDMA modules.

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 .../devicetree/bindings/net/airoha,en7581-eth.yaml          | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
index 0fdd1126541774acacc783d98e4c089b2d2b85e2..6d22131ac2f9e28390b9e785ce33e8d983eafd0f 100644
--- a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
+++ b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
@@ -57,6 +57,16 @@ properties:
       - const: hsi-mac
       - const: xfp-mac
 
+  memory-region:
+    items:
+      - description: QDMA0 buffer memory
+      - description: QDMA1 buffer memory
+
+  memory-region-names:
+    items:
+      - const: qdma0-buf
+      - const: qdma1-buf
+
   "#address-cells":
     const: 1
 
@@ -140,6 +150,9 @@ examples:
                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
                      <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 
+        memory-region = <&qdma0_buf>, <&qdma1_buf>;
+        memory-region-names = "qdma0-buf", "qdma1-buf";
+
         airoha,npu = <&npu>;
 
         #address-cells = <1>;

-- 
2.49.0



From lorenzo at kernel.org  Wed May 21 00:16:37 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 21 May 2025 09:16:37 +0200
Subject: [PATCH net-next v3 2/4] net: airoha: Do not store hfwd references
 in airoha_qdma struct
In-Reply-To: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
References: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
Message-ID: <20250521-airopha-desc-sram-v3-2-a6e9b085b4f0@kernel.org>

Since hfwd descriptor and buffer queues are allocated via
dmam_alloc_coherent() we do not need to store their references
in airoha_qdma struct. This patch does not introduce any logical changes,
just code clean-up.

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 drivers/net/ethernet/airoha/airoha_eth.c | 8 ++------
 drivers/net/ethernet/airoha/airoha_eth.h | 6 ------
 2 files changed, 2 insertions(+), 12 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 16c7896f931fd9532aa3b8cc78f41afc676aa117..5f7cbbcbb1d469836dfcea95137c960bfd076744 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -1081,17 +1081,13 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
 	int size;
 
 	size = HW_DSCP_NUM * sizeof(struct airoha_qdma_fwd_desc);
-	qdma->hfwd.desc = dmam_alloc_coherent(eth->dev, size, &dma_addr,
-					      GFP_KERNEL);
-	if (!qdma->hfwd.desc)
+	if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL))
 		return -ENOMEM;
 
 	airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr);
 
 	size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM;
-	qdma->hfwd.q = dmam_alloc_coherent(eth->dev, size, &dma_addr,
-					   GFP_KERNEL);
-	if (!qdma->hfwd.q)
+	if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL))
 		return -ENOMEM;
 
 	airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr);
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index 531a3c49c1562a986111a1ce1c215c8751c16e09..3e03ae9a5d0d21c0d8d717f2a282ff06ef3b9fbf 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -513,12 +513,6 @@ struct airoha_qdma {
 
 	struct airoha_queue q_tx[AIROHA_NUM_TX_RING];
 	struct airoha_queue q_rx[AIROHA_NUM_RX_RING];
-
-	/* descriptor and packet buffers for qdma hw forward */
-	struct {
-		void *desc;
-		void *q;
-	} hfwd;
 };
 
 struct airoha_gdm_port {

-- 
2.49.0



From lorenzo at kernel.org  Wed May 21 00:16:38 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 21 May 2025 09:16:38 +0200
Subject: [PATCH net-next v3 3/4] net: airoha: Add the capability to
 allocate hwfd buffers via reserved-memory
In-Reply-To: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
References: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
Message-ID: <20250521-airopha-desc-sram-v3-3-a6e9b085b4f0@kernel.org>

In some configurations QDMA blocks require a contiguous block of
system memory for hwfd buffers queue. Introduce the capability to allocate
hw buffers forwarding queue via the reserved-memory DTS property instead of
running dmam_alloc_coherent().

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 drivers/net/ethernet/airoha/airoha_eth.c | 33 +++++++++++++++++++++++++++++---
 1 file changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 5f7cbbcbb1d469836dfcea95137c960bfd076744..20e590d76735e72a1a538a42d2a1f49b882deccc 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -5,6 +5,7 @@
  */
 #include <linux/of.h>
 #include <linux/of_net.h>
+#include <linux/of_reserved_mem.h>
 #include <linux/platform_device.h>
 #include <linux/tcp.h>
 #include <linux/u64_stats_sync.h>
@@ -1076,9 +1077,11 @@ static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q)
 static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
 {
 	struct airoha_eth *eth = qdma->eth;
+	int id = qdma - &eth->qdma[0];
 	dma_addr_t dma_addr;
+	const char *name;
+	int size, index;
 	u32 status;
-	int size;
 
 	size = HW_DSCP_NUM * sizeof(struct airoha_qdma_fwd_desc);
 	if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL))
@@ -1086,10 +1089,34 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
 
 	airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr);
 
-	size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM;
-	if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL))
+	name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id);
+	if (!name)
 		return -ENOMEM;
 
+	index = of_property_match_string(eth->dev->of_node,
+					 "memory-region-names", name);
+	if (index >= 0) {
+		struct reserved_mem *rmem;
+		struct device_node *np;
+
+		/* Consume reserved memory for hw forwarding buffers queue if
+		 * available in the DTS
+		 */
+		np = of_parse_phandle(eth->dev->of_node, "memory-region",
+				      index);
+		if (!np)
+			return -ENODEV;
+
+		rmem = of_reserved_mem_lookup(np);
+		of_node_put(np);
+		dma_addr = rmem->base;
+	} else {
+		size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM;
+		if (!dmam_alloc_coherent(eth->dev, size, &dma_addr,
+					 GFP_KERNEL))
+			return -ENOMEM;
+	}
+
 	airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr);
 
 	airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG,

-- 
2.49.0



From lorenzo at kernel.org  Wed May 21 00:16:39 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 21 May 2025 09:16:39 +0200
Subject: [PATCH net-next v3 4/4] net: airoha: Add the capability to
 allocate hfwd descriptors in SRAM
In-Reply-To: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
References: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
Message-ID: <20250521-airopha-desc-sram-v3-4-a6e9b085b4f0@kernel.org>

In order to improve packet processing and packet forwarding
performances, EN7581 SoC supports consuming SRAM instead of DRAM for
hw forwarding descriptors queue.
For downlink hw accelerated traffic request to consume SRAM memory
for hw forwarding descriptors queue.

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 drivers/net/ethernet/airoha/airoha_eth.c | 11 +----------
 drivers/net/ethernet/airoha/airoha_eth.h |  9 +++++++++
 drivers/net/ethernet/airoha/airoha_ppe.c |  6 ++++++
 3 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 20e590d76735e72a1a538a42d2a1f49b882deccc..3cd56de716a5269b1530cff6d0ca3414d92ecb69 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -71,15 +71,6 @@ static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank,
 	airoha_qdma_set_irqmask(irq_bank, index, mask, 0);
 }
 
-static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
-{
-	/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
-	 * GDM{2,3,4} can be used as wan port connected to an external
-	 * phy module.
-	 */
-	return port->id == 1;
-}
-
 static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
 {
 	struct airoha_eth *eth = port->qdma->eth;
@@ -1128,7 +1119,7 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
 			LMGR_INIT_START | LMGR_SRAM_MODE_MASK |
 			HW_FWD_DESC_NUM_MASK,
 			FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) |
-			LMGR_INIT_START);
+			LMGR_INIT_START | LMGR_SRAM_MODE_MASK);
 
 	return read_poll_timeout(airoha_qdma_rr, status,
 				 !(status & LMGR_INIT_START), USEC_PER_MSEC,
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index 3e03ae9a5d0d21c0d8d717f2a282ff06ef3b9fbf..b815697302bfdf2a6d115a9bbbbadc05462dbadb 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -597,6 +597,15 @@ u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val);
 #define airoha_qdma_clear(qdma, offset, val)			\
 	airoha_rmw((qdma)->regs, (offset), (val), 0)
 
+static inline bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
+{
+	/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
+	 * GDM{2,3,4} can be used as wan port connected to an external
+	 * phy module.
+	 */
+	return port->id == 1;
+}
+
 bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
 			      struct airoha_gdm_port *port);
 
diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
index 2d273937f19cf304ab4b821241fdc3ea93604f0e..12d32c92717a6b4ba74728ec02bb2e166d4d9407 100644
--- a/drivers/net/ethernet/airoha/airoha_ppe.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe.c
@@ -251,6 +251,12 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
 		else
 			pse_port = 2; /* uplink relies on GDM2 loopback */
 		val |= FIELD_PREP(AIROHA_FOE_IB2_PSE_PORT, pse_port);
+
+		/* For downlink traffic consume SRAM memory for hw forwarding
+		 * descriptors queue.
+		 */
+		if (airhoa_is_lan_gdm_port(port))
+			val |= AIROHA_FOE_IB2_FAST_PATH;
 	}
 
 	if (is_multicast_ether_addr(data->eth.h_dest))

-- 
2.49.0



From friday.yang at mediatek.com  Wed May 21 02:16:16 2025
From: friday.yang at mediatek.com (Friday Yang)
Date: Wed, 21 May 2025 17:16:16 +0800
Subject: [PATCH v1] memory: mtk-smi: Add ostd setting for mt8186
Message-ID: <20250521091626.4283-1-friday.yang@mediatek.com>

Add initial ostd setting for mt8186. All the settings come from DE.
These settings help adjust Multimedia HW's bandwidth limits to achieve
a balanced bandwidth requirement. Without this, the VENC HW works
abnormal while stress testing.

Fixes: 86a010bfc739 ("memory: mtk-smi: mt8186: Add smi support")
Signed-off-by: Friday Yang <friday.yang at mediatek.com>
---
 drivers/memory/mtk-smi.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index c086c22511f7..733e22f695ab 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -320,6 +320,38 @@ static const u8 mtk_smi_larb_mt6893_ostd[][SMI_LARB_PORT_NR_MAX] = {
 	[20] = {0x9, 0x9, 0x5, 0x5, 0x1, 0x1},
 };

+static const u8 mtk_smi_larb_mt8186_ostd[][SMI_LARB_PORT_NR_MAX] = {
+	[0] = {0x2, 0x1, 0x8, 0x1,},
+	[1] = {0x1, 0x3, 0x1, 0x1,},
+	[2] = {0x6, 0x1, 0x4, 0x1,},
+	[3] = {},
+	[4] = {0xf, 0x1, 0x5, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
+	       0x1, 0x1, 0x1,},
+	[5] = {},
+	[6] = {},
+	[7] = {0x1, 0x3, 0x1, 0x1, 0x1, 0x3, 0x2, 0xd, 0x7, 0x5, 0x3,
+	       0x1, 0x5,},
+	[8] = {0x1, 0x2, 0x2,},
+	[9] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0xb, 0x7, 0x4,
+	       0x9, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
+	       0x1, 0x1, 0x1, 0x1, 0x1,},
+	[10] = {},
+	[11] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0xb, 0x7, 0x4,
+		0x9, 0x1, 0x1, 0x1, 0x1, 0x1, 0x8, 0x7, 0x7, 0x1, 0x6, 0x2,
+		0xf, 0x8, 0x1, 0x1, 0x1,},
+	[12] = {},
+	[13] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x6, 0x6, 0x6, 0x1, 0x1, 0x1,},
+	[14] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1,},
+	[15] = {},
+	[16] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x1, 0x14, 0x1, 0x4, 0x4, 0x4,
+		0x2, 0x4, 0x2, 0x8, 0x4, 0x4,},
+	[17] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x1, 0x14, 0x1, 0x4, 0x4, 0x4,
+		0x2, 0x4, 0x2, 0x8, 0x4, 0x4,},
+	[18] = {},
+	[19] = {0x1, 0x1, 0x1, 0x1,},
+	[20] = {0x2, 0x2, 0x2, 0x2, 0x1, 0x1,},
+};
+
 static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = {
 	[0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,},
 	[1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,},
@@ -491,6 +523,7 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = {
 	.config_port                = mtk_smi_larb_config_port_gen2_general,
 	.flags_general	            = MTK_SMI_FLAG_SLEEP_CTL,
+	.ostd			    = mtk_smi_larb_mt8186_ostd,
 };

 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = {
--
2.46.0



From angelogioacchino.delregno at collabora.com  Wed May 21 02:26:21 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 21 May 2025 11:26:21 +0200
Subject: [PATCH v1] memory: mtk-smi: Add ostd setting for mt8186
In-Reply-To: <20250521091626.4283-1-friday.yang@mediatek.com>
References: <20250521091626.4283-1-friday.yang@mediatek.com>
Message-ID: <9c594eaa-9ddc-4340-ac0d-d911073764ac@collabora.com>

Il 21/05/25 11:16, Friday Yang ha scritto:
> Add initial ostd setting for mt8186. All the settings come from DE.
> These settings help adjust Multimedia HW's bandwidth limits to achieve
> a balanced bandwidth requirement. Without this, the VENC HW works
> abnormal while stress testing.
> 
> Fixes: 86a010bfc739 ("memory: mtk-smi: mt8186: Add smi support")
> Signed-off-by: Friday Yang <friday.yang at mediatek.com>

I agree about this commit and you can get my

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

...but I still have a question.

This driver is getting lots of those big OSTD arrays, and I can foresee this
getting bigger and bigger with every new SoC getting supported in there.

I'd like to understand how we can improve that, hence, can you please describe
how the OSTD values are calculated and how are they limiting the bandwidth?

I'm thinking that we can do something such that we get this runtime calculated
instead of just holding fixed values, so that we may eventually replace all those
big arrays with just a few values (foreseeing 3-4 values) and performing a big
cleanup (which may bring further improvements in the future).

Cheers,
Angelo

> ---
>   drivers/memory/mtk-smi.c | 33 +++++++++++++++++++++++++++++++++
>   1 file changed, 33 insertions(+)
> 
> diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
> index c086c22511f7..733e22f695ab 100644
> --- a/drivers/memory/mtk-smi.c
> +++ b/drivers/memory/mtk-smi.c
> @@ -320,6 +320,38 @@ static const u8 mtk_smi_larb_mt6893_ostd[][SMI_LARB_PORT_NR_MAX] = {
>   	[20] = {0x9, 0x9, 0x5, 0x5, 0x1, 0x1},
>   };
> 
> +static const u8 mtk_smi_larb_mt8186_ostd[][SMI_LARB_PORT_NR_MAX] = {
> +	[0] = {0x2, 0x1, 0x8, 0x1,},
> +	[1] = {0x1, 0x3, 0x1, 0x1,},
> +	[2] = {0x6, 0x1, 0x4, 0x1,},
> +	[3] = {},
> +	[4] = {0xf, 0x1, 0x5, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
> +	       0x1, 0x1, 0x1,},
> +	[5] = {},
> +	[6] = {},
> +	[7] = {0x1, 0x3, 0x1, 0x1, 0x1, 0x3, 0x2, 0xd, 0x7, 0x5, 0x3,
> +	       0x1, 0x5,},
> +	[8] = {0x1, 0x2, 0x2,},
> +	[9] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0xb, 0x7, 0x4,
> +	       0x9, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
> +	       0x1, 0x1, 0x1, 0x1, 0x1,},
> +	[10] = {},
> +	[11] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0xb, 0x7, 0x4,
> +		0x9, 0x1, 0x1, 0x1, 0x1, 0x1, 0x8, 0x7, 0x7, 0x1, 0x6, 0x2,
> +		0xf, 0x8, 0x1, 0x1, 0x1,},
> +	[12] = {},
> +	[13] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x6, 0x6, 0x6, 0x1, 0x1, 0x1,},
> +	[14] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1,},
> +	[15] = {},
> +	[16] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x1, 0x14, 0x1, 0x4, 0x4, 0x4,
> +		0x2, 0x4, 0x2, 0x8, 0x4, 0x4,},
> +	[17] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x1, 0x14, 0x1, 0x4, 0x4, 0x4,
> +		0x2, 0x4, 0x2, 0x8, 0x4, 0x4,},
> +	[18] = {},
> +	[19] = {0x1, 0x1, 0x1, 0x1,},
> +	[20] = {0x2, 0x2, 0x2, 0x2, 0x1, 0x1,},
> +};
> +
>   static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = {
>   	[0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,},
>   	[1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,},
> @@ -491,6 +523,7 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
>   static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = {
>   	.config_port                = mtk_smi_larb_config_port_gen2_general,
>   	.flags_general	            = MTK_SMI_FLAG_SLEEP_CTL,
> +	.ostd			    = mtk_smi_larb_mt8186_ostd,
>   };
> 
>   static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = {
> --
> 2.46.0
> 



From angelogioacchino.delregno at collabora.com  Wed May 21 06:53:11 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 21 May 2025 15:53:11 +0200
Subject: [PATCH v2] pinctrl: mediatek: eint: Fix invalid pointer
 dereference for v1 platforms
In-Reply-To: <20250520-genio-350-eint-null-ptr-deref-fix-v2-1-6a3ca966a7ba@collabora.com>
References: <20250520-genio-350-eint-null-ptr-deref-fix-v2-1-6a3ca966a7ba@collabora.com>
Message-ID: <557a5182-4843-4925-953e-09e3b1e41f0c@collabora.com>

Il 20/05/25 23:15, N?colas F. R. A. Prado ha scritto:
> Commit 3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple
> addresses") introduced an access to the 'soc' field of struct
> mtk_pinctrl in mtk_eint_do_init() and for that an include of
> pinctrl-mtk-common-v2.h.
> 
> However, pinctrl drivers relying on the v1 common driver include
> pinctrl-mtk-common.h instead, which provides another definition of
> struct mtk_pinctrl that does not contain an 'soc' field.
> 
> Since mtk_eint_do_init() can be called both by v1 and v2 drivers, it
> will now try to dereference an invalid pointer when called on v1
> platforms. This has been observed on Genio 350 EVK (MT8365), which
> crashes very early in boot (the kernel trace can only be seen with
> earlycon).
> 
> In order to fix this, since 'struct mtk_pinctrl' was only needed to get
> a 'struct mtk_eint_pin', make 'struct mtk_eint_pin' a parameter
> of mtk_eint_do_init() so that callers need to supply it, removing
> mtk_eint_do_init()'s dependency on any particular 'struct mtk_pinctrl'.
> 
> Fixes: 3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple addresses")
> Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
> ---
> Changes in v2:
> - Completely changed approach to make mtk_eint_pin a parameter of
>    mtk_eint_do_init() as suggested by Angelo
> - Link to v1: https://lore.kernel.org/r/20250519-genio-350-eint-null-ptr-deref-fix-v1-1-07445d6d22c3 at collabora.com
> ---
>   drivers/pinctrl/mediatek/mtk-eint.c              | 26 ++++++++++--------------
>   drivers/pinctrl/mediatek/mtk-eint.h              |  5 +++--
>   drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c |  2 +-
>   drivers/pinctrl/mediatek/pinctrl-mtk-common.c    |  2 +-
>   4 files changed, 16 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c
> index 16af6a47028e67bb53db4041a37ebbbb8b9a1e43..d906a5e4101fb10968035fc48e9cf4a444d063a9 100644
> --- a/drivers/pinctrl/mediatek/mtk-eint.c
> +++ b/drivers/pinctrl/mediatek/mtk-eint.c
> @@ -22,7 +22,6 @@
>   #include <linux/platform_device.h>
>   
>   #include "mtk-eint.h"
> -#include "pinctrl-mtk-common-v2.h"
>   
>   #define MTK_EINT_EDGE_SENSITIVE           0
>   #define MTK_EINT_LEVEL_SENSITIVE          1
> @@ -505,10 +504,9 @@ int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
>   }
>   EXPORT_SYMBOL_GPL(mtk_eint_find_irq);
>   
> -int mtk_eint_do_init(struct mtk_eint *eint)
> +int mtk_eint_do_init(struct mtk_eint *eint, struct mtk_eint_pin *eint_pin)
>   {
>   	unsigned int size, i, port, virq, inst = 0;
> -	struct mtk_pinctrl *hw = (struct mtk_pinctrl *)eint->pctl;
>   
>   	/* If clients don't assign a specific regs, let's use generic one */
>   	if (!eint->regs)
> @@ -519,7 +517,15 @@ int mtk_eint_do_init(struct mtk_eint *eint)
>   	if (!eint->base_pin_num)
>   		return -ENOMEM;
>   
> -	if (eint->nbase == 1) {

Okay, dropping the nbase == 1 is sane, but that statement was actually documenting
the fact that *eint_pin is used only for multi-base EINT case, so please add those
comments:

> +	if (eint_pin) {

		/* EINT with multiple bases */

> +		eint->pins = eint_pin;
> +		for (i = 0; i < eint->hw->ap_num; i++) {
> +			inst = eint->pins[i].instance;
> +			if (inst >= eint->nbase)
> +				continue;
> +			eint->base_pin_num[inst]++;
> +		}
> +	} else {

		/* Single base EINT */

...after which:

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

Thanks for fixing this!



From angelogioacchino.delregno at collabora.com  Wed May 21 06:58:21 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 21 May 2025 15:58:21 +0200
Subject: [PATCH v2] pinctrl: mediatek: eint: Fix invalid pointer
 dereference for v1 platforms
In-Reply-To: <557a5182-4843-4925-953e-09e3b1e41f0c@collabora.com>
References: <20250520-genio-350-eint-null-ptr-deref-fix-v2-1-6a3ca966a7ba@collabora.com>
 <557a5182-4843-4925-953e-09e3b1e41f0c@collabora.com>
Message-ID: <5e237878-bc8c-4c88-ad9d-469ce4389274@collabora.com>

Il 21/05/25 15:53, AngeloGioacchino Del Regno ha scritto:
> Il 20/05/25 23:15, N?colas F. R. A. Prado ha scritto:
>> Commit 3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple
>> addresses") introduced an access to the 'soc' field of struct
>> mtk_pinctrl in mtk_eint_do_init() and for that an include of
>> pinctrl-mtk-common-v2.h.
>>
>> However, pinctrl drivers relying on the v1 common driver include
>> pinctrl-mtk-common.h instead, which provides another definition of
>> struct mtk_pinctrl that does not contain an 'soc' field.
>>
>> Since mtk_eint_do_init() can be called both by v1 and v2 drivers, it
>> will now try to dereference an invalid pointer when called on v1
>> platforms. This has been observed on Genio 350 EVK (MT8365), which
>> crashes very early in boot (the kernel trace can only be seen with
>> earlycon).
>>
>> In order to fix this, since 'struct mtk_pinctrl' was only needed to get
>> a 'struct mtk_eint_pin', make 'struct mtk_eint_pin' a parameter
>> of mtk_eint_do_init() so that callers need to supply it, removing
>> mtk_eint_do_init()'s dependency on any particular 'struct mtk_pinctrl'.
>>
>> Fixes: 3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple addresses")
>> Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
>> Signed-off-by: N?colas F. R. A. Prado <nfraprado at collabora.com>
>> ---
>> Changes in v2:
>> - Completely changed approach to make mtk_eint_pin a parameter of
>> ?? mtk_eint_do_init() as suggested by Angelo
>> - Link to v1: https://lore.kernel.org/r/20250519-genio-350-eint-null-ptr-deref- 
>> fix-v1-1-07445d6d22c3 at collabora.com
>> ---
>> ? drivers/pinctrl/mediatek/mtk-eint.c????????????? | 26 ++++++++++--------------
>> ? drivers/pinctrl/mediatek/mtk-eint.h????????????? |? 5 +++--
>> ? drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c |? 2 +-
>> ? drivers/pinctrl/mediatek/pinctrl-mtk-common.c??? |? 2 +-
>> ? 4 files changed, 16 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk- 
>> eint.c
>> index 
>> 16af6a47028e67bb53db4041a37ebbbb8b9a1e43..d906a5e4101fb10968035fc48e9cf4a444d063a9 100644
>> --- a/drivers/pinctrl/mediatek/mtk-eint.c
>> +++ b/drivers/pinctrl/mediatek/mtk-eint.c
>> @@ -22,7 +22,6 @@
>> ? #include <linux/platform_device.h>
>> ? #include "mtk-eint.h"
>> -#include "pinctrl-mtk-common-v2.h"
>> ? #define MTK_EINT_EDGE_SENSITIVE?????????? 0
>> ? #define MTK_EINT_LEVEL_SENSITIVE????????? 1
>> @@ -505,10 +504,9 @@ int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long 
>> eint_n)
>> ? }
>> ? EXPORT_SYMBOL_GPL(mtk_eint_find_irq);
>> -int mtk_eint_do_init(struct mtk_eint *eint)
>> +int mtk_eint_do_init(struct mtk_eint *eint, struct mtk_eint_pin *eint_pin)
>> ? {
>> ????? unsigned int size, i, port, virq, inst = 0;
>> -??? struct mtk_pinctrl *hw = (struct mtk_pinctrl *)eint->pctl;
>> ????? /* If clients don't assign a specific regs, let's use generic one */
>> ????? if (!eint->regs)
>> @@ -519,7 +517,15 @@ int mtk_eint_do_init(struct mtk_eint *eint)
>> ????? if (!eint->base_pin_num)
>> ????????? return -ENOMEM;
>> -??? if (eint->nbase == 1) {
> 
> Okay, dropping the nbase == 1 is sane, but that statement was actually documenting
> the fact that *eint_pin is used only for multi-base EINT case, so please add those
> comments:
> 
>> +??? if (eint_pin) {
> 
>  ??????? /* EINT with multiple bases */
> 
>> +??????? eint->pins = eint_pin;
>> +??????? for (i = 0; i < eint->hw->ap_num; i++) {
>> +??????????? inst = eint->pins[i].instance;
>> +??????????? if (inst >= eint->nbase)
>> +??????????????? continue;
>> +??????????? eint->base_pin_num[inst]++;
>> +??????? }
>> +??? } else {
> 
>  ??????? /* Single base EINT */
> 
> ...after which:
> 
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> 
> Thanks for fixing this!
> 

Just acknowledged that Linus already picked this one.

It's fine either way, no worries.

Cheers,
Angelo


From luca.ceresoli at bootlin.com  Wed May 21 07:22:16 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Wed, 21 May 2025 16:22:16 +0200
Subject: [PATCH v3 00/22] drm: convert all bridges to
 devm_drm_bridge_alloc()
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <20250521162216.79dd3290@booty>

Hello Maxime, Shawn, Liu, all,

On Fri, 09 May 2025 15:53:26 +0200
Luca Ceresoli <luca.ceresoli at bootlin.com> wrote:

> devm_drm_bridge_alloc() [0] is the new API to allocate and initialize a DRM
> bridge, and the only one supported from now on. It is the first milestone
> towards removal of bridges from a still existing DRM pipeline without
> use-after-free.

I applied on drm-misc-next patches 3-17,20-21 as they match all the
criteria:
 - At least a Acked-by (or R-by maintainers)
 - patch is for drm-misc

Being my very first commits to drm-misc, I tried to be careful, and
double checked all the patches with Louis (thanks!).

Here are the pending questions and plan for the remaining patches.

>       Revert "drm/exynos: mic: convert to devm_drm_bridge_alloc() API"

This reverts the commit applied my mistake:
https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/91c5c7b5bb2dd09b43b025bce6d790d3c79f4518

Neither the  original patch nor the revert has been reviewed/acked.

As the commit was a mistake, I'm applying the revert by the end of this
week (i.e. on Friday) unless there are better instructions.

>       drm: convert many bridge drivers from devm_kzalloc() to devm_drm_bridge_alloc() API

This patch affects multiple drivers. Running get_maintainers.pl
points at Shawn Guo's repository. After reviewing the MAINTAINERS file,
this looks like due to the 'N:' line in:

ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
M:	Shawn Guo <shawnguo at kernel.org>
M:	Sascha Hauer <s.hauer at pengutronix.de>
R:	Pengutronix Kernel Team <kernel at pengutronix.de>
...
T:	git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
N:	imx
...

(https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/drm-misc-next/MAINTAINERS?ref_type=heads#L2511-2528)

Here 'imx' matches the 'drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c'
file that is touched by the patch. That regexp appears overly generic to me.

Shawn, can it be fixed by making it less generic?

If not, can we at least add a band-aid 'X:' entry for
drivers/gpu/drm/bridge/imx?

I think the other matching entry is the one to consider:

DRM DRIVERS FOR FREESCALE IMX BRIDGE
M:	Liu Ying <victor.liu at nxp.com>
L:	dri-devel at lists.freedesktop.org
S:	Maintained
F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
F:	drivers/gpu/drm/bridge/imx/

(https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/drm-misc-next/MAINTAINERS?ref_type=heads#L7940-7948)

However it does not list any trees. I _guess_ drm-misc applies here as
a fallback as well as common sense.

Liu, should this entry have a 'T:' line for drm/misc?

>       drm/bridge: imx8qxp-pixel-combiner: convert to devm_drm_bridge_alloc() API

Not acked/reviewed, some discussion happened. I am resending it in v4,
possibly with updates based on the discussion.

But it has the same issue discussed above, with get_maintiners.pl
pointing at Shawn Guo's tree, so in the future I'm assuming this goes
to drm-misc unless there are news about that.

>       drm/bridge: tc358767: convert to devm_drm_bridge_alloc() API

No feedback, resending in v4.

>       drm/todo: add entry to remove devm_drm_put_bridge()

This involves documentation maintained on another tree. Where should it
be applied? There are two matching entries in MAINTAINERS:

 * DRM DRIVERS -> the drm tree
 * DRM DRIVERS AND MISC GPU PATCHES -> the drm-misc tree

To me it looks like the second is obviously the closest match as we are
dealing with DRM bridges, so I'm applying this as well on Friday unless
there are better instructions.

Best regards,
Luca

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


From vulab at iscas.ac.cn  Wed May 21 07:24:03 2025
From: vulab at iscas.ac.cn (Wentao Liang)
Date: Wed, 21 May 2025 22:24:03 +0800
Subject: [PATCH] remoteproc: mediatek: Add SCP watchdog handler in IRQ processing
Message-ID: <20250521142404.1077-1-vulab@iscas.ac.cn>

In mt8195_scp_c1_irq_handler(), only the IPC interrupt bit
(MT8192_SCP_IPC_INT_BIT) was checked., but does not handle
when this bit is not set. This could lead to unhandled watchdog
events. This could lead to unhandled watchdog events. A proper
implementation can be found in mt8183_scp_irq_handler().

Add a new branch to handle SCP watchdog events when the IPC
interrupt bit is not set.

Fixes: 6a1c9aaf04eb ("remoteproc: mediatek: Add MT8195 SCP core 1 operations")
Cc: stable at vger.kernel.org # v6.7
Signed-off-by: Wentao Liang <vulab at iscas.ac.cn>
---
 drivers/remoteproc/mtk_scp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c
index 0f4a7065d0bd..316e8c98a503 100644
--- a/drivers/remoteproc/mtk_scp.c
+++ b/drivers/remoteproc/mtk_scp.c
@@ -273,6 +273,8 @@ static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp)
 
 	if (scp_to_host & MT8192_SCP_IPC_INT_BIT)
 		scp_ipi_handler(scp);
+	else
+		scp_wdt_handler(scp, scp_to_host);
 
 	writel(scp_to_host, scp->cluster->reg_base + MT8195_SSHUB2APMCU_IPC_CLR);
 }
-- 
2.42.0.windows.2



From tanghuan at vivo.com  Wed May 21 07:32:24 2025
From: tanghuan at vivo.com (Huan Tang)
Date: Wed, 21 May 2025 22:32:24 +0800
Subject: [PATCH v5] ufs: core: Add HID support
In-Reply-To: <b0ec5b8a-b303-4e5b-bca9-4524eba9fa31@acm.org>
References: <b0ec5b8a-b303-4e5b-bca9-4524eba9fa31@acm.org>
Message-ID: <20250521143224.587-1-tanghuan@vivo.com>

>>> +static const char *ufs_hid_state_to_string(enum ufs_hid_state state)
>>> +{
>>> +       switch (state) {
>>> +       case HID_IDLE:
>>> +               return "idle";
>>> +       case ANALYSIS_IN_PROGRESS:
>>> +               return "analysis_in_progress";
>>> +       case DEFRAG_REQUIRED:
>>> +               return "defrag_required";
>>> +       case DEFRAG_IN_PROGRESS:
>>> +               return "defrag_in_progress";
>>> +       case DEFRAG_COMPLETED:
>>> +               return "defrag_completed";
>>> +       case DEFRAG_NOT_REQUIRED:
>>> +               return "defrag_not_required";
>>> +       default:
>>> +               return "unknown";
>>> +       }
>>> +}
>>
>>The enum ufs_hid_state values are contiguous and start from 0, maybe change switch-state to :
>>
>>#define NUM_UFS_HID_STATES 6
>>static const char *ufs_hid_states[NUM_UFS_HID_STATES] = {
>>     "idle",
>>      "analysis_in_progress",
>>      "defrag_required",
>>      "defrag_in_progress",
>>      "defrag_completed",
>>      "defrag_not_required"
>> };

> If this change is made, please use the designated initializer syntax
> ([label] = "text"). This will make it easier to verify that the
> enumeration labels and the strings match.

Hi bart and bean sir,

Thank you for your comments and guidance???

What do you think of the following changes?

ufs.h
 +/* bHIDState attribute values */                                               
 +enum ufs_hid_state {                                                           
 +       HID_IDLE                = 0,                                            
 +       ANALYSIS_IN_PROGRESS    = 1,                                            
 +       DEFRAG_REQUIRED         = 2,                                            
 +       DEFRAG_IN_PROGRESS      = 3,                                            
 +       DEFRAG_COMPLETED        = 4,                                            
 +       DEFRAG_NOT_REQUIRED     = 5,                                            
 +       NUM_UFS_HID_STATES      = 6,                                            
 +}; 

ufs-sysfs.c
 +static const char * const ufs_hid_states[] = {                                 
 +       [HID_IDLE]              = "idle",                                       
 +       [ANALYSIS_IN_PROGRESS]  = "analysis_in_progress",                       
 +       [DEFRAG_REQUIRED]       = "defrag_required",                            
 +       [DEFRAG_IN_PROGRESS]    = "defrag_in_progress",                         
 +       [DEFRAG_COMPLETED]      = "defrag_completed",                           
 +       [DEFRAG_NOT_REQUIRED]   = "defrag_not_required",                        
 +};                                                                             
 +                                                                               
 +static const char *ufs_hid_state_to_string(enum ufs_hid_state state)           
 +{                                                                              
 +       if (state < NUM_UFS_HID_STATES)                                         
 +               return ufs_hid_states[state];                                   
 +                                                                               
 +       return "unknown";                                                       
 +} 

...

+static ssize_t state_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_STATE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%s\n", ufs_hid_state_to_string(value));
+}

Thanks
Huan




From tanghuan at vivo.com  Wed May 21 07:33:17 2025
From: tanghuan at vivo.com (Huan Tang)
Date: Wed, 21 May 2025 22:33:17 +0800
Subject: [PATCH v5] ufs: core: Add HID support
In-Reply-To: <ab468bb26dafca673d7ffca7dff519b7cf024cdc.camel@mediatek.com>
References: <ab468bb26dafca673d7ffca7dff519b7cf024cdc.camel@mediatek.com>
Message-ID: <20250521143317.637-1-tanghuan@vivo.com>

>> +static const char * const hid_trigger_mode[] = {"disable",
>> "enable"};
>> +
>> +static ssize_t analysis_trigger_store(struct device *dev,
>> +               struct device_attribute *attr, const char *buf,
>> size_t count)
>> +{
>> +       struct ufs_hba *hba = dev_get_drvdata(dev);
>> +       int mode;
>> +       int ret;
>> +
>> +       mode = sysfs_match_string(hid_trigger_mode, buf);
>> +       if (mode < 0)
>> +               return -EINVAL;
>> 
> 
> Hi Haun,
> 
> Consider use below coding style for readability.
> 
> if (sysfs_streq(buf, "enable"))
>     mode = ...;
> else if (sysfs_streq(buf, "disable"))
>     mode = ...;
> else
>    return -EINVAL;

Hi peter sir,

Thank you for your comments and guidance???
I think your modification will indeed improve the readability of the code.
What do you think of the following changes?

ufs-sysfs.c
+static ssize_t analysis_trigger_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	int mode;
+	int ret;
+
+	if (sysfs_streq(buf, "enable"))
+		mode = HID_ANALYSIS_ENABLE;
+	else if (sysfs_streq(buf, "disable"))
+		mode = HID_ANALYSIS_AND_DEFRAG_DISABLE;
+	else
+		return -EINVAL;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_WO(analysis_trigger);
+
+static ssize_t defrag_trigger_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	int mode;
+	int ret;
+
+	if (sysfs_streq(buf, "enable"))
+		mode = HID_ANALYSIS_AND_DEFRAG_ENABLE;
+	else if (sysfs_streq(buf, "disable"))
+		mode = HID_ANALYSIS_AND_DEFRAG_DISABLE;
+	else
+		return -EINVAL;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
+
+	return ret < 0 ? ret : count;
+}


Thanks
Huan




From huobean at gmail.com  Wed May 21 07:56:50 2025
From: huobean at gmail.com (Bean Huo)
Date: Wed, 21 May 2025 16:56:50 +0200
Subject: [PATCH v5] ufs: core: Add HID support
In-Reply-To: <20250521143224.587-1-tanghuan@vivo.com>
References: <b0ec5b8a-b303-4e5b-bca9-4524eba9fa31@acm.org>
	 <20250521143224.587-1-tanghuan@vivo.com>
Message-ID: <7e034db7e46a33287f59159401affd58a81abad6.camel@gmail.com>

On Wed, 2025-05-21 at 22:32 +0800, Huan Tang wrote:
> > > > +static const char *ufs_hid_state_to_string(enum ufs_hid_state state)
> > > > +{
> > > > +?????? switch (state) {
> > > > +?????? case HID_IDLE:
> > > > +?????????????? return "idle";
> > > > +?????? case ANALYSIS_IN_PROGRESS:
> > > > +?????????????? return "analysis_in_progress";
> > > > +?????? case DEFRAG_REQUIRED:
> > > > +?????????????? return "defrag_required";
> > > > +?????? case DEFRAG_IN_PROGRESS:
> > > > +?????????????? return "defrag_in_progress";
> > > > +?????? case DEFRAG_COMPLETED:
> > > > +?????????????? return "defrag_completed";
> > > > +?????? case DEFRAG_NOT_REQUIRED:
> > > > +?????????????? return "defrag_not_required";
> > > > +?????? default:
> > > > +?????????????? return "unknown";
> > > > +?????? }
> > > > +}
> > > 
> > > The enum ufs_hid_state values are contiguous and start from 0, maybe change switch-state to :
> > > 
> > > #define NUM_UFS_HID_STATES 6
> > > static const char *ufs_hid_states[NUM_UFS_HID_STATES] = {
> > > ??? "idle",
> > > ???? "analysis_in_progress",
> > > ???? "defrag_required",
> > > ???? "defrag_in_progress",
> > > ???? "defrag_completed",
> > > ???? "defrag_not_required"
> > > };
> 
> > If this change is made, please use the designated initializer syntax
> > ([label] = "text"). This will make it easier to verify that the
> > enumeration labels and the strings match.
> 
> Hi bart and bean sir,
> 
> Thank you for your comments and guidance?
> 
> What do you think of the following changes?
> 
> ufs.h
> ?+/* bHIDState attribute values */?????????????????????????????????????????????? 
> ?+enum ufs_hid_state {?????????????????????????????????????????????????????????? 
> ?+?????? HID_IDLE??????????????? = 0,??????????????????????????????????????????? 
> ?+?????? ANALYSIS_IN_PROGRESS??? = 1,??????????????????????????????????????????? 
> ?+?????? DEFRAG_REQUIRED???????? = 2,??????????????????????????????????????????? 
> ?+?????? DEFRAG_IN_PROGRESS????? = 3,??????????????????????????????????????????? 
> ?+?????? DEFRAG_COMPLETED??????? = 4,??????????????????????????????????????????? 
> ?+?????? DEFRAG_NOT_REQUIRED???? = 5,??????????????????????????????????????????? 
> ?+?????? NUM_UFS_HID_STATES????? = 6,??????????????????????????????????????????? 
> ?+}; 
> 
> ufs-sysfs.c
> ?+static const char * const ufs_hid_states[] = {???????????????????????????????? 
> ?+?????? [HID_IDLE]????????????? = "idle",?????????????????????????????????????? 
> ?+?????? [ANALYSIS_IN_PROGRESS]? = "analysis_in_progress",?????????????????????? 
> ?+?????? [DEFRAG_REQUIRED]?????? = "defrag_required",??????????????????????????? 
> ?+?????? [DEFRAG_IN_PROGRESS]??? = "defrag_in_progress",???????????????????????? 
> ?+?????? [DEFRAG_COMPLETED]????? = "defrag_completed",?????????????????????????? 
> ?+?????? [DEFRAG_NOT_REQUIRED]?? = "defrag_not_required",??????????????????????? 
> ?+};???????????????????????????????????????????????????????????????????????????? 
> ?+?????????????????????????????????????????????????????????????????????????????? 
> ?+static const char *ufs_hid_state_to_string(enum ufs_hid_state state)?????????? 
> ?+{????????????????????????????????????????????????????????????????????????????? 
> ?+?????? if (state < NUM_UFS_HID_STATES)???????????????????????????????????????? 
> ?+?????????????? return ufs_hid_states[state];?????????????????????????????????? 
> ?+?????????????????????????????????????????????????????????????????????????????? 
> ?+?????? return "unknown";?????????????????????????????????????????????????????? 
> ?+} 
> 
> ...
> 
> +static ssize_t state_show(struct device *dev,
> +???????????????struct device_attribute *attr, char *buf)
> +{
> +???????struct ufs_hba *hba = dev_get_drvdata(dev);
> +???????u32 value;
> +???????int ret;
> +
> +???????ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
> +???????????????????????QUERY_ATTR_IDN_HID_STATE, &value);
> +???????if (ret)
> +???????????????return ret;
> +
> +???????return sysfs_emit(buf, "%s\n", ufs_hid_state_to_string(value));
> +}
> 
> Thanks
> Huan
> 
> 
> 


looks good to me, with this change, please add my reviewed-by tag in the next version.

Kind regards,
Bean

From angelogioacchino.delregno at collabora.com  Wed May 21 08:15:48 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Wed, 21 May 2025 17:15:48 +0200
Subject: [PATCH] iommu/mediatek: Fix compatible typo for mediatek,mt6893-iommu-mm
Message-ID: <20250521151548.185910-1-angelogioacchino.delregno@collabora.com>

Fix the "mediatek.mt6893-iommu-mm" compatible string typo, as the
dot was actually meant to be a comma: "mediatek,mt6893-iommu-mm".

Fixes: f6a1e89ab6e3 ("iommu/mediatek: Add support for Dimensity 1200 MT6893 MM IOMMU")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
---
 drivers/iommu/mtk_iommu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 0a54c6521bf5..cb95fecf6016 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -1791,7 +1791,7 @@ static const struct of_device_id mtk_iommu_of_ids[] = {
 	{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
 	{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
 	{ .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data},
-	{ .compatible = "mediatek.mt6893-iommu-mm", .data = &mt6893_data},
+	{ .compatible = "mediatek,mt6893-iommu-mm", .data = &mt6893_data},
 	{ .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
 	{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
 	{ .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
-- 
2.49.0



From patchwork-bot+bluetooth at kernel.org  Wed May 21 08:23:30 2025
From: patchwork-bot+bluetooth at kernel.org (patchwork-bot+bluetooth at kernel.org)
Date: Wed, 21 May 2025 15:23:30 +0000
Subject: [PATCH v2 0/2] Bluetooth: btmtksdio: ensure btmtksdio_close is
 executed before btmtksdio_remove
In-Reply-To: <20250422012156.586600-1-chris.lu@mediatek.com>
References: <20250422012156.586600-1-chris.lu@mediatek.com>
Message-ID: <174784101076.2084440.12163879869679696734.git-patchwork-notify@kernel.org>

Hello:

This series was applied to bluetooth/bluetooth-next.git (master)
by Luiz Augusto von Dentz <luiz.von.dentz at intel.com>:

On Tue, 22 Apr 2025 09:21:54 +0800 you wrote:
> If Bluetooth SDIO card is unexpectedly removed due to hardware removal
> or SDIO issue, it is possible for remove to be called before close.
> If an interrupt occurs during this process, it may cause kernel panic.
> Therefore, it is necessary to ensure that close is executed before
> remove to stop interrupts and cancel txrx workqueue.
> 
> Chris Lu (2):
>   Bluetooth: btmtksdio: Check function enabled before doing close
>   Bluetooth: btmtksdio: Do close if SDIO card removed without close
> 
> [...]

Here is the summary with links:
  - [v2,1/2] Bluetooth: btmtksdio: Check function enabled before doing close
    https://git.kernel.org/bluetooth/bluetooth-next/c/07e90048e356
  - [v2,2/2] Bluetooth: btmtksdio: Do close if SDIO card removed without close
    https://git.kernel.org/bluetooth/bluetooth-next/c/0b6d58bc6ea8

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html




From conor at kernel.org  Wed May 21 08:51:09 2025
From: conor at kernel.org (Conor Dooley)
Date: Wed, 21 May 2025 16:51:09 +0100
Subject: [PATCH net-next v3 1/4] dt-bindings: net: airoha: Add EN7581
 memory-region property
In-Reply-To: <20250521-airopha-desc-sram-v3-1-a6e9b085b4f0@kernel.org>
References: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
 <20250521-airopha-desc-sram-v3-1-a6e9b085b4f0@kernel.org>
Message-ID: <20250521-tinwork-numeric-35f98627d3d2@spud>

On Wed, May 21, 2025 at 09:16:36AM +0200, Lorenzo Bianconi wrote:
> Introduce memory-region and memory-region-names properties for the
> ethernet node available on EN7581 SoC in order to reserve system memory
> for hw forwarding buffers queue used by the QDMA modules.
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>

Acked-by: Conor Dooley <conor.dooley at microchip.com>
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From Markus.Elfring at web.de  Wed May 21 09:48:25 2025
From: Markus.Elfring at web.de (Markus Elfring)
Date: Wed, 21 May 2025 18:48:25 +0200
Subject: [PATCH] remoteproc: mediatek: Add SCP watchdog handler in IRQ
 processing
In-Reply-To: <20250521142404.1077-1-vulab@iscas.ac.cn>
References: <20250521142404.1077-1-vulab@iscas.ac.cn>
Message-ID: <cc69eb17-d55c-4843-8d90-fd49191c69e2@web.de>

> In mt8195_scp_c1_irq_handler(), only the IPC interrupt bit
> (MT8192_SCP_IPC_INT_BIT) was checked., but does not handle
> when this bit is not set. This could lead to unhandled watchdog
> events. This could lead to unhandled watchdog events. A proper
?

* You may occasionally put more than 63 characters into text lines
  of such a change description.

* Please avoid a duplicate sentence here.


Regards,
Markus


From Friday.Yang at mediatek.com  Wed May 21 19:42:46 2025
From: Friday.Yang at mediatek.com (=?utf-8?B?RnJpZGF5IFlhbmcgKOadqOmYsyk=?=)
Date: Thu, 22 May 2025 02:42:46 +0000
Subject: [PATCH v1] memory: mtk-smi: Add ostd setting for mt8186
In-Reply-To: <9c594eaa-9ddc-4340-ac0d-d911073764ac@collabora.com>
References: <20250521091626.4283-1-friday.yang@mediatek.com>
	 <9c594eaa-9ddc-4340-ac0d-d911073764ac@collabora.com>
Message-ID: <ee9f04f90721963feeeb98e83a8d4fb38ee6617c.camel@mediatek.com>

On Wed, 2025-05-21 at 11:26 +0200, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Il 21/05/25 11:16, Friday Yang ha scritto:
> > Add initial ostd setting for mt8186. All the settings come from DE.
> > These settings help adjust Multimedia HW's bandwidth limits to
> > achieve
> > a balanced bandwidth requirement. Without this, the VENC HW works
> > abnormal while stress testing.
> > 
> > Fixes: 86a010bfc739 ("memory: mtk-smi: mt8186: Add smi support")
> > Signed-off-by: Friday Yang <friday.yang at mediatek.com>
> 
> I agree about this commit and you can get my
> 
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno at collabora.com>
> 
> ...but I still have a question.
> 
> This driver is getting lots of those big OSTD arrays, and I can
> foresee this
> getting bigger and bigger with every new SoC getting supported in
> there.
> 
> I'd like to understand how we can improve that, hence, can you please
> describe
> how the OSTD values are calculated and how are they limiting the
> bandwidth?
> 
> I'm thinking that we can do something such that we get this runtime
> calculated
> instead of just holding fixed values, so that we may eventually
> replace all those
> big arrays with just a few values (foreseeing 3-4 values) and
> performing a big
> cleanup (which may bring further improvements in the future).
> 
> Cheers,
> Angelo
> 

Thank you for your comments.
OSTD indicates the number of commands that the SMI LARB has received
from masters but has not yet responded to from DRAM. The SMI LARB has a
set of registers for each port to set the OSTD value. For example, if
OSTD is set to 3, then the hardware allows 3 commands in the FIFO for
that LARB port.

For each SoC, the ESL DE simulates application scenarios and provides
an initial OSTD setting to the software. This is just the initial
configuration. We have MMQoS software that dynamically adjusts the
bandwidth and sets the OSTD-related registers of SMI. In the MT8196,
MMQoS will send upstream. However, in some projects, the MMQoS module
is not enabled, so we need to provide this initial OSTD setting to
achieve a balanced bandwidth requirement. Since we do not have a
formula to calculate OSTD, it is difficult for SMI to calculate OSTD at
runtime.

You are right, the SMI driver could become larger if we have to add
this OSTD array. How about adding an OSTD setting in the device tree?
For example, we could add a mediatek,smi-ostd array property for each
SMI LARB and SMI common. This would be more feasible for us. Is this
acceptable to you?

Best regard
Friday Yang

> > ---
> >   drivers/memory/mtk-smi.c | 33 +++++++++++++++++++++++++++++++++
> >   1 file changed, 33 insertions(+)
> > 
> > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
> > index c086c22511f7..733e22f695ab 100644
> > --- a/drivers/memory/mtk-smi.c
> > +++ b/drivers/memory/mtk-smi.c
> > @@ -320,6 +320,38 @@ static const u8
> > mtk_smi_larb_mt6893_ostd[][SMI_LARB_PORT_NR_MAX] = {
> >       [20] = {0x9, 0x9, 0x5, 0x5, 0x1, 0x1},
> >   };
> > 
> > +static const u8 mtk_smi_larb_mt8186_ostd[][SMI_LARB_PORT_NR_MAX] =
> > {
> > +     [0] = {0x2, 0x1, 0x8, 0x1,},
> > +     [1] = {0x1, 0x3, 0x1, 0x1,},
> > +     [2] = {0x6, 0x1, 0x4, 0x1,},
> > +     [3] = {},
> > +     [4] = {0xf, 0x1, 0x5, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
> > +            0x1, 0x1, 0x1,},
> > +     [5] = {},
> > +     [6] = {},
> > +     [7] = {0x1, 0x3, 0x1, 0x1, 0x1, 0x3, 0x2, 0xd, 0x7, 0x5, 0x3,
> > +            0x1, 0x5,},
> > +     [8] = {0x1, 0x2, 0x2,},
> > +     [9] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0xb, 0x7,
> > 0x4,
> > +            0x9, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
> > 0x1,
> > +            0x1, 0x1, 0x1, 0x1, 0x1,},
> > +     [10] = {},
> > +     [11] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0xb,
> > 0x7, 0x4,
> > +             0x9, 0x1, 0x1, 0x1, 0x1, 0x1, 0x8, 0x7, 0x7, 0x1,
> > 0x6, 0x2,
> > +             0xf, 0x8, 0x1, 0x1, 0x1,},
> > +     [12] = {},
> > +     [13] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x6, 0x6, 0x6, 0x1,
> > 0x1, 0x1,},
> > +     [14] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1,},
> > +     [15] = {},
> > +     [16] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x1, 0x14, 0x1, 0x4, 0x4,
> > 0x4,
> > +             0x2, 0x4, 0x2, 0x8, 0x4, 0x4,},
> > +     [17] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x1, 0x14, 0x1, 0x4, 0x4,
> > 0x4,
> > +             0x2, 0x4, 0x2, 0x8, 0x4, 0x4,},
> > +     [18] = {},
> > +     [19] = {0x1, 0x1, 0x1, 0x1,},
> > +     [20] = {0x2, 0x2, 0x2, 0x2, 0x1, 0x1,},
> > +};
> > +
> >   static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX]
> > = {
> >       [0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,},
> >       [1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,},
> > @@ -491,6 +523,7 @@ static const struct mtk_smi_larb_gen
> > mtk_smi_larb_mt8183 = {
> >   static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = {
> >       .config_port                =
> > mtk_smi_larb_config_port_gen2_general,
> >       .flags_general              = MTK_SMI_FLAG_SLEEP_CTL,
> > +     .ostd                       = mtk_smi_larb_mt8186_ostd,
> >   };
> > 
> >   static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = {
> > --
> > 2.46.0
> > 
> 
> 

From victor.liu at nxp.com  Wed May 21 20:01:13 2025
From: victor.liu at nxp.com (Liu Ying)
Date: Thu, 22 May 2025 11:01:13 +0800
Subject: [PATCH v2 30/34] drm/bridge: imx8qxp-pixel-combiner: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250506224720.5cbcf3e1@booty>
References: <20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b@bootlin.com>
 <20250424-drm-bridge-convert-to-alloc-api-v2-30-8f91a404d86b@bootlin.com>
 <553d62ed-976a-4e17-9678-cdc3d40ce4a7@nxp.com>
 <20250430112944.1b39caab@booty>
 <f71d18d2-4271-4bb9-b54f-0e5a585778f3@nxp.com>
 <20250506224720.5cbcf3e1@booty>
Message-ID: <67252c36-8b31-4c40-9d89-4f502da4a087@nxp.com>

On 05/07/2025, Luca Ceresoli wrote:

[...]

>> After looking into this patch and patch 31(though I've already provided my A-b)
>> more closely, I think the imx8qxp_pc and imx8{qm,qxp}_ldb main structures
>> should have the same life time with the embedded DRM bridges, because for
>> example the clk_apb clock in struct imx8qxp_pc would be accessed by the
>> imx8qxp_pc_bridge_mode_set DRM bridge callback.  But, IIUC, your patches extend
>> the life time for the embedded channel/bridge structures only, but not for the
>> main structures.  What do you think ?
> 
> I see you concern, but I'm sure the change I'm introducing is not
> creating the problem you are concerned about.
> 
> The key aspect is that my patch is merely changing the lifetime of the
> _allocation_ of the drm_bridge, not its usage. On drm_bridge_remove()
> the bridge is removed from its encoder chain and it is completely not
> reachable, both before and after my patch. With my patch it is not

drm_bridge_remove() only removes a bridge from the global bridge_list defined
in drm_bridge.c.  drm_bridge_detach() is the one which removes a bridge from
it's encoder chain.  It looks like you wrongly thought drm_bridge_remove()
is drm_bridge_detach().  So, even if drm_bridge_remove() is called, the removed
bridge could still be in it's encoder chain, hence an atomic commit could still
access the allocated bridge(with lifetime extended) and the clock_apb clock
for example in struct imx8qxp_pc could also be accessed.  That's why I think
the main structures should have the same lifetime with the allocated bridge.

> freed immediately, but it's just a piece of "wasted" memory that is
> still allocated until elsewhere in the kernel there are pointers to it,
> to avoid use-after-free.
> 
> With this explanation, do you think my patch is correct (after fixing
> the bug we already discussed of course)?
> 
> Best regards,
> Luca
> 

-- 
Regards,
Liu Ying


From victor.liu at nxp.com  Wed May 21 20:20:17 2025
From: victor.liu at nxp.com (Liu Ying)
Date: Thu, 22 May 2025 11:20:17 +0800
Subject: [PATCH v3 00/22] drm: convert all bridges to
 devm_drm_bridge_alloc()
In-Reply-To: <20250521162216.79dd3290@booty>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
 <20250521162216.79dd3290@booty>
Message-ID: <36ade269-a590-4243-889c-006f37d9ae6e@nxp.com>

On 05/21/2025, Luca Ceresoli wrote:
> Hello Maxime, Shawn, Liu, all,
> 
> On Fri, 09 May 2025 15:53:26 +0200
> Luca Ceresoli <luca.ceresoli at bootlin.com> wrote:
> 
>> devm_drm_bridge_alloc() [0] is the new API to allocate and initialize a DRM
>> bridge, and the only one supported from now on. It is the first milestone
>> towards removal of bridges from a still existing DRM pipeline without
>> use-after-free.
> 
> I applied on drm-misc-next patches 3-17,20-21 as they match all the
> criteria:
>  - At least a Acked-by (or R-by maintainers)
>  - patch is for drm-misc
> 
> Being my very first commits to drm-misc, I tried to be careful, and
> double checked all the patches with Louis (thanks!).
> 
> Here are the pending questions and plan for the remaining patches.
> 
>>       Revert "drm/exynos: mic: convert to devm_drm_bridge_alloc() API"
> 
> This reverts the commit applied my mistake:
> https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/91c5c7b5bb2dd09b43b025bce6d790d3c79f4518
> 
> Neither the  original patch nor the revert has been reviewed/acked.
> 
> As the commit was a mistake, I'm applying the revert by the end of this
> week (i.e. on Friday) unless there are better instructions.
> 
>>       drm: convert many bridge drivers from devm_kzalloc() to devm_drm_bridge_alloc() API
> 
> This patch affects multiple drivers. Running get_maintainers.pl
> points at Shawn Guo's repository. After reviewing the MAINTAINERS file,
> this looks like due to the 'N:' line in:
> 
> ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> M:	Shawn Guo <shawnguo at kernel.org>
> M:	Sascha Hauer <s.hauer at pengutronix.de>
> R:	Pengutronix Kernel Team <kernel at pengutronix.de>
> ...
> T:	git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
> N:	imx
> ...
> 
> (https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/drm-misc-next/MAINTAINERS?ref_type=heads#L2511-2528)
> 
> Here 'imx' matches the 'drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c'
> file that is touched by the patch. That regexp appears overly generic to me.
> 
> Shawn, can it be fixed by making it less generic?
> 
> If not, can we at least add a band-aid 'X:' entry for
> drivers/gpu/drm/bridge/imx?
> 
> I think the other matching entry is the one to consider:
> 
> DRM DRIVERS FOR FREESCALE IMX BRIDGE
> M:	Liu Ying <victor.liu at nxp.com>
> L:	dri-devel at lists.freedesktop.org
> S:	Maintained
> F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
> F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
> F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
> F:	drivers/gpu/drm/bridge/imx/
> 
> (https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/drm-misc-next/MAINTAINERS?ref_type=heads#L7940-7948)
> 
> However it does not list any trees. I _guess_ drm-misc applies here as
> a fallback as well as common sense.
> 
> Liu, should this entry have a 'T:' line for drm/misc?

These bridge drivers also don't have a 'T:' line:

DRM DRIVER FOR CHIPONE ICN6211 MIPI-DSI to RGB CONVERTER BRIDGE
DRM DRIVER FOR PARADE PS8640 BRIDGE CHIP
DRM DRIVER FOR TI DLPC3433 MIPI DSI TO DMD BRIDGE
DRM DRIVER FOR TI SN65DSI86 BRIDGE CHIP
LONTIUM LT8912B MIPI TO HDMI BRIDGE
MEGACHIPS STDPXXXX-GE-B850V3-FW LVDS/DP++ BRIDGES
MICROCHIP SAM9x7-COMPATIBLE LVDS CONTROLLER

I think that they fallback to drm-misc since "DRM DRIVERS FOR BRIDGE CHIPS"
covers them.  I don't have strong opinion on adding a "T" line to them, at
least to "DRM DRIVERS FOR FREESCALE IMX BRIDGE".  Anyway, it would be good
to know comments from maintainers for "DRM DRIVERS FOR BRIDGE CHIPS" and
"DRM DRIVERS".

> 
>>       drm/bridge: imx8qxp-pixel-combiner: convert to devm_drm_bridge_alloc() API
> 
> Not acked/reviewed, some discussion happened. I am resending it in v4,
> possibly with updates based on the discussion.

I still think the main structures in imx8qxp-pixel-combiner.c and imx*-ldb.c
should have the same lifetime with the allocated bridges.  I added a new
comment on this driver in v2 just now.

> 
> But it has the same issue discussed above, with get_maintiners.pl
> pointing at Shawn Guo's tree, so in the future I'm assuming this goes
> to drm-misc unless there are news about that.
> 
>>       drm/bridge: tc358767: convert to devm_drm_bridge_alloc() API
> 
> No feedback, resending in v4.
> 
>>       drm/todo: add entry to remove devm_drm_put_bridge()
> 
> This involves documentation maintained on another tree. Where should it
> be applied? There are two matching entries in MAINTAINERS:
> 
>  * DRM DRIVERS -> the drm tree
>  * DRM DRIVERS AND MISC GPU PATCHES -> the drm-misc tree
> 
> To me it looks like the second is obviously the closest match as we are
> dealing with DRM bridges, so I'm applying this as well on Friday unless
> there are better instructions.
> 
> Best regards,
> Luca
> 

-- 
Regards,
Liu Ying


From peter.wang at mediatek.com  Wed May 21 20:26:41 2025
From: peter.wang at mediatek.com (=?utf-8?B?UGV0ZXIgV2FuZyAo546L5L+h5Y+LKQ==?=)
Date: Thu, 22 May 2025 03:26:41 +0000
Subject: [PATCH v5] ufs: core: Add HID support
In-Reply-To: <20250521143317.637-1-tanghuan@vivo.com>
References: <ab468bb26dafca673d7ffca7dff519b7cf024cdc.camel@mediatek.com>
	 <20250521143317.637-1-tanghuan@vivo.com>
Message-ID: <f59c50ee3f5858535eca2887f326a8bb1117371f.camel@mediatek.com>

On Wed, 2025-05-21 at 22:33 +0800, Huan Tang wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> > > +static const char * const hid_trigger_mode[] = {"disable",
> 
> > > "enable"};
> 
> > > +
> 
> > > +static ssize_t analysis_trigger_store(struct device *dev,
> 
> > > +?????????????? struct device_attribute *attr, const char *buf,
> 
> > > size_t count)
> 
> > > +{
> 
> > > +?????? struct ufs_hba *hba = dev_get_drvdata(dev);
> 
> > > +?????? int mode;
> 
> > > +?????? int ret;
> 
> > > +
> 
> > > +?????? mode = sysfs_match_string(hid_trigger_mode, buf);
> 
> > > +?????? if (mode < 0)
> 
> > > +?????????????? return -EINVAL;
> 
> > > 
> 
> > 
> 
> > Hi Haun,
> 
> > 
> 
> > Consider use below coding style for readability.
> 
> > 
> 
> > if (sysfs_streq(buf, "enable"))
> 
> > ??? mode = ...;
> 
> > else if (sysfs_streq(buf, "disable"))
> 
> > ??? mode = ...;
> 
> > else
> 
> > ?? return -EINVAL;
> 
> 
> 
> Hi peter sir,
> 
> 
> 
> Thank you for your comments and guidance???
> I think your modification will indeed improve the readability of the
> code.
> 
> What do you think of the following changes?
> 
> 
> 
> ufs-sysfs.c
> 
> +static ssize_t analysis_trigger_store(struct device *dev,
> 
> +?????????????? struct device_attribute *attr, const char *buf,
> size_t count)
> 
> +{
> 
> +?????? struct ufs_hba *hba = dev_get_drvdata(dev);
> 
> +?????? int mode;
> 
> +?????? int ret;
> 
> +
> 
> +?????? if (sysfs_streq(buf, "enable"))
> 
> +?????????????? mode = HID_ANALYSIS_ENABLE;
> 
> +?????? else if (sysfs_streq(buf, "disable"))
> 
> +?????????????? mode = HID_ANALYSIS_AND_DEFRAG_DISABLE;
> 
> +?????? else
> 
> +?????????????? return -EINVAL;
> 
> +
> 
> +?????? ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
> 
> +?????????????????????? QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
> 
> +
> 
> +?????? return ret < 0 ? ret : count;
> 
> +}
> 
> +
> 
> +static DEVICE_ATTR_WO(analysis_trigger);
> 
> +
> 
> +static ssize_t defrag_trigger_store(struct device *dev,
> 
> +?????????????? struct device_attribute *attr, const char *buf,
> size_t count)
> 
> +{
> 
> +?????? struct ufs_hba *hba = dev_get_drvdata(dev);
> 
> +?????? int mode;
> 
> +?????? int ret;
> 
> +
> 
> +?????? if (sysfs_streq(buf, "enable"))
> 
> +?????????????? mode = HID_ANALYSIS_AND_DEFRAG_ENABLE;
> 
> +?????? else if (sysfs_streq(buf, "disable"))
> 
> +?????????????? mode = HID_ANALYSIS_AND_DEFRAG_DISABLE;
> 
> +?????? else
> 
> +?????????????? return -EINVAL;
> 
> +
> 
> +?????? ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
> 
> +?????????????????????? QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
> 
> +
> 
> +?????? return ret < 0 ? ret : count;
> 
> +}
> 
> 
> 
> 
> 
> Thanks
> 
> Huan
> 

Hi Huan,

looks good to me.

Thanks
Peter


From joro at 8bytes.org  Thu May 22 00:13:26 2025
From: joro at 8bytes.org (Joerg Roedel)
Date: Thu, 22 May 2025 09:13:26 +0200
Subject: [PATCH] iommu/mediatek: Fix compatible typo for
 mediatek,mt6893-iommu-mm
In-Reply-To: <20250521151548.185910-1-angelogioacchino.delregno@collabora.com>
References: <20250521151548.185910-1-angelogioacchino.delregno@collabora.com>
Message-ID: <aC7OlsGLaFvl6n95@8bytes.org>

Applied, thanks.


From luca.ceresoli at bootlin.com  Thu May 22 00:28:24 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Thu, 22 May 2025 09:28:24 +0200
Subject: [PATCH v3 00/22] drm: convert all bridges to
 devm_drm_bridge_alloc()
In-Reply-To: <36ade269-a590-4243-889c-006f37d9ae6e@nxp.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
	<20250521162216.79dd3290@booty>
	<36ade269-a590-4243-889c-006f37d9ae6e@nxp.com>
Message-ID: <20250522092824.421e766c@booty>

Hello Liu,

On Thu, 22 May 2025 11:20:17 +0800
Liu Ying <victor.liu at nxp.com> wrote:

> > If not, can we at least add a band-aid 'X:' entry for
> > drivers/gpu/drm/bridge/imx?
> > 
> > I think the other matching entry is the one to consider:
> > 
> > DRM DRIVERS FOR FREESCALE IMX BRIDGE
> > M:	Liu Ying <victor.liu at nxp.com>
> > L:	dri-devel at lists.freedesktop.org
> > S:	Maintained
> > F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
> > F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
> > F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> > F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
> > F:	drivers/gpu/drm/bridge/imx/
> > 
> > (https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/drm-misc-next/MAINTAINERS?ref_type=heads#L7940-7948)
> > 
> > However it does not list any trees. I _guess_ drm-misc applies here as
> > a fallback as well as common sense.
> > 
> > Liu, should this entry have a 'T:' line for drm/misc?  
> 
> These bridge drivers also don't have a 'T:' line:
> 
> DRM DRIVER FOR CHIPONE ICN6211 MIPI-DSI to RGB CONVERTER BRIDGE
> DRM DRIVER FOR PARADE PS8640 BRIDGE CHIP
> DRM DRIVER FOR TI DLPC3433 MIPI DSI TO DMD BRIDGE
> DRM DRIVER FOR TI SN65DSI86 BRIDGE CHIP
> LONTIUM LT8912B MIPI TO HDMI BRIDGE
> MEGACHIPS STDPXXXX-GE-B850V3-FW LVDS/DP++ BRIDGES
> MICROCHIP SAM9x7-COMPATIBLE LVDS CONTROLLER
> 
> I think that they fallback to drm-misc since "DRM DRIVERS FOR BRIDGE CHIPS"
> covers them.  I don't have strong opinion on adding a "T" line to them, at
> least to "DRM DRIVERS FOR FREESCALE IMX BRIDGE".  Anyway, it would be good
> to know comments from maintainers for "DRM DRIVERS FOR BRIDGE CHIPS" and
> "DRM DRIVERS".

I agree the fallback seems OK for this MAINTAINERS entry.

The other entry (ARM/FREESCALE IMX / MXC ARM ARCHITECTURE) is another
story.

> >>       drm/bridge: imx8qxp-pixel-combiner: convert to devm_drm_bridge_alloc() API  
> > 
> > Not acked/reviewed, some discussion happened. I am resending it in v4,
> > possibly with updates based on the discussion.  
> 
> I still think the main structures in imx8qxp-pixel-combiner.c and imx*-ldb.c
> should have the same lifetime with the allocated bridges.  I added a new
> comment on this driver in v2 just now.

Thanks, let's continue the conversation there.

Luca

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


From krzk at kernel.org  Thu May 22 00:52:07 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Thu, 22 May 2025 09:52:07 +0200
Subject: [PATCH v2 1/3] dt-bindings: mfd: mediatek: mt6397: Add
 #sound-dai-cells property
In-Reply-To: <20250514-mt8395-dtb-errors-v2-1-d67b9077c59a@collabora.com>
References: <20250514-mt8395-dtb-errors-v2-0-d67b9077c59a@collabora.com>
 <20250514-mt8395-dtb-errors-v2-1-d67b9077c59a@collabora.com>
Message-ID: <20250522-independent-ginger-bullfrog-4552d1@kuoka>

On Wed, May 14, 2025 at 10:19:56AM GMT, Julien Massot wrote:
> The 'mt6359.dtsi' file already uses the '#sound-dai-cells' property.
> Add the corresponding property to the binding to fix the following
> dtb-check error:
> 
> mediatek/mt8395-radxa-nio-12l.dtb: pmic: '#sound-dai-cells', 'mt6359rtc' do not match any of the regexes: 'pinctrl-[0-9]+'
> from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6397.yaml#

If this is a random drive-by, would be fine, but if that's your platform
which you should know, then I expect this to be a real reason instead
something which can easily be rejected with: what if DTS is wrong?

I could not find the ASoC driver for that compatible and quick glance to
MFD shown me no usage of dai cells, so you need proper explanation here.

Especially, that there is a subnode audio-codec, so adding dai cells to
the parent node feels just wrong. One is wrong - either subnode or
parent is a codec.

> 
> Fixes: 9bc8353be720 ("arm64: dts: mt6359: Add #sound-dai-cells property")
> Signed-off-by: Julien Massot <julien.massot at collabora.com>
> ---
>  Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
> index 6a89b479d10fad3c8b61cab5a3af1453baca4d1a..9580c4ec1ae00f1dd1182357d8b0a5035a1b7f82 100644
> --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
> +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
> @@ -30,6 +30,9 @@ description: |
>    See the following for pwrap node definitions:
>    Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
>  
> +allOf:
> +  - $ref: /schemas/sound/dai-common.yaml#
> +
>  properties:
>    compatible:
>      oneOf:
> @@ -53,6 +56,9 @@ properties:
>    "#interrupt-cells":
>      const: 2
>  
> +  '#sound-dai-cells':
> +    const: 1

Also extend the example, if there is one for such device.

Best regards,
Krzysztof



From krzk at kernel.org  Thu May 22 01:08:00 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Thu, 22 May 2025 10:08:00 +0200
Subject: [PATCH v2 2/3] dt-bindings: iommu: mediatek: Support 5 IRQs on
 MT8195 infra IOMMU
In-Reply-To: <20250514-mt8395-dtb-errors-v2-2-d67b9077c59a@collabora.com>
References: <20250514-mt8395-dtb-errors-v2-0-d67b9077c59a@collabora.com>
 <20250514-mt8395-dtb-errors-v2-2-d67b9077c59a@collabora.com>
Message-ID: <20250522-foamy-cricket-of-defiance-edc2cd@kuoka>

On Wed, May 14, 2025 at 10:19:57AM GMT, Julien Massot wrote:
> @@ -97,7 +97,8 @@ properties:
>      maxItems: 1
>  
>    interrupts:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 5
>  
>    clocks:
>      items:
> @@ -201,6 +202,21 @@ allOf:
>        required:
>          - mediatek,infracfg
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - mediatek,mt8195-iommu-infra
> +    then:
> +      properties:
> +        interrupts:
> +          minItems: 5

Instead list the items here and in else:, or in top-level if first
interrupt is the same.

> +    else:
> +      properties:
> +        interrupts:
> +          maxItems: 1

Best regards,
Krzysztof



From kuyo.chang at mediatek.com  Thu May 22 01:10:26 2025
From: kuyo.chang at mediatek.com (Kuyo Chang)
Date: Thu, 22 May 2025 16:10:26 +0800
Subject: [PATCH 1/1] [Bug] list_add corruption during CPU hotplug stress
 test
In-Reply-To: <20250521064238.3173224-1-kuyo.chang@mediatek.com>
References: <20250521064238.3173224-1-kuyo.chang@mediatek.com>
Message-ID: <a94b05d7fa647d1b358d28c604f87c03673f417c.camel@mediatek.com>

On Wed, 2025-05-21 at 14:42 +0800, Kuyo Chang wrote:
> From: kuyo chang <kuyo.chang at mediatek.com>
> 
> The commit (stop_machine, sched: Fix migrate_swap() vs.
> active_balance() deadlock)
> introduces wake_q_add rather than wake_up_process.
> However, it encounters sporadic failures during CPU hotplug stress
> test.
> 
> The kernel log shows list add fail as below
> kmemleak: list_add corruption. prev->next should be next
> (ffffff82812c7a00), but was 0000000000000000.
> (prev=ffffff82812c3208).
> kmemleak: kernel BUG at lib/list_debug.c:34!
> kmemleak: Call trace:
> kmemleak:? __list_add_valid_or_report+0x11c/0x144
> kmemleak:? cpu_stop_queue_work+0x440/0x474
> kmemleak:? stop_one_cpu_nowait_rec+0xe4/0x138
> kmemleak:? balance_push+0x1f4/0x3e4
> kmemleak:? __schedule+0x1adc/0x23bc
> kmemleak:? preempt_schedule_common+0x68/0xd0
> kmemleak:? preempt_schedule+0x60/0x80
> kmemleak:? _raw_spin_unlock_irqrestore+0x9c/0xa0
> kmemleak:? scan_gray_list+0x220/0x3e4
> kmemleak:? kmemleak_scan+0x410/0x740
> kmemleak:? kmemleak_scan_thread+0xb0/0xdc
> kmemleak:? kthread+0x2bc/0x494
> kmemleak:? ret_from_fork+0x10/0x20
> 
> Because the reproduction rate is very low, I designed a simple debug
> patch to help find the root cause of these sporadic failures.
> The purpose of this debug patch is to record the status of push_work
> at balance_push, cpu_stopper, and cpu_stop_work.
> In the regular case, we queue the push_work to stopper->works and set
> work->exec_state = WORK_QUEUE.
> Then, we call wake_q_add for the stopper and set
> cpu_stopper.stopper_wakeq = WAKEQ_ADD_OK.
> Finally, we wake up the stopper, which picks up the work from
> cpu_stop_work to execute.
> We then set stopper->exec_state = WORK_PREP_EXEC to indicate that the
> push_work has been consumed.
> 
> However, in the failure case, by memory dump
> cpu_stopper.stopper_wakeq = WAKEQ_ADD_FAIL
> stopper->exec_state = WORK_QUEUE.
> cpu_stopper.enabled = TRUE
> 
> Here is the failure sequence that leads to the bug.
> CPU0
> 1st balance_push
> stop_one_cpu_nowait
> cpu_stop_queue_work
> __cpu_stop_queue_work
> list_add_tail? -> fist add work
> wake_q_add?? -> returns failure
> wake_up_q(&wakeq); -> it doesn't wake up the stopper.
> 2nd balance_push
> stop_one_cpu_nowait
> cpu_stop_queue_work
> __cpu_stop_queue_work
> list_add_tail? -> A double list add is detected, which triggers
> kernel bugs.
> 
> Should we add queue status tracking in __cpu_stop_queue_work,
> or is there a better place to do this?
> 
> Signed-off-by: kuyo chang <kuyo.chang at mediatek.com>
> ---
> ?include/linux/sched/wake_q.h |? 1 +
> ?include/linux/stop_machine.h | 20 ++++++++++++++++++++
> ?kernel/sched/core.c????????? | 15 ++++++++++++++-
> ?kernel/stop_machine.c??????? | 36
> ++++++++++++++++++++++++++++++++++--
> ?4 files changed, 69 insertions(+), 3 deletions(-)
> 
> diff --git a/include/linux/sched/wake_q.h
> b/include/linux/sched/wake_q.h
> index 0f28b4623ad4..083ced4bb5dc 100644
> --- a/include/linux/sched/wake_q.h
> +++ b/include/linux/sched/wake_q.h
> @@ -60,6 +60,7 @@ static inline bool wake_q_empty(struct wake_q_head
> *head)
> ?}
> ?
> ?extern void wake_q_add(struct wake_q_head *head, struct task_struct
> *task);
> +extern bool wake_q_add_ret(struct wake_q_head *head, struct
> task_struct *task);
> ?extern void wake_q_add_safe(struct wake_q_head *head, struct
> task_struct *task);
> ?extern void wake_up_q(struct wake_q_head *head);
> ?
> diff --git a/include/linux/stop_machine.h
> b/include/linux/stop_machine.h
> index 3132262a404d..6daec44dcb99 100644
> --- a/include/linux/stop_machine.h
> +++ b/include/linux/stop_machine.h
> @@ -21,18 +21,38 @@ typedef int (*cpu_stop_fn_t)(void *arg);
> ?
> ?#ifdef CONFIG_SMP
> ?
> +enum work_state {
> +	WORK_INIT = 0,
> +	WORK_READY,
> +	WORK_QUEUE,
> +	WORK_PREP_EXEC,
> +};
> +
> +enum stopper_wakeq_state {
> +	WAKEQ_ADD_FAIL = 0,
> +	WAKEQ_ADD_OK,
> +};
> +
> +enum work_rec {
> +	WORK_NO_REC = 0,
> +	WORK_REC,
> +};
> ?struct cpu_stop_work {
> ?	struct list_head	list;		/* cpu_stopper-
> >works */
> ?	cpu_stop_fn_t		fn;
> ?	unsigned long		caller;
> ?	void			*arg;
> ?	struct cpu_stop_done	*done;
> +	enum work_rec		rec;
> +	enum work_state exec_state;
> ?};
> ?
> ?int stop_one_cpu(unsigned int cpu, cpu_stop_fn_t fn, void *arg);
> ?int stop_two_cpus(unsigned int cpu1, unsigned int cpu2,
> cpu_stop_fn_t fn, void *arg);
> ?bool stop_one_cpu_nowait(unsigned int cpu, cpu_stop_fn_t fn, void
> *arg,
> ?			 struct cpu_stop_work *work_buf);
> +bool stop_one_cpu_nowait_rec(unsigned int cpu, cpu_stop_fn_t fn,
> void *arg,
> +			struct cpu_stop_work *work_buf);
> ?void stop_machine_park(int cpu);
> ?void stop_machine_unpark(int cpu);
> ?void stop_machine_yield(const struct cpumask *cpumask);
> diff --git a/kernel/sched/core.c b/kernel/sched/core.c
> index c81cf642dba0..a617f51d3e5a 100644
> --- a/kernel/sched/core.c
> +++ b/kernel/sched/core.c
> @@ -1037,6 +1037,19 @@ void wake_q_add(struct wake_q_head *head,
> struct task_struct *task)
> ?		get_task_struct(task);
> ?}
> ?
> +/**
> + * wake_q_add_ret() - queue a wakeup for 'later' waking. record
> status.
> + */
> +bool wake_q_add_ret(struct wake_q_head *head, struct task_struct
> *task)
> +{
> +	bool ret = false;
> +
> +	ret = __wake_q_add(head, task);
> +	if (ret)
> +		get_task_struct(task);
> +	return ret;
> +}
> +
> ?/**
> ? * wake_q_add_safe() - safely queue a wakeup for 'later' waking.
> ? * @head: the wake_q_head to add @task to
> @@ -8100,7 +8113,7 @@ static void balance_push(struct rq *rq)
> ?	 */
> ?	preempt_disable();
> ?	raw_spin_rq_unlock(rq);
> -	stop_one_cpu_nowait(rq->cpu, __balance_push_cpu_stop,
> push_task,
> +	stop_one_cpu_nowait_rec(rq->cpu, __balance_push_cpu_stop,
> push_task,
> ?			??? this_cpu_ptr(&push_work));
> ?	preempt_enable();
> ?	/*
> diff --git a/kernel/stop_machine.c b/kernel/stop_machine.c
> index 5d2d0562115b..3a2c48ed2182 100644
> --- a/kernel/stop_machine.c
> +++ b/kernel/stop_machine.c
> @@ -42,6 +42,8 @@ struct cpu_stopper {
> ?	struct list_head	works;		/* list of pending
> works */
> ?
> ?	struct cpu_stop_work	stop_work;	/* for stop_cpus */
> +	enum stopper_wakeq_state stopper_wakeq;		/*
> for stopper wakeup */
> +	enum work_state exec_state;			/* for
> stopper exec state */
> ?	unsigned long		caller;
> ?	cpu_stop_fn_t		fn;
> ?};
> @@ -85,8 +87,18 @@ static void __cpu_stop_queue_work(struct
> cpu_stopper *stopper,
> ?					struct cpu_stop_work *work,
> ?					struct wake_q_head *wakeq)
> ?{
> +	bool wake_flag;
> +
> ?	list_add_tail(&work->list, &stopper->works);
> -	wake_q_add(wakeq, stopper->thread);
> +	wake_flag = wake_q_add_ret(wakeq, stopper->thread);
> +	if (work->rec == WORK_REC) {
> +		work->exec_state = WORK_QUEUE;
> +		stopper->exec_state = WORK_QUEUE;
> +		if (wake_flag)
> +			stopper->stopper_wakeq = WAKEQ_ADD_OK;
> +		else
> +			stopper->stopper_wakeq = WAKEQ_ADD_FAIL;
> +	}
> ?}
> ?
> ?/* queue @work to @stopper.? if offline, @work is completed
> immediately */
> @@ -141,6 +153,8 @@ int stop_one_cpu(unsigned int cpu, cpu_stop_fn_t
> fn, void *arg)
> ?	struct cpu_stop_done done;
> ?	struct cpu_stop_work work = { .fn = fn, .arg = arg, .done =
> &done, .caller = _RET_IP_ };
> ?
> +	work.rec = WORK_NO_REC;
> +	work.exec_state = WORK_INIT;
> ?	cpu_stop_init_done(&done, 1);
> ?	if (!cpu_stop_queue_work(cpu, &work))
> ?		return -ENOENT;
> @@ -350,6 +364,8 @@ int stop_two_cpus(unsigned int cpu1, unsigned int
> cpu2, cpu_stop_fn_t fn, void *
> ?		.arg = &msdata,
> ?		.done = &done,
> ?		.caller = _RET_IP_,
> +		.rec = WORK_NO_REC,
> +		.exec_state = WORK_INIT,
> ?	};
> ?
> ?	cpu_stop_init_done(&done, 2);
> @@ -386,6 +402,17 @@ bool stop_one_cpu_nowait(unsigned int cpu,
> cpu_stop_fn_t fn, void *arg,
> ?			struct cpu_stop_work *work_buf)
> ?{
> ?	*work_buf = (struct cpu_stop_work){ .fn = fn, .arg = arg,
> .caller = _RET_IP_, };
> +	work_buf->rec = WORK_NO_REC;
> +	work_buf->exec_state = WORK_INIT;
> +	return cpu_stop_queue_work(cpu, work_buf);
> +}
> +
> +bool stop_one_cpu_nowait_rec(unsigned int cpu, cpu_stop_fn_t fn,
> void *arg,
> +			struct cpu_stop_work *work_buf)
> +{
> +	*work_buf = (struct cpu_stop_work){ .fn = fn, .arg = arg,
> .caller = _RET_IP_, };
> +	work_buf->rec = WORK_REC;
> +	work_buf->exec_state = WORK_READY;
> ?	return cpu_stop_queue_work(cpu, work_buf);
> ?}
> ?
> @@ -411,6 +438,8 @@ static bool queue_stop_cpus_work(const struct
> cpumask *cpumask,
> ?		work->arg = arg;
> ?		work->done = done;
> ?		work->caller = _RET_IP_;
> +		work->rec = WORK_NO_REC;
> +		work->exec_state = WORK_INIT;
> ?		if (cpu_stop_queue_work(cpu, work))
> ?			queued = true;
> ?	}
> @@ -496,6 +525,8 @@ static void cpu_stopper_thread(unsigned int cpu)
> ?		work = list_first_entry(&stopper->works,
> ?					struct cpu_stop_work, list);
> ?		list_del_init(&work->list);
> +		if (work->rec == WORK_REC)
> +			stopper->exec_state = WORK_PREP_EXEC;
> ?	}
> ?	raw_spin_unlock_irq(&stopper->lock);
> ?
> @@ -572,7 +603,8 @@ static int __init cpu_stop_init(void)
> ?
> ?	for_each_possible_cpu(cpu) {
> ?		struct cpu_stopper *stopper = &per_cpu(cpu_stopper,
> cpu);
> -
> +		stopper->exec_state = WORK_INIT;
> +		stopper->stopper_wakeq = WAKEQ_ADD_OK;
> ?		raw_spin_lock_init(&stopper->lock);
> ?		INIT_LIST_HEAD(&stopper->works);
> ?	}


The test kernel version is 6.12.22

And add the timeslot log for this issue.
[   99407090000] kmemleak: list_add corruption. prev->next should be
next (ffffff82812c7a00), but was 0000000000000000.
(prev=ffffff82812c3208).
[   99408874000] kmemleak: ------------[ cut here ]------------
[   99409727000] kmemleak: kernel BUG at lib/list_debug.c:34!
[   99410555000] kmemleak: Internal error: Oops - BUG: 00000000f2000800
[#1] PREEMPT SMP

I dumped the stop task's sched_info as below.
on_cpu = 0x0,
on_rq = 0x1,
sched_info = (
        pcount = 0x0B7D,
        run_delay = 0x08248680,
        last_arrival = 0x0000001724054D00,
        last_queued = 0x0000001725208400),
}

The last_queued time (0x0000001725208400 = 99,407,135,744 ns) indicates
when the stopper was enqueued (wake_up_q->wake_up_process->ttwu), 
which occurred just after the list_add corruption (99,407,090,000 ns).
Therefore, let me correct my previous description: the wake_q_add
stopper is fine, but the subsequent latency wakeup stopper causes this
issue.





From jason-jh.lin at mediatek.com  Thu May 22 01:34:24 2025
From: jason-jh.lin at mediatek.com (Jason-JH Lin)
Date: Thu, 22 May 2025 16:34:24 +0800
Subject: [PATCH] drm/mediatek: Add wait_event_timeout when disabling plane
Message-ID: <20250522085149.3361598-1-jason-jh.lin@mediatek.com>

Our hardware registers are set through GCE, not by the CPU.
DRM might assume the hardware is disabled immediately after calling
atomic_disable() of drm_plane, but it is only truly disabled after the
GCE IRQ is triggered.

Additionally, the cursor plane in DRM uses async_commit, so DRM will
not wait for vblank and will free the buffer immediately after calling
atomic_disable().

To prevent the framebuffer from being freed before the layer disable
settings are configured into the hardware, which can cause an IOMMU
fault error, a wait_event_timeout has been added to wait for the
ddp_cmdq_cb() callback,indicating that the GCE IRQ has been triggered.

Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_crtc.c  | 30 ++++++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_crtc.h  |  1 +
 drivers/gpu/drm/mediatek/mtk_plane.c |  5 +++++
 3 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c
index 8f6fba4217ec..944a3d1e5ec9 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.c
@@ -719,6 +719,36 @@ int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
 	return 0;
 }
 
+void mtk_crtc_plane_disable(struct drm_crtc *crtc, struct drm_plane *plane)
+{
+	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
+	struct mtk_plane_state *plane_state = to_mtk_plane_state(plane->state);
+	int i;
+
+	if (!mtk_crtc->enabled)
+		return;
+
+	/* set pending plane state to disabled */
+	for (i = 0; i < mtk_crtc->layer_nr; i++) {
+		struct drm_plane *mtk_plane = &mtk_crtc->planes[i];
+		struct mtk_plane_state *mtk_plane_state = to_mtk_plane_state(mtk_plane->state);
+
+		if (mtk_plane->index == plane->index) {
+			memcpy(mtk_plane_state, plane_state, sizeof(*plane_state));
+			break;
+		}
+	}
+	mtk_crtc_update_config(mtk_crtc, false);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	/* wait for planes to be disabled by cmdq */
+	if (mtk_crtc->cmdq_client.chan)
+		wait_event_timeout(mtk_crtc->cb_blocking_queue,
+				   mtk_crtc->cmdq_vblank_cnt == 0,
+				   msecs_to_jiffies(500));
+#endif
+}
+
 void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
 			   struct drm_atomic_state *state)
 {
diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.h b/drivers/gpu/drm/mediatek/mtk_crtc.h
index 388e900b6f4d..828f109b83e7 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.h
@@ -21,6 +21,7 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
 		    unsigned int num_conn_routes);
 int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
 			 struct mtk_plane_state *state);
+void mtk_crtc_plane_disable(struct drm_crtc *crtc, struct drm_plane *plane);
 void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
 			   struct drm_atomic_state *plane_state);
 struct device *mtk_crtc_dma_dev_get(struct drm_crtc *crtc);
diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediatek/mtk_plane.c
index 655106bbb76d..59edbe26f01e 100644
--- a/drivers/gpu/drm/mediatek/mtk_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_plane.c
@@ -285,9 +285,14 @@ static void mtk_plane_atomic_disable(struct drm_plane *plane,
 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 									   plane);
 	struct mtk_plane_state *mtk_plane_state = to_mtk_plane_state(new_state);
+	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+									   plane);
+
 	mtk_plane_state->pending.enable = false;
 	wmb(); /* Make sure the above parameter is set before update */
 	mtk_plane_state->pending.dirty = true;
+
+	mtk_crtc_plane_disable(old_state->crtc, plane);
 }
 
 static void mtk_plane_atomic_update(struct drm_plane *plane,
-- 
2.43.0



From angelogioacchino.delregno at collabora.com  Thu May 22 03:28:48 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Thu, 22 May 2025 12:28:48 +0200
Subject: [PATCH v1] memory: mtk-smi: Add ostd setting for mt8186
In-Reply-To: <ee9f04f90721963feeeb98e83a8d4fb38ee6617c.camel@mediatek.com>
References: <20250521091626.4283-1-friday.yang@mediatek.com>
 <9c594eaa-9ddc-4340-ac0d-d911073764ac@collabora.com>
 <ee9f04f90721963feeeb98e83a8d4fb38ee6617c.camel@mediatek.com>
Message-ID: <a41e6b0c-5482-4947-8051-78fe677f5098@collabora.com>

Il 22/05/25 04:42, Friday Yang (??) ha scritto:
> On Wed, 2025-05-21 at 11:26 +0200, AngeloGioacchino Del Regno wrote:
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>
>>
>> Il 21/05/25 11:16, Friday Yang ha scritto:
>>> Add initial ostd setting for mt8186. All the settings come from DE.
>>> These settings help adjust Multimedia HW's bandwidth limits to
>>> achieve
>>> a balanced bandwidth requirement. Without this, the VENC HW works
>>> abnormal while stress testing.
>>>
>>> Fixes: 86a010bfc739 ("memory: mtk-smi: mt8186: Add smi support")
>>> Signed-off-by: Friday Yang <friday.yang at mediatek.com>
>>
>> I agree about this commit and you can get my
>>
>> Reviewed-by: AngeloGioacchino Del Regno <
>> angelogioacchino.delregno at collabora.com>
>>
>> ...but I still have a question.
>>
>> This driver is getting lots of those big OSTD arrays, and I can
>> foresee this
>> getting bigger and bigger with every new SoC getting supported in
>> there.
>>
>> I'd like to understand how we can improve that, hence, can you please
>> describe
>> how the OSTD values are calculated and how are they limiting the
>> bandwidth?
>>
>> I'm thinking that we can do something such that we get this runtime
>> calculated
>> instead of just holding fixed values, so that we may eventually
>> replace all those
>> big arrays with just a few values (foreseeing 3-4 values) and
>> performing a big
>> cleanup (which may bring further improvements in the future).
>>
>> Cheers,
>> Angelo
>>
> 
> Thank you for your comments.
> OSTD indicates the number of commands that the SMI LARB has received
> from masters but has not yet responded to from DRAM. The SMI LARB has a
> set of registers for each port to set the OSTD value. For example, if
> OSTD is set to 3, then the hardware allows 3 commands in the FIFO for
> that LARB port.
> 

> For each SoC, the ESL DE simulates application scenarios and provides
> an initial OSTD setting to the software. This is just the initial
> configuration.
 >

Thanks for this valuable information.

I wonder if you could please send a commit to add this information as a
comment into this driver, and/or in mediatek,smi-larb.yaml so that it will
not get lost :-)

> We have MMQoS software that dynamically adjusts the
> bandwidth and sets the OSTD-related registers of SMI. In the MT8196,
> MMQoS will send upstream. However, in some projects, the MMQoS module
> is not enabled, so we need to provide this initial OSTD setting to
> achieve a balanced bandwidth requirement. Since we do not have a
> formula to calculate OSTD, it is difficult for SMI to calculate OSTD at
> runtime.
> 

If the MMQoS is upstreamed and enabled, do we still need a "default" OSTD
configuration (for example, MT8196)?

> You are right, the SMI driver could become larger if we have to add
> this OSTD array. How about adding an OSTD setting in the device tree?
> For example, we could add a mediatek,smi-ostd array property for each
> SMI LARB and SMI common. This would be more feasible for us. Is this
> acceptable to you?

Unfortunately, this is not possible.

Devicetree is used to describe hardware, and this is configuration that does
not describe hardware, so this cannot go to the devicetree.

Though, if using MMQoS means that we don't need to add a default OSTD array,
this situation gets resolved as, from what I can see in the MT6991 downstream
kernel, the MMQoS module evaluates bandwidth numbers to calculate OSTD params.

That could be implemented as an interconnect driver: in that case, it would be
possible to leverage devicetree as we'd be specifying hardware interconnection
bandwidth "gears".

The DT would look more or less like:

disp_controller_opp_table: opp-table {
	compatible = "operating-points-v2";

	opp-0 {
		(frequencies and voltages if applicable, or none)

		opp-peak-kBps = <peak-bandwidth-value-in-kbps>;

		opp-avg-kBps = <average-bandwidth-in-kbps>; /* this is optional */
	};
	opp-1 .... etc
};

display-controller at 1234 {
	compatible = "mediatek,xyz";

	interconnects = <&mmqos MASTER_SOMETHING &mmqos SLAVE_SOMETHING>;
	operating-points-v2 = <&disp_controller_opp_table>;
};

...so that then MMQoS can set the OSTD values to SMI :-)

Thanks again!
Angelo

> 
> Best regard
> Friday Yang
> 
>>> ---
>>>    drivers/memory/mtk-smi.c | 33 +++++++++++++++++++++++++++++++++
>>>    1 file changed, 33 insertions(+)
>>>
>>> diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
>>> index c086c22511f7..733e22f695ab 100644
>>> --- a/drivers/memory/mtk-smi.c
>>> +++ b/drivers/memory/mtk-smi.c
>>> @@ -320,6 +320,38 @@ static const u8
>>> mtk_smi_larb_mt6893_ostd[][SMI_LARB_PORT_NR_MAX] = {
>>>        [20] = {0x9, 0x9, 0x5, 0x5, 0x1, 0x1},
>>>    };
>>>
>>> +static const u8 mtk_smi_larb_mt8186_ostd[][SMI_LARB_PORT_NR_MAX] =
>>> {
>>> +     [0] = {0x2, 0x1, 0x8, 0x1,},
>>> +     [1] = {0x1, 0x3, 0x1, 0x1,},
>>> +     [2] = {0x6, 0x1, 0x4, 0x1,},
>>> +     [3] = {},
>>> +     [4] = {0xf, 0x1, 0x5, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
>>> +            0x1, 0x1, 0x1,},
>>> +     [5] = {},
>>> +     [6] = {},
>>> +     [7] = {0x1, 0x3, 0x1, 0x1, 0x1, 0x3, 0x2, 0xd, 0x7, 0x5, 0x3,
>>> +            0x1, 0x5,},
>>> +     [8] = {0x1, 0x2, 0x2,},
>>> +     [9] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0xb, 0x7,
>>> 0x4,
>>> +            0x9, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
>>> 0x1,
>>> +            0x1, 0x1, 0x1, 0x1, 0x1,},
>>> +     [10] = {},
>>> +     [11] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0xb,
>>> 0x7, 0x4,
>>> +             0x9, 0x1, 0x1, 0x1, 0x1, 0x1, 0x8, 0x7, 0x7, 0x1,
>>> 0x6, 0x2,
>>> +             0xf, 0x8, 0x1, 0x1, 0x1,},
>>> +     [12] = {},
>>> +     [13] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x6, 0x6, 0x6, 0x1,
>>> 0x1, 0x1,},
>>> +     [14] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1,},
>>> +     [15] = {},
>>> +     [16] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x1, 0x14, 0x1, 0x4, 0x4,
>>> 0x4,
>>> +             0x2, 0x4, 0x2, 0x8, 0x4, 0x4,},
>>> +     [17] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x1, 0x14, 0x1, 0x4, 0x4,
>>> 0x4,
>>> +             0x2, 0x4, 0x2, 0x8, 0x4, 0x4,},
>>> +     [18] = {},
>>> +     [19] = {0x1, 0x1, 0x1, 0x1,},
>>> +     [20] = {0x2, 0x2, 0x2, 0x2, 0x1, 0x1,},
>>> +};
>>> +
>>>    static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX]
>>> = {
>>>        [0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,},
>>>        [1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,},
>>> @@ -491,6 +523,7 @@ static const struct mtk_smi_larb_gen
>>> mtk_smi_larb_mt8183 = {
>>>    static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = {
>>>        .config_port                =
>>> mtk_smi_larb_config_port_gen2_general,
>>>        .flags_general              = MTK_SMI_FLAG_SLEEP_CTL,
>>> +     .ostd                       = mtk_smi_larb_mt8186_ostd,
>>>    };
>>>
>>>    static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = {
>>> --
>>> 2.46.0
>>>
>>
>>


From angelogioacchino.delregno at collabora.com  Thu May 22 03:30:36 2025
From: angelogioacchino.delregno at collabora.com (AngeloGioacchino Del Regno)
Date: Thu, 22 May 2025 12:30:36 +0200
Subject: [PATCH] drm/mediatek: Add wait_event_timeout when disabling plane
In-Reply-To: <20250522085149.3361598-1-jason-jh.lin@mediatek.com>
References: <20250522085149.3361598-1-jason-jh.lin@mediatek.com>
Message-ID: <aed94e06-455f-4aa3-8740-57bd1facad22@collabora.com>

Il 22/05/25 10:34, Jason-JH Lin ha scritto:
> Our hardware registers are set through GCE, not by the CPU.
> DRM might assume the hardware is disabled immediately after calling
> atomic_disable() of drm_plane, but it is only truly disabled after the
> GCE IRQ is triggered.
> 
> Additionally, the cursor plane in DRM uses async_commit, so DRM will
> not wait for vblank and will free the buffer immediately after calling
> atomic_disable().
> 
> To prevent the framebuffer from being freed before the layer disable
> settings are configured into the hardware, which can cause an IOMMU
> fault error, a wait_event_timeout has been added to wait for the
> ddp_cmdq_cb() callback,indicating that the GCE IRQ has been triggered.
> 
> Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
> Signed-off-by: Jason-JH Lin <jason-jh.lin at mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>




From nbd at nbd.name  Thu May 22 03:49:55 2025
From: nbd at nbd.name (Felix Fietkau)
Date: Thu, 22 May 2025 12:49:55 +0200
Subject: [PATCH v2 2/2] wifi: mt76: mt7925: add RNR scan support for 6GHz
In-Reply-To: <20250321013829.3598-2-mingyen.hsieh@mediatek.com>
References: <20250321013829.3598-1-mingyen.hsieh@mediatek.com>
 <20250321013829.3598-2-mingyen.hsieh@mediatek.com>
Message-ID: <5a659f60-896e-4f2f-89c0-141e530c44d5@nbd.name>

On 21.03.25 02:38, Mingyen Hsieh wrote:
> From: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
> 
> Enhance the mt7925 to include RNR scan support. It adds
> the necessary RNR information to the scan command.
> 
> Signed-off-by: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
> ---
> v2:
>    - use '= {}' to replace the '= {0}' for short_ssid array.
>    - align with the open paranthesis for crc32_le.
>    - use ether_addr_copy() to replace the memcpy of bssid.
> ---
>   .../net/wireless/mediatek/mt76/mt7925/mcu.c   | 36 ++++++++++++++++---
>   .../net/wireless/mediatek/mt76/mt7925/mcu.h   | 17 +++++----
>   2 files changed, 41 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> index 243adace8799..22686faca1af 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> @@ -3078,7 +3079,11 @@ int mt7925_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
>   	for (i = 0; i < sreq->n_ssids; i++) {
>   		if (!sreq->ssids[i].ssid_len)
>   			continue;
> +		if (i > MT7925_RNR_SCAN_MAX_BSSIDS)
> +			break;
>   
> +		short_ssid[i] = ~crc32_le(~0, sreq->ssids[i].ssid,
> +					  sreq->ssids[i].ssid_len);

I had to remove this variable due to a unused-but-set warning. I'm not 
sure if the contents of it should have been stored somewhere in the MCU 
message, or if this was something that ended up not being necessary.
Please review and send a follow-up fix if needed.

- Felix


From Mingyen.Hsieh at mediatek.com  Thu May 22 04:12:14 2025
From: Mingyen.Hsieh at mediatek.com (=?utf-8?B?TWluZ3llbiBIc2llaCAo6Kyd5piO6Ku6KQ==?=)
Date: Thu, 22 May 2025 11:12:14 +0000
Subject: [PATCH v2 2/2] wifi: mt76: mt7925: add RNR scan support for 6GHz
In-Reply-To: <5a659f60-896e-4f2f-89c0-141e530c44d5@nbd.name>
References: <20250321013829.3598-1-mingyen.hsieh@mediatek.com>
	 <20250321013829.3598-2-mingyen.hsieh@mediatek.com>
	 <5a659f60-896e-4f2f-89c0-141e530c44d5@nbd.name>
Message-ID: <2727d1a0598247fb379347165979c160a79b9965.camel@mediatek.com>

On Thu, 2025-05-22 at 12:49 +0200, Felix Fietkau wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 21.03.25 02:38, Mingyen Hsieh wrote:
> > From: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
> > 
> > Enhance the mt7925 to include RNR scan support. It adds
> > the necessary RNR information to the scan command.
> > 
> > Signed-off-by: Ming Yen Hsieh <mingyen.hsieh at mediatek.com>
> > ---
> > v2:
> > ?? - use '= {}' to replace the '= {0}' for short_ssid array.
> > ?? - align with the open paranthesis for crc32_le.
> > ?? - use ether_addr_copy() to replace the memcpy of bssid.
> > ---
> > ? .../net/wireless/mediatek/mt76/mt7925/mcu.c?? | 36
> > ++++++++++++++++---
> > ? .../net/wireless/mediatek/mt76/mt7925/mcu.h?? | 17 +++++----
> > ? 2 files changed, 41 insertions(+), 12 deletions(-)
> > 
> > diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > index 243adace8799..22686faca1af 100644
> > --- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > +++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
> > @@ -3078,7 +3079,11 @@ int mt7925_mcu_hw_scan(struct mt76_phy *phy,
> > struct ieee80211_vif *vif,
> > ????? for (i = 0; i < sreq->n_ssids; i++) {
> > ????????????? if (!sreq->ssids[i].ssid_len)
> > ????????????????????? continue;
> > +???????????? if (i > MT7925_RNR_SCAN_MAX_BSSIDS)
> > +???????????????????? break;
> > 
> > +???????????? short_ssid[i] = ~crc32_le(~0, sreq->ssids[i].ssid,
> > +?????????????????????????????????????? sreq->ssids[i].ssid_len);
> 
> I had to remove this variable due to a unused-but-set warning. I'm
> not
> sure if the contents of it should have been stored somewhere in the
> MCU
> message, or if this was something that ended up not being necessary.
> Please review and send a follow-up fix if needed.
> 
> - Felix

Hi Felix,

This variable is currently not being used. I apologize for my oversight
that caused this warning. Should i submit a v3 to remove it, or will
you help remove it?

Yen.

From nbd at nbd.name  Thu May 22 04:21:32 2025
From: nbd at nbd.name (Felix Fietkau)
Date: Thu, 22 May 2025 13:21:32 +0200
Subject: [PATCH v2 2/2] wifi: mt76: mt7925: add RNR scan support for 6GHz
In-Reply-To: <2727d1a0598247fb379347165979c160a79b9965.camel@mediatek.com>
References: <20250321013829.3598-1-mingyen.hsieh@mediatek.com>
 <20250321013829.3598-2-mingyen.hsieh@mediatek.com>
 <5a659f60-896e-4f2f-89c0-141e530c44d5@nbd.name>
 <2727d1a0598247fb379347165979c160a79b9965.camel@mediatek.com>
Message-ID: <54d0b027-b086-4ad5-a090-37faa1475182@nbd.name>

On 22.05.25 13:12, Mingyen Hsieh (???) wrote:
> Hi Felix,
> 
> This variable is currently not being used. I apologize for my oversight
> that caused this warning. Should i submit a v3 to remove it, or will
> you help remove it?

No problem, I already removed the variable in my tree.

- Felix


From horms at kernel.org  Thu May 22 05:39:13 2025
From: horms at kernel.org (Simon Horman)
Date: Thu, 22 May 2025 13:39:13 +0100
Subject: [PATCH net-next v3 4/4] net: airoha: Add the capability to
 allocate hfwd descriptors in SRAM
In-Reply-To: <20250521-airopha-desc-sram-v3-4-a6e9b085b4f0@kernel.org>
References: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
 <20250521-airopha-desc-sram-v3-4-a6e9b085b4f0@kernel.org>
Message-ID: <20250522123913.GY365796@horms.kernel.org>

On Wed, May 21, 2025 at 09:16:39AM +0200, Lorenzo Bianconi wrote:
> In order to improve packet processing and packet forwarding
> performances, EN7581 SoC supports consuming SRAM instead of DRAM for
> hw forwarding descriptors queue.
> For downlink hw accelerated traffic request to consume SRAM memory
> for hw forwarding descriptors queue.
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
> ---
>  drivers/net/ethernet/airoha/airoha_eth.c | 11 +----------
>  drivers/net/ethernet/airoha/airoha_eth.h |  9 +++++++++
>  drivers/net/ethernet/airoha/airoha_ppe.c |  6 ++++++
>  3 files changed, 16 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index 20e590d76735e72a1a538a42d2a1f49b882deccc..3cd56de716a5269b1530cff6d0ca3414d92ecb69 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -71,15 +71,6 @@ static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank,
>  	airoha_qdma_set_irqmask(irq_bank, index, mask, 0);
>  }
>  
> -static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
> -{
> -	/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
> -	 * GDM{2,3,4} can be used as wan port connected to an external
> -	 * phy module.
> -	 */
> -	return port->id == 1;
> -}
> -
>  static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
>  {
>  	struct airoha_eth *eth = port->qdma->eth;
> @@ -1128,7 +1119,7 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
>  			LMGR_INIT_START | LMGR_SRAM_MODE_MASK |
>  			HW_FWD_DESC_NUM_MASK,
>  			FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) |
> -			LMGR_INIT_START);
> +			LMGR_INIT_START | LMGR_SRAM_MODE_MASK);

Hi Lorenzo,

I'm wondering if setting the LMGR_SRAM_MODE_MASK bit (maybe a different
name for the #define would be nice) is dependent on the SRAM region
being described in DT, as per code added above this line to this
function by the previous patch in this series.

>  
>  	return read_poll_timeout(airoha_qdma_rr, status,
>  				 !(status & LMGR_INIT_START), USEC_PER_MSEC,
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
> index 3e03ae9a5d0d21c0d8d717f2a282ff06ef3b9fbf..b815697302bfdf2a6d115a9bbbbadc05462dbadb 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.h
> +++ b/drivers/net/ethernet/airoha/airoha_eth.h
> @@ -597,6 +597,15 @@ u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val);
>  #define airoha_qdma_clear(qdma, offset, val)			\
>  	airoha_rmw((qdma)->regs, (offset), (val), 0)
>  
> +static inline bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
> +{
> +	/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
> +	 * GDM{2,3,4} can be used as wan port connected to an external
> +	 * phy module.
> +	 */
> +	return port->id == 1;
> +}
> +
>  bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
>  			      struct airoha_gdm_port *port);
>  
> diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
> index 2d273937f19cf304ab4b821241fdc3ea93604f0e..12d32c92717a6b4ba74728ec02bb2e166d4d9407 100644
> --- a/drivers/net/ethernet/airoha/airoha_ppe.c
> +++ b/drivers/net/ethernet/airoha/airoha_ppe.c
> @@ -251,6 +251,12 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
>  		else
>  			pse_port = 2; /* uplink relies on GDM2 loopback */
>  		val |= FIELD_PREP(AIROHA_FOE_IB2_PSE_PORT, pse_port);
> +
> +		/* For downlink traffic consume SRAM memory for hw forwarding
> +		 * descriptors queue.
> +		 */
> +		if (airhoa_is_lan_gdm_port(port))
> +			val |= AIROHA_FOE_IB2_FAST_PATH;
>  	}
>  
>  	if (is_multicast_ether_addr(data->eth.h_dest))
> 
> -- 
> 2.49.0
> 
> 


From lorenzo at kernel.org  Thu May 22 05:58:56 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Thu, 22 May 2025 14:58:56 +0200
Subject: [PATCH net-next v3 4/4] net: airoha: Add the capability to
 allocate hfwd descriptors in SRAM
In-Reply-To: <20250522123913.GY365796@horms.kernel.org>
References: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
 <20250521-airopha-desc-sram-v3-4-a6e9b085b4f0@kernel.org>
 <20250522123913.GY365796@horms.kernel.org>
Message-ID: <aC8fkFUEmBgyT3-W@lore-desk>

> On Wed, May 21, 2025 at 09:16:39AM +0200, Lorenzo Bianconi wrote:
> > In order to improve packet processing and packet forwarding
> > performances, EN7581 SoC supports consuming SRAM instead of DRAM for
> > hw forwarding descriptors queue.
> > For downlink hw accelerated traffic request to consume SRAM memory
> > for hw forwarding descriptors queue.
> > 
> > Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
> > ---
> >  drivers/net/ethernet/airoha/airoha_eth.c | 11 +----------
> >  drivers/net/ethernet/airoha/airoha_eth.h |  9 +++++++++
> >  drivers/net/ethernet/airoha/airoha_ppe.c |  6 ++++++
> >  3 files changed, 16 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> > index 20e590d76735e72a1a538a42d2a1f49b882deccc..3cd56de716a5269b1530cff6d0ca3414d92ecb69 100644
> > --- a/drivers/net/ethernet/airoha/airoha_eth.c
> > +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> > @@ -71,15 +71,6 @@ static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank,
> >  	airoha_qdma_set_irqmask(irq_bank, index, mask, 0);
> >  }
> >  
> > -static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
> > -{
> > -	/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
> > -	 * GDM{2,3,4} can be used as wan port connected to an external
> > -	 * phy module.
> > -	 */
> > -	return port->id == 1;
> > -}
> > -
> >  static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
> >  {
> >  	struct airoha_eth *eth = port->qdma->eth;
> > @@ -1128,7 +1119,7 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
> >  			LMGR_INIT_START | LMGR_SRAM_MODE_MASK |
> >  			HW_FWD_DESC_NUM_MASK,
> >  			FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) |
> > -			LMGR_INIT_START);
> > +			LMGR_INIT_START | LMGR_SRAM_MODE_MASK);
> 
> Hi Lorenzo,

Hi Simon,

> 
> I'm wondering if setting the LMGR_SRAM_MODE_MASK bit (maybe a different
> name for the #define would be nice) is dependent on the SRAM region

I did this way because LMGR_SRAM_MODE_MASK is just a bit. Do you prefer
to do something like:

FIELD_PREP(LMGR_SRAM_MODE_MASK, 1)?

> being described in DT, as per code added above this line to this
> function by the previous patch in this series.

Are you referring to qdma0_buf/qdma1_buf memory regions?
https://patchwork.kernel.org/project/netdevbpf/patch/20250521-airopha-desc-sram-v3-1-a6e9b085b4f0 at kernel.org/

If so, they are DRAM memory-regions and not SRAM ones. They are used for
hw forwarding buffers queue. SRAM is used for hw forwarding descriptor queue.

Regards,
Lorenzo

> 
> >  
> >  	return read_poll_timeout(airoha_qdma_rr, status,
> >  				 !(status & LMGR_INIT_START), USEC_PER_MSEC,
> > diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
> > index 3e03ae9a5d0d21c0d8d717f2a282ff06ef3b9fbf..b815697302bfdf2a6d115a9bbbbadc05462dbadb 100644
> > --- a/drivers/net/ethernet/airoha/airoha_eth.h
> > +++ b/drivers/net/ethernet/airoha/airoha_eth.h
> > @@ -597,6 +597,15 @@ u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val);
> >  #define airoha_qdma_clear(qdma, offset, val)			\
> >  	airoha_rmw((qdma)->regs, (offset), (val), 0)
> >  
> > +static inline bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
> > +{
> > +	/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
> > +	 * GDM{2,3,4} can be used as wan port connected to an external
> > +	 * phy module.
> > +	 */
> > +	return port->id == 1;
> > +}
> > +
> >  bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
> >  			      struct airoha_gdm_port *port);
> >  
> > diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
> > index 2d273937f19cf304ab4b821241fdc3ea93604f0e..12d32c92717a6b4ba74728ec02bb2e166d4d9407 100644
> > --- a/drivers/net/ethernet/airoha/airoha_ppe.c
> > +++ b/drivers/net/ethernet/airoha/airoha_ppe.c
> > @@ -251,6 +251,12 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
> >  		else
> >  			pse_port = 2; /* uplink relies on GDM2 loopback */
> >  		val |= FIELD_PREP(AIROHA_FOE_IB2_PSE_PORT, pse_port);
> > +
> > +		/* For downlink traffic consume SRAM memory for hw forwarding
> > +		 * descriptors queue.
> > +		 */
> > +		if (airhoa_is_lan_gdm_port(port))
> > +			val |= AIROHA_FOE_IB2_FAST_PATH;
> >  	}
> >  
> >  	if (is_multicast_ether_addr(data->eth.h_dest))
> > 
> > -- 
> > 2.49.0
> > 
> > 
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From horms at kernel.org  Thu May 22 06:35:34 2025
From: horms at kernel.org (Simon Horman)
Date: Thu, 22 May 2025 14:35:34 +0100
Subject: [PATCH net-next v3 4/4] net: airoha: Add the capability to
 allocate hfwd descriptors in SRAM
In-Reply-To: <aC8fkFUEmBgyT3-W@lore-desk>
References: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
 <20250521-airopha-desc-sram-v3-4-a6e9b085b4f0@kernel.org>
 <20250522123913.GY365796@horms.kernel.org>
 <aC8fkFUEmBgyT3-W@lore-desk>
Message-ID: <20250522133534.GB365796@horms.kernel.org>

On Thu, May 22, 2025 at 02:58:56PM +0200, Lorenzo Bianconi wrote:
> > On Wed, May 21, 2025 at 09:16:39AM +0200, Lorenzo Bianconi wrote:
> > > In order to improve packet processing and packet forwarding
> > > performances, EN7581 SoC supports consuming SRAM instead of DRAM for
> > > hw forwarding descriptors queue.
> > > For downlink hw accelerated traffic request to consume SRAM memory
> > > for hw forwarding descriptors queue.
> > > 
> > > Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
> > > ---
> > >  drivers/net/ethernet/airoha/airoha_eth.c | 11 +----------
> > >  drivers/net/ethernet/airoha/airoha_eth.h |  9 +++++++++
> > >  drivers/net/ethernet/airoha/airoha_ppe.c |  6 ++++++
> > >  3 files changed, 16 insertions(+), 10 deletions(-)
> > > 
> > > diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> > > index 20e590d76735e72a1a538a42d2a1f49b882deccc..3cd56de716a5269b1530cff6d0ca3414d92ecb69 100644
> > > --- a/drivers/net/ethernet/airoha/airoha_eth.c
> > > +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> > > @@ -71,15 +71,6 @@ static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank,
> > >  	airoha_qdma_set_irqmask(irq_bank, index, mask, 0);
> > >  }
> > >  
> > > -static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
> > > -{
> > > -	/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
> > > -	 * GDM{2,3,4} can be used as wan port connected to an external
> > > -	 * phy module.
> > > -	 */
> > > -	return port->id == 1;
> > > -}
> > > -
> > >  static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
> > >  {
> > >  	struct airoha_eth *eth = port->qdma->eth;
> > > @@ -1128,7 +1119,7 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
> > >  			LMGR_INIT_START | LMGR_SRAM_MODE_MASK |
> > >  			HW_FWD_DESC_NUM_MASK,
> > >  			FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) |
> > > -			LMGR_INIT_START);
> > > +			LMGR_INIT_START | LMGR_SRAM_MODE_MASK);
> > 
> > Hi Lorenzo,
> 
> Hi Simon,
> 
> > 
> > I'm wondering if setting the LMGR_SRAM_MODE_MASK bit (maybe a different
> > name for the #define would be nice) is dependent on the SRAM region
> 
> I did this way because LMGR_SRAM_MODE_MASK is just a bit. Do you prefer
> to do something like:
> 
> FIELD_PREP(LMGR_SRAM_MODE_MASK, 1)?

Let's leave it as you have it in this patch :)

> 
> > being described in DT, as per code added above this line to this
> > function by the previous patch in this series.
> 
> Are you referring to qdma0_buf/qdma1_buf memory regions?
> https://patchwork.kernel.org/project/netdevbpf/patch/20250521-airopha-desc-sram-v3-1-a6e9b085b4f0 at kernel.org/
> 
> If so, they are DRAM memory-regions and not SRAM ones. They are used for
> hw forwarding buffers queue. SRAM is used for hw forwarding descriptor queue.

Yes, my mistake.

With that cleared up I think this patch looks good.

Reviewed-by: Simon Horman <horms at kernel.org>


From horms at kernel.org  Thu May 22 06:37:33 2025
From: horms at kernel.org (Simon Horman)
Date: Thu, 22 May 2025 14:37:33 +0100
Subject: [PATCH net-next v3 2/4] net: airoha: Do not store hfwd
 references in airoha_qdma struct
In-Reply-To: <20250521-airopha-desc-sram-v3-2-a6e9b085b4f0@kernel.org>
References: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
 <20250521-airopha-desc-sram-v3-2-a6e9b085b4f0@kernel.org>
Message-ID: <20250522133733.GC365796@horms.kernel.org>

On Wed, May 21, 2025 at 09:16:37AM +0200, Lorenzo Bianconi wrote:
> Since hfwd descriptor and buffer queues are allocated via
> dmam_alloc_coherent() we do not need to store their references
> in airoha_qdma struct. This patch does not introduce any logical changes,
> just code clean-up.
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>

Reviewed-by: Simon Horman <horms at kernel.org>



From horms at kernel.org  Thu May 22 06:37:50 2025
From: horms at kernel.org (Simon Horman)
Date: Thu, 22 May 2025 14:37:50 +0100
Subject: [PATCH net-next v3 3/4] net: airoha: Add the capability to
 allocate hwfd buffers via reserved-memory
In-Reply-To: <20250521-airopha-desc-sram-v3-3-a6e9b085b4f0@kernel.org>
References: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
 <20250521-airopha-desc-sram-v3-3-a6e9b085b4f0@kernel.org>
Message-ID: <20250522133750.GD365796@horms.kernel.org>

On Wed, May 21, 2025 at 09:16:38AM +0200, Lorenzo Bianconi wrote:
> In some configurations QDMA blocks require a contiguous block of
> system memory for hwfd buffers queue. Introduce the capability to allocate
> hw buffers forwarding queue via the reserved-memory DTS property instead of
> running dmam_alloc_coherent().
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>

Reviewed-by: Simon Horman <horms at kernel.org>



From mathieu.poirier at linaro.org  Thu May 22 07:47:51 2025
From: mathieu.poirier at linaro.org (Mathieu Poirier)
Date: Thu, 22 May 2025 08:47:51 -0600
Subject: [PATCH] remoteproc: mediatek: Add SCP watchdog handler in IRQ
 processing
In-Reply-To: <20250521142404.1077-1-vulab@iscas.ac.cn>
References: <20250521142404.1077-1-vulab@iscas.ac.cn>
Message-ID: <aC85F1Rua2dn_qTY@p14s>

Good day,

On Wed, May 21, 2025 at 10:24:03PM +0800, Wentao Liang wrote:
> In mt8195_scp_c1_irq_handler(), only the IPC interrupt bit
> (MT8192_SCP_IPC_INT_BIT) was checked., but does not handle
> when this bit is not set. This could lead to unhandled watchdog
> events. This could lead to unhandled watchdog events. A proper
> implementation can be found in mt8183_scp_irq_handler().
>

As pointed out by Markus, this changelog needs work.

> Add a new branch to handle SCP watchdog events when the IPC
> interrupt bit is not set.
> 
> Fixes: 6a1c9aaf04eb ("remoteproc: mediatek: Add MT8195 SCP core 1 operations")
> Cc: stable at vger.kernel.org # v6.7
> Signed-off-by: Wentao Liang <vulab at iscas.ac.cn>
> ---
>  drivers/remoteproc/mtk_scp.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c
> index 0f4a7065d0bd..316e8c98a503 100644
> --- a/drivers/remoteproc/mtk_scp.c
> +++ b/drivers/remoteproc/mtk_scp.c
> @@ -273,6 +273,8 @@ static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp)
>  
>  	if (scp_to_host & MT8192_SCP_IPC_INT_BIT)
>  		scp_ipi_handler(scp);
> +	else
> +		scp_wdt_handler(scp, scp_to_host);

I would much rather see a test for the watchdog bit than just assuming it is
a watchdog interrupt.  And while at it, please refactor the bit definition to be
platform agnostic rather than reusing 8192 definitions on an 8195 platform.

Thanks,
Mathieu

>  
>  	writel(scp_to_host, scp->cluster->reg_base + MT8195_SSHUB2APMCU_IPC_CLR);
>  }
> -- 
> 2.42.0.windows.2
> 


From mripard at kernel.org  Thu May 22 07:57:30 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Thu, 22 May 2025 16:57:30 +0200
Subject: [PATCH v3 00/22] drm: convert all bridges to
 devm_drm_bridge_alloc()
In-Reply-To: <20250521162216.79dd3290@booty>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
 <20250521162216.79dd3290@booty>
Message-ID: <20250522-amphibian-shiny-chachalaca-cf05ba@houat>

On Wed, May 21, 2025 at 04:22:16PM +0200, Luca Ceresoli wrote:
> Hello Maxime, Shawn, Liu, all,
> 
> On Fri, 09 May 2025 15:53:26 +0200
> Luca Ceresoli <luca.ceresoli at bootlin.com> wrote:
> 
> > devm_drm_bridge_alloc() [0] is the new API to allocate and initialize a DRM
> > bridge, and the only one supported from now on. It is the first milestone
> > towards removal of bridges from a still existing DRM pipeline without
> > use-after-free.
> 
> I applied on drm-misc-next patches 3-17,20-21 as they match all the
> criteria:
>  - At least a Acked-by (or R-by maintainers)
>  - patch is for drm-misc
> 
> Being my very first commits to drm-misc, I tried to be careful, and
> double checked all the patches with Louis (thanks!).
> 
> Here are the pending questions and plan for the remaining patches.
> 
> >       Revert "drm/exynos: mic: convert to devm_drm_bridge_alloc() API"
> 
> This reverts the commit applied my mistake:
> https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/91c5c7b5bb2dd09b43b025bce6d790d3c79f4518
> 
> Neither the  original patch nor the revert has been reviewed/acked.
> 
> As the commit was a mistake, I'm applying the revert by the end of this
> week (i.e. on Friday) unless there are better instructions.

Given the lack of answers, and that it looks correct to me, just leave
it there. We can always revert later on if things turned out to be
broken.

> >       drm: convert many bridge drivers from devm_kzalloc() to devm_drm_bridge_alloc() API
> 
> This patch affects multiple drivers. Running get_maintainers.pl
> points at Shawn Guo's repository. After reviewing the MAINTAINERS file,
> this looks like due to the 'N:' line in:
> 
> ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> M:	Shawn Guo <shawnguo at kernel.org>
> M:	Sascha Hauer <s.hauer at pengutronix.de>
> R:	Pengutronix Kernel Team <kernel at pengutronix.de>
> ...
> T:	git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
> N:	imx
> ...
> 
> (https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/drm-misc-next/MAINTAINERS?ref_type=heads#L2511-2528)
> 
> Here 'imx' matches the 'drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c'
> file that is touched by the patch. That regexp appears overly generic to me.

I agree, or at least, we shouldn't wait for Shawn or Sasha...

> Shawn, can it be fixed by making it less generic?
> 
> If not, can we at least add a band-aid 'X:' entry for
> drivers/gpu/drm/bridge/imx?
> 
> I think the other matching entry is the one to consider:
> 
> DRM DRIVERS FOR FREESCALE IMX BRIDGE
> M:	Liu Ying <victor.liu at nxp.com>
> L:	dri-devel at lists.freedesktop.org
> S:	Maintained
> F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
> F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
> F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
> F:	drivers/gpu/drm/bridge/imx/
> 
> (https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/drm-misc-next/MAINTAINERS?ref_type=heads#L7940-7948)

... As long as Ying is fine with it, because it does look like they are
the actual maintainer.

> However it does not list any trees. I _guess_ drm-misc applies here as
> a fallback as well as common sense.
> 
> Liu, should this entry have a 'T:' line for drm/misc?
> 
> >       drm/bridge: imx8qxp-pixel-combiner: convert to devm_drm_bridge_alloc() API
> 
> Not acked/reviewed, some discussion happened. I am resending it in v4,
> possibly with updates based on the discussion.
> 
> But it has the same issue discussed above, with get_maintiners.pl
> pointing at Shawn Guo's tree, so in the future I'm assuming this goes
> to drm-misc unless there are news about that.
> 
> >       drm/bridge: tc358767: convert to devm_drm_bridge_alloc() API
> 
> No feedback, resending in v4.
> 
> >       drm/todo: add entry to remove devm_drm_put_bridge()
> 
> This involves documentation maintained on another tree. Where should it
> be applied? There are two matching entries in MAINTAINERS:
> 
>  * DRM DRIVERS -> the drm tree
>  * DRM DRIVERS AND MISC GPU PATCHES -> the drm-misc tree
> 
> To me it looks like the second is obviously the closest match as we are
> dealing with DRM bridges, so I'm applying this as well on Friday unless
> there are better instructions.

Yes, they should be applied to drm-misc.

That being said, putting a two days timeout on *any* email is really
over-the-top. I doubt you reply to any of your mail in such a short
timeframe. We have rules for a reason, I'd expect you to follow them, no
matter how frustrating the lack of answers can be.

Maxime
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From mripard at kernel.org  Thu May 22 08:01:57 2025
From: mripard at kernel.org (Maxime Ripard)
Date: Thu, 22 May 2025 17:01:57 +0200
Subject: [PATCH v3 00/22] drm: convert all bridges to
 devm_drm_bridge_alloc()
In-Reply-To: <36ade269-a590-4243-889c-006f37d9ae6e@nxp.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
 <20250521162216.79dd3290@booty>
 <36ade269-a590-4243-889c-006f37d9ae6e@nxp.com>
Message-ID: <20250522-eager-cautious-dragon-c09cbe@houat>

On Thu, May 22, 2025 at 11:20:17AM +0800, Liu Ying wrote:
> >>       drm: convert many bridge drivers from devm_kzalloc() to devm_drm_bridge_alloc() API
> > 
> > This patch affects multiple drivers. Running get_maintainers.pl
> > points at Shawn Guo's repository. After reviewing the MAINTAINERS file,
> > this looks like due to the 'N:' line in:
> > 
> > ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> > M:	Shawn Guo <shawnguo at kernel.org>
> > M:	Sascha Hauer <s.hauer at pengutronix.de>
> > R:	Pengutronix Kernel Team <kernel at pengutronix.de>
> > ...
> > T:	git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
> > N:	imx
> > ...
> > 
> > (https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/drm-misc-next/MAINTAINERS?ref_type=heads#L2511-2528)
> > 
> > Here 'imx' matches the 'drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c'
> > file that is touched by the patch. That regexp appears overly generic to me.
> > 
> > Shawn, can it be fixed by making it less generic?
> > 
> > If not, can we at least add a band-aid 'X:' entry for
> > drivers/gpu/drm/bridge/imx?
> > 
> > I think the other matching entry is the one to consider:
> > 
> > DRM DRIVERS FOR FREESCALE IMX BRIDGE
> > M:	Liu Ying <victor.liu at nxp.com>
> > L:	dri-devel at lists.freedesktop.org
> > S:	Maintained
> > F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
> > F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
> > F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> > F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
> > F:	drivers/gpu/drm/bridge/imx/
> > 
> > (https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/drm-misc-next/MAINTAINERS?ref_type=heads#L7940-7948)
> > 
> > However it does not list any trees. I _guess_ drm-misc applies here as
> > a fallback as well as common sense.
> > 
> > Liu, should this entry have a 'T:' line for drm/misc?
> 
> These bridge drivers also don't have a 'T:' line:
> 
> DRM DRIVER FOR CHIPONE ICN6211 MIPI-DSI to RGB CONVERTER BRIDGE
> DRM DRIVER FOR PARADE PS8640 BRIDGE CHIP
> DRM DRIVER FOR TI DLPC3433 MIPI DSI TO DMD BRIDGE
> DRM DRIVER FOR TI SN65DSI86 BRIDGE CHIP
> LONTIUM LT8912B MIPI TO HDMI BRIDGE
> MEGACHIPS STDPXXXX-GE-B850V3-FW LVDS/DP++ BRIDGES
> MICROCHIP SAM9x7-COMPATIBLE LVDS CONTROLLER
> 
> I think that they fallback to drm-misc since "DRM DRIVERS FOR BRIDGE CHIPS"
> covers them.  I don't have strong opinion on adding a "T" line to them, at
> least to "DRM DRIVERS FOR FREESCALE IMX BRIDGE".  Anyway, it would be good
> to know comments from maintainers for "DRM DRIVERS FOR BRIDGE CHIPS" and
> "DRM DRIVERS".

That's good enough to me. drivers/gpu/drm/bridge is indeed under the
maintenance of drm-misc and there's no exception afaik.

get_maintainers.pl also properly reports it, so I'm not sure we need to
do anything there.

Maxime
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From nancy.lin at mediatek.com  Thu May 22 08:03:32 2025
From: nancy.lin at mediatek.com (Nancy.Lin)
Date: Thu, 22 May 2025 23:03:32 +0800
Subject: [PATCH 0/2] Add MT8196 VMM driver support
Message-ID: <20250522150426.3418225-1-nancy.lin@mediatek.com>

From: Nancy Lin <nancy.lin at mediatek.com>

Add a driver for the MediaTek MT8196 VMM (Vcore for MultiMedia)
controller.

Nancy Lin (2):
  dt-bindings: regulator: mediatek: Add MT8196 vmm controller
  soc: mediatek: Add MT8196 VMM driver support

 .../mediatek,mt8196-vmm-regulator.yaml        |  70 +++
 drivers/soc/mediatek/Kconfig                  |  12 +
 drivers/soc/mediatek/Makefile                 |   1 +
 drivers/soc/mediatek/mtk-vmm-drv.c            | 471 ++++++++++++++++++
 4 files changed, 554 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.yaml
 create mode 100644 drivers/soc/mediatek/mtk-vmm-drv.c

-- 
2.45.2



From nancy.lin at mediatek.com  Thu May 22 08:03:33 2025
From: nancy.lin at mediatek.com (Nancy.Lin)
Date: Thu, 22 May 2025 23:03:33 +0800
Subject: [PATCH 1/2] dt-bindings: regulator: mediatek: Add MT8196 vmm controller
In-Reply-To: <20250522150426.3418225-1-nancy.lin@mediatek.com>
References: <20250522150426.3418225-1-nancy.lin@mediatek.com>
Message-ID: <20250522150426.3418225-2-nancy.lin@mediatek.com>

From: Nancy Lin <nancy.lin at mediatek.com>

Add a device tree binding document for the MediaTek MT8196 VMM (Vcore
for MultiMedia) regulator controller. The VMM controller acts as the
main power supplier for multimedia power domains, such as those used
by display, video encode and decode subsystems. It provides virtual
regulators that serve as the power sources for various multimedia IPs,
and coordinates with the hardware common clock framework (hwccf) and
the Video Companion Processor (VCP) to manage the power domains of
these components. The regulator is controlled by the VCP firmware,
and the operating system signals its requirement through a voting
hardware block (hwccf).

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
---
 .../mediatek,mt8196-vmm-regulator.yaml        | 70 +++++++++++++++++++
 1 file changed, 70 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.yaml

diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.yaml
new file mode 100644
index 000000000000..a50e35c2e238
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/regulator/mediatek,mt8196-vmm-regulator.yaml#"
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT8196 VMM (Vcore for MultiMedia) Regulator Controller
+
+maintainers:
+  - Nancy Lin <nancy.lin at mediatek.com>
+
+description: |
+  The MediaTek MT8196 VMM (Vcore for Multi Media) controller acts as the
+  main power supplier for multimedia power domains, such as those used by
+  display, video encode and decode subsystems. The VMM hardware block
+  provides virtual regulators that serve as the power sources (suppliers)
+  for various multimedia IPs. It coordinates with the MediaTek hardware
+  common clock framework (HWCCF) and the Video Companion Processor (VCP)
+  to manage the power domains of these multimedia components.
+
+  Each child node under the VMM node represents a virtual regulator
+  (e.g., vdisp, vdec-vcore) and must specify a 'regulator-name'.
+
+properties:
+  compatible:
+    const: "mediatek,mt8196-vmm"
+
+  mediatek,hw-ccf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: Phandle to the hardware common clock framework syscon controller.
+
+  mediatek,vcp:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: Phandle to the Video Co-Processor (VCP) node.
+
+patternProperties:
+  "^(vdisp|vdec-vcore)$":
+    type: object
+    description: |
+      Virtual regulator for a specific multimedia domain.
+      The node name should match the supported regulator (e.g., vdisp, vdec-vcore).
+    properties:
+      regulator-name:
+        type: string
+        description: The name of the virtual regulator.
+    required:
+      - regulator-name
+    additionalProperties: false
+
+required:
+  - compatible
+  - mediatek,hw-ccf
+  - mediatek,vcp
+
+additionalProperties: false
+
+examples:
+  - |
+    vmm: vmm {
+      compatible = "mediatek,mt8196-vmm";
+      mediatek,hw-ccf = <&mm_hwv>;
+      mediatek,vcp = <&vcp>;
+
+      vdisp: vdisp {
+        regulator-name = "vdisp";
+      };
+      vdec_vcore: vdec-vcore {
+        regulator-name = "vdec-vcore";
+      };
+    };
-- 
2.45.2



From nancy.lin at mediatek.com  Thu May 22 08:03:34 2025
From: nancy.lin at mediatek.com (Nancy.Lin)
Date: Thu, 22 May 2025 23:03:34 +0800
Subject: [PATCH 2/2] soc: mediatek: Add MT8196 VMM driver support
In-Reply-To: <20250522150426.3418225-1-nancy.lin@mediatek.com>
References: <20250522150426.3418225-1-nancy.lin@mediatek.com>
Message-ID: <20250522150426.3418225-3-nancy.lin@mediatek.com>

From: Nancy Lin <nancy.lin at mediatek.com>

Add a driver for the MediaTek MT8196 VMM (Vcore for MultiMedia)
controller, which acts as the main power supplier for multimedia power
domains such as display, video encode, and video decode on MediaTek SoCs.

The VMM controller provides virtual regulators for multimedia IPs and
coordinates with the hardware common clock framework (hwccf) and the
Video Companioin Processor (VCP) to manage power domains. The driver
uses a hardware voter through HWCCF to notify the VCP to turn on or
off VMM-related bucks.

Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
---
 drivers/soc/mediatek/Kconfig       |  12 +
 drivers/soc/mediatek/Makefile      |   1 +
 drivers/soc/mediatek/mtk-vmm-drv.c | 471 +++++++++++++++++++++++++++++
 3 files changed, 484 insertions(+)
 create mode 100644 drivers/soc/mediatek/mtk-vmm-drv.c

diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index d7293977f06e..4db4a0876083 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -69,6 +69,18 @@ config MTK_MMSYS
 	  Say yes here to add support for the MediaTek Multimedia
 	  Subsystem (MMSYS).
 
+config MTK_VMM
+	tristate "MediaTek VMM driver"
+	help
+	  Say Y here to enable support for the MediaTek VMM (Vcore for
+	  MultiMedia) controller, which acts as the main power supplier
+	  for multimedia power domains such as display, video encode and
+	  decode on MediaTek SoCs. The VMM controller provides virtual
+	  regulators for multimedia IPs and coordinates with the hardware
+	  common clock framework (hwccf) and the Video Companion Processor
+	  (VCP) to manage power domains. The VMM driver uses hardware voter
+	  through hwccf to notify VCP to turn on/off VMM-related bucks.
+
 config MTK_SVS
 	tristate "MediaTek Smart Voltage Scaling(SVS)"
 	depends on NVMEM_MTK_EFUSE && NVMEM
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index 0665573e3c4b..2b2071614ac4 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
 obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
 obj-$(CONFIG_MTK_REGULATOR_COUPLER) += mtk-regulator-coupler.o
 obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
+obj-$(CONFIG_MTK_VMM) += mtk-vmm-drv.o
 obj-$(CONFIG_MTK_MMSYS) += mtk-mutex.o
 obj-$(CONFIG_MTK_SVS) += mtk-svs.o
 obj-$(CONFIG_MTK_SOCINFO) += mtk-socinfo.o
diff --git a/drivers/soc/mediatek/mtk-vmm-drv.c b/drivers/soc/mediatek/mtk-vmm-drv.c
new file mode 100644
index 000000000000..de4ceb7d59fa
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-vmm-drv.c
@@ -0,0 +1,471 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Yunfei Dong <yunfei.dong at mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/kthread.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/regulator/driver.h>
+#if IS_ENABLED(CONFIG_MTK_VCP_RPROC)
+#include <linux/remoteproc.h>
+#include <linux/remoteproc/mtk_vcp_public.h>
+#endif
+
+#define mtk_vmm_dbg(dev, fmt, args...) \
+	dev_dbg(dev, "[vmm] %s(%d): " fmt "\n", __func__, __LINE__, ##args)
+
+#define mtk_vmm_err(dev, fmt, args...) \
+	dev_err(dev, "[vmm] err %s(%d): " fmt "\n", __func__, __LINE__, ##args)
+
+/* vdisp' id=0, vdec' id=1 */
+#define HW_CCF_XPU0_BACKUP_SET(id)      (0x230 + (id) * 0x8)
+#define HW_CCF_XPU0_BACKUP_CLR(id)      (0x234 + (id) * 0x8)
+#define HW_CCF_BACKUP_ENABLE(id)        (0x1430 + (id) * 0x10)
+#define HW_CCF_BACKUP_STATUS(id)        (0x1434 + (id) * 0x10)
+#define HW_CCF_BACKUP_STATUS_DBG(id)    (0x1438 + (id) * 0x10)
+#define HW_CCF_BACKUP_DONE(id)          (0x143c + (id) * 0x10)
+#define HW_CCF_BACKUP_SET_STATUS(id)    (0x1484 + (id) * 0x8)
+#define HW_CCF_BACKUP_CLR_STATUS(id)    (0x1488 + (id) * 0x8)
+
+#define DELAY_US      (1)
+#define POLL_TIMEOUT  (10000)
+
+#define MTK_VMM_REGULAR(match, _name)                  \
+[MTK_VMM_ID_##_name] = {                               \
+	.desc = {                                      \
+		.name = match,                         \
+		.of_match = of_match_ptr(match),       \
+		.ops = &mtk_vmm_regulator_ops,         \
+		.type = REGULATOR_VOLTAGE,             \
+		.id = MTK_VMM_ID_##_name,              \
+		.owner = THIS_MODULE,                  \
+	},                                             \
+}
+
+/*
+ * enum mtk_vmm_id - mtk vmm id' information
+ *
+ * @MTK_VMM_ID_VDISP: vdisp BIT, id
+ * @MTK_VMM_ID_VDEC_VCORE: vdec BIT, id
+ * @MTK_VMM_ID_MAX: invalid id
+ */
+enum mtk_vmm_id {
+	MTK_VMM_ID_VDISP = 0,
+	MTK_VMM_ID_VDEC_VCORE,
+	MTK_VMM_ID_MAX
+};
+
+/*
+ * struct mtk_vmm_drv - mtk vmm driver' information
+ *
+ * @vcp_device: vcp device
+ * @vcp_nb: vcp notifier block
+ * @hwccf_regmap: hardware common clock framework register map
+ * @dev: vmm device
+ * @kthr_vcp: vcp task thread
+ * @vcp_phandle: vcp handle
+ * @vcp_is_active: vcp active status
+ * @need_update: vcore regulator enable and disable
+ * @disable_status: disable status.
+ */
+struct mtk_vmm_drv {
+	struct mtk_vcp_device  *vcp_device;
+	struct notifier_block  vcp_nb;
+	struct regmap          *hwccf_regmap;
+	/* lock for hwccf control */
+	struct mutex           ctrl_mutex[MTK_VMM_ID_MAX];
+	struct device          *dev;
+	struct task_struct     *kthr_vcp;
+	phandle                vcp_phandle;
+	bool                   vcp_is_active;
+	bool                   need_update[MTK_VMM_ID_MAX];
+	bool                   disable_status[MTK_VMM_ID_MAX];
+};
+
+/*
+ * struct mtk_vmm_regulator - mtk vmm regulators' information
+ *
+ * @desc: standard fields of regulator description.
+ */
+struct mtk_vmm_regulator {
+	struct regulator_desc	desc;
+};
+
+/*
+ * struct mtk_vmm_regulator_init_data - mtk vmm regulators' init data
+ *
+ * @size: num of regulators
+ * @regulator_info: regulator info.
+ */
+struct mtk_vmm_regulator_init_data {
+	u32 size;
+	struct mtk_vmm_regulator *regulator_info;
+};
+
+static void mtk_vmm_debug_dump(struct mtk_vmm_drv *vmm_drv, int line, int id)
+{
+	u32 value0, value1, value2, value3, value4, value5, value6, value7;
+	u32 ccf_set;
+	u32 ccf_clr;
+	u32 ccf_enable;
+	u32 ccf_status;
+	u32 ccf_status_dbg;
+	u32 ccf_done;
+	u32 ccf_set_status;
+	u32 ccf_clr_status;
+
+	ccf_set = HW_CCF_XPU0_BACKUP_SET(id);
+	ccf_clr = HW_CCF_XPU0_BACKUP_CLR(id);
+	ccf_enable = HW_CCF_BACKUP_ENABLE(id);
+	ccf_status = HW_CCF_BACKUP_STATUS(id);
+	ccf_status_dbg = HW_CCF_BACKUP_STATUS_DBG(id);
+	ccf_done = HW_CCF_BACKUP_DONE(id);
+	ccf_set_status = HW_CCF_BACKUP_SET_STATUS(id);
+	ccf_clr_status = HW_CCF_BACKUP_CLR_STATUS(id);
+
+	regmap_read(vmm_drv->hwccf_regmap, ccf_set, &value0);
+	regmap_read(vmm_drv->hwccf_regmap, ccf_clr, &value1);
+	regmap_read(vmm_drv->hwccf_regmap, ccf_enable, &value2);
+	regmap_read(vmm_drv->hwccf_regmap, ccf_status, &value3);
+	regmap_read(vmm_drv->hwccf_regmap, ccf_status_dbg, &value4);
+	regmap_read(vmm_drv->hwccf_regmap, ccf_done, &value5);
+	regmap_read(vmm_drv->hwccf_regmap, ccf_set_status, &value6);
+	regmap_read(vmm_drv->hwccf_regmap, ccf_clr_status, &value7);
+
+	mtk_vmm_err(vmm_drv->dev, "id:%d %d: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+		    id, line, value0, value1, value2,
+		    value3, value4, value5, value6, value7);
+}
+
+static int mtk_vmm_hwccf_ctrl(struct mtk_vmm_drv *vmm_drv, bool enable, int id)
+{
+	u32 ctrl_reg;
+	u32 hwccf_ctrl_status;
+	u32 hwccf_done;
+	u32 bit_val;
+	int tmp, ret = 0;
+
+	if (IS_ERR_OR_NULL(vmm_drv->hwccf_regmap)) {
+		mtk_vmm_err(vmm_drv->dev, "hwccf_reg_base is null, need to map first.");
+		return -ENODEV;
+	}
+
+	if (!vmm_drv->vcp_is_active) {
+		vmm_drv->need_update[id] = true;
+		vmm_drv->disable_status[id] = !enable;
+		goto ctrl_end;
+	}
+
+	ctrl_reg = enable ? HW_CCF_XPU0_BACKUP_SET(id) : HW_CCF_XPU0_BACKUP_CLR(id);
+	hwccf_ctrl_status = enable ? HW_CCF_BACKUP_SET_STATUS(id) : HW_CCF_BACKUP_CLR_STATUS(id);
+	hwccf_done = HW_CCF_BACKUP_DONE(id);
+	bit_val = BIT(id);
+
+	/* polling hwccf write data done */
+	ret = regmap_read_poll_timeout(vmm_drv->hwccf_regmap, hwccf_done, tmp,
+				       ((tmp & bit_val) == bit_val), DELAY_US, POLL_TIMEOUT);
+	if (ret < 0) {
+		mtk_vmm_debug_dump(vmm_drv, __LINE__, id);
+		goto ctrl_end;
+	}
+
+	/* set and clr data */
+	ret = regmap_write(vmm_drv->hwccf_regmap, ctrl_reg, bit_val);
+	if (ret) {
+		mtk_vmm_debug_dump(vmm_drv, __LINE__, id);
+		goto ctrl_end;
+	}
+
+	/* polling hwccf write data done */
+	ret = regmap_read_poll_timeout(vmm_drv->hwccf_regmap, hwccf_done, tmp,
+				       ((tmp & bit_val) == bit_val), DELAY_US, POLL_TIMEOUT);
+	if (ret < 0) {
+		mtk_vmm_debug_dump(vmm_drv, __LINE__, id);
+		goto ctrl_end;
+	}
+
+	/* wait for current done */
+	ret = regmap_read_poll_timeout(vmm_drv->hwccf_regmap, hwccf_ctrl_status, tmp,
+				       !(tmp & bit_val), DELAY_US, POLL_TIMEOUT);
+	if (ret < 0) {
+		mtk_vmm_debug_dump(vmm_drv, __LINE__, id);
+		goto ctrl_end;
+	}
+ctrl_end:
+
+	return ret;
+}
+
+static int mtk_vmm_is_enabled(struct regulator_dev *rdev)
+{
+	u32 hwccf_enable;
+	u32 bit_val;
+	struct mtk_vmm_drv *vmm_drv = rdev_get_drvdata(rdev);
+	int ret = 0;
+	u32 val;
+	int id = rdev->desc->id;
+
+	if (id >= MTK_VMM_ID_MAX) {
+		mtk_vmm_err(vmm_drv->dev, "desc id is error %d\n", __LINE__);
+		goto ctrl_end;
+	}
+
+	hwccf_enable = HW_CCF_BACKUP_ENABLE(id);
+	bit_val = BIT(id);
+
+	ret = regmap_read(vmm_drv->hwccf_regmap, hwccf_enable, &val);
+	if (ret < 0)
+		mtk_vmm_err(vmm_drv->dev, "vmm id:%d read buck status failed\n", id);
+	else
+		ret = !!(val & bit_val);
+ctrl_end:
+
+	return ret;
+}
+
+static int mtk_vmm_enable(struct regulator_dev *rdev)
+{
+	struct mtk_vmm_drv *vmm_drv = rdev_get_drvdata(rdev);
+	int ret;
+	int id = rdev->desc->id;
+
+	mtk_vmm_dbg(vmm_drv->dev, "id:%d enable vmm driver %d",
+		    id, vmm_drv->vcp_is_active);
+	if (id >= MTK_VMM_ID_MAX) {
+		mtk_vmm_err(vmm_drv->dev, "desc id is error %d\n", __LINE__);
+		return -ENODEV;
+	}
+
+	mutex_lock(&vmm_drv->ctrl_mutex[id]);
+	ret = mtk_vmm_hwccf_ctrl(vmm_drv, true, id);
+	if (ret < 0)
+		mtk_vmm_err(vmm_drv->dev, "failed to enable hwccf, ret=%d\n", ret);
+	mutex_unlock(&vmm_drv->ctrl_mutex[id]);
+
+	return ret;
+}
+
+static int mtk_vmm_disable(struct regulator_dev *rdev)
+{
+	struct mtk_vmm_drv *vmm_drv = rdev_get_drvdata(rdev);
+	int ret = 0;
+	int id = rdev->desc->id;
+
+	mtk_vmm_dbg(vmm_drv->dev, "id:%d disable vmm driver %d",
+		    id, vmm_drv->vcp_is_active);
+	if (id >= MTK_VMM_ID_MAX) {
+		mtk_vmm_err(vmm_drv->dev, "desc id is error %d\n", __LINE__);
+		return -ENODEV;
+	}
+
+	mutex_lock(&vmm_drv->ctrl_mutex[id]);
+	ret = mtk_vmm_hwccf_ctrl(vmm_drv, false, id);
+	if (ret < 0)
+		mtk_vmm_err(vmm_drv->dev, "failed to disable hwccf, ret=%d\n", ret);
+	mutex_unlock(&vmm_drv->ctrl_mutex[id]);
+
+	return ret;
+}
+
+#if IS_ENABLED(CONFIG_MTK_VCP_RPROC)
+static int vmm_vcp_notifier(struct notifier_block *nb, unsigned long vcp_event, void *unused)
+{
+	struct mtk_vmm_drv *vmm_drv = container_of(nb, struct mtk_vmm_drv, vcp_nb);
+	int ret = NOTIFY_DONE;
+	int id;
+
+	switch (vcp_event) {
+	case VCP_EVENT_SUSPEND:
+	case VCP_EVENT_STOP:
+		mtk_vmm_dbg(vmm_drv->dev, "vcp notifier suspend");
+		break;
+	case VCP_EVENT_READY:
+	case VCP_EVENT_RESUME:
+		for (id = MTK_VMM_ID_VDISP; id < MTK_VMM_ID_MAX; id++) {
+			mutex_lock(&vmm_drv->ctrl_mutex[id]);
+			if (vmm_drv->need_update[id]) {
+				ret = mtk_vmm_hwccf_ctrl(vmm_drv, true, id);
+				if (ret < 0)
+					mtk_vmm_err(vmm_drv->dev,
+						    "failed to enable hwccf %d\n", ret);
+
+				if (vmm_drv->disable_status[id]) {
+					ret = mtk_vmm_hwccf_ctrl(vmm_drv, false, id);
+					if (ret < 0)
+						mtk_vmm_err(vmm_drv->dev,
+							    "failed to disable hwccf %d\n",
+							    ret);
+					vmm_drv->disable_status[id] = false;
+				}
+
+				vmm_drv->need_update[id] = false;
+			}
+			mutex_unlock(&vmm_drv->ctrl_mutex[id]);
+		}
+
+		mtk_vmm_dbg(vmm_drv->dev, "vcp notifier ready");
+		break;
+	}
+
+	return ret;
+}
+
+static int mtk_vmm_vcp_init_thread(void *arg)
+{
+	struct mtk_vmm_drv *vmm_drv = arg;
+	struct device *dev = vmm_drv->dev;
+	struct device_link *dev_link;
+	int retry = 0, retry_cnt = 10000;
+
+	while (request_module("mtk-vcp")) {
+		if (++retry > retry_cnt) {
+			mtk_vmm_err(vmm_drv->dev, "failed to load mtk-vcp module");
+			return -ENODEV;
+		}
+		ssleep(1);
+	}
+
+	if (of_property_read_u32(dev->of_node, "mediatek,vcp", &vmm_drv->vcp_phandle)) {
+		mtk_vmm_err(vmm_drv->dev, "can't get vcp handle.\n");
+		return -ENODEV;
+	}
+
+	vmm_drv->vcp_device = mtk_vcp_get_by_phandle(vmm_drv->vcp_phandle);
+	while (!vmm_drv->vcp_device) {
+		mtk_vmm_err(vmm_drv->dev, "get vcp device failed\n");
+		return -ENODEV;
+	}
+
+	dev_link = device_link_add(vmm_drv->dev, vmm_drv->vcp_device->dev, 0);
+	if (!dev_link) {
+		mtk_vmm_err(vmm_drv->dev, "device link is NULL\n");
+		return -EINVAL;
+	}
+
+	retry = 0;
+	retry_cnt = 10000;
+	while (!vmm_drv->vcp_device->data->vcp_is_ready(MMDVFS_MMUP_FEATURE_ID) ||
+	       !vmm_drv->vcp_device->data->vcp_is_ready(MMDVFS_VCP_FEATURE_ID)) {
+		if (++retry > retry_cnt) {
+			mtk_vmm_err(vmm_drv->dev, "vcp and mmup is not ready yet.");
+			return -ETIMEDOUT;
+		}
+		ssleep(1);
+	}
+
+	vmm_drv->vcp_is_active = true;
+	vmm_drv->vcp_device->data->vcp_register_feature(vmm_drv->vcp_device, VMM_FEATURE_ID);
+
+	vmm_drv->vcp_nb.notifier_call = vmm_vcp_notifier;
+	vmm_drv->vcp_device->data->vcp_register_notify(VMM_FEATURE_ID, &vmm_drv->vcp_nb);
+
+	return 0;
+}
+#endif
+
+static const struct regulator_ops mtk_vmm_regulator_ops = {
+	.enable = mtk_vmm_enable,
+	.disable = mtk_vmm_disable,
+	.is_enabled = mtk_vmm_is_enabled,
+};
+
+static struct mtk_vmm_regulator mt8196_vmm_regulators[] = {
+	MTK_VMM_REGULAR("vdisp", VDISP),
+	MTK_VMM_REGULAR("vdec-vcore", VDEC_VCORE),
+};
+
+static const struct mtk_vmm_regulator_init_data mt8196_regulator_data = {
+	.size = ARRAY_SIZE(mt8196_vmm_regulators),
+	.regulator_info = mt8196_vmm_regulators,
+};
+
+static const struct of_device_id of_vmm_match_tbl[] = {
+	{
+		.compatible = "mediatek,mt8196-vmm",
+		.data = &mt8196_regulator_data,
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, of_vmm_match_tbl);
+
+static int mtk_vmm_probe(struct platform_device *pdev)
+{
+	struct regulator_config config = { };
+	struct regulator_dev *rdev;
+	const struct mtk_vmm_regulator_init_data *regulator_init_data;
+	struct mtk_vmm_regulator *mtk_regulators;
+	struct mtk_vmm_drv *vmm_drv;
+	int i;
+
+	vmm_drv = devm_kzalloc(&pdev->dev, sizeof(*vmm_drv), GFP_KERNEL);
+	if (!vmm_drv)
+		return -ENOMEM;
+
+	vmm_drv->dev = &pdev->dev;
+	for (i = MTK_VMM_ID_VDISP; i < MTK_VMM_ID_MAX; i++)
+		mutex_init(&vmm_drv->ctrl_mutex[i]);
+
+	platform_set_drvdata(pdev, vmm_drv);
+
+	vmm_drv->hwccf_regmap =
+		syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "mediatek,hw-ccf");
+	if (IS_ERR(vmm_drv->hwccf_regmap))
+		return dev_err_probe(&pdev->dev, PTR_ERR(vmm_drv->hwccf_regmap),
+				     "cannot find hwccf controller.\n");
+
+	regulator_init_data = of_device_get_match_data(&pdev->dev);
+
+	mtk_regulators = regulator_init_data->regulator_info;
+	for (i = 0; i < regulator_init_data->size; i++) {
+		config.dev = &pdev->dev;
+		config.driver_data = vmm_drv;
+		rdev = devm_regulator_register(&pdev->dev, &(mtk_regulators + i)->desc, &config);
+		if (IS_ERR(rdev)) {
+			dev_err(&pdev->dev, "failed to register %d\n", i);
+			return PTR_ERR(rdev);
+		}
+	}
+
+#if IS_ENABLED(CONFIG_MTK_VCP_RPROC)
+	vmm_drv->kthr_vcp = kthread_run(mtk_vmm_vcp_init_thread, vmm_drv, "vmm-vcp");
+	if (IS_ERR(vmm_drv->kthr_vcp))
+		dev_err(&pdev->dev, "create kthread failed");
+#endif
+
+	mtk_vmm_dbg(&pdev->dev, "vmm prob done.");
+	return 0;
+}
+
+static void mtk_vmm_remove(struct platform_device *pdev)
+{
+#if IS_ENABLED(CONFIG_MTK_VCP_RPROC)
+	struct mtk_vmm_drv *vmm_drv = dev_get_drvdata(&pdev->dev);
+	struct mtk_vcp_device *vcp_device = vmm_drv->vcp_device;
+
+	vcp_device->data->vcp_deregister_feature(vcp_device, VMM_FEATURE_ID);
+	device_link_remove(vmm_drv->dev, vcp_device->dev);
+#endif
+}
+
+static struct platform_driver mtk_vmm_plat_drv = {
+	.probe = mtk_vmm_probe,
+	.remove = mtk_vmm_remove,
+	.driver = {
+		.name = "mtk-vmm-drv",
+		.of_match_table = of_vmm_match_tbl,
+	},
+};
+module_platform_driver(mtk_vmm_plat_drv);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MediaTek vmm driver");
-- 
2.45.2



From krzk at kernel.org  Thu May 22 08:09:19 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Thu, 22 May 2025 17:09:19 +0200
Subject: [PATCH 1/2] dt-bindings: regulator: mediatek: Add MT8196 vmm
 controller
In-Reply-To: <20250522150426.3418225-2-nancy.lin@mediatek.com>
References: <20250522150426.3418225-1-nancy.lin@mediatek.com>
 <20250522150426.3418225-2-nancy.lin@mediatek.com>
Message-ID: <d21e1775-d5d4-4f58-865e-0cb33d14f371@kernel.org>

On 22/05/2025 17:03, Nancy.Lin wrote:
> From: Nancy Lin <nancy.lin at mediatek.com>
> 
> Add a device tree binding document for the MediaTek MT8196 VMM (Vcore
> for MultiMedia) regulator controller. The VMM controller acts as the
> main power supplier for multimedia power domains, such as those used
> by display, video encode and decode subsystems. It provides virtual
> regulators that serve as the power sources for various multimedia IPs,

Virtual regulators do not sound real, so feels like you want some sort
of power domains?

A nit, subject: drop second/last, redundant "bindings". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18

> and coordinates with the hardware common clock framework (hwccf) and
> the Video Companion Processor (VCP) to manage the power domains of
> these components. The regulator is controlled by the VCP firmware,
> and the operating system signals its requirement through a voting
> hardware block (hwccf).
> 
> Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
> ---
>  .../mediatek,mt8196-vmm-regulator.yaml        | 70 +++++++++++++++++++
>  1 file changed, 70 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.yaml
> 
> diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.yaml
> new file mode 100644
> index 000000000000..a50e35c2e238
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/regulator/mediatek,mt8196-vmm-regulator.yaml#"
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MT8196 VMM (Vcore for MultiMedia) Regulator Controller
> +
> +maintainers:
> +  - Nancy Lin <nancy.lin at mediatek.com>
> +
> +description: |
> +  The MediaTek MT8196 VMM (Vcore for Multi Media) controller acts as the
> +  main power supplier for multimedia power domains, such as those used by
> +  display, video encode and decode subsystems. The VMM hardware block
> +  provides virtual regulators that serve as the power sources (suppliers)
> +  for various multimedia IPs. It coordinates with the MediaTek hardware
> +  common clock framework (HWCCF) and the Video Companion Processor (VCP)
> +  to manage the power domains of these multimedia components.
> +
> +  Each child node under the VMM node represents a virtual regulator
> +  (e.g., vdisp, vdec-vcore) and must specify a 'regulator-name'.
> +
> +properties:
> +  compatible:
> +    const: "mediatek,mt8196-vmm"

Not tested...

> +
> +  mediatek,hw-ccf:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: Phandle to the hardware common clock framework syscon controller.

No, you cannot express clocks with syscon.

> +
> +  mediatek,vcp:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: Phandle to the Video Co-Processor (VCP) node.

For what purpose?

> +
> +patternProperties:
> +  "^(vdisp|vdec-vcore)$":

Redundant nodes, useless. Drop these completely.


> +    type: object
> +    description: |
> +      Virtual regulator for a specific multimedia domain.
> +      The node name should match the supported regulator (e.g., vdisp, vdec-vcore).
> +    properties:
> +      regulator-name:

No, you cannot start redefining properties. This binding is nowhere
close to hardware description. Looks like some copy-paste downstream
driver, so binding to fulfill driver needs.

Please rework to match hardware. I suggest reaching internally to get
some help how upstream drivers and bindings look like *prior* sending
downstream code.

Best regards,
Krzysztof


From krzk at kernel.org  Thu May 22 08:10:56 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Thu, 22 May 2025 17:10:56 +0200
Subject: [PATCH 2/2] soc: mediatek: Add MT8196 VMM driver support
In-Reply-To: <20250522150426.3418225-3-nancy.lin@mediatek.com>
References: <20250522150426.3418225-1-nancy.lin@mediatek.com>
 <20250522150426.3418225-3-nancy.lin@mediatek.com>
Message-ID: <ea79d8fd-8134-4d14-92f6-f656be20cd9f@kernel.org>

On 22/05/2025 17:03, Nancy.Lin wrote:
> From: Nancy Lin <nancy.lin at mediatek.com>
> 
> Add a driver for the MediaTek MT8196 VMM (Vcore for MultiMedia)
> controller, which acts as the main power supplier for multimedia power
> domains such as display, video encode, and video decode on MediaTek SoCs.
> 
> The VMM controller provides virtual regulators for multimedia IPs and
> coordinates with the hardware common clock framework (hwccf) and the
> Video Companioin Processor (VCP) to manage power domains. The driver
> uses a hardware voter through HWCCF to notify the VCP to turn on or
> off VMM-related bucks.
> 
> Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
> ---
>  drivers/soc/mediatek/Kconfig       |  12 +
>  drivers/soc/mediatek/Makefile      |   1 +
>  drivers/soc/mediatek/mtk-vmm-drv.c | 471 +++++++++++++++++++++++++++++
>  3 files changed, 484 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mtk-vmm-drv.c
> 
> diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> index d7293977f06e..4db4a0876083 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -69,6 +69,18 @@ config MTK_MMSYS
>  	  Say yes here to add support for the MediaTek Multimedia
>  	  Subsystem (MMSYS).
>  
> +config MTK_VMM
> +	tristate "MediaTek VMM driver"
> +	help
> +	  Say Y here to enable support for the MediaTek VMM (Vcore for
> +	  MultiMedia) controller, which acts as the main power supplier
> +	  for multimedia power domains such as display, video encode and
> +	  decode on MediaTek SoCs. The VMM controller provides virtual
> +	  regulators for multimedia IPs and coordinates with the hardware
> +	  common clock framework (hwccf) and the Video Companion Processor
> +	  (VCP) to manage power domains. The VMM driver uses hardware voter
> +	  through hwccf to notify VCP to turn on/off VMM-related bucks.
> +
>  config MTK_SVS
>  	tristate "MediaTek Smart Voltage Scaling(SVS)"
>  	depends on NVMEM_MTK_EFUSE && NVMEM
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index 0665573e3c4b..2b2071614ac4 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
>  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
>  obj-$(CONFIG_MTK_REGULATOR_COUPLER) += mtk-regulator-coupler.o
>  obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> +obj-$(CONFIG_MTK_VMM) += mtk-vmm-drv.o
>  obj-$(CONFIG_MTK_MMSYS) += mtk-mutex.o
>  obj-$(CONFIG_MTK_SVS) += mtk-svs.o
>  obj-$(CONFIG_MTK_SOCINFO) += mtk-socinfo.o
> diff --git a/drivers/soc/mediatek/mtk-vmm-drv.c b/drivers/soc/mediatek/mtk-vmm-drv.c
> new file mode 100644
> index 000000000000..de4ceb7d59fa
> --- /dev/null
> +++ b/drivers/soc/mediatek/mtk-vmm-drv.c
> @@ -0,0 +1,471 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2025 MediaTek Inc.
> + * Author: Yunfei Dong <yunfei.dong at mediatek.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/kthread.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/driver.h>
> +#if IS_ENABLED(CONFIG_MTK_VCP_RPROC)

And that's the proof you send some sort of downstream code.

This does not exist.

> +#include <linux/remoteproc.h>
> +#include <linux/remoteproc/mtk_vcp_public.h>
> +#endif
> +
> +#define mtk_vmm_dbg(dev, fmt, args...) \
> +	dev_dbg(dev, "[vmm] %s(%d): " fmt "\n", __func__, __LINE__, ##args)

No, you do not get your own debug code.

NAK.

This is nowhere close to upstream code. Don't send us downstream
patterns please.

Best regards,
Krzysztof


From daeinki at gmail.com  Thu May 22 08:11:24 2025
From: daeinki at gmail.com (Inki Dae)
Date: Fri, 23 May 2025 00:11:24 +0900
Subject: [PATCH v3 00/22] drm: convert all bridges to devm_drm_bridge_alloc()
In-Reply-To: <20250521162216.79dd3290@booty>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
 <20250521162216.79dd3290@booty>
Message-ID: <CAAQKjZPX3iQgNhEydDZXMyC9BRuep7kL-XYEsjnkCxSt_1UsQg@mail.gmail.com>

Hello Luca Ceresoli,

2025? 5? 21? (?) ?? 11:23, Luca Ceresoli <luca.ceresoli at bootlin.com>?? ??:
>
> Hello Maxime, Shawn, Liu, all,
>
> On Fri, 09 May 2025 15:53:26 +0200
> Luca Ceresoli <luca.ceresoli at bootlin.com> wrote:
>
> > devm_drm_bridge_alloc() [0] is the new API to allocate and initialize a DRM
> > bridge, and the only one supported from now on. It is the first milestone
> > towards removal of bridges from a still existing DRM pipeline without
> > use-after-free.
>
> I applied on drm-misc-next patches 3-17,20-21 as they match all the
> criteria:
>  - At least a Acked-by (or R-by maintainers)
>  - patch is for drm-misc
>
> Being my very first commits to drm-misc, I tried to be careful, and
> double checked all the patches with Louis (thanks!).
>
> Here are the pending questions and plan for the remaining patches.
>
> >       Revert "drm/exynos: mic: convert to devm_drm_bridge_alloc() API"
>
> This reverts the commit applied my mistake:
> https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/91c5c7b5bb2dd09b43b025bce6d790d3c79f4518
>
> Neither the  original patch nor the revert has been reviewed/acked.
>
> As the commit was a mistake, I'm applying the revert by the end of this
> week (i.e. on Friday) unless there are better instructions.

Really sorry for late. I was made aware of it later through a
colleague's remark. There is no need to proceed with the revert.
Acked-by : Inki Dae <inki.dae at samsung.com>

Thanks,
Inki Dae


>
> >       drm: convert many bridge drivers from devm_kzalloc() to devm_drm_bridge_alloc() API
>
> This patch affects multiple drivers. Running get_maintainers.pl
> points at Shawn Guo's repository. After reviewing the MAINTAINERS file,
> this looks like due to the 'N:' line in:
>
> ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> M:      Shawn Guo <shawnguo at kernel.org>
> M:      Sascha Hauer <s.hauer at pengutronix.de>
> R:      Pengutronix Kernel Team <kernel at pengutronix.de>
> ...
> T:      git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
> N:      imx
> ...
>
> (https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/drm-misc-next/MAINTAINERS?ref_type=heads#L2511-2528)
>
> Here 'imx' matches the 'drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c'
> file that is touched by the patch. That regexp appears overly generic to me.
>
> Shawn, can it be fixed by making it less generic?
>
> If not, can we at least add a band-aid 'X:' entry for
> drivers/gpu/drm/bridge/imx?
>
> I think the other matching entry is the one to consider:
>
> DRM DRIVERS FOR FREESCALE IMX BRIDGE
> M:      Liu Ying <victor.liu at nxp.com>
> L:      dri-devel at lists.freedesktop.org
> S:      Maintained
> F:      Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
> F:      Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
> F:      Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> F:      Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
> F:      drivers/gpu/drm/bridge/imx/
>
> (https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/drm-misc-next/MAINTAINERS?ref_type=heads#L7940-7948)
>
> However it does not list any trees. I _guess_ drm-misc applies here as
> a fallback as well as common sense.
>
> Liu, should this entry have a 'T:' line for drm/misc?
>
> >       drm/bridge: imx8qxp-pixel-combiner: convert to devm_drm_bridge_alloc() API
>
> Not acked/reviewed, some discussion happened. I am resending it in v4,
> possibly with updates based on the discussion.
>
> But it has the same issue discussed above, with get_maintiners.pl
> pointing at Shawn Guo's tree, so in the future I'm assuming this goes
> to drm-misc unless there are news about that.
>
> >       drm/bridge: tc358767: convert to devm_drm_bridge_alloc() API
>
> No feedback, resending in v4.
>
> >       drm/todo: add entry to remove devm_drm_put_bridge()
>
> This involves documentation maintained on another tree. Where should it
> be applied? There are two matching entries in MAINTAINERS:
>
>  * DRM DRIVERS -> the drm tree
>  * DRM DRIVERS AND MISC GPU PATCHES -> the drm-misc tree
>
> To me it looks like the second is obviously the closest match as we are
> dealing with DRM bridges, so I'm applying this as well on Friday unless
> there are better instructions.
>
> Best regards,
> Luca
>
> --
> Luca Ceresoli, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
>


From krzk at kernel.org  Thu May 22 08:18:50 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Thu, 22 May 2025 17:18:50 +0200
Subject: [PATCH 1/2] dt-bindings: regulator: mediatek: Add MT8196 vmm
 controller
In-Reply-To: <d21e1775-d5d4-4f58-865e-0cb33d14f371@kernel.org>
References: <20250522150426.3418225-1-nancy.lin@mediatek.com>
 <20250522150426.3418225-2-nancy.lin@mediatek.com>
 <d21e1775-d5d4-4f58-865e-0cb33d14f371@kernel.org>
Message-ID: <42a7222b-43be-490a-95ed-fb506c55fbcb@kernel.org>

On 22/05/2025 17:09, Krzysztof Kozlowski wrote:
> On 22/05/2025 17:03, Nancy.Lin wrote:
>> From: Nancy Lin <nancy.lin at mediatek.com>
>>
>> Add a device tree binding document for the MediaTek MT8196 VMM (Vcore
>> for MultiMedia) regulator controller. The VMM controller acts as the
>> main power supplier for multimedia power domains, such as those used
>> by display, video encode and decode subsystems. It provides virtual
>> regulators that serve as the power sources for various multimedia IPs,
> 
> Virtual regulators do not sound real, so feels like you want some sort
> of power domains?
> 
> A nit, subject: drop second/last, redundant "bindings". The
> "dt-bindings" prefix is already stating that these are bindings.
> See also:
> https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
Wrong keyword... Please fix the subject prefixes:

For bindings, the preferred subjects are explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters

Best regards,
Krzysztof


From luca.ceresoli at bootlin.com  Thu May 22 08:56:23 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Thu, 22 May 2025 17:56:23 +0200
Subject: [PATCH v3 00/22] drm: convert all bridges to
 devm_drm_bridge_alloc()
In-Reply-To: <20250522-amphibian-shiny-chachalaca-cf05ba@houat>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
	<20250521162216.79dd3290@booty>
	<20250522-amphibian-shiny-chachalaca-cf05ba@houat>
Message-ID: <20250522175623.1a6d9b14@booty>

Hi Maxime,

On Thu, 22 May 2025 16:57:30 +0200
Maxime Ripard <mripard at kernel.org> wrote:

[...]

> > As the commit was a mistake, I'm applying the revert by the end of this
> > week (i.e. on Friday) unless there are better instructions.  
> 
> Given the lack of answers, and that it looks correct to me, just leave
> it there. We can always revert later on if things turned out to be
> broken.

OK, I'll leave the commit and drop the revert in v4.

> > >       drm: convert many bridge drivers from devm_kzalloc() to devm_drm_bridge_alloc() API  
> > 
> > This patch affects multiple drivers. Running get_maintainers.pl
> > points at Shawn Guo's repository. After reviewing the MAINTAINERS file,
> > this looks like due to the 'N:' line in:
> > 
> > ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> > M:	Shawn Guo <shawnguo at kernel.org>
> > M:	Sascha Hauer <s.hauer at pengutronix.de>
> > R:	Pengutronix Kernel Team <kernel at pengutronix.de>
> > ...
> > T:	git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
> > N:	imx
> > ...
> > 
> > (https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/drm-misc-next/MAINTAINERS?ref_type=heads#L2511-2528)
> > 
> > Here 'imx' matches the 'drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c'
> > file that is touched by the patch. That regexp appears overly generic to me.  
> 
> I agree, or at least, we shouldn't wait for Shawn or Sasha...
> 
> > Shawn, can it be fixed by making it less generic?
> > 
> > If not, can we at least add a band-aid 'X:' entry for
> > drivers/gpu/drm/bridge/imx?
> > 
> > I think the other matching entry is the one to consider:
> > 
> > DRM DRIVERS FOR FREESCALE IMX BRIDGE
> > M:	Liu Ying <victor.liu at nxp.com>
> > L:	dri-devel at lists.freedesktop.org
> > S:	Maintained
> > F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
> > F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
> > F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> > F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
> > F:	drivers/gpu/drm/bridge/imx/
> > 
> > (https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/drm-misc-next/MAINTAINERS?ref_type=heads#L7940-7948)  
> 
> ... As long as Ying is fine with it, because it does look like they are
> the actual maintainer.

Ack, thanks for confirming this.

Bottom line, given that large patch has your Acked-by, and given the
shawnguo repo was ruled out, the conclusion is it can apply it to
drm-misc-next.

Having that large patch applied will be relieving me a lot! I think
next time I'm going to split any imilar change in per-driver patches,
even if it is spatch-automated.

> > >       drm/todo: add entry to remove devm_drm_put_bridge()  
> > 
> > This involves documentation maintained on another tree. Where should it
> > be applied? There are two matching entries in MAINTAINERS:
> > 
> >  * DRM DRIVERS -> the drm tree
> >  * DRM DRIVERS AND MISC GPU PATCHES -> the drm-misc tree
> > 
> > To me it looks like the second is obviously the closest match as we are
> > dealing with DRM bridges, so I'm applying this as well on Friday unless
> > there are better instructions.  
> 
> Yes, they should be applied to drm-misc.

OK, will do soon.

> That being said, putting a two days timeout on *any* email is really
> over-the-top. I doubt you reply to any of your mail in such a short
> timeframe. We have rules for a reason, I'd expect you to follow them, no
> matter how frustrating the lack of answers can be.

Apologies if that was too much.

I was indeed nervous about the revert. A patch got applied by mistake
and I believe it should have been reverted very quickly, if need be.
Both Louis and I didn't want to break the process again. So we asked,
but not having answer after 2+ weeks I must admit I got a bit nervous
about it.

Sorry about that and thanks for the feedback about my questions.

Luca

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


From robh at kernel.org  Thu May 22 09:28:02 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Thu, 22 May 2025 11:28:02 -0500
Subject: [PATCH 1/2] dt-bindings: regulator: mediatek: Add MT8196 vmm
 controller
In-Reply-To: <20250522150426.3418225-2-nancy.lin@mediatek.com>
References: <20250522150426.3418225-1-nancy.lin@mediatek.com>
 <20250522150426.3418225-2-nancy.lin@mediatek.com>
Message-ID: <174793128032.2927822.14103783450131636692.robh@kernel.org>


On Thu, 22 May 2025 23:03:33 +0800, Nancy.Lin wrote:
> From: Nancy Lin <nancy.lin at mediatek.com>
> 
> Add a device tree binding document for the MediaTek MT8196 VMM (Vcore
> for MultiMedia) regulator controller. The VMM controller acts as the
> main power supplier for multimedia power domains, such as those used
> by display, video encode and decode subsystems. It provides virtual
> regulators that serve as the power sources for various multimedia IPs,
> and coordinates with the hardware common clock framework (hwccf) and
> the Video Companion Processor (VCP) to manage the power domains of
> these components. The regulator is controlled by the VCP firmware,
> and the operating system signals its requirement through a voting
> hardware block (hwccf).
> 
> Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
> ---
>  .../mediatek,mt8196-vmm-regulator.yaml        | 70 +++++++++++++++++++
>  1 file changed, 70 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.yaml: patternProperties:^(vdisp|vdec-vcore)$:properties:regulator-name:type: 'string' is not one of ['boolean', 'object']
	from schema $id: http://devicetree.org/meta-schemas/core.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.example.dtb: vmm (mediatek,mt8196-vmm): vdisp:regulator-name: ['vdisp'] is not of type 'string'
	from schema $id: http://devicetree.org/schemas/regulator/mediatek,mt8196-vmm-regulator.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.example.dtb: vmm (mediatek,mt8196-vmm): vdec-vcore:regulator-name: ['vdec-vcore'] is not of type 'string'
	from schema $id: http://devicetree.org/schemas/regulator/mediatek,mt8196-vmm-regulator.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250522150426.3418225-2-nancy.lin at mediatek.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.



From ansuelsmth at gmail.com  Thu May 22 09:53:08 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Thu, 22 May 2025 18:53:08 +0200
Subject: [net-next PATCH 0/3] net: dsa: mt7530: Add AN7583 support + PHY
Message-ID: <20250522165313.6411-1-ansuelsmth@gmail.com>

This small series add the required changes to make Airoha AN7583
Switch and Internal PHY work due to strange default configuration.

Christian Marangi (3):
  dt-bindings: net: dsa: mediatek,mt7530: Add airoha,an7583-switch
  net: dsa: mt7530: Add AN7583 support
  net: phy: mediatek: Add Airoha AN7583 PHY support

 .../bindings/net/dsa/mediatek,mt7530.yaml     |  5 ++++
 drivers/net/dsa/mt7530-mmio.c                 |  1 +
 drivers/net/dsa/mt7530.c                      | 24 +++++++++++++++++--
 drivers/net/dsa/mt7530.h                      | 18 ++++++++++----
 drivers/net/phy/mediatek/mtk-ge-soc.c         | 20 ++++++++++++++++
 5 files changed, 62 insertions(+), 6 deletions(-)

-- 
2.48.1



From ansuelsmth at gmail.com  Thu May 22 09:53:09 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Thu, 22 May 2025 18:53:09 +0200
Subject: [net-next PATCH 1/3] dt-bindings: net: dsa: mediatek,mt7530: Add airoha,an7583-switch
In-Reply-To: <20250522165313.6411-1-ansuelsmth@gmail.com>
References: <20250522165313.6411-1-ansuelsmth@gmail.com>
Message-ID: <20250522165313.6411-2-ansuelsmth@gmail.com>

Add airoha,an7583-switch additional compatible to the mt7530 DSA Switch
Family. This is an exact match of the airoha,en7581-switch (based on
mt7988-switch) with the additional requirement of tweak on the
GEPHY_CONN_CFG registers to make the internal PHY actually work.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 .../devicetree/bindings/net/dsa/mediatek,mt7530.yaml         | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
index ea979bcae1d6..51205f9f2985 100644
--- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
+++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
@@ -96,6 +96,10 @@ properties:
           Built-in switch of the Airoha EN7581 SoC
         const: airoha,en7581-switch
 
+      - description:
+          Built-in switch of the Airoha AN7583 SoC
+        const: airoha,an7583-switch
+
   reg:
     maxItems: 1
 
@@ -291,6 +295,7 @@ allOf:
           enum:
             - mediatek,mt7988-switch
             - airoha,en7581-switch
+            - airoha,an7583-switch
     then:
       $ref: "#/$defs/mt7530-dsa-port"
       properties:
-- 
2.48.1



From ansuelsmth at gmail.com  Thu May 22 09:53:10 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Thu, 22 May 2025 18:53:10 +0200
Subject: [net-next PATCH 2/3] net: dsa: mt7530: Add AN7583 support
In-Reply-To: <20250522165313.6411-1-ansuelsmth@gmail.com>
References: <20250522165313.6411-1-ansuelsmth@gmail.com>
Message-ID: <20250522165313.6411-3-ansuelsmth@gmail.com>

Add Airoha AN7583 Switch support. This is based on Airoha EN7581 that is
based on Mediatek MT7988 Switch.

Airoha AN7583 require additional tweak to the GEPHY_CONN_CFG register to
make the internal PHY work.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/dsa/mt7530-mmio.c |  1 +
 drivers/net/dsa/mt7530.c      | 24 ++++++++++++++++++++++--
 drivers/net/dsa/mt7530.h      | 18 ++++++++++++++----
 3 files changed, 37 insertions(+), 6 deletions(-)

diff --git a/drivers/net/dsa/mt7530-mmio.c b/drivers/net/dsa/mt7530-mmio.c
index 5f2db4317dd3..842d74268e77 100644
--- a/drivers/net/dsa/mt7530-mmio.c
+++ b/drivers/net/dsa/mt7530-mmio.c
@@ -11,6 +11,7 @@
 #include "mt7530.h"
 
 static const struct of_device_id mt7988_of_match[] = {
+	{ .compatible = "airoha,an7583-switch", .data = &mt753x_table[ID_AN7583], },
 	{ .compatible = "airoha,en7581-switch", .data = &mt753x_table[ID_EN7581], },
 	{ .compatible = "mediatek,mt7988-switch", .data = &mt753x_table[ID_MT7988], },
 	{ /* sentinel */ },
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index 7361380ffb5f..df213c37b4fe 100644
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -1298,7 +1298,7 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
 	 * is affine to the inbound user port.
 	 */
 	if (priv->id == ID_MT7531 || priv->id == ID_MT7988 ||
-	    priv->id == ID_EN7581)
+	    priv->id == ID_EN7581 || priv->id == ID_AN7583)
 		mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port)));
 
 	/* CPU port gets connected to all user ports of
@@ -2612,7 +2612,7 @@ mt7531_setup_common(struct dsa_switch *ds)
 	mt7530_set(priv, MT753X_AGC, LOCAL_EN);
 
 	/* Enable Special Tag for rx frames */
-	if (priv->id == ID_EN7581)
+	if (priv->id == ID_EN7581 || priv->id == ID_AN7583)
 		mt7530_write(priv, MT753X_CPORT_SPTAG_CFG,
 			     CPORT_SW2FE_STAG_EN | CPORT_FE2SW_STAG_EN);
 
@@ -3236,6 +3236,16 @@ static int mt7988_setup(struct dsa_switch *ds)
 	reset_control_deassert(priv->rstc);
 	usleep_range(20, 50);
 
+	/* AN7583 require additional tweak to CONN_CFG */
+	if (priv->id == ID_AN7583)
+		mt7530_rmw(priv, AN7583_GEPHY_CONN_CFG,
+			   AN7583_CSR_DPHY_CKIN_SEL |
+			   AN7583_CSR_PHY_CORE_REG_CLK_SEL |
+			   AN7583_CSR_ETHER_AFE_PWD,
+			   AN7583_CSR_DPHY_CKIN_SEL |
+			   AN7583_CSR_PHY_CORE_REG_CLK_SEL |
+			   FIELD_PREP(AN7583_CSR_ETHER_AFE_PWD, 0));
+
 	/* Reset the switch PHYs */
 	mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);
 
@@ -3344,6 +3354,16 @@ const struct mt753x_info mt753x_table[] = {
 		.phy_write_c45 = mt7531_ind_c45_phy_write,
 		.mac_port_get_caps = en7581_mac_port_get_caps,
 	},
+	[ID_AN7583] = {
+		.id = ID_AN7583,
+		.pcs_ops = &mt7530_pcs_ops,
+		.sw_setup = mt7988_setup,
+		.phy_read_c22 = mt7531_ind_c22_phy_read,
+		.phy_write_c22 = mt7531_ind_c22_phy_write,
+		.phy_read_c45 = mt7531_ind_c45_phy_read,
+		.phy_write_c45 = mt7531_ind_c45_phy_write,
+		.mac_port_get_caps = en7581_mac_port_get_caps,
+	},
 };
 EXPORT_SYMBOL_GPL(mt753x_table);
 
diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
index d4b838a055ad..7e47cd9af256 100644
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -20,6 +20,7 @@ enum mt753x_id {
 	ID_MT7531 = 2,
 	ID_MT7988 = 3,
 	ID_EN7581 = 4,
+	ID_AN7583 = 5,
 };
 
 #define	NUM_TRGMII_CTRL			5
@@ -66,7 +67,8 @@ enum mt753x_id {
 
 #define MT753X_MIRROR_REG(id)		((id == ID_MT7531 || \
 					  id == ID_MT7988 || \
-					  id == ID_EN7581) ? \
+					  id == ID_EN7581 || \
+					  id == ID_AN7583) ? \
 					 MT7531_CFC : MT753X_MFC)
 
 #define MT753X_MIRROR_EN(id)		((id == ID_MT7531 || \
@@ -76,19 +78,22 @@ enum mt753x_id {
 
 #define MT753X_MIRROR_PORT_MASK(id)	((id == ID_MT7531 || \
 					  id == ID_MT7988 || \
-					  id == ID_EN7581) ? \
+					  id == ID_EN7581 || \
+					  id == ID_AN7583) ? \
 					 MT7531_MIRROR_PORT_MASK : \
 					 MT7530_MIRROR_PORT_MASK)
 
 #define MT753X_MIRROR_PORT_GET(id, val)	((id == ID_MT7531 || \
 					  id == ID_MT7988 || \
-					  id == ID_EN7581) ? \
+					  id == ID_EN7581 || \
+					  id == ID_AN7583) ? \
 					 MT7531_MIRROR_PORT_GET(val) : \
 					 MT7530_MIRROR_PORT_GET(val))
 
 #define MT753X_MIRROR_PORT_SET(id, val)	((id == ID_MT7531 || \
 					  id == ID_MT7988 || \
-					  id == ID_EN7581) ? \
+					  id == ID_EN7581 || \
+					  id == ID_AN7583) ? \
 					 MT7531_MIRROR_PORT_SET(val) : \
 					 MT7530_MIRROR_PORT_SET(val))
 
@@ -673,6 +678,11 @@ enum mt7531_xtal_fsel {
 #define  CPORT_SW2FE_STAG_EN		BIT(1)
 #define  CPORT_FE2SW_STAG_EN		BIT(0)
 
+#define AN7583_GEPHY_CONN_CFG		0x7c14
+#define  AN7583_CSR_DPHY_CKIN_SEL	BIT(31)
+#define  AN7583_CSR_PHY_CORE_REG_CLK_SEL BIT(30)
+#define  AN7583_CSR_ETHER_AFE_PWD	GENMASK(28, 24)
+
 /* Registers for LED GPIO control (MT7530 only)
  * All registers follow this pattern:
  * [ 2: 0]  port 0
-- 
2.48.1



From ansuelsmth at gmail.com  Thu May 22 09:53:11 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Thu, 22 May 2025 18:53:11 +0200
Subject: [net-next PATCH 3/3] net: phy: mediatek: Add Airoha AN7583 PHY support
In-Reply-To: <20250522165313.6411-1-ansuelsmth@gmail.com>
References: <20250522165313.6411-1-ansuelsmth@gmail.com>
Message-ID: <20250522165313.6411-4-ansuelsmth@gmail.com>

Add Airoha AN7583 PHY support based on Airoha AN7581 with the small
difference that BMCR_PDOWN is enabled by default and needs to be cleared
to make the internal PHY correctly work.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/net/phy/mediatek/mtk-ge-soc.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediatek/mtk-ge-soc.c
index a284e8435cb6..cd09fbf92ef2 100644
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -17,6 +17,7 @@
 #define MTK_GPHY_ID_MT7981			0x03a29461
 #define MTK_GPHY_ID_MT7988			0x03a29481
 #define MTK_GPHY_ID_AN7581			0x03a294c1
+#define MTK_GPHY_ID_AN7583			0xc0ff0420
 
 #define MTK_EXT_PAGE_ACCESS			0x1f
 #define MTK_PHY_PAGE_STANDARD			0x0000
@@ -1463,6 +1464,12 @@ static int an7581_phy_led_polarity_set(struct phy_device *phydev, int index,
 			      MTK_PHY_LED_ON_POLARITY, val);
 }
 
+static int an7583_phy_config_init(struct phy_device *phydev)
+{
+	/* BMCR_PDOWN is enabled by default */
+	return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
+}
+
 static struct phy_driver mtk_socphy_driver[] = {
 	{
 		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
@@ -1509,6 +1516,18 @@ static struct phy_driver mtk_socphy_driver[] = {
 		.led_hw_control_get = mt798x_phy_led_hw_control_get,
 		.led_polarity_set = an7581_phy_led_polarity_set,
 	},
+	{
+		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7583),
+		.name		= "Airoha AN7583 PHY",
+		.config_init	= an7583_phy_config_init,
+		.probe		= an7581_phy_probe,
+		.led_blink_set	= mt798x_phy_led_blink_set,
+		.led_brightness_set = mt798x_phy_led_brightness_set,
+		.led_hw_is_supported = mt798x_phy_led_hw_is_supported,
+		.led_hw_control_set = mt798x_phy_led_hw_control_set,
+		.led_hw_control_get = mt798x_phy_led_hw_control_get,
+		.led_polarity_set = an7581_phy_led_polarity_set,
+	},
 };
 
 module_phy_driver(mtk_socphy_driver);
@@ -1517,6 +1536,7 @@ static const struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
 	{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
 	{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
 	{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581) },
+	{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7583) },
 	{ }
 };
 
-- 
2.48.1



From krzysztof.kozlowski at linaro.org  Thu May 22 11:34:19 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Thu, 22 May 2025 20:34:19 +0200
Subject: [PATCH] soc: mediatek: Do not enable MTK_SOCINFO by default
 during compile testing
In-Reply-To: <3e10ed93-dadb-4d0b-b419-28ea492a1603@collabora.com>
References: <20250404112359.255053-1-krzysztof.kozlowski@linaro.org>
 <3e10ed93-dadb-4d0b-b419-28ea492a1603@collabora.com>
Message-ID: <5ebc399d-88f4-4d90-adcc-8c9b31efbd95@linaro.org>

On 04/04/2025 13:29, AngeloGioacchino Del Regno wrote:
> Il 04/04/25 13:23, Krzysztof Kozlowski ha scritto:
>> Enabling the compile test should not cause automatic enabling of such
>> drivers.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> 
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> 
>> ---

Ping

This was almost two months ago. I would assume that with maintainer
review, this should be applied fast. What is here needed?

Best regards,
Krzysztof


From ck.hu at mediatek.com  Thu May 22 19:55:24 2025
From: ck.hu at mediatek.com (=?utf-8?B?Q0sgSHUgKOiDoeS/iuWFiSk=?=)
Date: Fri, 23 May 2025 02:55:24 +0000
Subject: [PATCH 1/2] dt-bindings: regulator: mediatek: Add MT8196 vmm
 controller
In-Reply-To: <20250522150426.3418225-2-nancy.lin@mediatek.com>
References: <20250522150426.3418225-1-nancy.lin@mediatek.com>
	 <20250522150426.3418225-2-nancy.lin@mediatek.com>
Message-ID: <caab284a85ad5906d1d2befd6a3bd2ef77301758.camel@mediatek.com>

On Thu, 2025-05-22 at 23:03 +0800, Nancy.Lin wrote:
> From: Nancy Lin <nancy.lin at mediatek.com>
> 
> Add a device tree binding document for the MediaTek MT8196 VMM (Vcore
> for MultiMedia) regulator controller. The VMM controller acts as the
> main power supplier for multimedia power domains, such as those used
> by display, video encode and decode subsystems. It provides virtual
> regulators that serve as the power sources for various multimedia IPs,
> and coordinates with the hardware common clock framework (hwccf) and
> the Video Companion Processor (VCP) to manage the power domains of
> these components. The regulator is controlled by the VCP firmware,
> and the operating system signals its requirement through a voting
> hardware block (hwccf).
> 
> Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
> ---
>  .../mediatek,mt8196-vmm-regulator.yaml        | 70 +++++++++++++++++++
>  1 file changed, 70 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.yaml
> 
> diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.yaml
> new file mode 100644
> index 000000000000..a50e35c2e238
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-regulator.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "https://urldefense.com/v3/__http://devicetree.org/schemas/regulator/mediatek,mt8196-vmm-regulator.yaml*__;Iw!!CTRNKA9wMg0ARbw!gawATNOT3u6UBtTwtgnoZggwdwVL3VBuFZQyf-baV8j1wUMIV1sIaqBvhcqtfnZSlmXFesengtZaYxCWtDo$ "
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!gawATNOT3u6UBtTwtgnoZggwdwVL3VBuFZQyf-baV8j1wUMIV1sIaqBvhcqtfnZSlmXFesengtZaLcnGLmw$ 
> +
> +title: MediaTek MT8196 VMM (Vcore for MultiMedia) Regulator Controller
> +
> +maintainers:
> +  - Nancy Lin <nancy.lin at mediatek.com>
> +
> +description: |
> +  The MediaTek MT8196 VMM (Vcore for Multi Media) controller acts as the
> +  main power supplier for multimedia power domains, such as those used by
> +  display, video encode and decode subsystems. The VMM hardware block
> +  provides virtual regulators that serve as the power sources (suppliers)
> +  for various multimedia IPs. It coordinates with the MediaTek hardware
> +  common clock framework (HWCCF) and the Video Companion Processor (VCP)
> +  to manage the power domains of these multimedia components.
> +
> +  Each child node under the VMM node represents a virtual regulator
> +  (e.g., vdisp, vdec-vcore) and must specify a 'regulator-name'.
> +
> +properties:
> +  compatible:
> +    const: "mediatek,mt8196-vmm"
> +
> +  mediatek,hw-ccf:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: Phandle to the hardware common clock framework syscon controller.
> +
> +  mediatek,vcp:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: Phandle to the Video Co-Processor (VCP) node.
> +
> +patternProperties:
> +  "^(vdisp|vdec-vcore)$":
> +    type: object
> +    description: |
> +      Virtual regulator for a specific multimedia domain.
> +      The node name should match the supported regulator (e.g., vdisp, vdec-vcore).
> +    properties:
> +      regulator-name:
> +        type: string
> +        description: The name of the virtual regulator.
> +    required:
> +      - regulator-name
> +    additionalProperties: false
> +
> +required:
> +  - compatible
> +  - mediatek,hw-ccf
> +  - mediatek,vcp
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    vmm: vmm {
> +      compatible = "mediatek,mt8196-vmm";
> +      mediatek,hw-ccf = <&mm_hwv>;
> +      mediatek,vcp = <&vcp>;
> +
> +      vdisp: vdisp {
> +        regulator-name = "vdisp";
> +      };
> +      vdec_vcore: vdec-vcore {
> +        regulator-name = "vdec-vcore";
> +      };
> +    };

device tree is used to describe real hardware.
vmm is a virtual device which is used for software to integrate the related driver,
so it should not have this virtual device.
According to your description, vcp is the master to control regulator,
so I think the device tree would be

vcp {
	regulator-name = "vdisp", "vdec-vcore";
};

And vcp driver control these regulator.

I'm not sure what does hw-ccf do, if it's also controlled by vcp, the node should be

vcp {
	mediatek,hw-ccf = <&mm_hwv>;
	regulator-name = "vdisp", "vdec-vcore";
};

Regards,
CK



From tanghuan at vivo.com  Thu May 22 23:46:04 2025
From: tanghuan at vivo.com (Huan Tang)
Date: Fri, 23 May 2025 14:46:04 +0800
Subject: [PATCH v6] ufs: core: Add HID support
Message-ID: <20250523064604.800-1-tanghuan@vivo.com>

Follow JESD220G, support HID(Host Initiated Defragmentation)
through sysfs, the relevant sysfs nodes are as follows:
	1.analysis_trigger
	2.defrag_trigger
	3.fragmented_size
	4.defrag_size
	5.progress_ratio
	6.state
The detailed definition	of the six nodes can be	found in the sysfs
documentation.

HID's execution policy is given to user-space.

Signed-off-by: Huan Tang <tanghuan at vivo.com>
Signed-off-by: Wenxing Cheng <wenxing.cheng at vivo.com>
Suggested-by: Bart Van Assche <bvanassche at acm.org>
Reviewed-by: Peter Wang <peter.wang at mediatek.com>
Reviewed-by: Bean Huo <huobean at gmail.com>
---
Changelog
===
v5 - > v6:
	1.Adopt Peter's suggestion to improve code readability
	2.Adopt Bean's suggestion to simplify code
v4 - > v5:
	1.Fixed a typo in "indicates"
	2."DEFRAG_IS_NOT_REQUIRED" -> "DEFRAG_NOT_REQUIRED"
	3.Fix some coding style issues
v3 - > v4:
	1.Move the changelog description under "---"
v2 - > v3:
	1.Remove the "ufs_" prefix from directory name
	2.Remove the "hid_" prefix from node names
	3.Make "ufs" appear only once in the HID group name
	4.Add "is_visible" callback for "ufs_sysfs_hid_group"
v1 - > v2:
	1.Refactor the HID code according to Bart and Peter and
	Arvi's suggestions

v5
	https://lore.kernel.org/all/20250520094054.313-1-tanghuan at vivo.com/
v4
	https://lore.kernel.org/all/20250520063512.213-1-tanghuan at vivo.com/
v3
	https://lore.kernel.org/all/20250519022912.292-1-tanghuan at vivo.com/
v2
	https://lore.kernel.org/all/20250512131519.138-1-tanghuan at vivo.com/
v1
	https://lore.kernel.org/all/20250417125008.123-1-tanghuan at vivo.com/

 Documentation/ABI/testing/sysfs-driver-ufs |  83 +++++++++
 drivers/ufs/core/ufs-sysfs.c               | 190 +++++++++++++++++++++
 drivers/ufs/core/ufshcd.c                  |   4 +
 include/ufs/ufs.h                          |  26 +++
 4 files changed, 303 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-driver-ufs b/Documentation/ABI/testing/sysfs-driver-ufs
index d4140dc6c5ba..f3de8c521bbd 100644
--- a/Documentation/ABI/testing/sysfs-driver-ufs
+++ b/Documentation/ABI/testing/sysfs-driver-ufs
@@ -1685,3 +1685,86 @@ Description:
 		================  ========================================
 
 		The file is read only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/analysis_trigger
+What:		/sys/bus/platform/devices/*.ufs/hid/analysis_trigger
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The host can enable or disable HID analysis operation.
+
+		=======  =========================================
+		disable   disable HID analysis operation
+		enable    enable HID analysis operation
+		=======  =========================================
+
+		The file is write only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/defrag_trigger
+What:		/sys/bus/platform/devices/*.ufs/hid/defrag_trigger
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The host can enable or disable HID defragmentation operation.
+
+		=======  =========================================
+		disable   disable HID defragmentation operation
+		enable    enable HID defragmentation operation
+		=======  =========================================
+
+		The attribute is write only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/fragmented_size
+What:		/sys/bus/platform/devices/*.ufs/hid/fragmented_size
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The total fragmented size in the device is reported through
+		this attribute.
+
+		The attribute is read only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/defrag_size
+What:		/sys/bus/platform/devices/*.ufs/hid/defrag_size
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The host sets the size to be defragmented by an HID
+		defragmentation operation.
+
+		The attribute is read/write.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/progress_ratio
+What:		/sys/bus/platform/devices/*.ufs/hid/progress_ratio
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		Defragmentation progress is reported by this attribute,
+		indicates the ratio of the completed defragmentation size
+		over the requested defragmentation size.
+
+		====  ============================================
+		1     1%
+		...
+		100   100%
+		====  ============================================
+
+		The attribute is read only.
+
+What:		/sys/bus/platform/drivers/ufshcd/*/hid/state
+What:		/sys/bus/platform/devices/*.ufs/hid/state
+Date:		May 2025
+Contact:	Huan Tang <tanghuan at vivo.com>
+Description:
+		The HID state is reported by this attribute.
+
+		====================   ===========================
+		idle			Idle (analysis required)
+		analysis_in_progress    Analysis in progress
+		defrag_required      	Defrag required
+		defrag_in_progress      Defrag in progress
+		defrag_completed      	Defrag completed
+		defrag_not_required     Defrag is not required
+		====================   ===========================
+
+		The attribute is read only.
diff --git a/drivers/ufs/core/ufs-sysfs.c b/drivers/ufs/core/ufs-sysfs.c
index de8b6acd4058..10006ae5ee35 100644
--- a/drivers/ufs/core/ufs-sysfs.c
+++ b/drivers/ufs/core/ufs-sysfs.c
@@ -87,6 +87,23 @@ static const char *ufs_wb_resize_status_to_string(enum wb_resize_status status)
 	}
 }
 
+static const char * const ufs_hid_states[] = {
+	[HID_IDLE]		= "idle",
+	[ANALYSIS_IN_PROGRESS]	= "analysis_in_progress",
+	[DEFRAG_REQUIRED]	= "defrag_required",
+	[DEFRAG_IN_PROGRESS]	= "defrag_in_progress",
+	[DEFRAG_COMPLETED]	= "defrag_completed",
+	[DEFRAG_NOT_REQUIRED]	= "defrag_not_required",
+};
+
+static const char *ufs_hid_state_to_string(enum ufs_hid_state state)
+{
+	if (state < NUM_UFS_HID_STATES)
+		return ufs_hid_states[state];
+
+	return "unknown";
+}
+
 static const char *ufshcd_uic_link_state_to_string(
 			enum uic_link_state state)
 {
@@ -1763,6 +1780,178 @@ static const struct attribute_group ufs_sysfs_attributes_group = {
 	.attrs = ufs_sysfs_attributes,
 };
 
+static int hid_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
+			enum attr_idn idn, u32 *attr_val)
+{
+	int ret;
+
+	down(&hba->host_sem);
+	if (!ufshcd_is_user_access_allowed(hba)) {
+		up(&hba->host_sem);
+		return -EBUSY;
+	}
+
+	ufshcd_rpm_get_sync(hba);
+	ret = ufshcd_query_attr(hba, opcode, idn, 0, 0, attr_val);
+	ufshcd_rpm_put_sync(hba);
+
+	up(&hba->host_sem);
+	return ret;
+}
+
+static ssize_t analysis_trigger_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	int mode;
+	int ret;
+
+	if (sysfs_streq(buf, "enable"))
+		mode = HID_ANALYSIS_ENABLE;
+	else if (sysfs_streq(buf, "disable"))
+		mode = HID_ANALYSIS_AND_DEFRAG_DISABLE;
+	else
+		return -EINVAL;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_WO(analysis_trigger);
+
+static ssize_t defrag_trigger_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	int mode;
+	int ret;
+
+	if (sysfs_streq(buf, "enable"))
+		mode = HID_ANALYSIS_AND_DEFRAG_ENABLE;
+	else if (sysfs_streq(buf, "disable"))
+		mode = HID_ANALYSIS_AND_DEFRAG_DISABLE;
+	else
+		return -EINVAL;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_DEFRAG_OPERATION, &mode);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_WO(defrag_trigger);
+
+static ssize_t fragmented_size_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_AVAILABLE_SIZE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%u\n", value);
+}
+
+static DEVICE_ATTR_RO(fragmented_size);
+
+static ssize_t defrag_size_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_SIZE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%u\n", value);
+}
+
+static ssize_t defrag_size_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	if (kstrtou32(buf, 0, &value))
+		return -EINVAL;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
+			QUERY_ATTR_IDN_HID_SIZE, &value);
+
+	return ret < 0 ? ret : count;
+}
+
+static DEVICE_ATTR_RW(defrag_size);
+
+static ssize_t progress_ratio_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_PROGRESS_RATIO, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%u\n", value);
+}
+
+static DEVICE_ATTR_RO(progress_ratio);
+
+static ssize_t state_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+	u32 value;
+	int ret;
+
+	ret = hid_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+			QUERY_ATTR_IDN_HID_STATE, &value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%s\n", ufs_hid_state_to_string(value));
+}
+
+static DEVICE_ATTR_RO(state);
+
+static struct attribute *ufs_sysfs_hid[] = {
+	&dev_attr_analysis_trigger.attr,
+	&dev_attr_defrag_trigger.attr,
+	&dev_attr_fragmented_size.attr,
+	&dev_attr_defrag_size.attr,
+	&dev_attr_progress_ratio.attr,
+	&dev_attr_state.attr,
+	NULL,
+};
+
+static umode_t ufs_sysfs_hid_is_visible(struct kobject *kobj,
+		struct attribute *attr, int n)
+{
+	struct device *dev = container_of(kobj, struct device, kobj);
+	struct ufs_hba *hba = dev_get_drvdata(dev);
+
+	return	hba->dev_info.hid_sup ? attr->mode : 0;
+}
+
+static const struct attribute_group ufs_sysfs_hid_group = {
+	.name = "hid",
+	.attrs = ufs_sysfs_hid,
+	.is_visible = ufs_sysfs_hid_is_visible,
+};
+
 static const struct attribute_group *ufs_sysfs_groups[] = {
 	&ufs_sysfs_default_group,
 	&ufs_sysfs_capabilities_group,
@@ -1777,6 +1966,7 @@ static const struct attribute_group *ufs_sysfs_groups[] = {
 	&ufs_sysfs_string_descriptors_group,
 	&ufs_sysfs_flags_group,
 	&ufs_sysfs_attributes_group,
+	&ufs_sysfs_hid_group,
 	NULL,
 };
 
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 3e2097e65964..8ccd923a5761 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -8390,6 +8390,10 @@ static int ufs_get_device_desc(struct ufs_hba *hba)
 
 	dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP];
 
+	dev_info->hid_sup = get_unaligned_be32(desc_buf +
+				DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP) &
+				UFS_DEV_HID_SUPPORT;
+
 	model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
 
 	err = ufshcd_read_string_desc(hba, model_index,
diff --git a/include/ufs/ufs.h b/include/ufs/ufs.h
index c0c59a8f7256..72fd385037a6 100644
--- a/include/ufs/ufs.h
+++ b/include/ufs/ufs.h
@@ -182,6 +182,11 @@ enum attr_idn {
 	QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE        = 0x1F,
 	QUERY_ATTR_IDN_TIMESTAMP		= 0x30,
 	QUERY_ATTR_IDN_DEV_LVL_EXCEPTION_ID     = 0x34,
+	QUERY_ATTR_IDN_HID_DEFRAG_OPERATION	= 0x35,
+	QUERY_ATTR_IDN_HID_AVAILABLE_SIZE	= 0x36,
+	QUERY_ATTR_IDN_HID_SIZE			= 0x37,
+	QUERY_ATTR_IDN_HID_PROGRESS_RATIO	= 0x38,
+	QUERY_ATTR_IDN_HID_STATE		= 0x39,
 	QUERY_ATTR_IDN_WB_BUF_RESIZE_HINT	= 0x3C,
 	QUERY_ATTR_IDN_WB_BUF_RESIZE_EN		= 0x3D,
 	QUERY_ATTR_IDN_WB_BUF_RESIZE_STATUS	= 0x3E,
@@ -401,6 +406,7 @@ enum {
 	UFS_DEV_HPB_SUPPORT		= BIT(7),
 	UFS_DEV_WRITE_BOOSTER_SUP	= BIT(8),
 	UFS_DEV_LVL_EXCEPTION_SUP       = BIT(12),
+	UFS_DEV_HID_SUPPORT		= BIT(13),
 };
 #define UFS_DEV_HPB_SUPPORT_VERSION		0x310
 
@@ -466,6 +472,24 @@ enum ufs_ref_clk_freq {
 	REF_CLK_FREQ_INVAL	= -1,
 };
 
+/* bDefragOperation attribute values */
+enum ufs_hid_defrag_operation {
+	HID_ANALYSIS_AND_DEFRAG_DISABLE	= 0,
+	HID_ANALYSIS_ENABLE		= 1,
+	HID_ANALYSIS_AND_DEFRAG_ENABLE	= 2,
+};
+
+/* bHIDState attribute values */
+enum ufs_hid_state {
+	HID_IDLE		= 0,
+	ANALYSIS_IN_PROGRESS	= 1,
+	DEFRAG_REQUIRED		= 2,
+	DEFRAG_IN_PROGRESS	= 3,
+	DEFRAG_COMPLETED	= 4,
+	DEFRAG_NOT_REQUIRED	= 5,
+	NUM_UFS_HID_STATES	= 6,
+};
+
 /* bWriteBoosterBufferResizeEn attribute */
 enum wb_resize_en {
 	WB_RESIZE_EN_IDLE	= 0,
@@ -625,6 +649,8 @@ struct ufs_dev_info {
 	u32 rtc_update_period;
 
 	u8 rtt_cap; /* bDeviceRTTCap */
+
+	bool hid_sup;
 };
 
 /*
-- 
2.48.1



From ot_cathy.xu at mediatek.com  Fri May 23 02:42:46 2025
From: ot_cathy.xu at mediatek.com (Cathy Xu)
Date: Fri, 23 May 2025 17:42:46 +0800
Subject: [PATCH 1/3] dt-bindings: pinctrl: mediatek: Add support for mt8189
In-Reply-To: <20250523094319.10377-1-ot_cathy.xu@mediatek.com>
References: <20250523094319.10377-1-ot_cathy.xu@mediatek.com>
Message-ID: <20250523094319.10377-2-ot_cathy.xu@mediatek.com>

Add the new binding document for pinctrl on MediaTek mt8189.

Signed-off-by: Cathy Xu <ot_cathy.xu at mediatek.com>
---
 .../pinctrl/mediatek,mt8189-pinctrl.yaml      | 217 ++++++++++++++++++
 1 file changed, 217 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8189-pinctrl.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8189-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8189-pinctrl.yaml
new file mode 100644
index 000000000000..43b6f15efad8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8189-pinctrl.yaml
@@ -0,0 +1,217 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8189-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT8189 Pin Controller
+
+maintainers:
+  - Lei Xue <lei.xue at mediatek.com>
+  - Cathy Xu <ot_cathy.xu at mediatek.com>
+
+description:
+  The MediaTek's MT8189 Pin controller is used to control SoC pins.
+
+properties:
+  compatible:
+    const: mediatek,mt8189-pinctrl
+
+  reg:
+    items:
+      - description: gpio base
+      - description: lm group IO
+      - description: rb0 group IO
+      - description: rb1 group IO
+      - description: bm0 group IO
+      - description: bm1 group IO
+      - description: bm2 group IO
+      - description: lt0 group IO
+      - description: lt1 group IO
+      - description: rt group IO
+      - description: eint0 group IO
+      - description: eint1 group IO
+      - description: eint2 group IO
+      - description: eint3 group IO
+      - description: eint4 group IO
+
+  reg-names:
+    items:
+      - const: base
+      - const: lm
+      - const: rb0
+      - const: rb1
+      - const: bm0
+      - const: bm1
+      - const: bm2
+      - const: lt0
+      - const: lt1
+      - const: rt
+      - const: eint0
+      - const: eint1
+      - const: eint2
+      - const: eint3
+      - const: eint4
+
+  interrupts:
+    description: The interrupt outputs to sysirq.
+    maxItems: 1
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    description:
+      Number of cells in GPIO specifier, should be two. The first cell is the
+      pin number, the second cell is used to specify optional parameters which
+      are defined in <dt-bindings/gpio/gpio.h>.
+    const: 2
+
+  gpio-ranges:
+    maxItems: 1
+
+  gpio-line-names: true
+
+# PIN CONFIGURATION NODES
+patternProperties:
+  '-pins$':
+    type: object
+    additionalProperties: false
+
+    patternProperties:
+      '^pins':
+        type: object
+        $ref: /schemas/pinctrl/pincfg-node.yaml
+        additionalProperties: false
+        description:
+          A pinctrl node should contain at least one subnode representing the
+          pinctrl groups available on the machine. Each subnode will list the
+          pins it needs, and how they should be configured, with regard to muxer
+          configuration, pullups, drive strength, input enable/disable and input
+          schmitt.
+
+        properties:
+          pinmux:
+            description:
+              Integer array, represents gpio pin number and mux setting.
+              Supported pin number and mux varies for different SoCs, and are
+              defined as macros in arch/arm64/boot/dts/mediatek/mt8189-pinfunc.h
+              directly, for this SoC.
+
+          drive-strength:
+            enum: [2, 4, 6, 8, 10, 12, 14, 16]
+
+          bias-pull-down:
+            oneOf:
+              - type: boolean
+              - enum: [100, 101, 102, 103]
+                description: mt8189 pull down PUPD/R0/R1 type define value.
+              - enum: [75000, 5000]
+                description: mt8189 pull down RSEL type si unit value(ohm).
+            description: |
+              For pull down type is normal, it doesn't need add R1R0 define
+              and resistance value.
+              For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
+              set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
+              "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
+              "MTK_PUPD_SET_R1R0_11" define in mt8189.
+              For pull down type is PD/RSEL, it can add resistance value(ohm)
+              to set different resistance by identifying property
+              "mediatek,rsel-resistance-in-si-unit". It can support resistance
+              value(ohm) "75000" & "5000" in mt8189.
+
+          bias-pull-up:
+            oneOf:
+              - type: boolean
+              - enum: [100, 101, 102, 103]
+                description: mt8189 pull up PUPD/R0/R1 type define value.
+              - enum: [1000, 1500, 2000, 3000, 4000, 5000, 75000]
+                description: mt8189 pull up RSEL type si unit value(ohm).
+            description: |
+              For pull up type is normal, it don't need add R1R0 define
+              and resistance value.
+              For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
+              set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
+              "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
+              "MTK_PUPD_SET_R1R0_11" define in mt8189.
+              For pull up type is PU/RSEL, it can add resistance value(ohm)
+              to set different resistance by identifying property
+              "mediatek,rsel-resistance-in-si-unit". It can support resistance
+              value(ohm) "1000" & "1500" & "2000" & "3000" & "4000" & "5000" &
+              "75000" in mt8189.
+
+          bias-disable: true
+
+          output-high: true
+
+          output-low: true
+
+          input-enable: true
+
+          input-disable: true
+
+          input-schmitt-enable: true
+
+          input-schmitt-disable: true
+
+        required:
+          - pinmux
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-controller
+  - '#interrupt-cells'
+  - gpio-controller
+  - '#gpio-cells'
+  - gpio-ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/pinctrl/mt65xx.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #define PINMUX_GPIO51__FUNC_SCL0 (MTK_PIN_NO(51) | 2)
+    #define PINMUX_GPIO52__FUNC_SDA0 (MTK_PIN_NO(52) | 2)
+
+    pio: pinctrl at 10005000 {
+        compatible = "mediatek,mt8189-pinctrl";
+        reg = <0x10005000 0x1000>,
+              <0x11b50000 0x1000>,
+              <0x11c50000 0x1000>,
+              <0x11c60000 0x1000>,
+              <0x11d20000 0x1000>,
+              <0x11d30000 0x1000>,
+              <0x11d40000 0x1000>,
+              <0x11e20000 0x1000>,
+              <0x11e30000 0x1000>,
+              <0x11f20000 0x1000>,
+              <0x11ce0000 0x1000>,
+              <0x11de0000 0x1000>,
+              <0x11e60000 0x1000>,
+              <0x1c01e000 0x1000>,
+              <0x11f00000 0x1000>;
+        reg-names = "base", "lm", "rb0", "rb1", "bm0" , "bm1",
+                    "bm2", "lt0", "lt1", "rt", "eint0", "eint1",
+                    "eint2", "eint3", "eint4";
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&pio 0 0 182>;
+        interrupt-controller;
+        interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
+        #interrupt-cells = <2>;
+
+        i2c0-pins {
+            pins {
+                pinmux = <PINMUX_GPIO51__FUNC_SCL0>,
+                         <PINMUX_GPIO52__FUNC_SDA0>;
+                bias-disable;
+            };
+        };
+    };
-- 
2.45.2



From ot_cathy.xu at mediatek.com  Fri May 23 02:42:45 2025
From: ot_cathy.xu at mediatek.com (Cathy Xu)
Date: Fri, 23 May 2025 17:42:45 +0800
Subject: [PATCH 0/3] pinctrl: mediatek: Add pinctrl driver on mt8189
Message-ID: <20250523094319.10377-1-ot_cathy.xu@mediatek.com>

This patch series introduces support for the MT8189 pinctrl driver, include
the driver implementation, new binding document and pinctrl header file.

Cathy Xu (3):
  dt-bindings: pinctrl: mediatek: Add support for mt8189
  arm64: dts: mediatek: mt8189: Add pinmux macro header file
  pinctrl: mediatek: Add pinctrl driver on mt8189

 .../pinctrl/mediatek,mt8189-pinctrl.yaml      |  217 ++
 arch/arm64/boot/dts/mediatek/mt8189-pinfunc.h | 1125 ++++++++
 drivers/pinctrl/mediatek/Kconfig              |   12 +
 drivers/pinctrl/mediatek/Makefile             |    1 +
 drivers/pinctrl/mediatek/pinctrl-mt8189.c     | 1700 ++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-mt8189.h | 2452 +++++++++++++++++
 6 files changed, 5507 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8189-pinctrl.yaml
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-pinfunc.h
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8189.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8189.h

-- 
2.45.2



From ot_cathy.xu at mediatek.com  Fri May 23 02:42:47 2025
From: ot_cathy.xu at mediatek.com (Cathy Xu)
Date: Fri, 23 May 2025 17:42:47 +0800
Subject: [PATCH 2/3] arm64: dts: mediatek: mt8189: Add pinmux macro header file
In-Reply-To: <20250523094319.10377-1-ot_cathy.xu@mediatek.com>
References: <20250523094319.10377-1-ot_cathy.xu@mediatek.com>
Message-ID: <20250523094319.10377-3-ot_cathy.xu@mediatek.com>

Add the pinctrl header file on MediaTek mt8189.

Signed-off-by: Cathy Xu <ot_cathy.xu at mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8189-pinfunc.h | 1125 +++++++++++++++++
 1 file changed, 1125 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-pinfunc.h

diff --git a/arch/arm64/boot/dts/mediatek/mt8189-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8189-pinfunc.h
new file mode 100644
index 000000000000..f9c270ebab89
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189-pinfunc.h
@@ -0,0 +1,1125 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ * Author: Lei Xue <lei.xue at mediatek.com>
+ *         Cathy Xu <ot_cathy.xu at mediatek.com>
+ */
+
+#ifndef __MT8189_PINFUNC_H
+#define __MT8189_PINFUNC_H
+
+#include "mt65xx.h"
+
+#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 1)
+#define PINMUX_GPIO0__FUNC_SPIM3_A_CSB (MTK_PIN_NO(0) | 2)
+#define PINMUX_GPIO0__FUNC_I2SOUT0_MCK (MTK_PIN_NO(0) | 3)
+#define PINMUX_GPIO0__FUNC_SCP_SPI0_CS (MTK_PIN_NO(0) | 4)
+#define PINMUX_GPIO0__FUNC_CONN_BPI_BUS6 (MTK_PIN_NO(0) | 6)
+#define PINMUX_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7)
+
+#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 1)
+#define PINMUX_GPIO1__FUNC_SPIM3_A_CLK (MTK_PIN_NO(1) | 2)
+#define PINMUX_GPIO1__FUNC_I2SOUT0_BCK (MTK_PIN_NO(1) | 3)
+#define PINMUX_GPIO1__FUNC_SCP_SPI0_CK (MTK_PIN_NO(1) | 4)
+#define PINMUX_GPIO1__FUNC_CONN_BPI_BUS7 (MTK_PIN_NO(1) | 6)
+#define PINMUX_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7)
+
+#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 1)
+#define PINMUX_GPIO2__FUNC_SPIM3_A_MO (MTK_PIN_NO(2) | 2)
+#define PINMUX_GPIO2__FUNC_I2SOUT0_LRCK (MTK_PIN_NO(2) | 3)
+#define PINMUX_GPIO2__FUNC_SCP_SPI0_MO (MTK_PIN_NO(2) | 4)
+#define PINMUX_GPIO2__FUNC_CONN_BPI_BUS8 (MTK_PIN_NO(2) | 6)
+#define PINMUX_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7)
+
+#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 1)
+#define PINMUX_GPIO3__FUNC_SPIM3_A_MI (MTK_PIN_NO(3) | 2)
+#define PINMUX_GPIO3__FUNC_I2SOUT0_DO (MTK_PIN_NO(3) | 3)
+#define PINMUX_GPIO3__FUNC_SCP_SPI0_MI (MTK_PIN_NO(3) | 4)
+#define PINMUX_GPIO3__FUNC_CONN_BPI_BUS9 (MTK_PIN_NO(3) | 6)
+#define PINMUX_GPIO3__FUNC_DBG_MON_A3 (MTK_PIN_NO(3) | 7)
+
+#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 1)
+#define PINMUX_GPIO4__FUNC_SPIM4_A_CSB (MTK_PIN_NO(4) | 2)
+#define PINMUX_GPIO4__FUNC_I2SIN0_DI (MTK_PIN_NO(4) | 3)
+#define PINMUX_GPIO4__FUNC_SCP_SPI1_CS (MTK_PIN_NO(4) | 4)
+#define PINMUX_GPIO4__FUNC_CONN_BPI_BUS10 (MTK_PIN_NO(4) | 6)
+#define PINMUX_GPIO4__FUNC_DBG_MON_A4 (MTK_PIN_NO(4) | 7)
+
+#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 1)
+#define PINMUX_GPIO5__FUNC_SPIM4_A_CLK (MTK_PIN_NO(5) | 2)
+#define PINMUX_GPIO5__FUNC_I2SIN0_BCK (MTK_PIN_NO(5) | 3)
+#define PINMUX_GPIO5__FUNC_SCP_SPI1_CK (MTK_PIN_NO(5) | 4)
+#define PINMUX_GPIO5__FUNC_CONN_BPI_BUS11_OLAT0 (MTK_PIN_NO(5) | 6)
+#define PINMUX_GPIO5__FUNC_DBG_MON_A5 (MTK_PIN_NO(5) | 7)
+
+#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 1)
+#define PINMUX_GPIO6__FUNC_SPIM4_A_MO (MTK_PIN_NO(6) | 2)
+#define PINMUX_GPIO6__FUNC_I2SIN0_LRCK (MTK_PIN_NO(6) | 3)
+#define PINMUX_GPIO6__FUNC_SCP_SPI1_MO (MTK_PIN_NO(6) | 4)
+#define PINMUX_GPIO6__FUNC_CONN_BPI_BUS12_OLAT1 (MTK_PIN_NO(6) | 6)
+#define PINMUX_GPIO6__FUNC_DBG_MON_A6 (MTK_PIN_NO(6) | 7)
+
+#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 1)
+#define PINMUX_GPIO7__FUNC_SPIM4_A_MI (MTK_PIN_NO(7) | 2)
+#define PINMUX_GPIO7__FUNC_I2SIN0_MCK (MTK_PIN_NO(7) | 3)
+#define PINMUX_GPIO7__FUNC_SCP_SPI1_MI (MTK_PIN_NO(7) | 4)
+#define PINMUX_GPIO7__FUNC_CONN_BPI_BUS13_OLAT2 (MTK_PIN_NO(7) | 6)
+#define PINMUX_GPIO7__FUNC_DBG_MON_A7 (MTK_PIN_NO(7) | 7)
+
+#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define PINMUX_GPIO8__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(8) | 1)
+#define PINMUX_GPIO8__FUNC_SPIM5_A_CSB (MTK_PIN_NO(8) | 2)
+#define PINMUX_GPIO8__FUNC_I2SOUT1_MCK (MTK_PIN_NO(8) | 3)
+#define PINMUX_GPIO8__FUNC_VADSP_UTXD0 (MTK_PIN_NO(8) | 4)
+#define PINMUX_GPIO8__FUNC_CONN_BPI_BUS14_OLAT3 (MTK_PIN_NO(8) | 6)
+#define PINMUX_GPIO8__FUNC_DBG_MON_A8 (MTK_PIN_NO(8) | 7)
+
+#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define PINMUX_GPIO9__FUNC_TP_URXD1_VLP (MTK_PIN_NO(9) | 1)
+#define PINMUX_GPIO9__FUNC_SPIM5_A_CLK (MTK_PIN_NO(9) | 2)
+#define PINMUX_GPIO9__FUNC_I2SOUT1_BCK (MTK_PIN_NO(9) | 3)
+#define PINMUX_GPIO9__FUNC_VADSP_URXD0 (MTK_PIN_NO(9) | 4)
+#define PINMUX_GPIO9__FUNC_CONN_BPI_BUS15_OLAT4 (MTK_PIN_NO(9) | 6)
+#define PINMUX_GPIO9__FUNC_DBG_MON_A9 (MTK_PIN_NO(9) | 7)
+
+#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define PINMUX_GPIO10__FUNC_TP_UCTS1_VLP (MTK_PIN_NO(10) | 1)
+#define PINMUX_GPIO10__FUNC_SPIM5_A_MO (MTK_PIN_NO(10) | 2)
+#define PINMUX_GPIO10__FUNC_I2SOUT1_LRCK (MTK_PIN_NO(10) | 3)
+#define PINMUX_GPIO10__FUNC_SRCLKENAI0 (MTK_PIN_NO(10) | 4)
+#define PINMUX_GPIO10__FUNC_CONN_BPI_BUS16_OLAT5 (MTK_PIN_NO(10) | 6)
+#define PINMUX_GPIO10__FUNC_DBG_MON_A10 (MTK_PIN_NO(10) | 7)
+
+#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define PINMUX_GPIO11__FUNC_TP_URTS1_VLP (MTK_PIN_NO(11) | 1)
+#define PINMUX_GPIO11__FUNC_SPIM5_A_MI (MTK_PIN_NO(11) | 2)
+#define PINMUX_GPIO11__FUNC_I2SOUT1_DO (MTK_PIN_NO(11) | 3)
+#define PINMUX_GPIO11__FUNC_SRCLKENAI1 (MTK_PIN_NO(11) | 4)
+#define PINMUX_GPIO11__FUNC_PWM_vlp (MTK_PIN_NO(11) | 5)
+#define PINMUX_GPIO11__FUNC_DBG_MON_A11 (MTK_PIN_NO(11) | 7)
+
+#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define PINMUX_GPIO12__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(12) | 1)
+#define PINMUX_GPIO12__FUNC_UTXD3 (MTK_PIN_NO(12) | 2)
+#define PINMUX_GPIO12__FUNC_CLKM0 (MTK_PIN_NO(12) | 3)
+#define PINMUX_GPIO12__FUNC_CMFLASH0 (MTK_PIN_NO(12) | 4)
+#define PINMUX_GPIO12__FUNC_ANT_SEL0 (MTK_PIN_NO(12) | 6)
+#define PINMUX_GPIO12__FUNC_DBG_MON_B20 (MTK_PIN_NO(12) | 7)
+
+#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define PINMUX_GPIO13__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(13) | 1)
+#define PINMUX_GPIO13__FUNC_URXD3 (MTK_PIN_NO(13) | 2)
+#define PINMUX_GPIO13__FUNC_CLKM1 (MTK_PIN_NO(13) | 3)
+#define PINMUX_GPIO13__FUNC_CMFLASH1 (MTK_PIN_NO(13) | 4)
+#define PINMUX_GPIO13__FUNC_ANT_SEL1 (MTK_PIN_NO(13) | 6)
+#define PINMUX_GPIO13__FUNC_DBG_MON_B21 (MTK_PIN_NO(13) | 7)
+
+#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define PINMUX_GPIO14__FUNC_TP_UCTS1_VCORE (MTK_PIN_NO(14) | 1)
+#define PINMUX_GPIO14__FUNC_UCTS3 (MTK_PIN_NO(14) | 2)
+#define PINMUX_GPIO14__FUNC_CLKM2 (MTK_PIN_NO(14) | 3)
+#define PINMUX_GPIO14__FUNC_CMFLASH2 (MTK_PIN_NO(14) | 4)
+#define PINMUX_GPIO14__FUNC_ANT_SEL2 (MTK_PIN_NO(14) | 6)
+#define PINMUX_GPIO14__FUNC_DBG_MON_B22 (MTK_PIN_NO(14) | 7)
+
+#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define PINMUX_GPIO15__FUNC_TP_URTS1_VCORE (MTK_PIN_NO(15) | 1)
+#define PINMUX_GPIO15__FUNC_URTS3 (MTK_PIN_NO(15) | 2)
+#define PINMUX_GPIO15__FUNC_CLKM3 (MTK_PIN_NO(15) | 3)
+#define PINMUX_GPIO15__FUNC_CMVREF0 (MTK_PIN_NO(15) | 4)
+#define PINMUX_GPIO15__FUNC_ANT_SEL3 (MTK_PIN_NO(15) | 6)
+#define PINMUX_GPIO15__FUNC_DBG_MON_B23 (MTK_PIN_NO(15) | 7)
+
+#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define PINMUX_GPIO16__FUNC_PWM_0 (MTK_PIN_NO(16) | 1)
+#define PINMUX_GPIO16__FUNC_UCTS2 (MTK_PIN_NO(16) | 2)
+#define PINMUX_GPIO16__FUNC_DP_TX_HPD (MTK_PIN_NO(16) | 3)
+#define PINMUX_GPIO16__FUNC_CMVREF1 (MTK_PIN_NO(16) | 4)
+#define PINMUX_GPIO16__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(16) | 5)
+#define PINMUX_GPIO16__FUNC_ANT_SEL4 (MTK_PIN_NO(16) | 6)
+#define PINMUX_GPIO16__FUNC_DBG_MON_B24 (MTK_PIN_NO(16) | 7)
+
+#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define PINMUX_GPIO17__FUNC_PWM_1 (MTK_PIN_NO(17) | 1)
+#define PINMUX_GPIO17__FUNC_URTS2 (MTK_PIN_NO(17) | 2)
+#define PINMUX_GPIO17__FUNC_EDP_TX_HPD (MTK_PIN_NO(17) | 3)
+#define PINMUX_GPIO17__FUNC_CMVREF2 (MTK_PIN_NO(17) | 4)
+#define PINMUX_GPIO17__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(17) | 5)
+#define PINMUX_GPIO17__FUNC_PMSR_SMAP (MTK_PIN_NO(17) | 6)
+#define PINMUX_GPIO17__FUNC_DBG_MON_B25 (MTK_PIN_NO(17) | 7)
+
+#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define PINMUX_GPIO18__FUNC_CMFLASH0 (MTK_PIN_NO(18) | 1)
+#define PINMUX_GPIO18__FUNC_CMVREF3 (MTK_PIN_NO(18) | 2)
+#define PINMUX_GPIO18__FUNC_UTXD2 (MTK_PIN_NO(18) | 3)
+#define PINMUX_GPIO18__FUNC_DISP_PWM1 (MTK_PIN_NO(18) | 4)
+#define PINMUX_GPIO18__FUNC_I2SIN1_MCK (MTK_PIN_NO(18) | 5)
+#define PINMUX_GPIO18__FUNC_mbistreaden_trigger (MTK_PIN_NO(18) | 6)
+#define PINMUX_GPIO18__FUNC_DBG_MON_A12 (MTK_PIN_NO(18) | 7)
+
+#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define PINMUX_GPIO19__FUNC_CMFLASH1 (MTK_PIN_NO(19) | 1)
+#define PINMUX_GPIO19__FUNC_CMVREF2 (MTK_PIN_NO(19) | 2)
+#define PINMUX_GPIO19__FUNC_URXD2 (MTK_PIN_NO(19) | 3)
+#define PINMUX_GPIO19__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(19) | 4)
+#define PINMUX_GPIO19__FUNC_I2SIN1_BCK (MTK_PIN_NO(19) | 5)
+#define PINMUX_GPIO19__FUNC_mbistwriteen_trigger (MTK_PIN_NO(19) | 6)
+#define PINMUX_GPIO19__FUNC_DBG_MON_A13 (MTK_PIN_NO(19) | 7)
+
+#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define PINMUX_GPIO20__FUNC_CMFLASH2 (MTK_PIN_NO(20) | 1)
+#define PINMUX_GPIO20__FUNC_CMVREF1 (MTK_PIN_NO(20) | 2)
+#define PINMUX_GPIO20__FUNC_UCTS2 (MTK_PIN_NO(20) | 3)
+#define PINMUX_GPIO20__FUNC_PERSTN (MTK_PIN_NO(20) | 4)
+#define PINMUX_GPIO20__FUNC_I2SIN1_LRCK (MTK_PIN_NO(20) | 5)
+#define PINMUX_GPIO20__FUNC_DMIC0_DAT1 (MTK_PIN_NO(20) | 6)
+#define PINMUX_GPIO20__FUNC_DBG_MON_A14 (MTK_PIN_NO(20) | 7)
+
+#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define PINMUX_GPIO21__FUNC_CMFLASH3 (MTK_PIN_NO(21) | 1)
+#define PINMUX_GPIO21__FUNC_CMVREF0 (MTK_PIN_NO(21) | 2)
+#define PINMUX_GPIO21__FUNC_URTS2 (MTK_PIN_NO(21) | 3)
+#define PINMUX_GPIO21__FUNC_CLKREQN (MTK_PIN_NO(21) | 4)
+#define PINMUX_GPIO21__FUNC_I2SIN1_DI (MTK_PIN_NO(21) | 5)
+#define PINMUX_GPIO21__FUNC_DMIC1_DAT1 (MTK_PIN_NO(21) | 6)
+#define PINMUX_GPIO21__FUNC_DBG_MON_A15 (MTK_PIN_NO(21) | 7)
+
+#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define PINMUX_GPIO22__FUNC_CMMCLK0 (MTK_PIN_NO(22) | 1)
+#define PINMUX_GPIO22__FUNC_TP_GPIO4_AO (MTK_PIN_NO(22) | 2)
+
+#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define PINMUX_GPIO23__FUNC_CMMCLK1 (MTK_PIN_NO(23) | 1)
+#define PINMUX_GPIO23__FUNC_TP_GPIO5_AO (MTK_PIN_NO(23) | 2)
+#define PINMUX_GPIO23__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(23) | 3)
+#define PINMUX_GPIO23__FUNC_PWM_vlp (MTK_PIN_NO(23) | 4)
+#define PINMUX_GPIO23__FUNC_SRCLKENAI0 (MTK_PIN_NO(23) | 6)
+
+#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define PINMUX_GPIO24__FUNC_CMMCLK2 (MTK_PIN_NO(24) | 1)
+#define PINMUX_GPIO24__FUNC_TP_GPIO6_AO (MTK_PIN_NO(24) | 2)
+#define PINMUX_GPIO24__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(24) | 3)
+#define PINMUX_GPIO24__FUNC_WAKEN (MTK_PIN_NO(24) | 4)
+#define PINMUX_GPIO24__FUNC_SPMI_P_TRIG_FLAG (MTK_PIN_NO(24) | 5)
+#define PINMUX_GPIO24__FUNC_SRCLKENAI1 (MTK_PIN_NO(24) | 6)
+
+#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define PINMUX_GPIO25__FUNC_LCM_RST (MTK_PIN_NO(25) | 1)
+#define PINMUX_GPIO25__FUNC_DP_TX_HPD (MTK_PIN_NO(25) | 2)
+#define PINMUX_GPIO25__FUNC_CMFLASH3 (MTK_PIN_NO(25) | 3)
+#define PINMUX_GPIO25__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(25) | 4)
+#define PINMUX_GPIO25__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(25) | 5)
+
+#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define PINMUX_GPIO26__FUNC_DSI_TE (MTK_PIN_NO(26) | 1)
+#define PINMUX_GPIO26__FUNC_EDP_TX_HPD (MTK_PIN_NO(26) | 2)
+#define PINMUX_GPIO26__FUNC_CMVREF3 (MTK_PIN_NO(26) | 3)
+#define PINMUX_GPIO26__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(26) | 4)
+#define PINMUX_GPIO26__FUNC_USB_DRVVBUS_3P (MTK_PIN_NO(26) | 5)
+
+#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define PINMUX_GPIO27__FUNC_DP_TX_HPD (MTK_PIN_NO(27) | 1)
+#define PINMUX_GPIO27__FUNC_mbistreaden_trigger (MTK_PIN_NO(27) | 2)
+#define PINMUX_GPIO27__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(27) | 3)
+#define PINMUX_GPIO27__FUNC_TP_UCTS1_VCORE (MTK_PIN_NO(27) | 4)
+#define PINMUX_GPIO27__FUNC_CMVREF4 (MTK_PIN_NO(27) | 5)
+#define PINMUX_GPIO27__FUNC_EXTIF0_ACT (MTK_PIN_NO(27) | 6)
+#define PINMUX_GPIO27__FUNC_ANT_SEL0 (MTK_PIN_NO(27) | 7)
+
+#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define PINMUX_GPIO28__FUNC_EDP_TX_HPD (MTK_PIN_NO(28) | 1)
+#define PINMUX_GPIO28__FUNC_mbistwriteen_trigger (MTK_PIN_NO(28) | 2)
+#define PINMUX_GPIO28__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(28) | 3)
+#define PINMUX_GPIO28__FUNC_TP_URTS1_VCORE (MTK_PIN_NO(28) | 4)
+#define PINMUX_GPIO28__FUNC_EXTIF0_PRI (MTK_PIN_NO(28) | 6)
+#define PINMUX_GPIO28__FUNC_ANT_SEL1 (MTK_PIN_NO(28) | 7)
+
+#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define PINMUX_GPIO29__FUNC_DISP_PWM0 (MTK_PIN_NO(29) | 1)
+#define PINMUX_GPIO29__FUNC_MD32_1_TXD (MTK_PIN_NO(29) | 2)
+#define PINMUX_GPIO29__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(29) | 3)
+#define PINMUX_GPIO29__FUNC_USB_DRVVBUS_4P (MTK_PIN_NO(29) | 5)
+
+#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define PINMUX_GPIO30__FUNC_DISP_PWM1 (MTK_PIN_NO(30) | 1)
+#define PINMUX_GPIO30__FUNC_MD32_1_RXD (MTK_PIN_NO(30) | 2)
+#define PINMUX_GPIO30__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(30) | 3)
+#define PINMUX_GPIO30__FUNC_PMSR_SMAP (MTK_PIN_NO(30) | 5)
+#define PINMUX_GPIO30__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(30) | 6)
+#define PINMUX_GPIO30__FUNC_ANT_SEL2 (MTK_PIN_NO(30) | 7)
+
+#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define PINMUX_GPIO31__FUNC_UTXD0 (MTK_PIN_NO(31) | 1)
+#define PINMUX_GPIO31__FUNC_MD32_0_TXD (MTK_PIN_NO(31) | 2)
+
+#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define PINMUX_GPIO32__FUNC_URXD0 (MTK_PIN_NO(32) | 1)
+#define PINMUX_GPIO32__FUNC_MD32_0_RXD (MTK_PIN_NO(32) | 2)
+
+#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define PINMUX_GPIO33__FUNC_UTXD1 (MTK_PIN_NO(33) | 1)
+#define PINMUX_GPIO33__FUNC_VADSP_UTXD0 (MTK_PIN_NO(33) | 2)
+#define PINMUX_GPIO33__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(33) | 3)
+#define PINMUX_GPIO33__FUNC_MD32_1_TXD (MTK_PIN_NO(33) | 4)
+#define PINMUX_GPIO33__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(33) | 5)
+#define PINMUX_GPIO33__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(33) | 6)
+
+#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define PINMUX_GPIO34__FUNC_URXD1 (MTK_PIN_NO(34) | 1)
+#define PINMUX_GPIO34__FUNC_VADSP_URXD0 (MTK_PIN_NO(34) | 2)
+#define PINMUX_GPIO34__FUNC_TP_URXD1_VLP (MTK_PIN_NO(34) | 3)
+#define PINMUX_GPIO34__FUNC_MD32_1_RXD (MTK_PIN_NO(34) | 4)
+#define PINMUX_GPIO34__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(34) | 5)
+
+#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define PINMUX_GPIO35__FUNC_UTXD2 (MTK_PIN_NO(35) | 1)
+#define PINMUX_GPIO35__FUNC_UCTS1 (MTK_PIN_NO(35) | 2)
+#define PINMUX_GPIO35__FUNC_TP_UCTS1_VLP (MTK_PIN_NO(35) | 3)
+#define PINMUX_GPIO35__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(35) | 4)
+#define PINMUX_GPIO35__FUNC_VADSP_UTXD0 (MTK_PIN_NO(35) | 5)
+#define PINMUX_GPIO35__FUNC_CONN_BT_TXD (MTK_PIN_NO(35) | 6)
+
+#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define PINMUX_GPIO36__FUNC_URXD2 (MTK_PIN_NO(36) | 1)
+#define PINMUX_GPIO36__FUNC_URTS1 (MTK_PIN_NO(36) | 2)
+#define PINMUX_GPIO36__FUNC_TP_URTS1_VLP (MTK_PIN_NO(36) | 3)
+#define PINMUX_GPIO36__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(36) | 4)
+#define PINMUX_GPIO36__FUNC_VADSP_URXD0 (MTK_PIN_NO(36) | 5)
+
+#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define PINMUX_GPIO37__FUNC_UTXD3 (MTK_PIN_NO(37) | 1)
+#define PINMUX_GPIO37__FUNC_UCTS0 (MTK_PIN_NO(37) | 2)
+#define PINMUX_GPIO37__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(37) | 3)
+#define PINMUX_GPIO37__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(37) | 4)
+#define PINMUX_GPIO37__FUNC_MD32_0_TXD (MTK_PIN_NO(37) | 6)
+#define PINMUX_GPIO37__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(37) | 7)
+
+#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define PINMUX_GPIO38__FUNC_URXD3 (MTK_PIN_NO(38) | 1)
+#define PINMUX_GPIO38__FUNC_URTS0 (MTK_PIN_NO(38) | 2)
+#define PINMUX_GPIO38__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(38) | 3)
+#define PINMUX_GPIO38__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(38) | 4)
+#define PINMUX_GPIO38__FUNC_MD32_0_RXD (MTK_PIN_NO(38) | 6)
+#define PINMUX_GPIO38__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(38) | 7)
+
+#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define PINMUX_GPIO39__FUNC_JTMS_SEL1 (MTK_PIN_NO(39) | 1)
+
+#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define PINMUX_GPIO40__FUNC_JTCK_SEL1 (MTK_PIN_NO(40) | 1)
+
+#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define PINMUX_GPIO41__FUNC_JTDI_SEL1 (MTK_PIN_NO(41) | 1)
+
+#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define PINMUX_GPIO42__FUNC_JTDO_SEL1 (MTK_PIN_NO(42) | 1)
+
+#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define PINMUX_GPIO43__FUNC_JTRSTn_SEL1 (MTK_PIN_NO(43) | 1)
+
+#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define PINMUX_GPIO44__FUNC_KPCOL0 (MTK_PIN_NO(44) | 1)
+
+#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define PINMUX_GPIO45__FUNC_KPCOL1 (MTK_PIN_NO(45) | 1)
+#define PINMUX_GPIO45__FUNC_TP_GPIO0_AO (MTK_PIN_NO(45) | 2)
+#define PINMUX_GPIO45__FUNC_SRCLKENAI1 (MTK_PIN_NO(45) | 3)
+#define PINMUX_GPIO45__FUNC_DBG_MON_A31 (MTK_PIN_NO(45) | 7)
+
+#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define PINMUX_GPIO46__FUNC_KPROW0 (MTK_PIN_NO(46) | 1)
+#define PINMUX_GPIO46__FUNC_TP_GPIO1_AO (MTK_PIN_NO(46) | 2)
+
+#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define PINMUX_GPIO47__FUNC_KPROW1 (MTK_PIN_NO(47) | 1)
+#define PINMUX_GPIO47__FUNC_TP_GPIO2_AO (MTK_PIN_NO(47) | 2)
+#define PINMUX_GPIO47__FUNC_SRCLKENAI0 (MTK_PIN_NO(47) | 3)
+#define PINMUX_GPIO47__FUNC_DBG_MON_A32 (MTK_PIN_NO(47) | 7)
+
+#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define PINMUX_GPIO48__FUNC_WAKEN (MTK_PIN_NO(48) | 1)
+#define PINMUX_GPIO48__FUNC_TP_GPIO3_AO (MTK_PIN_NO(48) | 2)
+#define PINMUX_GPIO48__FUNC_SPMI_P_TRIG_FLAG (MTK_PIN_NO(48) | 3)
+
+#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define PINMUX_GPIO49__FUNC_PERSTN (MTK_PIN_NO(49) | 1)
+#define PINMUX_GPIO49__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(49) | 2)
+#define PINMUX_GPIO49__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(49) | 3)
+#define PINMUX_GPIO49__FUNC_ANT_SEL3 (MTK_PIN_NO(49) | 7)
+
+#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define PINMUX_GPIO50__FUNC_CLKREQN (MTK_PIN_NO(50) | 1)
+#define PINMUX_GPIO50__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(50) | 2)
+#define PINMUX_GPIO50__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(50) | 3)
+#define PINMUX_GPIO50__FUNC_ANT_SEL4 (MTK_PIN_NO(50) | 7)
+
+#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define PINMUX_GPIO51__FUNC_SCP_SCL0 (MTK_PIN_NO(51) | 1)
+#define PINMUX_GPIO51__FUNC_SCL0 (MTK_PIN_NO(51) | 2)
+
+#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define PINMUX_GPIO52__FUNC_SCP_SDA0 (MTK_PIN_NO(52) | 1)
+#define PINMUX_GPIO52__FUNC_SDA0 (MTK_PIN_NO(52) | 2)
+
+#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define PINMUX_GPIO53__FUNC_SCP_SCL1 (MTK_PIN_NO(53) | 1)
+#define PINMUX_GPIO53__FUNC_SCL1 (MTK_PIN_NO(53) | 2)
+
+#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define PINMUX_GPIO54__FUNC_SCP_SDA1 (MTK_PIN_NO(54) | 1)
+#define PINMUX_GPIO54__FUNC_SDA1 (MTK_PIN_NO(54) | 2)
+
+#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define PINMUX_GPIO55__FUNC_SCL2 (MTK_PIN_NO(55) | 1)
+#define PINMUX_GPIO55__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(55) | 2)
+#define PINMUX_GPIO55__FUNC_SSUSB_U2SIF_SCL (MTK_PIN_NO(55) | 3)
+
+#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define PINMUX_GPIO56__FUNC_SDA2 (MTK_PIN_NO(56) | 1)
+#define PINMUX_GPIO56__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(56) | 2)
+#define PINMUX_GPIO56__FUNC_SSUSB_U2SIF_SDA (MTK_PIN_NO(56) | 3)
+
+#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define PINMUX_GPIO57__FUNC_SCL3 (MTK_PIN_NO(57) | 1)
+#define PINMUX_GPIO57__FUNC_PCIE_PHY_I2C_SCL (MTK_PIN_NO(57) | 2)
+#define PINMUX_GPIO57__FUNC_SSUSB_U2SIF_SCL_1P (MTK_PIN_NO(57) | 3)
+
+#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define PINMUX_GPIO58__FUNC_SDA3 (MTK_PIN_NO(58) | 1)
+#define PINMUX_GPIO58__FUNC_PCIE_PHY_I2C_SDA (MTK_PIN_NO(58) | 2)
+#define PINMUX_GPIO58__FUNC_SSUSB_U2SIF_SDA_1P (MTK_PIN_NO(58) | 3)
+
+#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define PINMUX_GPIO59__FUNC_SCL4 (MTK_PIN_NO(59) | 1)
+#define PINMUX_GPIO59__FUNC_SSUSB_U3PHY_I2C_SCL (MTK_PIN_NO(59) | 2)
+
+#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define PINMUX_GPIO60__FUNC_SDA4 (MTK_PIN_NO(60) | 1)
+#define PINMUX_GPIO60__FUNC_SSUSB_U3PHY_I2C_SDA (MTK_PIN_NO(60) | 2)
+
+#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define PINMUX_GPIO61__FUNC_SCL5 (MTK_PIN_NO(61) | 1)
+#define PINMUX_GPIO61__FUNC_SSPXTP_U3PHY_I2C_SCL (MTK_PIN_NO(61) | 2)
+
+#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define PINMUX_GPIO62__FUNC_SDA5 (MTK_PIN_NO(62) | 1)
+#define PINMUX_GPIO62__FUNC_SSPXTP_U3PHY_I2C_SDA (MTK_PIN_NO(62) | 2)
+
+#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define PINMUX_GPIO63__FUNC_SCL6 (MTK_PIN_NO(63) | 1)
+
+#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define PINMUX_GPIO64__FUNC_SDA6 (MTK_PIN_NO(64) | 1)
+
+#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define PINMUX_GPIO65__FUNC_SCL7 (MTK_PIN_NO(65) | 1)
+
+#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define PINMUX_GPIO66__FUNC_SDA7 (MTK_PIN_NO(66) | 1)
+
+#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define PINMUX_GPIO67__FUNC_SCL8 (MTK_PIN_NO(67) | 1)
+
+#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define PINMUX_GPIO68__FUNC_SDA8 (MTK_PIN_NO(68) | 1)
+
+#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define PINMUX_GPIO69__FUNC_SPIM0_CSB (MTK_PIN_NO(69) | 1)
+#define PINMUX_GPIO69__FUNC_SCP_SPI0_CS (MTK_PIN_NO(69) | 2)
+#define PINMUX_GPIO69__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(69) | 3)
+#define PINMUX_GPIO69__FUNC_VADSP_JTAG0_TMS (MTK_PIN_NO(69) | 4)
+#define PINMUX_GPIO69__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(69) | 5)
+#define PINMUX_GPIO69__FUNC_SSPM_JTAG_TMS_VLP (MTK_PIN_NO(69) | 6)
+#define PINMUX_GPIO69__FUNC_SCP_JTAG0_TMS_VLP (MTK_PIN_NO(69) | 7)
+
+#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define PINMUX_GPIO70__FUNC_SPIM0_CLK (MTK_PIN_NO(70) | 1)
+#define PINMUX_GPIO70__FUNC_SCP_SPI0_CK (MTK_PIN_NO(70) | 2)
+#define PINMUX_GPIO70__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(70) | 3)
+#define PINMUX_GPIO70__FUNC_VADSP_JTAG0_TCK (MTK_PIN_NO(70) | 4)
+#define PINMUX_GPIO70__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(70) | 5)
+#define PINMUX_GPIO70__FUNC_SSPM_JTAG_TCK_VLP (MTK_PIN_NO(70) | 6)
+#define PINMUX_GPIO70__FUNC_SCP_JTAG0_TCK_VLP (MTK_PIN_NO(70) | 7)
+
+#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define PINMUX_GPIO71__FUNC_SPIM0_MO (MTK_PIN_NO(71) | 1)
+#define PINMUX_GPIO71__FUNC_SCP_SPI0_MO (MTK_PIN_NO(71) | 2)
+#define PINMUX_GPIO71__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(71) | 3)
+#define PINMUX_GPIO71__FUNC_VADSP_JTAG0_TDI (MTK_PIN_NO(71) | 4)
+#define PINMUX_GPIO71__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(71) | 5)
+#define PINMUX_GPIO71__FUNC_SSPM_JTAG_TDI_VLP (MTK_PIN_NO(71) | 6)
+#define PINMUX_GPIO71__FUNC_SCP_JTAG0_TDI_VLP (MTK_PIN_NO(71) | 7)
+
+#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define PINMUX_GPIO72__FUNC_SPIM0_MI (MTK_PIN_NO(72) | 1)
+#define PINMUX_GPIO72__FUNC_SCP_SPI0_MI (MTK_PIN_NO(72) | 2)
+#define PINMUX_GPIO72__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(72) | 3)
+#define PINMUX_GPIO72__FUNC_VADSP_JTAG0_TDO (MTK_PIN_NO(72) | 4)
+#define PINMUX_GPIO72__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(72) | 5)
+#define PINMUX_GPIO72__FUNC_SSPM_JTAG_TDO_VLP (MTK_PIN_NO(72) | 6)
+#define PINMUX_GPIO72__FUNC_SCP_JTAG0_TDO_VLP (MTK_PIN_NO(72) | 7)
+
+#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define PINMUX_GPIO73__FUNC_SPIM1_CSB (MTK_PIN_NO(73) | 1)
+#define PINMUX_GPIO73__FUNC_SCP_SPI1_CS (MTK_PIN_NO(73) | 2)
+#define PINMUX_GPIO73__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(73) | 3)
+#define PINMUX_GPIO73__FUNC_VADSP_JTAG0_TRSTN (MTK_PIN_NO(73) | 4)
+#define PINMUX_GPIO73__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(73) | 5)
+#define PINMUX_GPIO73__FUNC_SSPM_JTAG_TRSTN_VLP (MTK_PIN_NO(73) | 6)
+#define PINMUX_GPIO73__FUNC_SCP_JTAG0_TRSTN_VLP (MTK_PIN_NO(73) | 7)
+
+#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define PINMUX_GPIO74__FUNC_SPIM1_CLK (MTK_PIN_NO(74) | 1)
+#define PINMUX_GPIO74__FUNC_SCP_SPI1_CK (MTK_PIN_NO(74) | 2)
+
+#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define PINMUX_GPIO75__FUNC_SPIM1_MO (MTK_PIN_NO(75) | 1)
+#define PINMUX_GPIO75__FUNC_SCP_SPI1_MO (MTK_PIN_NO(75) | 2)
+
+#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define PINMUX_GPIO76__FUNC_SPIM1_MI (MTK_PIN_NO(76) | 1)
+#define PINMUX_GPIO76__FUNC_SCP_SPI1_MI (MTK_PIN_NO(76) | 2)
+
+#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define PINMUX_GPIO77__FUNC_SPIM2_CSB (MTK_PIN_NO(77) | 1)
+#define PINMUX_GPIO77__FUNC_PCM0_SYNC (MTK_PIN_NO(77) | 2)
+#define PINMUX_GPIO77__FUNC_SSUSB_U2SIF_SCL (MTK_PIN_NO(77) | 3)
+#define PINMUX_GPIO77__FUNC_DBG_MON_A27 (MTK_PIN_NO(77) | 7)
+
+#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define PINMUX_GPIO78__FUNC_SPIM2_CLK (MTK_PIN_NO(78) | 1)
+#define PINMUX_GPIO78__FUNC_PCM0_CLK (MTK_PIN_NO(78) | 2)
+#define PINMUX_GPIO78__FUNC_SSUSB_U2SIF_SDA (MTK_PIN_NO(78) | 3)
+#define PINMUX_GPIO78__FUNC_DBG_MON_A28 (MTK_PIN_NO(78) | 7)
+
+#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define PINMUX_GPIO79__FUNC_SPIM2_MO (MTK_PIN_NO(79) | 1)
+#define PINMUX_GPIO79__FUNC_PCM0_DO (MTK_PIN_NO(79) | 2)
+#define PINMUX_GPIO79__FUNC_SSUSB_U2SIF_SCL_1P (MTK_PIN_NO(79) | 3)
+#define PINMUX_GPIO79__FUNC_DBG_MON_A29 (MTK_PIN_NO(79) | 7)
+
+#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define PINMUX_GPIO80__FUNC_SPIM2_MI (MTK_PIN_NO(80) | 1)
+#define PINMUX_GPIO80__FUNC_PCM0_DI (MTK_PIN_NO(80) | 2)
+#define PINMUX_GPIO80__FUNC_SSUSB_U2SIF_SDA_1P (MTK_PIN_NO(80) | 3)
+#define PINMUX_GPIO80__FUNC_DBG_MON_A30 (MTK_PIN_NO(80) | 7)
+
+#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define PINMUX_GPIO81__FUNC_IDDIG (MTK_PIN_NO(81) | 1)
+#define PINMUX_GPIO81__FUNC_DBG_MON_B32 (MTK_PIN_NO(81) | 7)
+
+#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define PINMUX_GPIO82__FUNC_USB_DRVVBUS (MTK_PIN_NO(82) | 1)
+
+#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define PINMUX_GPIO83__FUNC_VBUSVALID (MTK_PIN_NO(83) | 1)
+
+#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define PINMUX_GPIO84__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(84) | 1)
+#define PINMUX_GPIO84__FUNC_DBG_MON_A16 (MTK_PIN_NO(84) | 7)
+
+#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
+#define PINMUX_GPIO85__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(85) | 1)
+#define PINMUX_GPIO85__FUNC_DBG_MON_A17 (MTK_PIN_NO(85) | 7)
+
+#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
+#define PINMUX_GPIO86__FUNC_USB_DRVVBUS_3P (MTK_PIN_NO(86) | 1)
+#define PINMUX_GPIO86__FUNC_DBG_MON_A18 (MTK_PIN_NO(86) | 7)
+
+#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
+#define PINMUX_GPIO87__FUNC_USB_DRVVBUS_4P (MTK_PIN_NO(87) | 1)
+#define PINMUX_GPIO87__FUNC_CMVREF4 (MTK_PIN_NO(87) | 6)
+#define PINMUX_GPIO87__FUNC_DBG_MON_A19 (MTK_PIN_NO(87) | 7)
+
+#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
+#define PINMUX_GPIO88__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(88) | 1)
+
+#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
+#define PINMUX_GPIO89__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(89) | 1)
+
+#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
+#define PINMUX_GPIO90__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(90) | 1)
+
+#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
+#define PINMUX_GPIO91__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(91) | 1)
+
+#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
+#define PINMUX_GPIO92__FUNC_SRCLKENA0 (MTK_PIN_NO(92) | 1)
+
+#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
+#define PINMUX_GPIO93__FUNC_SRCLKENA1 (MTK_PIN_NO(93) | 1)
+
+#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
+#define PINMUX_GPIO94__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(94) | 1)
+
+#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define PINMUX_GPIO95__FUNC_RTC32K_CK (MTK_PIN_NO(95) | 1)
+
+#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define PINMUX_GPIO96__FUNC_WATCHDOG (MTK_PIN_NO(96) | 1)
+
+#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define PINMUX_GPIO97__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(97) | 1)
+
+#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define PINMUX_GPIO98__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(98) | 1)
+
+#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define PINMUX_GPIO99__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(99) | 1)
+
+#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define PINMUX_GPIO100__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(100) | 1)
+
+#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define PINMUX_GPIO101__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(101) | 1)
+
+#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define PINMUX_GPIO102__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(102) | 1)
+
+#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define PINMUX_GPIO103__FUNC_I2SIN0_MCK (MTK_PIN_NO(103) | 1)
+#define PINMUX_GPIO103__FUNC_SPIM3_B_CSB (MTK_PIN_NO(103) | 2)
+#define PINMUX_GPIO103__FUNC_APU_JTAG_TMS (MTK_PIN_NO(103) | 3)
+#define PINMUX_GPIO103__FUNC_SCP_JTAG0_TMS_VCORE (MTK_PIN_NO(103) | 4)
+#define PINMUX_GPIO103__FUNC_CONN_WF_MCU_TMS (MTK_PIN_NO(103) | 5)
+#define PINMUX_GPIO103__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(103) | 6)
+#define PINMUX_GPIO103__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(103) | 7)
+
+#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define PINMUX_GPIO104__FUNC_I2SIN0_BCK (MTK_PIN_NO(104) | 1)
+#define PINMUX_GPIO104__FUNC_SPIM3_B_CLK (MTK_PIN_NO(104) | 2)
+#define PINMUX_GPIO104__FUNC_APU_JTAG_TCK (MTK_PIN_NO(104) | 3)
+#define PINMUX_GPIO104__FUNC_SCP_JTAG0_TCK_VCORE (MTK_PIN_NO(104) | 4)
+#define PINMUX_GPIO104__FUNC_CONN_WF_MCU_TCK (MTK_PIN_NO(104) | 5)
+#define PINMUX_GPIO104__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(104) | 6)
+#define PINMUX_GPIO104__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(104) | 7)
+
+#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define PINMUX_GPIO105__FUNC_I2SIN0_LRCK (MTK_PIN_NO(105) | 1)
+#define PINMUX_GPIO105__FUNC_SPIM3_B_MO (MTK_PIN_NO(105) | 2)
+#define PINMUX_GPIO105__FUNC_APU_JTAG_TDI (MTK_PIN_NO(105) | 3)
+#define PINMUX_GPIO105__FUNC_SCP_JTAG0_TDI_VCORE (MTK_PIN_NO(105) | 4)
+#define PINMUX_GPIO105__FUNC_CONN_WF_MCU_TDI (MTK_PIN_NO(105) | 5)
+#define PINMUX_GPIO105__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(105) | 6)
+#define PINMUX_GPIO105__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(105) | 7)
+
+#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define PINMUX_GPIO106__FUNC_I2SIN0_DI (MTK_PIN_NO(106) | 1)
+#define PINMUX_GPIO106__FUNC_SPIM3_B_MI (MTK_PIN_NO(106) | 2)
+#define PINMUX_GPIO106__FUNC_APU_JTAG_TDO (MTK_PIN_NO(106) | 3)
+#define PINMUX_GPIO106__FUNC_SCP_JTAG0_TDO_VCORE (MTK_PIN_NO(106) | 4)
+#define PINMUX_GPIO106__FUNC_CONN_WF_MCU_TDO (MTK_PIN_NO(106) | 5)
+#define PINMUX_GPIO106__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(106) | 6)
+#define PINMUX_GPIO106__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(106) | 7)
+
+#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define PINMUX_GPIO107__FUNC_I2SOUT0_MCK (MTK_PIN_NO(107) | 1)
+#define PINMUX_GPIO107__FUNC_SPIM4_B_CSB (MTK_PIN_NO(107) | 2)
+#define PINMUX_GPIO107__FUNC_APU_JTAG_TRST (MTK_PIN_NO(107) | 3)
+#define PINMUX_GPIO107__FUNC_SCP_JTAG0_TRSTN_VCORE (MTK_PIN_NO(107) | 4)
+#define PINMUX_GPIO107__FUNC_CONN_WF_MCU_TRST_B (MTK_PIN_NO(107) | 5)
+#define PINMUX_GPIO107__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(107) | 6)
+#define PINMUX_GPIO107__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(107) | 7)
+
+#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define PINMUX_GPIO108__FUNC_I2SOUT0_BCK (MTK_PIN_NO(108) | 1)
+#define PINMUX_GPIO108__FUNC_SPIM4_B_CLK (MTK_PIN_NO(108) | 2)
+#define PINMUX_GPIO108__FUNC_EXTIF0_ACT (MTK_PIN_NO(108) | 3)
+#define PINMUX_GPIO108__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(108) | 4)
+#define PINMUX_GPIO108__FUNC_CLKM2 (MTK_PIN_NO(108) | 6)
+#define PINMUX_GPIO108__FUNC_DBG_MON_A20 (MTK_PIN_NO(108) | 7)
+
+#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define PINMUX_GPIO109__FUNC_I2SOUT0_LRCK (MTK_PIN_NO(109) | 1)
+#define PINMUX_GPIO109__FUNC_SPIM4_B_MO (MTK_PIN_NO(109) | 2)
+#define PINMUX_GPIO109__FUNC_EXTIF0_PRI (MTK_PIN_NO(109) | 3)
+#define PINMUX_GPIO109__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(109) | 4)
+#define PINMUX_GPIO109__FUNC_CLKM3 (MTK_PIN_NO(109) | 6)
+#define PINMUX_GPIO109__FUNC_DBG_MON_A21 (MTK_PIN_NO(109) | 7)
+
+#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define PINMUX_GPIO110__FUNC_I2SOUT0_DO (MTK_PIN_NO(110) | 1)
+#define PINMUX_GPIO110__FUNC_SPIM4_B_MI (MTK_PIN_NO(110) | 2)
+#define PINMUX_GPIO110__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(110) | 3)
+#define PINMUX_GPIO110__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(110) | 4)
+#define PINMUX_GPIO110__FUNC_DBG_MON_A22 (MTK_PIN_NO(110) | 7)
+
+#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define PINMUX_GPIO111__FUNC_DMIC0_CLK (MTK_PIN_NO(111) | 1)
+#define PINMUX_GPIO111__FUNC_I2SIN1_MCK (MTK_PIN_NO(111) | 2)
+#define PINMUX_GPIO111__FUNC_I2SOUT1_MCK (MTK_PIN_NO(111) | 3)
+#define PINMUX_GPIO111__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(111) | 4)
+#define PINMUX_GPIO111__FUNC_CONN_MIPI0_SDATA (MTK_PIN_NO(111) | 6)
+#define PINMUX_GPIO111__FUNC_DBG_MON_A23 (MTK_PIN_NO(111) | 7)
+
+#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define PINMUX_GPIO112__FUNC_DMIC0_DAT0 (MTK_PIN_NO(112) | 1)
+#define PINMUX_GPIO112__FUNC_I2SIN1_BCK (MTK_PIN_NO(112) | 2)
+#define PINMUX_GPIO112__FUNC_I2SOUT1_BCK (MTK_PIN_NO(112) | 3)
+#define PINMUX_GPIO112__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(112) | 4)
+#define PINMUX_GPIO112__FUNC_CONN_MIPI0_SCLK (MTK_PIN_NO(112) | 6)
+#define PINMUX_GPIO112__FUNC_DBG_MON_A24 (MTK_PIN_NO(112) | 7)
+
+#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define PINMUX_GPIO113__FUNC_DMIC1_CLK (MTK_PIN_NO(113) | 1)
+#define PINMUX_GPIO113__FUNC_I2SIN1_LRCK (MTK_PIN_NO(113) | 2)
+#define PINMUX_GPIO113__FUNC_I2SOUT1_LRCK (MTK_PIN_NO(113) | 3)
+#define PINMUX_GPIO113__FUNC_PMSR_SMAP (MTK_PIN_NO(113) | 4)
+#define PINMUX_GPIO113__FUNC_CONN_MIPI1_SDATA (MTK_PIN_NO(113) | 6)
+#define PINMUX_GPIO113__FUNC_DBG_MON_A25 (MTK_PIN_NO(113) | 7)
+
+#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define PINMUX_GPIO114__FUNC_DMIC1_DAT0 (MTK_PIN_NO(114) | 1)
+#define PINMUX_GPIO114__FUNC_I2SIN1_DI (MTK_PIN_NO(114) | 2)
+#define PINMUX_GPIO114__FUNC_I2SOUT1_DO (MTK_PIN_NO(114) | 3)
+#define PINMUX_GPIO114__FUNC_CONN_MIPI1_SCLK (MTK_PIN_NO(114) | 6)
+#define PINMUX_GPIO114__FUNC_DBG_MON_A26 (MTK_PIN_NO(114) | 7)
+
+#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define PINMUX_GPIO115__FUNC_PCM0_CLK (MTK_PIN_NO(115) | 1)
+#define PINMUX_GPIO115__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(115) | 2)
+#define PINMUX_GPIO115__FUNC_PCIE_PHY_I2C_SCL (MTK_PIN_NO(115) | 3)
+#define PINMUX_GPIO115__FUNC_SSUSB_U3PHY_I2C_SCL (MTK_PIN_NO(115) | 4)
+#define PINMUX_GPIO115__FUNC_CMFLASH0 (MTK_PIN_NO(115) | 6)
+#define PINMUX_GPIO115__FUNC_EXTIF0_ACT (MTK_PIN_NO(115) | 7)
+
+#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define PINMUX_GPIO116__FUNC_PCM0_SYNC (MTK_PIN_NO(116) | 1)
+#define PINMUX_GPIO116__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(116) | 2)
+#define PINMUX_GPIO116__FUNC_PCIE_PHY_I2C_SDA (MTK_PIN_NO(116) | 3)
+#define PINMUX_GPIO116__FUNC_SSUSB_U3PHY_I2C_SDA (MTK_PIN_NO(116) | 4)
+#define PINMUX_GPIO116__FUNC_CMFLASH1 (MTK_PIN_NO(116) | 6)
+#define PINMUX_GPIO116__FUNC_EXTIF0_PRI (MTK_PIN_NO(116) | 7)
+
+#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define PINMUX_GPIO117__FUNC_PCM0_DI (MTK_PIN_NO(117) | 1)
+#define PINMUX_GPIO117__FUNC_USB_DRVVBUS_3P (MTK_PIN_NO(117) | 2)
+#define PINMUX_GPIO117__FUNC_DP_TX_HPD (MTK_PIN_NO(117) | 3)
+#define PINMUX_GPIO117__FUNC_SSPXTP_U3PHY_I2C_SCL (MTK_PIN_NO(117) | 4)
+#define PINMUX_GPIO117__FUNC_CMVREF0 (MTK_PIN_NO(117) | 6)
+#define PINMUX_GPIO117__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(117) | 7)
+
+#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define PINMUX_GPIO118__FUNC_PCM0_DO (MTK_PIN_NO(118) | 1)
+#define PINMUX_GPIO118__FUNC_USB_DRVVBUS_4P (MTK_PIN_NO(118) | 2)
+#define PINMUX_GPIO118__FUNC_EDP_TX_HPD (MTK_PIN_NO(118) | 3)
+#define PINMUX_GPIO118__FUNC_SSPXTP_U3PHY_I2C_SDA (MTK_PIN_NO(118) | 4)
+#define PINMUX_GPIO118__FUNC_CMVREF1 (MTK_PIN_NO(118) | 6)
+
+#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define PINMUX_GPIO119__FUNC_GBE_TXD3 (MTK_PIN_NO(119) | 1)
+#define PINMUX_GPIO119__FUNC_DMIC0_CLK (MTK_PIN_NO(119) | 2)
+#define PINMUX_GPIO119__FUNC_LVTS_FOUT (MTK_PIN_NO(119) | 3)
+#define PINMUX_GPIO119__FUNC_CONN_BGF_MCU_TMS (MTK_PIN_NO(119) | 4)
+#define PINMUX_GPIO119__FUNC_UDI_TMS (MTK_PIN_NO(119) | 5)
+#define PINMUX_GPIO119__FUNC_ANT_SEL5 (MTK_PIN_NO(119) | 6)
+#define PINMUX_GPIO119__FUNC_DBG_MON_B0 (MTK_PIN_NO(119) | 7)
+
+#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define PINMUX_GPIO120__FUNC_GBE_TXD2 (MTK_PIN_NO(120) | 1)
+#define PINMUX_GPIO120__FUNC_DMIC0_DAT0 (MTK_PIN_NO(120) | 2)
+#define PINMUX_GPIO120__FUNC_LVTS_SDO (MTK_PIN_NO(120) | 3)
+#define PINMUX_GPIO120__FUNC_CONN_BGF_MCU_TCK (MTK_PIN_NO(120) | 4)
+#define PINMUX_GPIO120__FUNC_UDI_TCK (MTK_PIN_NO(120) | 5)
+#define PINMUX_GPIO120__FUNC_ANT_SEL6 (MTK_PIN_NO(120) | 6)
+#define PINMUX_GPIO120__FUNC_DBG_MON_B1 (MTK_PIN_NO(120) | 7)
+
+#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define PINMUX_GPIO121__FUNC_GBE_TXD1 (MTK_PIN_NO(121) | 1)
+#define PINMUX_GPIO121__FUNC_DMIC0_DAT1 (MTK_PIN_NO(121) | 2)
+#define PINMUX_GPIO121__FUNC_LVTS_26M (MTK_PIN_NO(121) | 3)
+#define PINMUX_GPIO121__FUNC_CONN_BGF_MCU_TDI (MTK_PIN_NO(121) | 4)
+#define PINMUX_GPIO121__FUNC_UDI_TDI (MTK_PIN_NO(121) | 5)
+#define PINMUX_GPIO121__FUNC_ANT_SEL7 (MTK_PIN_NO(121) | 6)
+#define PINMUX_GPIO121__FUNC_DBG_MON_B2 (MTK_PIN_NO(121) | 7)
+
+#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define PINMUX_GPIO122__FUNC_GBE_TXD0 (MTK_PIN_NO(122) | 1)
+#define PINMUX_GPIO122__FUNC_DMIC1_CLK (MTK_PIN_NO(122) | 2)
+#define PINMUX_GPIO122__FUNC_LVTS_SCF (MTK_PIN_NO(122) | 3)
+#define PINMUX_GPIO122__FUNC_CONN_BGF_MCU_TDO (MTK_PIN_NO(122) | 4)
+#define PINMUX_GPIO122__FUNC_UDI_TDO (MTK_PIN_NO(122) | 5)
+#define PINMUX_GPIO122__FUNC_ANT_SEL8 (MTK_PIN_NO(122) | 6)
+#define PINMUX_GPIO122__FUNC_DBG_MON_B3 (MTK_PIN_NO(122) | 7)
+
+#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define PINMUX_GPIO123__FUNC_GBE_RXD3 (MTK_PIN_NO(123) | 1)
+#define PINMUX_GPIO123__FUNC_DMIC1_DAT0 (MTK_PIN_NO(123) | 2)
+#define PINMUX_GPIO123__FUNC_LVTS_SCK (MTK_PIN_NO(123) | 3)
+#define PINMUX_GPIO123__FUNC_CONN_BGF_MCU_TRST_B (MTK_PIN_NO(123) | 4)
+#define PINMUX_GPIO123__FUNC_UDI_NTRST (MTK_PIN_NO(123) | 5)
+#define PINMUX_GPIO123__FUNC_ANT_SEL9 (MTK_PIN_NO(123) | 6)
+#define PINMUX_GPIO123__FUNC_DBG_MON_B4 (MTK_PIN_NO(123) | 7)
+
+#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define PINMUX_GPIO124__FUNC_GBE_RXD2 (MTK_PIN_NO(124) | 1)
+#define PINMUX_GPIO124__FUNC_DMIC1_DAT1 (MTK_PIN_NO(124) | 2)
+#define PINMUX_GPIO124__FUNC_LVTS_SDI (MTK_PIN_NO(124) | 3)
+#define PINMUX_GPIO124__FUNC_CONN_WF_MCU_TMS (MTK_PIN_NO(124) | 4)
+#define PINMUX_GPIO124__FUNC_SCP_JTAG0_TMS_VCORE (MTK_PIN_NO(124) | 5)
+#define PINMUX_GPIO124__FUNC_ANT_SEL10 (MTK_PIN_NO(124) | 6)
+#define PINMUX_GPIO124__FUNC_DBG_MON_B5 (MTK_PIN_NO(124) | 7)
+
+#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define PINMUX_GPIO125__FUNC_GBE_RXD1 (MTK_PIN_NO(125) | 1)
+#define PINMUX_GPIO125__FUNC_CLKM2 (MTK_PIN_NO(125) | 2)
+#define PINMUX_GPIO125__FUNC_CONN_WF_MCU_TCK (MTK_PIN_NO(125) | 4)
+#define PINMUX_GPIO125__FUNC_SCP_JTAG0_TCK_VCORE (MTK_PIN_NO(125) | 5)
+#define PINMUX_GPIO125__FUNC_ANT_SEL11 (MTK_PIN_NO(125) | 6)
+#define PINMUX_GPIO125__FUNC_DBG_MON_B6 (MTK_PIN_NO(125) | 7)
+
+#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define PINMUX_GPIO126__FUNC_GBE_RXD0 (MTK_PIN_NO(126) | 1)
+#define PINMUX_GPIO126__FUNC_CLKM3 (MTK_PIN_NO(126) | 2)
+#define PINMUX_GPIO126__FUNC_CONN_WF_MCU_TDI (MTK_PIN_NO(126) | 4)
+#define PINMUX_GPIO126__FUNC_SCP_JTAG0_TDI_VCORE (MTK_PIN_NO(126) | 5)
+#define PINMUX_GPIO126__FUNC_ANT_SEL12 (MTK_PIN_NO(126) | 6)
+#define PINMUX_GPIO126__FUNC_DBG_MON_B7 (MTK_PIN_NO(126) | 7)
+
+#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
+#define PINMUX_GPIO127__FUNC_GBE_TXC (MTK_PIN_NO(127) | 1)
+#define PINMUX_GPIO127__FUNC_I2SIN1_MCK (MTK_PIN_NO(127) | 2)
+#define PINMUX_GPIO127__FUNC_CONN_WF_MCU_TDO (MTK_PIN_NO(127) | 4)
+#define PINMUX_GPIO127__FUNC_SCP_JTAG0_TDO_VCORE (MTK_PIN_NO(127) | 5)
+#define PINMUX_GPIO127__FUNC_ANT_SEL13 (MTK_PIN_NO(127) | 6)
+#define PINMUX_GPIO127__FUNC_DBG_MON_B8 (MTK_PIN_NO(127) | 7)
+
+#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
+#define PINMUX_GPIO128__FUNC_GBE_RXC (MTK_PIN_NO(128) | 1)
+#define PINMUX_GPIO128__FUNC_I2SIN1_BCK (MTK_PIN_NO(128) | 2)
+#define PINMUX_GPIO128__FUNC_CONN_WF_MCU_TRST_B (MTK_PIN_NO(128) | 4)
+#define PINMUX_GPIO128__FUNC_SCP_JTAG0_TRSTN_VCORE (MTK_PIN_NO(128) | 5)
+#define PINMUX_GPIO128__FUNC_ANT_SEL14 (MTK_PIN_NO(128) | 6)
+#define PINMUX_GPIO128__FUNC_DBG_MON_B9 (MTK_PIN_NO(128) | 7)
+
+#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
+#define PINMUX_GPIO129__FUNC_GBE_RXDV (MTK_PIN_NO(129) | 1)
+#define PINMUX_GPIO129__FUNC_I2SIN1_LRCK (MTK_PIN_NO(129) | 2)
+#define PINMUX_GPIO129__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(129) | 4)
+#define PINMUX_GPIO129__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(129) | 5)
+#define PINMUX_GPIO129__FUNC_ANT_SEL15 (MTK_PIN_NO(129) | 6)
+#define PINMUX_GPIO129__FUNC_DBG_MON_B10 (MTK_PIN_NO(129) | 7)
+
+#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
+#define PINMUX_GPIO130__FUNC_GBE_TXEN (MTK_PIN_NO(130) | 1)
+#define PINMUX_GPIO130__FUNC_I2SIN1_DI (MTK_PIN_NO(130) | 2)
+#define PINMUX_GPIO130__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(130) | 4)
+#define PINMUX_GPIO130__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(130) | 5)
+#define PINMUX_GPIO130__FUNC_ANT_SEL16 (MTK_PIN_NO(130) | 6)
+#define PINMUX_GPIO130__FUNC_DBG_MON_B11 (MTK_PIN_NO(130) | 7)
+
+#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
+#define PINMUX_GPIO131__FUNC_GBE_MDC (MTK_PIN_NO(131) | 1)
+#define PINMUX_GPIO131__FUNC_CLKM0 (MTK_PIN_NO(131) | 2)
+#define PINMUX_GPIO131__FUNC_mbistreaden_trigger (MTK_PIN_NO(131) | 3)
+#define PINMUX_GPIO131__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(131) | 4)
+#define PINMUX_GPIO131__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(131) | 5)
+#define PINMUX_GPIO131__FUNC_ANT_SEL17 (MTK_PIN_NO(131) | 6)
+#define PINMUX_GPIO131__FUNC_DBG_MON_B12 (MTK_PIN_NO(131) | 7)
+
+#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
+#define PINMUX_GPIO132__FUNC_GBE_MDIO (MTK_PIN_NO(132) | 1)
+#define PINMUX_GPIO132__FUNC_CLKM1 (MTK_PIN_NO(132) | 2)
+#define PINMUX_GPIO132__FUNC_mbistwriteen_trigger (MTK_PIN_NO(132) | 3)
+#define PINMUX_GPIO132__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(132) | 4)
+#define PINMUX_GPIO132__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(132) | 5)
+#define PINMUX_GPIO132__FUNC_ANT_SEL18 (MTK_PIN_NO(132) | 6)
+#define PINMUX_GPIO132__FUNC_DBG_MON_B13 (MTK_PIN_NO(132) | 7)
+
+#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
+#define PINMUX_GPIO133__FUNC_GBE_TXER (MTK_PIN_NO(133) | 1)
+#define PINMUX_GPIO133__FUNC_GBE_AUX_PPS2 (MTK_PIN_NO(133) | 2)
+#define PINMUX_GPIO133__FUNC_CONN_BT_TXD (MTK_PIN_NO(133) | 4)
+#define PINMUX_GPIO133__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(133) | 5)
+#define PINMUX_GPIO133__FUNC_ANT_SEL19 (MTK_PIN_NO(133) | 6)
+#define PINMUX_GPIO133__FUNC_DBG_MON_B14 (MTK_PIN_NO(133) | 7)
+
+#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
+#define PINMUX_GPIO134__FUNC_GBE_RXER (MTK_PIN_NO(134) | 1)
+#define PINMUX_GPIO134__FUNC_GBE_AUX_PPS3 (MTK_PIN_NO(134) | 2)
+#define PINMUX_GPIO134__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(134) | 3)
+#define PINMUX_GPIO134__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(134) | 4)
+#define PINMUX_GPIO134__FUNC_APU_JTAG_TMS (MTK_PIN_NO(134) | 5)
+#define PINMUX_GPIO134__FUNC_ANT_SEL20 (MTK_PIN_NO(134) | 6)
+#define PINMUX_GPIO134__FUNC_DBG_MON_B15 (MTK_PIN_NO(134) | 7)
+
+#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
+#define PINMUX_GPIO135__FUNC_GBE_COL (MTK_PIN_NO(135) | 1)
+#define PINMUX_GPIO135__FUNC_I2SOUT1_MCK (MTK_PIN_NO(135) | 2)
+#define PINMUX_GPIO135__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(135) | 3)
+#define PINMUX_GPIO135__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(135) | 4)
+#define PINMUX_GPIO135__FUNC_APU_JTAG_TCK (MTK_PIN_NO(135) | 5)
+#define PINMUX_GPIO135__FUNC_ANT_SEL21 (MTK_PIN_NO(135) | 6)
+#define PINMUX_GPIO135__FUNC_DBG_MON_B16 (MTK_PIN_NO(135) | 7)
+
+#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
+#define PINMUX_GPIO136__FUNC_GBE_INTR (MTK_PIN_NO(136) | 1)
+#define PINMUX_GPIO136__FUNC_I2SOUT1_BCK (MTK_PIN_NO(136) | 2)
+#define PINMUX_GPIO136__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(136) | 3)
+#define PINMUX_GPIO136__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(136) | 4)
+#define PINMUX_GPIO136__FUNC_APU_JTAG_TDI (MTK_PIN_NO(136) | 5)
+#define PINMUX_GPIO136__FUNC_PWM_0 (MTK_PIN_NO(136) | 6)
+#define PINMUX_GPIO136__FUNC_DBG_MON_B17 (MTK_PIN_NO(136) | 7)
+
+#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
+#define PINMUX_GPIO137__FUNC_GBE_AUX_PPS0 (MTK_PIN_NO(137) | 1)
+#define PINMUX_GPIO137__FUNC_I2SOUT1_LRCK (MTK_PIN_NO(137) | 2)
+#define PINMUX_GPIO137__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(137) | 3)
+#define PINMUX_GPIO137__FUNC_DP_TX_HPD (MTK_PIN_NO(137) | 4)
+#define PINMUX_GPIO137__FUNC_APU_JTAG_TDO (MTK_PIN_NO(137) | 5)
+#define PINMUX_GPIO137__FUNC_PWM_1 (MTK_PIN_NO(137) | 6)
+#define PINMUX_GPIO137__FUNC_DBG_MON_B18 (MTK_PIN_NO(137) | 7)
+
+#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
+#define PINMUX_GPIO138__FUNC_GBE_AUX_PPS1 (MTK_PIN_NO(138) | 1)
+#define PINMUX_GPIO138__FUNC_I2SOUT1_DO (MTK_PIN_NO(138) | 2)
+#define PINMUX_GPIO138__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(138) | 3)
+#define PINMUX_GPIO138__FUNC_EDP_TX_HPD (MTK_PIN_NO(138) | 4)
+#define PINMUX_GPIO138__FUNC_APU_JTAG_TRST (MTK_PIN_NO(138) | 5)
+#define PINMUX_GPIO138__FUNC_PWM_2 (MTK_PIN_NO(138) | 6)
+#define PINMUX_GPIO138__FUNC_DBG_MON_B19 (MTK_PIN_NO(138) | 7)
+
+#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
+#define PINMUX_GPIO139__FUNC_CONN_TOP_CLK (MTK_PIN_NO(139) | 1)
+
+#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
+#define PINMUX_GPIO140__FUNC_CONN_TOP_DATA (MTK_PIN_NO(140) | 1)
+
+#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
+#define PINMUX_GPIO141__FUNC_CONN_BT_CLK (MTK_PIN_NO(141) | 1)
+
+#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
+#define PINMUX_GPIO142__FUNC_CONN_BT_DATA (MTK_PIN_NO(142) | 1)
+
+#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
+#define PINMUX_GPIO143__FUNC_CONN_HRST_B (MTK_PIN_NO(143) | 1)
+
+#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
+#define PINMUX_GPIO144__FUNC_CONN_WB_PTA (MTK_PIN_NO(144) | 1)
+
+#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
+#define PINMUX_GPIO145__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(145) | 1)
+
+#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
+#define PINMUX_GPIO146__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(146) | 1)
+
+#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
+#define PINMUX_GPIO147__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(147) | 1)
+
+#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
+#define PINMUX_GPIO148__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(148) | 1)
+
+#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
+#define PINMUX_GPIO149__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(149) | 1)
+
+#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
+#define PINMUX_GPIO150__FUNC_SPINOR_CK (MTK_PIN_NO(150) | 1)
+#define PINMUX_GPIO150__FUNC_DMIC0_CLK (MTK_PIN_NO(150) | 2)
+#define PINMUX_GPIO150__FUNC_DP_TX_HPD (MTK_PIN_NO(150) | 3)
+#define PINMUX_GPIO150__FUNC_PWM_0 (MTK_PIN_NO(150) | 4)
+#define PINMUX_GPIO150__FUNC_CONN_BPI_BUS17_ANT0 (MTK_PIN_NO(150) | 5)
+#define PINMUX_GPIO150__FUNC_LVTS_FOUT (MTK_PIN_NO(150) | 6)
+#define PINMUX_GPIO150__FUNC_DBG_MON_B26 (MTK_PIN_NO(150) | 7)
+
+#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
+#define PINMUX_GPIO151__FUNC_SPINOR_CS (MTK_PIN_NO(151) | 1)
+#define PINMUX_GPIO151__FUNC_DMIC0_DAT0 (MTK_PIN_NO(151) | 2)
+#define PINMUX_GPIO151__FUNC_EDP_TX_HPD (MTK_PIN_NO(151) | 3)
+#define PINMUX_GPIO151__FUNC_PWM_1 (MTK_PIN_NO(151) | 4)
+#define PINMUX_GPIO151__FUNC_CONN_BPI_BUS18_ANT1 (MTK_PIN_NO(151) | 5)
+#define PINMUX_GPIO151__FUNC_LVTS_SDO (MTK_PIN_NO(151) | 6)
+#define PINMUX_GPIO151__FUNC_DBG_MON_B27 (MTK_PIN_NO(151) | 7)
+
+#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
+#define PINMUX_GPIO152__FUNC_SPINOR_IO0 (MTK_PIN_NO(152) | 1)
+#define PINMUX_GPIO152__FUNC_DMIC0_DAT1 (MTK_PIN_NO(152) | 2)
+#define PINMUX_GPIO152__FUNC_UTXD2 (MTK_PIN_NO(152) | 3)
+#define PINMUX_GPIO152__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(152) | 4)
+#define PINMUX_GPIO152__FUNC_CONN_BPI_BUS19_ANT2 (MTK_PIN_NO(152) | 5)
+#define PINMUX_GPIO152__FUNC_LVTS_26M (MTK_PIN_NO(152) | 6)
+#define PINMUX_GPIO152__FUNC_DBG_MON_B28 (MTK_PIN_NO(152) | 7)
+
+#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
+#define PINMUX_GPIO153__FUNC_SPINOR_IO1 (MTK_PIN_NO(153) | 1)
+#define PINMUX_GPIO153__FUNC_DMIC1_CLK (MTK_PIN_NO(153) | 2)
+#define PINMUX_GPIO153__FUNC_UCTS2 (MTK_PIN_NO(153) | 3)
+#define PINMUX_GPIO153__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(153) | 4)
+#define PINMUX_GPIO153__FUNC_CONN_BPI_BUS20_ANT3 (MTK_PIN_NO(153) | 5)
+#define PINMUX_GPIO153__FUNC_LVTS_SCF (MTK_PIN_NO(153) | 6)
+#define PINMUX_GPIO153__FUNC_DBG_MON_B29 (MTK_PIN_NO(153) | 7)
+
+#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
+#define PINMUX_GPIO154__FUNC_SPINOR_IO2 (MTK_PIN_NO(154) | 1)
+#define PINMUX_GPIO154__FUNC_DMIC1_DAT0 (MTK_PIN_NO(154) | 2)
+#define PINMUX_GPIO154__FUNC_URTS2 (MTK_PIN_NO(154) | 3)
+#define PINMUX_GPIO154__FUNC_USB_DRVVBUS_3P (MTK_PIN_NO(154) | 4)
+#define PINMUX_GPIO154__FUNC_CONN_BPI_BUS21_ANT4 (MTK_PIN_NO(154) | 5)
+#define PINMUX_GPIO154__FUNC_LVTS_SCK (MTK_PIN_NO(154) | 6)
+#define PINMUX_GPIO154__FUNC_DBG_MON_B30 (MTK_PIN_NO(154) | 7)
+
+#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
+#define PINMUX_GPIO155__FUNC_SPINOR_IO3 (MTK_PIN_NO(155) | 1)
+#define PINMUX_GPIO155__FUNC_DMIC1_DAT1 (MTK_PIN_NO(155) | 2)
+#define PINMUX_GPIO155__FUNC_URXD2 (MTK_PIN_NO(155) | 3)
+#define PINMUX_GPIO155__FUNC_USB_DRVVBUS_4P (MTK_PIN_NO(155) | 4)
+#define PINMUX_GPIO155__FUNC_DISP_PWM1 (MTK_PIN_NO(155) | 5)
+#define PINMUX_GPIO155__FUNC_LVTS_SDI (MTK_PIN_NO(155) | 6)
+#define PINMUX_GPIO155__FUNC_DBG_MON_B31 (MTK_PIN_NO(155) | 7)
+
+#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
+#define PINMUX_GPIO156__FUNC_MSDC0_DAT7 (MTK_PIN_NO(156) | 1)
+
+#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
+#define PINMUX_GPIO157__FUNC_MSDC0_DAT6 (MTK_PIN_NO(157) | 1)
+
+#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
+#define PINMUX_GPIO158__FUNC_MSDC0_DAT5 (MTK_PIN_NO(158) | 1)
+
+#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
+#define PINMUX_GPIO159__FUNC_MSDC0_DAT4 (MTK_PIN_NO(159) | 1)
+
+#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
+#define PINMUX_GPIO160__FUNC_MSDC0_RSTB (MTK_PIN_NO(160) | 1)
+
+#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
+#define PINMUX_GPIO161__FUNC_MSDC0_CMD (MTK_PIN_NO(161) | 1)
+
+#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
+#define PINMUX_GPIO162__FUNC_MSDC0_CLK (MTK_PIN_NO(162) | 1)
+
+#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
+#define PINMUX_GPIO163__FUNC_MSDC0_DAT3 (MTK_PIN_NO(163) | 1)
+
+#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
+#define PINMUX_GPIO164__FUNC_MSDC0_DAT2 (MTK_PIN_NO(164) | 1)
+
+#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
+#define PINMUX_GPIO165__FUNC_MSDC0_DAT1 (MTK_PIN_NO(165) | 1)
+
+#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
+#define PINMUX_GPIO166__FUNC_MSDC0_DAT0 (MTK_PIN_NO(166) | 1)
+
+#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
+#define PINMUX_GPIO167__FUNC_MSDC0_DSL (MTK_PIN_NO(167) | 1)
+
+#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
+#define PINMUX_GPIO168__FUNC_MSDC1_CMD (MTK_PIN_NO(168) | 1)
+#define PINMUX_GPIO168__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(168) | 2)
+#define PINMUX_GPIO168__FUNC_UCTS1 (MTK_PIN_NO(168) | 3)
+#define PINMUX_GPIO168__FUNC_UDI_TMS (MTK_PIN_NO(168) | 4)
+#define PINMUX_GPIO168__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(168) | 5)
+#define PINMUX_GPIO168__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(168) | 6)
+#define PINMUX_GPIO168__FUNC_CONN_BGF_MCU_TMS (MTK_PIN_NO(168) | 7)
+
+#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
+#define PINMUX_GPIO169__FUNC_MSDC1_CLK (MTK_PIN_NO(169) | 1)
+#define PINMUX_GPIO169__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(169) | 2)
+#define PINMUX_GPIO169__FUNC_URTS1 (MTK_PIN_NO(169) | 3)
+#define PINMUX_GPIO169__FUNC_UDI_TCK (MTK_PIN_NO(169) | 4)
+#define PINMUX_GPIO169__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(169) | 5)
+#define PINMUX_GPIO169__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(169) | 6)
+#define PINMUX_GPIO169__FUNC_CONN_BGF_MCU_TCK (MTK_PIN_NO(169) | 7)
+
+#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
+#define PINMUX_GPIO170__FUNC_MSDC1_DAT0 (MTK_PIN_NO(170) | 1)
+#define PINMUX_GPIO170__FUNC_SPIM5_B_CSB (MTK_PIN_NO(170) | 2)
+#define PINMUX_GPIO170__FUNC_UCTS2 (MTK_PIN_NO(170) | 3)
+#define PINMUX_GPIO170__FUNC_UDI_TDI (MTK_PIN_NO(170) | 4)
+#define PINMUX_GPIO170__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(170) | 5)
+#define PINMUX_GPIO170__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(170) | 6)
+#define PINMUX_GPIO170__FUNC_CONN_BGF_MCU_TDI (MTK_PIN_NO(170) | 7)
+
+#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
+#define PINMUX_GPIO171__FUNC_MSDC1_DAT1 (MTK_PIN_NO(171) | 1)
+#define PINMUX_GPIO171__FUNC_SPIM5_B_CLK (MTK_PIN_NO(171) | 2)
+#define PINMUX_GPIO171__FUNC_URTS2 (MTK_PIN_NO(171) | 3)
+#define PINMUX_GPIO171__FUNC_UDI_TDO (MTK_PIN_NO(171) | 4)
+#define PINMUX_GPIO171__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(171) | 5)
+#define PINMUX_GPIO171__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(171) | 6)
+#define PINMUX_GPIO171__FUNC_CONN_BGF_MCU_TDO (MTK_PIN_NO(171) | 7)
+
+#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
+#define PINMUX_GPIO172__FUNC_MSDC1_DAT2 (MTK_PIN_NO(172) | 1)
+#define PINMUX_GPIO172__FUNC_SPIM5_B_MO (MTK_PIN_NO(172) | 2)
+#define PINMUX_GPIO172__FUNC_UCTS3 (MTK_PIN_NO(172) | 3)
+#define PINMUX_GPIO172__FUNC_UDI_NTRST (MTK_PIN_NO(172) | 4)
+#define PINMUX_GPIO172__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(172) | 5)
+#define PINMUX_GPIO172__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(172) | 6)
+#define PINMUX_GPIO172__FUNC_CONN_BGF_MCU_TRST_B (MTK_PIN_NO(172) | 7)
+
+#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
+#define PINMUX_GPIO173__FUNC_MSDC1_DAT3 (MTK_PIN_NO(173) | 1)
+#define PINMUX_GPIO173__FUNC_SPIM5_B_MI (MTK_PIN_NO(173) | 2)
+#define PINMUX_GPIO173__FUNC_URTS3 (MTK_PIN_NO(173) | 3)
+#define PINMUX_GPIO173__FUNC_CLKM0 (MTK_PIN_NO(173) | 4)
+#define PINMUX_GPIO173__FUNC_PWM_2 (MTK_PIN_NO(173) | 5)
+
+#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
+#define PINMUX_GPIO174__FUNC_MSDC2_CMD (MTK_PIN_NO(174) | 1)
+#define PINMUX_GPIO174__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(174) | 2)
+#define PINMUX_GPIO174__FUNC_UTXD1 (MTK_PIN_NO(174) | 3)
+#define PINMUX_GPIO174__FUNC_VADSP_JTAG0_TMS (MTK_PIN_NO(174) | 4)
+#define PINMUX_GPIO174__FUNC_SSPM_JTAG_TMS_VLP (MTK_PIN_NO(174) | 5)
+#define PINMUX_GPIO174__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(174) | 6)
+#define PINMUX_GPIO174__FUNC_SCP_JTAG0_TMS_VLP (MTK_PIN_NO(174) | 7)
+
+#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
+#define PINMUX_GPIO175__FUNC_MSDC2_CLK (MTK_PIN_NO(175) | 1)
+#define PINMUX_GPIO175__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(175) | 2)
+#define PINMUX_GPIO175__FUNC_URXD1 (MTK_PIN_NO(175) | 3)
+#define PINMUX_GPIO175__FUNC_VADSP_JTAG0_TCK (MTK_PIN_NO(175) | 4)
+#define PINMUX_GPIO175__FUNC_SSPM_JTAG_TCK_VLP (MTK_PIN_NO(175) | 5)
+#define PINMUX_GPIO175__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(175) | 6)
+#define PINMUX_GPIO175__FUNC_SCP_JTAG0_TCK_VLP (MTK_PIN_NO(175) | 7)
+
+#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
+#define PINMUX_GPIO176__FUNC_MSDC2_DAT0 (MTK_PIN_NO(176) | 1)
+#define PINMUX_GPIO176__FUNC_SRCLKENAI0 (MTK_PIN_NO(176) | 2)
+#define PINMUX_GPIO176__FUNC_UTXD2 (MTK_PIN_NO(176) | 3)
+#define PINMUX_GPIO176__FUNC_VADSP_JTAG0_TDI (MTK_PIN_NO(176) | 4)
+#define PINMUX_GPIO176__FUNC_SSPM_JTAG_TDI_VLP (MTK_PIN_NO(176) | 5)
+#define PINMUX_GPIO176__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(176) | 6)
+#define PINMUX_GPIO176__FUNC_SCP_JTAG0_TDI_VLP (MTK_PIN_NO(176) | 7)
+
+#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
+#define PINMUX_GPIO177__FUNC_MSDC2_DAT1 (MTK_PIN_NO(177) | 1)
+#define PINMUX_GPIO177__FUNC_SRCLKENAI1 (MTK_PIN_NO(177) | 2)
+#define PINMUX_GPIO177__FUNC_URXD2 (MTK_PIN_NO(177) | 3)
+#define PINMUX_GPIO177__FUNC_VADSP_JTAG0_TDO (MTK_PIN_NO(177) | 4)
+#define PINMUX_GPIO177__FUNC_SSPM_JTAG_TDO_VLP (MTK_PIN_NO(177) | 5)
+#define PINMUX_GPIO177__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(177) | 6)
+#define PINMUX_GPIO177__FUNC_SCP_JTAG0_TDO_VLP (MTK_PIN_NO(177) | 7)
+
+#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
+#define PINMUX_GPIO178__FUNC_MSDC2_DAT2 (MTK_PIN_NO(178) | 1)
+#define PINMUX_GPIO178__FUNC_UTXD3 (MTK_PIN_NO(178) | 3)
+#define PINMUX_GPIO178__FUNC_VADSP_JTAG0_TRSTN (MTK_PIN_NO(178) | 4)
+#define PINMUX_GPIO178__FUNC_SSPM_JTAG_TRSTN_VLP (MTK_PIN_NO(178) | 5)
+#define PINMUX_GPIO178__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(178) | 6)
+#define PINMUX_GPIO178__FUNC_SCP_JTAG0_TRSTN_VLP (MTK_PIN_NO(178) | 7)
+
+#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
+#define PINMUX_GPIO179__FUNC_MSDC2_DAT3 (MTK_PIN_NO(179) | 1)
+#define PINMUX_GPIO179__FUNC_URXD3 (MTK_PIN_NO(179) | 3)
+#define PINMUX_GPIO179__FUNC_CLKM1 (MTK_PIN_NO(179) | 4)
+#define PINMUX_GPIO179__FUNC_PWM_vlp (MTK_PIN_NO(179) | 5)
+#define PINMUX_GPIO179__FUNC_TP_GPIO7_AO (MTK_PIN_NO(179) | 7)
+
+#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)
+#define PINMUX_GPIO180__FUNC_SPMI_P_SCL (MTK_PIN_NO(180) | 1)
+
+#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)
+#define PINMUX_GPIO181__FUNC_SPMI_P_SDA (MTK_PIN_NO(181) | 1)
+
+#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)
+#define PINMUX_GPIO182__FUNC_DDR_PAD_RRESETB (MTK_PIN_NO(182) | 1)
+
+#endif /* __MT8189_PINFUNC_H */
-- 
2.45.2



From ot_cathy.xu at mediatek.com  Fri May 23 02:42:48 2025
From: ot_cathy.xu at mediatek.com (Cathy Xu)
Date: Fri, 23 May 2025 17:42:48 +0800
Subject: [PATCH 3/3] pinctrl: mediatek: Add pinctrl driver on mt8189
In-Reply-To: <20250523094319.10377-1-ot_cathy.xu@mediatek.com>
References: <20250523094319.10377-1-ot_cathy.xu@mediatek.com>
Message-ID: <20250523094319.10377-4-ot_cathy.xu@mediatek.com>

Add pinctrl driver support for MediaTek Soc mt8189.

Signed-off-by: Cathy Xu <ot_cathy.xu at mediatek.com>
---
 drivers/pinctrl/mediatek/Kconfig              |   12 +
 drivers/pinctrl/mediatek/Makefile             |    1 +
 drivers/pinctrl/mediatek/pinctrl-mt8189.c     | 1700 ++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-mt8189.h | 2452 +++++++++++++++++
 4 files changed, 4165 insertions(+)
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8189.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8189.h

diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 2d15af6be276..5b191e12a8aa 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -259,6 +259,18 @@ config PINCTRL_MT8188
 	  In MTK platform, we support virtual gpio and use it to
 	  map specific eint which doesn't have real gpio pin.
 
+config PINCTRL_MT8189
+        bool "MediaTek MT8189 pin control"
+        depends on OF
+        depends on ARM64 || COMPILE_TEST
+        default ARM64 && ARCH_MEDIATEK
+        select PINCTRL_MTK_PARIS
+        help
+          Say yes here to support pin controller and gpio driver
+          on MediaTek MT8189 SoC.
+          In MTK platform, we support virtual gpio and use it to
+          map specific eint which doesn't have real gpio pin.
+
 config PINCTRL_MT8192
 	bool "MediaTek MT8192 pin control"
 	depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 7518980fba59..5d4646939ba3 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_PINCTRL_MT8173)		+= pinctrl-mt8173.o
 obj-$(CONFIG_PINCTRL_MT8183)		+= pinctrl-mt8183.o
 obj-$(CONFIG_PINCTRL_MT8186)		+= pinctrl-mt8186.o
 obj-$(CONFIG_PINCTRL_MT8188)		+= pinctrl-mt8188.o
+obj-$(CONFIG_PINCTRL_MT8189)            += pinctrl-mt8189.o
 obj-$(CONFIG_PINCTRL_MT8192)		+= pinctrl-mt8192.o
 obj-$(CONFIG_PINCTRL_MT8195)		+= pinctrl-mt8195.o
 obj-$(CONFIG_PINCTRL_MT8196)		+= pinctrl-mt8196.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8189.c b/drivers/pinctrl/mediatek/pinctrl-mt8189.c
new file mode 100644
index 000000000000..a352833aa7b4
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8189.c
@@ -0,0 +1,1700 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ * Author: Lei Xue <lei.xue at mediatek.com>
+ *         Cathy Xu <ot_cathy.xu at mediatek.com>
+ */
+
+#include "pinctrl-mtk-mt8189.h"
+#include "pinctrl-paris.h"
+
+#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits)  \
+	PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+		       32, 0)
+
+#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+	PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+		       32, 1)
+
+static const struct mtk_pin_field_calc mt8189_pin_mode_range[] = {
+	PIN_FIELD(0, 182, 0x0300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt8189_pin_dir_range[] = {
+	PIN_FIELD(0, 182, 0x0000, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8189_pin_di_range[] = {
+	PIN_FIELD(0, 182, 0x0200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8189_pin_do_range[] = {
+	PIN_FIELD(0, 182, 0x0100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8189_pin_smt_range[] = {
+	PIN_FIELD_BASE(0, 0, 7, 0x00e0, 0x10, 5, 1),
+	PIN_FIELD_BASE(1, 1, 8, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(2, 2, 8, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(3, 3, 8, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(4, 4, 8, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(5, 5, 8, 0x00c0, 0x10, 7, 1),
+	PIN_FIELD_BASE(6, 6, 7, 0x00e0, 0x10, 6, 1),
+	PIN_FIELD_BASE(7, 7, 7, 0x00e0, 0x10, 7, 1),
+	PIN_FIELD_BASE(8, 8, 7, 0x00e0, 0x10, 8, 1),
+	PIN_FIELD_BASE(9, 9, 7, 0x00e0, 0x10, 9, 1),
+	PIN_FIELD_BASE(10, 10, 7, 0x00e0, 0x10, 10, 1),
+	PIN_FIELD_BASE(11, 11, 7, 0x00e0, 0x10, 11, 1),
+	PIN_FIELD_BASE(12, 12, 2, 0x00e0, 0x10, 5, 1),
+	PIN_FIELD_BASE(13, 13, 2, 0x00e0, 0x10, 6, 1),
+	PIN_FIELD_BASE(14, 14, 3, 0x00f0, 0x10, 0, 1),
+	PIN_FIELD_BASE(15, 15, 3, 0x00f0, 0x10, 1, 1),
+	PIN_FIELD_BASE(16, 16, 2, 0x00e0, 0x10, 7, 1),
+	PIN_FIELD_BASE(17, 17, 2, 0x00e0, 0x10, 8, 1),
+	PIN_FIELD_BASE(18, 18, 7, 0x00e0, 0x10, 0, 1),
+	PIN_FIELD_BASE(19, 19, 7, 0x00e0, 0x10, 2, 1),
+	PIN_FIELD_BASE(20, 20, 7, 0x00e0, 0x10, 1, 1),
+	PIN_FIELD_BASE(21, 21, 7, 0x00e0, 0x10, 3, 1),
+	PIN_FIELD_BASE(22, 22, 9, 0x00f0, 0x10, 0, 1),
+	PIN_FIELD_BASE(23, 23, 9, 0x00f0, 0x10, 1, 1),
+	PIN_FIELD_BASE(24, 24, 9, 0x00f0, 0x10, 2, 1),
+	PIN_FIELD_BASE(25, 25, 4, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(26, 26, 4, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(27, 27, 2, 0x00e0, 0x10, 1, 1),
+	PIN_FIELD_BASE(28, 28, 2, 0x00e0, 0x10, 2, 1),
+	PIN_FIELD_BASE(29, 29, 4, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(30, 30, 2, 0x00e0, 0x10, 0, 1),
+	PIN_FIELD_BASE(31, 31, 3, 0x00f0, 0x10, 19, 1),
+	PIN_FIELD_BASE(32, 32, 1, 0x00c0, 0x10, 30, 1),
+	PIN_FIELD_BASE(33, 33, 3, 0x00f0, 0x10, 21, 1),
+	PIN_FIELD_BASE(34, 34, 3, 0x00f0, 0x10, 20, 1),
+	PIN_FIELD_BASE(35, 35, 3, 0x00f0, 0x10, 23, 1),
+	PIN_FIELD_BASE(36, 36, 3, 0x00f0, 0x10, 22, 1),
+	PIN_FIELD_BASE(37, 37, 3, 0x00f0, 0x10, 25, 1),
+	PIN_FIELD_BASE(38, 38, 3, 0x00f0, 0x10, 24, 1),
+	PIN_FIELD_BASE(39, 39, 3, 0x00f0, 0x10, 5, 1),
+	PIN_FIELD_BASE(40, 40, 3, 0x00f0, 0x10, 2, 1),
+	PIN_FIELD_BASE(41, 41, 3, 0x00f0, 0x10, 3, 1),
+	PIN_FIELD_BASE(42, 42, 3, 0x00f0, 0x10, 4, 1),
+	PIN_FIELD_BASE(43, 43, 3, 0x00f0, 0x10, 6, 1),
+	PIN_FIELD_BASE(44, 44, 7, 0x00e0, 0x10, 20, 1),
+	PIN_FIELD_BASE(45, 45, 7, 0x00e0, 0x10, 21, 1),
+	PIN_FIELD_BASE(46, 46, 7, 0x00e0, 0x10, 22, 1),
+	PIN_FIELD_BASE(47, 47, 7, 0x00e0, 0x10, 23, 1),
+	PIN_FIELD_BASE(48, 48, 4, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(49, 49, 4, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(50, 50, 4, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(51, 51, 8, 0x00c0, 0x10, 8, 1),
+	PIN_FIELD_BASE(52, 52, 8, 0x00c0, 0x10, 10, 1),
+	PIN_FIELD_BASE(53, 53, 8, 0x00c0, 0x10, 9, 1),
+	PIN_FIELD_BASE(54, 54, 8, 0x00c0, 0x10, 11, 1),
+	PIN_FIELD_BASE(55, 55, 4, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(56, 56, 4, 0x00c0, 0x10, 7, 1),
+	PIN_FIELD_BASE(57, 57, 2, 0x00e0, 0x10, 13, 1),
+	PIN_FIELD_BASE(58, 58, 2, 0x00e0, 0x10, 17, 1),
+	PIN_FIELD_BASE(59, 59, 2, 0x00e0, 0x10, 14, 1),
+	PIN_FIELD_BASE(60, 60, 2, 0x00e0, 0x10, 18, 1),
+	PIN_FIELD_BASE(61, 61, 2, 0x00e0, 0x10, 15, 1),
+	PIN_FIELD_BASE(62, 62, 2, 0x00e0, 0x10, 19, 1),
+	PIN_FIELD_BASE(63, 63, 2, 0x00e0, 0x10, 16, 1),
+	PIN_FIELD_BASE(64, 64, 2, 0x00e0, 0x10, 20, 1),
+	PIN_FIELD_BASE(65, 65, 9, 0x00f0, 0x10, 10, 1),
+	PIN_FIELD_BASE(66, 66, 9, 0x00f0, 0x10, 12, 1),
+	PIN_FIELD_BASE(67, 67, 9, 0x00f0, 0x10, 11, 1),
+	PIN_FIELD_BASE(68, 68, 9, 0x00f0, 0x10, 13, 1),
+	PIN_FIELD_BASE(69, 69, 2, 0x00e0, 0x10, 22, 1),
+	PIN_FIELD_BASE(70, 70, 2, 0x00e0, 0x10, 21, 1),
+	PIN_FIELD_BASE(71, 71, 2, 0x00e0, 0x10, 24, 1),
+	PIN_FIELD_BASE(72, 72, 2, 0x00e0, 0x10, 23, 1),
+	PIN_FIELD_BASE(73, 73, 2, 0x00e0, 0x10, 26, 1),
+	PIN_FIELD_BASE(74, 74, 2, 0x00e0, 0x10, 25, 1),
+	PIN_FIELD_BASE(75, 75, 3, 0x00f0, 0x10, 13, 1),
+	PIN_FIELD_BASE(76, 76, 2, 0x00e0, 0x10, 27, 1),
+	PIN_FIELD_BASE(77, 77, 8, 0x00c0, 0x10, 13, 1),
+	PIN_FIELD_BASE(78, 78, 8, 0x00c0, 0x10, 12, 1),
+	PIN_FIELD_BASE(79, 79, 8, 0x00c0, 0x10, 15, 1),
+	PIN_FIELD_BASE(80, 80, 8, 0x00c0, 0x10, 14, 1),
+	PIN_FIELD_BASE(81, 81, 2, 0x00e0, 0x10, 29, 1),
+	PIN_FIELD_BASE(82, 82, 2, 0x00e0, 0x10, 28, 1),
+	PIN_FIELD_BASE(83, 83, 2, 0x00e0, 0x10, 30, 1),
+	PIN_FIELD_BASE(84, 84, 7, 0x00e0, 0x10, 24, 1),
+	PIN_FIELD_BASE(85, 85, 7, 0x00e0, 0x10, 25, 1),
+	PIN_FIELD_BASE(86, 86, 7, 0x00e0, 0x10, 26, 1),
+	PIN_FIELD_BASE(87, 87, 7, 0x00e0, 0x10, 27, 1),
+	PIN_FIELD_BASE(88, 88, 5, 0x0120, 0x10, 20, 1),
+	PIN_FIELD_BASE(89, 89, 5, 0x0120, 0x10, 19, 1),
+	PIN_FIELD_BASE(90, 90, 5, 0x0120, 0x10, 22, 1),
+	PIN_FIELD_BASE(91, 91, 5, 0x0120, 0x10, 21, 1),
+	PIN_FIELD_BASE(92, 92, 5, 0x0120, 0x10, 16, 1),
+	PIN_FIELD_BASE(93, 93, 5, 0x0120, 0x10, 17, 1),
+	PIN_FIELD_BASE(94, 94, 5, 0x0120, 0x10, 23, 1),
+	PIN_FIELD_BASE(95, 95, 5, 0x0120, 0x10, 15, 1),
+	PIN_FIELD_BASE(96, 96, 5, 0x0120, 0x10, 18, 1),
+	PIN_FIELD_BASE(97, 97, 5, 0x0120, 0x10, 0, 1),
+	PIN_FIELD_BASE(98, 98, 5, 0x0120, 0x10, 5, 1),
+	PIN_FIELD_BASE(99, 99, 5, 0x0120, 0x10, 3, 1),
+	PIN_FIELD_BASE(100, 100, 5, 0x0120, 0x10, 4, 1),
+	PIN_FIELD_BASE(101, 101, 5, 0x0120, 0x10, 1, 1),
+	PIN_FIELD_BASE(102, 102, 5, 0x0120, 0x10, 2, 1),
+	PIN_FIELD_BASE(103, 103, 7, 0x00e0, 0x10, 15, 1),
+	PIN_FIELD_BASE(104, 104, 7, 0x00e0, 0x10, 12, 1),
+	PIN_FIELD_BASE(105, 105, 7, 0x00e0, 0x10, 14, 1),
+	PIN_FIELD_BASE(106, 106, 7, 0x00e0, 0x10, 13, 1),
+	PIN_FIELD_BASE(107, 107, 7, 0x00e0, 0x10, 19, 1),
+	PIN_FIELD_BASE(108, 108, 7, 0x00e0, 0x10, 16, 1),
+	PIN_FIELD_BASE(109, 109, 7, 0x00e0, 0x10, 18, 1),
+	PIN_FIELD_BASE(110, 110, 7, 0x00e0, 0x10, 17, 1),
+	PIN_FIELD_BASE(111, 111, 7, 0x00e0, 0x10, 4, 1),
+	PIN_FIELD_BASE(112, 112, 8, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(113, 113, 8, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(114, 114, 8, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(115, 115, 2, 0x00e0, 0x10, 9, 1),
+	PIN_FIELD_BASE(116, 116, 2, 0x00e0, 0x10, 12, 1),
+	PIN_FIELD_BASE(117, 117, 2, 0x00e0, 0x10, 10, 1),
+	PIN_FIELD_BASE(118, 118, 2, 0x00e0, 0x10, 11, 1),
+	PIN_FIELD_BASE(119, 119, 1, 0x00c0, 0x10, 26, 1),
+	PIN_FIELD_BASE(120, 120, 1, 0x00c0, 0x10, 25, 1),
+	PIN_FIELD_BASE(121, 121, 1, 0x00c0, 0x10, 24, 1),
+	PIN_FIELD_BASE(122, 122, 1, 0x00c0, 0x10, 23, 1),
+	PIN_FIELD_BASE(123, 123, 1, 0x00c0, 0x10, 19, 1),
+	PIN_FIELD_BASE(124, 124, 1, 0x00c0, 0x10, 18, 1),
+	PIN_FIELD_BASE(125, 125, 1, 0x00c0, 0x10, 17, 1),
+	PIN_FIELD_BASE(126, 126, 1, 0x00c0, 0x10, 16, 1),
+	PIN_FIELD_BASE(127, 127, 1, 0x00c0, 0x10, 22, 1),
+	PIN_FIELD_BASE(128, 128, 1, 0x00c0, 0x10, 15, 1),
+	PIN_FIELD_BASE(129, 129, 1, 0x00c0, 0x10, 20, 1),
+	PIN_FIELD_BASE(130, 130, 1, 0x00c0, 0x10, 27, 1),
+	PIN_FIELD_BASE(131, 131, 1, 0x00c0, 0x10, 13, 1),
+	PIN_FIELD_BASE(132, 132, 1, 0x00c0, 0x10, 14, 1),
+	PIN_FIELD_BASE(133, 133, 1, 0x00c0, 0x10, 28, 1),
+	PIN_FIELD_BASE(134, 134, 1, 0x00c0, 0x10, 21, 1),
+	PIN_FIELD_BASE(135, 135, 1, 0x00c0, 0x10, 11, 1),
+	PIN_FIELD_BASE(136, 136, 1, 0x00c0, 0x10, 12, 1),
+	PIN_FIELD_BASE(137, 137, 2, 0x00e0, 0x10, 3, 1),
+	PIN_FIELD_BASE(138, 138, 2, 0x00e0, 0x10, 4, 1),
+	PIN_FIELD_BASE(139, 139, 1, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(140, 140, 1, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(141, 141, 1, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(142, 142, 1, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(143, 143, 1, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(144, 144, 1, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(145, 145, 1, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(146, 146, 1, 0x00c0, 0x10, 7, 1),
+	PIN_FIELD_BASE(147, 147, 1, 0x00c0, 0x10, 8, 1),
+	PIN_FIELD_BASE(148, 148, 1, 0x00c0, 0x10, 9, 1),
+	PIN_FIELD_BASE(149, 149, 1, 0x00c0, 0x10, 10, 1),
+	PIN_FIELD_BASE(150, 150, 3, 0x00f0, 0x10, 14, 1),
+	PIN_FIELD_BASE(151, 151, 1, 0x00c0, 0x10, 29, 1),
+	PIN_FIELD_BASE(152, 152, 3, 0x00f0, 0x10, 15, 1),
+	PIN_FIELD_BASE(153, 153, 3, 0x00f0, 0x10, 16, 1),
+	PIN_FIELD_BASE(154, 154, 3, 0x00f0, 0x10, 17, 1),
+	PIN_FIELD_BASE(155, 155, 3, 0x00f0, 0x10, 18, 1),
+	PIN_FIELD_BASE(156, 156, 5, 0x0120, 0x10, 12, 1),
+	PIN_FIELD_BASE(157, 157, 5, 0x0120, 0x10, 11, 1),
+	PIN_FIELD_BASE(158, 158, 5, 0x0120, 0x10, 10, 1),
+	PIN_FIELD_BASE(159, 159, 6, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(160, 160, 5, 0x0120, 0x10, 14, 1),
+	PIN_FIELD_BASE(161, 161, 5, 0x0120, 0x10, 7, 1),
+	PIN_FIELD_BASE(162, 162, 5, 0x0120, 0x10, 6, 1),
+	PIN_FIELD_BASE(163, 163, 6, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(164, 164, 5, 0x0120, 0x10, 9, 1),
+	PIN_FIELD_BASE(165, 165, 5, 0x0120, 0x10, 8, 1),
+	PIN_FIELD_BASE(166, 166, 6, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(167, 167, 5, 0x0120, 0x10, 13, 1),
+	PIN_FIELD_BASE(168, 168, 3, 0x00f0, 0x10, 8, 1),
+	PIN_FIELD_BASE(169, 169, 3, 0x00f0, 0x10, 7, 1),
+	PIN_FIELD_BASE(170, 170, 3, 0x00f0, 0x10, 9, 1),
+	PIN_FIELD_BASE(171, 171, 3, 0x00f0, 0x10, 10, 1),
+	PIN_FIELD_BASE(172, 172, 3, 0x00f0, 0x10, 11, 1),
+	PIN_FIELD_BASE(173, 173, 3, 0x00f0, 0x10, 12, 1),
+	PIN_FIELD_BASE(174, 174, 9, 0x00f0, 0x10, 5, 1),
+	PIN_FIELD_BASE(175, 175, 9, 0x00f0, 0x10, 4, 1),
+	PIN_FIELD_BASE(176, 176, 9, 0x00f0, 0x10, 6, 1),
+	PIN_FIELD_BASE(177, 177, 9, 0x00f0, 0x10, 7, 1),
+	PIN_FIELD_BASE(178, 178, 9, 0x00f0, 0x10, 8, 1),
+	PIN_FIELD_BASE(179, 179, 9, 0x00f0, 0x10, 9, 1),
+	PIN_FIELD_BASE(180, 180, 5, 0x0120, 0x10, 24, 1),
+	PIN_FIELD_BASE(181, 181, 5, 0x0120, 0x10, 25, 1),
+	PIN_FIELD_BASE(182, 182, 9, 0x00f0, 0x10, 3, 1),
+};
+
+static const struct mtk_pin_field_calc mt8189_pin_ies_range[] = {
+	PIN_FIELD_BASE(0, 0, 7, 0x0050, 0x10, 5, 1),
+	PIN_FIELD_BASE(1, 1, 8, 0x0050, 0x10, 3, 1),
+	PIN_FIELD_BASE(2, 2, 8, 0x0050, 0x10, 4, 1),
+	PIN_FIELD_BASE(3, 3, 8, 0x0050, 0x10, 5, 1),
+	PIN_FIELD_BASE(4, 4, 8, 0x0050, 0x10, 6, 1),
+	PIN_FIELD_BASE(5, 5, 8, 0x0050, 0x10, 7, 1),
+	PIN_FIELD_BASE(6, 6, 7, 0x0050, 0x10, 6, 1),
+	PIN_FIELD_BASE(7, 7, 7, 0x0050, 0x10, 7, 1),
+	PIN_FIELD_BASE(8, 8, 7, 0x0050, 0x10, 8, 1),
+	PIN_FIELD_BASE(9, 9, 7, 0x0050, 0x10, 9, 1),
+	PIN_FIELD_BASE(10, 10, 7, 0x0050, 0x10, 10, 1),
+	PIN_FIELD_BASE(11, 11, 7, 0x0050, 0x10, 11, 1),
+	PIN_FIELD_BASE(12, 12, 2, 0x0070, 0x10, 5, 1),
+	PIN_FIELD_BASE(13, 13, 2, 0x0070, 0x10, 6, 1),
+	PIN_FIELD_BASE(14, 14, 3, 0x0050, 0x10, 0, 1),
+	PIN_FIELD_BASE(15, 15, 3, 0x0050, 0x10, 1, 1),
+	PIN_FIELD_BASE(16, 16, 2, 0x0070, 0x10, 7, 1),
+	PIN_FIELD_BASE(17, 17, 2, 0x0070, 0x10, 8, 1),
+	PIN_FIELD_BASE(18, 18, 7, 0x0050, 0x10, 0, 1),
+	PIN_FIELD_BASE(19, 19, 7, 0x0050, 0x10, 2, 1),
+	PIN_FIELD_BASE(20, 20, 7, 0x0050, 0x10, 1, 1),
+	PIN_FIELD_BASE(21, 21, 7, 0x0050, 0x10, 3, 1),
+	PIN_FIELD_BASE(22, 22, 9, 0x0040, 0x10, 0, 1),
+	PIN_FIELD_BASE(23, 23, 9, 0x0040, 0x10, 1, 1),
+	PIN_FIELD_BASE(24, 24, 9, 0x0040, 0x10, 2, 1),
+	PIN_FIELD_BASE(25, 25, 4, 0x0050, 0x10, 2, 1),
+	PIN_FIELD_BASE(26, 26, 4, 0x0050, 0x10, 1, 1),
+	PIN_FIELD_BASE(27, 27, 2, 0x0070, 0x10, 1, 1),
+	PIN_FIELD_BASE(28, 28, 2, 0x0070, 0x10, 2, 1),
+	PIN_FIELD_BASE(29, 29, 4, 0x0050, 0x10, 0, 1),
+	PIN_FIELD_BASE(30, 30, 2, 0x0070, 0x10, 0, 1),
+	PIN_FIELD_BASE(31, 31, 3, 0x0050, 0x10, 19, 1),
+	PIN_FIELD_BASE(32, 32, 1, 0x0050, 0x10, 30, 1),
+	PIN_FIELD_BASE(33, 33, 3, 0x0050, 0x10, 21, 1),
+	PIN_FIELD_BASE(34, 34, 3, 0x0050, 0x10, 20, 1),
+	PIN_FIELD_BASE(35, 35, 3, 0x0050, 0x10, 23, 1),
+	PIN_FIELD_BASE(36, 36, 3, 0x0050, 0x10, 22, 1),
+	PIN_FIELD_BASE(37, 37, 3, 0x0050, 0x10, 25, 1),
+	PIN_FIELD_BASE(38, 38, 3, 0x0050, 0x10, 24, 1),
+	PIN_FIELD_BASE(39, 39, 3, 0x0050, 0x10, 5, 1),
+	PIN_FIELD_BASE(40, 40, 3, 0x0050, 0x10, 2, 1),
+	PIN_FIELD_BASE(41, 41, 3, 0x0050, 0x10, 3, 1),
+	PIN_FIELD_BASE(42, 42, 3, 0x0050, 0x10, 4, 1),
+	PIN_FIELD_BASE(43, 43, 3, 0x0050, 0x10, 6, 1),
+	PIN_FIELD_BASE(44, 44, 7, 0x0050, 0x10, 20, 1),
+	PIN_FIELD_BASE(45, 45, 7, 0x0050, 0x10, 21, 1),
+	PIN_FIELD_BASE(46, 46, 7, 0x0050, 0x10, 22, 1),
+	PIN_FIELD_BASE(47, 47, 7, 0x0050, 0x10, 23, 1),
+	PIN_FIELD_BASE(48, 48, 4, 0x0050, 0x10, 5, 1),
+	PIN_FIELD_BASE(49, 49, 4, 0x0050, 0x10, 4, 1),
+	PIN_FIELD_BASE(50, 50, 4, 0x0050, 0x10, 3, 1),
+	PIN_FIELD_BASE(51, 51, 8, 0x0050, 0x10, 8, 1),
+	PIN_FIELD_BASE(52, 52, 8, 0x0050, 0x10, 10, 1),
+	PIN_FIELD_BASE(53, 53, 8, 0x0050, 0x10, 9, 1),
+	PIN_FIELD_BASE(54, 54, 8, 0x0050, 0x10, 11, 1),
+	PIN_FIELD_BASE(55, 55, 4, 0x0050, 0x10, 6, 1),
+	PIN_FIELD_BASE(56, 56, 4, 0x0050, 0x10, 7, 1),
+	PIN_FIELD_BASE(57, 57, 2, 0x0070, 0x10, 13, 1),
+	PIN_FIELD_BASE(58, 58, 2, 0x0070, 0x10, 17, 1),
+	PIN_FIELD_BASE(59, 59, 2, 0x0070, 0x10, 14, 1),
+	PIN_FIELD_BASE(60, 60, 2, 0x0070, 0x10, 18, 1),
+	PIN_FIELD_BASE(61, 61, 2, 0x0070, 0x10, 15, 1),
+	PIN_FIELD_BASE(62, 62, 2, 0x0070, 0x10, 19, 1),
+	PIN_FIELD_BASE(63, 63, 2, 0x0070, 0x10, 16, 1),
+	PIN_FIELD_BASE(64, 64, 2, 0x0070, 0x10, 20, 1),
+	PIN_FIELD_BASE(65, 65, 9, 0x0040, 0x10, 10, 1),
+	PIN_FIELD_BASE(66, 66, 9, 0x0040, 0x10, 12, 1),
+	PIN_FIELD_BASE(67, 67, 9, 0x0040, 0x10, 11, 1),
+	PIN_FIELD_BASE(68, 68, 9, 0x0040, 0x10, 13, 1),
+	PIN_FIELD_BASE(69, 69, 2, 0x0070, 0x10, 22, 1),
+	PIN_FIELD_BASE(70, 70, 2, 0x0070, 0x10, 21, 1),
+	PIN_FIELD_BASE(71, 71, 2, 0x0070, 0x10, 24, 1),
+	PIN_FIELD_BASE(72, 72, 2, 0x0070, 0x10, 23, 1),
+	PIN_FIELD_BASE(73, 73, 2, 0x0070, 0x10, 26, 1),
+	PIN_FIELD_BASE(74, 74, 2, 0x0070, 0x10, 25, 1),
+	PIN_FIELD_BASE(75, 75, 3, 0x0050, 0x10, 13, 1),
+	PIN_FIELD_BASE(76, 76, 2, 0x0070, 0x10, 27, 1),
+	PIN_FIELD_BASE(77, 77, 8, 0x0050, 0x10, 13, 1),
+	PIN_FIELD_BASE(78, 78, 8, 0x0050, 0x10, 12, 1),
+	PIN_FIELD_BASE(79, 79, 8, 0x0050, 0x10, 15, 1),
+	PIN_FIELD_BASE(80, 80, 8, 0x0050, 0x10, 14, 1),
+	PIN_FIELD_BASE(81, 81, 2, 0x0070, 0x10, 29, 1),
+	PIN_FIELD_BASE(82, 82, 2, 0x0070, 0x10, 28, 1),
+	PIN_FIELD_BASE(83, 83, 2, 0x0070, 0x10, 30, 1),
+	PIN_FIELD_BASE(84, 84, 7, 0x0050, 0x10, 24, 1),
+	PIN_FIELD_BASE(85, 85, 7, 0x0050, 0x10, 25, 1),
+	PIN_FIELD_BASE(86, 86, 7, 0x0050, 0x10, 26, 1),
+	PIN_FIELD_BASE(87, 87, 7, 0x0050, 0x10, 27, 1),
+	PIN_FIELD_BASE(88, 88, 5, 0x0060, 0x10, 20, 1),
+	PIN_FIELD_BASE(89, 89, 5, 0x0060, 0x10, 19, 1),
+	PIN_FIELD_BASE(90, 90, 5, 0x0060, 0x10, 22, 1),
+	PIN_FIELD_BASE(91, 91, 5, 0x0060, 0x10, 21, 1),
+	PIN_FIELD_BASE(92, 92, 5, 0x0060, 0x10, 16, 1),
+	PIN_FIELD_BASE(93, 93, 5, 0x0060, 0x10, 17, 1),
+	PIN_FIELD_BASE(94, 94, 5, 0x0060, 0x10, 23, 1),
+	PIN_FIELD_BASE(95, 95, 5, 0x0060, 0x10, 15, 1),
+	PIN_FIELD_BASE(96, 96, 5, 0x0060, 0x10, 18, 1),
+	PIN_FIELD_BASE(97, 97, 5, 0x0060, 0x10, 0, 1),
+	PIN_FIELD_BASE(98, 98, 5, 0x0060, 0x10, 5, 1),
+	PIN_FIELD_BASE(99, 99, 5, 0x0060, 0x10, 3, 1),
+	PIN_FIELD_BASE(100, 100, 5, 0x0060, 0x10, 4, 1),
+	PIN_FIELD_BASE(101, 101, 5, 0x0060, 0x10, 1, 1),
+	PIN_FIELD_BASE(102, 102, 5, 0x0060, 0x10, 2, 1),
+	PIN_FIELD_BASE(103, 103, 7, 0x0050, 0x10, 15, 1),
+	PIN_FIELD_BASE(104, 104, 7, 0x0050, 0x10, 12, 1),
+	PIN_FIELD_BASE(105, 105, 7, 0x0050, 0x10, 14, 1),
+	PIN_FIELD_BASE(106, 106, 7, 0x0050, 0x10, 13, 1),
+	PIN_FIELD_BASE(107, 107, 7, 0x0050, 0x10, 19, 1),
+	PIN_FIELD_BASE(108, 108, 7, 0x0050, 0x10, 16, 1),
+	PIN_FIELD_BASE(109, 109, 7, 0x0050, 0x10, 18, 1),
+	PIN_FIELD_BASE(110, 110, 7, 0x0050, 0x10, 17, 1),
+	PIN_FIELD_BASE(111, 111, 7, 0x0050, 0x10, 4, 1),
+	PIN_FIELD_BASE(112, 112, 8, 0x0050, 0x10, 0, 1),
+	PIN_FIELD_BASE(113, 113, 8, 0x0050, 0x10, 1, 1),
+	PIN_FIELD_BASE(114, 114, 8, 0x0050, 0x10, 2, 1),
+	PIN_FIELD_BASE(115, 115, 2, 0x0070, 0x10, 9, 1),
+	PIN_FIELD_BASE(116, 116, 2, 0x0070, 0x10, 12, 1),
+	PIN_FIELD_BASE(117, 117, 2, 0x0070, 0x10, 10, 1),
+	PIN_FIELD_BASE(118, 118, 2, 0x0070, 0x10, 11, 1),
+	PIN_FIELD_BASE(119, 119, 1, 0x0050, 0x10, 26, 1),
+	PIN_FIELD_BASE(120, 120, 1, 0x0050, 0x10, 25, 1),
+	PIN_FIELD_BASE(121, 121, 1, 0x0050, 0x10, 24, 1),
+	PIN_FIELD_BASE(122, 122, 1, 0x0050, 0x10, 23, 1),
+	PIN_FIELD_BASE(123, 123, 1, 0x0050, 0x10, 19, 1),
+	PIN_FIELD_BASE(124, 124, 1, 0x0050, 0x10, 18, 1),
+	PIN_FIELD_BASE(125, 125, 1, 0x0050, 0x10, 17, 1),
+	PIN_FIELD_BASE(126, 126, 1, 0x0050, 0x10, 16, 1),
+	PIN_FIELD_BASE(127, 127, 1, 0x0050, 0x10, 22, 1),
+	PIN_FIELD_BASE(128, 128, 1, 0x0050, 0x10, 15, 1),
+	PIN_FIELD_BASE(129, 129, 1, 0x0050, 0x10, 20, 1),
+	PIN_FIELD_BASE(130, 130, 1, 0x0050, 0x10, 27, 1),
+	PIN_FIELD_BASE(131, 131, 1, 0x0050, 0x10, 13, 1),
+	PIN_FIELD_BASE(132, 132, 1, 0x0050, 0x10, 14, 1),
+	PIN_FIELD_BASE(133, 133, 1, 0x0050, 0x10, 28, 1),
+	PIN_FIELD_BASE(134, 134, 1, 0x0050, 0x10, 21, 1),
+	PIN_FIELD_BASE(135, 135, 1, 0x0050, 0x10, 11, 1),
+	PIN_FIELD_BASE(136, 136, 1, 0x0050, 0x10, 12, 1),
+	PIN_FIELD_BASE(137, 137, 2, 0x0070, 0x10, 3, 1),
+	PIN_FIELD_BASE(138, 138, 2, 0x0070, 0x10, 4, 1),
+	PIN_FIELD_BASE(139, 139, 1, 0x0050, 0x10, 3, 1),
+	PIN_FIELD_BASE(140, 140, 1, 0x0050, 0x10, 4, 1),
+	PIN_FIELD_BASE(141, 141, 1, 0x0050, 0x10, 0, 1),
+	PIN_FIELD_BASE(142, 142, 1, 0x0050, 0x10, 1, 1),
+	PIN_FIELD_BASE(143, 143, 1, 0x0050, 0x10, 2, 1),
+	PIN_FIELD_BASE(144, 144, 1, 0x0050, 0x10, 5, 1),
+	PIN_FIELD_BASE(145, 145, 1, 0x0050, 0x10, 6, 1),
+	PIN_FIELD_BASE(146, 146, 1, 0x0050, 0x10, 7, 1),
+	PIN_FIELD_BASE(147, 147, 1, 0x0050, 0x10, 8, 1),
+	PIN_FIELD_BASE(148, 148, 1, 0x0050, 0x10, 9, 1),
+	PIN_FIELD_BASE(149, 149, 1, 0x0050, 0x10, 10, 1),
+	PIN_FIELD_BASE(150, 150, 3, 0x0050, 0x10, 14, 1),
+	PIN_FIELD_BASE(151, 151, 1, 0x0050, 0x10, 29, 1),
+	PIN_FIELD_BASE(152, 152, 3, 0x0050, 0x10, 15, 1),
+	PIN_FIELD_BASE(153, 153, 3, 0x0050, 0x10, 16, 1),
+	PIN_FIELD_BASE(154, 154, 3, 0x0050, 0x10, 17, 1),
+	PIN_FIELD_BASE(155, 155, 3, 0x0050, 0x10, 18, 1),
+	PIN_FIELD_BASE(156, 156, 5, 0x0060, 0x10, 12, 1),
+	PIN_FIELD_BASE(157, 157, 5, 0x0060, 0x10, 11, 1),
+	PIN_FIELD_BASE(158, 158, 5, 0x0060, 0x10, 10, 1),
+	PIN_FIELD_BASE(159, 159, 6, 0x0020, 0x10, 2, 1),
+	PIN_FIELD_BASE(160, 160, 5, 0x0060, 0x10, 14, 1),
+	PIN_FIELD_BASE(161, 161, 5, 0x0060, 0x10, 7, 1),
+	PIN_FIELD_BASE(162, 162, 5, 0x0060, 0x10, 6, 1),
+	PIN_FIELD_BASE(163, 163, 6, 0x0020, 0x10, 1, 1),
+	PIN_FIELD_BASE(164, 164, 5, 0x0060, 0x10, 9, 1),
+	PIN_FIELD_BASE(165, 165, 5, 0x0060, 0x10, 8, 1),
+	PIN_FIELD_BASE(166, 166, 6, 0x0020, 0x10, 0, 1),
+	PIN_FIELD_BASE(167, 167, 5, 0x0060, 0x10, 13, 1),
+	PIN_FIELD_BASE(168, 168, 3, 0x0050, 0x10, 8, 1),
+	PIN_FIELD_BASE(169, 169, 3, 0x0050, 0x10, 7, 1),
+	PIN_FIELD_BASE(170, 170, 3, 0x0050, 0x10, 9, 1),
+	PIN_FIELD_BASE(171, 171, 3, 0x0050, 0x10, 10, 1),
+	PIN_FIELD_BASE(172, 172, 3, 0x0050, 0x10, 11, 1),
+	PIN_FIELD_BASE(173, 173, 3, 0x0050, 0x10, 12, 1),
+	PIN_FIELD_BASE(174, 174, 9, 0x0040, 0x10, 5, 1),
+	PIN_FIELD_BASE(175, 175, 9, 0x0040, 0x10, 4, 1),
+	PIN_FIELD_BASE(176, 176, 9, 0x0040, 0x10, 6, 1),
+	PIN_FIELD_BASE(177, 177, 9, 0x0040, 0x10, 7, 1),
+	PIN_FIELD_BASE(178, 178, 9, 0x0040, 0x10, 8, 1),
+	PIN_FIELD_BASE(179, 179, 9, 0x0040, 0x10, 9, 1),
+	PIN_FIELD_BASE(180, 180, 5, 0x0060, 0x10, 24, 1),
+	PIN_FIELD_BASE(181, 181, 5, 0x0060, 0x10, 25, 1),
+	PIN_FIELD_BASE(182, 182, 9, 0x0040, 0x10, 3, 1),
+};
+
+static const struct mtk_pin_field_calc mt8189_pin_tdsel_range[] = {
+	PIN_FIELD_BASE(0, 0, 7, 0x00f0, 0x10, 0, 4),
+	PIN_FIELD_BASE(1, 1, 8, 0x00d0, 0x10, 0, 4),
+	PIN_FIELD_BASE(2, 2, 8, 0x00d0, 0x10, 4, 4),
+	PIN_FIELD_BASE(3, 3, 8, 0x00d0, 0x10, 8, 4),
+	PIN_FIELD_BASE(4, 4, 8, 0x00d0, 0x10, 12, 4),
+	PIN_FIELD_BASE(5, 5, 8, 0x00d0, 0x10, 16, 4),
+	PIN_FIELD_BASE(6, 6, 7, 0x00f0, 0x10, 4, 4),
+	PIN_FIELD_BASE(7, 7, 7, 0x00f0, 0x10, 8, 4),
+	PIN_FIELD_BASE(8, 8, 7, 0x00f0, 0x10, 12, 4),
+	PIN_FIELD_BASE(9, 9, 7, 0x00f0, 0x10, 16, 4),
+	PIN_FIELD_BASE(10, 10, 7, 0x00f0, 0x10, 20, 4),
+	PIN_FIELD_BASE(11, 11, 7, 0x00f0, 0x10, 24, 4),
+	PIN_FIELD_BASE(12, 12, 2, 0x00f0, 0x10, 12, 4),
+	PIN_FIELD_BASE(13, 13, 2, 0x00f0, 0x10, 16, 4),
+	PIN_FIELD_BASE(14, 14, 3, 0x0110, 0x10, 0, 4),
+	PIN_FIELD_BASE(15, 15, 3, 0x0110, 0x10, 4, 4),
+	PIN_FIELD_BASE(16, 16, 2, 0x00f0, 0x10, 20, 4),
+	PIN_FIELD_BASE(17, 17, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(18, 18, 7, 0x0100, 0x10, 28, 4),
+	PIN_FIELD_BASE(19, 19, 7, 0x0110, 0x10, 0, 4),
+	PIN_FIELD_BASE(20, 20, 7, 0x0110, 0x10, 0, 4),
+	PIN_FIELD_BASE(21, 21, 7, 0x0110, 0x10, 0, 4),
+	PIN_FIELD_BASE(22, 22, 9, 0x0110, 0x10, 0, 4),
+	PIN_FIELD_BASE(23, 23, 9, 0x0110, 0x10, 4, 4),
+	PIN_FIELD_BASE(24, 24, 9, 0x0110, 0x10, 8, 4),
+	PIN_FIELD_BASE(25, 25, 4, 0x00d0, 0x10, 12, 4),
+	PIN_FIELD_BASE(26, 26, 4, 0x00d0, 0x10, 8, 4),
+	PIN_FIELD_BASE(27, 27, 2, 0x00f0, 0x10, 4, 4),
+	PIN_FIELD_BASE(28, 28, 2, 0x00f0, 0x10, 8, 4),
+	PIN_FIELD_BASE(29, 29, 4, 0x00d0, 0x10, 8, 4),
+	PIN_FIELD_BASE(30, 30, 2, 0x00f0, 0x10, 0, 4),
+	PIN_FIELD_BASE(31, 31, 3, 0x0120, 0x10, 8, 4),
+	PIN_FIELD_BASE(32, 32, 1, 0x00f0, 0x10, 16, 4),
+	PIN_FIELD_BASE(33, 33, 3, 0x0120, 0x10, 16, 4),
+	PIN_FIELD_BASE(34, 34, 3, 0x0120, 0x10, 4, 4),
+	PIN_FIELD_BASE(35, 35, 3, 0x0120, 0x10, 0, 4),
+	PIN_FIELD_BASE(36, 36, 3, 0x0120, 0x10, 8, 4),
+	PIN_FIELD_BASE(37, 37, 3, 0x0120, 0x10, 4, 4),
+	PIN_FIELD_BASE(38, 38, 3, 0x0120, 0x10, 4, 4),
+	PIN_FIELD_BASE(39, 39, 3, 0x0120, 0x10, 8, 4),
+	PIN_FIELD_BASE(40, 40, 3, 0x0120, 0x10, 8, 4),
+	PIN_FIELD_BASE(41, 41, 3, 0x0120, 0x10, 8, 4),
+	PIN_FIELD_BASE(42, 42, 3, 0x0120, 0x10, 8, 4),
+	PIN_FIELD_BASE(43, 43, 3, 0x0120, 0x10, 8, 4),
+	PIN_FIELD_BASE(44, 44, 7, 0x0110, 0x10, 0, 4),
+	PIN_FIELD_BASE(45, 45, 7, 0x0110, 0x10, 0, 4),
+	PIN_FIELD_BASE(46, 46, 7, 0x0110, 0x10, 0, 4),
+	PIN_FIELD_BASE(47, 47, 7, 0x0110, 0x10, 0, 4),
+	PIN_FIELD_BASE(48, 48, 4, 0x00d0, 0x10, 8, 4),
+	PIN_FIELD_BASE(49, 49, 4, 0x00d0, 0x10, 4, 4),
+	PIN_FIELD_BASE(50, 50, 4, 0x00d0, 0x10, 0, 4),
+	PIN_FIELD_BASE(51, 51, 8, 0x00d0, 0x10, 20, 4),
+	PIN_FIELD_BASE(52, 52, 8, 0x00d0, 0x10, 20, 4),
+	PIN_FIELD_BASE(53, 53, 8, 0x00d0, 0x10, 20, 4),
+	PIN_FIELD_BASE(54, 54, 8, 0x00d0, 0x10, 20, 4),
+	PIN_FIELD_BASE(55, 55, 4, 0x00d0, 0x10, 12, 4),
+	PIN_FIELD_BASE(56, 56, 4, 0x00d0, 0x10, 12, 4),
+	PIN_FIELD_BASE(57, 57, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(58, 58, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(59, 59, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(60, 60, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(61, 61, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(62, 62, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(63, 63, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(64, 64, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(65, 65, 9, 0x0120, 0x10, 4, 4),
+	PIN_FIELD_BASE(66, 66, 9, 0x0120, 0x10, 4, 4),
+	PIN_FIELD_BASE(67, 67, 9, 0x0120, 0x10, 4, 4),
+	PIN_FIELD_BASE(68, 68, 9, 0x0120, 0x10, 4, 4),
+	PIN_FIELD_BASE(69, 69, 2, 0x0100, 0x10, 4, 4),
+	PIN_FIELD_BASE(70, 70, 2, 0x0100, 0x10, 0, 4),
+	PIN_FIELD_BASE(71, 71, 2, 0x0100, 0x10, 12, 4),
+	PIN_FIELD_BASE(72, 72, 2, 0x0100, 0x10, 8, 4),
+	PIN_FIELD_BASE(73, 73, 2, 0x0100, 0x10, 20, 4),
+	PIN_FIELD_BASE(74, 74, 2, 0x0100, 0x10, 16, 4),
+	PIN_FIELD_BASE(75, 75, 3, 0x0120, 0x10, 12, 4),
+	PIN_FIELD_BASE(76, 76, 2, 0x0100, 0x10, 24, 4),
+	PIN_FIELD_BASE(77, 77, 8, 0x00d0, 0x10, 28, 4),
+	PIN_FIELD_BASE(78, 78, 8, 0x00d0, 0x10, 24, 4),
+	PIN_FIELD_BASE(79, 79, 8, 0x00e0, 0x10, 4, 4),
+	PIN_FIELD_BASE(80, 80, 8, 0x00e0, 0x10, 0, 4),
+	PIN_FIELD_BASE(81, 81, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(82, 82, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(83, 83, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(84, 84, 7, 0x0110, 0x10, 0, 4),
+	PIN_FIELD_BASE(85, 85, 7, 0x0110, 0x10, 0, 4),
+	PIN_FIELD_BASE(86, 86, 7, 0x0110, 0x10, 0, 4),
+	PIN_FIELD_BASE(87, 87, 7, 0x0110, 0x10, 0, 4),
+	PIN_FIELD_BASE(88, 88, 5, 0x0140, 0x10, 4, 4),
+	PIN_FIELD_BASE(89, 89, 5, 0x0140, 0x10, 4, 4),
+	PIN_FIELD_BASE(90, 90, 5, 0x0140, 0x10, 4, 4),
+	PIN_FIELD_BASE(91, 91, 5, 0x0140, 0x10, 4, 4),
+	PIN_FIELD_BASE(92, 92, 5, 0x0140, 0x10, 8, 4),
+	PIN_FIELD_BASE(93, 93, 5, 0x0140, 0x10, 8, 4),
+	PIN_FIELD_BASE(94, 94, 5, 0x0140, 0x10, 8, 4),
+	PIN_FIELD_BASE(95, 95, 5, 0x0140, 0x10, 8, 4),
+	PIN_FIELD_BASE(96, 96, 5, 0x0140, 0x10, 12, 4),
+	PIN_FIELD_BASE(97, 97, 5, 0x0140, 0x10, 8, 4),
+	PIN_FIELD_BASE(98, 98, 5, 0x0140, 0x10, 8, 4),
+	PIN_FIELD_BASE(99, 99, 5, 0x0140, 0x10, 8, 4),
+	PIN_FIELD_BASE(100, 100, 5, 0x0140, 0x10, 8, 4),
+	PIN_FIELD_BASE(101, 101, 5, 0x0140, 0x10, 8, 4),
+	PIN_FIELD_BASE(102, 102, 5, 0x0140, 0x10, 8, 4),
+	PIN_FIELD_BASE(103, 103, 7, 0x0100, 0x10, 8, 4),
+	PIN_FIELD_BASE(104, 104, 7, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(105, 105, 7, 0x0100, 0x10, 4, 4),
+	PIN_FIELD_BASE(106, 106, 7, 0x0100, 0x10, 0, 4),
+	PIN_FIELD_BASE(107, 107, 7, 0x0100, 0x10, 24, 4),
+	PIN_FIELD_BASE(108, 108, 7, 0x0100, 0x10, 12, 4),
+	PIN_FIELD_BASE(109, 109, 7, 0x0100, 0x10, 20, 4),
+	PIN_FIELD_BASE(110, 110, 7, 0x0100, 0x10, 16, 4),
+	PIN_FIELD_BASE(111, 111, 7, 0x0110, 0x10, 0, 4),
+	PIN_FIELD_BASE(112, 112, 8, 0x00d0, 0x10, 20, 4),
+	PIN_FIELD_BASE(113, 113, 8, 0x00d0, 0x10, 20, 4),
+	PIN_FIELD_BASE(114, 114, 8, 0x00d0, 0x10, 20, 4),
+	PIN_FIELD_BASE(115, 115, 2, 0x00f0, 0x10, 24, 4),
+	PIN_FIELD_BASE(116, 116, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(117, 117, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(118, 118, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(119, 119, 1, 0x00e0, 0x10, 24, 4),
+	PIN_FIELD_BASE(120, 120, 1, 0x00e0, 0x10, 20, 4),
+	PIN_FIELD_BASE(121, 121, 1, 0x00e0, 0x10, 16, 4),
+	PIN_FIELD_BASE(122, 122, 1, 0x00e0, 0x10, 12, 4),
+	PIN_FIELD_BASE(123, 123, 1, 0x00d0, 0x10, 28, 4),
+	PIN_FIELD_BASE(124, 124, 1, 0x00d0, 0x10, 24, 4),
+	PIN_FIELD_BASE(125, 125, 1, 0x00d0, 0x10, 20, 4),
+	PIN_FIELD_BASE(126, 126, 1, 0x00d0, 0x10, 16, 4),
+	PIN_FIELD_BASE(127, 127, 1, 0x00e0, 0x10, 8, 4),
+	PIN_FIELD_BASE(128, 128, 1, 0x00d0, 0x10, 12, 4),
+	PIN_FIELD_BASE(129, 129, 1, 0x00e0, 0x10, 0, 4),
+	PIN_FIELD_BASE(130, 130, 1, 0x00e0, 0x10, 28, 4),
+	PIN_FIELD_BASE(131, 131, 1, 0x00d0, 0x10, 4, 4),
+	PIN_FIELD_BASE(132, 132, 1, 0x00d0, 0x10, 8, 4),
+	PIN_FIELD_BASE(133, 133, 1, 0x00f0, 0x10, 0, 4),
+	PIN_FIELD_BASE(134, 134, 1, 0x00e0, 0x10, 4, 4),
+	PIN_FIELD_BASE(135, 135, 1, 0x00d0, 0x10, 0, 4),
+	PIN_FIELD_BASE(136, 136, 1, 0x00f0, 0x10, 4, 4),
+	PIN_FIELD_BASE(137, 137, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(138, 138, 2, 0x00f0, 0x10, 28, 4),
+	PIN_FIELD_BASE(139, 139, 1, 0x00f0, 0x10, 12, 4),
+	PIN_FIELD_BASE(140, 140, 1, 0x00f0, 0x10, 12, 4),
+	PIN_FIELD_BASE(141, 141, 1, 0x00f0, 0x10, 12, 4),
+	PIN_FIELD_BASE(142, 142, 1, 0x00f0, 0x10, 12, 4),
+	PIN_FIELD_BASE(143, 143, 1, 0x00f0, 0x10, 12, 4),
+	PIN_FIELD_BASE(144, 144, 1, 0x00f0, 0x10, 12, 4),
+	PIN_FIELD_BASE(145, 145, 1, 0x00f0, 0x10, 8, 4),
+	PIN_FIELD_BASE(146, 146, 1, 0x00f0, 0x10, 8, 4),
+	PIN_FIELD_BASE(147, 147, 1, 0x00f0, 0x10, 8, 4),
+	PIN_FIELD_BASE(148, 148, 1, 0x00f0, 0x10, 8, 4),
+	PIN_FIELD_BASE(149, 149, 1, 0x00f0, 0x10, 8, 4),
+	PIN_FIELD_BASE(150, 150, 3, 0x0120, 0x10, 8, 4),
+	PIN_FIELD_BASE(151, 151, 1, 0x00f0, 0x10, 16, 4),
+	PIN_FIELD_BASE(152, 152, 3, 0x0120, 0x10, 8, 4),
+	PIN_FIELD_BASE(153, 153, 3, 0x0120, 0x10, 8, 4),
+	PIN_FIELD_BASE(154, 154, 3, 0x0120, 0x10, 8, 4),
+	PIN_FIELD_BASE(155, 155, 3, 0x0120, 0x10, 8, 4),
+	PIN_FIELD_BASE(156, 156, 5, 0x0130, 0x10, 24, 4),
+	PIN_FIELD_BASE(157, 157, 5, 0x0130, 0x10, 20, 4),
+	PIN_FIELD_BASE(158, 158, 5, 0x0130, 0x10, 16, 4),
+	PIN_FIELD_BASE(159, 159, 6, 0x00a0, 0x10, 8, 4),
+	PIN_FIELD_BASE(160, 160, 5, 0x0140, 0x10, 0, 4),
+	PIN_FIELD_BASE(161, 161, 5, 0x0130, 0x10, 4, 4),
+	PIN_FIELD_BASE(162, 162, 5, 0x0130, 0x10, 0, 4),
+	PIN_FIELD_BASE(163, 163, 6, 0x00a0, 0x10, 4, 4),
+	PIN_FIELD_BASE(164, 164, 5, 0x0130, 0x10, 12, 4),
+	PIN_FIELD_BASE(165, 165, 5, 0x0130, 0x10, 8, 4),
+	PIN_FIELD_BASE(166, 166, 6, 0x00a0, 0x10, 0, 4),
+	PIN_FIELD_BASE(167, 167, 5, 0x0130, 0x10, 28, 4),
+	PIN_FIELD_BASE(168, 168, 3, 0x0110, 0x10, 12, 4),
+	PIN_FIELD_BASE(169, 169, 3, 0x0110, 0x10, 8, 4),
+	PIN_FIELD_BASE(170, 170, 3, 0x0110, 0x10, 16, 4),
+	PIN_FIELD_BASE(171, 171, 3, 0x0110, 0x10, 20, 4),
+	PIN_FIELD_BASE(172, 172, 3, 0x0110, 0x10, 24, 4),
+	PIN_FIELD_BASE(173, 173, 3, 0x0110, 0x10, 28, 4),
+	PIN_FIELD_BASE(174, 174, 9, 0x0110, 0x10, 16, 4),
+	PIN_FIELD_BASE(175, 175, 9, 0x0110, 0x10, 12, 4),
+	PIN_FIELD_BASE(176, 176, 9, 0x0110, 0x10, 20, 4),
+	PIN_FIELD_BASE(177, 177, 9, 0x0110, 0x10, 24, 4),
+	PIN_FIELD_BASE(178, 178, 9, 0x0110, 0x10, 28, 4),
+	PIN_FIELD_BASE(179, 179, 9, 0x0120, 0x10, 0, 4),
+	PIN_FIELD_BASE(180, 180, 5, 0x0140, 0x10, 16, 4),
+	PIN_FIELD_BASE(181, 181, 5, 0x0140, 0x10, 20, 4),
+	PIN_FIELD_BASE(182, 182, 9, 0x0120, 0x10, 8, 4),
+};
+
+static const struct mtk_pin_field_calc mt8189_pin_rdsel_range[] = {
+	PIN_FIELD_BASE(0, 0, 7, 0x00d0, 0x10, 0, 2),
+	PIN_FIELD_BASE(1, 1, 8, 0x00a0, 0x10, 0, 2),
+	PIN_FIELD_BASE(2, 2, 8, 0x00a0, 0x10, 2, 2),
+	PIN_FIELD_BASE(3, 3, 8, 0x00a0, 0x10, 4, 2),
+	PIN_FIELD_BASE(4, 4, 8, 0x00a0, 0x10, 6, 2),
+	PIN_FIELD_BASE(5, 5, 8, 0x00a0, 0x10, 8, 2),
+	PIN_FIELD_BASE(6, 6, 7, 0x00d0, 0x10, 2, 2),
+	PIN_FIELD_BASE(7, 7, 7, 0x00d0, 0x10, 4, 2),
+	PIN_FIELD_BASE(8, 8, 7, 0x00d0, 0x10, 6, 2),
+	PIN_FIELD_BASE(9, 9, 7, 0x00d0, 0x10, 8, 2),
+	PIN_FIELD_BASE(10, 10, 7, 0x00d0, 0x10, 10, 2),
+	PIN_FIELD_BASE(11, 11, 7, 0x00d0, 0x10, 12, 2),
+	PIN_FIELD_BASE(12, 12, 2, 0x00c0, 0x10, 6, 2),
+	PIN_FIELD_BASE(13, 13, 2, 0x00c0, 0x10, 8, 2),
+	PIN_FIELD_BASE(14, 14, 3, 0x00d0, 0x10, 0, 2),
+	PIN_FIELD_BASE(15, 15, 3, 0x00d0, 0x10, 2, 2),
+	PIN_FIELD_BASE(16, 16, 2, 0x00c0, 0x10, 10, 2),
+	PIN_FIELD_BASE(17, 17, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(18, 18, 7, 0x00d0, 0x10, 30, 2),
+	PIN_FIELD_BASE(19, 19, 7, 0x00d0, 0x10, 30, 2),
+	PIN_FIELD_BASE(20, 20, 7, 0x00d0, 0x10, 30, 2),
+	PIN_FIELD_BASE(21, 21, 7, 0x00d0, 0x10, 30, 2),
+	PIN_FIELD_BASE(22, 22, 9, 0x00c0, 0x10, 0, 2),
+	PIN_FIELD_BASE(23, 23, 9, 0x00c0, 0x10, 2, 2),
+	PIN_FIELD_BASE(24, 24, 9, 0x00c0, 0x10, 4, 2),
+	PIN_FIELD_BASE(25, 25, 4, 0x00a0, 0x10, 6, 2),
+	PIN_FIELD_BASE(26, 26, 4, 0x00a0, 0x10, 4, 2),
+	PIN_FIELD_BASE(27, 27, 2, 0x00c0, 0x10, 2, 2),
+	PIN_FIELD_BASE(28, 28, 2, 0x00c0, 0x10, 4, 2),
+	PIN_FIELD_BASE(29, 29, 4, 0x00a0, 0x10, 4, 2),
+	PIN_FIELD_BASE(30, 30, 2, 0x00c0, 0x10, 0, 2),
+	PIN_FIELD_BASE(31, 31, 3, 0x00e0, 0x10, 16, 2),
+	PIN_FIELD_BASE(32, 32, 1, 0x00b0, 0x10, 8, 2),
+	PIN_FIELD_BASE(33, 33, 3, 0x00e0, 0x10, 20, 2),
+	PIN_FIELD_BASE(34, 34, 3, 0x00e0, 0x10, 14, 2),
+	PIN_FIELD_BASE(35, 35, 3, 0x00e0, 0x10, 12, 2),
+	PIN_FIELD_BASE(36, 36, 3, 0x00e0, 0x10, 16, 2),
+	PIN_FIELD_BASE(37, 37, 3, 0x00e0, 0x10, 14, 2),
+	PIN_FIELD_BASE(38, 38, 3, 0x00e0, 0x10, 14, 2),
+	PIN_FIELD_BASE(39, 39, 3, 0x00e0, 0x10, 16, 2),
+	PIN_FIELD_BASE(40, 40, 3, 0x00e0, 0x10, 16, 2),
+	PIN_FIELD_BASE(41, 41, 3, 0x00e0, 0x10, 16, 2),
+	PIN_FIELD_BASE(42, 42, 3, 0x00e0, 0x10, 16, 2),
+	PIN_FIELD_BASE(43, 43, 3, 0x00e0, 0x10, 16, 2),
+	PIN_FIELD_BASE(44, 44, 7, 0x00d0, 0x10, 30, 2),
+	PIN_FIELD_BASE(45, 45, 7, 0x00d0, 0x10, 30, 2),
+	PIN_FIELD_BASE(46, 46, 7, 0x00d0, 0x10, 30, 2),
+	PIN_FIELD_BASE(47, 47, 7, 0x00d0, 0x10, 30, 2),
+	PIN_FIELD_BASE(48, 48, 4, 0x00a0, 0x10, 4, 2),
+	PIN_FIELD_BASE(49, 49, 4, 0x00a0, 0x10, 2, 2),
+	PIN_FIELD_BASE(50, 50, 4, 0x00a0, 0x10, 0, 2),
+	PIN_FIELD_BASE(51, 51, 8, 0x00a0, 0x10, 10, 2),
+	PIN_FIELD_BASE(52, 52, 8, 0x00a0, 0x10, 10, 2),
+	PIN_FIELD_BASE(53, 53, 8, 0x00a0, 0x10, 10, 2),
+	PIN_FIELD_BASE(54, 54, 8, 0x00a0, 0x10, 10, 2),
+	PIN_FIELD_BASE(55, 55, 4, 0x00a0, 0x10, 6, 2),
+	PIN_FIELD_BASE(56, 56, 4, 0x00a0, 0x10, 6, 2),
+	PIN_FIELD_BASE(57, 57, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(58, 58, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(59, 59, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(60, 60, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(61, 61, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(62, 62, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(63, 63, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(64, 64, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(65, 65, 9, 0x00d0, 0x10, 12, 2),
+	PIN_FIELD_BASE(66, 66, 9, 0x00d0, 0x10, 12, 2),
+	PIN_FIELD_BASE(67, 67, 9, 0x00d0, 0x10, 12, 2),
+	PIN_FIELD_BASE(68, 68, 9, 0x00d0, 0x10, 12, 2),
+	PIN_FIELD_BASE(69, 69, 2, 0x00c0, 0x10, 16, 2),
+	PIN_FIELD_BASE(70, 70, 2, 0x00c0, 0x10, 14, 2),
+	PIN_FIELD_BASE(71, 71, 2, 0x00c0, 0x10, 20, 2),
+	PIN_FIELD_BASE(72, 72, 2, 0x00c0, 0x10, 18, 2),
+	PIN_FIELD_BASE(73, 73, 2, 0x00c0, 0x10, 24, 2),
+	PIN_FIELD_BASE(74, 74, 2, 0x00c0, 0x10, 22, 2),
+	PIN_FIELD_BASE(75, 75, 3, 0x00e0, 0x10, 18, 2),
+	PIN_FIELD_BASE(76, 76, 2, 0x00c0, 0x10, 26, 2),
+	PIN_FIELD_BASE(77, 77, 8, 0x00a0, 0x10, 14, 2),
+	PIN_FIELD_BASE(78, 78, 8, 0x00a0, 0x10, 12, 2),
+	PIN_FIELD_BASE(79, 79, 8, 0x00a0, 0x10, 18, 2),
+	PIN_FIELD_BASE(80, 80, 8, 0x00a0, 0x10, 16, 2),
+	PIN_FIELD_BASE(81, 81, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(82, 82, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(83, 83, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(84, 84, 7, 0x00d0, 0x10, 30, 2),
+	PIN_FIELD_BASE(85, 85, 7, 0x00d0, 0x10, 30, 2),
+	PIN_FIELD_BASE(86, 86, 7, 0x00d0, 0x10, 30, 2),
+	PIN_FIELD_BASE(87, 87, 7, 0x00d0, 0x10, 30, 2),
+	PIN_FIELD_BASE(88, 88, 5, 0x00f0, 0x10, 24, 2),
+	PIN_FIELD_BASE(89, 89, 5, 0x00f0, 0x10, 24, 2),
+	PIN_FIELD_BASE(90, 90, 5, 0x00f0, 0x10, 24, 2),
+	PIN_FIELD_BASE(91, 91, 5, 0x00f0, 0x10, 24, 2),
+	PIN_FIELD_BASE(92, 92, 5, 0x00f0, 0x10, 26, 2),
+	PIN_FIELD_BASE(93, 93, 5, 0x00f0, 0x10, 26, 2),
+	PIN_FIELD_BASE(94, 94, 5, 0x00f0, 0x10, 26, 2),
+	PIN_FIELD_BASE(95, 95, 5, 0x00f0, 0x10, 26, 2),
+	PIN_FIELD_BASE(96, 96, 5, 0x00f0, 0x10, 28, 2),
+	PIN_FIELD_BASE(97, 97, 5, 0x00f0, 0x10, 26, 2),
+	PIN_FIELD_BASE(98, 98, 5, 0x00f0, 0x10, 26, 2),
+	PIN_FIELD_BASE(99, 99, 5, 0x00f0, 0x10, 26, 2),
+	PIN_FIELD_BASE(100, 100, 5, 0x00f0, 0x10, 26, 2),
+	PIN_FIELD_BASE(101, 101, 5, 0x00f0, 0x10, 26, 2),
+	PIN_FIELD_BASE(102, 102, 5, 0x00f0, 0x10, 26, 2),
+	PIN_FIELD_BASE(103, 103, 7, 0x00d0, 0x10, 20, 2),
+	PIN_FIELD_BASE(104, 104, 7, 0x00d0, 0x10, 14, 2),
+	PIN_FIELD_BASE(105, 105, 7, 0x00d0, 0x10, 18, 2),
+	PIN_FIELD_BASE(106, 106, 7, 0x00d0, 0x10, 16, 2),
+	PIN_FIELD_BASE(107, 107, 7, 0x00d0, 0x10, 28, 2),
+	PIN_FIELD_BASE(108, 108, 7, 0x00d0, 0x10, 22, 2),
+	PIN_FIELD_BASE(109, 109, 7, 0x00d0, 0x10, 26, 2),
+	PIN_FIELD_BASE(110, 110, 7, 0x00d0, 0x10, 24, 2),
+	PIN_FIELD_BASE(111, 111, 7, 0x00d0, 0x10, 30, 2),
+	PIN_FIELD_BASE(112, 112, 8, 0x00a0, 0x10, 10, 2),
+	PIN_FIELD_BASE(113, 113, 8, 0x00a0, 0x10, 10, 2),
+	PIN_FIELD_BASE(114, 114, 8, 0x00a0, 0x10, 10, 2),
+	PIN_FIELD_BASE(115, 115, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(116, 116, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(117, 117, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(118, 118, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(119, 119, 1, 0x00a0, 0x10, 28, 2),
+	PIN_FIELD_BASE(120, 120, 1, 0x00a0, 0x10, 26, 2),
+	PIN_FIELD_BASE(121, 121, 1, 0x00a0, 0x10, 24, 2),
+	PIN_FIELD_BASE(122, 122, 1, 0x00a0, 0x10, 22, 2),
+	PIN_FIELD_BASE(123, 123, 1, 0x00a0, 0x10, 14, 2),
+	PIN_FIELD_BASE(124, 124, 1, 0x00a0, 0x10, 12, 2),
+	PIN_FIELD_BASE(125, 125, 1, 0x00a0, 0x10, 10, 2),
+	PIN_FIELD_BASE(126, 126, 1, 0x00a0, 0x10, 8, 2),
+	PIN_FIELD_BASE(127, 127, 1, 0x00a0, 0x10, 20, 2),
+	PIN_FIELD_BASE(128, 128, 1, 0x00a0, 0x10, 6, 2),
+	PIN_FIELD_BASE(129, 129, 1, 0x00a0, 0x10, 16, 2),
+	PIN_FIELD_BASE(130, 130, 1, 0x00a0, 0x10, 30, 2),
+	PIN_FIELD_BASE(131, 131, 1, 0x00a0, 0x10, 2, 2),
+	PIN_FIELD_BASE(132, 132, 1, 0x00a0, 0x10, 4, 2),
+	PIN_FIELD_BASE(133, 133, 1, 0x00b0, 0x10, 0, 2),
+	PIN_FIELD_BASE(134, 134, 1, 0x00a0, 0x10, 18, 2),
+	PIN_FIELD_BASE(135, 135, 1, 0x00a0, 0x10, 0, 2),
+	PIN_FIELD_BASE(136, 136, 1, 0x00b0, 0x10, 2, 2),
+	PIN_FIELD_BASE(137, 137, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(138, 138, 2, 0x00c0, 0x10, 12, 2),
+	PIN_FIELD_BASE(139, 139, 1, 0x00b0, 0x10, 6, 2),
+	PIN_FIELD_BASE(140, 140, 1, 0x00b0, 0x10, 6, 2),
+	PIN_FIELD_BASE(141, 141, 1, 0x00b0, 0x10, 6, 2),
+	PIN_FIELD_BASE(142, 142, 1, 0x00b0, 0x10, 6, 2),
+	PIN_FIELD_BASE(143, 143, 1, 0x00b0, 0x10, 6, 2),
+	PIN_FIELD_BASE(144, 144, 1, 0x00b0, 0x10, 6, 2),
+	PIN_FIELD_BASE(145, 145, 1, 0x00b0, 0x10, 4, 2),
+	PIN_FIELD_BASE(146, 146, 1, 0x00b0, 0x10, 4, 2),
+	PIN_FIELD_BASE(147, 147, 1, 0x00b0, 0x10, 4, 2),
+	PIN_FIELD_BASE(148, 148, 1, 0x00b0, 0x10, 4, 2),
+	PIN_FIELD_BASE(149, 149, 1, 0x00b0, 0x10, 4, 2),
+	PIN_FIELD_BASE(150, 150, 3, 0x00e0, 0x10, 16, 2),
+	PIN_FIELD_BASE(151, 151, 1, 0x00b0, 0x10, 8, 2),
+	PIN_FIELD_BASE(152, 152, 3, 0x00e0, 0x10, 16, 2),
+	PIN_FIELD_BASE(153, 153, 3, 0x00e0, 0x10, 16, 2),
+	PIN_FIELD_BASE(154, 154, 3, 0x00e0, 0x10, 16, 2),
+	PIN_FIELD_BASE(155, 155, 3, 0x00e0, 0x10, 16, 2),
+	PIN_FIELD_BASE(156, 156, 5, 0x00f0, 0x10, 6, 6),
+	PIN_FIELD_BASE(157, 157, 5, 0x00f0, 0x10, 0, 6),
+	PIN_FIELD_BASE(158, 158, 5, 0x00e0, 0x10, 24, 6),
+	PIN_FIELD_BASE(159, 159, 6, 0x0080, 0x10, 12, 6),
+	PIN_FIELD_BASE(160, 160, 5, 0x00f0, 0x10, 18, 6),
+	PIN_FIELD_BASE(161, 161, 5, 0x00e0, 0x10, 6, 6),
+	PIN_FIELD_BASE(162, 162, 5, 0x00e0, 0x10, 0, 6),
+	PIN_FIELD_BASE(163, 163, 6, 0x0080, 0x10, 6, 6),
+	PIN_FIELD_BASE(164, 164, 5, 0x00e0, 0x10, 18, 6),
+	PIN_FIELD_BASE(165, 165, 5, 0x00e0, 0x10, 12, 6),
+	PIN_FIELD_BASE(166, 166, 6, 0x0080, 0x10, 0, 6),
+	PIN_FIELD_BASE(167, 167, 5, 0x00f0, 0x10, 12, 6),
+	PIN_FIELD_BASE(168, 168, 3, 0x00d0, 0x10, 10, 6),
+	PIN_FIELD_BASE(169, 169, 3, 0x00d0, 0x10, 4, 6),
+	PIN_FIELD_BASE(170, 170, 3, 0x00d0, 0x10, 16, 6),
+	PIN_FIELD_BASE(171, 171, 3, 0x00d0, 0x10, 22, 6),
+	PIN_FIELD_BASE(172, 172, 3, 0x00e0, 0x10, 0, 6),
+	PIN_FIELD_BASE(173, 173, 3, 0x00e0, 0x10, 6, 6),
+	PIN_FIELD_BASE(174, 174, 9, 0x00c0, 0x10, 12, 6),
+	PIN_FIELD_BASE(175, 175, 9, 0x00c0, 0x10, 6, 6),
+	PIN_FIELD_BASE(176, 176, 9, 0x00c0, 0x10, 18, 6),
+	PIN_FIELD_BASE(177, 177, 9, 0x00c0, 0x10, 24, 6),
+	PIN_FIELD_BASE(178, 178, 9, 0x00d0, 0x10, 0, 6),
+	PIN_FIELD_BASE(179, 179, 9, 0x00d0, 0x10, 6, 6),
+	PIN_FIELD_BASE(180, 180, 5, 0x00f0, 0x10, 30, 2),
+	PIN_FIELD_BASE(181, 181, 5, 0x0100, 0x10, 0, 2),
+	PIN_FIELD_BASE(182, 182, 9, 0x00d0, 0x10, 14, 2),
+};
+
+static const struct mtk_pin_field_calc mt8189_pin_pupd_range[] = {
+	PIN_FIELD_BASE(44, 44, 7, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(45, 45, 7, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(46, 46, 7, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(47, 47, 7, 0x0090, 0x10, 3, 1),
+	PIN_FIELD_BASE(156, 156, 5, 0x00a0, 0x10, 6, 1),
+	PIN_FIELD_BASE(157, 157, 5, 0x00a0, 0x10, 5, 1),
+	PIN_FIELD_BASE(158, 158, 5, 0x00a0, 0x10, 4, 1),
+	PIN_FIELD_BASE(159, 159, 6, 0x0050, 0x10, 2, 1),
+	PIN_FIELD_BASE(160, 160, 5, 0x00a0, 0x10, 8, 1),
+	PIN_FIELD_BASE(161, 161, 5, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(162, 162, 5, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(163, 163, 6, 0x0050, 0x10, 1, 1),
+	PIN_FIELD_BASE(164, 164, 5, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(165, 165, 5, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(166, 166, 6, 0x0050, 0x10, 0, 1),
+	PIN_FIELD_BASE(167, 167, 5, 0x00a0, 0x10, 7, 1),
+	PIN_FIELD_BASE(168, 168, 3, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(169, 169, 3, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(170, 170, 3, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(171, 171, 3, 0x0090, 0x10, 3, 1),
+	PIN_FIELD_BASE(172, 172, 3, 0x0090, 0x10, 4, 1),
+	PIN_FIELD_BASE(173, 173, 3, 0x0090, 0x10, 5, 1),
+	PIN_FIELD_BASE(174, 174, 9, 0x0080, 0x10, 1, 1),
+	PIN_FIELD_BASE(175, 175, 9, 0x0080, 0x10, 0, 1),
+	PIN_FIELD_BASE(176, 176, 9, 0x0080, 0x10, 2, 1),
+	PIN_FIELD_BASE(177, 177, 9, 0x0080, 0x10, 3, 1),
+	PIN_FIELD_BASE(178, 178, 9, 0x0080, 0x10, 4, 1),
+	PIN_FIELD_BASE(179, 179, 9, 0x0080, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt8189_pin_r0_range[] = {
+	PIN_FIELD_BASE(44, 44, 7, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(45, 45, 7, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(46, 46, 7, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(47, 47, 7, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(156, 156, 5, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(157, 157, 5, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(158, 158, 5, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(159, 159, 6, 0x0060, 0x10, 2, 1),
+	PIN_FIELD_BASE(160, 160, 5, 0x00c0, 0x10, 8, 1),
+	PIN_FIELD_BASE(161, 161, 5, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(162, 162, 5, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(163, 163, 6, 0x0060, 0x10, 1, 1),
+	PIN_FIELD_BASE(164, 164, 5, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(165, 165, 5, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(166, 166, 6, 0x0060, 0x10, 0, 1),
+	PIN_FIELD_BASE(167, 167, 5, 0x00c0, 0x10, 7, 1),
+	PIN_FIELD_BASE(168, 168, 3, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(169, 169, 3, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(170, 170, 3, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(171, 171, 3, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(172, 172, 3, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(173, 173, 3, 0x00b0, 0x10, 5, 1),
+	PIN_FIELD_BASE(174, 174, 9, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(175, 175, 9, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(176, 176, 9, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(177, 177, 9, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(178, 178, 9, 0x00a0, 0x10, 4, 1),
+	PIN_FIELD_BASE(179, 179, 9, 0x00a0, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt8189_pin_r1_range[] = {
+	PIN_FIELD_BASE(44, 44, 7, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(45, 45, 7, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(46, 46, 7, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(47, 47, 7, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(156, 156, 5, 0x00d0, 0x10, 6, 1),
+	PIN_FIELD_BASE(157, 157, 5, 0x00d0, 0x10, 5, 1),
+	PIN_FIELD_BASE(158, 158, 5, 0x00d0, 0x10, 4, 1),
+	PIN_FIELD_BASE(159, 159, 6, 0x0070, 0x10, 2, 1),
+	PIN_FIELD_BASE(160, 160, 5, 0x00d0, 0x10, 8, 1),
+	PIN_FIELD_BASE(161, 161, 5, 0x00d0, 0x10, 1, 1),
+	PIN_FIELD_BASE(162, 162, 5, 0x00d0, 0x10, 0, 1),
+	PIN_FIELD_BASE(163, 163, 6, 0x0070, 0x10, 1, 1),
+	PIN_FIELD_BASE(164, 164, 5, 0x00d0, 0x10, 3, 1),
+	PIN_FIELD_BASE(165, 165, 5, 0x00d0, 0x10, 2, 1),
+	PIN_FIELD_BASE(166, 166, 6, 0x0070, 0x10, 0, 1),
+	PIN_FIELD_BASE(167, 167, 5, 0x00d0, 0x10, 7, 1),
+	PIN_FIELD_BASE(168, 168, 3, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(169, 169, 3, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(170, 170, 3, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(171, 171, 3, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(172, 172, 3, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(173, 173, 3, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(174, 174, 9, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(175, 175, 9, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(176, 176, 9, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(177, 177, 9, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(178, 178, 9, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(179, 179, 9, 0x00b0, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt8189_pin_pu_range[] = {
+	PIN_FIELD_BASE(0, 0, 7, 0x00a0, 0x10, 5, 1),
+	PIN_FIELD_BASE(1, 1, 8, 0x0090, 0x10, 3, 1),
+	PIN_FIELD_BASE(2, 2, 8, 0x0090, 0x10, 4, 1),
+	PIN_FIELD_BASE(3, 3, 8, 0x0090, 0x10, 5, 1),
+	PIN_FIELD_BASE(4, 4, 8, 0x0090, 0x10, 6, 1),
+	PIN_FIELD_BASE(5, 5, 8, 0x0090, 0x10, 7, 1),
+	PIN_FIELD_BASE(6, 6, 7, 0x00a0, 0x10, 6, 1),
+	PIN_FIELD_BASE(7, 7, 7, 0x00a0, 0x10, 7, 1),
+	PIN_FIELD_BASE(8, 8, 7, 0x00a0, 0x10, 8, 1),
+	PIN_FIELD_BASE(9, 9, 7, 0x00a0, 0x10, 9, 1),
+	PIN_FIELD_BASE(10, 10, 7, 0x00a0, 0x10, 10, 1),
+	PIN_FIELD_BASE(11, 11, 7, 0x00a0, 0x10, 11, 1),
+	PIN_FIELD_BASE(12, 12, 2, 0x00b0, 0x10, 5, 1),
+	PIN_FIELD_BASE(13, 13, 2, 0x00b0, 0x10, 6, 1),
+	PIN_FIELD_BASE(14, 14, 3, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(15, 15, 3, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(16, 16, 2, 0x00b0, 0x10, 7, 1),
+	PIN_FIELD_BASE(17, 17, 2, 0x00b0, 0x10, 8, 1),
+	PIN_FIELD_BASE(18, 18, 7, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(19, 19, 7, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(20, 20, 7, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(21, 21, 7, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(22, 22, 9, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(23, 23, 9, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(24, 24, 9, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(25, 25, 4, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(26, 26, 4, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(27, 27, 2, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(28, 28, 2, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(29, 29, 4, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(30, 30, 2, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(31, 31, 3, 0x00a0, 0x10, 13, 1),
+	PIN_FIELD_BASE(32, 32, 1, 0x0090, 0x10, 30, 1),
+	PIN_FIELD_BASE(33, 33, 3, 0x00a0, 0x10, 15, 1),
+	PIN_FIELD_BASE(34, 34, 3, 0x00a0, 0x10, 14, 1),
+	PIN_FIELD_BASE(35, 35, 3, 0x00a0, 0x10, 17, 1),
+	PIN_FIELD_BASE(36, 36, 3, 0x00a0, 0x10, 16, 1),
+	PIN_FIELD_BASE(37, 37, 3, 0x00a0, 0x10, 19, 1),
+	PIN_FIELD_BASE(38, 38, 3, 0x00a0, 0x10, 18, 1),
+	PIN_FIELD_BASE(39, 39, 3, 0x00a0, 0x10, 5, 1),
+	PIN_FIELD_BASE(40, 40, 3, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(41, 41, 3, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(42, 42, 3, 0x00a0, 0x10, 4, 1),
+	PIN_FIELD_BASE(43, 43, 3, 0x00a0, 0x10, 6, 1),
+	PIN_FIELD_BASE(48, 48, 4, 0x0090, 0x10, 5, 1),
+	PIN_FIELD_BASE(49, 49, 4, 0x0090, 0x10, 4, 1),
+	PIN_FIELD_BASE(50, 50, 4, 0x0090, 0x10, 3, 1),
+	PIN_FIELD_BASE(51, 51, 8, 0x0090, 0x10, 8, 1),
+	PIN_FIELD_BASE(52, 52, 8, 0x0090, 0x10, 10, 1),
+	PIN_FIELD_BASE(53, 53, 8, 0x0090, 0x10, 9, 1),
+	PIN_FIELD_BASE(54, 54, 8, 0x0090, 0x10, 11, 1),
+	PIN_FIELD_BASE(55, 55, 4, 0x0090, 0x10, 6, 1),
+	PIN_FIELD_BASE(56, 56, 4, 0x0090, 0x10, 7, 1),
+	PIN_FIELD_BASE(57, 57, 2, 0x00b0, 0x10, 13, 1),
+	PIN_FIELD_BASE(58, 58, 2, 0x00b0, 0x10, 17, 1),
+	PIN_FIELD_BASE(59, 59, 2, 0x00b0, 0x10, 14, 1),
+	PIN_FIELD_BASE(60, 60, 2, 0x00b0, 0x10, 18, 1),
+	PIN_FIELD_BASE(61, 61, 2, 0x00b0, 0x10, 15, 1),
+	PIN_FIELD_BASE(62, 62, 2, 0x00b0, 0x10, 19, 1),
+	PIN_FIELD_BASE(63, 63, 2, 0x00b0, 0x10, 16, 1),
+	PIN_FIELD_BASE(64, 64, 2, 0x00b0, 0x10, 20, 1),
+	PIN_FIELD_BASE(65, 65, 9, 0x0090, 0x10, 4, 1),
+	PIN_FIELD_BASE(66, 66, 9, 0x0090, 0x10, 6, 1),
+	PIN_FIELD_BASE(67, 67, 9, 0x0090, 0x10, 5, 1),
+	PIN_FIELD_BASE(68, 68, 9, 0x0090, 0x10, 7, 1),
+	PIN_FIELD_BASE(69, 69, 2, 0x00b0, 0x10, 22, 1),
+	PIN_FIELD_BASE(70, 70, 2, 0x00b0, 0x10, 21, 1),
+	PIN_FIELD_BASE(71, 71, 2, 0x00b0, 0x10, 24, 1),
+	PIN_FIELD_BASE(72, 72, 2, 0x00b0, 0x10, 23, 1),
+	PIN_FIELD_BASE(73, 73, 2, 0x00b0, 0x10, 26, 1),
+	PIN_FIELD_BASE(74, 74, 2, 0x00b0, 0x10, 25, 1),
+	PIN_FIELD_BASE(75, 75, 3, 0x00a0, 0x10, 7, 1),
+	PIN_FIELD_BASE(76, 76, 2, 0x00b0, 0x10, 27, 1),
+	PIN_FIELD_BASE(77, 77, 8, 0x0090, 0x10, 13, 1),
+	PIN_FIELD_BASE(78, 78, 8, 0x0090, 0x10, 12, 1),
+	PIN_FIELD_BASE(79, 79, 8, 0x0090, 0x10, 15, 1),
+	PIN_FIELD_BASE(80, 80, 8, 0x0090, 0x10, 14, 1),
+	PIN_FIELD_BASE(81, 81, 2, 0x00b0, 0x10, 29, 1),
+	PIN_FIELD_BASE(82, 82, 2, 0x00b0, 0x10, 28, 1),
+	PIN_FIELD_BASE(83, 83, 2, 0x00b0, 0x10, 30, 1),
+	PIN_FIELD_BASE(84, 84, 7, 0x00a0, 0x10, 22, 1),
+	PIN_FIELD_BASE(85, 85, 7, 0x00a0, 0x10, 23, 1),
+	PIN_FIELD_BASE(86, 86, 7, 0x00a0, 0x10, 24, 1),
+	PIN_FIELD_BASE(87, 87, 7, 0x00a0, 0x10, 25, 1),
+	PIN_FIELD_BASE(88, 88, 5, 0x00b0, 0x10, 11, 1),
+	PIN_FIELD_BASE(89, 89, 5, 0x00b0, 0x10, 10, 1),
+	PIN_FIELD_BASE(90, 90, 5, 0x00b0, 0x10, 13, 1),
+	PIN_FIELD_BASE(91, 91, 5, 0x00b0, 0x10, 12, 1),
+	PIN_FIELD_BASE(92, 92, 5, 0x00b0, 0x10, 7, 1),
+	PIN_FIELD_BASE(93, 93, 5, 0x00b0, 0x10, 8, 1),
+	PIN_FIELD_BASE(94, 94, 5, 0x00b0, 0x10, 14, 1),
+	PIN_FIELD_BASE(95, 95, 5, 0x00b0, 0x10, 6, 1),
+	PIN_FIELD_BASE(96, 96, 5, 0x00b0, 0x10, 9, 1),
+	PIN_FIELD_BASE(97, 97, 5, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(98, 98, 5, 0x00b0, 0x10, 5, 1),
+	PIN_FIELD_BASE(99, 99, 5, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(100, 100, 5, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(101, 101, 5, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(102, 102, 5, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(103, 103, 7, 0x00a0, 0x10, 15, 1),
+	PIN_FIELD_BASE(104, 104, 7, 0x00a0, 0x10, 12, 1),
+	PIN_FIELD_BASE(105, 105, 7, 0x00a0, 0x10, 14, 1),
+	PIN_FIELD_BASE(106, 106, 7, 0x00a0, 0x10, 13, 1),
+	PIN_FIELD_BASE(107, 107, 7, 0x00a0, 0x10, 19, 1),
+	PIN_FIELD_BASE(108, 108, 7, 0x00a0, 0x10, 16, 1),
+	PIN_FIELD_BASE(109, 109, 7, 0x00a0, 0x10, 18, 1),
+	PIN_FIELD_BASE(110, 110, 7, 0x00a0, 0x10, 17, 1),
+	PIN_FIELD_BASE(111, 111, 7, 0x00a0, 0x10, 4, 1),
+	PIN_FIELD_BASE(112, 112, 8, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(113, 113, 8, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(114, 114, 8, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(115, 115, 2, 0x00b0, 0x10, 9, 1),
+	PIN_FIELD_BASE(116, 116, 2, 0x00b0, 0x10, 12, 1),
+	PIN_FIELD_BASE(117, 117, 2, 0x00b0, 0x10, 10, 1),
+	PIN_FIELD_BASE(118, 118, 2, 0x00b0, 0x10, 11, 1),
+	PIN_FIELD_BASE(119, 119, 1, 0x0090, 0x10, 26, 1),
+	PIN_FIELD_BASE(120, 120, 1, 0x0090, 0x10, 25, 1),
+	PIN_FIELD_BASE(121, 121, 1, 0x0090, 0x10, 24, 1),
+	PIN_FIELD_BASE(122, 122, 1, 0x0090, 0x10, 23, 1),
+	PIN_FIELD_BASE(123, 123, 1, 0x0090, 0x10, 19, 1),
+	PIN_FIELD_BASE(124, 124, 1, 0x0090, 0x10, 18, 1),
+	PIN_FIELD_BASE(125, 125, 1, 0x0090, 0x10, 17, 1),
+	PIN_FIELD_BASE(126, 126, 1, 0x0090, 0x10, 16, 1),
+	PIN_FIELD_BASE(127, 127, 1, 0x0090, 0x10, 22, 1),
+	PIN_FIELD_BASE(128, 128, 1, 0x0090, 0x10, 15, 1),
+	PIN_FIELD_BASE(129, 129, 1, 0x0090, 0x10, 20, 1),
+	PIN_FIELD_BASE(130, 130, 1, 0x0090, 0x10, 27, 1),
+	PIN_FIELD_BASE(131, 131, 1, 0x0090, 0x10, 13, 1),
+	PIN_FIELD_BASE(132, 132, 1, 0x0090, 0x10, 14, 1),
+	PIN_FIELD_BASE(133, 133, 1, 0x0090, 0x10, 28, 1),
+	PIN_FIELD_BASE(134, 134, 1, 0x0090, 0x10, 21, 1),
+	PIN_FIELD_BASE(135, 135, 1, 0x0090, 0x10, 11, 1),
+	PIN_FIELD_BASE(136, 136, 1, 0x0090, 0x10, 12, 1),
+	PIN_FIELD_BASE(137, 137, 2, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(138, 138, 2, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(139, 139, 1, 0x0090, 0x10, 3, 1),
+	PIN_FIELD_BASE(140, 140, 1, 0x0090, 0x10, 4, 1),
+	PIN_FIELD_BASE(141, 141, 1, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(142, 142, 1, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(143, 143, 1, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(144, 144, 1, 0x0090, 0x10, 5, 1),
+	PIN_FIELD_BASE(145, 145, 1, 0x0090, 0x10, 6, 1),
+	PIN_FIELD_BASE(146, 146, 1, 0x0090, 0x10, 7, 1),
+	PIN_FIELD_BASE(147, 147, 1, 0x0090, 0x10, 8, 1),
+	PIN_FIELD_BASE(148, 148, 1, 0x0090, 0x10, 9, 1),
+	PIN_FIELD_BASE(149, 149, 1, 0x0090, 0x10, 10, 1),
+	PIN_FIELD_BASE(150, 150, 3, 0x00a0, 0x10, 8, 1),
+	PIN_FIELD_BASE(151, 151, 1, 0x0090, 0x10, 29, 1),
+	PIN_FIELD_BASE(152, 152, 3, 0x00a0, 0x10, 9, 1),
+	PIN_FIELD_BASE(153, 153, 3, 0x00a0, 0x10, 10, 1),
+	PIN_FIELD_BASE(154, 154, 3, 0x00a0, 0x10, 11, 1),
+	PIN_FIELD_BASE(155, 155, 3, 0x00a0, 0x10, 12, 1),
+	PIN_FIELD_BASE(180, 180, 5, 0x00b0, 0x10, 15, 1),
+	PIN_FIELD_BASE(181, 181, 5, 0x00b0, 0x10, 16, 1),
+	PIN_FIELD_BASE(182, 182, 9, 0x0090, 0x10, 3, 1),
+};
+
+static const struct mtk_pin_field_calc mt8189_pin_pd_range[] = {
+	PIN_FIELD_BASE(0, 0, 7, 0x0080, 0x10, 5, 1),
+	PIN_FIELD_BASE(1, 1, 8, 0x0080, 0x10, 3, 1),
+	PIN_FIELD_BASE(2, 2, 8, 0x0080, 0x10, 4, 1),
+	PIN_FIELD_BASE(3, 3, 8, 0x0080, 0x10, 5, 1),
+	PIN_FIELD_BASE(4, 4, 8, 0x0080, 0x10, 6, 1),
+	PIN_FIELD_BASE(5, 5, 8, 0x0080, 0x10, 7, 1),
+	PIN_FIELD_BASE(6, 6, 7, 0x0080, 0x10, 6, 1),
+	PIN_FIELD_BASE(7, 7, 7, 0x0080, 0x10, 7, 1),
+	PIN_FIELD_BASE(8, 8, 7, 0x0080, 0x10, 8, 1),
+	PIN_FIELD_BASE(9, 9, 7, 0x0080, 0x10, 9, 1),
+	PIN_FIELD_BASE(10, 10, 7, 0x0080, 0x10, 10, 1),
+	PIN_FIELD_BASE(11, 11, 7, 0x0080, 0x10, 11, 1),
+	PIN_FIELD_BASE(12, 12, 2, 0x00a0, 0x10, 5, 1),
+	PIN_FIELD_BASE(13, 13, 2, 0x00a0, 0x10, 6, 1),
+	PIN_FIELD_BASE(14, 14, 3, 0x0080, 0x10, 0, 1),
+	PIN_FIELD_BASE(15, 15, 3, 0x0080, 0x10, 1, 1),
+	PIN_FIELD_BASE(16, 16, 2, 0x00a0, 0x10, 7, 1),
+	PIN_FIELD_BASE(17, 17, 2, 0x00a0, 0x10, 8, 1),
+	PIN_FIELD_BASE(18, 18, 7, 0x0080, 0x10, 0, 1),
+	PIN_FIELD_BASE(19, 19, 7, 0x0080, 0x10, 2, 1),
+	PIN_FIELD_BASE(20, 20, 7, 0x0080, 0x10, 1, 1),
+	PIN_FIELD_BASE(21, 21, 7, 0x0080, 0x10, 3, 1),
+	PIN_FIELD_BASE(22, 22, 9, 0x0070, 0x10, 0, 1),
+	PIN_FIELD_BASE(23, 23, 9, 0x0070, 0x10, 1, 1),
+	PIN_FIELD_BASE(24, 24, 9, 0x0070, 0x10, 2, 1),
+	PIN_FIELD_BASE(25, 25, 4, 0x0080, 0x10, 2, 1),
+	PIN_FIELD_BASE(26, 26, 4, 0x0080, 0x10, 1, 1),
+	PIN_FIELD_BASE(27, 27, 2, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(28, 28, 2, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(29, 29, 4, 0x0080, 0x10, 0, 1),
+	PIN_FIELD_BASE(30, 30, 2, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(31, 31, 3, 0x0080, 0x10, 13, 1),
+	PIN_FIELD_BASE(32, 32, 1, 0x0080, 0x10, 30, 1),
+	PIN_FIELD_BASE(33, 33, 3, 0x0080, 0x10, 15, 1),
+	PIN_FIELD_BASE(34, 34, 3, 0x0080, 0x10, 14, 1),
+	PIN_FIELD_BASE(35, 35, 3, 0x0080, 0x10, 17, 1),
+	PIN_FIELD_BASE(36, 36, 3, 0x0080, 0x10, 16, 1),
+	PIN_FIELD_BASE(37, 37, 3, 0x0080, 0x10, 19, 1),
+	PIN_FIELD_BASE(38, 38, 3, 0x0080, 0x10, 18, 1),
+	PIN_FIELD_BASE(39, 39, 3, 0x0080, 0x10, 5, 1),
+	PIN_FIELD_BASE(40, 40, 3, 0x0080, 0x10, 2, 1),
+	PIN_FIELD_BASE(41, 41, 3, 0x0080, 0x10, 3, 1),
+	PIN_FIELD_BASE(42, 42, 3, 0x0080, 0x10, 4, 1),
+	PIN_FIELD_BASE(43, 43, 3, 0x0080, 0x10, 6, 1),
+	PIN_FIELD_BASE(48, 48, 4, 0x0080, 0x10, 5, 1),
+	PIN_FIELD_BASE(49, 49, 4, 0x0080, 0x10, 4, 1),
+	PIN_FIELD_BASE(50, 50, 4, 0x0080, 0x10, 3, 1),
+	PIN_FIELD_BASE(51, 51, 8, 0x0080, 0x10, 8, 1),
+	PIN_FIELD_BASE(52, 52, 8, 0x0080, 0x10, 10, 1),
+	PIN_FIELD_BASE(53, 53, 8, 0x0080, 0x10, 9, 1),
+	PIN_FIELD_BASE(54, 54, 8, 0x0080, 0x10, 11, 1),
+	PIN_FIELD_BASE(55, 55, 4, 0x0080, 0x10, 6, 1),
+	PIN_FIELD_BASE(56, 56, 4, 0x0080, 0x10, 7, 1),
+	PIN_FIELD_BASE(57, 57, 2, 0x00a0, 0x10, 13, 1),
+	PIN_FIELD_BASE(58, 58, 2, 0x00a0, 0x10, 17, 1),
+	PIN_FIELD_BASE(59, 59, 2, 0x00a0, 0x10, 14, 1),
+	PIN_FIELD_BASE(60, 60, 2, 0x00a0, 0x10, 18, 1),
+	PIN_FIELD_BASE(61, 61, 2, 0x00a0, 0x10, 15, 1),
+	PIN_FIELD_BASE(62, 62, 2, 0x00a0, 0x10, 19, 1),
+	PIN_FIELD_BASE(63, 63, 2, 0x00a0, 0x10, 16, 1),
+	PIN_FIELD_BASE(64, 64, 2, 0x00a0, 0x10, 20, 1),
+	PIN_FIELD_BASE(65, 65, 9, 0x0070, 0x10, 4, 1),
+	PIN_FIELD_BASE(66, 66, 9, 0x0070, 0x10, 6, 1),
+	PIN_FIELD_BASE(67, 67, 9, 0x0070, 0x10, 5, 1),
+	PIN_FIELD_BASE(68, 68, 9, 0x0070, 0x10, 7, 1),
+	PIN_FIELD_BASE(69, 69, 2, 0x00a0, 0x10, 22, 1),
+	PIN_FIELD_BASE(70, 70, 2, 0x00a0, 0x10, 21, 1),
+	PIN_FIELD_BASE(71, 71, 2, 0x00a0, 0x10, 24, 1),
+	PIN_FIELD_BASE(72, 72, 2, 0x00a0, 0x10, 23, 1),
+	PIN_FIELD_BASE(73, 73, 2, 0x00a0, 0x10, 26, 1),
+	PIN_FIELD_BASE(74, 74, 2, 0x00a0, 0x10, 25, 1),
+	PIN_FIELD_BASE(75, 75, 3, 0x0080, 0x10, 7, 1),
+	PIN_FIELD_BASE(76, 76, 2, 0x00a0, 0x10, 27, 1),
+	PIN_FIELD_BASE(77, 77, 8, 0x0080, 0x10, 13, 1),
+	PIN_FIELD_BASE(78, 78, 8, 0x0080, 0x10, 12, 1),
+	PIN_FIELD_BASE(79, 79, 8, 0x0080, 0x10, 15, 1),
+	PIN_FIELD_BASE(80, 80, 8, 0x0080, 0x10, 14, 1),
+	PIN_FIELD_BASE(81, 81, 2, 0x00a0, 0x10, 29, 1),
+	PIN_FIELD_BASE(82, 82, 2, 0x00a0, 0x10, 28, 1),
+	PIN_FIELD_BASE(83, 83, 2, 0x00a0, 0x10, 30, 1),
+	PIN_FIELD_BASE(84, 84, 7, 0x0080, 0x10, 22, 1),
+	PIN_FIELD_BASE(85, 85, 7, 0x0080, 0x10, 23, 1),
+	PIN_FIELD_BASE(86, 86, 7, 0x0080, 0x10, 24, 1),
+	PIN_FIELD_BASE(87, 87, 7, 0x0080, 0x10, 25, 1),
+	PIN_FIELD_BASE(88, 88, 5, 0x0090, 0x10, 11, 1),
+	PIN_FIELD_BASE(89, 89, 5, 0x0090, 0x10, 10, 1),
+	PIN_FIELD_BASE(90, 90, 5, 0x0090, 0x10, 13, 1),
+	PIN_FIELD_BASE(91, 91, 5, 0x0090, 0x10, 12, 1),
+	PIN_FIELD_BASE(92, 92, 5, 0x0090, 0x10, 7, 1),
+	PIN_FIELD_BASE(93, 93, 5, 0x0090, 0x10, 8, 1),
+	PIN_FIELD_BASE(94, 94, 5, 0x0090, 0x10, 14, 1),
+	PIN_FIELD_BASE(95, 95, 5, 0x0090, 0x10, 6, 1),
+	PIN_FIELD_BASE(96, 96, 5, 0x0090, 0x10, 9, 1),
+	PIN_FIELD_BASE(97, 97, 5, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(98, 98, 5, 0x0090, 0x10, 5, 1),
+	PIN_FIELD_BASE(99, 99, 5, 0x0090, 0x10, 3, 1),
+	PIN_FIELD_BASE(100, 100, 5, 0x0090, 0x10, 4, 1),
+	PIN_FIELD_BASE(101, 101, 5, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(102, 102, 5, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(103, 103, 7, 0x0080, 0x10, 15, 1),
+	PIN_FIELD_BASE(104, 104, 7, 0x0080, 0x10, 12, 1),
+	PIN_FIELD_BASE(105, 105, 7, 0x0080, 0x10, 14, 1),
+	PIN_FIELD_BASE(106, 106, 7, 0x0080, 0x10, 13, 1),
+	PIN_FIELD_BASE(107, 107, 7, 0x0080, 0x10, 19, 1),
+	PIN_FIELD_BASE(108, 108, 7, 0x0080, 0x10, 16, 1),
+	PIN_FIELD_BASE(109, 109, 7, 0x0080, 0x10, 18, 1),
+	PIN_FIELD_BASE(110, 110, 7, 0x0080, 0x10, 17, 1),
+	PIN_FIELD_BASE(111, 111, 7, 0x0080, 0x10, 4, 1),
+	PIN_FIELD_BASE(112, 112, 8, 0x0080, 0x10, 0, 1),
+	PIN_FIELD_BASE(113, 113, 8, 0x0080, 0x10, 1, 1),
+	PIN_FIELD_BASE(114, 114, 8, 0x0080, 0x10, 2, 1),
+	PIN_FIELD_BASE(115, 115, 2, 0x00a0, 0x10, 9, 1),
+	PIN_FIELD_BASE(116, 116, 2, 0x00a0, 0x10, 12, 1),
+	PIN_FIELD_BASE(117, 117, 2, 0x00a0, 0x10, 10, 1),
+	PIN_FIELD_BASE(118, 118, 2, 0x00a0, 0x10, 11, 1),
+	PIN_FIELD_BASE(119, 119, 1, 0x0080, 0x10, 26, 1),
+	PIN_FIELD_BASE(120, 120, 1, 0x0080, 0x10, 25, 1),
+	PIN_FIELD_BASE(121, 121, 1, 0x0080, 0x10, 24, 1),
+	PIN_FIELD_BASE(122, 122, 1, 0x0080, 0x10, 23, 1),
+	PIN_FIELD_BASE(123, 123, 1, 0x0080, 0x10, 19, 1),
+	PIN_FIELD_BASE(124, 124, 1, 0x0080, 0x10, 18, 1),
+	PIN_FIELD_BASE(125, 125, 1, 0x0080, 0x10, 17, 1),
+	PIN_FIELD_BASE(126, 126, 1, 0x0080, 0x10, 16, 1),
+	PIN_FIELD_BASE(127, 127, 1, 0x0080, 0x10, 22, 1),
+	PIN_FIELD_BASE(128, 128, 1, 0x0080, 0x10, 15, 1),
+	PIN_FIELD_BASE(129, 129, 1, 0x0080, 0x10, 20, 1),
+	PIN_FIELD_BASE(130, 130, 1, 0x0080, 0x10, 27, 1),
+	PIN_FIELD_BASE(131, 131, 1, 0x0080, 0x10, 13, 1),
+	PIN_FIELD_BASE(132, 132, 1, 0x0080, 0x10, 14, 1),
+	PIN_FIELD_BASE(133, 133, 1, 0x0080, 0x10, 28, 1),
+	PIN_FIELD_BASE(134, 134, 1, 0x0080, 0x10, 21, 1),
+	PIN_FIELD_BASE(135, 135, 1, 0x0080, 0x10, 11, 1),
+	PIN_FIELD_BASE(136, 136, 1, 0x0080, 0x10, 12, 1),
+	PIN_FIELD_BASE(137, 137, 2, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(138, 138, 2, 0x00a0, 0x10, 4, 1),
+	PIN_FIELD_BASE(139, 139, 1, 0x0080, 0x10, 3, 1),
+	PIN_FIELD_BASE(140, 140, 1, 0x0080, 0x10, 4, 1),
+	PIN_FIELD_BASE(141, 141, 1, 0x0080, 0x10, 0, 1),
+	PIN_FIELD_BASE(142, 142, 1, 0x0080, 0x10, 1, 1),
+	PIN_FIELD_BASE(143, 143, 1, 0x0080, 0x10, 2, 1),
+	PIN_FIELD_BASE(144, 144, 1, 0x0080, 0x10, 5, 1),
+	PIN_FIELD_BASE(145, 145, 1, 0x0080, 0x10, 6, 1),
+	PIN_FIELD_BASE(146, 146, 1, 0x0080, 0x10, 7, 1),
+	PIN_FIELD_BASE(147, 147, 1, 0x0080, 0x10, 8, 1),
+	PIN_FIELD_BASE(148, 148, 1, 0x0080, 0x10, 9, 1),
+	PIN_FIELD_BASE(149, 149, 1, 0x0080, 0x10, 10, 1),
+	PIN_FIELD_BASE(150, 150, 3, 0x0080, 0x10, 8, 1),
+	PIN_FIELD_BASE(151, 151, 1, 0x0080, 0x10, 29, 1),
+	PIN_FIELD_BASE(152, 152, 3, 0x0080, 0x10, 9, 1),
+	PIN_FIELD_BASE(153, 153, 3, 0x0080, 0x10, 10, 1),
+	PIN_FIELD_BASE(154, 154, 3, 0x0080, 0x10, 11, 1),
+	PIN_FIELD_BASE(155, 155, 3, 0x0080, 0x10, 12, 1),
+	PIN_FIELD_BASE(180, 180, 5, 0x0090, 0x10, 15, 1),
+	PIN_FIELD_BASE(181, 181, 5, 0x0090, 0x10, 16, 1),
+	PIN_FIELD_BASE(182, 182, 9, 0x0070, 0x10, 3, 1),
+};
+
+static const struct mtk_pin_field_calc mt8189_pin_drv_range[] = {
+	PIN_FIELD_BASE(0, 0, 7, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(1, 1, 8, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(2, 2, 8, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(3, 3, 8, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(4, 4, 8, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(5, 5, 8, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(6, 6, 7, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(7, 7, 7, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(8, 8, 7, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(9, 9, 7, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(10, 10, 7, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(11, 11, 7, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(12, 12, 2, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(13, 13, 2, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(14, 14, 3, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(15, 15, 3, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(16, 16, 2, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(17, 17, 2, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(18, 18, 7, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(19, 19, 7, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(20, 20, 7, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(21, 21, 7, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(22, 22, 9, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(23, 23, 9, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(24, 24, 9, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(25, 25, 4, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(26, 26, 4, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(27, 27, 2, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(28, 28, 2, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(29, 29, 4, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(30, 30, 2, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(31, 31, 3, 0x0010, 0x10, 27, 3),
+	PIN_FIELD_BASE(32, 32, 1, 0x0030, 0x10, 0, 3),
+	PIN_FIELD_BASE(33, 33, 3, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(34, 34, 3, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(35, 35, 3, 0x0020, 0x10, 9, 3),
+	PIN_FIELD_BASE(36, 36, 3, 0x0020, 0x10, 6, 3),
+	PIN_FIELD_BASE(37, 37, 3, 0x0020, 0x10, 15, 3),
+	PIN_FIELD_BASE(38, 38, 3, 0x0020, 0x10, 12, 3),
+	PIN_FIELD_BASE(39, 39, 3, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(40, 40, 3, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(41, 41, 3, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(42, 42, 3, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(43, 43, 3, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(44, 44, 7, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(45, 45, 7, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(46, 46, 7, 0x0020, 0x10, 6, 3),
+	PIN_FIELD_BASE(47, 47, 7, 0x0020, 0x10, 9, 3),
+	PIN_FIELD_BASE(48, 48, 4, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(49, 49, 4, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(50, 50, 4, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(51, 51, 8, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(52, 52, 8, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(53, 53, 8, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(54, 54, 8, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(55, 55, 4, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(56, 56, 4, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(57, 57, 2, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(58, 58, 2, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(59, 59, 2, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(60, 60, 2, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(61, 61, 2, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(62, 62, 2, 0x0010, 0x10, 27, 3),
+	PIN_FIELD_BASE(63, 63, 2, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(64, 64, 2, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(65, 65, 9, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(66, 66, 9, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(67, 67, 9, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(68, 68, 9, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(69, 69, 2, 0x0020, 0x10, 6, 3),
+	PIN_FIELD_BASE(70, 70, 2, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(71, 71, 2, 0x0020, 0x10, 12, 3),
+	PIN_FIELD_BASE(72, 72, 2, 0x0020, 0x10, 9, 3),
+	PIN_FIELD_BASE(73, 73, 2, 0x0020, 0x10, 18, 3),
+	PIN_FIELD_BASE(74, 74, 2, 0x0020, 0x10, 15, 3),
+	PIN_FIELD_BASE(75, 75, 3, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(76, 76, 2, 0x0020, 0x10, 21, 3),
+	PIN_FIELD_BASE(77, 77, 8, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(78, 78, 8, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(79, 79, 8, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(80, 80, 8, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(81, 81, 2, 0x0020, 0x10, 27, 3),
+	PIN_FIELD_BASE(82, 82, 2, 0x0020, 0x10, 24, 3),
+	PIN_FIELD_BASE(83, 83, 2, 0x0030, 0x10, 0, 3),
+	PIN_FIELD_BASE(84, 84, 7, 0x0020, 0x10, 12, 3),
+	PIN_FIELD_BASE(85, 85, 7, 0x0020, 0x10, 15, 3),
+	PIN_FIELD_BASE(86, 86, 7, 0x0020, 0x10, 18, 3),
+	PIN_FIELD_BASE(87, 87, 7, 0x0020, 0x10, 21, 3),
+	PIN_FIELD_BASE(88, 88, 5, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(89, 89, 5, 0x0010, 0x10, 27, 3),
+	PIN_FIELD_BASE(90, 90, 5, 0x0020, 0x10, 6, 3),
+	PIN_FIELD_BASE(91, 91, 5, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(92, 92, 5, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(93, 93, 5, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(94, 94, 5, 0x0020, 0x10, 9, 3),
+	PIN_FIELD_BASE(95, 95, 5, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(96, 96, 5, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(97, 97, 5, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(98, 98, 5, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(99, 99, 5, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(100, 100, 5, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(101, 101, 5, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(102, 102, 5, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(103, 103, 7, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(104, 104, 7, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(105, 105, 7, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(106, 106, 7, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(107, 107, 7, 0x0010, 0x10, 27, 3),
+	PIN_FIELD_BASE(108, 108, 7, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(109, 109, 7, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(110, 110, 7, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(111, 111, 7, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(112, 112, 8, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(113, 113, 8, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(114, 114, 8, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(115, 115, 2, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(116, 116, 2, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(117, 117, 2, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(118, 118, 2, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(119, 119, 1, 0x0020, 0x10, 18, 3),
+	PIN_FIELD_BASE(120, 120, 1, 0x0020, 0x10, 15, 3),
+	PIN_FIELD_BASE(121, 121, 1, 0x0020, 0x10, 12, 3),
+	PIN_FIELD_BASE(122, 122, 1, 0x0020, 0x10, 9, 3),
+	PIN_FIELD_BASE(123, 123, 1, 0x0010, 0x10, 27, 3),
+	PIN_FIELD_BASE(124, 124, 1, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(125, 125, 1, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(126, 126, 1, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(127, 127, 1, 0x0020, 0x10, 6, 3),
+	PIN_FIELD_BASE(128, 128, 1, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(129, 129, 1, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(130, 130, 1, 0x0020, 0x10, 21, 3),
+	PIN_FIELD_BASE(131, 131, 1, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(132, 132, 1, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(133, 133, 1, 0x0020, 0x10, 24, 3),
+	PIN_FIELD_BASE(134, 134, 1, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(135, 135, 1, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(136, 136, 1, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(137, 137, 2, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(138, 138, 2, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(139, 139, 1, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(140, 140, 1, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(141, 141, 1, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(142, 142, 1, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(143, 143, 1, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(144, 144, 1, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(145, 145, 1, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(146, 146, 1, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(147, 147, 1, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(148, 148, 1, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(149, 149, 1, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(150, 150, 3, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(151, 151, 1, 0x0020, 0x10, 27, 3),
+	PIN_FIELD_BASE(152, 152, 3, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(153, 153, 3, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(154, 154, 3, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(155, 155, 3, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(156, 156, 5, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(157, 157, 5, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(158, 158, 5, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(159, 159, 6, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(160, 160, 5, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(161, 161, 5, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(162, 162, 5, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(163, 163, 6, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(164, 164, 5, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(165, 165, 5, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(166, 166, 6, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(167, 167, 5, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(168, 168, 3, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(169, 169, 3, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(170, 170, 3, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(171, 171, 3, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(172, 172, 3, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(173, 173, 3, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(174, 174, 9, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(175, 175, 9, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(176, 176, 9, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(177, 177, 9, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(178, 178, 9, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(179, 179, 9, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(180, 180, 5, 0x0020, 0x10, 12, 3),
+	PIN_FIELD_BASE(181, 181, 5, 0x0020, 0x10, 15, 3),
+	PIN_FIELD_BASE(182, 182, 9, 0x0000, 0x10, 9, 3),
+};
+
+static const struct mtk_pin_field_calc mt8189_pin_drv_adv_range[] = {
+	PIN_FIELD_BASE(51, 51, 8, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(52, 52, 8, 0x0020, 0x10, 6, 3),
+	PIN_FIELD_BASE(53, 53, 8, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(54, 54, 8, 0x0020, 0x10, 9, 3),
+	PIN_FIELD_BASE(55, 55, 4, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(56, 56, 4, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(57, 57, 2, 0x0040, 0x10, 0, 3),
+	PIN_FIELD_BASE(58, 58, 2, 0x0040, 0x10, 12, 3),
+	PIN_FIELD_BASE(59, 59, 2, 0x0040, 0x10, 3, 3),
+	PIN_FIELD_BASE(60, 60, 2, 0x0040, 0x10, 15, 3),
+	PIN_FIELD_BASE(61, 61, 2, 0x0040, 0x10, 6, 3),
+	PIN_FIELD_BASE(62, 62, 2, 0x0040, 0x10, 18, 3),
+	PIN_FIELD_BASE(63, 63, 2, 0x0040, 0x10, 9, 3),
+	PIN_FIELD_BASE(64, 64, 2, 0x0040, 0x10, 21, 3),
+	PIN_FIELD_BASE(65, 65, 9, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(66, 66, 9, 0x0020, 0x10, 6, 3),
+	PIN_FIELD_BASE(67, 67, 9, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(68, 68, 9, 0x0020, 0x10, 9, 3),
+	PIN_FIELD_BASE(180, 180, 5, 0x0030, 0x10, 0, 3),
+	PIN_FIELD_BASE(181, 181, 5, 0x0030, 0x10, 3, 3),
+};
+
+static const struct mtk_pin_field_calc mt8189_pin_rsel_range[] = {
+	PIN_FIELD_BASE(51, 51, 8, 0x00b0, 0x10, 0, 3),
+	PIN_FIELD_BASE(52, 52, 8, 0x00b0, 0x10, 6, 3),
+	PIN_FIELD_BASE(53, 53, 8, 0x00b0, 0x10, 3, 3),
+	PIN_FIELD_BASE(54, 54, 8, 0x00b0, 0x10, 9, 3),
+	PIN_FIELD_BASE(55, 55, 4, 0x00b0, 0x10, 0, 3),
+	PIN_FIELD_BASE(56, 56, 4, 0x00b0, 0x10, 3, 3),
+	PIN_FIELD_BASE(57, 57, 2, 0x00d0, 0x10, 0, 3),
+	PIN_FIELD_BASE(58, 58, 2, 0x00d0, 0x10, 12, 3),
+	PIN_FIELD_BASE(59, 59, 2, 0x00d0, 0x10, 3, 3),
+	PIN_FIELD_BASE(60, 60, 2, 0x00d0, 0x10, 15, 3),
+	PIN_FIELD_BASE(61, 61, 2, 0x00d0, 0x10, 6, 3),
+	PIN_FIELD_BASE(62, 62, 2, 0x00d0, 0x10, 18, 3),
+	PIN_FIELD_BASE(63, 63, 2, 0x00d0, 0x10, 9, 3),
+	PIN_FIELD_BASE(64, 64, 2, 0x00d0, 0x10, 21, 3),
+	PIN_FIELD_BASE(65, 65, 9, 0x00e0, 0x10, 0, 3),
+	PIN_FIELD_BASE(66, 66, 9, 0x00e0, 0x10, 6, 3),
+	PIN_FIELD_BASE(67, 67, 9, 0x00e0, 0x10, 3, 3),
+	PIN_FIELD_BASE(68, 68, 9, 0x00e0, 0x10, 9, 3),
+	PIN_FIELD_BASE(180, 180, 5, 0x0110, 0x10, 0, 3),
+	PIN_FIELD_BASE(181, 181, 5, 0x0110, 0x10, 3, 3),
+};
+
+static const struct mtk_pin_rsel mt8189_pin_rsel_val_range[] = {
+	PIN_RSEL(51, 68, 0x0, 75000, 75000),
+	PIN_RSEL(51, 68, 0x1, 10000, 5000),
+	PIN_RSEL(51, 68, 0x2, 5000, 75000),
+	PIN_RSEL(51, 68, 0x3, 4000, 5000),
+	PIN_RSEL(51, 68, 0x4, 3000, 75000),
+	PIN_RSEL(51, 68, 0x5, 2000, 5000),
+	PIN_RSEL(51, 68, 0x6, 1500, 75000),
+	PIN_RSEL(51, 68, 0x7, 1000, 5000),
+	PIN_RSEL(180, 181, 0x0, 75000, 75000),
+	PIN_RSEL(180, 181, 0x1, 10000, 5000),
+	PIN_RSEL(180, 181, 0x2, 5000, 75000),
+	PIN_RSEL(180, 181, 0x3, 4000, 5000),
+	PIN_RSEL(180, 181, 0x4, 3000, 75000),
+	PIN_RSEL(180, 181, 0x5, 2000, 5000),
+	PIN_RSEL(180, 181, 0x6, 1500, 75000),
+	PIN_RSEL(180, 181, 0x7, 1000, 5000),
+};
+
+static const unsigned int mt8189_pull_type[] = {
+	MTK_PULL_PU_PD_TYPE, /*0*/
+	MTK_PULL_PU_PD_TYPE, /*1*/
+	MTK_PULL_PU_PD_TYPE, /*2*/
+	MTK_PULL_PU_PD_TYPE, /*3*/
+	MTK_PULL_PU_PD_TYPE, /*4*/
+	MTK_PULL_PU_PD_TYPE, /*5*/
+	MTK_PULL_PU_PD_TYPE, /*6*/
+	MTK_PULL_PU_PD_TYPE, /*7*/
+	MTK_PULL_PU_PD_TYPE, /*8*/
+	MTK_PULL_PU_PD_TYPE, /*9*/
+	MTK_PULL_PU_PD_TYPE, /*10*/
+	MTK_PULL_PU_PD_TYPE, /*11*/
+	MTK_PULL_PU_PD_TYPE, /*12*/
+	MTK_PULL_PU_PD_TYPE, /*13*/
+	MTK_PULL_PU_PD_TYPE, /*14*/
+	MTK_PULL_PU_PD_TYPE, /*15*/
+	MTK_PULL_PU_PD_TYPE, /*16*/
+	MTK_PULL_PU_PD_TYPE, /*17*/
+	MTK_PULL_PU_PD_TYPE, /*18*/
+	MTK_PULL_PU_PD_TYPE, /*19*/
+	MTK_PULL_PU_PD_TYPE, /*20*/
+	MTK_PULL_PU_PD_TYPE, /*21*/
+	MTK_PULL_PU_PD_TYPE, /*22*/
+	MTK_PULL_PU_PD_TYPE, /*23*/
+	MTK_PULL_PU_PD_TYPE, /*24*/
+	MTK_PULL_PU_PD_TYPE, /*25*/
+	MTK_PULL_PU_PD_TYPE, /*26*/
+	MTK_PULL_PU_PD_TYPE, /*27*/
+	MTK_PULL_PU_PD_TYPE, /*28*/
+	MTK_PULL_PU_PD_TYPE, /*29*/
+	MTK_PULL_PU_PD_TYPE, /*30*/
+	MTK_PULL_PU_PD_TYPE, /*31*/
+	MTK_PULL_PU_PD_TYPE, /*32*/
+	MTK_PULL_PU_PD_TYPE, /*33*/
+	MTK_PULL_PU_PD_TYPE, /*34*/
+	MTK_PULL_PU_PD_TYPE, /*35*/
+	MTK_PULL_PU_PD_TYPE, /*36*/
+	MTK_PULL_PU_PD_TYPE, /*37*/
+	MTK_PULL_PU_PD_TYPE, /*38*/
+	MTK_PULL_PU_PD_TYPE, /*39*/
+	MTK_PULL_PU_PD_TYPE, /*40*/
+	MTK_PULL_PU_PD_TYPE, /*41*/
+	MTK_PULL_PU_PD_TYPE, /*42*/
+	MTK_PULL_PU_PD_TYPE, /*43*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*44*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*45*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*46*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*47*/
+	MTK_PULL_PU_PD_TYPE, /*48*/
+	MTK_PULL_PU_PD_TYPE, /*49*/
+	MTK_PULL_PU_PD_TYPE, /*50*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*51*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*52*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*53*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*54*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*55*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*56*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*57*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*58*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*59*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*60*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*61*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*62*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*63*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*64*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*65*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*66*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*67*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*68*/
+	MTK_PULL_PU_PD_TYPE, /*69*/
+	MTK_PULL_PU_PD_TYPE, /*70*/
+	MTK_PULL_PU_PD_TYPE, /*71*/
+	MTK_PULL_PU_PD_TYPE, /*72*/
+	MTK_PULL_PU_PD_TYPE, /*73*/
+	MTK_PULL_PU_PD_TYPE, /*74*/
+	MTK_PULL_PU_PD_TYPE, /*75*/
+	MTK_PULL_PU_PD_TYPE, /*76*/
+	MTK_PULL_PU_PD_TYPE, /*77*/
+	MTK_PULL_PU_PD_TYPE, /*78*/
+	MTK_PULL_PU_PD_TYPE, /*79*/
+	MTK_PULL_PU_PD_TYPE, /*80*/
+	MTK_PULL_PU_PD_TYPE, /*81*/
+	MTK_PULL_PU_PD_TYPE, /*82*/
+	MTK_PULL_PU_PD_TYPE, /*83*/
+	MTK_PULL_PU_PD_TYPE, /*84*/
+	MTK_PULL_PU_PD_TYPE, /*85*/
+	MTK_PULL_PU_PD_TYPE, /*86*/
+	MTK_PULL_PU_PD_TYPE, /*87*/
+	MTK_PULL_PU_PD_TYPE, /*88*/
+	MTK_PULL_PU_PD_TYPE, /*89*/
+	MTK_PULL_PU_PD_TYPE, /*90*/
+	MTK_PULL_PU_PD_TYPE, /*91*/
+	MTK_PULL_PU_PD_TYPE, /*92*/
+	MTK_PULL_PU_PD_TYPE, /*93*/
+	MTK_PULL_PU_PD_TYPE, /*94*/
+	MTK_PULL_PU_PD_TYPE, /*95*/
+	MTK_PULL_PU_PD_TYPE, /*96*/
+	MTK_PULL_PU_PD_TYPE, /*97*/
+	MTK_PULL_PU_PD_TYPE, /*98*/
+	MTK_PULL_PU_PD_TYPE, /*99*/
+	MTK_PULL_PU_PD_TYPE, /*100*/
+	MTK_PULL_PU_PD_TYPE, /*101*/
+	MTK_PULL_PU_PD_TYPE, /*102*/
+	MTK_PULL_PU_PD_TYPE, /*103*/
+	MTK_PULL_PU_PD_TYPE, /*104*/
+	MTK_PULL_PU_PD_TYPE, /*105*/
+	MTK_PULL_PU_PD_TYPE, /*106*/
+	MTK_PULL_PU_PD_TYPE, /*107*/
+	MTK_PULL_PU_PD_TYPE, /*108*/
+	MTK_PULL_PU_PD_TYPE, /*109*/
+	MTK_PULL_PU_PD_TYPE, /*110*/
+	MTK_PULL_PU_PD_TYPE, /*111*/
+	MTK_PULL_PU_PD_TYPE, /*112*/
+	MTK_PULL_PU_PD_TYPE, /*113*/
+	MTK_PULL_PU_PD_TYPE, /*114*/
+	MTK_PULL_PU_PD_TYPE, /*115*/
+	MTK_PULL_PU_PD_TYPE, /*116*/
+	MTK_PULL_PU_PD_TYPE, /*117*/
+	MTK_PULL_PU_PD_TYPE, /*118*/
+	MTK_PULL_PU_PD_TYPE, /*119*/
+	MTK_PULL_PU_PD_TYPE, /*120*/
+	MTK_PULL_PU_PD_TYPE, /*121*/
+	MTK_PULL_PU_PD_TYPE, /*122*/
+	MTK_PULL_PU_PD_TYPE, /*123*/
+	MTK_PULL_PU_PD_TYPE, /*124*/
+	MTK_PULL_PU_PD_TYPE, /*125*/
+	MTK_PULL_PU_PD_TYPE, /*126*/
+	MTK_PULL_PU_PD_TYPE, /*127*/
+	MTK_PULL_PU_PD_TYPE, /*128*/
+	MTK_PULL_PU_PD_TYPE, /*129*/
+	MTK_PULL_PU_PD_TYPE, /*130*/
+	MTK_PULL_PU_PD_TYPE, /*131*/
+	MTK_PULL_PU_PD_TYPE, /*132*/
+	MTK_PULL_PU_PD_TYPE, /*133*/
+	MTK_PULL_PU_PD_TYPE, /*134*/
+	MTK_PULL_PU_PD_TYPE, /*135*/
+	MTK_PULL_PU_PD_TYPE, /*136*/
+	MTK_PULL_PU_PD_TYPE, /*137*/
+	MTK_PULL_PU_PD_TYPE, /*138*/
+	MTK_PULL_PU_PD_TYPE, /*139*/
+	MTK_PULL_PU_PD_TYPE, /*140*/
+	MTK_PULL_PU_PD_TYPE, /*141*/
+	MTK_PULL_PU_PD_TYPE, /*142*/
+	MTK_PULL_PU_PD_TYPE, /*143*/
+	MTK_PULL_PU_PD_TYPE, /*144*/
+	MTK_PULL_PU_PD_TYPE, /*145*/
+	MTK_PULL_PU_PD_TYPE, /*146*/
+	MTK_PULL_PU_PD_TYPE, /*147*/
+	MTK_PULL_PU_PD_TYPE, /*148*/
+	MTK_PULL_PU_PD_TYPE, /*149*/
+	MTK_PULL_PU_PD_TYPE, /*150*/
+	MTK_PULL_PU_PD_TYPE, /*151*/
+	MTK_PULL_PU_PD_TYPE, /*152*/
+	MTK_PULL_PU_PD_TYPE, /*153*/
+	MTK_PULL_PU_PD_TYPE, /*154*/
+	MTK_PULL_PU_PD_TYPE, /*155*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*156*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*157*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*158*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*159*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*160*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*161*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*162*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*163*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*164*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*165*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*166*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*167*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*168*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*169*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*170*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*171*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*172*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*173*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*174*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*175*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*176*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*177*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*178*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*179*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*180*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*181*/
+	MTK_PULL_PU_PD_TYPE, /*182*/
+};
+
+static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = {
+	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8189_pin_mode_range),
+	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8189_pin_dir_range),
+	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8189_pin_di_range),
+	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8189_pin_do_range),
+	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8189_pin_smt_range),
+	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8189_pin_ies_range),
+	[PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt8189_pin_tdsel_range),
+	[PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt8189_pin_rdsel_range),
+	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8189_pin_pupd_range),
+	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8189_pin_r0_range),
+	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8189_pin_r1_range),
+	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8189_pin_pu_range),
+	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8189_pin_pd_range),
+	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8189_pin_drv_range),
+	[PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8189_pin_drv_adv_range),
+	[PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8189_pin_rsel_range),
+};
+
+static const char * const mt8189_pinctrl_register_base_names[] = {
+	"gpio_base", "iocfg_bm0_base", "iocfg_bm1_base", "iocfg_bm2_base", "iocfg_lm_base",
+	"iocfg_lt0_base", "iocfg_lt1_base", "iocfg_rb0_base", "iocfg_rb1_base",
+	"iocfg_rt_base"
+};
+
+static const struct mtk_eint_hw mt8189_eint_hw = {
+	.port_mask	= 0xf,
+	.ports		= 3,
+	.ap_num		= 210,
+	.db_cnt		= 32,
+	.db_time	= debounce_time_mt6765,
+};
+
+static const struct mtk_pin_soc mt8189_data = {
+	.reg_cal = mt8189_reg_cals,
+	.pins = mtk_pins_mt8189,
+	.npins = ARRAY_SIZE(mtk_pins_mt8189),
+	.ngrps = ARRAY_SIZE(mtk_pins_mt8189),
+	.eint_pin = eint_pins_mt8189,
+	.eint_hw = &mt8189_eint_hw,
+	.nfuncs = 8,
+	.gpio_m = 0,
+	.base_names = mt8189_pinctrl_register_base_names,
+	.nbase_names = ARRAY_SIZE(mt8189_pinctrl_register_base_names),
+	.bias_set_combo = mtk_pinconf_bias_set_combo,
+	.bias_get_combo = mtk_pinconf_bias_get_combo,
+	.pull_type = mt8189_pull_type,
+	.pin_rsel = mt8189_pin_rsel_val_range,
+	.npin_rsel = ARRAY_SIZE(mt8189_pin_rsel_val_range),
+	.drive_set = mtk_pinconf_drive_set_rev1,
+	.drive_get = mtk_pinconf_drive_get_rev1,
+	.adv_drive_set = mtk_pinconf_adv_drive_set_raw,
+	.adv_drive_get = mtk_pinconf_adv_drive_get_raw,
+};
+
+static const struct of_device_id mt8189_pinctrl_of_match[] = {
+	{ .compatible = "mediatek,mt8189-pinctrl", .data = &mt8189_data },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver mt8189_pinctrl_driver = {
+	.driver = {
+		.name = "mt8189-pinctrl",
+		.of_match_table = mt8189_pinctrl_of_match,
+		.pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops),
+	},
+	.probe = mtk_paris_pinctrl_probe,
+};
+
+static int __init mt8189_pinctrl_init(void)
+{
+	return platform_driver_register(&mt8189_pinctrl_driver);
+}
+arch_initcall(mt8189_pinctrl_init);
+
+MODULE_DESCRIPTION("MediaTek MT8189 Pinctrl Driver");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8189.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8189.h
new file mode 100644
index 000000000000..771efb3da73f
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8189.h
@@ -0,0 +1,2452 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ * Author: Lei Xue <lei.xue at mediatek.com>
+ *         Cathy Xu <ot_cathy.xu at mediatek.com>
+ */
+
+#ifndef __PINCTRL_MTK_MT8189_H
+#define __PINCTRL_MTK_MT8189_H
+
+#include "pinctrl-paris.h"
+
+static const struct mtk_pin_desc mtk_pins_mt8189[] = {
+	MTK_PIN(
+		0, "GPIO0",
+		MTK_EINT_FUNCTION(0, 0),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO0"),
+		MTK_FUNCTION(1, "TP_GPIO0_AO"),
+		MTK_FUNCTION(2, "SPIM3_A_CSB"),
+		MTK_FUNCTION(3, "I2SOUT0_MCK"),
+		MTK_FUNCTION(4, "SCP_SPI0_CS"),
+		MTK_FUNCTION(6, "CONN_BPI_BUS6"),
+		MTK_FUNCTION(7, "DBG_MON_A0")
+	),
+
+	MTK_PIN(
+		1, "GPIO1",
+		MTK_EINT_FUNCTION(0, 1),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO1"),
+		MTK_FUNCTION(1, "TP_GPIO1_AO"),
+		MTK_FUNCTION(2, "SPIM3_A_CLK"),
+		MTK_FUNCTION(3, "I2SOUT0_BCK"),
+		MTK_FUNCTION(4, "SCP_SPI0_CK"),
+		MTK_FUNCTION(6, "CONN_BPI_BUS7"),
+		MTK_FUNCTION(7, "DBG_MON_A1")
+	),
+
+	MTK_PIN(
+		2, "GPIO2",
+		MTK_EINT_FUNCTION(0, 2),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO2"),
+		MTK_FUNCTION(1, "TP_GPIO2_AO"),
+		MTK_FUNCTION(2, "SPIM3_A_MO"),
+		MTK_FUNCTION(3, "I2SOUT0_LRCK"),
+		MTK_FUNCTION(4, "SCP_SPI0_MO"),
+		MTK_FUNCTION(6, "CONN_BPI_BUS8"),
+		MTK_FUNCTION(7, "DBG_MON_A2")
+	),
+
+	MTK_PIN(
+		3, "GPIO3",
+		MTK_EINT_FUNCTION(0, 3),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO3"),
+		MTK_FUNCTION(1, "TP_GPIO3_AO"),
+		MTK_FUNCTION(2, "SPIM3_A_MI"),
+		MTK_FUNCTION(3, "I2SOUT0_DO"),
+		MTK_FUNCTION(4, "SCP_SPI0_MI"),
+		MTK_FUNCTION(6, "CONN_BPI_BUS9"),
+		MTK_FUNCTION(7, "DBG_MON_A3")
+	),
+
+	MTK_PIN(
+		4, "GPIO4",
+		MTK_EINT_FUNCTION(0, 4),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO4"),
+		MTK_FUNCTION(1, "TP_GPIO4_AO"),
+		MTK_FUNCTION(2, "SPIM4_A_CSB"),
+		MTK_FUNCTION(3, "I2SIN0_DI"),
+		MTK_FUNCTION(4, "SCP_SPI1_CS"),
+		MTK_FUNCTION(6, "CONN_BPI_BUS10"),
+		MTK_FUNCTION(7, "DBG_MON_A4")
+	),
+
+	MTK_PIN(
+		5, "GPIO5",
+		MTK_EINT_FUNCTION(0, 5),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO5"),
+		MTK_FUNCTION(1, "TP_GPIO5_AO"),
+		MTK_FUNCTION(2, "SPIM4_A_CLK"),
+		MTK_FUNCTION(3, "I2SIN0_BCK"),
+		MTK_FUNCTION(4, "SCP_SPI1_CK"),
+		MTK_FUNCTION(6, "CONN_BPI_BUS11_OLAT0"),
+		MTK_FUNCTION(7, "DBG_MON_A5")
+	),
+
+	MTK_PIN(
+		6, "GPIO6",
+		MTK_EINT_FUNCTION(0, 6),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO6"),
+		MTK_FUNCTION(1, "TP_GPIO6_AO"),
+		MTK_FUNCTION(2, "SPIM4_A_MO"),
+		MTK_FUNCTION(3, "I2SIN0_LRCK"),
+		MTK_FUNCTION(4, "SCP_SPI1_MO"),
+		MTK_FUNCTION(6, "CONN_BPI_BUS12_OLAT1"),
+		MTK_FUNCTION(7, "DBG_MON_A6")
+	),
+
+	MTK_PIN(
+		7, "GPIO7",
+		MTK_EINT_FUNCTION(0, 7),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO7"),
+		MTK_FUNCTION(1, "TP_GPIO7_AO"),
+		MTK_FUNCTION(2, "SPIM4_A_MI"),
+		MTK_FUNCTION(3, "I2SIN0_MCK"),
+		MTK_FUNCTION(4, "SCP_SPI1_MI"),
+		MTK_FUNCTION(6, "CONN_BPI_BUS13_OLAT2"),
+		MTK_FUNCTION(7, "DBG_MON_A7")
+	),
+
+	MTK_PIN(
+		8, "GPIO8",
+		MTK_EINT_FUNCTION(0, 8),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO8"),
+		MTK_FUNCTION(1, "TP_UTXD1_VLP"),
+		MTK_FUNCTION(2, "SPIM5_A_CSB"),
+		MTK_FUNCTION(3, "I2SOUT1_MCK"),
+		MTK_FUNCTION(4, "VADSP_UTXD0"),
+		MTK_FUNCTION(6, "CONN_BPI_BUS14_OLAT3"),
+		MTK_FUNCTION(7, "DBG_MON_A8")
+	),
+
+	MTK_PIN(
+		9, "GPIO9",
+		MTK_EINT_FUNCTION(0, 9),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO9"),
+		MTK_FUNCTION(1, "TP_URXD1_VLP"),
+		MTK_FUNCTION(2, "SPIM5_A_CLK"),
+		MTK_FUNCTION(3, "I2SOUT1_BCK"),
+		MTK_FUNCTION(4, "VADSP_URXD0"),
+		MTK_FUNCTION(6, "CONN_BPI_BUS15_OLAT4"),
+		MTK_FUNCTION(7, "DBG_MON_A9")
+	),
+
+	MTK_PIN(
+		10, "GPIO10",
+		MTK_EINT_FUNCTION(0, 10),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO10"),
+		MTK_FUNCTION(1, "TP_UCTS1_VLP"),
+		MTK_FUNCTION(2, "SPIM5_A_MO"),
+		MTK_FUNCTION(3, "I2SOUT1_LRCK"),
+		MTK_FUNCTION(4, "SRCLKENAI0"),
+		MTK_FUNCTION(6, "CONN_BPI_BUS16_OLAT5"),
+		MTK_FUNCTION(7, "DBG_MON_A10")
+	),
+
+	MTK_PIN(
+		11, "GPIO11",
+		MTK_EINT_FUNCTION(0, 11),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO11"),
+		MTK_FUNCTION(1, "TP_URTS1_VLP"),
+		MTK_FUNCTION(2, "SPIM5_A_MI"),
+		MTK_FUNCTION(3, "I2SOUT1_DO"),
+		MTK_FUNCTION(4, "SRCLKENAI1"),
+		MTK_FUNCTION(5, "PWM_vlp"),
+		MTK_FUNCTION(7, "DBG_MON_A11")
+	),
+
+	MTK_PIN(
+		12, "GPIO12",
+		MTK_EINT_FUNCTION(0, 12),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO12"),
+		MTK_FUNCTION(1, "TP_UTXD1_VCORE"),
+		MTK_FUNCTION(2, "UTXD3"),
+		MTK_FUNCTION(3, "CLKM0"),
+		MTK_FUNCTION(4, "CMFLASH0"),
+		MTK_FUNCTION(6, "ANT_SEL0"),
+		MTK_FUNCTION(7, "DBG_MON_B20")
+	),
+
+	MTK_PIN(
+		13, "GPIO13",
+		MTK_EINT_FUNCTION(0, 13),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO13"),
+		MTK_FUNCTION(1, "TP_URXD1_VCORE"),
+		MTK_FUNCTION(2, "URXD3"),
+		MTK_FUNCTION(3, "CLKM1"),
+		MTK_FUNCTION(4, "CMFLASH1"),
+		MTK_FUNCTION(6, "ANT_SEL1"),
+		MTK_FUNCTION(7, "DBG_MON_B21")
+	),
+
+	MTK_PIN(
+		14, "GPIO14",
+		MTK_EINT_FUNCTION(0, 14),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO14"),
+		MTK_FUNCTION(1, "TP_UCTS1_VCORE"),
+		MTK_FUNCTION(2, "UCTS3"),
+		MTK_FUNCTION(3, "CLKM2"),
+		MTK_FUNCTION(4, "CMFLASH2"),
+		MTK_FUNCTION(6, "ANT_SEL2"),
+		MTK_FUNCTION(7, "DBG_MON_B22")
+	),
+
+	MTK_PIN(
+		15, "GPIO15",
+		MTK_EINT_FUNCTION(0, 15),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO15"),
+		MTK_FUNCTION(1, "TP_URTS1_VCORE"),
+		MTK_FUNCTION(2, "URTS3"),
+		MTK_FUNCTION(3, "CLKM3"),
+		MTK_FUNCTION(4, "CMVREF0"),
+		MTK_FUNCTION(6, "ANT_SEL3"),
+		MTK_FUNCTION(7, "DBG_MON_B23")
+	),
+
+	MTK_PIN(
+		16, "GPIO16",
+		MTK_EINT_FUNCTION(0, 16),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO16"),
+		MTK_FUNCTION(1, "PWM_0"),
+		MTK_FUNCTION(2, "UCTS2"),
+		MTK_FUNCTION(3, "DP_TX_HPD"),
+		MTK_FUNCTION(4, "CMVREF1"),
+		MTK_FUNCTION(5, "MD32_0_GPIO0"),
+		MTK_FUNCTION(6, "ANT_SEL4"),
+		MTK_FUNCTION(7, "DBG_MON_B24")
+	),
+
+	MTK_PIN(
+		17, "GPIO17",
+		MTK_EINT_FUNCTION(0, 17),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO17"),
+		MTK_FUNCTION(1, "PWM_1"),
+		MTK_FUNCTION(2, "URTS2"),
+		MTK_FUNCTION(3, "EDP_TX_HPD"),
+		MTK_FUNCTION(4, "CMVREF2"),
+		MTK_FUNCTION(5, "MD32_1_GPIO0"),
+		MTK_FUNCTION(6, "PMSR_SMAP"),
+		MTK_FUNCTION(7, "DBG_MON_B25")
+	),
+
+	MTK_PIN(
+		18, "GPIO18",
+		MTK_EINT_FUNCTION(0, 18),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO18"),
+		MTK_FUNCTION(1, "CMFLASH0"),
+		MTK_FUNCTION(2, "CMVREF3"),
+		MTK_FUNCTION(3, "UTXD2"),
+		MTK_FUNCTION(4, "DISP_PWM1"),
+		MTK_FUNCTION(5, "I2SIN1_MCK"),
+		MTK_FUNCTION(6, "mbistreaden_trigger"),
+		MTK_FUNCTION(7, "DBG_MON_A12")
+	),
+
+	MTK_PIN(
+		19, "GPIO19",
+		MTK_EINT_FUNCTION(0, 19),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO19"),
+		MTK_FUNCTION(1, "CMFLASH1"),
+		MTK_FUNCTION(2, "CMVREF2"),
+		MTK_FUNCTION(3, "URXD2"),
+		MTK_FUNCTION(4, "USB_DRVVBUS_1P"),
+		MTK_FUNCTION(5, "I2SIN1_BCK"),
+		MTK_FUNCTION(6, "mbistwriteen_trigger"),
+		MTK_FUNCTION(7, "DBG_MON_A13")
+	),
+
+	MTK_PIN(
+		20, "GPIO20",
+		MTK_EINT_FUNCTION(0, 20),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO20"),
+		MTK_FUNCTION(1, "CMFLASH2"),
+		MTK_FUNCTION(2, "CMVREF1"),
+		MTK_FUNCTION(3, "UCTS2"),
+		MTK_FUNCTION(4, "PERSTN"),
+		MTK_FUNCTION(5, "I2SIN1_LRCK"),
+		MTK_FUNCTION(6, "DMIC0_DAT1"),
+		MTK_FUNCTION(7, "DBG_MON_A14")
+	),
+
+	MTK_PIN(
+		21, "GPIO21",
+		MTK_EINT_FUNCTION(0, 21),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO21"),
+		MTK_FUNCTION(1, "CMFLASH3"),
+		MTK_FUNCTION(2, "CMVREF0"),
+		MTK_FUNCTION(3, "URTS2"),
+		MTK_FUNCTION(4, "CLKREQN"),
+		MTK_FUNCTION(5, "I2SIN1_DI"),
+		MTK_FUNCTION(6, "DMIC1_DAT1"),
+		MTK_FUNCTION(7, "DBG_MON_A15")
+	),
+
+	MTK_PIN(
+		22, "GPIO22",
+		MTK_EINT_FUNCTION(0, 22),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO22"),
+		MTK_FUNCTION(1, "CMMCLK0"),
+		MTK_FUNCTION(2, "TP_GPIO4_AO")
+	),
+
+	MTK_PIN(
+		23, "GPIO23",
+		MTK_EINT_FUNCTION(0, 23),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO23"),
+		MTK_FUNCTION(1, "CMMCLK1"),
+		MTK_FUNCTION(2, "TP_GPIO5_AO"),
+		MTK_FUNCTION(3, "SSPM_UTXD_AO_VLP"),
+		MTK_FUNCTION(4, "PWM_vlp"),
+		MTK_FUNCTION(6, "SRCLKENAI0")
+	),
+
+	MTK_PIN(
+		24, "GPIO24",
+		MTK_EINT_FUNCTION(0, 24),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO24"),
+		MTK_FUNCTION(1, "CMMCLK2"),
+		MTK_FUNCTION(2, "TP_GPIO6_AO"),
+		MTK_FUNCTION(3, "SSPM_URXD_AO_VLP"),
+		MTK_FUNCTION(4, "WAKEN"),
+		MTK_FUNCTION(5, "SPMI_P_TRIG_FLAG"),
+		MTK_FUNCTION(6, "SRCLKENAI1")
+	),
+
+	MTK_PIN(
+		25, "GPIO25",
+		MTK_EINT_FUNCTION(0, 25),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO25"),
+		MTK_FUNCTION(1, "LCM_RST"),
+		MTK_FUNCTION(2, "DP_TX_HPD"),
+		MTK_FUNCTION(3, "CMFLASH3"),
+		MTK_FUNCTION(4, "MD32_0_GPIO0"),
+		MTK_FUNCTION(5, "USB_DRVVBUS_2P")
+	),
+
+	MTK_PIN(
+		26, "GPIO26",
+		MTK_EINT_FUNCTION(0, 26),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO26"),
+		MTK_FUNCTION(1, "DSI_TE"),
+		MTK_FUNCTION(2, "EDP_TX_HPD"),
+		MTK_FUNCTION(3, "CMVREF3"),
+		MTK_FUNCTION(4, "MD32_1_GPIO0"),
+		MTK_FUNCTION(5, "USB_DRVVBUS_3P")
+	),
+
+	MTK_PIN(
+		27, "GPIO27",
+		MTK_EINT_FUNCTION(0, 27),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO27"),
+		MTK_FUNCTION(1, "DP_TX_HPD"),
+		MTK_FUNCTION(2, "mbistreaden_trigger"),
+		MTK_FUNCTION(3, "MD32_0_GPIO0"),
+		MTK_FUNCTION(4, "TP_UCTS1_VCORE"),
+		MTK_FUNCTION(5, "CMVREF4"),
+		MTK_FUNCTION(6, "EXTIF0_ACT"),
+		MTK_FUNCTION(7, "ANT_SEL0")
+	),
+
+	MTK_PIN(
+		28, "GPIO28",
+		MTK_EINT_FUNCTION(0, 28),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO28"),
+		MTK_FUNCTION(1, "EDP_TX_HPD"),
+		MTK_FUNCTION(2, "mbistwriteen_trigger"),
+		MTK_FUNCTION(3, "MD32_1_GPIO0"),
+		MTK_FUNCTION(4, "TP_URTS1_VCORE"),
+		MTK_FUNCTION(6, "EXTIF0_PRI"),
+		MTK_FUNCTION(7, "ANT_SEL1")
+	),
+
+	MTK_PIN(
+		29, "GPIO29",
+		MTK_EINT_FUNCTION(0, 29),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO29"),
+		MTK_FUNCTION(1, "DISP_PWM0"),
+		MTK_FUNCTION(2, "MD32_1_TXD"),
+		MTK_FUNCTION(3, "SSPM_UTXD_AO_VCORE"),
+		MTK_FUNCTION(5, "USB_DRVVBUS_4P")
+	),
+
+	MTK_PIN(
+		30, "GPIO30",
+		MTK_EINT_FUNCTION(0, 30),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO30"),
+		MTK_FUNCTION(1, "DISP_PWM1"),
+		MTK_FUNCTION(2, "MD32_1_RXD"),
+		MTK_FUNCTION(3, "SSPM_URXD_AO_VCORE"),
+		MTK_FUNCTION(5, "PMSR_SMAP"),
+		MTK_FUNCTION(6, "EXTIF0_GNT_B"),
+		MTK_FUNCTION(7, "ANT_SEL2")
+	),
+
+	MTK_PIN(
+		31, "GPIO31",
+		MTK_EINT_FUNCTION(0, 31),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO31"),
+		MTK_FUNCTION(1, "UTXD0"),
+		MTK_FUNCTION(2, "MD32_0_TXD")
+	),
+
+	MTK_PIN(
+		32, "GPIO32",
+		MTK_EINT_FUNCTION(0, 32),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO32"),
+		MTK_FUNCTION(1, "URXD0"),
+		MTK_FUNCTION(2, "MD32_0_RXD")
+	),
+
+	MTK_PIN(
+		33, "GPIO33",
+		MTK_EINT_FUNCTION(0, 33),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO33"),
+		MTK_FUNCTION(1, "UTXD1"),
+		MTK_FUNCTION(2, "VADSP_UTXD0"),
+		MTK_FUNCTION(3, "TP_UTXD1_VLP"),
+		MTK_FUNCTION(4, "MD32_1_TXD"),
+		MTK_FUNCTION(5, "CONN_BGF_UART0_TXD"),
+		MTK_FUNCTION(6, "CONN_WIFI_TXD")
+	),
+
+	MTK_PIN(
+		34, "GPIO34",
+		MTK_EINT_FUNCTION(0, 34),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO34"),
+		MTK_FUNCTION(1, "URXD1"),
+		MTK_FUNCTION(2, "VADSP_URXD0"),
+		MTK_FUNCTION(3, "TP_URXD1_VLP"),
+		MTK_FUNCTION(4, "MD32_1_RXD"),
+		MTK_FUNCTION(5, "CONN_BGF_UART0_RXD")
+	),
+
+	MTK_PIN(
+		35, "GPIO35",
+		MTK_EINT_FUNCTION(0, 35),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO35"),
+		MTK_FUNCTION(1, "UTXD2"),
+		MTK_FUNCTION(2, "UCTS1"),
+		MTK_FUNCTION(3, "TP_UCTS1_VLP"),
+		MTK_FUNCTION(4, "SSPM_UTXD_AO_VLP"),
+		MTK_FUNCTION(5, "VADSP_UTXD0"),
+		MTK_FUNCTION(6, "CONN_BT_TXD")
+	),
+
+	MTK_PIN(
+		36, "GPIO36",
+		MTK_EINT_FUNCTION(0, 36),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO36"),
+		MTK_FUNCTION(1, "URXD2"),
+		MTK_FUNCTION(2, "URTS1"),
+		MTK_FUNCTION(3, "TP_URTS1_VLP"),
+		MTK_FUNCTION(4, "SSPM_URXD_AO_VLP"),
+		MTK_FUNCTION(5, "VADSP_URXD0")
+	),
+
+	MTK_PIN(
+		37, "GPIO37",
+		MTK_EINT_FUNCTION(0, 37),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO37"),
+		MTK_FUNCTION(1, "UTXD3"),
+		MTK_FUNCTION(2, "UCTS0"),
+		MTK_FUNCTION(3, "TP_UTXD1_VCORE"),
+		MTK_FUNCTION(4, "SSPM_UTXD_AO_VCORE"),
+		MTK_FUNCTION(6, "MD32_0_TXD"),
+		MTK_FUNCTION(7, "CONN_BGF_UART0_TXD")
+	),
+
+	MTK_PIN(
+		38, "GPIO38",
+		MTK_EINT_FUNCTION(0, 38),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO38"),
+		MTK_FUNCTION(1, "URXD3"),
+		MTK_FUNCTION(2, "URTS0"),
+		MTK_FUNCTION(3, "TP_URXD1_VCORE"),
+		MTK_FUNCTION(4, "SSPM_URXD_AO_VCORE"),
+		MTK_FUNCTION(6, "MD32_0_RXD"),
+		MTK_FUNCTION(7, "CONN_BGF_UART0_RXD")
+	),
+
+	MTK_PIN(
+		39, "GPIO39",
+		MTK_EINT_FUNCTION(0, 39),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO39"),
+		MTK_FUNCTION(1, "JTMS_SEL1")
+	),
+
+	MTK_PIN(
+		40, "GPIO40",
+		MTK_EINT_FUNCTION(0, 40),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO40"),
+		MTK_FUNCTION(1, "JTCK_SEL1")
+	),
+
+	MTK_PIN(
+		41, "GPIO41",
+		MTK_EINT_FUNCTION(0, 41),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO41"),
+		MTK_FUNCTION(1, "JTDI_SEL1")
+	),
+
+	MTK_PIN(
+		42, "GPIO42",
+		MTK_EINT_FUNCTION(0, 42),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO42"),
+		MTK_FUNCTION(1, "JTDO_SEL1")
+	),
+
+	MTK_PIN(
+		43, "GPIO43",
+		MTK_EINT_FUNCTION(0, 43),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO43"),
+		MTK_FUNCTION(1, "JTRSTn_SEL1")
+	),
+
+	MTK_PIN(
+		44, "GPIO44",
+		MTK_EINT_FUNCTION(0, 44),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO44"),
+		MTK_FUNCTION(1, "KPCOL0")
+	),
+
+	MTK_PIN(
+		45, "GPIO45",
+		MTK_EINT_FUNCTION(0, 45),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO45"),
+		MTK_FUNCTION(1, "KPCOL1"),
+		MTK_FUNCTION(2, "TP_GPIO0_AO"),
+		MTK_FUNCTION(3, "SRCLKENAI1"),
+		MTK_FUNCTION(7, "DBG_MON_A31")
+	),
+
+	MTK_PIN(
+		46, "GPIO46",
+		MTK_EINT_FUNCTION(0, 46),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO46"),
+		MTK_FUNCTION(1, "KPROW0"),
+		MTK_FUNCTION(2, "TP_GPIO1_AO")
+	),
+
+	MTK_PIN(
+		47, "GPIO47",
+		MTK_EINT_FUNCTION(0, 47),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO47"),
+		MTK_FUNCTION(1, "KPROW1"),
+		MTK_FUNCTION(2, "TP_GPIO2_AO"),
+		MTK_FUNCTION(3, "SRCLKENAI0"),
+		MTK_FUNCTION(7, "DBG_MON_A32")
+	),
+
+	MTK_PIN(
+		48, "GPIO48",
+		MTK_EINT_FUNCTION(0, 48),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO48"),
+		MTK_FUNCTION(1, "WAKEN"),
+		MTK_FUNCTION(2, "TP_GPIO3_AO"),
+		MTK_FUNCTION(3, "SPMI_P_TRIG_FLAG")
+	),
+
+	MTK_PIN(
+		49, "GPIO49",
+		MTK_EINT_FUNCTION(0, 49),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO49"),
+		MTK_FUNCTION(1, "PERSTN"),
+		MTK_FUNCTION(2, "MD32_0_GPIO0"),
+		MTK_FUNCTION(3, "UFS_MPHY_SCL"),
+		MTK_FUNCTION(7, "ANT_SEL3")
+	),
+
+	MTK_PIN(
+		50, "GPIO50",
+		MTK_EINT_FUNCTION(0, 50),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO50"),
+		MTK_FUNCTION(1, "CLKREQN"),
+		MTK_FUNCTION(2, "MD32_1_GPIO0"),
+		MTK_FUNCTION(3, "UFS_MPHY_SDA"),
+		MTK_FUNCTION(7, "ANT_SEL4")
+	),
+
+	MTK_PIN(
+		51, "GPIO51",
+		MTK_EINT_FUNCTION(0, 51),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO51"),
+		MTK_FUNCTION(1, "SCP_SCL0"),
+		MTK_FUNCTION(2, "SCL0")
+	),
+
+	MTK_PIN(
+		52, "GPIO52",
+		MTK_EINT_FUNCTION(0, 52),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO52"),
+		MTK_FUNCTION(1, "SCP_SDA0"),
+		MTK_FUNCTION(2, "SDA0")
+	),
+
+	MTK_PIN(
+		53, "GPIO53",
+		MTK_EINT_FUNCTION(0, 53),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO53"),
+		MTK_FUNCTION(1, "SCP_SCL1"),
+		MTK_FUNCTION(2, "SCL1")
+	),
+
+	MTK_PIN(
+		54, "GPIO54",
+		MTK_EINT_FUNCTION(0, 54),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO54"),
+		MTK_FUNCTION(1, "SCP_SDA1"),
+		MTK_FUNCTION(2, "SDA1")
+	),
+
+	MTK_PIN(
+		55, "GPIO55",
+		MTK_EINT_FUNCTION(0, 55),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO55"),
+		MTK_FUNCTION(1, "SCL2"),
+		MTK_FUNCTION(2, "UFS_MPHY_SCL"),
+		MTK_FUNCTION(3, "SSUSB_U2SIF_SCL")
+	),
+
+	MTK_PIN(
+		56, "GPIO56",
+		MTK_EINT_FUNCTION(0, 56),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO56"),
+		MTK_FUNCTION(1, "SDA2"),
+		MTK_FUNCTION(2, "UFS_MPHY_SDA"),
+		MTK_FUNCTION(3, "SSUSB_U2SIF_SDA")
+	),
+
+	MTK_PIN(
+		57, "GPIO57",
+		MTK_EINT_FUNCTION(0, 57),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO57"),
+		MTK_FUNCTION(1, "SCL3"),
+		MTK_FUNCTION(2, "PCIE_PHY_I2C_SCL"),
+		MTK_FUNCTION(3, "SSUSB_U2SIF_SCL_1P")
+	),
+
+	MTK_PIN(
+		58, "GPIO58",
+		MTK_EINT_FUNCTION(0, 58),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO58"),
+		MTK_FUNCTION(1, "SDA3"),
+		MTK_FUNCTION(2, "PCIE_PHY_I2C_SDA"),
+		MTK_FUNCTION(3, "SSUSB_U2SIF_SDA_1P")
+	),
+
+	MTK_PIN(
+		59, "GPIO59",
+		MTK_EINT_FUNCTION(0, 59),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO59"),
+		MTK_FUNCTION(1, "SCL4"),
+		MTK_FUNCTION(2, "SSUSB_U3PHY_I2C_SCL")
+	),
+
+	MTK_PIN(
+		60, "GPIO60",
+		MTK_EINT_FUNCTION(0, 60),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO60"),
+		MTK_FUNCTION(1, "SDA4"),
+		MTK_FUNCTION(2, "SSUSB_U3PHY_I2C_SDA")
+	),
+
+	MTK_PIN(
+		61, "GPIO61",
+		MTK_EINT_FUNCTION(0, 61),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO61"),
+		MTK_FUNCTION(1, "SCL5"),
+		MTK_FUNCTION(2, "SSPXTP_U3PHY_I2C_SCL")
+	),
+
+	MTK_PIN(
+		62, "GPIO62",
+		MTK_EINT_FUNCTION(0, 62),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO62"),
+		MTK_FUNCTION(1, "SDA5"),
+		MTK_FUNCTION(2, "SSPXTP_U3PHY_I2C_SDA")
+	),
+
+	MTK_PIN(
+		63, "GPIO63",
+		MTK_EINT_FUNCTION(0, 63),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO63"),
+		MTK_FUNCTION(1, "SCL6")
+	),
+
+	MTK_PIN(
+		64, "GPIO64",
+		MTK_EINT_FUNCTION(0, 64),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO64"),
+		MTK_FUNCTION(1, "SDA6")
+	),
+
+	MTK_PIN(
+		65, "GPIO65",
+		MTK_EINT_FUNCTION(0, 65),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO65"),
+		MTK_FUNCTION(1, "SCL7")
+	),
+
+	MTK_PIN(
+		66, "GPIO66",
+		MTK_EINT_FUNCTION(0, 66),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO66"),
+		MTK_FUNCTION(1, "SDA7")
+	),
+
+	MTK_PIN(
+		67, "GPIO67",
+		MTK_EINT_FUNCTION(0, 67),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO67"),
+		MTK_FUNCTION(1, "SCL8")
+	),
+
+	MTK_PIN(
+		68, "GPIO68",
+		MTK_EINT_FUNCTION(0, 68),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO68"),
+		MTK_FUNCTION(1, "SDA8")
+	),
+
+	MTK_PIN(
+		69, "GPIO69",
+		MTK_EINT_FUNCTION(0, 69),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO69"),
+		MTK_FUNCTION(1, "SPIM0_CSB"),
+		MTK_FUNCTION(2, "SCP_SPI0_CS"),
+		MTK_FUNCTION(3, "SPM_JTAG_TMS_VCORE"),
+		MTK_FUNCTION(4, "VADSP_JTAG0_TMS"),
+		MTK_FUNCTION(5, "SPM_JTAG_TMS"),
+		MTK_FUNCTION(6, "SSPM_JTAG_TMS_VLP"),
+		MTK_FUNCTION(7, "SCP_JTAG0_TMS_VLP")
+	),
+
+	MTK_PIN(
+		70, "GPIO70",
+		MTK_EINT_FUNCTION(0, 70),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO70"),
+		MTK_FUNCTION(1, "SPIM0_CLK"),
+		MTK_FUNCTION(2, "SCP_SPI0_CK"),
+		MTK_FUNCTION(3, "SPM_JTAG_TCK_VCORE"),
+		MTK_FUNCTION(4, "VADSP_JTAG0_TCK"),
+		MTK_FUNCTION(5, "SPM_JTAG_TCK"),
+		MTK_FUNCTION(6, "SSPM_JTAG_TCK_VLP"),
+		MTK_FUNCTION(7, "SCP_JTAG0_TCK_VLP")
+	),
+
+	MTK_PIN(
+		71, "GPIO71",
+		MTK_EINT_FUNCTION(0, 71),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO71"),
+		MTK_FUNCTION(1, "SPIM0_MO"),
+		MTK_FUNCTION(2, "SCP_SPI0_MO"),
+		MTK_FUNCTION(3, "SPM_JTAG_TDI_VCORE"),
+		MTK_FUNCTION(4, "VADSP_JTAG0_TDI"),
+		MTK_FUNCTION(5, "SPM_JTAG_TDI"),
+		MTK_FUNCTION(6, "SSPM_JTAG_TDI_VLP"),
+		MTK_FUNCTION(7, "SCP_JTAG0_TDI_VLP")
+	),
+
+	MTK_PIN(
+		72, "GPIO72",
+		MTK_EINT_FUNCTION(0, 72),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO72"),
+		MTK_FUNCTION(1, "SPIM0_MI"),
+		MTK_FUNCTION(2, "SCP_SPI0_MI"),
+		MTK_FUNCTION(3, "SPM_JTAG_TDO_VCORE"),
+		MTK_FUNCTION(4, "VADSP_JTAG0_TDO"),
+		MTK_FUNCTION(5, "SPM_JTAG_TDO"),
+		MTK_FUNCTION(6, "SSPM_JTAG_TDO_VLP"),
+		MTK_FUNCTION(7, "SCP_JTAG0_TDO_VLP")
+	),
+
+	MTK_PIN(
+		73, "GPIO73",
+		MTK_EINT_FUNCTION(0, 73),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO73"),
+		MTK_FUNCTION(1, "SPIM1_CSB"),
+		MTK_FUNCTION(2, "SCP_SPI1_CS"),
+		MTK_FUNCTION(3, "SPM_JTAG_TRSTN_VCORE"),
+		MTK_FUNCTION(4, "VADSP_JTAG0_TRSTN"),
+		MTK_FUNCTION(5, "SPM_JTAG_TRSTN"),
+		MTK_FUNCTION(6, "SSPM_JTAG_TRSTN_VLP"),
+		MTK_FUNCTION(7, "SCP_JTAG0_TRSTN_VLP")
+	),
+
+	MTK_PIN(
+		74, "GPIO74",
+		MTK_EINT_FUNCTION(0, 74),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO74"),
+		MTK_FUNCTION(1, "SPIM1_CLK"),
+		MTK_FUNCTION(2, "SCP_SPI1_CK")
+	),
+
+	MTK_PIN(
+		75, "GPIO75",
+		MTK_EINT_FUNCTION(0, 75),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO75"),
+		MTK_FUNCTION(1, "SPIM1_MO"),
+		MTK_FUNCTION(2, "SCP_SPI1_MO")
+	),
+
+	MTK_PIN(
+		76, "GPIO76",
+		MTK_EINT_FUNCTION(0, 76),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO76"),
+		MTK_FUNCTION(1, "SPIM1_MI"),
+		MTK_FUNCTION(2, "SCP_SPI1_MI")
+	),
+
+	MTK_PIN(
+		77, "GPIO77",
+		MTK_EINT_FUNCTION(0, 77),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO77"),
+		MTK_FUNCTION(1, "SPIM2_CSB"),
+		MTK_FUNCTION(2, "PCM0_SYNC"),
+		MTK_FUNCTION(3, "SSUSB_U2SIF_SCL"),
+		MTK_FUNCTION(7, "DBG_MON_A27")
+	),
+
+	MTK_PIN(
+		78, "GPIO78",
+		MTK_EINT_FUNCTION(0, 78),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO78"),
+		MTK_FUNCTION(1, "SPIM2_CLK"),
+		MTK_FUNCTION(2, "PCM0_CLK"),
+		MTK_FUNCTION(3, "SSUSB_U2SIF_SDA"),
+		MTK_FUNCTION(7, "DBG_MON_A28")
+	),
+
+	MTK_PIN(
+		79, "GPIO79",
+		MTK_EINT_FUNCTION(0, 79),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO79"),
+		MTK_FUNCTION(1, "SPIM2_MO"),
+		MTK_FUNCTION(2, "PCM0_DO"),
+		MTK_FUNCTION(3, "SSUSB_U2SIF_SCL_1P"),
+		MTK_FUNCTION(7, "DBG_MON_A29")
+	),
+
+	MTK_PIN(
+		80, "GPIO80",
+		MTK_EINT_FUNCTION(0, 80),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO80"),
+		MTK_FUNCTION(1, "SPIM2_MI"),
+		MTK_FUNCTION(2, "PCM0_DI"),
+		MTK_FUNCTION(3, "SSUSB_U2SIF_SDA_1P"),
+		MTK_FUNCTION(7, "DBG_MON_A30")
+	),
+
+	MTK_PIN(
+		81, "GPIO81",
+		MTK_EINT_FUNCTION(0, 81),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO81"),
+		MTK_FUNCTION(1, "IDDIG"),
+		MTK_FUNCTION(7, "DBG_MON_B32")
+	),
+
+	MTK_PIN(
+		82, "GPIO82",
+		MTK_EINT_FUNCTION(0, 82),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO82"),
+		MTK_FUNCTION(1, "USB_DRVVBUS")
+	),
+
+	MTK_PIN(
+		83, "GPIO83",
+		MTK_EINT_FUNCTION(0, 83),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO83"),
+		MTK_FUNCTION(1, "VBUSVALID")
+	),
+
+	MTK_PIN(
+		84, "GPIO84",
+		MTK_EINT_FUNCTION(0, 84),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO84"),
+		MTK_FUNCTION(1, "USB_DRVVBUS_1P"),
+		MTK_FUNCTION(7, "DBG_MON_A16")
+	),
+
+	MTK_PIN(
+		85, "GPIO85",
+		MTK_EINT_FUNCTION(0, 85),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO85"),
+		MTK_FUNCTION(1, "USB_DRVVBUS_2P"),
+		MTK_FUNCTION(7, "DBG_MON_A17")
+	),
+
+	MTK_PIN(
+		86, "GPIO86",
+		MTK_EINT_FUNCTION(0, 86),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO86"),
+		MTK_FUNCTION(1, "USB_DRVVBUS_3P"),
+		MTK_FUNCTION(7, "DBG_MON_A18")
+	),
+
+	MTK_PIN(
+		87, "GPIO87",
+		MTK_EINT_FUNCTION(0, 87),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO87"),
+		MTK_FUNCTION(1, "USB_DRVVBUS_4P"),
+		MTK_FUNCTION(6, "CMVREF4"),
+		MTK_FUNCTION(7, "DBG_MON_A19")
+	),
+
+	MTK_PIN(
+		88, "GPIO88",
+		MTK_EINT_FUNCTION(0, 88),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO88"),
+		MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
+	),
+
+	MTK_PIN(
+		89, "GPIO89",
+		MTK_EINT_FUNCTION(0, 89),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO89"),
+		MTK_FUNCTION(1, "PWRAP_SPI0_CK")
+	),
+
+	MTK_PIN(
+		90, "GPIO90",
+		MTK_EINT_FUNCTION(0, 90),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO90"),
+		MTK_FUNCTION(1, "PWRAP_SPI0_MO")
+	),
+
+	MTK_PIN(
+		91, "GPIO91",
+		MTK_EINT_FUNCTION(0, 91),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO91"),
+		MTK_FUNCTION(1, "PWRAP_SPI0_MI")
+	),
+
+	MTK_PIN(
+		92, "GPIO92",
+		MTK_EINT_FUNCTION(0, 92),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO92"),
+		MTK_FUNCTION(1, "SRCLKENA0")
+	),
+
+	MTK_PIN(
+		93, "GPIO93",
+		MTK_EINT_FUNCTION(0, 93),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO93"),
+		MTK_FUNCTION(1, "SRCLKENA1")
+	),
+
+	MTK_PIN(
+		94, "GPIO94",
+		MTK_EINT_FUNCTION(0, 94),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO94"),
+		MTK_FUNCTION(1, "SCP_VREQ_VAO")
+	),
+
+	MTK_PIN(
+		95, "GPIO95",
+		MTK_EINT_FUNCTION(0, 95),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO95"),
+		MTK_FUNCTION(1, "RTC32K_CK")
+	),
+
+	MTK_PIN(
+		96, "GPIO96",
+		MTK_EINT_FUNCTION(0, 96),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO96"),
+		MTK_FUNCTION(1, "WATCHDOG")
+	),
+
+	MTK_PIN(
+		97, "GPIO97",
+		MTK_EINT_FUNCTION(0, 97),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO97"),
+		MTK_FUNCTION(1, "AUD_CLK_MOSI")
+	),
+
+	MTK_PIN(
+		98, "GPIO98",
+		MTK_EINT_FUNCTION(0, 98),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO98"),
+		MTK_FUNCTION(1, "AUD_SYNC_MOSI")
+	),
+
+	MTK_PIN(
+		99, "GPIO99",
+		MTK_EINT_FUNCTION(0, 99),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO99"),
+		MTK_FUNCTION(1, "AUD_DAT_MOSI0")
+	),
+
+	MTK_PIN(
+		100, "GPIO100",
+		MTK_EINT_FUNCTION(0, 100),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO100"),
+		MTK_FUNCTION(1, "AUD_DAT_MOSI1")
+	),
+
+	MTK_PIN(
+		101, "GPIO101",
+		MTK_EINT_FUNCTION(0, 101),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO101"),
+		MTK_FUNCTION(1, "AUD_DAT_MISO0")
+	),
+
+	MTK_PIN(
+		102, "GPIO102",
+		MTK_EINT_FUNCTION(0, 102),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO102"),
+		MTK_FUNCTION(1, "AUD_DAT_MISO1")
+	),
+
+	MTK_PIN(
+		103, "GPIO103",
+		MTK_EINT_FUNCTION(0, 103),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO103"),
+		MTK_FUNCTION(1, "I2SIN0_MCK"),
+		MTK_FUNCTION(2, "SPIM3_B_CSB"),
+		MTK_FUNCTION(3, "APU_JTAG_TMS"),
+		MTK_FUNCTION(4, "SCP_JTAG0_TMS_VCORE"),
+		MTK_FUNCTION(5, "CONN_WF_MCU_TMS"),
+		MTK_FUNCTION(6, "SSPM_JTAG_TMS_VCORE"),
+		MTK_FUNCTION(7, "IPU_JTAG_TMS")
+	),
+
+	MTK_PIN(
+		104, "GPIO104",
+		MTK_EINT_FUNCTION(0, 104),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO104"),
+		MTK_FUNCTION(1, "I2SIN0_BCK"),
+		MTK_FUNCTION(2, "SPIM3_B_CLK"),
+		MTK_FUNCTION(3, "APU_JTAG_TCK"),
+		MTK_FUNCTION(4, "SCP_JTAG0_TCK_VCORE"),
+		MTK_FUNCTION(5, "CONN_WF_MCU_TCK"),
+		MTK_FUNCTION(6, "SSPM_JTAG_TCK_VCORE"),
+		MTK_FUNCTION(7, "IPU_JTAG_TCK")
+	),
+
+	MTK_PIN(
+		105, "GPIO105",
+		MTK_EINT_FUNCTION(0, 105),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO105"),
+		MTK_FUNCTION(1, "I2SIN0_LRCK"),
+		MTK_FUNCTION(2, "SPIM3_B_MO"),
+		MTK_FUNCTION(3, "APU_JTAG_TDI"),
+		MTK_FUNCTION(4, "SCP_JTAG0_TDI_VCORE"),
+		MTK_FUNCTION(5, "CONN_WF_MCU_TDI"),
+		MTK_FUNCTION(6, "SSPM_JTAG_TDI_VCORE"),
+		MTK_FUNCTION(7, "IPU_JTAG_TDI")
+	),
+
+	MTK_PIN(
+		106, "GPIO106",
+		MTK_EINT_FUNCTION(0, 106),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO106"),
+		MTK_FUNCTION(1, "I2SIN0_DI"),
+		MTK_FUNCTION(2, "SPIM3_B_MI"),
+		MTK_FUNCTION(3, "APU_JTAG_TDO"),
+		MTK_FUNCTION(4, "SCP_JTAG0_TDO_VCORE"),
+		MTK_FUNCTION(5, "CONN_WF_MCU_TDO"),
+		MTK_FUNCTION(6, "SSPM_JTAG_TDO_VCORE"),
+		MTK_FUNCTION(7, "IPU_JTAG_TDO")
+	),
+
+	MTK_PIN(
+		107, "GPIO107",
+		MTK_EINT_FUNCTION(0, 107),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO107"),
+		MTK_FUNCTION(1, "I2SOUT0_MCK"),
+		MTK_FUNCTION(2, "SPIM4_B_CSB"),
+		MTK_FUNCTION(3, "APU_JTAG_TRST"),
+		MTK_FUNCTION(4, "SCP_JTAG0_TRSTN_VCORE"),
+		MTK_FUNCTION(5, "CONN_WF_MCU_TRST_B"),
+		MTK_FUNCTION(6, "SSPM_JTAG_TRSTN_VCORE"),
+		MTK_FUNCTION(7, "IPU_JTAG_TRST")
+	),
+
+	MTK_PIN(
+		108, "GPIO108",
+		MTK_EINT_FUNCTION(0, 108),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO108"),
+		MTK_FUNCTION(1, "I2SOUT0_BCK"),
+		MTK_FUNCTION(2, "SPIM4_B_CLK"),
+		MTK_FUNCTION(3, "EXTIF0_ACT"),
+		MTK_FUNCTION(4, "SPM_JTAG_TMS_VCORE"),
+		MTK_FUNCTION(6, "CLKM2"),
+		MTK_FUNCTION(7, "DBG_MON_A20")
+	),
+
+	MTK_PIN(
+		109, "GPIO109",
+		MTK_EINT_FUNCTION(0, 109),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO109"),
+		MTK_FUNCTION(1, "I2SOUT0_LRCK"),
+		MTK_FUNCTION(2, "SPIM4_B_MO"),
+		MTK_FUNCTION(3, "EXTIF0_PRI"),
+		MTK_FUNCTION(4, "SPM_JTAG_TCK_VCORE"),
+		MTK_FUNCTION(6, "CLKM3"),
+		MTK_FUNCTION(7, "DBG_MON_A21")
+	),
+
+	MTK_PIN(
+		110, "GPIO110",
+		MTK_EINT_FUNCTION(0, 110),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO110"),
+		MTK_FUNCTION(1, "I2SOUT0_DO"),
+		MTK_FUNCTION(2, "SPIM4_B_MI"),
+		MTK_FUNCTION(3, "EXTIF0_GNT_B"),
+		MTK_FUNCTION(4, "SPM_JTAG_TDI_VCORE"),
+		MTK_FUNCTION(7, "DBG_MON_A22")
+	),
+
+	MTK_PIN(
+		111, "GPIO111",
+		MTK_EINT_FUNCTION(0, 111),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO111"),
+		MTK_FUNCTION(1, "DMIC0_CLK"),
+		MTK_FUNCTION(2, "I2SIN1_MCK"),
+		MTK_FUNCTION(3, "I2SOUT1_MCK"),
+		MTK_FUNCTION(4, "SPM_JTAG_TDO_VCORE"),
+		MTK_FUNCTION(6, "CONN_MIPI0_SDATA"),
+		MTK_FUNCTION(7, "DBG_MON_A23")
+	),
+
+	MTK_PIN(
+		112, "GPIO112",
+		MTK_EINT_FUNCTION(0, 112),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO112"),
+		MTK_FUNCTION(1, "DMIC0_DAT0"),
+		MTK_FUNCTION(2, "I2SIN1_BCK"),
+		MTK_FUNCTION(3, "I2SOUT1_BCK"),
+		MTK_FUNCTION(4, "SPM_JTAG_TRSTN_VCORE"),
+		MTK_FUNCTION(6, "CONN_MIPI0_SCLK"),
+		MTK_FUNCTION(7, "DBG_MON_A24")
+	),
+
+	MTK_PIN(
+		113, "GPIO113",
+		MTK_EINT_FUNCTION(0, 113),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO113"),
+		MTK_FUNCTION(1, "DMIC1_CLK"),
+		MTK_FUNCTION(2, "I2SIN1_LRCK"),
+		MTK_FUNCTION(3, "I2SOUT1_LRCK"),
+		MTK_FUNCTION(4, "PMSR_SMAP"),
+		MTK_FUNCTION(6, "CONN_MIPI1_SDATA"),
+		MTK_FUNCTION(7, "DBG_MON_A25")
+	),
+
+	MTK_PIN(
+		114, "GPIO114",
+		MTK_EINT_FUNCTION(0, 114),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO114"),
+		MTK_FUNCTION(1, "DMIC1_DAT0"),
+		MTK_FUNCTION(2, "I2SIN1_DI"),
+		MTK_FUNCTION(3, "I2SOUT1_DO"),
+		MTK_FUNCTION(6, "CONN_MIPI1_SCLK"),
+		MTK_FUNCTION(7, "DBG_MON_A26")
+	),
+
+	MTK_PIN(
+		115, "GPIO115",
+		MTK_EINT_FUNCTION(0, 115),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO115"),
+		MTK_FUNCTION(1, "PCM0_CLK"),
+		MTK_FUNCTION(2, "USB_DRVVBUS_1P"),
+		MTK_FUNCTION(3, "PCIE_PHY_I2C_SCL"),
+		MTK_FUNCTION(4, "SSUSB_U3PHY_I2C_SCL"),
+		MTK_FUNCTION(6, "CMFLASH0"),
+		MTK_FUNCTION(7, "EXTIF0_ACT")
+	),
+
+	MTK_PIN(
+		116, "GPIO116",
+		MTK_EINT_FUNCTION(0, 116),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO116"),
+		MTK_FUNCTION(1, "PCM0_SYNC"),
+		MTK_FUNCTION(2, "USB_DRVVBUS_2P"),
+		MTK_FUNCTION(3, "PCIE_PHY_I2C_SDA"),
+		MTK_FUNCTION(4, "SSUSB_U3PHY_I2C_SDA"),
+		MTK_FUNCTION(6, "CMFLASH1"),
+		MTK_FUNCTION(7, "EXTIF0_PRI")
+	),
+
+	MTK_PIN(
+		117, "GPIO117",
+		MTK_EINT_FUNCTION(0, 117),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO117"),
+		MTK_FUNCTION(1, "PCM0_DI"),
+		MTK_FUNCTION(2, "USB_DRVVBUS_3P"),
+		MTK_FUNCTION(3, "DP_TX_HPD"),
+		MTK_FUNCTION(4, "SSPXTP_U3PHY_I2C_SCL"),
+		MTK_FUNCTION(6, "CMVREF0"),
+		MTK_FUNCTION(7, "EXTIF0_GNT_B")
+	),
+
+	MTK_PIN(
+		118, "GPIO118",
+		MTK_EINT_FUNCTION(0, 118),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO118"),
+		MTK_FUNCTION(1, "PCM0_DO"),
+		MTK_FUNCTION(2, "USB_DRVVBUS_4P"),
+		MTK_FUNCTION(3, "EDP_TX_HPD"),
+		MTK_FUNCTION(4, "SSPXTP_U3PHY_I2C_SDA"),
+		MTK_FUNCTION(6, "CMVREF1")
+	),
+
+	MTK_PIN(
+		119, "GPIO119",
+		MTK_EINT_FUNCTION(0, 119),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO119"),
+		MTK_FUNCTION(1, "GBE_TXD3"),
+		MTK_FUNCTION(2, "DMIC0_CLK"),
+		MTK_FUNCTION(3, "LVTS_FOUT"),
+		MTK_FUNCTION(4, "CONN_BGF_MCU_TMS"),
+		MTK_FUNCTION(5, "UDI_TMS"),
+		MTK_FUNCTION(6, "ANT_SEL5"),
+		MTK_FUNCTION(7, "DBG_MON_B0")
+	),
+
+	MTK_PIN(
+		120, "GPIO120",
+		MTK_EINT_FUNCTION(0, 120),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO120"),
+		MTK_FUNCTION(1, "GBE_TXD2"),
+		MTK_FUNCTION(2, "DMIC0_DAT0"),
+		MTK_FUNCTION(3, "LVTS_SDO"),
+		MTK_FUNCTION(4, "CONN_BGF_MCU_TCK"),
+		MTK_FUNCTION(5, "UDI_TCK"),
+		MTK_FUNCTION(6, "ANT_SEL6"),
+		MTK_FUNCTION(7, "DBG_MON_B1")
+	),
+
+	MTK_PIN(
+		121, "GPIO121",
+		MTK_EINT_FUNCTION(0, 121),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO121"),
+		MTK_FUNCTION(1, "GBE_TXD1"),
+		MTK_FUNCTION(2, "DMIC0_DAT1"),
+		MTK_FUNCTION(3, "LVTS_26M"),
+		MTK_FUNCTION(4, "CONN_BGF_MCU_TDI"),
+		MTK_FUNCTION(5, "UDI_TDI"),
+		MTK_FUNCTION(6, "ANT_SEL7"),
+		MTK_FUNCTION(7, "DBG_MON_B2")
+	),
+
+	MTK_PIN(
+		122, "GPIO122",
+		MTK_EINT_FUNCTION(0, 122),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO122"),
+		MTK_FUNCTION(1, "GBE_TXD0"),
+		MTK_FUNCTION(2, "DMIC1_CLK"),
+		MTK_FUNCTION(3, "LVTS_SCF"),
+		MTK_FUNCTION(4, "CONN_BGF_MCU_TDO"),
+		MTK_FUNCTION(5, "UDI_TDO"),
+		MTK_FUNCTION(6, "ANT_SEL8"),
+		MTK_FUNCTION(7, "DBG_MON_B3")
+	),
+
+	MTK_PIN(
+		123, "GPIO123",
+		MTK_EINT_FUNCTION(0, 123),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO123"),
+		MTK_FUNCTION(1, "GBE_RXD3"),
+		MTK_FUNCTION(2, "DMIC1_DAT0"),
+		MTK_FUNCTION(3, "LVTS_SCK"),
+		MTK_FUNCTION(4, "CONN_BGF_MCU_TRST_B"),
+		MTK_FUNCTION(5, "UDI_NTRST"),
+		MTK_FUNCTION(6, "ANT_SEL9"),
+		MTK_FUNCTION(7, "DBG_MON_B4")
+	),
+
+	MTK_PIN(
+		124, "GPIO124",
+		MTK_EINT_FUNCTION(0, 124),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO124"),
+		MTK_FUNCTION(1, "GBE_RXD2"),
+		MTK_FUNCTION(2, "DMIC1_DAT1"),
+		MTK_FUNCTION(3, "LVTS_SDI"),
+		MTK_FUNCTION(4, "CONN_WF_MCU_TMS"),
+		MTK_FUNCTION(5, "SCP_JTAG0_TMS_VCORE"),
+		MTK_FUNCTION(6, "ANT_SEL10"),
+		MTK_FUNCTION(7, "DBG_MON_B5")
+	),
+
+	MTK_PIN(
+		125, "GPIO125",
+		MTK_EINT_FUNCTION(0, 125),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO125"),
+		MTK_FUNCTION(1, "GBE_RXD1"),
+		MTK_FUNCTION(2, "CLKM2"),
+		MTK_FUNCTION(4, "CONN_WF_MCU_TCK"),
+		MTK_FUNCTION(5, "SCP_JTAG0_TCK_VCORE"),
+		MTK_FUNCTION(6, "ANT_SEL11"),
+		MTK_FUNCTION(7, "DBG_MON_B6")
+	),
+
+	MTK_PIN(
+		126, "GPIO126",
+		MTK_EINT_FUNCTION(0, 126),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO126"),
+		MTK_FUNCTION(1, "GBE_RXD0"),
+		MTK_FUNCTION(2, "CLKM3"),
+		MTK_FUNCTION(4, "CONN_WF_MCU_TDI"),
+		MTK_FUNCTION(5, "SCP_JTAG0_TDI_VCORE"),
+		MTK_FUNCTION(6, "ANT_SEL12"),
+		MTK_FUNCTION(7, "DBG_MON_B7")
+	),
+
+	MTK_PIN(
+		127, "GPIO127",
+		MTK_EINT_FUNCTION(0, 127),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO127"),
+		MTK_FUNCTION(1, "GBE_TXC"),
+		MTK_FUNCTION(2, "I2SIN1_MCK"),
+		MTK_FUNCTION(4, "CONN_WF_MCU_TDO"),
+		MTK_FUNCTION(5, "SCP_JTAG0_TDO_VCORE"),
+		MTK_FUNCTION(6, "ANT_SEL13"),
+		MTK_FUNCTION(7, "DBG_MON_B8")
+	),
+
+	MTK_PIN(
+		128, "GPIO128",
+		MTK_EINT_FUNCTION(0, 128),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO128"),
+		MTK_FUNCTION(1, "GBE_RXC"),
+		MTK_FUNCTION(2, "I2SIN1_BCK"),
+		MTK_FUNCTION(4, "CONN_WF_MCU_TRST_B"),
+		MTK_FUNCTION(5, "SCP_JTAG0_TRSTN_VCORE"),
+		MTK_FUNCTION(6, "ANT_SEL14"),
+		MTK_FUNCTION(7, "DBG_MON_B9")
+	),
+
+	MTK_PIN(
+		129, "GPIO129",
+		MTK_EINT_FUNCTION(0, 129),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO129"),
+		MTK_FUNCTION(1, "GBE_RXDV"),
+		MTK_FUNCTION(2, "I2SIN1_LRCK"),
+		MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TMSC"),
+		MTK_FUNCTION(5, "IPU_JTAG_TMS"),
+		MTK_FUNCTION(6, "ANT_SEL15"),
+		MTK_FUNCTION(7, "DBG_MON_B10")
+	),
+
+	MTK_PIN(
+		130, "GPIO130",
+		MTK_EINT_FUNCTION(0, 130),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO130"),
+		MTK_FUNCTION(1, "GBE_TXEN"),
+		MTK_FUNCTION(2, "I2SIN1_DI"),
+		MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TCKC"),
+		MTK_FUNCTION(5, "IPU_JTAG_TCK"),
+		MTK_FUNCTION(6, "ANT_SEL16"),
+		MTK_FUNCTION(7, "DBG_MON_B11")
+	),
+
+	MTK_PIN(
+		131, "GPIO131",
+		MTK_EINT_FUNCTION(0, 131),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO131"),
+		MTK_FUNCTION(1, "GBE_MDC"),
+		MTK_FUNCTION(2, "CLKM0"),
+		MTK_FUNCTION(3, "mbistreaden_trigger"),
+		MTK_FUNCTION(4, "CONN_BGF_UART0_TXD"),
+		MTK_FUNCTION(5, "IPU_JTAG_TDI"),
+		MTK_FUNCTION(6, "ANT_SEL17"),
+		MTK_FUNCTION(7, "DBG_MON_B12")
+	),
+
+	MTK_PIN(
+		132, "GPIO132",
+		MTK_EINT_FUNCTION(0, 132),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO132"),
+		MTK_FUNCTION(1, "GBE_MDIO"),
+		MTK_FUNCTION(2, "CLKM1"),
+		MTK_FUNCTION(3, "mbistwriteen_trigger"),
+		MTK_FUNCTION(4, "CONN_BGF_UART0_RXD"),
+		MTK_FUNCTION(5, "IPU_JTAG_TDO"),
+		MTK_FUNCTION(6, "ANT_SEL18"),
+		MTK_FUNCTION(7, "DBG_MON_B13")
+	),
+
+	MTK_PIN(
+		133, "GPIO133",
+		MTK_EINT_FUNCTION(0, 133),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO133"),
+		MTK_FUNCTION(1, "GBE_TXER"),
+		MTK_FUNCTION(2, "GBE_AUX_PPS2"),
+		MTK_FUNCTION(4, "CONN_BT_TXD"),
+		MTK_FUNCTION(5, "IPU_JTAG_TRST"),
+		MTK_FUNCTION(6, "ANT_SEL19"),
+		MTK_FUNCTION(7, "DBG_MON_B14")
+	),
+
+	MTK_PIN(
+		134, "GPIO134",
+		MTK_EINT_FUNCTION(0, 134),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO134"),
+		MTK_FUNCTION(1, "GBE_RXER"),
+		MTK_FUNCTION(2, "GBE_AUX_PPS3"),
+		MTK_FUNCTION(3, "MCUPM_JTAG_TMS"),
+		MTK_FUNCTION(4, "CONN_WF_MCU_AICE_TMSC"),
+		MTK_FUNCTION(5, "APU_JTAG_TMS"),
+		MTK_FUNCTION(6, "ANT_SEL20"),
+		MTK_FUNCTION(7, "DBG_MON_B15")
+	),
+
+	MTK_PIN(
+		135, "GPIO135",
+		MTK_EINT_FUNCTION(0, 135),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO135"),
+		MTK_FUNCTION(1, "GBE_COL"),
+		MTK_FUNCTION(2, "I2SOUT1_MCK"),
+		MTK_FUNCTION(3, "MCUPM_JTAG_TCK"),
+		MTK_FUNCTION(4, "CONN_WF_MCU_AICE_TCKC"),
+		MTK_FUNCTION(5, "APU_JTAG_TCK"),
+		MTK_FUNCTION(6, "ANT_SEL21"),
+		MTK_FUNCTION(7, "DBG_MON_B16")
+	),
+
+	MTK_PIN(
+		136, "GPIO136",
+		MTK_EINT_FUNCTION(0, 136),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO136"),
+		MTK_FUNCTION(1, "GBE_INTR"),
+		MTK_FUNCTION(2, "I2SOUT1_BCK"),
+		MTK_FUNCTION(3, "MCUPM_JTAG_TDI"),
+		MTK_FUNCTION(4, "CONN_WIFI_TXD"),
+		MTK_FUNCTION(5, "APU_JTAG_TDI"),
+		MTK_FUNCTION(6, "PWM_0"),
+		MTK_FUNCTION(7, "DBG_MON_B17")
+	),
+
+	MTK_PIN(
+		137, "GPIO137",
+		MTK_EINT_FUNCTION(0, 137),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO137"),
+		MTK_FUNCTION(1, "GBE_AUX_PPS0"),
+		MTK_FUNCTION(2, "I2SOUT1_LRCK"),
+		MTK_FUNCTION(3, "MCUPM_JTAG_TDO"),
+		MTK_FUNCTION(4, "DP_TX_HPD"),
+		MTK_FUNCTION(5, "APU_JTAG_TDO"),
+		MTK_FUNCTION(6, "PWM_1"),
+		MTK_FUNCTION(7, "DBG_MON_B18")
+	),
+
+	MTK_PIN(
+		138, "GPIO138",
+		MTK_EINT_FUNCTION(0, 138),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO138"),
+		MTK_FUNCTION(1, "GBE_AUX_PPS1"),
+		MTK_FUNCTION(2, "I2SOUT1_DO"),
+		MTK_FUNCTION(3, "MCUPM_JTAG_TRSTN"),
+		MTK_FUNCTION(4, "EDP_TX_HPD"),
+		MTK_FUNCTION(5, "APU_JTAG_TRST"),
+		MTK_FUNCTION(6, "PWM_2"),
+		MTK_FUNCTION(7, "DBG_MON_B19")
+	),
+
+	MTK_PIN(
+		139, "GPIO139",
+		MTK_EINT_FUNCTION(0, 139),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO139"),
+		MTK_FUNCTION(1, "CONN_TOP_CLK")
+	),
+
+	MTK_PIN(
+		140, "GPIO140",
+		MTK_EINT_FUNCTION(0, 140),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO140"),
+		MTK_FUNCTION(1, "CONN_TOP_DATA")
+	),
+
+	MTK_PIN(
+		141, "GPIO141",
+		MTK_EINT_FUNCTION(0, 141),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO141"),
+		MTK_FUNCTION(1, "CONN_BT_CLK")
+	),
+
+	MTK_PIN(
+		142, "GPIO142",
+		MTK_EINT_FUNCTION(0, 142),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO142"),
+		MTK_FUNCTION(1, "CONN_BT_DATA")
+	),
+
+	MTK_PIN(
+		143, "GPIO143",
+		MTK_EINT_FUNCTION(0, 143),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO143"),
+		MTK_FUNCTION(1, "CONN_HRST_B")
+	),
+
+	MTK_PIN(
+		144, "GPIO144",
+		MTK_EINT_FUNCTION(0, 144),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO144"),
+		MTK_FUNCTION(1, "CONN_WB_PTA")
+	),
+
+	MTK_PIN(
+		145, "GPIO145",
+		MTK_EINT_FUNCTION(0, 145),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO145"),
+		MTK_FUNCTION(1, "CONN_WF_CTRL0")
+	),
+
+	MTK_PIN(
+		146, "GPIO146",
+		MTK_EINT_FUNCTION(0, 146),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO146"),
+		MTK_FUNCTION(1, "CONN_WF_CTRL1")
+	),
+
+	MTK_PIN(
+		147, "GPIO147",
+		MTK_EINT_FUNCTION(0, 147),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO147"),
+		MTK_FUNCTION(1, "CONN_WF_CTRL2")
+	),
+
+	MTK_PIN(
+		148, "GPIO148",
+		MTK_EINT_FUNCTION(0, 148),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO148"),
+		MTK_FUNCTION(1, "CONN_WF_CTRL3")
+	),
+
+	MTK_PIN(
+		149, "GPIO149",
+		MTK_EINT_FUNCTION(0, 149),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO149"),
+		MTK_FUNCTION(1, "CONN_WF_CTRL4")
+	),
+
+	MTK_PIN(
+		150, "GPIO150",
+		MTK_EINT_FUNCTION(0, 150),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO150"),
+		MTK_FUNCTION(1, "SPINOR_CK"),
+		MTK_FUNCTION(2, "DMIC0_CLK"),
+		MTK_FUNCTION(3, "DP_TX_HPD"),
+		MTK_FUNCTION(4, "PWM_0"),
+		MTK_FUNCTION(5, "CONN_BPI_BUS17_ANT0"),
+		MTK_FUNCTION(6, "LVTS_FOUT"),
+		MTK_FUNCTION(7, "DBG_MON_B26")
+	),
+
+	MTK_PIN(
+		151, "GPIO151",
+		MTK_EINT_FUNCTION(0, 151),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO151"),
+		MTK_FUNCTION(1, "SPINOR_CS"),
+		MTK_FUNCTION(2, "DMIC0_DAT0"),
+		MTK_FUNCTION(3, "EDP_TX_HPD"),
+		MTK_FUNCTION(4, "PWM_1"),
+		MTK_FUNCTION(5, "CONN_BPI_BUS18_ANT1"),
+		MTK_FUNCTION(6, "LVTS_SDO"),
+		MTK_FUNCTION(7, "DBG_MON_B27")
+	),
+
+	MTK_PIN(
+		152, "GPIO152",
+		MTK_EINT_FUNCTION(0, 152),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO152"),
+		MTK_FUNCTION(1, "SPINOR_IO0"),
+		MTK_FUNCTION(2, "DMIC0_DAT1"),
+		MTK_FUNCTION(3, "UTXD2"),
+		MTK_FUNCTION(4, "USB_DRVVBUS_1P"),
+		MTK_FUNCTION(5, "CONN_BPI_BUS19_ANT2"),
+		MTK_FUNCTION(6, "LVTS_26M"),
+		MTK_FUNCTION(7, "DBG_MON_B28")
+	),
+
+	MTK_PIN(
+		153, "GPIO153",
+		MTK_EINT_FUNCTION(0, 153),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO153"),
+		MTK_FUNCTION(1, "SPINOR_IO1"),
+		MTK_FUNCTION(2, "DMIC1_CLK"),
+		MTK_FUNCTION(3, "UCTS2"),
+		MTK_FUNCTION(4, "USB_DRVVBUS_2P"),
+		MTK_FUNCTION(5, "CONN_BPI_BUS20_ANT3"),
+		MTK_FUNCTION(6, "LVTS_SCF"),
+		MTK_FUNCTION(7, "DBG_MON_B29")
+	),
+
+	MTK_PIN(
+		154, "GPIO154",
+		MTK_EINT_FUNCTION(0, 154),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO154"),
+		MTK_FUNCTION(1, "SPINOR_IO2"),
+		MTK_FUNCTION(2, "DMIC1_DAT0"),
+		MTK_FUNCTION(3, "URTS2"),
+		MTK_FUNCTION(4, "USB_DRVVBUS_3P"),
+		MTK_FUNCTION(5, "CONN_BPI_BUS21_ANT4"),
+		MTK_FUNCTION(6, "LVTS_SCK"),
+		MTK_FUNCTION(7, "DBG_MON_B30")
+	),
+
+	MTK_PIN(
+		155, "GPIO155",
+		MTK_EINT_FUNCTION(0, 155),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO155"),
+		MTK_FUNCTION(1, "SPINOR_IO3"),
+		MTK_FUNCTION(2, "DMIC1_DAT1"),
+		MTK_FUNCTION(3, "URXD2"),
+		MTK_FUNCTION(4, "USB_DRVVBUS_4P"),
+		MTK_FUNCTION(5, "DISP_PWM1"),
+		MTK_FUNCTION(6, "LVTS_SDI"),
+		MTK_FUNCTION(7, "DBG_MON_B31")
+	),
+
+	MTK_PIN(
+		156, "GPIO156",
+		MTK_EINT_FUNCTION(0, 156),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO156"),
+		MTK_FUNCTION(1, "MSDC0_DAT7")
+	),
+
+	MTK_PIN(
+		157, "GPIO157",
+		MTK_EINT_FUNCTION(0, 157),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO157"),
+		MTK_FUNCTION(1, "MSDC0_DAT6")
+	),
+
+	MTK_PIN(
+		158, "GPIO158",
+		MTK_EINT_FUNCTION(0, 158),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO158"),
+		MTK_FUNCTION(1, "MSDC0_DAT5")
+	),
+
+	MTK_PIN(
+		159, "GPIO159",
+		MTK_EINT_FUNCTION(0, 159),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO159"),
+		MTK_FUNCTION(1, "MSDC0_DAT4")
+	),
+
+	MTK_PIN(
+		160, "GPIO160",
+		MTK_EINT_FUNCTION(0, 160),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO160"),
+		MTK_FUNCTION(1, "MSDC0_RSTB")
+	),
+
+	MTK_PIN(
+		161, "GPIO161",
+		MTK_EINT_FUNCTION(0, 161),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO161"),
+		MTK_FUNCTION(1, "MSDC0_CMD")
+	),
+
+	MTK_PIN(
+		162, "GPIO162",
+		MTK_EINT_FUNCTION(0, 162),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO162"),
+		MTK_FUNCTION(1, "MSDC0_CLK")
+	),
+
+	MTK_PIN(
+		163, "GPIO163",
+		MTK_EINT_FUNCTION(0, 163),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO163"),
+		MTK_FUNCTION(1, "MSDC0_DAT3")
+	),
+
+	MTK_PIN(
+		164, "GPIO164",
+		MTK_EINT_FUNCTION(0, 164),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO164"),
+		MTK_FUNCTION(1, "MSDC0_DAT2")
+	),
+
+	MTK_PIN(
+		165, "GPIO165",
+		MTK_EINT_FUNCTION(0, 165),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO165"),
+		MTK_FUNCTION(1, "MSDC0_DAT1")
+	),
+
+	MTK_PIN(
+		166, "GPIO166",
+		MTK_EINT_FUNCTION(0, 166),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO166"),
+		MTK_FUNCTION(1, "MSDC0_DAT0")
+	),
+
+	MTK_PIN(
+		167, "GPIO167",
+		MTK_EINT_FUNCTION(0, 167),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO167"),
+		MTK_FUNCTION(1, "MSDC0_DSL")
+	),
+
+	MTK_PIN(
+		168, "GPIO168",
+		MTK_EINT_FUNCTION(0, 168),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO168"),
+		MTK_FUNCTION(1, "MSDC1_CMD"),
+		MTK_FUNCTION(2, "CONN_WF_MCU_AICE_TMSC"),
+		MTK_FUNCTION(3, "UCTS1"),
+		MTK_FUNCTION(4, "UDI_TMS"),
+		MTK_FUNCTION(5, "SSPM_JTAG_TMS_VCORE"),
+		MTK_FUNCTION(6, "MCUPM_JTAG_TMS"),
+		MTK_FUNCTION(7, "CONN_BGF_MCU_TMS")
+	),
+
+	MTK_PIN(
+		169, "GPIO169",
+		MTK_EINT_FUNCTION(0, 169),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO169"),
+		MTK_FUNCTION(1, "MSDC1_CLK"),
+		MTK_FUNCTION(2, "CONN_WF_MCU_AICE_TCKC"),
+		MTK_FUNCTION(3, "URTS1"),
+		MTK_FUNCTION(4, "UDI_TCK"),
+		MTK_FUNCTION(5, "SSPM_JTAG_TCK_VCORE"),
+		MTK_FUNCTION(6, "MCUPM_JTAG_TCK"),
+		MTK_FUNCTION(7, "CONN_BGF_MCU_TCK")
+	),
+
+	MTK_PIN(
+		170, "GPIO170",
+		MTK_EINT_FUNCTION(0, 170),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO170"),
+		MTK_FUNCTION(1, "MSDC1_DAT0"),
+		MTK_FUNCTION(2, "SPIM5_B_CSB"),
+		MTK_FUNCTION(3, "UCTS2"),
+		MTK_FUNCTION(4, "UDI_TDI"),
+		MTK_FUNCTION(5, "SSPM_JTAG_TDI_VCORE"),
+		MTK_FUNCTION(6, "MCUPM_JTAG_TDI"),
+		MTK_FUNCTION(7, "CONN_BGF_MCU_TDI")
+	),
+
+	MTK_PIN(
+		171, "GPIO171",
+		MTK_EINT_FUNCTION(0, 171),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO171"),
+		MTK_FUNCTION(1, "MSDC1_DAT1"),
+		MTK_FUNCTION(2, "SPIM5_B_CLK"),
+		MTK_FUNCTION(3, "URTS2"),
+		MTK_FUNCTION(4, "UDI_TDO"),
+		MTK_FUNCTION(5, "SSPM_JTAG_TDO_VCORE"),
+		MTK_FUNCTION(6, "MCUPM_JTAG_TDO"),
+		MTK_FUNCTION(7, "CONN_BGF_MCU_TDO")
+	),
+
+	MTK_PIN(
+		172, "GPIO172",
+		MTK_EINT_FUNCTION(0, 172),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO172"),
+		MTK_FUNCTION(1, "MSDC1_DAT2"),
+		MTK_FUNCTION(2, "SPIM5_B_MO"),
+		MTK_FUNCTION(3, "UCTS3"),
+		MTK_FUNCTION(4, "UDI_NTRST"),
+		MTK_FUNCTION(5, "SSPM_JTAG_TRSTN_VCORE"),
+		MTK_FUNCTION(6, "MCUPM_JTAG_TRSTN"),
+		MTK_FUNCTION(7, "CONN_BGF_MCU_TRST_B")
+	),
+
+	MTK_PIN(
+		173, "GPIO173",
+		MTK_EINT_FUNCTION(0, 173),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO173"),
+		MTK_FUNCTION(1, "MSDC1_DAT3"),
+		MTK_FUNCTION(2, "SPIM5_B_MI"),
+		MTK_FUNCTION(3, "URTS3"),
+		MTK_FUNCTION(4, "CLKM0"),
+		MTK_FUNCTION(5, "PWM_2")
+	),
+
+	MTK_PIN(
+		174, "GPIO174",
+		MTK_EINT_FUNCTION(0, 174),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO174"),
+		MTK_FUNCTION(1, "MSDC2_CMD"),
+		MTK_FUNCTION(2, "CONN_BGF_MCU_AICE_TMSC"),
+		MTK_FUNCTION(3, "UTXD1"),
+		MTK_FUNCTION(4, "VADSP_JTAG0_TMS"),
+		MTK_FUNCTION(5, "SSPM_JTAG_TMS_VLP"),
+		MTK_FUNCTION(6, "SPM_JTAG_TMS"),
+		MTK_FUNCTION(7, "SCP_JTAG0_TMS_VLP")
+	),
+
+	MTK_PIN(
+		175, "GPIO175",
+		MTK_EINT_FUNCTION(0, 175),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO175"),
+		MTK_FUNCTION(1, "MSDC2_CLK"),
+		MTK_FUNCTION(2, "CONN_BGF_MCU_AICE_TCKC"),
+		MTK_FUNCTION(3, "URXD1"),
+		MTK_FUNCTION(4, "VADSP_JTAG0_TCK"),
+		MTK_FUNCTION(5, "SSPM_JTAG_TCK_VLP"),
+		MTK_FUNCTION(6, "SPM_JTAG_TCK"),
+		MTK_FUNCTION(7, "SCP_JTAG0_TCK_VLP")
+	),
+
+	MTK_PIN(
+		176, "GPIO176",
+		MTK_EINT_FUNCTION(0, 176),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO176"),
+		MTK_FUNCTION(1, "MSDC2_DAT0"),
+		MTK_FUNCTION(2, "SRCLKENAI0"),
+		MTK_FUNCTION(3, "UTXD2"),
+		MTK_FUNCTION(4, "VADSP_JTAG0_TDI"),
+		MTK_FUNCTION(5, "SSPM_JTAG_TDI_VLP"),
+		MTK_FUNCTION(6, "SPM_JTAG_TDI"),
+		MTK_FUNCTION(7, "SCP_JTAG0_TDI_VLP")
+	),
+
+	MTK_PIN(
+		177, "GPIO177",
+		MTK_EINT_FUNCTION(0, 177),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO177"),
+		MTK_FUNCTION(1, "MSDC2_DAT1"),
+		MTK_FUNCTION(2, "SRCLKENAI1"),
+		MTK_FUNCTION(3, "URXD2"),
+		MTK_FUNCTION(4, "VADSP_JTAG0_TDO"),
+		MTK_FUNCTION(5, "SSPM_JTAG_TDO_VLP"),
+		MTK_FUNCTION(6, "SPM_JTAG_TDO"),
+		MTK_FUNCTION(7, "SCP_JTAG0_TDO_VLP")
+	),
+
+	MTK_PIN(
+		178, "GPIO178",
+		MTK_EINT_FUNCTION(0, 178),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO178"),
+		MTK_FUNCTION(1, "MSDC2_DAT2"),
+		MTK_FUNCTION(3, "UTXD3"),
+		MTK_FUNCTION(4, "VADSP_JTAG0_TRSTN"),
+		MTK_FUNCTION(5, "SSPM_JTAG_TRSTN_VLP"),
+		MTK_FUNCTION(6, "SPM_JTAG_TRSTN"),
+		MTK_FUNCTION(7, "SCP_JTAG0_TRSTN_VLP")
+	),
+
+	MTK_PIN(
+		179, "GPIO179",
+		MTK_EINT_FUNCTION(0, 179),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO179"),
+		MTK_FUNCTION(1, "MSDC2_DAT3"),
+		MTK_FUNCTION(3, "URXD3"),
+		MTK_FUNCTION(4, "CLKM1"),
+		MTK_FUNCTION(5, "PWM_vlp"),
+		MTK_FUNCTION(7, "TP_GPIO7_AO")
+	),
+
+	MTK_PIN(
+		180, "GPIO180",
+		MTK_EINT_FUNCTION(0, 180),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO180"),
+		MTK_FUNCTION(1, "SPMI_P_SCL")
+	),
+
+	MTK_PIN(
+		181, "GPIO181",
+		MTK_EINT_FUNCTION(0, 181),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO181"),
+		MTK_FUNCTION(1, "SPMI_P_SDA")
+	),
+
+	MTK_PIN(
+		182, "GPIO182",
+		MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO182"),
+		MTK_FUNCTION(1, "DDR_PAD_RRESETB")
+	),
+
+	MTK_PIN(
+		183, "GPIO183",
+		MTK_EINT_FUNCTION(0, 182),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		184, "GPIO184",
+		MTK_EINT_FUNCTION(0, 183),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		185, "GPIO185",
+		MTK_EINT_FUNCTION(0, 184),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		186, "GPIO186",
+		MTK_EINT_FUNCTION(0, 185),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		187, "GPIO187",
+		MTK_EINT_FUNCTION(0, 186),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		188, "GPIO188",
+		MTK_EINT_FUNCTION(0, 187),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		189, "GPIO189",
+		MTK_EINT_FUNCTION(0, 188),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		190, "GPIO190",
+		MTK_EINT_FUNCTION(0, 189),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		191, "GPIO191",
+		MTK_EINT_FUNCTION(0, 190),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		192, "GPIO192",
+		MTK_EINT_FUNCTION(0, 191),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		193, "GPIO193",
+		MTK_EINT_FUNCTION(0, 192),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		194, "GPIO194",
+		MTK_EINT_FUNCTION(0, 193),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		195, "GPIO195",
+		MTK_EINT_FUNCTION(0, 194),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		196, "GPIO196",
+		MTK_EINT_FUNCTION(0, 195),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		197, "GPIO197",
+		MTK_EINT_FUNCTION(0, 196),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		198, "GPIO198",
+		MTK_EINT_FUNCTION(0, 197),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		199, "GPIO199",
+		MTK_EINT_FUNCTION(0, 198),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		200, "GPIO200",
+		MTK_EINT_FUNCTION(0, 199),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		201, "GPIO201",
+		MTK_EINT_FUNCTION(0, 200),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		202, "GPIO202",
+		MTK_EINT_FUNCTION(0, 201),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		203, "GPIO203",
+		MTK_EINT_FUNCTION(0, 202),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		204, "GPIO204",
+		MTK_EINT_FUNCTION(0, 203),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		205, "GPIO205",
+		MTK_EINT_FUNCTION(0, 204),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		206, "GPIO206",
+		MTK_EINT_FUNCTION(0, 205),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		207, "GPIO207",
+		MTK_EINT_FUNCTION(0, 206),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		208, "GPIO208",
+		MTK_EINT_FUNCTION(0, 207),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		209, "GPIO209",
+		MTK_EINT_FUNCTION(0, 208),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+	MTK_PIN(
+		210, "GPIO210",
+		MTK_EINT_FUNCTION(0, 209),
+		DRV_FIXED,
+		MTK_FUNCTION(0, NULL)
+	),
+
+};
+
+static struct mtk_eint_pin eint_pins_mt8189[] = {
+	MTK_EINT_PIN(0, 0, 0, 1),
+	MTK_EINT_PIN(1, 0, 1, 1),
+	MTK_EINT_PIN(2, 0, 2, 1),
+	MTK_EINT_PIN(3, 0, 3, 1),
+	MTK_EINT_PIN(4, 0, 4, 1),
+	MTK_EINT_PIN(5, 0, 5, 1),
+	MTK_EINT_PIN(6, 0, 6, 1),
+	MTK_EINT_PIN(7, 0, 7, 1),
+	MTK_EINT_PIN(8, 0, 8, 1),
+	MTK_EINT_PIN(9, 0, 9, 1),
+	MTK_EINT_PIN(10, 0, 10, 1),
+	MTK_EINT_PIN(11, 0, 11, 1),
+	MTK_EINT_PIN(12, 1, 0, 1),
+	MTK_EINT_PIN(13, 1, 1, 1),
+	MTK_EINT_PIN(14, 1, 2, 1),
+	MTK_EINT_PIN(15, 1, 3, 1),
+	MTK_EINT_PIN(16, 1, 4, 1),
+	MTK_EINT_PIN(17, 1, 5, 1),
+	MTK_EINT_PIN(18, 0, 12, 1),
+	MTK_EINT_PIN(19, 0, 13, 1),
+	MTK_EINT_PIN(20, 0, 14, 1),
+	MTK_EINT_PIN(21, 0, 15, 1),
+	MTK_EINT_PIN(22, 0, 16, 1),
+	MTK_EINT_PIN(23, 0, 17, 1),
+	MTK_EINT_PIN(24, 0, 18, 1),
+	MTK_EINT_PIN(25, 2, 0, 1),
+	MTK_EINT_PIN(26, 2, 1, 1),
+	MTK_EINT_PIN(27, 1, 6, 1),
+	MTK_EINT_PIN(28, 1, 7, 1),
+	MTK_EINT_PIN(29, 2, 2, 1),
+	MTK_EINT_PIN(30, 1, 8, 1),
+	MTK_EINT_PIN(31, 1, 9, 1),
+	MTK_EINT_PIN(32, 1, 10, 1),
+	MTK_EINT_PIN(33, 1, 11, 1),
+	MTK_EINT_PIN(34, 1, 12, 1),
+	MTK_EINT_PIN(35, 1, 13, 1),
+	MTK_EINT_PIN(36, 1, 14, 1),
+	MTK_EINT_PIN(37, 1, 15, 1),
+	MTK_EINT_PIN(38, 1, 16, 1),
+	MTK_EINT_PIN(39, 1, 17, 1),
+	MTK_EINT_PIN(40, 1, 18, 1),
+	MTK_EINT_PIN(41, 1, 19, 1),
+	MTK_EINT_PIN(42, 1, 20, 1),
+	MTK_EINT_PIN(43, 1, 21, 1),
+	MTK_EINT_PIN(44, 0, 19, 1),
+	MTK_EINT_PIN(45, 0, 20, 1),
+	MTK_EINT_PIN(46, 0, 21, 1),
+	MTK_EINT_PIN(47, 0, 22, 1),
+	MTK_EINT_PIN(48, 2, 3, 1),
+	MTK_EINT_PIN(49, 2, 4, 1),
+	MTK_EINT_PIN(50, 2, 5, 1),
+	MTK_EINT_PIN(51, 0, 23, 1),
+	MTK_EINT_PIN(52, 0, 24, 1),
+	MTK_EINT_PIN(53, 0, 25, 1),
+	MTK_EINT_PIN(54, 0, 26, 1),
+	MTK_EINT_PIN(55, 2, 6, 1),
+	MTK_EINT_PIN(56, 2, 7, 1),
+	MTK_EINT_PIN(57, 1, 22, 1),
+	MTK_EINT_PIN(58, 1, 23, 1),
+	MTK_EINT_PIN(59, 1, 24, 1),
+	MTK_EINT_PIN(60, 1, 25, 1),
+	MTK_EINT_PIN(61, 1, 26, 1),
+	MTK_EINT_PIN(62, 1, 27, 1),
+	MTK_EINT_PIN(63, 1, 28, 1),
+	MTK_EINT_PIN(64, 1, 29, 1),
+	MTK_EINT_PIN(65, 0, 27, 1),
+	MTK_EINT_PIN(66, 0, 28, 1),
+	MTK_EINT_PIN(67, 0, 29, 1),
+	MTK_EINT_PIN(68, 0, 30, 1),
+	MTK_EINT_PIN(69, 1, 30, 1),
+	MTK_EINT_PIN(70, 1, 31, 1),
+	MTK_EINT_PIN(71, 1, 32, 1),
+	MTK_EINT_PIN(72, 1, 33, 1),
+	MTK_EINT_PIN(73, 1, 34, 1),
+	MTK_EINT_PIN(74, 1, 35, 1),
+	MTK_EINT_PIN(75, 1, 36, 1),
+	MTK_EINT_PIN(76, 1, 37, 1),
+	MTK_EINT_PIN(77, 0, 31, 1),
+	MTK_EINT_PIN(78, 0, 32, 1),
+	MTK_EINT_PIN(79, 0, 33, 1),
+	MTK_EINT_PIN(80, 0, 34, 1),
+	MTK_EINT_PIN(81, 1, 38, 1),
+	MTK_EINT_PIN(82, 1, 39, 1),
+	MTK_EINT_PIN(83, 1, 40, 1),
+	MTK_EINT_PIN(84, 0, 35, 1),
+	MTK_EINT_PIN(85, 0, 36, 1),
+	MTK_EINT_PIN(86, 0, 37, 1),
+	MTK_EINT_PIN(87, 0, 38, 1),
+	MTK_EINT_PIN(88, 2, 8, 1),
+	MTK_EINT_PIN(89, 2, 9, 1),
+	MTK_EINT_PIN(90, 2, 10, 1),
+	MTK_EINT_PIN(91, 2, 11, 1),
+	MTK_EINT_PIN(92, 2, 12, 1),
+	MTK_EINT_PIN(93, 2, 13, 1),
+	MTK_EINT_PIN(94, 2, 14, 1),
+	MTK_EINT_PIN(95, 2, 15, 1),
+	MTK_EINT_PIN(96, 2, 16, 1),
+	MTK_EINT_PIN(97, 2, 17, 1),
+	MTK_EINT_PIN(98, 2, 18, 1),
+	MTK_EINT_PIN(99, 2, 19, 1),
+	MTK_EINT_PIN(100, 2, 20, 1),
+	MTK_EINT_PIN(101, 2, 21, 1),
+	MTK_EINT_PIN(102, 2, 22, 1),
+	MTK_EINT_PIN(103, 0, 39, 1),
+	MTK_EINT_PIN(104, 0, 40, 1),
+	MTK_EINT_PIN(105, 0, 41, 1),
+	MTK_EINT_PIN(106, 0, 42, 1),
+	MTK_EINT_PIN(107, 0, 43, 1),
+	MTK_EINT_PIN(108, 0, 44, 1),
+	MTK_EINT_PIN(109, 0, 45, 1),
+	MTK_EINT_PIN(110, 0, 46, 1),
+	MTK_EINT_PIN(111, 0, 47, 1),
+	MTK_EINT_PIN(112, 0, 48, 0),
+	MTK_EINT_PIN(113, 0, 49, 1),
+	MTK_EINT_PIN(114, 0, 50, 0),
+	MTK_EINT_PIN(115, 1, 41, 1),
+	MTK_EINT_PIN(116, 1, 42, 1),
+	MTK_EINT_PIN(117, 1, 43, 1),
+	MTK_EINT_PIN(118, 1, 44, 1),
+	MTK_EINT_PIN(119, 1, 45, 1),
+	MTK_EINT_PIN(120, 1, 46, 1),
+	MTK_EINT_PIN(121, 1, 47, 1),
+	MTK_EINT_PIN(122, 1, 48, 1),
+	MTK_EINT_PIN(123, 1, 49, 1),
+	MTK_EINT_PIN(124, 1, 50, 1),
+	MTK_EINT_PIN(125, 1, 51, 1),
+	MTK_EINT_PIN(126, 1, 52, 1),
+	MTK_EINT_PIN(127, 1, 53, 1),
+	MTK_EINT_PIN(128, 1, 54, 1),
+	MTK_EINT_PIN(129, 1, 55, 1),
+	MTK_EINT_PIN(130, 1, 56, 1),
+	MTK_EINT_PIN(131, 1, 57, 1),
+	MTK_EINT_PIN(132, 1, 58, 1),
+	MTK_EINT_PIN(133, 1, 59, 1),
+	MTK_EINT_PIN(134, 1, 60, 1),
+	MTK_EINT_PIN(135, 1, 61, 1),
+	MTK_EINT_PIN(136, 1, 62, 1),
+	MTK_EINT_PIN(137, 1, 63, 1),
+	MTK_EINT_PIN(138, 1, 64, 1),
+	MTK_EINT_PIN(139, 1, 65, 1),
+	MTK_EINT_PIN(140, 1, 66, 1),
+	MTK_EINT_PIN(141, 1, 67, 1),
+	MTK_EINT_PIN(142, 1, 68, 1),
+	MTK_EINT_PIN(143, 1, 69, 1),
+	MTK_EINT_PIN(144, 1, 70, 1),
+	MTK_EINT_PIN(145, 1, 71, 1),
+	MTK_EINT_PIN(146, 1, 72, 1),
+	MTK_EINT_PIN(147, 1, 73, 1),
+	MTK_EINT_PIN(148, 1, 74, 1),
+	MTK_EINT_PIN(149, 1, 75, 1),
+	MTK_EINT_PIN(150, 1, 76, 1),
+	MTK_EINT_PIN(151, 1, 77, 1),
+	MTK_EINT_PIN(152, 1, 78, 1),
+	MTK_EINT_PIN(153, 1, 79, 1),
+	MTK_EINT_PIN(154, 1, 80, 1),
+	MTK_EINT_PIN(155, 1, 81, 1),
+	MTK_EINT_PIN(156, 2, 23, 1),
+	MTK_EINT_PIN(157, 2, 24, 1),
+	MTK_EINT_PIN(158, 2, 25, 1),
+	MTK_EINT_PIN(159, 4, 0, 1),
+	MTK_EINT_PIN(160, 2, 26, 1),
+	MTK_EINT_PIN(161, 2, 27, 1),
+	MTK_EINT_PIN(162, 2, 28, 1),
+	MTK_EINT_PIN(163, 4, 1, 1),
+	MTK_EINT_PIN(164, 2, 29, 1),
+	MTK_EINT_PIN(165, 2, 30, 1),
+	MTK_EINT_PIN(166, 4, 2, 1),
+	MTK_EINT_PIN(167, 2, 31, 0),
+	MTK_EINT_PIN(168, 1, 82, 1),
+	MTK_EINT_PIN(169, 1, 83, 1),
+	MTK_EINT_PIN(170, 1, 84, 1),
+	MTK_EINT_PIN(171, 1, 85, 0),
+	MTK_EINT_PIN(172, 1, 86, 1),
+	MTK_EINT_PIN(173, 1, 87, 0),
+	MTK_EINT_PIN(174, 4, 3, 1),
+	MTK_EINT_PIN(175, 4, 4, 1),
+	MTK_EINT_PIN(176, 4, 5, 1),
+	MTK_EINT_PIN(177, 4, 6, 1),
+	MTK_EINT_PIN(178, 4, 7, 1),
+	MTK_EINT_PIN(179, 4, 8, 1),
+	MTK_EINT_PIN(180, 2, 32, 1),
+	MTK_EINT_PIN(181, 2, 33, 0),
+	MTK_EINT_PIN(182, 3, 0, 1),
+	MTK_EINT_PIN(183, 3, 1, 1),
+	MTK_EINT_PIN(184, 3, 2, 1),
+	MTK_EINT_PIN(185, 3, 3, 1),
+	MTK_EINT_PIN(186, 3, 4, 1),
+	MTK_EINT_PIN(187, 3, 5, 1),
+	MTK_EINT_PIN(188, 3, 6, 1),
+	MTK_EINT_PIN(189, 3, 7, 1),
+	MTK_EINT_PIN(190, 3, 8, 1),
+	MTK_EINT_PIN(191, 3, 9, 1),
+	MTK_EINT_PIN(192, 3, 10, 1),
+	MTK_EINT_PIN(193, 3, 11, 1),
+	MTK_EINT_PIN(194, 3, 12, 1),
+	MTK_EINT_PIN(195, 3, 13, 1),
+	MTK_EINT_PIN(196, 3, 14, 1),
+	MTK_EINT_PIN(197, 3, 15, 1),
+	MTK_EINT_PIN(198, 3, 16, 1),
+	MTK_EINT_PIN(199, 3, 17, 1),
+	MTK_EINT_PIN(200, 3, 18, 1),
+	MTK_EINT_PIN(201, 3, 19, 1),
+	MTK_EINT_PIN(202, 3, 20, 1),
+	MTK_EINT_PIN(203, 3, 21, 1),
+	MTK_EINT_PIN(204, 3, 22, 1),
+	MTK_EINT_PIN(205, 3, 23, 1),
+	MTK_EINT_PIN(206, 3, 24, 1),
+	MTK_EINT_PIN(207, 3, 25, 1),
+	MTK_EINT_PIN(208, 3, 26, 1),
+	MTK_EINT_PIN(209, 3, 27, 1)
+};
+
+#endif /* __PINCTRL_MTK_MT8189_H */
-- 
2.45.2



From naomi.chu at mediatek.com  Fri May 23 03:10:34 2025
From: naomi.chu at mediatek.com (naomi.chu at mediatek.com)
Date: Fri, 23 May 2025 18:10:34 +0800
Subject: [PATCH 1/1] ufs: core: add fatal errors check for LINERESET
Message-ID: <20250523101041.3615819-1-naomi.chu@mediatek.com>

From: Naomi Chu <naomi.chu at mediatek.com>

The current error handling flow directly checks the power mode after a
LINERESET occurs. However, if a PA_INIT_ERR occurs after the LINERESET,
checking the power mode may require waiting for three DME_GET timeouts,
which wastes 1.5 seconds.

To improve efficiency, when a LINERESET occurs, wait for PA_INIT to
complete and check for any other errors. After a LINERESET, PA_INIT
takes up to 75.4ms to complete. Therefore, a 100ms delay is added.

Signed-off-by: Naomi Chu <naomi.chu at mediatek.com>
---
 drivers/ufs/core/ufshcd.c | 45 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 7735421e3991..c7cc62429fc9 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -6359,6 +6359,46 @@ static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
 	       (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
 }
 
+static bool ufshcd_is_linereset_fatal(struct ufs_hba *hba)
+{
+	bool needs_reset = true;
+	unsigned long flags;
+	int err;
+
+	spin_lock_irqsave(hba->host->host_lock, flags);
+
+	if (ufshcd_is_saved_err_fatal(hba)) {
+		spin_unlock_irqrestore(hba->host->host_lock, flags);
+		goto out;
+	}
+
+	/*
+	 * Wait for 100ms to ensure the PA_INIT flow is complete,
+	 * and check for PA_INIT_ERR or other fatal errors.
+	 */
+	spin_unlock_irqrestore(hba->host->host_lock, flags);
+	msleep(100);
+	spin_lock_irqsave(hba->host->host_lock, flags);
+
+	if (ufshcd_is_saved_err_fatal(hba)) {
+		spin_unlock_irqrestore(hba->host->host_lock, flags);
+		goto out;
+	}
+
+	/*
+	 * PA_INIT_ERR on the device side will not trigger UIC
+	 * error interrupt.
+	 * Send NOP to check if the link is alive.
+	 */
+	spin_unlock_irqrestore(hba->host->host_lock, flags);
+	err = ufshcd_verify_dev_init(hba);
+	if (!err)
+		needs_reset = false;
+
+out:
+	return needs_reset;
+}
+
 void ufshcd_schedule_eh_work(struct ufs_hba *hba)
 {
 	lockdep_assert_held(hba->host->host_lock);
@@ -6655,6 +6695,11 @@ static void ufshcd_err_handler(struct work_struct *work)
 		if (!hba->saved_uic_err)
 			hba->saved_err &= ~UIC_ERROR;
 		spin_unlock_irqrestore(hba->host->host_lock, flags);
+		if (ufshcd_is_linereset_fatal(hba)) {
+			needs_reset = true;
+			spin_lock_irqsave(hba->host->host_lock, flags);
+			goto do_reset;
+		}
 		if (ufshcd_is_pwr_mode_restore_needed(hba))
 			needs_restore = true;
 		spin_lock_irqsave(hba->host->host_lock, flags);
-- 
2.45.2



From SkyLake.Huang at mediatek.com  Fri May 23 04:35:59 2025
From: SkyLake.Huang at mediatek.com (Sky Huang)
Date: Fri, 23 May 2025 19:35:59 +0800
Subject: [PATCH net-next 0/2] Add LED support/fix to MediaTek 2.5Gphy & Gphy
Message-ID: <20250523113601.3627781-1-SkyLake.Huang@mediatek.com>

From: Sky Huang <skylake.huang at mediatek.com>

This patchset adds LED support to MediaTek's built-in 2.5G phy, which
basically hooks the same helper function with built-in Gphy. Also, fix
LED behavior when blinking(delay_on & delay_off are both zero) is not set.

Sky Huang (2):
  net: phy: mtk-2p5ge: Add LED support for MT7988
  net: phy: mtk-ge-soc: Fix LED behavior if blinking is not set.

 drivers/net/phy/mediatek/mtk-2p5ge.c  | 104 ++++++++++++++++++++++++--
 drivers/net/phy/mediatek/mtk-ge-soc.c |   7 +-
 2 files changed, 103 insertions(+), 8 deletions(-)

-- 
2.45.2



From SkyLake.Huang at mediatek.com  Fri May 23 04:36:00 2025
From: SkyLake.Huang at mediatek.com (Sky Huang)
Date: Fri, 23 May 2025 19:36:00 +0800
Subject: [PATCH net-next 1/2] net: phy: mtk-2p5ge: Add LED support for MT7988
In-Reply-To: <20250523113601.3627781-1-SkyLake.Huang@mediatek.com>
References: <20250523113601.3627781-1-SkyLake.Huang@mediatek.com>
Message-ID: <20250523113601.3627781-2-SkyLake.Huang@mediatek.com>

From: Sky Huang <skylake.huang at mediatek.com>

Add LED support for MT7988's built-in 2.5Gphy. LED hardware has almost
the same design with MT7981's/MT7988's built-in GbE. So hook the same
helper function here.

Before mtk_phy_leds_state_init(), set correct default values of LED0
and LED1.

Signed-off-by: Sky Huang <skylake.huang at mediatek.com>
---
 drivers/net/phy/mediatek/mtk-2p5ge.c | 104 +++++++++++++++++++++++++--
 1 file changed, 98 insertions(+), 6 deletions(-)

diff --git a/drivers/net/phy/mediatek/mtk-2p5ge.c b/drivers/net/phy/mediatek/mtk-2p5ge.c
index e147eab52..de8a41a18 100644
--- a/drivers/net/phy/mediatek/mtk-2p5ge.c
+++ b/drivers/net/phy/mediatek/mtk-2p5ge.c
@@ -249,8 +249,80 @@ static int mt798x_2p5ge_phy_get_rate_matching(struct phy_device *phydev,
 	return RATE_MATCH_PAUSE;
 }
 
+static const unsigned long supported_triggers =
+	BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
+	BIT(TRIGGER_NETDEV_LINK)        |
+	BIT(TRIGGER_NETDEV_LINK_10)     |
+	BIT(TRIGGER_NETDEV_LINK_100)    |
+	BIT(TRIGGER_NETDEV_LINK_1000)   |
+	BIT(TRIGGER_NETDEV_LINK_2500)   |
+	BIT(TRIGGER_NETDEV_RX)          |
+	BIT(TRIGGER_NETDEV_TX);
+
+static int mt798x_2p5ge_phy_led_blink_set(struct phy_device *phydev, u8 index,
+					  unsigned long *delay_on,
+					  unsigned long *delay_off)
+{
+	bool blinking = false;
+	int err = 0;
+
+	err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking);
+	if (err < 0)
+		return err;
+
+	err = mtk_phy_hw_led_blink_set(phydev, index, blinking);
+	if (err)
+		return err;
+
+	if (blinking)
+		mtk_phy_hw_led_on_set(phydev, index, MTK_2P5GPHY_LED_ON_MASK,
+				      false);
+
+	return 0;
+}
+
+static int mt798x_2p5ge_phy_led_brightness_set(struct phy_device *phydev,
+					       u8 index,
+					       enum led_brightness value)
+{
+	int err;
+
+	err = mtk_phy_hw_led_blink_set(phydev, index, false);
+	if (err)
+		return err;
+
+	return mtk_phy_hw_led_on_set(phydev, index, MTK_2P5GPHY_LED_ON_MASK,
+				     (value != LED_OFF));
+}
+
+static int mt798x_2p5ge_phy_led_hw_is_supported(struct phy_device *phydev,
+						u8 index, unsigned long rules)
+{
+	return mtk_phy_led_hw_is_supported(phydev, index, rules,
+					   supported_triggers);
+}
+
+static int mt798x_2p5ge_phy_led_hw_control_get(struct phy_device *phydev,
+					       u8 index, unsigned long *rules)
+{
+	return mtk_phy_led_hw_ctrl_get(phydev, index, rules,
+				       MTK_2P5GPHY_LED_ON_SET,
+				       MTK_2P5GPHY_LED_RX_BLINK_SET,
+				       MTK_2P5GPHY_LED_TX_BLINK_SET);
+};
+
+static int mt798x_2p5ge_phy_led_hw_control_set(struct phy_device *phydev,
+					       u8 index, unsigned long rules)
+{
+	return mtk_phy_led_hw_ctrl_set(phydev, index, rules,
+				       MTK_2P5GPHY_LED_ON_SET,
+				       MTK_2P5GPHY_LED_RX_BLINK_SET,
+				       MTK_2P5GPHY_LED_TX_BLINK_SET);
+};
+
 static int mt798x_2p5ge_phy_probe(struct phy_device *phydev)
 {
+	struct mtk_socphy_priv *priv;
 	struct pinctrl *pinctrl;
 	int ret;
 
@@ -273,19 +345,34 @@ static int mt798x_2p5ge_phy_probe(struct phy_device *phydev)
 	if (ret < 0)
 		return ret;
 
-	/* Setup LED */
+	/* Setup LED. On default, LED0 is on/off when link is up/down. As for
+	 * LED1, it blinks as tx/rx transmission takes place.
+	 */
 	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
-			 MTK_PHY_LED_ON_POLARITY | MTK_PHY_LED_ON_LINK10 |
-			 MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK1000 |
-			 MTK_PHY_LED_ON_LINK2500);
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
-			 MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX);
+			 MTK_PHY_LED_ON_POLARITY | MTK_2P5GPHY_LED_ON_SET);
+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL,
+			   MTK_2P5GPHY_LED_TX_BLINK_SET |
+			   MTK_2P5GPHY_LED_RX_BLINK_SET);
+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
+			   MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX |
+			   MTK_2P5GPHY_LED_ON_SET);
+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL,
+			 MTK_2P5GPHY_LED_TX_BLINK_SET |
+			 MTK_2P5GPHY_LED_RX_BLINK_SET);
 
 	/* Switch pinctrl after setting polarity to avoid bogus blinking */
 	pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
 	if (IS_ERR(pinctrl))
 		dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
 
+	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv),
+			    GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	phydev->priv = priv;
+
+	mtk_phy_leds_state_init(phydev);
+
 	return 0;
 }
 
@@ -303,6 +390,11 @@ static struct phy_driver mtk_2p5gephy_driver[] = {
 		.resume = genphy_resume,
 		.read_page = mtk_phy_read_page,
 		.write_page = mtk_phy_write_page,
+		.led_blink_set = mt798x_2p5ge_phy_led_blink_set,
+		.led_brightness_set = mt798x_2p5ge_phy_led_brightness_set,
+		.led_hw_is_supported = mt798x_2p5ge_phy_led_hw_is_supported,
+		.led_hw_control_get = mt798x_2p5ge_phy_led_hw_control_get,
+		.led_hw_control_set = mt798x_2p5ge_phy_led_hw_control_set,
 	},
 };
 
-- 
2.45.2



From SkyLake.Huang at mediatek.com  Fri May 23 04:36:01 2025
From: SkyLake.Huang at mediatek.com (Sky Huang)
Date: Fri, 23 May 2025 19:36:01 +0800
Subject: [PATCH net-next 2/2] net: phy: mtk-ge-soc: Fix LED behavior if blinking is not set.
In-Reply-To: <20250523113601.3627781-1-SkyLake.Huang@mediatek.com>
References: <20250523113601.3627781-1-SkyLake.Huang@mediatek.com>
Message-ID: <20250523113601.3627781-3-SkyLake.Huang@mediatek.com>

From: Sky Huang <skylake.huang at mediatek.com>

If delay_on==0 and delay_off==0 are passed to
mt798x_2p5ge_phy_led_blink_set() and mtk_phy_led_num_dly_cfg(),
blinking is actually not set. So don't clean "LED on" status under
this circumstance.

Signed-off-by: Sky Huang <skylake.huang at mediatek.com>
---
 drivers/net/phy/mediatek/mtk-ge-soc.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediatek/mtk-ge-soc.c
index cd0968478..15dcf2046 100644
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -1228,8 +1228,11 @@ static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
 	if (err)
 		return err;
 
-	return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK,
-				     false);
+	if (blinking)
+		mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK,
+				      false);
+
+	return 0;
 }
 
 static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
-- 
2.45.2



From alpernebiyasak at gmail.com  Fri May 23 05:58:10 2025
From: alpernebiyasak at gmail.com (Alper Nebi Yasak)
Date: Fri, 23 May 2025 15:58:10 +0300
Subject: mt6358-regulator does not probe automatically on MT8183 and
 MT8186 Chromebooks
In-Reply-To: <dc21b01f-e89f-42f5-b6d1-f6a00a524235@collabora.com>
References: <f3c6ea1d-da0f-40cc-ba70-7cabb5c3189f@gmail.com>
 <dc21b01f-e89f-42f5-b6d1-f6a00a524235@collabora.com>
Message-ID: <8f9ae0f1-130f-482c-b0a2-d5a403639099@gmail.com>

Hello again,

On 2024-12-23 14:21 +03:00, AngeloGioacchino Del Regno wrote:
> Il 21/12/24 16:38, Alper Nebi Yasak ha scritto:
>> Hello,
>>
>> I'm left with one small problem trying to boot Debian on MT8183 and
>> MT8186 Chromebooks (Cozmo and Magneton respectively). I see a lot of
>> probe deferrals and get dropped into an initramfs shell. All of them
>> get resolved if I run `modprobe mt6358-regulator`, after which I can
>> exit the initramfs shell to continue booting.
>>
>> It has been happening for a long time, still unsolved as of v6.12 and
>> next-20241220. I am using `softdep mediatek-drm pre: mt6358-regulator`
>> and so on in /etc/modprobe.d/ to trigger it to probe, as a workaround.
>>
>> But I would like if it was solved upstream so distro kernels can work
>> "out of the box". Any ideas why isn't it probing automatically, and how
>> to make it so it works?
>>
>> More info from a serial connection below (on mt8183-kukui-jacuzzi-cozmo):
>>
> 
> It's a bit odd, thanks for reporting.
> 
> I'll check that next year........ (which is really in 2 weeks anyway, but it's fun
> to say)

I couldn't manage to ping you for this, let alone look further into it
until now. It has been a while, I assume it's still not fixed, do you
need me to test again?

> Btw, that softdep is obviously not right, but I think I shouldn't even have pointed
> that out; still, better safe than sorry, anyway.

Yep, that was just a debug trick I use. My current workaround is using
CONFIG_MFD_MT6397=y and CONFIG_REGULATOR_MT6358=y like everyone else (as
in the defconfig).


On 2024-12-23 19:00 +03:00, Mark Brown wrote:
> As indicated in that thread the MFD should register the regulator
> function driver with the name "mt6358-regulator" used by the driver,
> then the existing MODULE_DEVICE_TABLE() will DTRT.

As far as I can see, mt6397-core.c is doing a devm_mfd_add_devices()
call with the necessary data, roughly paraphrasing:

> static const struct mfd_cell mt6358_devs[] = {
>  [...]
> 	}, {
> 		.name = "mt6358-regulator",
> 		.of_compatible = "mediatek,mt6358-regulator"
> 	}, {
>  [...]
> };
> 
> static const struct chip_data mt6358_core = {
> 	.cid_addr = MT6358_SWCID,
> 	.cid_shift = 8,
> 	.cells = mt6358_devs,
> 	.cell_size = ARRAY_SIZE(mt6358_devs),
> 	.irq_init = mt6358_irq_init,
> };
> 
> static int mt6397_probe(struct platform_device *pdev)
> {
> 	int ret;
> 	unsigned int id = 0;
> 	struct mt6397_chip *pmic;
> 	const struct chip_data *pmic_core;
>  [...]
> 	pmic_core = of_device_get_match_data(&pdev->dev);
> 	if (!pmic_core)
> 		return -ENODEV;
>  [...]
> 	ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE,
> 				   pmic_core->cells, pmic_core->cell_size,
> 				   NULL, 0, pmic->irq_domain);
>  [...]
> 	return ret;
> }
> 
> static const struct of_device_id mt6397_of_match[] = {
>  [...]
> 	}, {
> 		.compatible = "mediatek,mt6358",
> 		.data = &mt6358_core,
> 	}, {
>  [...]
> };
> MODULE_DEVICE_TABLE(of, mt6397_of_match);
> 
> static const struct platform_device_id mt6397_id[] = {
> 	{ "mt6397", 0 },
> 	{ },
> };
> MODULE_DEVICE_TABLE(platform, mt6397_id);
> 
> static struct platform_driver mt6397_driver = {
> 	.probe = mt6397_probe,
> 	.driver = {
> 		.name = "mt6397",
> 		.of_match_table = mt6397_of_match,
> 	},
> 	.id_table = mt6397_id,
> };
> 
> module_platform_driver(mt6397_driver);

It has more things like "mt6359-auxadc" and "mtk-pmic-keys", that also
list compatibles in the non-mfd driver's MODULE_DEVICE_TABLE(of, ...).
See `git grep -C5 '\"mediatek,mt63..\+-' -- drivers/`.

Maybe if the target driver isn't available by the time MFD registers it,
it doesn't try again later? And so people have added the compatibles to
subdevices to let them get another chance to probe?


From luca.ceresoli at bootlin.com  Fri May 23 06:23:04 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Fri, 23 May 2025 15:23:04 +0200
Subject: [PATCH v3 00/22] drm: convert all bridges to
 devm_drm_bridge_alloc()
In-Reply-To: <CAAQKjZPX3iQgNhEydDZXMyC9BRuep7kL-XYEsjnkCxSt_1UsQg@mail.gmail.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
	<20250521162216.79dd3290@booty>
	<CAAQKjZPX3iQgNhEydDZXMyC9BRuep7kL-XYEsjnkCxSt_1UsQg@mail.gmail.com>
Message-ID: <20250523152304.5c66e195@booty>

Hello Inki,

On Fri, 23 May 2025 00:11:24 +0900
Inki Dae <daeinki at gmail.com> wrote:

> Hello Luca Ceresoli,
> 
> 2025? 5? 21? (?) ?? 11:23, Luca Ceresoli <luca.ceresoli at bootlin.com>?? ??:
> >
> > Hello Maxime, Shawn, Liu, all,
> >
> > On Fri, 09 May 2025 15:53:26 +0200
> > Luca Ceresoli <luca.ceresoli at bootlin.com> wrote:
> >  
> > > devm_drm_bridge_alloc() [0] is the new API to allocate and initialize a DRM
> > > bridge, and the only one supported from now on. It is the first milestone
> > > towards removal of bridges from a still existing DRM pipeline without
> > > use-after-free.  
> >
> > I applied on drm-misc-next patches 3-17,20-21 as they match all the
> > criteria:
> >  - At least a Acked-by (or R-by maintainers)
> >  - patch is for drm-misc
> >
> > Being my very first commits to drm-misc, I tried to be careful, and
> > double checked all the patches with Louis (thanks!).
> >
> > Here are the pending questions and plan for the remaining patches.
> >  
> > >       Revert "drm/exynos: mic: convert to devm_drm_bridge_alloc() API"  
> >
> > This reverts the commit applied my mistake:
> > https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/91c5c7b5bb2dd09b43b025bce6d790d3c79f4518
> >
> > Neither the  original patch nor the revert has been reviewed/acked.
> >
> > As the commit was a mistake, I'm applying the revert by the end of this
> > week (i.e. on Friday) unless there are better instructions.  
> 
> Really sorry for late. I was made aware of it later through a
> colleague's remark. There is no need to proceed with the revert.
> Acked-by : Inki Dae <inki.dae at samsung.com>

Thanks for the feedback. As agreed with Maxime and approved by you, I'm
leaving the commit as is, without reverting and reapplying. Your
Acked-by is in the records anyway, so somehow reachable in case of need.

Luca

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


From conor at kernel.org  Fri May 23 08:34:35 2025
From: conor at kernel.org (Conor Dooley)
Date: Fri, 23 May 2025 16:34:35 +0100
Subject: [net-next PATCH 1/3] dt-bindings: net: dsa: mediatek,mt7530: Add
 airoha,an7583-switch
In-Reply-To: <20250522165313.6411-2-ansuelsmth@gmail.com>
References: <20250522165313.6411-1-ansuelsmth@gmail.com>
 <20250522165313.6411-2-ansuelsmth@gmail.com>
Message-ID: <20250523-poster-suffix-8a15978bc704@spud>

On Thu, May 22, 2025 at 06:53:09PM +0200, Christian Marangi wrote:
> Add airoha,an7583-switch additional compatible to the mt7530 DSA Switch
> Family. This is an exact match of the airoha,en7581-switch (based on
> mt7988-switch) with the additional requirement of tweak on the
> GEPHY_CONN_CFG registers to make the internal PHY actually work.
> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>

Acked-by: Conor Dooley <conor.dooley at microchip.com>
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From andrew at lunn.ch  Fri May 23 08:58:20 2025
From: andrew at lunn.ch (Andrew Lunn)
Date: Fri, 23 May 2025 17:58:20 +0200
Subject: [net-next PATCH 3/3] net: phy: mediatek: Add Airoha AN7583 PHY
 support
In-Reply-To: <20250522165313.6411-4-ansuelsmth@gmail.com>
References: <20250522165313.6411-1-ansuelsmth@gmail.com>
 <20250522165313.6411-4-ansuelsmth@gmail.com>
Message-ID: <879d0fed-37e7-43b0-9dab-4a20b65c6d75@lunn.ch>

On Thu, May 22, 2025 at 06:53:11PM +0200, Christian Marangi wrote:
> Add Airoha AN7583 PHY support based on Airoha AN7581 with the small
> difference that BMCR_PDOWN is enabled by default and needs to be cleared
> to make the internal PHY correctly work.
> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>

Reviewed-by: Andrew Lunn <andrew at lunn.ch>

    Andrew


From andrew at lunn.ch  Fri May 23 09:00:20 2025
From: andrew at lunn.ch (Andrew Lunn)
Date: Fri, 23 May 2025 18:00:20 +0200
Subject: [net-next PATCH 2/3] net: dsa: mt7530: Add AN7583 support
In-Reply-To: <20250522165313.6411-3-ansuelsmth@gmail.com>
References: <20250522165313.6411-1-ansuelsmth@gmail.com>
 <20250522165313.6411-3-ansuelsmth@gmail.com>
Message-ID: <a4366913-2368-4d59-b3c0-4c534c9b2c4d@lunn.ch>

On Thu, May 22, 2025 at 06:53:10PM +0200, Christian Marangi wrote:
> Add Airoha AN7583 Switch support. This is based on Airoha EN7581 that is
> based on Mediatek MT7988 Switch.
> 
> Airoha AN7583 require additional tweak to the GEPHY_CONN_CFG register to
> make the internal PHY work.
> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>

Reviewed-by: Andrew Lunn <andrew at lunn.ch>

    Andrew


From andrew at lunn.ch  Fri May 23 09:02:02 2025
From: andrew at lunn.ch (Andrew Lunn)
Date: Fri, 23 May 2025 18:02:02 +0200
Subject: [PATCH net-next 1/2] net: phy: mtk-2p5ge: Add LED support for
 MT7988
In-Reply-To: <20250523113601.3627781-2-SkyLake.Huang@mediatek.com>
References: <20250523113601.3627781-1-SkyLake.Huang@mediatek.com>
 <20250523113601.3627781-2-SkyLake.Huang@mediatek.com>
Message-ID: <afb80927-d921-44d7-8a32-f109e5ec5143@lunn.ch>

On Fri, May 23, 2025 at 07:36:00PM +0800, Sky Huang wrote:
> From: Sky Huang <skylake.huang at mediatek.com>
> 
> Add LED support for MT7988's built-in 2.5Gphy. LED hardware has almost
> the same design with MT7981's/MT7988's built-in GbE. So hook the same
> helper function here.
> 
> Before mtk_phy_leds_state_init(), set correct default values of LED0
> and LED1.
> 
> Signed-off-by: Sky Huang <skylake.huang at mediatek.com>

Reviewed-by: Andrew Lunn <andrew at lunn.ch>

    Andrew


From dan.carpenter at linaro.org  Fri May 23 09:06:54 2025
From: dan.carpenter at linaro.org (Dan Carpenter)
Date: Fri, 23 May 2025 19:06:54 +0300
Subject: [PATCH] dmaengine: mediatek: Re-enable IRQs in mtk_cqdma_tx_status()
Message-ID: <aDCdHh-G2ShU6uid@stanley.mountain>

This code calls spin_lock_irqsave() twice but obviously we can't store
two sets of flags in the same "flags" variable.  The result is that we
never re-enable IRQs in mtk_cqdma_tx_status().

Fixes: 157ae5ffd76a ("dmaengine: mediatek: Fix a possible deadlock error in mtk_cqdma_tx_status()")
Signed-off-by: Dan Carpenter <dan.carpenter at linaro.org>
---
 drivers/dma/mediatek/mtk-cqdma.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index 47c8adfdc155..9f0c41ca7770 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -449,9 +449,9 @@ static enum dma_status mtk_cqdma_tx_status(struct dma_chan *c,
 		return ret;
 
 	spin_lock_irqsave(&cvc->pc->lock, flags);
-	spin_lock_irqsave(&cvc->vc.lock, flags);
+	spin_lock(&cvc->vc.lock);
 	vd = mtk_cqdma_find_active_desc(c, cookie);
-	spin_unlock_irqrestore(&cvc->vc.lock, flags);
+	spin_unlock(&cvc->vc.lock);
 	spin_unlock_irqrestore(&cvc->pc->lock, flags);
 
 	if (vd) {
-- 
2.47.2



From andrew at lunn.ch  Fri May 23 09:07:49 2025
From: andrew at lunn.ch (Andrew Lunn)
Date: Fri, 23 May 2025 18:07:49 +0200
Subject: [PATCH net-next 2/2] net: phy: mtk-ge-soc: Fix LED behavior if
 blinking is not set.
In-Reply-To: <20250523113601.3627781-3-SkyLake.Huang@mediatek.com>
References: <20250523113601.3627781-1-SkyLake.Huang@mediatek.com>
 <20250523113601.3627781-3-SkyLake.Huang@mediatek.com>
Message-ID: <39d5d8af-0bac-4b91-85df-4e04a5835f53@lunn.ch>

On Fri, May 23, 2025 at 07:36:01PM +0800, Sky Huang wrote:
> From: Sky Huang <skylake.huang at mediatek.com>
> 
> If delay_on==0 and delay_off==0 are passed to
> mt798x_2p5ge_phy_led_blink_set() and mtk_phy_led_num_dly_cfg(),
> blinking is actually not set. So don't clean "LED on" status under
> this circumstance.

Actually, i think mtk_phy_led_num_dly_cfg() is wrong.

https://docs.kernel.org/leds/leds-class.html#hardware-accelerated-blink-of-leds

   The blink_set() function should choose a user friendly blinking
   value if it is called with *delay_on==0 && *delay_off==0
   parameters. In this case the driver should give back the chosen
   value through delay_on and delay_off parameters to the leds
   subsystem.

That is not what mtk_phy_led_num_dly_cfg() does.

    Andrew

---
pw-bot: cr


From bvanassche at acm.org  Fri May 23 09:14:17 2025
From: bvanassche at acm.org (Bart Van Assche)
Date: Fri, 23 May 2025 09:14:17 -0700
Subject: [PATCH 1/1] ufs: core: add fatal errors check for LINERESET
In-Reply-To: <20250523101041.3615819-1-naomi.chu@mediatek.com>
References: <20250523101041.3615819-1-naomi.chu@mediatek.com>
Message-ID: <c2608cd6-8c77-48f2-bc50-2ff087b0d48f@acm.org>

On 5/23/25 3:10 AM, naomi.chu at mediatek.com wrote:
> +static bool ufshcd_is_linereset_fatal(struct ufs_hba *hba)
> +{
> +	bool needs_reset = true;
> +	unsigned long flags;
> +	int err;
> +
> +	spin_lock_irqsave(hba->host->host_lock, flags);
> +
> +	if (ufshcd_is_saved_err_fatal(hba)) {
> +		spin_unlock_irqrestore(hba->host->host_lock, flags);
> +		goto out;
> +	}
> +
> +	/*
> +	 * Wait for 100ms to ensure the PA_INIT flow is complete,
> +	 * and check for PA_INIT_ERR or other fatal errors.
> +	 */
> +	spin_unlock_irqrestore(hba->host->host_lock, flags);

Please use scoped_guard(spinlock_irqsave) instead of calling 
spin_lock_irqsave() and spin_unlock_irqrestore() directly.

 > +	msleep(100);

Can ufshcd_is_linereset_fatal() be called from IRQ context? If so,
calling msleep() is not allowed. If it can't be called from IRQ
context, saving and restoring 'flags' is not necessary.

Bart.


From lorenzo at kernel.org  Fri May 23 12:23:29 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Fri, 23 May 2025 21:23:29 +0200
Subject: [PATCH net-next 0/2] net: airoha: Enable hw acceleration for PPPoE
 traffic
Message-ID: <20250523-b4-airoha-flowtable-pppoe-v1-0-8584401568e0@kernel.org>

Initialize PPE UPDMEM source-mac table used during IPv6 traffic hw
acceleration.
Introduce flowtable hw acceleration for PPPoE traffic.

---
Lorenzo Bianconi (2):
      net: airoha: Initialize PPE UPDMEM source-mac table
      net: airoha: Add PPPoE offload support

 drivers/net/ethernet/airoha/airoha_eth.c  |  2 ++
 drivers/net/ethernet/airoha/airoha_eth.h  |  1 +
 drivers/net/ethernet/airoha/airoha_ppe.c  | 60 ++++++++++++++++++++++++-------
 drivers/net/ethernet/airoha/airoha_regs.h | 10 ++++++
 4 files changed, 60 insertions(+), 13 deletions(-)
---
base-commit: ea15e046263b19e91ffd827645ae5dfa44ebd044
change-id: 20250413-b4-airoha-flowtable-pppoe-2c199f5059ea

Best regards,
-- 
Lorenzo Bianconi <lorenzo at kernel.org>



From lorenzo at kernel.org  Fri May 23 12:23:30 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Fri, 23 May 2025 21:23:30 +0200
Subject: [PATCH net-next 1/2] net: airoha: Initialize PPE UPDMEM source-mac
 table
In-Reply-To: <20250523-b4-airoha-flowtable-pppoe-v1-0-8584401568e0@kernel.org>
References: <20250523-b4-airoha-flowtable-pppoe-v1-0-8584401568e0@kernel.org>
Message-ID: <20250523-b4-airoha-flowtable-pppoe-v1-1-8584401568e0@kernel.org>

UPDMEM source-mac table is a key-value map used to store devices mac
addresses according to the port identifier. UPDMEM source mac table is
used during IPv6 traffic hw acceleration since PPE entries, for space
constraints, do not contain the full source mac address but just the
identifier in the UPDMEM source-mac table.

Fixes: 00a7678310fe ("net: airoha: Introduce flowtable offload support")
Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 drivers/net/ethernet/airoha/airoha_eth.c  |  2 ++
 drivers/net/ethernet/airoha/airoha_eth.h  |  1 +
 drivers/net/ethernet/airoha/airoha_ppe.c  | 25 ++++++++++++++++++++++++-
 drivers/net/ethernet/airoha/airoha_regs.h | 10 ++++++++++
 4 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 0d627e511266d94e079e8a87d2f812fb14b4ad07..e4c67c7bbf215d448640f978cd0d9d50abd73644 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -92,6 +92,8 @@ static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
 	val = (addr[3] << 16) | (addr[4] << 8) | addr[5];
 	airoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), val);
 	airoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), val);
+
+	airoha_ppe_init_upd_mem(port);
 }
 
 static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr,
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index 531a3c49c1562a986111a1ce1c215c8751c16e09..a951246c0171e14497b510d3029fc0a7f891efe6 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -611,6 +611,7 @@ void airoha_ppe_check_skb(struct airoha_ppe *ppe, struct sk_buff *skb,
 int airoha_ppe_setup_tc_block_cb(struct net_device *dev, void *type_data);
 int airoha_ppe_init(struct airoha_eth *eth);
 void airoha_ppe_deinit(struct airoha_eth *eth);
+void airoha_ppe_init_upd_mem(struct airoha_gdm_port *port);
 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe,
 						  u32 hash);
 void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash,
diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
index 2d273937f19cf304ab4b821241fdc3ea93604f0e..1d5a04eb82a6645e2b6a22ff4e694275ef1727d8 100644
--- a/drivers/net/ethernet/airoha/airoha_ppe.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe.c
@@ -223,6 +223,7 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
 	int dsa_port = airoha_get_dsa_port(&dev);
 	struct airoha_foe_mac_info_common *l2;
 	u32 qdata, ports_pad, val;
+	u8 smac_id = 0xf;
 
 	memset(hwe, 0, sizeof(*hwe));
 
@@ -251,6 +252,7 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
 		else
 			pse_port = 2; /* uplink relies on GDM2 loopback */
 		val |= FIELD_PREP(AIROHA_FOE_IB2_PSE_PORT, pse_port);
+		smac_id = port->id;
 	}
 
 	if (is_multicast_ether_addr(data->eth.h_dest))
@@ -285,7 +287,7 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
 		hwe->ipv4.l2.src_mac_lo =
 			get_unaligned_be16(data->eth.h_source + 4);
 	} else {
-		l2->src_mac_hi = FIELD_PREP(AIROHA_FOE_MAC_SMAC_ID, 0xf);
+		l2->src_mac_hi = FIELD_PREP(AIROHA_FOE_MAC_SMAC_ID, smac_id);
 	}
 
 	if (data->vlan.num) {
@@ -1232,6 +1234,27 @@ void airoha_ppe_check_skb(struct airoha_ppe *ppe, struct sk_buff *skb,
 	airoha_ppe_foe_insert_entry(ppe, skb, hash);
 }
 
+void airoha_ppe_init_upd_mem(struct airoha_gdm_port *port)
+{
+	struct airoha_eth *eth = port->qdma->eth;
+	struct net_device *dev = port->dev;
+	const u8 *addr = dev->dev_addr;
+	u32 val;
+
+	val = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
+	airoha_fe_wr(eth, REG_UPDMEM_DATA(0), val);
+	airoha_fe_wr(eth, REG_UPDMEM_CTRL(0),
+		     FIELD_PREP(PPE_UPDMEM_ADDR_MASK, port->id) |
+		     PPE_UPDMEM_WR_MASK | PPE_UPDMEM_REQ_MASK);
+
+	val = (addr[0] << 8) | addr[1];
+	airoha_fe_wr(eth, REG_UPDMEM_DATA(0), val);
+	airoha_fe_wr(eth, REG_UPDMEM_CTRL(0),
+		     FIELD_PREP(PPE_UPDMEM_ADDR_MASK, port->id) |
+		     FIELD_PREP(PPE_UPDMEM_OFFSET_MASK, 1) |
+		     PPE_UPDMEM_WR_MASK | PPE_UPDMEM_REQ_MASK);
+}
+
 int airoha_ppe_init(struct airoha_eth *eth)
 {
 	struct airoha_ppe *ppe;
diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
index d931530fc96fb00ada36a6ad37fa295865a6f0a8..04187eb40ec674ec5a4ccfc968bb4bd579a53095 100644
--- a/drivers/net/ethernet/airoha/airoha_regs.h
+++ b/drivers/net/ethernet/airoha/airoha_regs.h
@@ -313,6 +313,16 @@
 #define REG_PPE_RAM_BASE(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x320)
 #define REG_PPE_RAM_ENTRY(_m, _n)		(REG_PPE_RAM_BASE(_m) + ((_n) << 2))
 
+#define REG_UPDMEM_CTRL(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x370)
+#define PPE_UPDMEM_ACK_MASK			BIT(31)
+#define PPE_UPDMEM_ADDR_MASK			GENMASK(11, 8)
+#define PPE_UPDMEM_OFFSET_MASK			GENMASK(7, 4)
+#define PPE_UPDMEM_SEL_MASK			GENMASK(3, 2)
+#define PPE_UPDMEM_WR_MASK			BIT(1)
+#define PPE_UPDMEM_REQ_MASK			BIT(0)
+
+#define REG_UPDMEM_DATA(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x374)
+
 #define REG_FE_GDM_TX_OK_PKT_CNT_H(_n)		(GDM_BASE(_n) + 0x280)
 #define REG_FE_GDM_TX_OK_BYTE_CNT_H(_n)		(GDM_BASE(_n) + 0x284)
 #define REG_FE_GDM_TX_ETH_PKT_CNT_H(_n)		(GDM_BASE(_n) + 0x288)

-- 
2.49.0



From lorenzo at kernel.org  Fri May 23 12:23:31 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Fri, 23 May 2025 21:23:31 +0200
Subject: [PATCH net-next 2/2] net: airoha: Add PPPoE offload support
In-Reply-To: <20250523-b4-airoha-flowtable-pppoe-v1-0-8584401568e0@kernel.org>
References: <20250523-b4-airoha-flowtable-pppoe-v1-0-8584401568e0@kernel.org>
Message-ID: <20250523-b4-airoha-flowtable-pppoe-v1-2-8584401568e0@kernel.org>

Introduce flowtable hw acceleration for PPPoE traffic.

Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 drivers/net/ethernet/airoha/airoha_ppe.c | 37 +++++++++++++++++++++-----------
 1 file changed, 24 insertions(+), 13 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
index 1d5a04eb82a6645e2b6a22ff4e694275ef1727d8..6571511cf4bb8c341b03b94ba8e444f558cbf125 100644
--- a/drivers/net/ethernet/airoha/airoha_ppe.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe.c
@@ -232,6 +232,7 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
 	      FIELD_PREP(AIROHA_FOE_IB1_BIND_UDP, l4proto == IPPROTO_UDP) |
 	      FIELD_PREP(AIROHA_FOE_IB1_BIND_VLAN_LAYER, data->vlan.num) |
 	      FIELD_PREP(AIROHA_FOE_IB1_BIND_VPM, data->vlan.num) |
+	      FIELD_PREP(AIROHA_FOE_IB1_BIND_PPPOE, data->pppoe.num) |
 	      AIROHA_FOE_IB1_BIND_TTL;
 	hwe->ib1 = val;
 
@@ -274,33 +275,38 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
 		hwe->ipv6.data = qdata;
 		hwe->ipv6.ib2 = val;
 		l2 = &hwe->ipv6.l2;
+		l2->etype = ETH_P_IPV6;
 	} else {
 		hwe->ipv4.data = qdata;
 		hwe->ipv4.ib2 = val;
 		l2 = &hwe->ipv4.l2.common;
+		l2->etype = ETH_P_IP;
 	}
 
 	l2->dest_mac_hi = get_unaligned_be32(data->eth.h_dest);
 	l2->dest_mac_lo = get_unaligned_be16(data->eth.h_dest + 4);
 	if (type <= PPE_PKT_TYPE_IPV4_DSLITE) {
+		struct airoha_foe_mac_info *mac_info;
+
 		l2->src_mac_hi = get_unaligned_be32(data->eth.h_source);
 		hwe->ipv4.l2.src_mac_lo =
 			get_unaligned_be16(data->eth.h_source + 4);
-	} else {
-		l2->src_mac_hi = FIELD_PREP(AIROHA_FOE_MAC_SMAC_ID, smac_id);
-	}
 
-	if (data->vlan.num) {
-		l2->etype = dsa_port >= 0 ? BIT(dsa_port) : 0;
-		l2->vlan1 = data->vlan.hdr[0].id;
-		if (data->vlan.num == 2)
-			l2->vlan2 = data->vlan.hdr[1].id;
-	} else if (dsa_port >= 0) {
-		l2->etype = BIT(15) | BIT(dsa_port);
-	} else if (type >= PPE_PKT_TYPE_IPV6_ROUTE_3T) {
-		l2->etype = ETH_P_IPV6;
+		mac_info = (struct airoha_foe_mac_info *)l2;
+		mac_info->pppoe_id = data->pppoe.sid;
 	} else {
-		l2->etype = ETH_P_IP;
+		l2->src_mac_hi = FIELD_PREP(AIROHA_FOE_MAC_SMAC_ID, smac_id) |
+				 FIELD_PREP(AIROHA_FOE_MAC_PPPOE_ID,
+					    data->pppoe.sid);
+	}
+	l2->vlan1 = data->vlan.hdr[0].id;
+	l2->vlan2 = data->vlan.hdr[1].id;
+
+	if (dsa_port >= 0) {
+		l2->etype = BIT(dsa_port);
+		l2->etype |= !data->vlan.num ? BIT(15) : 0;
+	} else if (data->pppoe.num) {
+		l2->etype = ETH_P_PPP_SES;
 	}
 
 	return 0;
@@ -944,6 +950,11 @@ static int airoha_ppe_flow_offload_replace(struct airoha_gdm_port *port,
 		case FLOW_ACTION_VLAN_POP:
 			break;
 		case FLOW_ACTION_PPPOE_PUSH:
+			if (data.pppoe.num == 1 || data.vlan.num == 2)
+				return -EOPNOTSUPP;
+
+			data.pppoe.sid = act->pppoe.sid;
+			data.pppoe.num++;
 			break;
 		default:
 			return -EOPNOTSUPP;

-- 
2.49.0



From christophe.jaillet at wanadoo.fr  Sat May 24 00:29:11 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Sat, 24 May 2025 09:29:11 +0200
Subject: [PATCH v4 net] net: airoha: Fix an error handling path in airoha_alloc_gdm_port()
Message-ID: <1b94b91345017429ed653e2f05d25620dc2823f9.1746715755.git.christophe.jaillet@wanadoo.fr>

If register_netdev() fails, the error handling path of the probe will not
free the memory allocated by the previous airoha_metadata_dst_alloc() call
because port->dev->reg_state will not be NETREG_REGISTERED.

So, an explicit airoha_metadata_dst_free() call is needed in this case to
avoid a memory leak.

Fixes: af3cf757d5c9 ("net: airoha: Move DSA tag in DMA descriptor")
Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
Acked-by: Lorenzo Bianconi <lorenzo at kernel.org>
Reviewed-by: Simon Horman <horms at kernel.org>
---
Changes in v4:
  - Add A-b and R-b tags
  - Rebase against latest -next (because v3 now gets "Hunk #1 succeeded
    at 2869 (offset -4 lines)")

Changes in v3:
  - None
v3: https://lore.kernel.org/all/5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet at wanadoo.fr/

Changes in v2:
  - New patch
v2: https://lore.kernel.org/all/5c94b9b3850f7f29ed653e2205325620df28c3ff.1746715755.git.christophe.jaillet at wanadoo.fr/

Compile tested only.

In the previous iteration, this patch was part of a serie. But it
should be related to 'net', while the rest of the serie was for
'net-next'. So it is resent as a stand-alone patch, as a v4.

---
 drivers/net/ethernet/airoha/airoha_eth.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 16c7896f931f..af8c4015938c 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2869,7 +2869,15 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
 	if (err)
 		return err;
 
-	return register_netdev(dev);
+	err = register_netdev(dev);
+	if (err)
+		goto free_metadata_dst;
+
+	return 0;
+
+free_metadata_dst:
+	airoha_metadata_dst_free(port);
+	return err;
 }
 
 static int airoha_probe(struct platform_device *pdev)
-- 
2.49.0



From christophe.jaillet at wanadoo.fr  Sat May 24 01:54:22 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Sat, 24 May 2025 10:54:22 +0200
Subject: [PATCH v3 2/4] net: airoha: Fix an error handling path in
 airoha_probe()
In-Reply-To: <20250516201625.GI3339421@horms.kernel.org>
References: <5c94b9b345017f29ed653e2f05d25620d128c3f0.1746715755.git.christophe.jaillet@wanadoo.fr>
 <47910951a3fa3c3bd2a942210e821d9301362128.1746715755.git.christophe.jaillet@wanadoo.fr>
 <20250516201625.GI3339421@horms.kernel.org>
Message-ID: <7ae4c256-b14e-4add-b5f1-8b861e853407@wanadoo.fr>

Le 16/05/2025 ? 22:16, Simon Horman a ?crit?:
> On Thu, May 15, 2025 at 09:59:36PM +0200, Christophe JAILLET wrote:
>> If an error occurs after a successful airoha_hw_init() call,
>> airoha_ppe_deinit() needs to be called as already done in the remove
>> function.
>>
>> Fixes: 00a7678310fe ("net: airoha: Introduce flowtable offload support")
>> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
> 
> Reviewed-by: Simon Horman <horms at kernel.org>
> 

Hi,

I guess, that is patch should also be targeted against -net?

CJ


From olivia.wen at mediatek.com  Sat May 24 04:49:54 2025
From: olivia.wen at mediatek.com (Olivia Wen)
Date: Sat, 24 May 2025 19:49:54 +0800
Subject: [PATCH v1 02/10] dt-bindings: media: Add MT8188 ImgSys's LARB
In-Reply-To: <20250524115144.3832748-1-olivia.wen@mediatek.com>
References: <20250524115144.3832748-1-olivia.wen@mediatek.com>
Message-ID: <20250524115144.3832748-3-olivia.wen@mediatek.com>

This patch adds support for the MT8188 Image System's Local Arbiter
(LARB) in the device tree bindings. The LARB is a crucial component in
MediaTek's ImgSys architecture, responsible for managing memory access
and arbitration between various hardware modules.

Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
---
 .../bindings/media/mediatek,imgsys-larbs.yaml | 75 +++++++++++++++++++
 1 file changed, 75 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,imgsys-larbs.yaml

diff --git a/Documentation/devicetree/bindings/media/mediatek,imgsys-larbs.yaml b/Documentation/devicetree/bindings/media/mediatek,imgsys-larbs.yaml
new file mode 100644
index 000000000000..d2966c64ddb6
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,imgsys-larbs.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,imgsys-larbs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LARB Information for MediaTek Camera Image System Hardware
+
+maintainers:
+  - Olivia Wen <olivia.wen at mediatek.com>
+
+description:
+  Detailed configuration for MediaTek Camera Image System's Local Arbiter
+  (LARB) hardware integration.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt8188-imgsys-larbs
+
+  iommus:
+    minItems: 1
+    maxItems: 30
+
+  '#address-cells':
+    const: 2
+
+  '#size-cells':
+    const: 2
+
+required:
+  - compatible
+  - iommus
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
+
+    imgsys-l11b {
+        compatible = "mediatek,mt8188-imgsys-larb";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        iommus = <&vpp_iommu M4U_PORT_L11B_WPE_RDMA_0>,
+             <&vpp_iommu M4U_PORT_L11B_WPE_RDMA_1>,
+             <&vpp_iommu M4U_PORT_L11B_WPE_RDMA_4P_0>,
+             <&vpp_iommu M4U_PORT_L11B_WPE_RDMA_4P_1>,
+             <&vpp_iommu M4U_PORT_L11B_WPE_CQ0>,
+             <&vpp_iommu M4U_PORT_L11B_WPE_CQ1>,
+             <&vpp_iommu M4U_PORT_L11B_PIMGI_P1>,
+             <&vpp_iommu M4U_PORT_L11B_PIMGBI_P1>,
+             <&vpp_iommu M4U_PORT_L11B_PIMGCI_P1>,
+             <&vpp_iommu M4U_PORT_L11B_IMGI_T1_C>,
+             <&vpp_iommu M4U_PORT_L11B_IMGBI_T1_C>,
+             <&vpp_iommu M4U_PORT_L11B_IMGCI_T1_C>,
+             <&vpp_iommu M4U_PORT_L11B_SMTI_T1_C>,
+             <&vpp_iommu M4U_PORT_L11B_SMTI_T4_C>,
+             <&vpp_iommu M4U_PORT_L11B_SMTI_T6_C>,
+             <&vpp_iommu M4U_PORT_L11B_YUVO_T1_C>,
+             <&vpp_iommu M4U_PORT_L11B_YUVBO_T1_C>,
+             <&vpp_iommu M4U_PORT_L11B_YUVCO_T1_C>,
+             <&vpp_iommu M4U_PORT_L11B_WPE_WDMA_0>,
+             <&vpp_iommu M4U_PORT_L11B_WPE_WDMA_4P_0>,
+             <&vpp_iommu M4U_PORT_L11B_WROT_P1>,
+             <&vpp_iommu M4U_PORT_L11B_TCCSO_P1>,
+             <&vpp_iommu M4U_PORT_L11B_TCCSI_P1>,
+             <&vpp_iommu M4U_PORT_L11B_TIMGO_T1_C>,
+             <&vpp_iommu M4U_PORT_L11B_YUVO_T2_C>,
+             <&vpp_iommu M4U_PORT_L11B_YUVO_T5_C>,
+             <&vpp_iommu M4U_PORT_L11B_SMTO_T1_C>,
+             <&vpp_iommu M4U_PORT_L11B_SMTO_T4_C>,
+             <&vpp_iommu M4U_PORT_L11B_SMTO_T6_C>,
+             <&vpp_iommu M4U_PORT_L11B_DBGO_T1_C>;
+    };
-- 
2.45.2



From olivia.wen at mediatek.com  Sat May 24 04:49:57 2025
From: olivia.wen at mediatek.com (Olivia Wen)
Date: Sat, 24 May 2025 19:49:57 +0800
Subject: [PATCH v1 05/10] media: mediatek: isp: Add the Imgsys LARBs device
In-Reply-To: <20250524115144.3832748-1-olivia.wen@mediatek.com>
References: <20250524115144.3832748-1-olivia.wen@mediatek.com>
Message-ID: <20250524115144.3832748-6-olivia.wen@mediatek.com>

The ImgSys driver is implemented as a series of patches, with this patch
focusing on the Imgsys LARBs device. This patch adds an independent
device driver for the ImgSys Local Arbiter (LARB) devices. The addition
is necessary because the IOMMU (Input/Output Memory Management Unit)
cannot support multiple LARBs within a single device node.

Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
---
 .../isp/isp_7x/imgsys/mtk_imgsys-v4l2.c       | 61 +++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
index cfd65858c751..919c69493bbc 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
@@ -28,6 +28,58 @@
 #define IMGSYS_MAX_BUFFERS	256
 #define IMGSYS_SUSPEND_TIME 3000 /* ms */
 
+struct mtk_imgsys_larb_device {
+	struct device	*dev;
+	struct mtk_imgsys_dev *imgsys_dev;
+};
+
+static int mtk_imgsys_larb_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mtk_imgsys_larb_device *larb_dev;
+
+	larb_dev = devm_kzalloc(dev, sizeof(*dev), GFP_KERNEL);
+	if (!larb_dev)
+		return -ENOMEM;
+
+	if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34)))
+		dev_err(dev, "No suitable DMA available\n");
+
+	if (!dev->dma_parms) {
+		dev->dma_parms =
+			devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
+		if (!dev->dma_parms)
+			return -ENOMEM;
+	}
+	if (pdev->dev.dma_parms)
+		dma_set_max_seg_size(dev, UINT_MAX);
+
+	pm_runtime_enable(dev);
+
+	return 0;
+}
+
+static void mtk_imgsys_larb_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+
+	pm_runtime_disable(dev);
+}
+
+static const struct of_device_id mtk_imgsys_larb_match[] = {
+	{.compatible = "mediatek,mt8188-imgsys-larb",},
+	{},
+};
+
+static struct platform_driver mtk_imgsys_larb_driver = {
+	.probe  = mtk_imgsys_larb_probe,
+	.remove = mtk_imgsys_larb_remove,
+	.driver = {
+		.name   = "mtk-imgsys-larb",
+		.of_match_table = of_match_ptr(mtk_imgsys_larb_match),
+	},
+};
+
 static int mtk_imgsys_sd_subscribe_event(struct v4l2_subdev *subdev,
 					 struct v4l2_fh *fh,
 					 struct v4l2_event_subscription *sub)
@@ -1537,8 +1589,16 @@ static int mtk_imgsys_probe(struct platform_device *pdev)
 	pm_runtime_use_autosuspend(&pdev->dev);
 	pm_runtime_enable(&pdev->dev);
 
+	ret = platform_driver_register(&mtk_imgsys_larb_driver);
+	if (ret) {
+		dev_info(imgsys_dev->dev, "register mtk_imgsys_larb_driver fail\n");
+		goto err_release_deinit_v4l2;
+	}
+
 	return 0;
 
+err_release_deinit_v4l2:
+	mtk_imgsys_dev_v4l2_release(imgsys_dev);
 err_free_larb_alloc:
 	devm_kfree(&pdev->dev, imgsys_dev->larbs);
 err_free_dev_alloc:
@@ -1551,6 +1611,7 @@ static void mtk_imgsys_remove(struct platform_device *pdev)
 	struct mtk_imgsys_dev *imgsys_dev = dev_get_drvdata(&pdev->dev);
 
 	pm_runtime_disable(&pdev->dev);
+	platform_driver_unregister(&mtk_imgsys_larb_driver);
 	mtk_imgsys_dev_v4l2_release(imgsys_dev);
 	devm_kfree(&pdev->dev, imgsys_dev->larbs);
 	devm_kfree(&pdev->dev, imgsys_dev);
-- 
2.45.2



From olivia.wen at mediatek.com  Sat May 24 04:49:58 2025
From: olivia.wen at mediatek.com (Olivia Wen)
Date: Sat, 24 May 2025 19:49:58 +0800
Subject: [PATCH v1 06/10] media: mediatek: isp: Add module operations structure for ImgSys
In-Reply-To: <20250524115144.3832748-1-olivia.wen@mediatek.com>
References: <20250524115144.3832748-1-olivia.wen@mediatek.com>
Message-ID: <20250524115144.3832748-7-olivia.wen@mediatek.com>

The ImgSys driver is implemented as a series of patches, with this patch
focusing on a set of operations for specific modules.
The ImgSys architecture includes various modules such as WPE (Warping
Engine), TRAW (Tile-Raw), DIP (Digital Image Processing), PQDIP (Picture
Quality Digital Image Processing), and ME (Motion Estimation).
Each module requires specific operations for initialization and
deinitialization to ensure proper setup and cleanup.

Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
---
 .../mediatek/isp/isp_7x/imgsys/Makefile       |   8 +
 .../isp_7x/imgsys/modules/mtk_imgsys-dip.c    | 115 +++++++++++
 .../isp_7x/imgsys/modules/mtk_imgsys-dip.h    |  18 ++
 .../isp_7x/imgsys/modules/mtk_imgsys-pqdip.c  | 113 +++++++++++
 .../isp_7x/imgsys/modules/mtk_imgsys-pqdip.h  |  17 ++
 .../isp_7x/imgsys/modules/mtk_imgsys-traw.c   |  65 +++++++
 .../isp_7x/imgsys/modules/mtk_imgsys-traw.h   |  17 ++
 .../isp_7x/imgsys/modules/mtk_imgsys-wpe.c    | 116 +++++++++++
 .../isp_7x/imgsys/modules/mtk_imgsys-wpe.h    |  17 ++
 .../isp/isp_7x/imgsys/mtk_imgsys-dev.h        |  12 +-
 .../isp_7x/imgsys/mtk_imgsys-module_common.h  |  82 ++++++++
 .../isp_7x/imgsys/mtk_imgsys-module_main.c    | 183 ++++++++++++++++++
 .../isp_7x/imgsys/mtk_imgsys-module_main.h    |  17 ++
 .../isp/isp_7x/imgsys/mtk_imgsys-module_ops.h |  26 +++
 .../isp/isp_7x/imgsys/mtk_imgsys-of.h         |   3 +
 .../isp/isp_7x/imgsys/mtk_imgsys-sys.c        |  73 ++++++-
 .../isp/isp_7x/imgsys/mtk_imgsys-v4l2.c       |  45 ++++-
 17 files changed, 923 insertions(+), 4 deletions(-)
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_common.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_main.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_main.h

diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
index 571d0ae000eb..26c8c1d39750 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
@@ -2,10 +2,18 @@
 #
 
 mtk_imgsys_util-objs := \
+mtk_imgsys-module_main.o \
 mtk_imgsys-of.o \
 mtk_imgsys-formats.o \
 mtk_imgsys-dev.o \
 mtk_imgsys-sys.o \
 mtk_imgsys-v4l2.o
 
+mtk_imgsys_hw_isp-objs := \
+modules/mtk_imgsys-dip.o \
+modules/mtk_imgsys-traw.o \
+modules/mtk_imgsys-pqdip.o \
+modules/mtk_imgsys-wpe.o
+
 obj-$(CONFIG_VIDEO_MTK_ISP_71_IMGSYS) += mtk_imgsys_util.o
+obj-$(CONFIG_VIDEO_MTK_ISP_71_IMGSYS) += mtk_imgsys_hw_isp.o
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.c
new file mode 100644
index 000000000000..1cc1f3e87e8b
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *         Holmes Chiou <holmes.chiou at mediatek.com>
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/of_address.h>
+#include "../mtk_imgsys-module_common.h"
+#include "mtk_imgsys-dip.h"
+
+/********************************************************************
+ * Global Define
+ ********************************************************************/
+#define DIPCTL_D1A_DIPCTL_INT1_EN    0x094
+#define DIPCTL_D1A_DIPCTL_INT2_EN    0x0A0
+#define DIPCTL_D1A_DIPCTL_INT3_EN    0x0AC
+#define DIPCTL_D1A_DIPCTL_CQ_INT1_EN 0x0C4
+#define DIPCTL_D1A_DIPCTL_CQ_INT2_EN 0x0D0
+#define DIPCTL_D1A_DIPCTL_CQ_INT3_EN 0x0DC
+
+#define DIPCQ_D1A_DIPCQ_CQ_THR0_CTL  0x208
+#define DIPCQ_D1A_DIPCQ_CQ_THR1_CTL  0x218
+#define DIPCQ_D1A_DIPCQ_CQ_THR2_CTL  0x228
+#define DIPCQ_D1A_DIPCQ_CQ_THR3_CTL  0x238
+#define DIPCQ_D1A_DIPCQ_CQ_THR4_CTL  0x248
+#define DIPCQ_D1A_DIPCQ_CQ_THR5_CTL  0x258
+#define DIPCQ_D1A_DIPCQ_CQ_THR6_CTL  0x268
+#define DIPCQ_D1A_DIPCQ_CQ_THR7_CTL  0x278
+#define DIPCQ_D1A_DIPCQ_CQ_THR8_CTL  0x288
+#define DIPCQ_D1A_DIPCQ_CQ_THR9_CTL  0x298
+#define DIPCQ_D1A_DIPCQ_CQ_THR10_CTL 0x2A8
+#define DIPCQ_D1A_DIPCQ_CQ_THR11_CTL 0x2B8
+#define DIPCQ_D1A_DIPCQ_CQ_THR12_CTL 0x2C8
+#define DIPCQ_D1A_DIPCQ_CQ_THR13_CTL 0x2D8
+#define DIPCQ_D1A_DIPCQ_CQ_THR14_CTL 0x2E8
+#define DIPCQ_D1A_DIPCQ_CQ_THR15_CTL 0x2F8
+#define DIPCQ_D1A_DIPCQ_CQ_THR16_CTL 0x308
+#define DIPCQ_D1A_DIPCQ_CQ_THR17_CTL 0x318
+#define DIPCQ_D1A_DIPCQ_CQ_THR18_CTL 0x328
+
+#define DIP_INIT_ARRAY_COUNT	ARRAY_SIZE(mtk_imgsys_dip_init_ary)
+
+/********************************************************************
+ * Global Variable
+ ********************************************************************/
+static const struct mtk_imgsys_init_array mtk_imgsys_dip_init_ary[] = {
+	{ DIPCTL_D1A_DIPCTL_INT1_EN, 0x80000000 },
+	{ DIPCTL_D1A_DIPCTL_INT2_EN, 0x0 },
+	{ DIPCTL_D1A_DIPCTL_INT3_EN, 0x0 },
+	{ DIPCTL_D1A_DIPCTL_CQ_INT1_EN, 0x0 },
+	{ DIPCTL_D1A_DIPCTL_CQ_INT2_EN, 0x0 },
+	{ DIPCTL_D1A_DIPCTL_CQ_INT3_EN, 0x0 },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR0_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR1_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR2_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR3_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR4_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR5_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR6_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR7_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR8_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR9_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR10_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR11_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR12_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR13_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR14_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR15_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR16_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR17_CTL, CQ_THRX_CTL },
+	{ DIPCQ_D1A_DIPCQ_CQ_THR18_CTL, CQ_THRX_CTL },
+};
+
+static void __iomem *dip_reg_base[MTK_IMGSYS_DIP_HW_SET];
+
+/********************************************************************
+ * Functions
+ ********************************************************************/
+void imgsys_dip_init(struct mtk_imgsys_dev *imgsys_dev)
+{
+	unsigned int i, hw_id, hw_idx;
+	void __iomem *offset = NULL;
+
+	for (hw_idx = 0; hw_idx < MTK_IMGSYS_DIP_HW_SET; hw_idx++) {
+		hw_id = IMGSYS_REG_DIP1 + hw_idx;
+		dip_reg_base[hw_idx] = of_iomap(imgsys_dev->dev->of_node, hw_id);
+		if (!dip_reg_base[hw_idx]) {
+			dev_info(imgsys_dev->dev,
+				 "%s: error: unable to iomap dip_%d registers, devnode(%s).\n",
+				 __func__, hw_id, imgsys_dev->dev->of_node->name);
+			continue;
+		}
+
+		for (i = 0 ; i < DIP_INIT_ARRAY_COUNT; i++) {
+			offset = dip_reg_base[hw_idx] + mtk_imgsys_dip_init_ary[i].offset;
+			writel(mtk_imgsys_dip_init_ary[i].value, offset);
+		}
+	}
+}
+EXPORT_SYMBOL_GPL(imgsys_dip_init);
+
+void imgsys_dip_uninit(struct mtk_imgsys_dev *imgsys_dev)
+{
+	unsigned int hw_idx;
+
+	for (hw_idx = 0; hw_idx < MTK_IMGSYS_DIP_HW_SET; hw_idx++) {
+		iounmap(dip_reg_base[hw_idx]);
+		dip_reg_base[hw_idx] = NULL;
+	}
+}
+EXPORT_SYMBOL_GPL(imgsys_dip_uninit);
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.h
new file mode 100644
index 000000000000..22b4a7c3616d
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_DIP_DIP_H_
+#define _MTK_DIP_DIP_H_
+
+#include "../mtk_imgsys-dev.h"
+
+void imgsys_dip_init(struct mtk_imgsys_dev *imgsys_dev);
+void imgsys_dip_uninit(struct mtk_imgsys_dev *imgsys_dev);
+
+#endif /* _MTK_DIP_DIP_H_ */
+
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.c
new file mode 100644
index 000000000000..d1d3507555d9
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ *
+ * Author: Daniel Huang <daniel.huang at mediatek.com>
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/of_address.h>
+#include "../mtk_imgsys-module_common.h"
+#include "mtk_imgsys-pqdip.h"
+
+/********************************************************************
+ * Global Define
+ ********************************************************************/
+#define PQDIPCTL_P1A_REG_PQDIPCTL_INT1_EN		0x0050
+#define PQDIPCTL_P1A_REG_PQDIPCTL_INT2_EN		0x0060
+#define PQDIPCTL_P1A_REG_PQDIPCTL_CQ_INT1_EN	0x0070
+#define PQDIPCTL_P1A_REG_PQDIPCTL_CQ_INT2_EN	0x0080
+#define PQDIPCTL_P1A_REG_PQDIPCTL_CQ_INT3_EN	0x0090
+
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR0_CTL			0x0208
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR1_CTL			0x0218
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR2_CTL			0x0228
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR3_CTL			0x0238
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR4_CTL			0x0248
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR5_CTL			0x0258
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR6_CTL			0x0268
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR7_CTL			0x0278
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR8_CTL			0x0288
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR9_CTL			0x0298
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR10_CTL		0x02A8
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR11_CTL		0x02B8
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR12_CTL		0x02C8
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR13_CTL		0x02D8
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR14_CTL		0x02E8
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR15_CTL		0x02F8
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR16_CTL		0x0308
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR17_CTL		0x0318
+#define DIPCQ_P1A_REG_DIPCQ_CQ_THR18_CTL		0x0328
+
+#define PQDIP_INIT_ARRAY_COUNT	ARRAY_SIZE(mtk_imgsys_pqdip_init_ary)
+
+/********************************************************************
+ * Global Variable
+ ********************************************************************/
+static const struct mtk_imgsys_init_array mtk_imgsys_pqdip_init_ary[] = {
+	{ PQDIPCTL_P1A_REG_PQDIPCTL_INT1_EN, 0x80000000 },
+	{ PQDIPCTL_P1A_REG_PQDIPCTL_INT2_EN, 0x0 },
+	{ PQDIPCTL_P1A_REG_PQDIPCTL_CQ_INT1_EN, 0x0 },
+	{ PQDIPCTL_P1A_REG_PQDIPCTL_CQ_INT2_EN, 0x0 },
+	{ PQDIPCTL_P1A_REG_PQDIPCTL_CQ_INT3_EN, 0x0 },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR0_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR1_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR2_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR3_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR4_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR5_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR6_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR7_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR8_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR9_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR10_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR11_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR12_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR13_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR14_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR15_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR16_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR17_CTL, CQ_THRX_CTL },
+	{ DIPCQ_P1A_REG_DIPCQ_CQ_THR18_CTL, CQ_THRX_CTL },
+};
+
+static void __iomem *pqdip_reg_base[MTK_IMGSYS_PQDIP_HW_SET];
+
+/********************************************************************
+ * Functions
+ ********************************************************************/
+void imgsys_pqdip_init(struct mtk_imgsys_dev *imgsys_dev)
+{
+	unsigned int i, hw_id, hw_idx;
+	void __iomem *offset = NULL;
+
+	for (hw_idx = 0; hw_idx < MTK_IMGSYS_PQDIP_HW_SET; hw_idx++) {
+		hw_id = IMGSYS_REG_PQDIP1 + hw_idx;
+		pqdip_reg_base[hw_idx] = of_iomap(imgsys_dev->dev->of_node, hw_id);
+		if (!pqdip_reg_base[hw_idx]) {
+			dev_info(imgsys_dev->dev,
+				 "%s: error: unable to iomap pqdip_%d registers, devnode(%s).\n",
+				 __func__, hw_id, imgsys_dev->dev->of_node->name);
+			continue;
+		}
+
+		for (i = 0 ; i < PQDIP_INIT_ARRAY_COUNT; i++) {
+			offset = pqdip_reg_base[hw_idx] + mtk_imgsys_pqdip_init_ary[i].offset;
+			writel(mtk_imgsys_pqdip_init_ary[i].value, offset);
+		}
+	}
+}
+EXPORT_SYMBOL_GPL(imgsys_pqdip_init);
+
+void imgsys_pqdip_uninit(struct mtk_imgsys_dev *imgsys_dev)
+{
+	unsigned int hw_idx;
+
+	for (hw_idx = 0; hw_idx < MTK_IMGSYS_PQDIP_HW_SET; hw_idx++) {
+		iounmap(pqdip_reg_base[hw_idx]);
+		pqdip_reg_base[hw_idx] = NULL;
+	}
+}
+EXPORT_SYMBOL_GPL(imgsys_pqdip_uninit);
+
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.h
new file mode 100644
index 000000000000..00f93d536181
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ *
+ * Author: Daniel Huang <daniel.huang at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_IMGSYS_PQDIP_H_
+#define _MTK_IMGSYS_PQDIP_H_
+
+#include "../mtk_imgsys-dev.h"
+
+void imgsys_pqdip_init(struct mtk_imgsys_dev *imgsys_dev);
+void imgsys_pqdip_uninit(struct mtk_imgsys_dev *imgsys_dev);
+
+#endif /* _MTK_IMGSYS_PQDIP_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.c
new file mode 100644
index 000000000000..292f0ad09c46
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ *
+ * Author: Shih-Fang Chuang <shih-fang.chuang at mediatek.com>
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/of_address.h>
+#include "../mtk_imgsys-module_common.h"
+#include "mtk_imgsys-traw.h"
+
+/********************************************************************
+ * Global Define
+ ********************************************************************/
+#define TRAWCTL_INT1_EN 0x00A0
+
+#define TRAW_INIT_ARRAY_COUNT	ARRAY_SIZE(mtk_imgsys_traw_init_ary)
+
+/********************************************************************
+ * Global Variable
+ ********************************************************************/
+static const struct mtk_imgsys_init_array mtk_imgsys_traw_init_ary[] = {
+	{ TRAWCTL_INT1_EN, 0x80000000 },
+};
+
+static void __iomem *traw_reg_base[MTK_IMGSYS_TRAW_HW_SET];
+
+/********************************************************************
+ * Functions
+ ********************************************************************/
+void imgsys_traw_init(struct mtk_imgsys_dev *imgsys_dev)
+{
+	unsigned int i, hw_id, hw_idx;
+	void __iomem *offset = NULL;
+
+	for (hw_idx = 0; hw_idx < MTK_IMGSYS_TRAW_HW_SET; hw_idx++) {
+		hw_id = IMGSYS_REG_TRAW1 + hw_idx;
+		traw_reg_base[hw_idx] = of_iomap(imgsys_dev->dev->of_node, hw_id);
+		if (!traw_reg_base[hw_idx]) {
+			dev_info(imgsys_dev->dev,
+				 "%s: error: unable to iomap traw_%d registers, devnode(%s).\n",
+				 __func__, hw_id, imgsys_dev->dev->of_node->name);
+			continue;
+		}
+
+		for (i = 0 ; i < TRAW_INIT_ARRAY_COUNT; i++) {
+			offset = traw_reg_base[hw_idx] + mtk_imgsys_traw_init_ary[i].offset;
+			writel(mtk_imgsys_traw_init_ary[i].value, offset);
+		}
+	}
+}
+EXPORT_SYMBOL_GPL(imgsys_traw_init);
+
+void imgsys_traw_uninit(struct mtk_imgsys_dev *imgsys_dev)
+{
+	unsigned int hw_idx;
+
+	for (hw_idx = 0; hw_idx < MTK_IMGSYS_TRAW_HW_SET; hw_idx++) {
+		iounmap(traw_reg_base[hw_idx]);
+		traw_reg_base[hw_idx] = NULL;
+	}
+}
+EXPORT_SYMBOL_GPL(imgsys_traw_uninit);
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.h
new file mode 100644
index 000000000000..f3727216b58c
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ *
+ * Author: Shih-fang Chuang <shih-fang.chuang at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_IMGSYS_TRAW_H_
+#define _MTK_IMGSYS_TRAW_H_
+
+#include "../mtk_imgsys-dev.h"
+
+void imgsys_traw_init(struct mtk_imgsys_dev *imgsys_dev);
+void imgsys_traw_uninit(struct mtk_imgsys_dev *imgsys_dev);
+
+#endif /* _MTK_IMGSYS_TRAW_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.c
new file mode 100644
index 000000000000..b19d61529b80
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ *
+ * Author: Floria Huang <floria.huang at mediatek.com>
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/of_address.h>
+#include "../mtk_imgsys-module_common.h"
+#include "mtk_imgsys-wpe.h"
+
+/********************************************************************
+ * Global Define
+ ********************************************************************/
+/* Define register offsets */
+#define WPE_TOP_CTL_INT_EN_OFFSET       0x0018
+#define WPE_TOP_CTL_INT_STATUSX_OFFSET  0x0024
+#define WPE_TOP_CQ_IRQ_EN_OFFSET        0x00D4
+#define WPE_TOP_CQ_IRQ_STX_OFFSET       0x00DC
+#define WPE_TOP_CQ_IRQ_EN2_OFFSET       0x00E0
+#define WPE_TOP_CQ_IRQ_STX2_OFFSET      0x00E8
+#define WPE_TOP_CQ_IRQ_EN3_OFFSET       0x00EC
+#define WPE_TOP_CQ_IRQ_STX3_OFFSET      0x00F4
+#define WPE_CACHE_RWCTL_CTL_OFFSET      0x0204
+#define WPE_DMA_DMA_ERR_CTRL_OFFSET     0x03D4
+#define DIPCQ_W1A_DIPCQ_CQ_THR0_CTL_OFFSET 0x0B08
+#define DIPCQ_W1A_DIPCQ_CQ_THR1_CTL_OFFSET 0x0B18
+#define DIPCQ_W1A_DIPCQ_CQ_THR2_CTL_OFFSET 0x0B28
+#define DIPCQ_W1A_DIPCQ_CQ_THR3_CTL_OFFSET 0x0B38
+#define DIPCQ_W1A_DIPCQ_CQ_THR4_CTL_OFFSET 0x0B48
+#define DIPCQ_W1A_DIPCQ_CQ_THR5_CTL_OFFSET 0x0B58
+#define DIPCQ_W1A_DIPCQ_CQ_THR6_CTL_OFFSET 0x0B68
+#define DIPCQ_W1A_DIPCQ_CQ_THR7_CTL_OFFSET 0x0B78
+#define DIPCQ_W1A_DIPCQ_CQ_THR8_CTL_OFFSET 0x0B88
+#define DIPCQ_W1A_DIPCQ_CQ_THR9_CTL_OFFSET 0x0B98
+#define DIPCQ_W1A_DIPCQ_CQ_THR10_CTL_OFFSET 0x0BA8
+#define DIPCQ_W1A_DIPCQ_CQ_THR11_CTL_OFFSET 0x0BB8
+#define DIPCQ_W1A_DIPCQ_CQ_THR12_CTL_OFFSET 0x0BC8
+#define DIPCQ_W1A_DIPCQ_CQ_THR13_CTL_OFFSET 0x0BD8
+#define DIPCQ_W1A_DIPCQ_CQ_THR14_CTL_OFFSET 0x0BE8
+
+#define WPE_INIT_ARRAY_COUNT	ARRAY_SIZE(mtk_imgsys_wpe_init_ary)
+/********************************************************************
+ * Global Variable
+ ********************************************************************/
+static const struct mtk_imgsys_init_array mtk_imgsys_wpe_init_ary[] = {
+	{ WPE_TOP_CTL_INT_EN_OFFSET, 0x80000000 },
+	{ WPE_TOP_CTL_INT_STATUSX_OFFSET, 0xFFFFFFFF },
+	{ WPE_TOP_CQ_IRQ_EN_OFFSET, 0x80000000 },
+	{ WPE_TOP_CQ_IRQ_STX_OFFSET, 0xFFFFFFFF },
+	{ WPE_TOP_CQ_IRQ_EN2_OFFSET, 0x80000000 },
+	{ WPE_TOP_CQ_IRQ_STX2_OFFSET, 0xFFFFFFFF },
+	{ WPE_TOP_CQ_IRQ_EN3_OFFSET, 0x80000000 },
+	{ WPE_TOP_CQ_IRQ_STX3_OFFSET, 0xFFFFFFFF },
+	{ WPE_CACHE_RWCTL_CTL_OFFSET, 0x00000002 },
+	{ WPE_DMA_DMA_ERR_CTRL_OFFSET, 0x80000000 },
+	{ DIPCQ_W1A_DIPCQ_CQ_THR0_CTL_OFFSET, CQ_THRX_CTL },
+	{ DIPCQ_W1A_DIPCQ_CQ_THR1_CTL_OFFSET, CQ_THRX_CTL },
+	{ DIPCQ_W1A_DIPCQ_CQ_THR2_CTL_OFFSET, CQ_THRX_CTL },
+	{ DIPCQ_W1A_DIPCQ_CQ_THR3_CTL_OFFSET, CQ_THRX_CTL },
+	{ DIPCQ_W1A_DIPCQ_CQ_THR4_CTL_OFFSET, CQ_THRX_CTL },
+	{ DIPCQ_W1A_DIPCQ_CQ_THR5_CTL_OFFSET, CQ_THRX_CTL },
+	{ DIPCQ_W1A_DIPCQ_CQ_THR6_CTL_OFFSET, CQ_THRX_CTL },
+	{ DIPCQ_W1A_DIPCQ_CQ_THR7_CTL_OFFSET, CQ_THRX_CTL },
+	{ DIPCQ_W1A_DIPCQ_CQ_THR8_CTL_OFFSET, CQ_THRX_CTL },
+	{ DIPCQ_W1A_DIPCQ_CQ_THR9_CTL_OFFSET, CQ_THRX_CTL },
+	{ DIPCQ_W1A_DIPCQ_CQ_THR10_CTL_OFFSET, CQ_THRX_CTL },
+	{ DIPCQ_W1A_DIPCQ_CQ_THR11_CTL_OFFSET, CQ_THRX_CTL },
+	{ DIPCQ_W1A_DIPCQ_CQ_THR12_CTL_OFFSET, CQ_THRX_CTL },
+	{ DIPCQ_W1A_DIPCQ_CQ_THR13_CTL_OFFSET, CQ_THRX_CTL },
+	{ DIPCQ_W1A_DIPCQ_CQ_THR14_CTL_OFFSET, CQ_THRX_CTL },
+};
+
+static void __iomem *wpe_reg_base[MTK_IMGSYS_WPE_HW_SET];
+
+/********************************************************************
+ * Functions
+ ********************************************************************/
+void imgsys_wpe_init(struct mtk_imgsys_dev *imgsys_dev)
+{
+	unsigned int i, hw_id, hw_idx;
+	void __iomem *offset = NULL;
+
+	for (hw_idx = 0; hw_idx < MTK_IMGSYS_WPE_HW_SET; hw_idx++) {
+		hw_id = IMGSYS_REG_WPE1 + hw_idx;
+		wpe_reg_base[hw_idx] = of_iomap(imgsys_dev->dev->of_node, hw_id);
+		if (!wpe_reg_base[hw_idx]) {
+			dev_info(imgsys_dev->dev,
+				 "%s: error: unable to iomap wpe_%d registers, devnode(%s).\n",
+				 __func__, hw_id, imgsys_dev->dev->of_node->name);
+			continue;
+		}
+
+		for (i = 0 ; i < WPE_INIT_ARRAY_COUNT; i++) {
+			offset = wpe_reg_base[hw_idx] + mtk_imgsys_wpe_init_ary[i].offset;
+			writel(mtk_imgsys_wpe_init_ary[i].value, offset);
+		}
+	}
+}
+EXPORT_SYMBOL_GPL(imgsys_wpe_init);
+
+void imgsys_wpe_uninit(struct mtk_imgsys_dev *imgsys_dev)
+{
+	unsigned int hw_idx;
+
+	for (hw_idx = 0; hw_idx < MTK_IMGSYS_WPE_HW_SET; hw_idx++) {
+		iounmap(wpe_reg_base[hw_idx]);
+		wpe_reg_base[hw_idx] = NULL;
+	}
+}
+EXPORT_SYMBOL_GPL(imgsys_wpe_uninit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MediaTek IMGSYS Modules");
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.h
new file mode 100644
index 000000000000..6001575265e6
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ *
+ * Author: Floria Huang <floria.huang at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_IMGSYS_WPE_H_
+#define _MTK_IMGSYS_WPE_H_
+
+#include "../mtk_imgsys-dev.h"
+
+void imgsys_wpe_init(struct mtk_imgsys_dev *imgsys_dev);
+void imgsys_wpe_uninit(struct mtk_imgsys_dev *imgsys_dev);
+
+#endif /* _MTK_IMGSYS_WPE_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.h
index b69cfd0043d3..b8c30cb32b97 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.h
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.h
@@ -23,7 +23,7 @@
 #include <linux/videodev2.h>
 #include <media/videobuf2-core.h>
 #include <media/videobuf2-v4l2.h>
-
+#include "mtk_imgsys-module_ops.h"
 #include "mtk_header_desc.h"
 
 #define MTK_IMGSYS_MEDIA_MODEL_NAME	"MTK-ISP-DIP-V4L2"
@@ -273,6 +273,7 @@ struct mtk_imgsys_pipe {
  * @v4l2_dev: V4L2 device structure for video device operations.
  * @imgsys_pipe: Image system pipeline configuration structure.
  * @cust_pipes: Pointer to custom pipeline descriptors.
+ * @modules: Pointer to image system module operations.
  * @clks: Array of clock bulk data for managing multiple clocks.
  * @num_clks: Number of clocks in the clock array.
  * @larbs: Array of device pointers for managing LARB (local arbiter).
@@ -281,6 +282,9 @@ struct mtk_imgsys_pipe {
  * @rproc_handle: Handle for remote processor interface.
  * @smem_dev: Device structure for shared memory operations.
  * @num_mods: Number of modules in the image system.
+ * @init_kref: Reference counter for initialization tracking.
+ * @hw_op_lock: Mutex for serializing hardware operations.
+ * @stream_cnt: Counter for active streams, increased on stream on.
  */
 struct mtk_imgsys_dev {
 	/* Device and Resource Information */
@@ -292,6 +296,8 @@ struct mtk_imgsys_dev {
 	struct mtk_imgsys_pipe imgsys_pipe;
 	/* Imgsys Pipeline Information */
 	const struct mtk_imgsys_pipe_desc *cust_pipes;
+	/* Imgsys Moudles Information */
+	const struct module_ops *modules;
 	/* Clock Information */
 	struct clk_bulk_data *clks;
 	int num_clks;
@@ -304,6 +310,10 @@ struct mtk_imgsys_dev {
 	struct device *smem_dev;
 	/* Number of modules */
 	int num_mods;
+	/* Synchronization and Flow Control */
+	struct kref init_kref;
+	struct mutex hw_op_lock; /* Protect HW operations */
+	int stream_cnt;
 };
 
 /**
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_common.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_common.h
new file mode 100644
index 000000000000..dd02a8fa28d4
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_common.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Christopher Chen <christopher.chen at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_IMGSYS_CORE_REG_H_
+#define _MTK_IMGSYS_CORE_REG_H_
+
+/**
+ * Define the minimum and maximum hardware IDs
+ * for different MediaTek Image System components
+ */
+#define WPE_HW_MIN_ID	IMGSYS_REG_WPE1
+#define WPE_HW_MAX_ID	IMGSYS_REG_WPE3
+#define TRAW_HW_MIN_ID	IMGSYS_REG_TRAW1
+#define TRAW_HW_MAX_ID	IMGSYS_REG_TRAW3
+#define DIP_HW_MIN_ID	IMGSYS_REG_DIP1
+#define DIP_HW_MAX_ID	IMGSYS_REG_DIP2
+#define PQDIP_HW_MIN_ID	IMGSYS_REG_PQDIP1
+#define PQDIP_HW_MAX_ID	IMGSYS_REG_PQDIP2
+#define ME_HW_MIN_ID	IMGSYS_REG_ME
+#define ME_HW_MAX_ID	IMGSYS_REG_ME
+
+/* Macro to calculate the size of a hardware set */
+#define HW_SET_SIZE(min_id, max_id) ((max_id) - (min_id) + 1)
+
+/* Define the hardware set sizes */
+#define MTK_IMGSYS_WPE_HW_SET	HW_SET_SIZE(WPE_HW_MIN_ID, WPE_HW_MAX_ID)
+#define MTK_IMGSYS_TRAW_HW_SET	HW_SET_SIZE(TRAW_HW_MIN_ID, TRAW_HW_MAX_ID)
+#define MTK_IMGSYS_DIP_HW_SET	HW_SET_SIZE(DIP_HW_MIN_ID, DIP_HW_MAX_ID)
+#define MTK_IMGSYS_PQDIP_HW_SET	HW_SET_SIZE(PQDIP_HW_MIN_ID, PQDIP_HW_MAX_ID)
+#define MTK_IMGSYS_ME_HW_SET	HW_SET_SIZE(ME_HW_MIN_ID, ME_HW_MAX_ID)
+
+/* Define the CQ's control register bits */
+#define CQ_THRX_CTL_EN		BIT(0)
+#define CQ_THRX_CTL_MODE	BIT(4)
+#define CQ_THRX_CTL			(CQ_THRX_CTL_EN | CQ_THRX_CTL_MODE)
+
+/**
+ * enum mtk_imgsys_reg_id
+ *
+ * Definition about hw register map id
+ * The engine order should be the same as register order in dts
+ */
+enum mtk_imgsys_reg_id {
+	IMGSYS_REG_TOP = 0,
+	IMGSYS_REG_TRAW1,
+	IMGSYS_REG_TRAW2,
+	IMGSYS_REG_TRAW3,
+	IMGSYS_REG_DIP1,
+	IMGSYS_REG_DIP2,
+	IMGSYS_REG_PQDIP1,
+	IMGSYS_REG_PQDIP2,
+	IMGSYS_REG_WPE1,
+	IMGSYS_REG_WPE2,
+	IMGSYS_REG_WPE3,
+	IMGSYS_REG_WPE1_DIP1,
+	IMGSYS_REG_ME,
+	IMGSYS_REG_WPE2_DIP1,
+	IMGSYS_REG_WPE3_DIP1,
+	IMGSYS_REG_DIP1_TOP,
+	IMGSYS_REG_DIP2_TOP
+};
+
+/**
+ * struct mtk_imgsys_init_array - Array structure for initializing registers
+ * @offset: Offset of the register
+ * @val: Value to be written to the register
+ *
+ * This structure represents an array element used for initializing registers
+ * in the MediaTek Image System. Each element contains the offset of the register
+ * and the value to be written to that register.
+ */
+struct mtk_imgsys_init_array {
+	unsigned int    offset;
+	unsigned int    value;
+};
+#endif /* _MTK_IMGSYS_CORE_REG_H_ */
+
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_main.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_main.c
new file mode 100644
index 000000000000..5daa8f863bd2
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_main.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Christopher Chen <christopher.chen at mediatek.com>
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/of_address.h>
+#include "mtk_imgsys-module_common.h"
+#include "mtk_imgsys-module_main.h"
+
+/********************************************************************
+ * Global Define
+ ********************************************************************/
+/* Define the reset register bits */
+#define SW_RST				(0x000C)
+
+/********************************************************************
+ * Global Variable
+ ********************************************************************/
+static void __iomem *imgsys_main_reg_base;
+static void __iomem *wpe_dip1_reg_base;
+static void __iomem *wpe_dip2_reg_base;
+static void __iomem *wpe_dip3_reg_base;
+static void __iomem *dip1_reg_base;
+static void __iomem *dip2_reg_base;
+
+/********************************************************************
+ * Functions
+ ********************************************************************/
+static void imgsys_main_hw_init(struct mtk_imgsys_dev *imgsys_dev)
+{
+	void __iomem *wpe_reg_base = NULL;
+	void __iomem *wpe_ctrl = NULL;
+	unsigned int hw_idx = 0;
+
+	/* Enable all LARBs of ImgSys */
+	/**
+	 * The flow will be updated based on the patch series 958467 from
+	 * the Linux MediaTek project. For more details, refer to the following link:
+	 * https://patchwork.kernel.org/project/linux-mediatek/list/?series=958467
+	 */
+
+	/* Reset ImgSys hardware */
+	iowrite32(0xFFFFFFFF, dip1_reg_base + SW_RST);
+	iowrite32(0xFFFFFFFF, dip2_reg_base + SW_RST);
+
+	for (hw_idx = 0; hw_idx < MTK_IMGSYS_WPE_HW_SET; hw_idx++) {
+		if (hw_idx == 0)
+			wpe_reg_base = wpe_dip1_reg_base;
+		else if (hw_idx == 1)
+			wpe_reg_base = wpe_dip2_reg_base;
+		else
+			wpe_reg_base = wpe_dip3_reg_base;
+
+		wpe_ctrl = wpe_reg_base + SW_RST;
+		iowrite32(0xFFFFFFFF, wpe_ctrl);
+		iowrite32(0x0, wpe_ctrl);
+	}
+
+	iowrite32(0x00CF00FF, imgsys_main_reg_base + SW_RST);
+	iowrite32(0x0, imgsys_main_reg_base + SW_RST);
+
+	iowrite32(0x0, dip1_reg_base + SW_RST);
+	iowrite32(0x0, dip2_reg_base + SW_RST);
+
+	for (hw_idx = 0; hw_idx < MTK_IMGSYS_WPE_HW_SET; hw_idx++) {
+		if (hw_idx == 0)
+			wpe_reg_base = wpe_dip1_reg_base;
+		else if (hw_idx == 1)
+			wpe_reg_base = wpe_dip2_reg_base;
+		else
+			wpe_reg_base = wpe_dip3_reg_base;
+
+		wpe_ctrl = wpe_reg_base + SW_RST;
+		iowrite32(0xFFFFFFFF, wpe_ctrl);
+		iowrite32(0x0, wpe_ctrl);
+	}
+
+	iowrite32(0x00CF00FF, imgsys_main_reg_base + SW_RST);
+	iowrite32(0x0, imgsys_main_reg_base + SW_RST);
+
+	/* Disable all LARBs of ImgSys*/
+	/**
+	 * The flow will be updated based on the patch series 958467 from
+	 * the Linux MediaTek project. For more details, refer to the following link:
+	 * https://patchwork.kernel.org/project/linux-mediatek/list/?series=958467
+	 */
+}
+
+void imgsys_main_init(struct mtk_imgsys_dev *imgsys_dev)
+{
+	imgsys_main_reg_base = of_iomap(imgsys_dev->dev->of_node, IMGSYS_REG_TOP);
+	if (!imgsys_main_reg_base) {
+		dev_info(imgsys_dev->dev, "%s Unable to ioremap imgsys_top registers\n",
+			 __func__);
+		dev_info(imgsys_dev->dev, "%s of_iomap fail, devnode(%s).\n",
+			 __func__, imgsys_dev->dev->of_node->name);
+		return;
+	}
+
+	wpe_dip1_reg_base = of_iomap(imgsys_dev->dev->of_node, IMGSYS_REG_WPE1_DIP1);
+	if (!wpe_dip1_reg_base) {
+		dev_info(imgsys_dev->dev, "%s Unable to ioremap wpe_dip1 registers\n",
+			 __func__);
+		dev_info(imgsys_dev->dev, "%s of_iomap fail, devnode(%s).\n",
+			 __func__, imgsys_dev->dev->of_node->name);
+		return;
+	}
+
+	wpe_dip2_reg_base = of_iomap(imgsys_dev->dev->of_node, IMGSYS_REG_WPE2_DIP1);
+	if (!wpe_dip2_reg_base) {
+		dev_info(imgsys_dev->dev, "%s Unable to ioremap wpe_dip2 registers\n",
+			 __func__);
+		dev_info(imgsys_dev->dev, "%s of_iomap fail, devnode(%s).\n",
+			 __func__, imgsys_dev->dev->of_node->name);
+		return;
+	}
+
+	wpe_dip3_reg_base = of_iomap(imgsys_dev->dev->of_node, IMGSYS_REG_WPE3_DIP1);
+	if (!wpe_dip3_reg_base) {
+		dev_info(imgsys_dev->dev, "%s Unable to ioremap wpe_dip3 registers\n",
+			 __func__);
+		dev_info(imgsys_dev->dev, "%s of_iomap fail, devnode(%s).\n",
+			 __func__, imgsys_dev->dev->of_node->name);
+		return;
+	}
+
+	dip1_reg_base = of_iomap(imgsys_dev->dev->of_node, IMGSYS_REG_DIP1_TOP);
+	if (!dip1_reg_base) {
+		dev_info(imgsys_dev->dev, "%s Unable to ioremap dip_top registers\n",
+			 __func__);
+		dev_info(imgsys_dev->dev, "%s of_iomap fail, devnode(%s).\n",
+			 __func__, imgsys_dev->dev->of_node->name);
+		return;
+	}
+
+	dip2_reg_base = of_iomap(imgsys_dev->dev->of_node, IMGSYS_REG_DIP2_TOP);
+	if (!dip2_reg_base) {
+		dev_info(imgsys_dev->dev, "%s Unable to ioremap dip_top_nr registers\n",
+			 __func__);
+		dev_info(imgsys_dev->dev, "%s of_iomap fail, devnode(%s).\n",
+			 __func__, imgsys_dev->dev->of_node->name);
+		return;
+	}
+
+	imgsys_main_hw_init(imgsys_dev);
+}
+
+void imgsys_main_uninit(struct mtk_imgsys_dev *imgsys_dev)
+{
+	if (imgsys_main_reg_base) {
+		iounmap(imgsys_main_reg_base);
+		imgsys_main_reg_base = NULL;
+	}
+
+	if (wpe_dip1_reg_base) {
+		iounmap(wpe_dip1_reg_base);
+		wpe_dip1_reg_base = NULL;
+	}
+
+	if (wpe_dip2_reg_base) {
+		iounmap(wpe_dip2_reg_base);
+		wpe_dip2_reg_base = NULL;
+	}
+
+	if (wpe_dip3_reg_base) {
+		iounmap(wpe_dip3_reg_base);
+		wpe_dip3_reg_base = NULL;
+	}
+
+	if (dip1_reg_base) {
+		iounmap(dip1_reg_base);
+		dip1_reg_base = NULL;
+	}
+
+	if (dip2_reg_base) {
+		iounmap(dip2_reg_base);
+		dip2_reg_base = NULL;
+	}
+}
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_main.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_main.h
new file mode 100644
index 000000000000..2a3fbd08d128
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_main.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Christopher Chen <christopher.chen at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_IMGSYS_DEBUG_H_
+#define _MTK_IMGSYS_DEBUG_H_
+
+#include "mtk_imgsys-dev.h"
+
+void imgsys_main_init(struct mtk_imgsys_dev *imgsys_dev);
+void imgsys_main_uninit(struct mtk_imgsys_dev *imgsys_dev);
+
+#endif /* _MTK_IMGSYS_DEBUG_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_ops.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_ops.h
index 6dc4b7b60832..a2eea8f4fb3c 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_ops.h
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_ops.h
@@ -24,4 +24,30 @@ enum mtk_imgsys_module {
 	IMGSYS_MOD_MAX,
 };
 
+struct mtk_imgsys_dev;
+
+/**
+ * struct module_ops - Operations for a specific module in the MediaTek Image System
+ * @module_id: Identifier for the module.
+ * @init: Function pointer to initialize the module.
+ *        This function sets the default values for various software-related
+ *        parameters and ensures that the module is ready for operation.
+ *        Example function: imgsys_dip_init
+ * @uninit: Function pointer to uninitialize the module.
+ *          This function resets various software-related parameters to ensure
+ *          the module is properly cleaned up and ready for shutdown.
+ *          Example function: imgsys_dip_uninit
+ *
+ * This structure defines a set of operations for specific modules within the
+ * MediaTek Image System, such as WPE (Warping Engine), TRAW (Tile-Raw),
+ * DIP (Digital Image Processing), PQDIP (Picture Quality Digital Image
+ * Processing), and ME (Motion Estimation). Each module is identified by
+ * a unique identifier and includes function pointers for operations like
+ * initialization and deinitialization.
+ */
+struct module_ops {
+	int module_id;
+	void (*init)(struct mtk_imgsys_dev *imgsys_dev);
+	void (*uninit)(struct mtk_imgsys_dev *imgsys_dev);
+};
 #endif /* _MTK_IMGSYS_MODULES_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.h
index 5088c9df704c..f34ea9465745 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.h
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.h
@@ -12,6 +12,7 @@
 
 #include <linux/clk.h>
 #include "mtk_imgsys-dev.h"
+#include "mtk_imgsys-module_ops.h"
 
 /**
  * struct mtk_imgsys_mod_pipe_desc - Description of a module's pipeline
@@ -31,6 +32,7 @@ struct mtk_imgsys_mod_pipe_desc {
  * @mod_num: Number of modules in the pipeline.
  * @pipe_settings: Pointer to pipeline settings for the module.
  * @pipe_num: Number of pipeline settings.
+ * @imgsys_modules: Pointer to module operations for image system modules.
  */
 struct cust_data {
 	struct clk_bulk_data *clks;
@@ -39,6 +41,7 @@ struct cust_data {
 	unsigned int mod_num;
 	const struct mtk_imgsys_pipe_desc *pipe_settings;
 	unsigned int pipe_num;
+	const struct module_ops *imgsys_modules;
 };
 
 /**
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
index 9cdcdb0a0200..9f118491b37d 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
@@ -6,7 +6,45 @@
  *
  */
 
+#include <linux/pm_runtime.h>
 #include "mtk_imgsys-sys.h"
+#include "mtk_imgsys-dev.h"
+
+static int mtk_imgsys_hw_connect(struct mtk_imgsys_dev *imgsys_dev)
+{
+	int ret, i;
+
+	ret = pm_runtime_get_sync(imgsys_dev->dev);
+	if (ret < 0) {
+		dev_err(imgsys_dev->dev, "Failed to sync runtime PM: %d\n", ret);
+		return ret;
+	}
+
+	/* Set default value for hardware modules */
+	for (i = 0; i < (imgsys_dev->num_mods); i++)
+		imgsys_dev->modules[i].init(imgsys_dev);
+
+	kref_init(&imgsys_dev->init_kref);
+
+	return 0;
+}
+
+static void module_uninit(struct kref *kref)
+{
+	struct mtk_imgsys_dev *imgsys_dev;
+	int i;
+
+	imgsys_dev = container_of(kref, struct mtk_imgsys_dev, init_kref);
+
+	for (i = 0; i < (imgsys_dev->num_mods); i++)
+		if (imgsys_dev->modules[i].uninit)
+			imgsys_dev->modules[i].uninit(imgsys_dev);
+}
+
+static void mtk_imgsys_hw_disconnect(struct mtk_imgsys_dev *imgsys_dev)
+{
+	kref_put(&imgsys_dev->init_kref, module_uninit);
+}
 
 void mtk_imgsys_hw_enqueue(struct mtk_imgsys_dev *imgsys_dev,
 			   struct mtk_imgsys_request *req)
@@ -16,12 +54,43 @@ void mtk_imgsys_hw_enqueue(struct mtk_imgsys_dev *imgsys_dev,
 
 int mtk_imgsys_hw_streamon(struct mtk_imgsys_pipe *pipe)
 {
-	/* Function implementation will be provided in subsequent patches */
+	struct mtk_imgsys_dev *imgsys_dev = pipe->imgsys_dev;
+	int ret;
+
+	mutex_lock(&imgsys_dev->hw_op_lock);
+	if (!imgsys_dev->stream_cnt) {
+		ret = mtk_imgsys_hw_connect(pipe->imgsys_dev);
+		if (ret) {
+			dev_info(pipe->imgsys_dev->dev,
+				 "%s:%s: pipe(%d) connect to dip_hw failed\n",
+				 __func__, pipe->desc->name, pipe->desc->id);
+			mutex_unlock(&imgsys_dev->hw_op_lock);
+			return ret;
+		}
+	}
+	imgsys_dev->stream_cnt++;
+	mutex_unlock(&imgsys_dev->hw_op_lock);
+
+	dev_dbg(pipe->imgsys_dev->dev,
+		"%s:%s: stream on, id(%d), stream cnt(%d)\n",
+		__func__, pipe->desc->name, pipe->desc->id, imgsys_dev->stream_cnt);
+
 	return 0;
 }
 
 int mtk_imgsys_hw_streamoff(struct mtk_imgsys_pipe *pipe)
 {
-	/* Function implementation will be provided in subsequent patches */
+	struct mtk_imgsys_dev *imgsys_dev = pipe->imgsys_dev;
+
+	dev_dbg(pipe->imgsys_dev->dev,
+		"%s:%s: stream off, id(%d), stream cnt(%d)\n",
+		__func__, pipe->desc->name, pipe->desc->id, imgsys_dev->stream_cnt);
+
+	mutex_lock(&imgsys_dev->hw_op_lock);
+	imgsys_dev->stream_cnt--;
+	if (!imgsys_dev->stream_cnt)
+		mtk_imgsys_hw_disconnect(imgsys_dev);
+	mutex_unlock(&imgsys_dev->hw_op_lock);
+
 	return 0;
 }
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
index 919c69493bbc..e25f17b98649 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
@@ -18,8 +18,13 @@
 #include <media/v4l2-subdev.h>
 #include <media/v4l2-event.h>
 #include "linux/mtkisp_imgsys.h"
-#include "mtk_imgsys-of.h"
 #include "mtk_imgsys-module_ops.h"
+#include "mtk_imgsys-module_main.h"
+#include "modules/mtk_imgsys-dip.h"
+#include "modules/mtk_imgsys-traw.h"
+#include "modules/mtk_imgsys-pqdip.h"
+#include "modules/mtk_imgsys-wpe.h"
+#include "mtk_imgsys-of.h"
 #include "mtk_imgsys-vnode_id.h"
 #include "mtk_imgsys_v4l2_vnode.h"
 #include "mtk_imgsys-dev.h"
@@ -1499,6 +1504,7 @@ static int mtk_imgsys_probe(struct platform_device *pdev)
 	init_imgsys_pipeline(data);
 
 	imgsys_dev->cust_pipes = data->pipe_settings;
+	imgsys_dev->modules = data->imgsys_modules;
 	imgsys_dev->dev = &pdev->dev;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1511,6 +1517,8 @@ static int mtk_imgsys_probe(struct platform_device *pdev)
 	dev_set_drvdata(&pdev->dev, imgsys_dev);
 
 	imgsys_dev->num_mods = data->mod_num;
+	imgsys_dev->stream_cnt = 0;
+	mutex_init(&imgsys_dev->hw_op_lock);
 
 	/* Get Clocks */
 	imgsys_dev->clks = data->clks;
@@ -1613,6 +1621,7 @@ static void mtk_imgsys_remove(struct platform_device *pdev)
 	pm_runtime_disable(&pdev->dev);
 	platform_driver_unregister(&mtk_imgsys_larb_driver);
 	mtk_imgsys_dev_v4l2_release(imgsys_dev);
+	mutex_destroy(&imgsys_dev->hw_op_lock);
 	devm_kfree(&pdev->dev, imgsys_dev->larbs);
 	devm_kfree(&pdev->dev, imgsys_dev);
 }
@@ -1709,6 +1718,39 @@ static struct clk_bulk_data imgsys_isp7_clks[] = {
 	{ .id = "ME_CG_LARB12" },
 };
 
+static const struct module_ops imgsys_isp7_modules[] = {
+	[IMGSYS_MOD_IMGMAIN] = {
+		.module_id = IMGSYS_MOD_IMGMAIN,
+		.init = imgsys_main_init,
+		.uninit = imgsys_main_uninit,
+	},
+	[IMGSYS_MOD_WPE] = {
+		.module_id = IMGSYS_MOD_WPE,
+		.init = imgsys_wpe_init,
+		.uninit = imgsys_wpe_uninit,
+	},
+	[IMGSYS_MOD_TRAW] = {
+		.module_id = IMGSYS_MOD_TRAW,
+		.init = imgsys_traw_init,
+		.uninit = imgsys_traw_uninit,
+	},
+	[IMGSYS_MOD_DIP] = {
+		.module_id = IMGSYS_MOD_DIP,
+		.init = imgsys_dip_init,
+		.uninit = imgsys_dip_uninit,
+	},
+	[IMGSYS_MOD_PQDIP] = {
+		.module_id = IMGSYS_MOD_PQDIP,
+		.init = imgsys_pqdip_init,
+		.uninit = imgsys_pqdip_uninit,
+	},
+	[IMGSYS_MOD_ME] = {
+		.module_id = IMGSYS_MOD_ME,
+		.init = NULL,
+		.uninit = NULL,
+	},
+};
+
 static const struct cust_data imgsys_data[] = {
 	[0] = {
 		.clks = imgsys_isp7_clks,
@@ -1717,6 +1759,7 @@ static const struct cust_data imgsys_data[] = {
 		.mod_num = ARRAY_SIZE(module_pipe_isp7),
 		.pipe_settings = pipe_settings_isp7,
 		.pipe_num = ARRAY_SIZE(pipe_settings_isp7),
+		.imgsys_modules = imgsys_isp7_modules,
 	},
 };
 
-- 
2.45.2



From olivia.wen at mediatek.com  Sat May 24 04:49:55 2025
From: olivia.wen at mediatek.com (Olivia Wen)
Date: Sat, 24 May 2025 19:49:55 +0800
Subject: [PATCH v1 03/10] uapi: linux: Add MediaTek Imgsys user API
In-Reply-To: <20250524115144.3832748-1-olivia.wen@mediatek.com>
References: <20250524115144.3832748-1-olivia.wen@mediatek.com>
Message-ID: <20250524115144.3832748-4-olivia.wen@mediatek.com>

Add controls and formats for MediaTek Imgsys processing

Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
---
 include/uapi/linux/mtkisp_imgsys.h | 215 +++++++++++++++++++++++++++++
 1 file changed, 215 insertions(+)
 create mode 100644 include/uapi/linux/mtkisp_imgsys.h

diff --git a/include/uapi/linux/mtkisp_imgsys.h b/include/uapi/linux/mtkisp_imgsys.h
new file mode 100644
index 000000000000..c7528c8bf4a2
--- /dev/null
+++ b/include/uapi/linux/mtkisp_imgsys.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * MediaTek ISP imgsys User space API
+ *
+ * Copyright (c) 2024 MediaTek Inc.
+ */
+
+#ifndef _MTKISP_IMGSYS_USER_H
+#define _MTKISP_IMGSYS_USER_H
+
+#include <linux/v4l2-controls.h>
+
+/******************************************************/
+/*            MediaTek ISP imgsys controls            */
+/******************************************************/
+
+/* The base for the MediaTek imgsys driver controls */
+/* We reserve 48 controls for this driver. */
+#define V4L2_CID_USER_MTK_IMG_BASE		(V4L2_CID_USER_BASE + 0x1100)
+
+/**
+ * Define a control identifier, V4L2_CID_MTK_IMG_RESIZE_RATIO, for setting the
+ * image processing resize ratio for MediaTek chip. This identifier allows
+ * adjustment of the image resize ratio to accommodate various display or
+ * processing needs. ImgSys hardware supports multiple resizers, including
+ * any ratio, downscaling by factors of 2, 4, and 42, with NULL indicating
+ * the end of menu options.
+ */
+#define V4L2_CID_MTK_IMG_RESIZE_RATIO	(V4L2_CID_USER_MTK_IMG_BASE + 34)
+
+/******************************************************/
+/*       Vendor specific - MediaTek ISP formats       */
+/******************************************************/
+
+/* MediaTek warp map 32-bit, 2 plane */
+#define V4L2_PIX_FMT_WARP2P      v4l2_fourcc('M', 'W', '2', 'P')
+/* YUV-10bit packed 4:2:0 2plane, (Y)(UV)  */
+#define V4L2_PIX_FMT_YUV_2P010P    v4l2_fourcc('U', '0', '2', 'A')
+/* YUV-12bit packed 4:2:0 2plane, (Y)(UV)  */
+#define V4L2_PIX_FMT_YUV_2P012P    v4l2_fourcc('U', '0', '2', 'C')
+/* Y-32bit */
+#define V4L2_PIX_FMT_MTISP_Y32   v4l2_fourcc('M', 'T', '3', '2')
+/* Y-16bit */
+#define V4L2_PIX_FMT_MTISP_Y16   v4l2_fourcc('M', 'T', '1', '6')
+/* Y-8bit */
+#define V4L2_PIX_FMT_MTISP_Y8   v4l2_fourcc('M', 'T', '0', '8')
+
+/**
+ * Describes the MediaTek APLY8(V4L2_PIX_FMT_MTISP_APLY8) format, which includes
+ * Y-8bit image data and appends APL(Average Pixel Level) data utilized by the
+ * ME(motion estimation) hardware to the end of the image.
+ *
+ * The hardware ME generates motion vectors by processing two consecutive frames,
+ * referred to as the previous and current frames, to enhance graphic processing.
+ * The diagram is shown below.
+ *
+ *                                     +------------------+
+ *  the thumbnail of previous frame -> |                  |
+ *  (include the L0 frame and L1 frame)|                  |
+ *                                     |        ME        | -> motion vectors
+ *  the thumbnail of current frame  -> |                  |
+ *  (include the L0 frame and L1 frame)|                  |
+ *                                     +------------------+
+ *
+ * To accelerate computation, the two images will be resized into two different
+ * smaller images, referred to as L0 frame, L1 frame and APL data.
+ * The L1 frame is a scaled-down version of the L0 frame, reduced to one-fourth
+ * of its original size containing APL data.
+ *
+ *                                     +------------------+
+ *                previous L0 frame -> |                  |
+ *                previous L1 frame -> |                  |
+ *                (include APL data)   |                  |
+ *                                     |        ME        | -> motion vectors
+ *                current L0 frame  -> |                  |
+ *                current L1 frame  -> |                  |
+ *                (include APL data)   |                  |
+ *                                     +------------------+
+ *
+ * Each frame size:
+ *    the width of L0 frame (L0_wd) = 576 (fixed value)
+ *    the height of L0 frame (L0_ht) =
+ *    16 pixels align((the width of original image * L0_wd) / the height of original image)
+ *    the width of L1 frame (L1_wd) = L0_wd / 4
+ *    the height of L1 frame (L1_ht) = L0_ht / 4
+ *
+ * Buffer size:
+ *    line_size = width * bytes_per_pixel(1)
+ *    stride with 16 bytes alignment = ((line_size + 15) / 16) * 16
+ *    buffer_size = stride with 16 bytes alignment * height + APL data(16 bytes)
+ *
+ * And the memory layout should be followed as
+ *
+ *  @code
+ *           APLY8
+ *    +------------------+
+ *    |     Y Plane      |
+ *    |    Bit Stream    |
+ *    +------------------+
+ *    |      APL data    |
+ *    +------------------+
+ *  @endcode
+ *
+ *  @note The APL data size is 16 bytes.The caller SHOULD NOT modify it.
+ */
+/* Y-8bit image data and append the APL data */
+#define V4L2_PIX_FMT_MTISP_APLY8   v4l2_fourcc('M', 'T', 'A', '8')
+
+/*  Packed 10-bit  */
+#define V4L2_PIX_FMT_MTISP_SBGGR10  v4l2_fourcc('M', 'B', 'B', 'A')
+#define V4L2_PIX_FMT_MTISP_SGBRG10  v4l2_fourcc('M', 'B', 'G', 'A')
+#define V4L2_PIX_FMT_MTISP_SGRBG10  v4l2_fourcc('M', 'B', 'g', 'A')
+#define V4L2_PIX_FMT_MTISP_SRGGB10  v4l2_fourcc('M', 'B', 'R', 'A')
+
+/* Vendor specific - MediaTek ISP parameters for firmware */
+/* ISP tuning parameters */
+#define V4L2_META_FMT_MTISP_TUN_PARAMS  v4l2_fourcc('M', 'T', 'f', 't')
+/* ISP statistics parameters */
+#define V4L2_META_FMT_MTISP_STAT_PARAMS v4l2_fourcc('M', 'T', 'f', 's')
+/* ISP controlling parameters */
+#define V4L2_META_FMT_MTISP_CTL_PARAMS  v4l2_fourcc('M', 'T', 'f', 'c')
+
+/*****************************************************************************/
+/* Define sizes for various formats used in the MediaTek image system driver */
+/*****************************************************************************/
+/**
+ * SIZE_OF_APL_DATA - Size of the APL (Average Pixel Level) data
+ *
+ * This constant defines the size of the APL data, which is 16 bytes.
+ * The APL data is appended to the image format defined by
+ * V4L2_PIX_FMT_MTISP_APLY8. This format includes 8-bit Y image data
+ * followed by the APL data, which is utilized by the motion estimation
+ * hardware for enhanced processing. The APL data provides important
+ * information about the average pixel levels, which can be critical
+ * for various image processing tasks.
+ */
+#define SIZE_OF_APL_DATA 16 /* Size of APL data used by V4L2_PIX_FMT_MTISP_APLY8 */
+
+/**
+ * MediaTek Tuning Metadata Buffer for Image Processing Modules
+ *
+ * This definition is used for format V4L2_META_FMT_MTISP_TUN_PARAMS.
+ * This buffer contains essential tuning information for the MediaTek camera,
+ * including:
+ * - Sensor tuning settings
+ * - Digital gain for adjusting image brightness
+ * - White balance gain
+ *
+ * Note: The individual fields of the tuning metadata structure are not exposed
+ * to the kernel. The kernel only requires the size of the tuning metadata
+ * for memory allocation and management purposes. This encapsulation provides
+ * flexibility in implementing the tuning metadata without impacting the
+ * kernel's interface.
+ */
+ #define SIZE_OF_TUNING_META 219352
+
+/**
+ * MediaTek Control Metadata Buffer for Image Processing Modules
+ *
+ * This definition is used for format V4L2_META_FMT_MTISP_CTL_PARAMS.
+ * The control metadata buffer aggregates control information for multiple
+ * image processing modules, including TRAW, DIP, PQDIP, ME, WPE, and ADL.
+ * It facilitates the configuration and management of these modules by
+ * encapsulating relevant parameters and settings required for processing
+ * image data efficiently. This structure serves as a central point for
+ * coordinating the operation of different hardware components in the image
+ * processing pipeline.
+ *
+ * Note: The individual fields of the control metadata structure are not exposed
+ * to the kernel. The kernel only requires the size of the control metadata
+ * for memory allocation and management purposes. This encapsulation provides
+ * flexibility in implementing the control metadata without impacting the
+ * kernel's interface.
+ */
+#define SIZE_OF_COMMON_CTRL       688
+#define SIZE_OF_WPE_CTRL          240
+#define SIZE_OF_TRAW_CTRL         120
+#define SIZE_OF_DIP_CTRL          112
+#define SIZE_OF_PQDIP_CTRL        112
+#define SIZE_OF_ME_CTRL           8
+#define SIZE_OF_ADL_CTRL          64
+#define SIZE_OF_YUFO_META_INFO_WPE 4228
+#define SIZE_OF_YUFO_META_INFO_DIP 4228
+
+#define SIZE_OF_CTRL_META ( \
+	SIZE_OF_COMMON_CTRL + \
+	SIZE_OF_WPE_CTRL + \
+	SIZE_OF_TRAW_CTRL + \
+	SIZE_OF_DIP_CTRL + \
+	SIZE_OF_PQDIP_CTRL + \
+	SIZE_OF_ME_CTRL + \
+	SIZE_OF_ADL_CTRL + \
+	SIZE_OF_YUFO_META_INFO_WPE + \
+	SIZE_OF_YUFO_META_INFO_DIP \
+)
+
+/**
+ * MediaTek Statistics Metadata Buffer for Image Processing Modules
+ *
+ * This definition is used for format V4L2_META_FMT_MTISP_STAT_PARAMS.
+ * This buffer contains essential statistics information for the MediaTek camera,
+ * including:
+ * - Readiness and corresponding values for tone and contrast statistics
+ * - Motion estimation (ME) statistics
+ * - ME feature match blocks statistics
+ *
+ * Note: The individual fields of the statistics buffer structure are not exposed
+ * to the kernel. The kernel only requires the size of the statistics metadata
+ * for memory allocation and management purposes. This encapsulation provides
+ * flexibility in implementing the statistics metadata without impacting the
+ * kernel's interface.
+ */
+ #define SIZE_OF_STATISTICS_META 88
+
+#endif /* _MTKISP_IMGSYS_USER_H */
-- 
2.45.2



From olivia.wen at mediatek.com  Sat May 24 04:49:53 2025
From: olivia.wen at mediatek.com (Olivia Wen)
Date: Sat, 24 May 2025 19:49:53 +0800
Subject: [PATCH v1 01/10] dt-bindings: media: Add MediaTek mt8188 ImgSys components
In-Reply-To: <20250524115144.3832748-1-olivia.wen@mediatek.com>
References: <20250524115144.3832748-1-olivia.wen@mediatek.com>
Message-ID: <20250524115144.3832748-2-olivia.wen@mediatek.com>

Introduce more Image System (ImgSys) components present in MT8188.

Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
---
 .../bindings/media/mediatek,imgsys.yaml       | 180 ++++++++++++++++++
 1 file changed, 180 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,imgsys.yaml

diff --git a/Documentation/devicetree/bindings/media/mediatek,imgsys.yaml b/Documentation/devicetree/bindings/media/mediatek,imgsys.yaml
new file mode 100644
index 000000000000..c2899c4b227b
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,imgsys.yaml
@@ -0,0 +1,180 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,imgsys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Camera Image System
+
+maintainers:
+  - Olivia Wen <olivia.wen at mediatek.com>
+
+description:
+  MediaTek Camera Image System is the image processing hardware present in MediaTek SoCs
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt8188-isp-imgsys
+
+  reg:
+    minItems: 1
+    maxItems: 17
+
+  clocks:
+    minItems: 1
+    maxItems: 17
+
+  clock-names:
+    minItems: 1
+    maxItems: 17
+
+  assigned-clocks: true
+
+  assigned-clock-parents: true
+
+  '#address-cells':
+    const: 2
+
+  '#size-cells':
+    const: 2
+
+  iommus:
+    minItems: 1
+    maxItems: 30
+
+  mediatek,larbs:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 32
+    items:
+      maxItems: 1
+    description: |
+      List of phandle to the local arbiters in the current Socs.
+      Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
+      according to the local arbiter index, like larb0, larb1, larb2...
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - iommus
+  - mediatek,larbs
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          enum:
+            - mediatek,mt8188-isp-imgsys
+
+    then:
+      required:
+        - compatible
+        - reg
+        - clocks
+        - clock-names
+        - iommus
+        - mediatek,larbs
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mediatek,mt8188-clk.h>
+    #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
+
+    imgsys_fw: imgsys-fw at 15000000 {
+        compatible = "mediatek,mt8188-isp-imgsys";
+        reg = <0 0x15000000 0 0x4000>,  /* 0 IMGSYS_TOP */
+              <0 0x15020000 0 0x10000>, /* 1 IMGSYS_TRAW */
+              <0 0x15040000 0 0x10000>, /* 2 IMGSYS_LTRAW */
+              <0 0x15640000 0 0x10000>, /* 3 IMGSYS_XTRAW */
+              <0 0x15100000 0 0x10000>, /* 4 IMGSYS_DIP */
+              <0 0x15150000 0 0x10000>, /* 5 IMGSYS_DIP_NR */
+              <0 0x15210000 0 0x10000>, /* 6 IMGSYS_PQDIP_A */
+              <0 0x15510000 0 0x10000>,	/* 7 IMGSYS_PQDIP_B */
+              <0 0x15200000 0 0x10000>,	/* 8 IMGSYS_WPE_EIS */
+              <0 0x15500000 0 0x10000>,	/* 9 IMGSYS_WPE_TNR */
+              <0 0x15600000 0 0x10000>,	/* 10 IMGSYS_WPE_LITE */
+              <0 0x15220000 0 0x00100>,	/* 11 IMGSYS_WPE1_DIP1 */
+              <0 0x15320000 0 0x10000>,	/* 12 IMGSYS_ME */
+              <0 0x15520000 0 0x00100>,	/* 13 IMGSYS_WPE2_DIP1 */
+              <0 0x15620000 0 0x00100>,	/* 14 IMGSYS_WPE3_DIP1 */
+              <0 0x15110000 0 0x00100>,	/* 15 IMGSYS_DIP_TOP */
+              <0 0x15130000 0 0x00100>;	/* 16 IMGSYS_DIP_TOP_NR */
+
+        assigned-clocks = <&topckgen CLK_TOP_IMG>;
+        assigned-clock-parents = <&apmixedsys CLK_APMIXED_IMGPLL>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        clocks = <&imgsys CLK_IMGSYS_MAIN_TRAW0>,
+             <&imgsys CLK_IMGSYS_MAIN_TRAW1>,
+             <&imgsys CLK_IMGSYS_MAIN_VCORE_GALS>,
+             <&imgsys CLK_IMGSYS_MAIN_DIP0>,
+             <&imgsys CLK_IMGSYS_MAIN_WPE0>,
+             <&imgsys CLK_IMGSYS_MAIN_WPE1>,
+             <&imgsys CLK_IMGSYS_MAIN_WPE2>,
+             <&imgsys CLK_IMGSYS_MAIN_GALS>,
+             <&imgsys1_dip_top CLK_IMGSYS1_DIP_TOP_DIP_TOP>,
+             <&imgsys1_dip_nr CLK_IMGSYS1_DIP_NR_DIP_NR>,
+             <&imgsys_wpe1 CLK_IMGSYS_WPE1>,
+             <&imgsys_wpe2 CLK_IMGSYS_WPE2>,
+             <&imgsys_wpe3 CLK_IMGSYS_WPE3>,
+             <&imgsys CLK_IMGSYS_MAIN_IPE>,
+             <&ipesys CLK_IPESYS_TOP>,
+             <&ipesys CLK_IPE_ME>,
+             <&ipesys CLK_IPE_SMI_LARB12>;
+        clock-names = "IMGSYS_CG_IMG_TRAW0",
+                  "IMGSYS_CG_IMG_TRAW1",
+                  "IMGSYS_CG_IMG_VCORE_GALS",
+                  "IMGSYS_CG_IMG_DIP0",
+                  "IMGSYS_CG_IMG_WPE0",
+                  "IMGSYS_CG_IMG_WPE1",
+                  "IMGSYS_CG_IMG_WPE2",
+                  "IMGSYS_CG_IMG_GALS",
+                  "DIP_TOP_DIP_TOP",
+                  "DIP_NR_DIP_NR",
+                  "WPE1_CG_DIP1_WPE",
+                  "WPE2_CG_DIP1_WPE",
+                  "WPE3_CG_DIP1_WPE",
+                  "ME_CG_IPE",
+                  "ME_CG_IPE_TOP",
+                  "ME_CG",
+                  "ME_CG_LARB12";
+
+        iommus = <&vdo_iommu M4U_PORT_L9_IMGI_T1_A>,
+                 <&vdo_iommu M4U_PORT_L9_UFDI_T1_A>,
+                 <&vdo_iommu M4U_PORT_L9_IMGBI_T1_A>,
+                 <&vdo_iommu M4U_PORT_L9_IMGCI_T1_A>,
+                 <&vdo_iommu M4U_PORT_L9_SMTI_T1_A>,
+                 <&vdo_iommu M4U_PORT_L9_SMTI_T4_A>,
+                 <&vdo_iommu M4U_PORT_L9_TNCSTI_T1_A>,
+                 <&vdo_iommu M4U_PORT_L9_TNCSTI_T4_A>,
+                 <&vdo_iommu M4U_PORT_L9_YUVO_T1_A>,
+                 <&vdo_iommu M4U_PORT_L9_YUVBO_T1_A>,
+                 <&vdo_iommu M4U_PORT_L9_YUVCO_T1_A>,
+                 <&vdo_iommu M4U_PORT_L9_TIMGO_T1_A>,
+                 <&vdo_iommu M4U_PORT_L9_YUVO_T2_A>,
+                 <&vdo_iommu M4U_PORT_L9_YUVO_T5_A>,
+                 <&vdo_iommu M4U_PORT_L9_IMGI_T1_B>,
+                 <&vdo_iommu M4U_PORT_L9_IMGBI_T1_B>,
+                 <&vdo_iommu M4U_PORT_L9_IMGCI_T1_B>,
+                 <&vdo_iommu M4U_PORT_L9_SMTI_T4_B>,
+                 <&vdo_iommu M4U_PORT_L9_TNCSO_T1_A>,
+                 <&vdo_iommu M4U_PORT_L9_SMTO_T1_A>,
+                 <&vdo_iommu M4U_PORT_L9_SMTO_T4_A>,
+                 <&vdo_iommu M4U_PORT_L9_TNCSTO_T1_A>,
+                 <&vdo_iommu M4U_PORT_L9_YUVO_T2_B>,
+                 <&vdo_iommu M4U_PORT_L9_YUVO_T5_B>,
+                 <&vdo_iommu M4U_PORT_L9_SMTO_T4_B>;
+
+        mediatek,larbs = <&larb9>,
+                         <&larb10>,
+                         <&larb11a>,
+                         <&larb11b>,
+                         <&larb11c>,
+                         <&larb15>,
+                         <&larb12>;
+    };
-- 
2.45.2



From olivia.wen at mediatek.com  Sat May 24 04:49:52 2025
From: olivia.wen at mediatek.com (Olivia Wen)
Date: Sat, 24 May 2025 19:49:52 +0800
Subject: [PATCH v1 00/10] Add MediaTek ISP7 Image Syatem driver
Message-ID: <20250524115144.3832748-1-olivia.wen@mediatek.com>

Dear Maintainers,

I am pleased to submit this patch series that introduces the MediaTek
ISP7 Image System driver. This series consists of ten patches that
collectively add support for various components and functionalities of
the ISP7 architecture. The patches include device tree bindings, user
API definitions, V4L2 flow support, LARB device integration, CMDQ
support, SCP support, and image processing flows.

MediaTek's Image System (ImgSys), also known as ISP Pass2, is a
memory-to-memory hardware device designed for advanced image processing
tasks. ImgSys includes multiple hardware components such as TRAW, DIP,
PQDIP, ME, and WPE.

- **TRAW (Tile RAW)**:
  Provides multiple downscaled resizers for multi-scale noise reduction
  and supports RAW/RGB format conversion.

- **DIP (Digital Image Processing) and PQDIP (Picture Quality DIP)**:
  Supports temporal and spatial noise reduction (TNR/SNR), edge
  enhancement (EE), sharpness (SHP), image scaling, and rotation.

- **ME (Motion Estimation)**:
  Supports motion estimation between consecutive frames.

- **WPE (Warping Engine)**:
  Handles image warping and de-warping processes.

ImgSys utilizes Multi-Frame Combined Noise Reduction (MCNR) technology to
enhance image quality.

Below is a simplified architecture of the ImgSys driver:
User -> V4L2 Framework -> ImgSys Driver
     -> SCP (It packages the hardware settings into commands)
     -> ImgSys Driver
     -> CMDQ (The packaged commands are sent to the hardware via GCE)
     -> Hardware

Thease patches are base on linux-next/master, tag: next-20250523
Thank you for reviewing these patches.

Olivia Wen (10):
  dt-bindings: media: Add MediaTek mt8188 ImgSys components
  dt-bindings: media: Add MT8188 ImgSys's LARB
  uapi: linux: Add MediaTek Imgsys user API
  media: mediatek: isp: Add V4L2 flow support for ImgSys driver
  media: mediatek: isp: Add the Imgsys LARBs device
  media: mediatek: isp: Add module operations structure for ImgSys
  media: mediatek: isp: Add CMDQ support for ImgSys driver
  media: mediatek: isp: Add SCP support for ImgSys driver
  media: mediatek: isp: Add image processing flow
  media: mediatek: isp: Add normal data dump flow

 .../bindings/media/mediatek,imgsys-larbs.yaml |   75 +
 .../bindings/media/mediatek,imgsys.yaml       |  180 ++
 drivers/media/platform/mediatek/Kconfig       |    1 +
 drivers/media/platform/mediatek/Makefile      |    1 +
 drivers/media/platform/mediatek/isp/Kconfig   |   23 +
 .../platform/mediatek/isp/isp_7x/Makefile     |    6 +
 .../mediatek/isp/isp_7x/imgsys/Makefile       |   25 +
 .../imgsys/modules/mtk_dip_v4l2_vnode.h       |  594 +++++
 .../isp_7x/imgsys/modules/mtk_imgsys-dip.c    |  162 ++
 .../isp_7x/imgsys/modules/mtk_imgsys-dip.h    |   21 +
 .../isp/isp_7x/imgsys/modules/mtk_imgsys-me.c |   65 +
 .../isp/isp_7x/imgsys/modules/mtk_imgsys-me.h |   30 +
 .../isp_7x/imgsys/modules/mtk_imgsys-pqdip.c  |  165 ++
 .../isp_7x/imgsys/modules/mtk_imgsys-pqdip.h  |   20 +
 .../isp_7x/imgsys/modules/mtk_imgsys-traw.c   |  120 ++
 .../isp_7x/imgsys/modules/mtk_imgsys-traw.h   |   20 +
 .../isp_7x/imgsys/modules/mtk_imgsys-wpe.c    |  176 ++
 .../isp_7x/imgsys/modules/mtk_imgsys-wpe.h    |   20 +
 .../isp_7x/imgsys/modules/mtk_me_v4l2_vnode.h |  386 ++++
 .../imgsys/modules/mtk_pqdip_v4l2_vnode.h     |  149 ++
 .../imgsys/modules/mtk_traw_v4l2_vnode.h      |  371 ++++
 .../imgsys/modules/mtk_wpe_v4l2_vnode.h       |  317 +++
 .../mediatek/isp/isp_7x/imgsys/mtk-img-ipi.h  |  151 ++
 .../isp/isp_7x/imgsys/mtk_header_desc.h       |  129 ++
 .../isp/isp_7x/imgsys/mtk_imgsys-cmdq-plat.h  |  502 +++++
 .../isp/isp_7x/imgsys/mtk_imgsys-cmdq.c       |  690 ++++++
 .../isp/isp_7x/imgsys/mtk_imgsys-cmdq.h       |   29 +
 .../isp/isp_7x/imgsys/mtk_imgsys-dev.c        |  299 +++
 .../isp/isp_7x/imgsys/mtk_imgsys-dev.h        |  570 +++++
 .../isp/isp_7x/imgsys/mtk_imgsys-formats.c    |  139 ++
 .../isp/isp_7x/imgsys/mtk_imgsys-formats.h    |   72 +
 .../isp/isp_7x/imgsys/mtk_imgsys-gce_work.c   |   86 +
 .../isp/isp_7x/imgsys/mtk_imgsys-gce_work.h   |   37 +
 .../isp_7x/imgsys/mtk_imgsys-module_common.h  |  102 +
 .../isp_7x/imgsys/mtk_imgsys-module_main.c    |  187 ++
 .../isp_7x/imgsys/mtk_imgsys-module_main.h    |   17 +
 .../isp/isp_7x/imgsys/mtk_imgsys-module_ops.h |   64 +
 .../isp_7x/imgsys/mtk_imgsys-ndd_debugfs.c    |  342 +++
 .../isp_7x/imgsys/mtk_imgsys-ndd_debugfs.h    |   64 +
 .../isp/isp_7x/imgsys/mtk_imgsys-of.c         |   39 +
 .../isp/isp_7x/imgsys/mtk_imgsys-of.h         |   58 +
 .../isp/isp_7x/imgsys/mtk_imgsys-scp.c        |  349 +++
 .../isp/isp_7x/imgsys/mtk_imgsys-scp.h        |  194 ++
 .../isp/isp_7x/imgsys/mtk_imgsys-sys.c        |  556 +++++
 .../isp/isp_7x/imgsys/mtk_imgsys-sys.h        |   50 +
 .../isp/isp_7x/imgsys/mtk_imgsys-v4l2.c       | 1919 +++++++++++++++++
 .../isp/isp_7x/imgsys/mtk_imgsys-vnode_id.h   |  100 +
 .../isp/isp_7x/imgsys/mtk_imgsys-work_buf.c   |  113 +
 .../isp/isp_7x/imgsys/mtk_imgsys-work_buf.h   |   55 +
 .../isp/isp_7x/imgsys/mtk_imgsys_v4l2_vnode.h |  135 ++
 include/uapi/linux/mtkisp_imgsys.h            |  215 ++
 51 files changed, 10190 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,imgsys-larbs.yaml
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,imgsys.yaml
 create mode 100644 drivers/media/platform/mediatek/isp/Kconfig
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/Makefile
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_dip_v4l2_vnode.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-me.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-me.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_me_v4l2_vnode.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_pqdip_v4l2_vnode.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_traw_v4l2_vnode.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_wpe_v4l2_vnode.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk-img-ipi.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_header_desc.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-cmdq-plat.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-cmdq.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-cmdq.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-formats.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-formats.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-gce_work.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-gce_work.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_common.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_main.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_main.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_ops.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-ndd_debugfs.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-ndd_debugfs.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-scp.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-scp.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-vnode_id.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-work_buf.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-work_buf.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys_v4l2_vnode.h
 create mode 100644 include/uapi/linux/mtkisp_imgsys.h

-- 
2.45.2



From olivia.wen at mediatek.com  Sat May 24 04:50:00 2025
From: olivia.wen at mediatek.com (Olivia Wen)
Date: Sat, 24 May 2025 19:50:00 +0800
Subject: [PATCH v1 08/10] media: mediatek: isp: Add SCP support for ImgSys driver
In-Reply-To: <20250524115144.3832748-1-olivia.wen@mediatek.com>
References: <20250524115144.3832748-1-olivia.wen@mediatek.com>
Message-ID: <20250524115144.3832748-9-olivia.wen@mediatek.com>

The ImgSys driver is implemented as a series of patches, with this patch
focusing on the SCP support for ImgSys driver. It covers the memory
allocation and transmission interfaces required by SCP. Frame-related
information is transmitted to SCP, where it is packaged into commands
and the necessary hardware information. These commands are then sent to
the kernel for further processing.

Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
---
 .../mediatek/isp/isp_7x/imgsys/Makefile       |   1 +
 .../mediatek/isp/isp_7x/imgsys/mtk-img-ipi.h  | 143 +++++++
 .../isp/isp_7x/imgsys/mtk_imgsys-scp.c        | 349 ++++++++++++++++++
 .../isp/isp_7x/imgsys/mtk_imgsys-scp.h        | 194 ++++++++++
 4 files changed, 687 insertions(+)
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk-img-ipi.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-scp.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-scp.h

diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
index c0f0f3a0c38a..29c18c773fdc 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
@@ -3,6 +3,7 @@
 
 mtk_imgsys_util-objs := \
 mtk_imgsys-cmdq.o \
+mtk_imgsys-scp.o \
 mtk_imgsys-module_main.o \
 mtk_imgsys-of.o \
 mtk_imgsys-formats.o \
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk-img-ipi.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk-img-ipi.h
new file mode 100644
index 000000000000..850f6ec99a96
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk-img-ipi.h
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_IMG_IPI_H__
+#define __MTK_IMG_IPI_H__
+
+#include <linux/types.h>
+#include "mtk_header_desc.h"
+
+#define HEADER_VER 19481
+#define IMG_MAX_HW_DMAS 72
+#define IMG_MAX_HW 12
+#define WPE_ENG_NUM 3
+#define TMAX 16
+
+/**
+ * enum img_module_id - Enumeration of image processing module IDs
+ * @IMG_MODULE_WPE: ID for the WPE (Warp Engine) module
+ * @IMG_MODULE_TRAW: ID for the TRAW (Tile Raw) module
+ * @IMG_MODULE_DIP: ID for the DIP (Digital Image Processing) module
+ * @IMG_MODULE_PQDIP: ID for the PQDIP (Picture Quality Digital Image Processing) module
+ * @IMG_MODULE_MAX: Maximum ID value, used for boundary checking
+ */
+enum img_module_id {
+	IMG_MODULE_WPE = 0,
+	IMG_MODULE_TRAW = 1,
+	IMG_MODULE_DIP = 2,
+	IMG_MODULE_PQDIP = 3,
+	IMG_MODULE_MAX = 4,
+};
+
+/**
+ * struct module_init_info - Information about module initialization
+ * @c_wbuf: Command queue (CQ) working buffer address
+ * @c_wbuf_dma: DMA address of the CQ working buffer
+ * @c_wbuf_sz: Size of the CQ working buffer
+ * @t_wbuf: Tile dirvier (TDR) working buffer address
+ * @t_wbuf_dma: DMA address of the TDR working buffer
+ * @t_wbuf_sz: Size of the TDR working buffer
+ */
+struct module_init_info {
+	u64 c_wbuf;         /* CQ working buffer address */
+	u64 c_wbuf_dma;     /* DMA address of the CQ working buffer */
+	u32 c_wbuf_sz;      /* Size of the CQ working buffer */
+	u64 t_wbuf;         /* TDR working buffer address */
+	u64 t_wbuf_dma;     /* DMA address of the TDR working buffer */
+	u32 t_wbuf_sz;      /* Size of the TDR working buffer */
+} __packed;
+
+/**
+ * struct img_init_info - Information about image initialization
+ * @header_version: Version of the header
+ * @isp_version: ISP version
+ * @frameparam_size: Size of the frame parameters
+ * @module_info: Array of module working buffer information
+ * @g_wbuf: Global Command Engine (GCE) working buffer address
+ * @g_wbuf_sz: Size of the GCE working buffer
+ *
+ * This structure is used as the parameter for IPI_IMGSYS_INIT_ID and
+ * IPI_IMGSYS_DEINIT_ID. It contains information necessary for initializing and
+ * deinitializing the image system.
+ */
+struct img_init_info {
+	u32	header_version;
+	u32	isp_version;
+	u32	frameparam_size;
+	struct module_init_info module_info[IMG_MODULE_MAX];
+	u64	g_wbuf;
+	u32	g_wbuf_sz;
+} __packed;
+
+/**
+ * struct img_swfrm_info - Software frame information structure for image system
+ * @hw_comb: Hardware combination, which used to store the combination of
+ * enum mtk_imgsys_engine_bitmask
+ * @sw_ridx: Software read index, provided to SCP upon notification to access
+ * GCE buffer location
+ * @is_time_shared: Indicates if the frame is time-shared
+ * @is_earlycb: Indicates if early callback is enabled
+ * @sw_goft: offset of GCE buffer
+ * @g_swbuf: virtual address of GCE buffer
+ *
+ * These fields are primarily set by SCP (System Control Processor) and used by
+ * the kernel for processing and verifing data.
+ */
+struct img_swfrm_info {
+	u32 hw_comb;
+	int sw_ridx;
+	u8 is_time_shared;
+	u8 is_earlycb;
+	u64 sw_goft;
+	void *g_swbuf;
+} __packed;
+
+/**
+ * struct img_ipi_frameparam - Frame parameters for IMGSYS IPI
+ * @dmas_enable: Array indicating enabled DMAs for each hardware unit
+ * @dmas: Array of DMA descriptors for each hardware unit
+ * @tuning_meta: Descriptor for tuning metadata
+ * @ctrl_meta: Descriptor for control metadata
+ *
+ * This structure defines the frame parameters used in the IMGSYS IPI
+ * (Inter-Processor Interface). It includes arrays to indicate enabled DMAs and
+ * their descriptors, as well as descriptors for tuning and control metadata.
+ */
+struct img_ipi_frameparam {
+	u8 dmas_enable[IMG_MAX_HW_DMAS];
+	struct header_desc_norm	dmas[IMG_MAX_HW_DMAS];
+	struct header_desc_norm	tuning_meta;
+	struct header_desc_norm	ctrl_meta;
+};
+
+/**
+ * struct img_sw_buffer - Software buffer address information
+ * @scp_addr: Physical address accessed by SCP
+ * @offset: Address offset
+ *
+ * This structure defines the address information of a software buffer used in
+ * the SCP.
+ */
+struct img_sw_buffer {
+	u32	scp_addr;
+	u32	offset;
+} __packed;
+
+/**
+ * struct img_ipi_param - Parameters for IMGSYS IPI
+ * @frm_param: Software buffer adreess for frame parameters
+ * @req_addr_va: Virtual address for the request
+ *
+ * This structure defines the parameters used in the IMGSYS IPI, including a
+ * software buffer physical address for frame parameters and a virtual address
+ * for the request.
+ */
+struct img_ipi_param {
+	struct img_sw_buffer frm_param;
+	u64	req_addr_va;
+} __packed;
+
+#endif  /* __MTK_IMG_IPI_H__ */
+
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-scp.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-scp.c
new file mode 100644
index 000000000000..4e6126d9f28c
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-scp.c
@@ -0,0 +1,349 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+#include <linux/slab.h>
+#include <linux/remoteproc.h>
+#include <linux/dma-direction.h>
+#include "mtk_imgsys-cmdq.h"
+#include "mtk_imgsys-scp.h"
+
+#define SCP_TIMEOUT_MS          4000U
+
+/**
+ * struct mtk_scp_reserve_memblock - Represents a memory block reserved by the
+ * kernel for usage by the SCP (System Control Processor).
+ *
+ * @id:         Unique identifier for the memory block. This ID is used to
+ *              reference and manage the memory block within the system.
+ * @start_phys: Physical address the starting point of the buffer.
+ * @start_virt: Kernel virtual address of the starting point of the buffer.
+ * @start_dma:  DMA (Direct Memory Access) address of the starting point of the
+ *              buffer.
+ * @size:       Size of the allocated buffer, in bytes.
+ * @dma_dir:	Direction of DMA data transfer, indicating whether the data is
+ *				being transferred to the device, from the device, or
+ *				bidirectionally.
+ */
+struct mtk_scp_reserve_memblock {
+	unsigned int id;
+	phys_addr_t start_phys;
+	void *start_virt;
+	phys_addr_t start_dma;
+	unsigned int size;
+	enum dma_data_direction dma_dir;
+};
+
+/* Array of reserved memory blocks for various hardware components */
+static struct mtk_scp_reserve_memblock reserve_memblock[] = {
+	{
+		/*WPE CQ buffer for WPE HW usage*/
+		.id = WPE_MEM_C_ID,
+		.start_phys = 0x0,
+		.start_virt = NULL,
+		.start_dma  = 0x0,
+		.size = 0xE1000,   /*900KB*/
+		.dma_dir = DMA_TO_DEVICE,
+	},
+	{
+		/*WPE TDR buffer for tile driver usage*/
+		.id = WPE_MEM_T_ID,
+		.start_phys = 0x0,
+		.start_virt = NULL,
+		.start_dma  = 0x0,
+		.size = 0x196000,   /*1MB + 600KB*/
+		.dma_dir = DMA_TO_DEVICE,
+	},
+	{
+		/*TRAW CQ buffer for TRAW driver usage*/
+		.id = TRAW_MEM_C_ID,
+		.start_phys = 0x0,
+		.start_virt = NULL,
+		.start_dma  = 0x0,
+		.size = 0x4C8000,   /*4MB + 800KB*/
+		.dma_dir = DMA_TO_DEVICE,
+	},
+	{
+		/*TRAW TDR buffer for tile driver usage*/
+		.id = TRAW_MEM_T_ID,
+		.start_phys = 0x0,
+		.start_virt = NULL,
+		.start_dma  = 0x0,
+		.size = 0x1AC8000,   /*26MB + 800KB*/
+		.dma_dir = DMA_TO_DEVICE,
+	},
+	{
+		/*DIP CQ buffer for TRAW HW usage*/
+		.id = DIP_MEM_C_ID,
+		.start_phys = 0x0,
+		.start_virt = NULL,
+		.start_dma  = 0x0,
+		.size = 0x5C8000,   /*5MB + 800KB*/
+		.dma_dir = DMA_TO_DEVICE,
+	},
+	{
+		/*DIP TDR buffer for tile driver usage*/
+		.id = DIP_MEM_T_ID,
+		.start_phys = 0x0,
+		.start_virt = NULL,
+		.start_dma  = 0x0,
+		.size = 0x1FAF000,   /*31MB + 700KB*/
+		.dma_dir = DMA_TO_DEVICE,
+	},
+	{
+		/*PQDIP CQ buffer for TRAW HW usage*/
+		.id = PQDIP_MEM_C_ID,
+		.start_phys = 0x0,
+		.start_virt = NULL,
+		.start_dma  = 0x0,
+		.size = 0x100000,   /*1MB*/
+		.dma_dir = DMA_TO_DEVICE,
+	},
+	{
+		/*PQDIP TDR buffer for tile driver usage*/
+		.id = PQDIP_MEM_T_ID,
+		.start_phys = 0x0,
+		.start_virt = NULL,
+		.start_dma  = 0x0,
+		.size = 0x170000,   /*1MB + 500KB*/
+		.dma_dir = DMA_TO_DEVICE,
+	},
+	{
+		/*GCE command buffer for GCE HW usage*/
+		.id = IMG_MEM_G_ID,
+		.start_phys = 0x0,
+		.start_virt = NULL,
+		.start_dma  = 0x0,
+		.size = 0x1800000,
+		.dma_dir = DMA_BIDIRECTIONAL,
+	},
+};
+
+static phys_addr_t imgsys_scp_get_reserve_mem_phys(enum img_mem_id id)
+{
+	if (id >= IMG_MEM_ID_COUNT) {
+		pr_err("[SCP] no reserve memory for %d", id);
+		return 0;
+	}
+	return reserve_memblock[id].start_phys;
+}
+
+static phys_addr_t imgsys_scp_get_reserve_mem_dma(enum img_mem_id id)
+{
+	if (id >= IMG_MEM_ID_COUNT) {
+		pr_err("[SCP] no reserve memory for %d", id);
+		return 0;
+	}
+	return reserve_memblock[id].start_dma;
+}
+
+void *imgsys_scp_get_reserve_mem_virt(enum img_mem_id id)
+{
+	if (id >= IMG_MEM_ID_COUNT)
+		return NULL;
+	else
+		return reserve_memblock[id].start_virt;
+}
+EXPORT_SYMBOL(imgsys_scp_get_reserve_mem_virt);
+
+unsigned int imgsys_scp_get_reserve_mem_size(enum img_mem_id id)
+{
+	if (id >= IMG_MEM_ID_COUNT) {
+		pr_err("[SCP] no reserve memory for %d", id);
+		return 0;
+	}
+	return reserve_memblock[id].size;
+}
+
+int imgsys_scp_alloc_reserve_mem(struct mtk_imgsys_dev *imgsys_dev)
+{
+	enum img_mem_id id;
+	unsigned int block_num;
+	void *ptr;
+	dma_addr_t addr;
+
+	block_num = ARRAY_SIZE(reserve_memblock);
+	for (id = 0; id < block_num; id++) {
+		ptr = dma_alloc_coherent(imgsys_dev->smem_dev,
+					 reserve_memblock[id].size,
+					 &addr, GFP_KERNEL);
+		if (!ptr)
+			return -ENOMEM;
+
+		reserve_memblock[id].start_virt = ptr;
+		reserve_memblock[id].start_phys = addr;
+		reserve_memblock[id].start_dma =
+			dma_map_resource(imgsys_dev->dev, addr,
+					 reserve_memblock[id].size,
+					 reserve_memblock[id].dma_dir,
+					 DMA_ATTR_SKIP_CPU_SYNC);
+		if (dma_mapping_error(imgsys_dev->dev,
+				      reserve_memblock[id].start_dma)) {
+			dev_err(imgsys_dev->dev, "failed to map scp iova\n");
+			return -ENOMEM;
+		}
+	}
+
+	return 0;
+}
+
+int imgsys_scp_free_reserve_mem(struct mtk_imgsys_dev *imgsys_dev)
+{
+	enum img_mem_id id;
+
+	/* release reserved memory */
+	for (id = 0; id < IMG_MEM_ID_COUNT; id++) {
+		dma_unmap_resource(imgsys_dev->dev,
+				   reserve_memblock[id].start_dma,
+				   reserve_memblock[id].size,
+				   reserve_memblock[id].dma_dir,
+				   DMA_ATTR_SKIP_CPU_SYNC);
+		dma_free_coherent(imgsys_dev->smem_dev,
+				  reserve_memblock[id].size,
+				  reserve_memblock[id].start_virt,
+				  reserve_memblock[id].start_phys);
+
+		reserve_memblock[id].start_dma = 0x0;
+		reserve_memblock[id].start_virt = NULL;
+		reserve_memblock[id].start_phys = 0x0;
+	}
+
+	return 0;
+}
+
+int imgsys_scp_get_reserve_mem_info(struct img_init_info *info)
+{
+	if (!info) {
+		pr_err("%s:NULL info\n", __func__);
+		return -EINVAL;
+	}
+
+	/* WPE */
+	info->module_info[IMG_MODULE_WPE].c_wbuf =
+				imgsys_scp_get_reserve_mem_phys(WPE_MEM_C_ID);
+	info->module_info[IMG_MODULE_WPE].c_wbuf_dma =
+				imgsys_scp_get_reserve_mem_dma(WPE_MEM_C_ID);
+	info->module_info[IMG_MODULE_WPE].c_wbuf_sz =
+				imgsys_scp_get_reserve_mem_size(WPE_MEM_C_ID);
+	info->module_info[IMG_MODULE_WPE].t_wbuf =
+				imgsys_scp_get_reserve_mem_phys(WPE_MEM_T_ID);
+	info->module_info[IMG_MODULE_WPE].t_wbuf_dma =
+				imgsys_scp_get_reserve_mem_dma(WPE_MEM_T_ID);
+	info->module_info[IMG_MODULE_WPE].t_wbuf_sz =
+				imgsys_scp_get_reserve_mem_size(WPE_MEM_T_ID);
+
+	/* TRAW */
+	info->module_info[IMG_MODULE_TRAW].c_wbuf =
+				imgsys_scp_get_reserve_mem_phys(TRAW_MEM_C_ID);
+	info->module_info[IMG_MODULE_TRAW].c_wbuf_dma =
+				imgsys_scp_get_reserve_mem_dma(TRAW_MEM_C_ID);
+	info->module_info[IMG_MODULE_TRAW].c_wbuf_sz =
+				imgsys_scp_get_reserve_mem_size(TRAW_MEM_C_ID);
+	info->module_info[IMG_MODULE_TRAW].t_wbuf =
+				imgsys_scp_get_reserve_mem_phys(TRAW_MEM_T_ID);
+	info->module_info[IMG_MODULE_TRAW].t_wbuf_dma =
+				imgsys_scp_get_reserve_mem_dma(TRAW_MEM_T_ID);
+	info->module_info[IMG_MODULE_TRAW].t_wbuf_sz =
+				imgsys_scp_get_reserve_mem_size(TRAW_MEM_T_ID);
+
+	/* DIP */
+	info->module_info[IMG_MODULE_DIP].c_wbuf =
+				imgsys_scp_get_reserve_mem_phys(DIP_MEM_C_ID);
+	info->module_info[IMG_MODULE_DIP].c_wbuf_dma =
+				imgsys_scp_get_reserve_mem_dma(DIP_MEM_C_ID);
+	info->module_info[IMG_MODULE_DIP].c_wbuf_sz =
+				imgsys_scp_get_reserve_mem_size(DIP_MEM_C_ID);
+	info->module_info[IMG_MODULE_DIP].t_wbuf =
+				imgsys_scp_get_reserve_mem_phys(DIP_MEM_T_ID);
+	info->module_info[IMG_MODULE_DIP].t_wbuf_dma =
+				imgsys_scp_get_reserve_mem_dma(DIP_MEM_T_ID);
+	info->module_info[IMG_MODULE_DIP].t_wbuf_sz =
+				imgsys_scp_get_reserve_mem_size(DIP_MEM_T_ID);
+
+	/* PQDIP */
+	info->module_info[IMG_MODULE_PQDIP].c_wbuf =
+				imgsys_scp_get_reserve_mem_phys(PQDIP_MEM_C_ID);
+	info->module_info[IMG_MODULE_PQDIP].c_wbuf_dma =
+				imgsys_scp_get_reserve_mem_dma(PQDIP_MEM_C_ID);
+	info->module_info[IMG_MODULE_PQDIP].c_wbuf_sz =
+				imgsys_scp_get_reserve_mem_size(PQDIP_MEM_C_ID);
+	info->module_info[IMG_MODULE_PQDIP].t_wbuf =
+				imgsys_scp_get_reserve_mem_phys(PQDIP_MEM_T_ID);
+	info->module_info[IMG_MODULE_PQDIP].t_wbuf_dma =
+				imgsys_scp_get_reserve_mem_dma(PQDIP_MEM_T_ID);
+	info->module_info[IMG_MODULE_PQDIP].t_wbuf_sz =
+				imgsys_scp_get_reserve_mem_size(PQDIP_MEM_T_ID);
+
+	/* GCE command */
+	info->g_wbuf = imgsys_scp_get_reserve_mem_phys(IMG_MEM_G_ID);
+	info->g_wbuf_sz = imgsys_scp_get_reserve_mem_size(IMG_MEM_G_ID);
+
+	return 0;
+}
+
+int imgsys_scp_init(struct mtk_imgsys_dev *imgsys_dev,
+		    scp_ipi_handler_t imgsys_scp_handler)
+{
+	int ret = 0;
+
+	ret = rproc_boot(imgsys_dev->rproc_handle);
+	if (ret) {
+		dev_err(imgsys_dev->dev,
+			"%s failed to rproc_boot\n", __func__);
+		return ret;
+	}
+
+	ret = scp_ipi_register(imgsys_dev->scp, SCP_IPI_IMGSYS_CMD,
+			       imgsys_scp_handler, imgsys_dev);
+	if (ret) {
+		dev_err(imgsys_dev->dev,
+			"%s failed to register IPI cmd\n", __func__);
+		return ret;
+	}
+
+	return ret;
+}
+
+void imgsys_scp_deinit(struct mtk_imgsys_dev *imgsys_dev)
+{
+	rproc_shutdown(imgsys_dev->rproc_handle);
+}
+
+int imgsys_scp_send(struct mtk_imgsys_dev *imgsys_dev,
+		    enum imgsys_ipi_id id, void *buf,
+		    unsigned int len, int req_fd,
+		    unsigned int wait)
+{
+	struct share_buf send_obj = { 0 };
+	int ret = 0;
+
+	dev_dbg(imgsys_dev->dev, "%s id:%d len %d\n",
+		__func__, id, len);
+
+	if (id < IPI_IMGSYS_INIT_ID || id >= IPI_MAX_ID ||
+	    len > sizeof(send_obj.share_data) || !buf) {
+		dev_info(imgsys_dev->dev,
+			 "%s failed to send scp message (len/sz(%d/%zu)\n",
+			 __func__, len, sizeof(send_obj.share_data));
+		return -EINVAL;
+	}
+
+	send_obj.len = len;
+	send_obj.id = id;
+	memcpy((void *)send_obj.share_data, buf, len);
+
+	send_obj.info.send.ipi = id;
+	send_obj.info.send.req = req_fd;
+	send_obj.info.send.ack = (wait ? 1 : 0);
+	send_obj.info.send.seq = 0;
+
+	ret = scp_ipi_send(imgsys_dev->scp, SCP_IPI_IMGSYS_CMD,
+			   (void *)&send_obj, sizeof(send_obj),
+			   wait ? msecs_to_jiffies(SCP_TIMEOUT_MS) : 0);
+	if (ret)
+		dev_err(imgsys_dev->dev,
+			"%s: send SCP(%d) failed %d\n", __func__, id, ret);
+
+	return 0;
+}
+
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-scp.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-scp.h
new file mode 100644
index 000000000000..2082c4bdf96f
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-scp.h
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef MTK_IMGSYS_SCP_H
+#define MTK_IMGSYS_SCP_H
+
+#include <linux/remoteproc/mtk_scp.h>
+#include "mtk-img-ipi.h"
+#include "mtk_imgsys-dev.h"
+
+/* the size of share buffer between the kernel and SCP */
+#define SCP_SHARE_BUF_SIZE      576
+
+/**
+ * struct object_info - Represents information associated with a object,
+ * particularly in the context of inter-processor communication and media
+ * processing.
+ *
+ * @ipi: Specifies the IPI (Inter-Processor Interrupt) ID, using 5 bits.
+ * @ack: Indicates whether an acknowledgment is required, using 1 bit.
+ * @req: Holds the media request ID, using 10 bits.
+ * @seq: A sequence number, using 16 bits, for tracking the order of
+ *       objects or messages.
+ * @cmd: Combined command representation.
+ */
+struct object_info {
+	union {
+		struct send {
+			u32 ipi: 5;  /* IPI ID */
+			u32 ack: 1;  /* Acknowledgment flag */
+			u32 req: 10; /* Media request ID */
+			u32 seq: 16; /* Sequence number */
+		} __packed send;
+		u32 cmd; /* Combined command representation */
+	};
+} __packed;
+
+/**
+ * struct share_buf - DTCM (Data Tightly-Coupled Memory) buffer shared with
+ *                    AP and hardware components of IMGSYS
+ *
+ * @id:               IPI (Inter-Processor Interrupt) ID
+ * @len:              Length of the shared buffer
+ * @share_data:       Data contained in the shared buffer
+ * @info:             Information associated with the object
+ *
+ * This structure represents a DTCM buffer that is shared between the AP and
+ * the hardware components of the MediaTek Image System (IMGSYS). It includes
+ * the IPI ID, the length of the shared buffer, the actual buffer data, and
+ * additional object information.
+ */
+struct share_buf {
+	u32 id;                            /* IPI (Inter-Processor Interrupt) ID */
+	u32 len;                           /* Length of the shared buffer */
+	u8 share_data[SCP_SHARE_BUF_SIZE]; /* Data contained in the shared buffer */
+	struct object_info info;           /* Information object */
+};
+
+/**
+ * enum img_mem_id - Enumeration of image memory IDs
+ *
+ * @WPE_MEM_C_ID: Warping Engine (WPE) module command queue (CQ) buffer
+ * @WPE_MEM_T_ID: WPE module tile driver (TDR) buffer
+ * @TRAW_MEM_C_ID: Tile-Raw (TRAW) module CQ buffer
+ * @TRAW_MEM_T_ID: TRAW module TDR buffer
+ * @DIP_MEM_C_ID: Digital Image Processing (DIP) module CQ buffer
+ * @DIP_MEM_T_ID: DIP module TDR buffer
+ * @PQDIP_MEM_C_ID: Picture Quality image processing (PQDIP) CQ buffer
+ * @PQDIP_MEM_T_ID: PQDIP TDR buffer
+ * @IMG_MEM_G_ID: GCE command buffer
+ * @IMG_MEM_ID_COUNT: Total number of memory IDs
+ *
+ * This enumeration defines the various memory IDs used in the MediaTek
+ * image system. Each memory ID corresponds to a specific buffer used
+ * by different modules within the image system.
+ */
+enum img_mem_id {
+	WPE_MEM_C_ID,       /* WPE module CQ buffer */
+	WPE_MEM_T_ID,       /* WPE module TDR buffer */
+	TRAW_MEM_C_ID,      /* TRAW module CQ buffer */
+	TRAW_MEM_T_ID,      /* TRAW module TDR buffer */
+	DIP_MEM_C_ID,       /* DIP module CQ buffer */
+	DIP_MEM_T_ID,       /* DIP module TDR buffer */
+	PQDIP_MEM_C_ID,     /* PQDIP CQ buffer */
+	PQDIP_MEM_T_ID,     /* PQDIP TDR buffer */
+	IMG_MEM_G_ID,       /* GCE command buffer */
+	IMG_MEM_ID_COUNT,   /* Total number of memory IDs */
+};
+
+/**
+ * enum imgsys_ipi_id - Enumeration of IPI (Inter-Processor Interrupt) IDs
+ * @IPI_IMGSYS_INIT_ID: ID for initializing the image system
+ * @IPI_IMGSYS_FRAME_ID: ID for processing a frame
+ * @IPI_IMGSYS_DEQUE_DONE_ID: ID for indicating frame dequeuing is done
+ * @IPI_IMGSYS_DEINIT_ID: ID for deinitializing the image system
+ * @IPI_MAX_ID: Maximum ID value, used for boundary checking
+ */
+enum imgsys_ipi_id {
+	IPI_IMGSYS_INIT_ID = 0,	/* ID for initializing the image system */
+	IPI_IMGSYS_FRAME_ID,	/* ID for processing a frame */
+	IPI_IMGSYS_DEQUE_DONE_ID,	/* ID for dequeuing frame is done */
+	IPI_IMGSYS_DEINIT_ID,	/* ID for deinitializing the image system */
+	IPI_MAX_ID,	/* Maximum ID value*/
+};
+
+/**
+ * imgsys_scp_alloc_reserve_mem - allocate reserved memory for use by the
+ * kernel and the SCP (System Control Processor)
+ *
+ * @imgsys_dev:	Pointer to the imgsys platform device structure
+ *
+ **/
+int imgsys_scp_alloc_reserve_mem(struct mtk_imgsys_dev *imgsys_dev);
+
+/**
+ * imgsys_scp_free_reserve_mem - free reserved memory for use by the kernel and
+ * SCP
+ *
+ * @imgsys_dev:	Pointer to the imgsys platform device structure
+ *
+ **/
+int imgsys_scp_free_reserve_mem(struct mtk_imgsys_dev *imgsys_dev);
+
+/**
+ * imgsys_scp_get_reserve_mem_info - get the information about reserved memory
+ *
+ * @info: A pointer to an already allocated structure of type img_init_info,
+ * where this function will populate the reserved memory details.
+ *
+ **/
+int imgsys_scp_get_reserve_mem_info(struct img_init_info *info);
+
+/**
+ * imgsys_scp_get_reserve_mem_virt - get the virtual address of reserved memory
+ * by a particular memory ID
+ *
+ * @id:	The identifier of the reserved memory block
+ *
+ **/
+void *imgsys_scp_get_reserve_mem_virt(enum img_mem_id id);
+
+/**
+ * imgsys_scp_get_reserve_mem_size - get the size of reserved memory by a
+ * particular memory ID
+ *
+ * @id:	The identifier of the reserved memory block
+ *
+ **/
+unsigned int imgsys_scp_get_reserve_mem_size(enum img_mem_id id);
+
+/**
+ * imgsys_scp_init - start the SCP
+ *
+ * @imgsys_dev:	Pointer to the imgsys platform device structure
+ * @imgsys_scp_handler: Handler for SCP IPI
+ **/
+int imgsys_scp_init(struct mtk_imgsys_dev *imgsys_dev,
+		    scp_ipi_handler_t imgsys_scp_handler);
+
+/**
+ * imgsys_scp_deinit - stop the SCP
+ *
+ * @imgsys_dev:	Pointer to the imgsys platform device structure
+ *
+ **/
+void imgsys_scp_deinit(struct mtk_imgsys_dev *imgsys_dev);
+
+/**
+ * imgsys_scp_send - send data from AP to SCP
+ *
+ * @imgsys_dev:	Pointer to the imgsys platform device structure
+ * @id:	IPI ID
+ * @buf:the data buffer
+ * @len: the data buffer length
+ * @req_fd: the file descriptor of media request
+ * @wait: wait until ipi done or not
+ *
+ * This function is thread-safe. When this function returns,
+ * SCP has received the data and starts the processing.
+ * When the processing completes, IPI handler registered
+ * by scp_ipi_register will be called in interrupt context.
+ *
+ **/
+int imgsys_scp_send(struct mtk_imgsys_dev *imgsys_dev,
+		    enum imgsys_ipi_id id,
+		    void *buf,
+		    unsigned int len,
+		    int req_fd,
+		    unsigned int wait);
+
+#endif /* MTK_IMGSYS_SCP_H */
+
-- 
2.45.2



From olivia.wen at mediatek.com  Sat May 24 04:49:56 2025
From: olivia.wen at mediatek.com (Olivia Wen)
Date: Sat, 24 May 2025 19:49:56 +0800
Subject: [PATCH v1 04/10] media: mediatek: isp: Add V4L2 flow support for ImgSys driver
In-Reply-To: <20250524115144.3832748-1-olivia.wen@mediatek.com>
References: <20250524115144.3832748-1-olivia.wen@mediatek.com>
Message-ID: <20250524115144.3832748-5-olivia.wen@mediatek.com>

The ImgSys driver is implemented as a series of patches, with this patch
focusing on the V4L2 flow. The MediaTek's Image System (ImgSys), also
known as ISP Pass2. ImgSys is a memory-to-memory hardware device
designed for advanced image processing tasks. It is composed of multiple
hardware components, including TRAW, DIP, PQDIP, ME, and WPE.

TRAW (Tile RAW):
- Provides multiple downscaled resizers to support multi-scale noise
  reduction.
- Supports RAW/RGB format conversion.

DIP (Digital Image Processing) and PQDIP (Picture Quality DIP):
- Supports such as temporal and spatial noise reduction (TNR/SNR),
  edge enhancement (EE), and sharpness (SHP).
- PQDIP also supports image scaling and rotation.

ME (Motion Estimation):
- Supports motion estimation between two consecutive frames.

WPE (Warping Engine):
- Handles image warping and de-warping processes.

The ImgSys driver, primarily utilized for Google Chromebook products,
uses Multi-Frame Combined Noise Reduction technology to enhance image
quality.

Below is a simplified architecture of the ImgSys driver:
User -> V4L2 Framework -> ImgSys Driver
     -> SCP (It packages the hardware settings into commands)
     -> ImgSys Driver
     -> CMDQ (The packaged commands are sent to the hardware via GCE)
     -> Hardware

Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
---
 drivers/media/platform/mediatek/Kconfig       |    1 +
 drivers/media/platform/mediatek/Makefile      |    1 +
 drivers/media/platform/mediatek/isp/Kconfig   |   23 +
 .../platform/mediatek/isp/isp_7x/Makefile     |    6 +
 .../mediatek/isp/isp_7x/imgsys/Makefile       |   11 +
 .../imgsys/modules/mtk_dip_v4l2_vnode.h       |  594 ++++++
 .../isp_7x/imgsys/modules/mtk_me_v4l2_vnode.h |  386 ++++
 .../imgsys/modules/mtk_pqdip_v4l2_vnode.h     |  149 ++
 .../imgsys/modules/mtk_traw_v4l2_vnode.h      |  371 ++++
 .../imgsys/modules/mtk_wpe_v4l2_vnode.h       |  317 ++++
 .../isp/isp_7x/imgsys/mtk_header_desc.h       |   28 +
 .../isp/isp_7x/imgsys/mtk_imgsys-dev.c        |  238 +++
 .../isp/isp_7x/imgsys/mtk_imgsys-dev.h        |  427 +++++
 .../isp/isp_7x/imgsys/mtk_imgsys-formats.c    |  139 ++
 .../isp/isp_7x/imgsys/mtk_imgsys-formats.h    |   72 +
 .../isp/isp_7x/imgsys/mtk_imgsys-module_ops.h |   27 +
 .../isp/isp_7x/imgsys/mtk_imgsys-of.c         |   39 +
 .../isp/isp_7x/imgsys/mtk_imgsys-of.h         |   55 +
 .../isp/isp_7x/imgsys/mtk_imgsys-sys.c        |   27 +
 .../isp/isp_7x/imgsys/mtk_imgsys-sys.h        |   50 +
 .../isp/isp_7x/imgsys/mtk_imgsys-v4l2.c       | 1684 +++++++++++++++++
 .../isp/isp_7x/imgsys/mtk_imgsys-vnode_id.h   |  100 +
 .../isp/isp_7x/imgsys/mtk_imgsys_v4l2_vnode.h |  135 ++
 23 files changed, 4880 insertions(+)
 create mode 100644 drivers/media/platform/mediatek/isp/Kconfig
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/Makefile
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_dip_v4l2_vnode.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_me_v4l2_vnode.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_pqdip_v4l2_vnode.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_traw_v4l2_vnode.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_wpe_v4l2_vnode.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_header_desc.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-formats.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-formats.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_ops.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-vnode_id.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys_v4l2_vnode.h

diff --git a/drivers/media/platform/mediatek/Kconfig b/drivers/media/platform/mediatek/Kconfig
index 84104e2cd024..4e0a5a43f35e 100644
--- a/drivers/media/platform/mediatek/Kconfig
+++ b/drivers/media/platform/mediatek/Kconfig
@@ -7,3 +7,4 @@ source "drivers/media/platform/mediatek/mdp/Kconfig"
 source "drivers/media/platform/mediatek/vcodec/Kconfig"
 source "drivers/media/platform/mediatek/vpu/Kconfig"
 source "drivers/media/platform/mediatek/mdp3/Kconfig"
+source "drivers/media/platform/mediatek/isp/Kconfig"
diff --git a/drivers/media/platform/mediatek/Makefile b/drivers/media/platform/mediatek/Makefile
index 38e6ba917fe5..611fa95416bc 100644
--- a/drivers/media/platform/mediatek/Makefile
+++ b/drivers/media/platform/mediatek/Makefile
@@ -4,3 +4,4 @@ obj-y += mdp/
 obj-y += vcodec/
 obj-y += vpu/
 obj-y += mdp3/
+obj-y += isp/isp_7x/
diff --git a/drivers/media/platform/mediatek/isp/Kconfig b/drivers/media/platform/mediatek/isp/Kconfig
new file mode 100644
index 000000000000..df92ac67574d
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/Kconfig
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config VIDEO_MTK_ISP_71_IMGSYS
+	tristate "MediaTek ISP71 image processing system function"
+	depends on MTK_CMDQ
+	depends on REMOTEPROC
+	depends on MTK_SCP
+	select VIDEO_V4L2_SUBDEV_API
+	select VIDEOBUF2_DMA_CONTIG
+	select VIDEOBUF2_CORE
+	select VIDEOBUF2_V4L2
+	select VIDEOBUF2_MEMOPS
+	select MEDIA_CONTROLLER
+
+	default n
+	help
+	    Support the basic Image processing system driver.
+
+	    IMGSYS driver provides image format conversion, resizing,
+	    and rotation function through the low power hardware.
+	    IMGSYS also supports multiple output feature. It can
+	    generate two or more output image with different effect
+	    based on a single input image at the same time.
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/Makefile b/drivers/media/platform/mediatek/isp/isp_7x/Makefile
new file mode 100644
index 000000000000..11d2aee9a3dc
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+
+subdir-ccflags-y += -Werror
+
+obj-$(CONFIG_VIDEO_MTK_ISP_71_IMGSYS) += imgsys/
+
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
new file mode 100644
index 000000000000..571d0ae000eb
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+
+mtk_imgsys_util-objs := \
+mtk_imgsys-of.o \
+mtk_imgsys-formats.o \
+mtk_imgsys-dev.o \
+mtk_imgsys-sys.o \
+mtk_imgsys-v4l2.o
+
+obj-$(CONFIG_VIDEO_MTK_ISP_71_IMGSYS) += mtk_imgsys_util.o
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_dip_v4l2_vnode.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_dip_v4l2_vnode.h
new file mode 100644
index 000000000000..1b5c8b738a54
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_dip_v4l2_vnode.h
@@ -0,0 +1,594 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_DIP_V4L2_VNODE_H_
+#define _MTK_DIP_V4L2_VNODE_H_
+
+#include "../mtk_imgsys-dev.h"
+#include "../mtk_imgsys-formats.h"
+#include "../mtk_imgsys-vnode_id.h"
+
+static const struct mtk_imgsys_dev_format dip_imgi_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_nv12,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_nv21,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 16,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p012p,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p010p,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_y8,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format dip_vipi_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_nv12,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_nv21,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 16,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p012p,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p010p,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format dip_rec_dsi_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_nv12,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_nv21,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p012p,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 16,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format dip_rec_dpi_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_nv12,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_nv21,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_y32,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 16,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format dip_meta_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_y32,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 16,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_y8,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format dip_tnrw_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 192,
+		.scan_align = 192,
+	},
+	{
+		.fmt = &mtk_imgsys_format_y8,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format dip_tnrci_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 144,
+		.scan_align = 108,
+	},
+	{
+		.fmt = &mtk_imgsys_format_y8,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format dip_tnrli_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_nv12,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_nv21,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format dip_img2o_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_nv12,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_nv21,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 16,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p010p,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_y8,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format dip_img3o_fmts[] = {
+	/* YUV422, 3 plane 8 bit */
+	/* YUV420, 2 plane 8 bit */
+	{
+		.fmt = &mtk_imgsys_format_nv12,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_nv21,
+		.align = 1,
+		.scan_align = 1,
+	},
+	/* Y8 bit */
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p012p,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p010p,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format dip_img4o_fmts[] = {
+	/* YUV420, 2 plane 8 bit */
+	{
+		.fmt = &mtk_imgsys_format_nv12,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_nv21,
+		.align = 1,
+		.scan_align = 1,
+	},
+	/* Y8 bit */
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 16,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p012p,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p010p,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct v4l2_frmsizeenum dip_in_frmsizeenum = {
+	.type = V4L2_FRMSIZE_TYPE_CONTINUOUS,
+	.stepwise.max_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+	.stepwise.min_width = MTK_IMGSYS_CAPTURE_MIN_WIDTH,
+	.stepwise.max_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+	.stepwise.min_height = MTK_IMGSYS_CAPTURE_MIN_HEIGHT,
+	.stepwise.step_height = 1,
+	.stepwise.step_width = 1,
+};
+
+static const struct v4l2_frmsizeenum dip_out_frmsizeenum = {
+	.type = V4L2_FRMSIZE_TYPE_CONTINUOUS,
+	.stepwise.max_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+	.stepwise.min_width = MTK_IMGSYS_OUTPUT_MIN_WIDTH,
+	.stepwise.max_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+	.stepwise.min_height = MTK_IMGSYS_OUTPUT_MIN_HEIGHT,
+	.stepwise.step_height = 1,
+	.stepwise.step_width = 1,
+};
+
+static const struct mtk_imgsys_video_device_desc dip_setting[] = {
+	/* Input Video Node */
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_IMGI_OUT,
+		.name = "Imgi Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_imgi_fmts,
+		.num_fmts = ARRAY_SIZE(dip_imgi_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &dip_in_frmsizeenum,
+		.description = "Main image source",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_VIPI_OUT,
+		.name = "Vipi Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_vipi_fmts,
+		.num_fmts = ARRAY_SIZE(dip_vipi_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_in_frmsizeenum,
+		.description = "Vipi image source",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_REC_DSI_OUT,
+		.name = "Rec_Dsi Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_rec_dsi_fmts,
+		.num_fmts = ARRAY_SIZE(dip_rec_dsi_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_in_frmsizeenum,
+		.description = "Down Source Image",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_REC_DPI_OUT,
+		.name = "Rec_Dpi Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_rec_dpi_fmts,
+		.num_fmts = ARRAY_SIZE(dip_rec_dpi_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_in_frmsizeenum,
+		.description = "Down Processed Image",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_CNR_BLURMAPI_OUT,
+		.name = "Bokeh Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_meta_fmts,
+		.num_fmts = ARRAY_SIZE(dip_meta_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_in_frmsizeenum,
+		.description = "Bokehi data",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_LFEI_OUT,
+		.name = "Dmgi_FM Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_meta_fmts,
+		.num_fmts = ARRAY_SIZE(dip_meta_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_in_frmsizeenum,
+		.description = "Dmgi_FM data",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_RFEI_OUT,
+		.name = "Depi_FM Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_meta_fmts,
+		.num_fmts = ARRAY_SIZE(dip_meta_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_in_frmsizeenum,
+		.description = "Depi_FM data",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TNRSI_OUT,
+		.name = "Tnrsi Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_meta_fmts,
+		.num_fmts = ARRAY_SIZE(dip_meta_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_in_frmsizeenum,
+		.description = "Statistics input",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TNRWI_OUT,
+		.name = "Tnrwi Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_tnrw_fmts,
+		.num_fmts = ARRAY_SIZE(dip_tnrw_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_in_frmsizeenum,
+		.description = "Weighting input",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TNRMI_OUT,
+		.name = "Tnrmi Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_meta_fmts,
+		.num_fmts = ARRAY_SIZE(dip_meta_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_in_frmsizeenum,
+		.description = "Motion Map input",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TNRCI_OUT,
+		.name = "Tnrci Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_tnrci_fmts,
+		.num_fmts = ARRAY_SIZE(dip_tnrci_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_in_frmsizeenum,
+		.description = "Confidence Map input",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TNRLI_OUT,
+		.name = "Tnrli Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_tnrli_fmts,
+		.num_fmts = ARRAY_SIZE(dip_tnrli_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_in_frmsizeenum,
+		.description = "Low Frequency Diff input",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TNRVBI_OUT,
+		.name = "Tnrvbi Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_meta_fmts,
+		.num_fmts = ARRAY_SIZE(dip_meta_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_in_frmsizeenum,
+		.description = "Valid Bit Map input",
+	},
+	/* Output Video Node */
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_IMG2O_CAPTURE,
+		.name = "Img2o Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_img2o_fmts,
+		.num_fmts = ARRAY_SIZE(dip_img2o_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_out_frmsizeenum,
+		.description = "Resized output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_IMG3O_CAPTURE,
+		.name = "Img3o Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_img3o_fmts,
+		.num_fmts = ARRAY_SIZE(dip_img3o_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_out_frmsizeenum,
+		.description = "Dip output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_IMG4O_CAPTURE,
+		.name = "Img4o Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_img4o_fmts,
+		.num_fmts = ARRAY_SIZE(dip_img4o_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_out_frmsizeenum,
+		.description = "Nr3d output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_FMO_CAPTURE,
+		.name = "FM Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_meta_fmts,
+		.num_fmts = ARRAY_SIZE(dip_meta_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_out_frmsizeenum,
+		.description = "FM output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TNRSO_CAPTURE,
+		.name = "Tnrso Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_meta_fmts,
+		.num_fmts = ARRAY_SIZE(dip_meta_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_out_frmsizeenum,
+		.description = "statistics output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TNRWO_CAPTURE,
+		.name = "Tnrwo Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_tnrw_fmts,
+		.num_fmts = ARRAY_SIZE(dip_tnrw_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_out_frmsizeenum,
+		.description = "Weighting output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TNRMO_CAPTURE,
+		.name = "Tnrmo Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = dip_meta_fmts,
+		.num_fmts = ARRAY_SIZE(dip_meta_fmts),
+		.default_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &dip_out_frmsizeenum,
+		.description = "Motion Map output",
+	},
+};
+
+#endif // _MTK_IMGSYS_V4L2_VNODE_H_
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_me_v4l2_vnode.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_me_v4l2_vnode.h
new file mode 100644
index 000000000000..d33f8847731f
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_me_v4l2_vnode.h
@@ -0,0 +1,386 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_ME_V4L2_VNODE_H_
+#define _MTK_ME_V4L2_VNODE_H_
+
+#include "../mtk_imgsys-dev.h"
+#include "../mtk_imgsys-formats.h"
+#include "../mtk_imgsys-vnode_id.h"
+
+static const struct mtk_imgsys_dev_format me_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_y32,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_y16,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_y8,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 16,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format mewmap_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_warp2p,
+		.align = 8,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format melmi_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_y16,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format mel1i_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_aply8,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct v4l2_frmsizeenum in_frmsizeenum = {
+	.type = V4L2_FRMSIZE_TYPE_CONTINUOUS,
+	.stepwise.max_width = MTK_IMGSYS_CAPTURE_MAX_WIDTH,
+	.stepwise.min_width = MTK_IMGSYS_CAPTURE_MIN_WIDTH,
+	.stepwise.max_height = MTK_IMGSYS_CAPTURE_MAX_HEIGHT,
+	.stepwise.min_height = MTK_IMGSYS_CAPTURE_MIN_HEIGHT,
+	.stepwise.step_height = 1,
+	.stepwise.step_width = 1,
+};
+
+static const struct v4l2_frmsizeenum out_frmsizeenum = {
+	.type = V4L2_FRMSIZE_TYPE_CONTINUOUS,
+	.stepwise.max_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+	.stepwise.min_width = MTK_IMGSYS_OUTPUT_MIN_WIDTH,
+	.stepwise.max_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+	.stepwise.min_height = MTK_IMGSYS_OUTPUT_MIN_HEIGHT,
+	.stepwise.step_height = 1,
+	.stepwise.step_width = 1,
+};
+
+static const struct mtk_imgsys_video_device_desc me_setting[] = {
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEL0IMG0_OUT,
+		.name = "L0I0I Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &in_frmsizeenum,
+		.description = "ME Input",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEL0IMG1_OUT,
+		.name = "L0I1I Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &in_frmsizeenum,
+		.description = "ME Input",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEL1IMG0_OUT,
+		.name = "L1I0I Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = mel1i_fmts,
+		.num_fmts = ARRAY_SIZE(mel1i_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &in_frmsizeenum,
+		.description = "ME L1 Input ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEL1IMG1_OUT,
+		.name = "L1I1I Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = mel1i_fmts,
+		.num_fmts = ARRAY_SIZE(mel1i_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &in_frmsizeenum,
+		.description = "ME L1 Input ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEIMGSTATS_OUT,
+		.name = "STATI Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &in_frmsizeenum,
+		.description = "ME IMGSTATS Input ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEL0RMV_OUT,
+		.name = "L0RMVI Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &in_frmsizeenum,
+		.description = "ME L0RMV Input ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEL1RMV_OUT,
+		.name = "L1RMVI Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &in_frmsizeenum,
+		.description = "ME L1RMV Input ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEL0FMB_OUT,
+		.name = "L0FMBI Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &in_frmsizeenum,
+		.description = "ME L0FMB Input ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEL1FMB_OUT,
+		.name = "L1FMBI Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &in_frmsizeenum,
+		.description = "ME L1FMB Input ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEMIL_OUT,
+		.name = "MEMILI Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &in_frmsizeenum,
+		.description = "ME MIL Input ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEMMGMIL_CAPTURE,
+		.name = "MILO Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &out_frmsizeenum,
+		.description = "ME MMGMIL Output ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEL0WMV_CAPTURE,
+		.name = "L0WMVO Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &out_frmsizeenum,
+		.description = "ME L0WMV Output ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEL1WMV_CAPTURE,
+		.name = "L1WMVO Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &out_frmsizeenum,
+		.description = "ME L1WMV Output ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MECONF_CAPTURE,
+		.name = "CONFO Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &out_frmsizeenum,
+		.description = "ME CONF Output ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEWMAP_CAPTURE,
+		.name = "WMAPO Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = mewmap_fmts,
+		.num_fmts = ARRAY_SIZE(mewmap_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &out_frmsizeenum,
+		.description = "ME WMAP Output ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEFMV_CAPTURE,
+		.name = "FMVO Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &out_frmsizeenum,
+		.description = "ME OTHERS Output ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEFST_CAPTURE,
+		.name = "FSTO Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &out_frmsizeenum,
+		.description = "ME FST Output ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MELMI_CAPTURE,
+		.name = "LMIO Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = melmi_fmts,
+		.num_fmts = ARRAY_SIZE(melmi_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &out_frmsizeenum,
+		.description = "ME LMI Output ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEL0WFMB_CAPTURE,
+		.name = "L0FMBO Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &out_frmsizeenum,
+		.description = "ME L0FMB Output ",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_MEL1WFMB_CAPTURE,
+		.name = "L1FMBO Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = me_fmts,
+		.num_fmts = ARRAY_SIZE(me_fmts),
+		.default_width = MTK_IMGSYS_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_IMGSYS_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &out_frmsizeenum,
+		.description = "ME L1FMB Output ",
+	},
+};
+
+#endif /* _MTK_ME_V4L2_VNODE_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_pqdip_v4l2_vnode.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_pqdip_v4l2_vnode.h
new file mode 100644
index 000000000000..23c8db3b30f3
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_pqdip_v4l2_vnode.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ *
+ * Author: Daniel Huang <daniel.huang at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_PQDIP_V4L2_VNODE_H_
+#define _MTK_PQDIP_V4L2_VNODE_H_
+
+#include "../mtk_imgsys-dev.h"
+#include "../mtk_imgsys-formats.h"
+#include "../mtk_imgsys-vnode_id.h"
+
+#define MTK_PQDIP_OUTPUT_MIN_WIDTH		2U
+#define MTK_PQDIP_OUTPUT_MIN_HEIGHT		2U
+#define MTK_PQDIP_OUTPUT_MAX_WIDTH		5376U
+#define MTK_PQDIP_OUTPUT_MAX_HEIGHT		4032U
+#define MTK_PQDIP_CAPTURE_MIN_WIDTH		2U
+#define MTK_PQDIP_CAPTURE_MIN_HEIGHT		2U
+#define MTK_PQDIP_CAPTURE_MAX_WIDTH		5376U
+#define MTK_PQDIP_CAPTURE_MAX_HEIGHT		4032U
+
+static const struct mtk_imgsys_dev_format pqdip_pimgi_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_nv12,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format pqdip_wroto_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_nv12,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format pqdip_tccso_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 16,
+		.scan_align = 1,
+	},
+};
+
+static const struct v4l2_frmsizeenum pqdip_in_frmsizeenum = {
+	.type = V4L2_FRMSIZE_TYPE_CONTINUOUS,
+	.stepwise.max_width = MTK_PQDIP_CAPTURE_MAX_WIDTH,
+	.stepwise.min_width = MTK_PQDIP_CAPTURE_MIN_WIDTH,
+	.stepwise.max_height = MTK_PQDIP_CAPTURE_MAX_HEIGHT,
+	.stepwise.min_height = MTK_PQDIP_CAPTURE_MIN_HEIGHT,
+	.stepwise.step_height = 1,
+	.stepwise.step_width = 1,
+};
+
+static const struct v4l2_frmsizeenum pqdip_out_frmsizeenum = {
+	.type = V4L2_FRMSIZE_TYPE_CONTINUOUS,
+	.stepwise.max_width = MTK_PQDIP_OUTPUT_MAX_WIDTH,
+	.stepwise.min_width = MTK_PQDIP_OUTPUT_MIN_WIDTH,
+	.stepwise.max_height = MTK_PQDIP_OUTPUT_MAX_HEIGHT,
+	.stepwise.min_height = MTK_PQDIP_OUTPUT_MIN_HEIGHT,
+	.stepwise.step_height = 1,
+	.stepwise.step_width = 1,
+};
+
+static const struct mtk_imgsys_video_device_desc pqdip_setting[] = {
+	/* Input Video Node */
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_PIMGI_OUT,
+		.name = "PIMGI Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = pqdip_pimgi_fmts,
+		.num_fmts = ARRAY_SIZE(pqdip_pimgi_fmts),
+		.default_width = MTK_PQDIP_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_PQDIP_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &pqdip_in_frmsizeenum,
+		.description = "Imgi image source",
+	},
+	/* Output Video Node */
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_WROT_A_CAPTURE,
+		.name = "WROTO A Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = pqdip_wroto_fmts,
+		.num_fmts = ARRAY_SIZE(pqdip_wroto_fmts),
+		.default_width = MTK_PQDIP_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_PQDIP_CAPTURE_MAX_WIDTH,
+		.frmsizeenum = &pqdip_out_frmsizeenum,
+		.description = "Output quality enhanced image",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_WROT_B_CAPTURE,
+		.name = "WROTO B Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = pqdip_wroto_fmts,
+		.num_fmts = ARRAY_SIZE(pqdip_wroto_fmts),
+		.default_width = MTK_PQDIP_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_PQDIP_CAPTURE_MAX_WIDTH,
+		.frmsizeenum = &pqdip_out_frmsizeenum,
+		.description = "Output quality enhanced image",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TCCSO_A_CAPTURE,
+		.name = "TCCSO A Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = pqdip_tccso_fmts,
+		.num_fmts = ARRAY_SIZE(pqdip_tccso_fmts),
+		.default_width = MTK_PQDIP_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_PQDIP_CAPTURE_MAX_WIDTH,
+		.frmsizeenum = &pqdip_out_frmsizeenum,
+		.description = "Output tone curve statistics",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TCCSO_B_CAPTURE,
+		.name = "TCCSO B Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = pqdip_tccso_fmts,
+		.num_fmts = ARRAY_SIZE(pqdip_tccso_fmts),
+		.default_width = MTK_PQDIP_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_PQDIP_CAPTURE_MAX_WIDTH,
+		.frmsizeenum = &pqdip_out_frmsizeenum,
+		.description = "Output tone curve statistics",
+	},
+};
+
+#endif /* _MTK_PQDIP_V4L2_VNODE_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_traw_v4l2_vnode.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_traw_v4l2_vnode.h
new file mode 100644
index 000000000000..ec03f7a59be8
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_traw_v4l2_vnode.h
@@ -0,0 +1,371 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ *
+ * Author: Shih-Fang chuang <shih-fang.chuang at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_TRAW_V4L2_VNODE_H_
+#define _MTK_TRAW_V4L2_VNODE_H_
+
+#include "../mtk_imgsys-dev.h"
+#include "../mtk_imgsys-formats.h"
+#include "../mtk_imgsys-vnode_id.h"
+
+#define MTK_TRAW_OUTPUT_MIN_WIDTH		2U
+#define MTK_TRAW_OUTPUT_MIN_HEIGHT		2U
+#define MTK_TRAW_OUTPUT_MAX_WIDTH		5376U
+#define MTK_TRAW_OUTPUT_MAX_HEIGHT		4032U
+#define MTK_TRAW_CAPTURE_MIN_WIDTH		2U
+#define MTK_TRAW_CAPTURE_MIN_HEIGHT		2U
+#define MTK_TRAW_CAPTURE_MAX_WIDTH		5376U
+#define MTK_TRAW_CAPTURE_MAX_HEIGHT		4032U
+
+static const struct mtk_imgsys_dev_format traw_imgi_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_nv12,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_sgbrg10,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 16,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p012p,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p010p,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_warp2p,
+		.align = 8,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_y8,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_srggb10,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_sgrbg10,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format traw_metai_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_metai,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format traw_stato_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_stt,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format traw_yuvo_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_nv12,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p012p,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p010p,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_warp2p,
+		.align = 8,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_y8,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_aply8,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format traw_pdc_fmts[] = {
+	/* Y8 bit */
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 16,
+		.scan_align = 1,
+	},
+};
+
+static const struct v4l2_frmsizeenum traw_in_frmsizeenum = {
+	.type = V4L2_FRMSIZE_TYPE_CONTINUOUS,
+	.stepwise.max_width = MTK_TRAW_CAPTURE_MAX_WIDTH,
+	.stepwise.min_width = MTK_TRAW_CAPTURE_MIN_WIDTH,
+	.stepwise.max_height = MTK_TRAW_CAPTURE_MAX_HEIGHT,
+	.stepwise.min_height = MTK_TRAW_CAPTURE_MIN_HEIGHT,
+	.stepwise.step_height = 1,
+	.stepwise.step_width = 1,
+};
+
+static const struct v4l2_frmsizeenum traw_out_frmsizeenum = {
+	.type = V4L2_FRMSIZE_TYPE_CONTINUOUS,
+	.stepwise.max_width = MTK_TRAW_OUTPUT_MAX_WIDTH,
+	.stepwise.min_width = MTK_TRAW_OUTPUT_MIN_WIDTH,
+	.stepwise.max_height = MTK_TRAW_OUTPUT_MAX_HEIGHT,
+	.stepwise.min_height = MTK_TRAW_OUTPUT_MIN_HEIGHT,
+	.stepwise.step_height = 1,
+	.stepwise.step_width = 1,
+};
+
+static const struct mtk_imgsys_video_device_desc traw_setting[] = {
+	/* Input Video Node */
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TIMGI_OUT,
+		.name = "TIMGI Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = traw_imgi_fmts,
+		.num_fmts = ARRAY_SIZE(traw_imgi_fmts),
+		.default_width = MTK_TRAW_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_TRAW_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &traw_in_frmsizeenum,
+		.description = "Imgi image source",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_METAI_OUT,
+		.name = "METAI Input",
+		.cap = V4L2_CAP_META_OUTPUT | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_META_OUTPUT,
+		.smem_alloc = 1,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = traw_metai_fmts,
+		.num_fmts = ARRAY_SIZE(traw_metai_fmts),
+		.default_width = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_TRAW_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &traw_in_frmsizeenum,
+		.description = "METAI image source",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_PDC_OUT,
+		.name = "PDC Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = traw_pdc_fmts,
+		.num_fmts = ARRAY_SIZE(traw_pdc_fmts),
+		.default_width = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_TRAW_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &traw_in_frmsizeenum,
+		.description = "PDC image source",
+	},
+	/* Output Video Node */
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TYUVO_CAPTURE,
+		.name = "TYUVO Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = traw_yuvo_fmts,
+		.num_fmts = ARRAY_SIZE(traw_yuvo_fmts),
+		.default_width = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.frmsizeenum = &traw_out_frmsizeenum,
+		.description = "YUVO output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TYUV2O_CAPTURE,
+		.name = "TYUV2O Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = traw_yuvo_fmts,
+		.num_fmts = ARRAY_SIZE(traw_yuvo_fmts),
+		.default_width = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.frmsizeenum = &traw_out_frmsizeenum,
+		.description = "YUV2O output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TYUV3O_CAPTURE,
+		.name = "TYUV3O Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = traw_yuvo_fmts,
+		.num_fmts = ARRAY_SIZE(traw_yuvo_fmts),
+		.default_width = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.frmsizeenum = &traw_out_frmsizeenum,
+		.description = "YUV3O output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TYUV4O_CAPTURE,
+		.name = "TYUV4O Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = traw_yuvo_fmts,
+		.num_fmts = ARRAY_SIZE(traw_yuvo_fmts),
+		.default_width = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.frmsizeenum = &traw_out_frmsizeenum,
+		.description = "YUV4O output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TYUV5O_CAPTURE,
+		.name = "TYUV5O Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = traw_yuvo_fmts,
+		.num_fmts = ARRAY_SIZE(traw_yuvo_fmts),
+		.default_width = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.frmsizeenum = &traw_out_frmsizeenum,
+		.description = "YUV5O output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_FEO_CAPTURE,
+		.name = "FEO Output",
+		.cap = V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_META_CAPTURE,
+		.smem_alloc = 1,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = traw_metai_fmts,
+		.num_fmts = ARRAY_SIZE(traw_metai_fmts),
+		.default_width = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.frmsizeenum = &traw_out_frmsizeenum,
+		.description = "FEO output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TIMGO_CAPTURE,
+		.name = "TIMGO Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = traw_imgi_fmts,
+		.num_fmts = ARRAY_SIZE(traw_imgi_fmts),
+		.default_width = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.frmsizeenum = &traw_out_frmsizeenum,
+		.description = "TIMGO output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_IMGSTATO_CAPTURE,
+		.name = "IMGSTATO Output",
+		.cap = V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_META_CAPTURE,
+		.smem_alloc = 1,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = traw_stato_fmts,
+		.num_fmts = ARRAY_SIZE(traw_stato_fmts),
+		.default_width = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.frmsizeenum = &traw_out_frmsizeenum,
+		.description = "IMGSTATO output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_XTMEO_CAPTURE,
+		.name = "XTMEO Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = traw_pdc_fmts,
+		.num_fmts = ARRAY_SIZE(traw_pdc_fmts),
+		.default_width = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.frmsizeenum = &traw_out_frmsizeenum,
+		.description = "XTMEO output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_XTFDO_CAPTURE,
+		.name = "XTFDO Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = traw_yuvo_fmts,
+		.num_fmts = ARRAY_SIZE(traw_yuvo_fmts),
+		.default_width = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.frmsizeenum = &traw_out_frmsizeenum,
+		.description = "XTFDO output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_XTADLDBGO_CAPTURE,
+		.name = "XTDBGO Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = traw_imgi_fmts,
+		.num_fmts = ARRAY_SIZE(traw_imgi_fmts),
+		.default_width = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_TRAW_CAPTURE_MAX_WIDTH,
+		.frmsizeenum = &traw_out_frmsizeenum,
+		.description = "XTDBGO output",
+	},
+};
+
+#endif /* _MTK_TRAW_V4L2_VNODE_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_wpe_v4l2_vnode.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_wpe_v4l2_vnode.h
new file mode 100644
index 000000000000..3e378d54b900
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_wpe_v4l2_vnode.h
@@ -0,0 +1,317 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ *
+ * Author: Floria Huang <floria.huang at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_WPE_V4L2_VNODE_H_
+#define _MTK_WPE_V4L2_VNODE_H_
+
+#include "../mtk_imgsys-dev.h"
+#include "../mtk_imgsys-formats.h"
+#include "../mtk_imgsys-vnode_id.h"
+
+#define MTK_WPE_OUTPUT_MIN_WIDTH	2U
+#define MTK_WPE_OUTPUT_MIN_HEIGHT	2U
+#define MTK_WPE_OUTPUT_MAX_WIDTH	18472U
+#define MTK_WPE_OUTPUT_MAX_HEIGHT	13856U
+
+#define MTK_WPE_MAP_OUTPUT_MIN_WIDTH	2U
+#define MTK_WPE_MAP_OUTPUT_MIN_HEIGHT	2U
+#define MTK_WPE_MAP_OUTPUT_MAX_WIDTH	640U
+#define MTK_WPE_MAP_OUTPUT_MAX_HEIGHT	480U
+
+#define MTK_WPE_PSP_OUTPUT_WIDTH	8U
+#define MTK_WPE_PSP_OUTPUT_HEIGHT	33U
+
+#define MTK_WPE_CAPTURE_MIN_WIDTH	2U
+#define MTK_WPE_CAPTURE_MIN_HEIGHT	2U
+#define MTK_WPE_CAPTURE_MAX_WIDTH	18472U
+#define MTK_WPE_CAPTURE_MAX_HEIGHT	13856U
+
+static const struct mtk_imgsys_dev_format wpe_wpei_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_nv12,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_nv21,
+		.align = 1,
+		.scan_align = 1,
+	},
+	/* Y8 bit */
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 192,
+		.scan_align = 192,
+	},
+	/* Bayer 10 bit */
+	{
+		.fmt = &mtk_imgsys_format_sgbrg10,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p010p,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p012p,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format wpe_veci_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_warp2p,
+		.align = 8,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format wpe_pspi_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 16,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_y32,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format wpe_wpeo_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_nv12,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_nv21,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 192,
+		.scan_align = 192,
+	},
+	{
+		.fmt = &mtk_imgsys_format_sgbrg10,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p010p,
+		.align = 1,
+		.scan_align = 1,
+	},
+	{
+		.fmt = &mtk_imgsys_format_2p012p,
+		.align = 1,
+		.scan_align = 1,
+	},
+};
+
+static const struct mtk_imgsys_dev_format wpe_msko_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_grey,
+		.align = 16,
+		.scan_align = 1,
+	},
+};
+
+static const struct v4l2_frmsizeenum wpe_in_frmsizeenum = {
+	.type = V4L2_FRMSIZE_TYPE_CONTINUOUS,
+	.stepwise.max_width = MTK_WPE_CAPTURE_MAX_WIDTH,
+	.stepwise.min_width = MTK_WPE_CAPTURE_MIN_WIDTH,
+	.stepwise.max_height = MTK_WPE_CAPTURE_MAX_HEIGHT,
+	.stepwise.min_height = MTK_WPE_CAPTURE_MIN_HEIGHT,
+	.stepwise.step_height = 1,
+	.stepwise.step_width = 1,
+};
+
+static const struct v4l2_frmsizeenum wpe_in_map_frmsizeenum = {
+	.type = V4L2_FRMSIZE_TYPE_CONTINUOUS,
+	.stepwise.max_width = MTK_WPE_MAP_OUTPUT_MAX_WIDTH,
+	.stepwise.min_width = MTK_WPE_MAP_OUTPUT_MIN_WIDTH,
+	.stepwise.max_height = MTK_WPE_MAP_OUTPUT_MAX_HEIGHT,
+	.stepwise.min_height = MTK_WPE_MAP_OUTPUT_MIN_HEIGHT,
+	.stepwise.step_height = 1,
+	.stepwise.step_width = 1,
+};
+
+static const struct v4l2_frmsizeenum wpe_out_frmsizeenum = {
+	.type = V4L2_FRMSIZE_TYPE_CONTINUOUS,
+	.stepwise.max_width = MTK_WPE_OUTPUT_MAX_WIDTH,
+	.stepwise.min_width = MTK_WPE_OUTPUT_MIN_WIDTH,
+	.stepwise.max_height = MTK_WPE_OUTPUT_MAX_HEIGHT,
+	.stepwise.min_height = MTK_WPE_OUTPUT_MIN_HEIGHT,
+	.stepwise.step_height = 1,
+	.stepwise.step_width = 1,
+};
+
+static const struct mtk_imgsys_video_device_desc wpe_setting[] = {
+	/* Input Video Node */
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_WWPEI_OUT,
+		.name = "WPEI_E Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = wpe_wpei_fmts,
+		.num_fmts = ARRAY_SIZE(wpe_wpei_fmts),
+		.default_width = MTK_WPE_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_WPE_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &wpe_in_frmsizeenum,
+		.description = "WPE main image input",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_WVECI_OUT,
+		.name = "VECI_E Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = wpe_veci_fmts,
+		.num_fmts = ARRAY_SIZE(wpe_veci_fmts),
+		.default_width = MTK_WPE_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_WPE_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &wpe_in_map_frmsizeenum,
+		.description = "WarpMap input",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_WPSP_COEFI_OUT,
+		.name = "PSPI_E Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = wpe_pspi_fmts,
+		.num_fmts = ARRAY_SIZE(wpe_pspi_fmts),
+		.default_width = MTK_WPE_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_WPE_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &wpe_in_frmsizeenum,
+		.description = "PSP coef. table input",
+	},
+	/* WPE_EIS Output Video Node */
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_WWPEO_CAPTURE,
+		.name = "WPEO_E Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = wpe_wpeo_fmts,
+		.num_fmts = ARRAY_SIZE(wpe_wpeo_fmts),
+		.default_width = MTK_WPE_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_WPE_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &wpe_out_frmsizeenum,
+		.description = "WPE image output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_WMSKO_CAPTURE,
+		.name = "MSKO_E Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = wpe_msko_fmts,
+		.num_fmts = ARRAY_SIZE(wpe_msko_fmts),
+		.default_width = MTK_WPE_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_WPE_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &wpe_out_frmsizeenum,
+		.description = "WPE valid map output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_WTWPEI_OUT,
+		.name = "WPEI_T Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = wpe_wpei_fmts,
+		.num_fmts = ARRAY_SIZE(wpe_wpei_fmts),
+		.default_width = MTK_WPE_OUTPUT_MAX_WIDTH,
+		.default_height = MTK_WPE_OUTPUT_MAX_HEIGHT,
+		.frmsizeenum = &wpe_in_frmsizeenum,
+		.description = "WPE main image input",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_WTVECI_OUT,
+		.name = "VECI_T Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = wpe_veci_fmts,
+		.num_fmts = ARRAY_SIZE(wpe_veci_fmts),
+		.default_width = MTK_WPE_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_WPE_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &wpe_in_map_frmsizeenum,
+		.description = "WarpMap input",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_WTPSP_COEFI_OUT,
+		.name = "PSPI_T Input",
+		.cap = V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = wpe_pspi_fmts,
+		.num_fmts = ARRAY_SIZE(wpe_pspi_fmts),
+		.default_width = MTK_WPE_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_WPE_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &wpe_in_frmsizeenum,
+		.description = "PSP coef. table input",
+	},
+	/* WPE_TNR Output Video Node */
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_WTWPEO_CAPTURE,
+		.name = "WPEO_T Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = wpe_wpeo_fmts,
+		.num_fmts = ARRAY_SIZE(wpe_wpeo_fmts),
+		.default_width = MTK_WPE_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_WPE_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &wpe_out_frmsizeenum,
+		.description = "WPE image output",
+	},
+	{
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_WTMSKO_CAPTURE,
+		.name = "MSKO_T Output",
+		.cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+		.smem_alloc = 0,
+		.supports_ctrls = true,
+		.flags = MEDIA_LNK_FL_DYNAMIC,
+		.fmts = wpe_msko_fmts,
+		.num_fmts = ARRAY_SIZE(wpe_msko_fmts),
+		.default_width = MTK_WPE_CAPTURE_MAX_WIDTH,
+		.default_height = MTK_WPE_CAPTURE_MAX_HEIGHT,
+		.frmsizeenum = &wpe_out_frmsizeenum,
+		.description = "WPE valid map output",
+	},
+};
+
+#endif /* _MTK_WPE_V4L2_VNODE_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_header_desc.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_header_desc.h
new file mode 100644
index 000000000000..50c2e3c3395b
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_header_desc.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ *
+ */
+
+#ifndef _HEADER_DESC_
+#define _HEADER_DESC_
+
+#include <linux/videodev2.h>
+
+/**
+ * struct mtk_imgsys_crop - Crop parameters for MediaTek Image System
+ * @c: Rectangle defining the crop area
+ * @left_subpix: Sub-pixel adjustment for the left edge
+ * @top_subpix: Sub-pixel adjustment for the top edge
+ * @width_subpix: Sub-pixel adjustment for the width
+ * @height_subpix: Sub-pixel adjustment for the height
+ */
+struct mtk_imgsys_crop {
+	struct v4l2_rect    c;             /* Rectangle defining the crop area */
+	struct v4l2_fract   left_subpix;   /* Sub-pixel adjustment for the left edge */
+	struct v4l2_fract   top_subpix;    /* Sub-pixel adjustment for the top edge */
+	struct v4l2_fract   width_subpix;  /* Sub-pixel adjustment for the width */
+	struct v4l2_fract   height_subpix; /* Sub-pixel adjustment for the height */
+};
+
+#endif
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.c
new file mode 100644
index 000000000000..28a35a3226a2
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.c
@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *
+ */
+
+#include "linux/list.h"
+#include <linux/dma-buf.h>
+#include <linux/dma-direction.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/hashtable.h>
+#include <media/videobuf2-dma-contig.h>
+#include <media/v4l2-event.h>
+#include "mtk_imgsys-formats.h"
+#include "mtk_imgsys-vnode_id.h"
+#include "mtk_imgsys-dev.h"
+#include "mtk_imgsys-sys.h"
+
+int mtk_imgsys_pipe_init(struct mtk_imgsys_dev *imgsys_dev,
+			 struct mtk_imgsys_pipe *pipe,
+			 const struct mtk_imgsys_pipe_desc *setting)
+{
+	u32 i, nodes_num;
+	size_t nodes_size;
+
+	pipe->imgsys_dev = imgsys_dev;
+	pipe->desc = setting;
+	pipe->nodes_enabled = 0ULL;
+	pipe->nodes_streaming = 0ULL;
+
+	atomic_set(&pipe->pipe_job_sequence, 0);
+	INIT_LIST_HEAD(&pipe->pipe_job_running_list);
+	INIT_LIST_HEAD(&pipe->pipe_job_pending_list);
+
+	spin_lock_init(&pipe->pending_job_lock);
+	spin_lock_init(&pipe->running_job_lock);
+	mutex_init(&pipe->lock);
+
+	nodes_num = pipe->desc->total_queues;
+	nodes_size = sizeof(*pipe->nodes) * nodes_num;
+	pipe->nodes = devm_kzalloc(imgsys_dev->dev, nodes_size, GFP_KERNEL);
+	if (!pipe->nodes)
+		return -ENOMEM;
+
+	for (i = 0; i < nodes_num; i++) {
+		pipe->nodes[i].desc = &pipe->desc->queue_descs[i];
+		pipe->nodes[i].flags = pipe->nodes[i].desc->flags;
+		spin_lock_init(&pipe->nodes[i].buf_list_lock);
+		INIT_LIST_HEAD(&pipe->nodes[i].buf_list);
+
+		pipe->nodes[i].crop.left = 0;
+		pipe->nodes[i].crop.top = 0;
+		pipe->nodes[i].crop.width =
+			pipe->nodes[i].desc->frmsizeenum->stepwise.max_width;
+		pipe->nodes[i].crop.height =
+			pipe->nodes[i].desc->frmsizeenum->stepwise.max_height;
+
+		pipe->nodes[i].compose.left = 0;
+		pipe->nodes[i].compose.top = 0;
+		pipe->nodes[i].compose.width =
+			pipe->nodes[i].desc->frmsizeenum->stepwise.max_width;
+		pipe->nodes[i].compose.height =
+			pipe->nodes[i].desc->frmsizeenum->stepwise.max_height;
+	}
+
+	return 0;
+}
+
+int mtk_imgsys_pipe_release(struct mtk_imgsys_pipe *pipe)
+{
+	mutex_destroy(&pipe->lock);
+
+	return 0;
+}
+
+int mtk_imgsys_pipe_next_job_id(struct mtk_imgsys_pipe *pipe)
+{
+	int global_job_id = atomic_inc_return(&pipe->pipe_job_sequence);
+
+	return (global_job_id & 0x0000FFFF) | (pipe->desc->id << 16);
+}
+
+void mtk_imgsys_pipe_debug_job(struct mtk_imgsys_pipe *pipe,
+			       struct mtk_imgsys_request *req)
+{
+	int i;
+
+	dev_dbg(pipe->imgsys_dev->dev, "%s:%s: pipe-job(%p),id(%d)\n",
+		__func__, pipe->desc->name, req, req->id);
+
+	for (i = 0; i < pipe->desc->total_queues ; i++) {
+		if (req->buf_map[i])
+			dev_dbg(pipe->imgsys_dev->dev, "%s:%s:buf(%p)\n",
+				pipe->desc->name, pipe->nodes[i].desc->name,
+				req->buf_map[i]);
+	}
+}
+
+static unsigned int mtk_imgsys_get_stride(unsigned int width,
+					  const struct mtk_imgsys_dev_format *dfmt,
+					  unsigned int plane)
+{
+	unsigned int stride =
+		(width + dfmt->fmt->pixels_per_group - 1) /
+		dfmt->fmt->pixels_per_group * dfmt->fmt->bytes_per_group[plane];
+
+	return (stride + dfmt->align - 1) / dfmt->align * dfmt->align;
+}
+
+static unsigned int mtk_imgsys_get_height(unsigned int height,
+					  const struct mtk_imgsys_dev_format *dfmt,
+					  unsigned int plane)
+{
+	unsigned int plane_height =
+		(height + dfmt->fmt->vertical_sub_sampling[plane] - 1) /
+		dfmt->fmt->vertical_sub_sampling[plane];
+
+	return (plane_height + dfmt->scan_align - 1) / dfmt->scan_align * dfmt->scan_align;
+}
+
+void mtk_imgsys_pipe_try_fmt(struct mtk_imgsys_video_device *node,
+			     struct v4l2_format *fmt,
+			     const struct v4l2_format *ufmt,
+			     const struct mtk_imgsys_dev_format *dfmt)
+{
+	unsigned int i;
+
+	if (!dfmt)
+		return;
+
+	fmt->type = ufmt->type;
+	fmt->fmt.pix_mp.width =
+		clamp_val(ufmt->fmt.pix_mp.width,
+			  node->desc->frmsizeenum->stepwise.min_width,
+			  node->desc->frmsizeenum->stepwise.max_width);
+	fmt->fmt.pix_mp.height =
+		clamp_val(ufmt->fmt.pix_mp.height,
+			  node->desc->frmsizeenum->stepwise.min_height,
+			  node->desc->frmsizeenum->stepwise.max_height);
+	fmt->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT;
+	fmt->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
+	fmt->fmt.pix_mp.colorspace = V4L2_COLORSPACE_SRGB;
+	fmt->fmt.pix_mp.field = V4L2_FIELD_NONE;
+
+	fmt->fmt.pix_mp.pixelformat = dfmt->fmt->format;
+	fmt->fmt.pix_mp.num_planes = dfmt->fmt->num_planes;
+
+	for (i = 0; i < fmt->fmt.pix_mp.num_planes; ++i) {
+		struct v4l2_plane_pix_format *plane =
+			&fmt->fmt.pix_mp.plane_fmt[i];
+		const struct v4l2_plane_pix_format *uplane;
+
+		uplane = &ufmt->fmt.pix_mp.plane_fmt[i];
+		plane->bytesperline =
+			mtk_imgsys_get_stride(fmt->fmt.pix_mp.width, dfmt, i);
+		if (plane->bytesperline < uplane->bytesperline)
+			plane->bytesperline = uplane->bytesperline;
+
+		plane->sizeimage = plane->bytesperline *
+			mtk_imgsys_get_height(fmt->fmt.pix_mp.height, dfmt, i);
+
+		plane->sizeimage += dfmt->fmt->ext_data;
+	}
+}
+
+static void set_meta_fmt(struct mtk_imgsys_pipe *pipe,
+			 struct v4l2_meta_format *fmt,
+			 const struct mtk_imgsys_dev_format *dev_fmt)
+{
+	fmt->dataformat = dev_fmt->fmt->format;
+	fmt->buffersize = dev_fmt->fmt->buffer_size;
+}
+
+void mtk_imgsys_pipe_load_default_fmt(struct mtk_imgsys_pipe *pipe,
+				      struct mtk_imgsys_video_device *node,
+				      struct v4l2_format *fmt)
+{
+	fmt->type = node->desc->buf_type;
+	if (mtk_imgsys_buf_is_meta(node->desc->buf_type)) {
+		set_meta_fmt(pipe, &fmt->fmt.meta,
+			     &node->desc->fmts[0]);
+	} else {
+		fmt->fmt.pix_mp.width = node->desc->default_width;
+		fmt->fmt.pix_mp.height = node->desc->default_height;
+		mtk_imgsys_pipe_try_fmt(node, fmt, fmt,
+					&node->desc->fmts[0]);
+	}
+}
+
+const struct mtk_imgsys_dev_format*
+mtk_imgsys_pipe_find_fmt(struct mtk_imgsys_pipe *pipe,
+			 struct mtk_imgsys_video_device *node,
+			 u32 format)
+{
+	int i;
+
+	for (i = 0; i < node->desc->num_fmts; i++) {
+		if (node->desc->fmts[i].fmt->format == format)
+			return &node->desc->fmts[i];
+	}
+
+	return NULL;
+}
+
+void mtk_imgsys_pipe_try_enqueue(struct mtk_imgsys_pipe *pipe)
+{
+	struct mtk_imgsys_request *req = NULL;
+	unsigned long flag;
+
+	if (!pipe->streaming)
+		return;
+
+	spin_lock_irqsave(&pipe->pending_job_lock, flag);
+	if (list_empty(&pipe->pipe_job_pending_list)) {
+		spin_unlock_irqrestore(&pipe->pending_job_lock, flag);
+		return;
+	}
+
+	req = list_first_entry(&pipe->pipe_job_pending_list, struct mtk_imgsys_request, list);
+	list_del(&req->list);
+	pipe->num_pending_jobs--;
+	spin_unlock_irqrestore(&pipe->pending_job_lock, flag);
+
+	spin_lock_irqsave(&pipe->running_job_lock, flag);
+	list_add_tail(&req->list,
+		      &pipe->pipe_job_running_list);
+	pipe->num_jobs++;
+	spin_unlock_irqrestore(&pipe->running_job_lock, flag);
+
+	mtk_imgsys_hw_enqueue(pipe->imgsys_dev, req);
+	dev_dbg(pipe->imgsys_dev->dev,
+		"%s:%s: pending jobs(%d), running jobs(%d)\n",
+		__func__, pipe->desc->name, pipe->num_pending_jobs,
+		pipe->num_jobs);
+}
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.h
new file mode 100644
index 000000000000..b69cfd0043d3
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.h
@@ -0,0 +1,427 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_IMGSYS_DEV_H_
+#define _MTK_IMGSYS_DEV_H_
+
+#include <linux/completion.h>
+#include <linux/types.h>
+#include <linux/time.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
+#include <linux/regulator/consumer.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-device.h>
+#include <linux/videodev2.h>
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-v4l2.h>
+
+#include "mtk_header_desc.h"
+
+#define MTK_IMGSYS_MEDIA_MODEL_NAME	"MTK-ISP-DIP-V4L2"
+
+#define MTK_IMGSYS_OUTPUT_MIN_WIDTH		1U
+#define MTK_IMGSYS_OUTPUT_MIN_HEIGHT		1U
+#define MTK_IMGSYS_OUTPUT_MAX_WIDTH		5376U
+#define MTK_IMGSYS_OUTPUT_MAX_HEIGHT		4032U
+
+#define MTK_IMGSYS_CAPTURE_MIN_WIDTH		1U
+#define MTK_IMGSYS_CAPTURE_MIN_HEIGHT		1U
+#define MTK_IMGSYS_CAPTURE_MAX_WIDTH		5376U
+#define MTK_IMGSYS_CAPTURE_MAX_HEIGHT		4032U
+
+/**
+ * struct mtk_imgsys_dev_format - Device format for MediaTek Image System
+ * @fmt: Pointer to the Image System format structure
+ * @align: Alignment requirement
+ * @scan_align: Scan alignment requirement
+ *
+ * This structure defines the format used by the MediaTek Image System device.
+ * It includes a pointer to the format structure, and alignment and scan
+ * alignment requirements.
+ */
+struct mtk_imgsys_dev_format {
+	const struct mtk_imgsys_format *fmt;
+	u32 align;
+	u32 scan_align;
+};
+
+/**
+ * struct mtk_imgsys_dev_buffer - Device buffer for MediaTek Image System
+ * @vbb: Video buffer structure for V4L2
+ * @fmt: Format of the video buffer
+ * @dev_fmt: Pointer to the device-specific format structure
+ * @isp_daddr: DMA addresses for ISP processing, indexed by plane
+ * @scp_daddr: DMA addresses for SCP processing, indexed by plane
+ * @crop: Crop information for image processing
+ * @compose: Composition rectangle for output
+ * @rotation: Rotation angle for the image
+ * @hflip: Horizontal flip flag
+ * @vflip: Vertical flip flag
+ * @resize_ratio: Ratio for resizing the image
+ * @dataofst: Offset for the data buffer
+ * @list: List head for buffer management
+ *
+ * This structure represents the buffer used by the MediaTek ImgSys device.
+ * It includes various parameters for buffer management and image processing,
+ * such as format, DMA addresses, cropping, composition, rotation, flipping,
+ * resizing, and list management. This buffer is essential for handling
+ * image data in the device's processing pipeline.
+ */
+struct mtk_imgsys_dev_buffer {
+	struct vb2_v4l2_buffer vbb;
+	struct v4l2_format fmt;
+	const struct mtk_imgsys_dev_format *dev_fmt;
+	dma_addr_t isp_daddr[VB2_MAX_PLANES];
+	dma_addr_t scp_daddr[VB2_MAX_PLANES];
+	struct mtk_imgsys_crop crop;
+	struct v4l2_rect compose;
+	__u32 rotation;
+	__u32 hflip;
+	__u32 vflip;
+	__u32 resize_ratio;
+	__u32 dataofst;
+	struct list_head list;
+};
+
+/**
+ * struct mtk_imgsys_pipe_desc - Description of an image processing pipeline
+ * @name: Name of the pipeline
+ * @id: Identifier for the pipeline
+ * @queue_descs: Pointer to an array of video device descriptors
+ * @total_queues: Total number of queues in the pipeline
+ *
+ * This structure describes an image processing pipeline within the MediaTek
+ * image system. It includes the name and identifier of the pipeline, and
+ * an array of video device descriptors along with the total number of queues.
+ */
+struct mtk_imgsys_pipe_desc {
+	char *name;
+	int id;
+	struct mtk_imgsys_video_device_desc *queue_descs;
+	int total_queues;
+};
+
+/**
+ * struct mtk_imgsys_video_device_desc - Description of a video device
+ * @id: Identifier for the video device
+ * @name: Name of the video device
+ * @buf_type: Buffer type used by the video device
+ * @cap: Capabilities of the video device
+ * @smem_alloc: Using the smem_dev as alloc device or not
+ * @supports_ctrls: Flag indicating if the device supports controls
+ * @fmts: Pointer to an array of supported formats
+ * @num_fmts: Number of supported formats
+ * @description: Description of the video device
+ * @default_width: Default width of the video frames
+ * @default_height: Default height of the video frames
+ * @dma_port: DMA port used by the video device
+ * @frmsizeenum: Pointer to an array of frame size enumerations
+ * @flags: Additional flags for the video device
+ *
+ * This structure describes a video device within the MediaTek image system.
+ * It includes various properties such as the identifier, name, buffer type,
+ * capabilities, supported formats, and other relevant details.
+ */
+struct mtk_imgsys_video_device_desc {
+	int id;
+	char *name;
+	u32 buf_type;
+	u32 cap;
+	int smem_alloc;
+	int supports_ctrls;
+	const struct mtk_imgsys_dev_format *fmts;
+	int num_fmts;
+	char *description;
+	int default_width;
+	int default_height;
+	unsigned int dma_port;
+	const struct v4l2_frmsizeenum *frmsizeenum;
+	u32 flags;
+};
+
+/**
+ * struct mtk_imgsys_dev_queue - Device queue structure for image system
+ * @vbq: VB2 queue structure
+ * @lock: Mutex to serialize vb2 queue and video device operations
+ * @dev_fmt: Pointer to the device format structure
+ *
+ * This structure defines the device queue for the image system, including the
+ * VB2 queue, a mutex for serializing operations, and a pointer to the device
+ * format.
+ */
+struct mtk_imgsys_dev_queue {
+	struct vb2_queue vbq;
+	struct mutex lock; /* Protect the vb2_queue */
+	const struct mtk_imgsys_dev_format *dev_fmt;
+};
+
+/**
+ * struct mtk_imgsys_video_device -
+ * Video device structure for MediaTek Image System
+ *
+ * @vdev: Video device structure
+ * @dev_q: Device queue for buffer management
+ * @vdev_fmt: Format of the video device
+ * @vdev_pad: Media pad for the video device
+ * @pad_fmt: Media bus frame format for the pad
+ * @ctrl_handler: Control handler for V4L2 controls
+ * @resize_ratio_ctrl: Pointer to the resize ratio control
+ * @flags: Link attribute flags (e.g., MEDIA_LNK_FL_ENABLED)
+ * @desc: Pointer to the video device description structure
+ * @buf_list: List head for buffer management
+ * @crop: Crop rectangle for the video device
+ * @compose: Composition rectangle for the video device
+ * @rotation: Rotation angle for the video device
+ * @vflip: Vertical flip flag
+ * @hflip: Horizontal flip flag
+ * @resize_ratio: Resize ratio for the video device
+ * @buf_list_lock: Spinlock to protect the in-device buffer list
+ *
+ * This structure represents the video device used by the MediaTek Image System.
+ * It includes various parameters for managing video buffers, formats, media pads,
+ * controls, cropping, composition, rotation, flipping, resizing, and buffer list
+ * protection. This structure is essential for handling video data and device
+ * configuration in the MediaTek Image System.
+ */
+struct mtk_imgsys_video_device {
+	struct video_device vdev;
+	struct mtk_imgsys_dev_queue dev_q;
+	struct v4l2_format vdev_fmt;
+	struct media_pad vdev_pad;
+	struct v4l2_mbus_framefmt pad_fmt;
+	struct v4l2_ctrl_handler ctrl_handler;
+	struct v4l2_ctrl *resize_ratio_ctrl;
+	u32 flags; /* Link attribute flags, e.g. MEDIA_LNK_FL_ENABLED */
+	const struct mtk_imgsys_video_device_desc *desc;
+	struct list_head buf_list;
+	struct v4l2_rect crop;
+	struct v4l2_rect compose;
+	int rotation;
+	bool vflip;
+	bool hflip;
+	int resize_ratio;
+	/* protect the in-device buffer list */
+	spinlock_t buf_list_lock;
+};
+
+/**
+ * struct mtk_imgsys_pipe - Pipeline structure for MediaTek Image System
+ * @imgsys_dev: Pointer to the image system device
+ * @nodes: Pointer to the video device nodes associated with the pipeline
+ * @nodes_streaming: Bitmap representing streaming status of nodes
+ * @nodes_enabled: Bitmap representing enabled status of nodes
+ * @streaming: Flag indicating if the pipeline is currently streaming
+ * @subdev_pads: Media pads for subdevice connections
+ * @pipeline: Media pipeline structure
+ * @subdev: V4L2 subdevice structure
+ * @fh: File handle for subdevice operations
+ * @pipe_job_sequence: Atomic counter for job sequencing
+ * @pipe_job_pending_list: List head for pending jobs in the pipeline
+ * @num_pending_jobs: Number of pending jobs in the pipeline
+ * @pending_job_lock: To protect pipe_job_pending_list and num_pending_jobs
+ * @pipe_job_running_list: List head for running jobs in the pipeline
+ * @running_job_lock: Spinlock to protect pipe_job_running_list
+ * @num_jobs: Total number of jobs in the pipeline
+ * @lock: Mutex to serialize stream on/off and buffer enqueue operations
+ * @desc: Pointer to the pipeline description structure
+ *
+ * This structure represents a pipeline in the MediaTek Image System. It includes
+ * various components for managing the image processing pipeline, such as device
+ * pointers, video nodes, streaming flags, media pads, pipeline configuration,
+ * subdevice operations, job management, and synchronization mechanisms.
+ * This structure is essential for coordinating the flow of image data through
+ * the processing pipeline.
+ */
+struct mtk_imgsys_pipe {
+	struct mtk_imgsys_dev *imgsys_dev;
+	struct mtk_imgsys_video_device *nodes;
+	unsigned long long nodes_streaming;
+	unsigned long long nodes_enabled;
+	int streaming;
+	struct media_pad *subdev_pads;
+	struct media_pipeline pipeline;
+	struct v4l2_subdev subdev;
+	struct v4l2_subdev_fh *fh;
+	atomic_t pipe_job_sequence;
+	struct list_head pipe_job_pending_list;
+	int num_pending_jobs;
+	/* protect pipe_job_pending_list and num_pending_jobs */
+	spinlock_t pending_job_lock;
+	struct list_head pipe_job_running_list;
+	/* protect pipe_job_running_list */
+	spinlock_t running_job_lock;
+	int num_jobs;
+	/* Serializes pipe's stream on/off and buffers enqueue operations */
+	struct mutex lock;
+	const struct mtk_imgsys_pipe_desc *desc;
+};
+
+/**
+ * struct mtk_imgsys_dev - MediaTek Image System Device Structure
+ * @dev: Pointer to the device structure.
+ * @imgsys_resource: Resource descriptor for image system hardware.
+ * @mdev: Media device structure for media controller framework integration.
+ * @v4l2_dev: V4L2 device structure for video device operations.
+ * @imgsys_pipe: Image system pipeline configuration structure.
+ * @cust_pipes: Pointer to custom pipeline descriptors.
+ * @clks: Array of clock bulk data for managing multiple clocks.
+ * @num_clks: Number of clocks in the clock array.
+ * @larbs: Array of device pointers for managing LARB (local arbiter).
+ * @num_larbs: Number of LARBs in the system.
+ * @scp: Pointer to the SCP (System Control Processor) structure.
+ * @rproc_handle: Handle for remote processor interface.
+ * @smem_dev: Device structure for shared memory operations.
+ * @num_mods: Number of modules in the image system.
+ */
+struct mtk_imgsys_dev {
+	/* Device and Resource Information */
+	struct device *dev;
+	struct resource *imgsys_resource;
+	/* Media and V4L2 Device Management */
+	struct media_device mdev;
+	struct v4l2_device v4l2_dev;
+	struct mtk_imgsys_pipe imgsys_pipe;
+	/* Imgsys Pipeline Information */
+	const struct mtk_imgsys_pipe_desc *cust_pipes;
+	/* Clock Information */
+	struct clk_bulk_data *clks;
+	int num_clks;
+	/* LARB (Local Arbitration) Control */
+	struct device **larbs;
+	unsigned int num_larbs;
+	/* SCP (System Control Processor) Integration */
+	struct mtk_scp *scp;
+	struct rproc *rproc_handle;
+	struct device *smem_dev;
+	/* Number of modules */
+	int num_mods;
+};
+
+/**
+ * struct req_frameparam - Request frame parameters for MediaTek Image System
+ * @frame_no: Frame number identifier
+ * @state: State of the frame (e.g., init, timeout)
+ *
+ * This structure represents the parameters for a request frame in the MediaTek Image System.
+ * It includes various attributes such as the frame index, frame number, timestamp, state,
+ * and the number of input and output buffers. This structure is used to manage and track
+ * the frames within the image processing pipeline.
+ */
+struct req_frameparam {
+	u32		frame_no;
+	u8		state;
+} __packed;
+
+/**
+ * struct mtk_imgsys_request - Request structure for MediaTek Image System
+ * @req: Media request structure
+ * @imgsys_pipe: Pointer to the image system pipeline
+ * @id: Unique identifier for the request
+ * @buf_map: Pointer to an array of device buffers mapped to the request
+ * @list: List head for request management
+ * @img_fparam: Frame parameters associated with the request
+ * @composer_work: Work structure for composer tasks
+ * @runner_work: Work structure for runner tasks
+ * @working_buf: Pointer to the hardware working buffer
+ * @swfrm_info: Pointer to software frame information
+ * @buf_count: Atomic counter for buffer management
+ * @request_fd: File descriptor for the request
+ *
+ * This structure represents a request in the MediaTek Image System. It includes
+ * various parameters for managing media requests, image processing pipeline,
+ * buffer mapping, frame parameters, work tasks, hardware buffers, software frame
+ * information, buffer count, and request file descriptor. This structure is
+ * essential for handling and processing image requests within the MediaTek Image
+ * System.
+ */
+struct mtk_imgsys_request {
+	struct media_request req;
+	struct mtk_imgsys_pipe *imgsys_pipe;
+	int id;
+	struct mtk_imgsys_dev_buffer **buf_map;
+	struct list_head list;
+	struct req_frameparam img_fparam;
+	atomic_t buf_count;
+	int request_fd;
+};
+
+static inline struct mtk_imgsys_video_device*
+mtk_imgsys_file_to_node(struct file *file)
+{
+	return container_of(video_devdata(file),
+			    struct mtk_imgsys_video_device, vdev);
+}
+
+static inline struct mtk_imgsys_pipe*
+mtk_imgsys_subdev_to_pipe(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct mtk_imgsys_pipe, subdev);
+}
+
+static inline struct mtk_imgsys_dev*
+mtk_imgsys_mdev_to_dev(struct media_device *mdev)
+{
+	return container_of(mdev, struct mtk_imgsys_dev, mdev);
+}
+
+static inline struct mtk_imgsys_video_device*
+mtk_imgsys_vbq_to_node(struct vb2_queue *vq)
+{
+	return container_of(vq, struct mtk_imgsys_video_device, dev_q.vbq);
+}
+
+static inline struct mtk_imgsys_dev_buffer*
+mtk_imgsys_vb2_buf_to_dev_buf(struct vb2_buffer *vb)
+{
+	return container_of(vb, struct mtk_imgsys_dev_buffer, vbb.vb2_buf);
+}
+
+static inline struct mtk_imgsys_request*
+mtk_imgsys_media_req_to_imgsys_req(struct media_request *req)
+{
+	return container_of(req, struct mtk_imgsys_request, req);
+}
+
+static inline int mtk_imgsys_buf_is_meta(u32 type)
+{
+	return type == V4L2_BUF_TYPE_META_CAPTURE ||
+	       type == V4L2_BUF_TYPE_META_OUTPUT;
+}
+
+int mtk_imgsys_pipe_init(struct mtk_imgsys_dev *imgsys_dev,
+			 struct mtk_imgsys_pipe *pipe,
+			 const struct mtk_imgsys_pipe_desc *setting);
+
+int mtk_imgsys_pipe_release(struct mtk_imgsys_pipe *pipe);
+
+int mtk_imgsys_pipe_next_job_id(struct mtk_imgsys_pipe *pipe);
+
+void mtk_imgsys_pipe_debug_job(struct mtk_imgsys_pipe *pipe,
+			       struct mtk_imgsys_request *req);
+
+const struct mtk_imgsys_dev_format *
+mtk_imgsys_pipe_find_fmt(struct mtk_imgsys_pipe *pipe,
+			 struct mtk_imgsys_video_device *node,
+			 u32 format);
+
+void mtk_imgsys_pipe_try_fmt(struct mtk_imgsys_video_device *node,
+			     struct v4l2_format *fmt,
+			     const struct v4l2_format *ufmt,
+			     const struct mtk_imgsys_dev_format *dfmt);
+
+void mtk_imgsys_pipe_load_default_fmt(struct mtk_imgsys_pipe *pipe,
+				      struct mtk_imgsys_video_device *node,
+				      struct v4l2_format *fmt_to_fill);
+
+void mtk_imgsys_pipe_try_enqueue(struct mtk_imgsys_pipe *pipe);
+
+#endif /* _MTK_IMGSYS_DEV_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-formats.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-formats.c
new file mode 100644
index 000000000000..6a3a98e9cd42
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-formats.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek ISP ImgSys formats
+ *
+ * Copyright (c) 2024 MediaTek Inc.
+ */
+
+#include <linux/mtkisp_imgsys.h>
+#include <linux/videodev2.h>
+#include "mtk_imgsys-formats.h"
+
+const struct mtk_imgsys_format mtk_imgsys_format_nv12 = {
+	.format = V4L2_PIX_FMT_NV12,
+	.num_planes = 2,
+	.pixels_per_group = 2,
+	.bytes_per_group = {2, 2},
+	.vertical_sub_sampling = { 1, 2 },
+};
+
+const struct mtk_imgsys_format mtk_imgsys_format_nv21 = {
+	.format = V4L2_PIX_FMT_NV21,
+	.num_planes = 2,
+	.pixels_per_group = 2,
+	.bytes_per_group = {2, 2},
+	.vertical_sub_sampling = { 1, 2 },
+};
+
+const struct mtk_imgsys_format mtk_imgsys_format_grey = {
+	.format = V4L2_PIX_FMT_GREY,
+	.num_planes = 1,
+	.pixels_per_group = 1,
+	.bytes_per_group = { 1 },
+	.vertical_sub_sampling = { 1 },
+};
+
+const struct mtk_imgsys_format mtk_imgsys_format_2p012p = {
+	.format = V4L2_PIX_FMT_YUV_2P012P,
+	.num_planes = 2,
+	.pixels_per_group = 64,
+	.bytes_per_group = { 96, 96 },
+	.vertical_sub_sampling = { 1, 2 },
+};
+
+const struct mtk_imgsys_format mtk_imgsys_format_2p010p = {
+	.format = V4L2_PIX_FMT_YUV_2P010P,
+	.num_planes = 2,
+	.pixels_per_group = 64,
+	.bytes_per_group = { 80, 80 },
+	.vertical_sub_sampling = { 1, 2 },
+};
+
+const struct mtk_imgsys_format mtk_imgsys_format_y8 = {
+	.format = V4L2_PIX_FMT_MTISP_Y8,
+	.num_planes = 1,
+	.pixels_per_group = 1,
+	.bytes_per_group = { 1 },
+	.vertical_sub_sampling = { 1 },
+};
+
+const struct mtk_imgsys_format mtk_imgsys_format_y16 = {
+	.format = V4L2_PIX_FMT_MTISP_Y16,
+	.num_planes = 1,
+	.buffer_size = 0,
+	.pixels_per_group = 1,
+	.bytes_per_group = { 2 },
+	.vertical_sub_sampling = { 1 },
+};
+
+const struct mtk_imgsys_format mtk_imgsys_format_y32 = {
+	.format = V4L2_PIX_FMT_MTISP_Y32,
+	.num_planes = 1,
+	.buffer_size = 0,
+	.pixels_per_group = 1,
+	.bytes_per_group = { 4 },
+	.vertical_sub_sampling = { 1 },
+};
+
+const struct mtk_imgsys_format mtk_imgsys_format_warp2p = {
+	.format = V4L2_PIX_FMT_WARP2P,
+	.num_planes = 2,
+	.buffer_size = 0,
+	.pixels_per_group = 4,
+	.bytes_per_group = { 8, 8 },
+	.vertical_sub_sampling = { 1, 1 },
+};
+
+const struct mtk_imgsys_format mtk_imgsys_format_sgbrg10 = {
+	.format = V4L2_PIX_FMT_MTISP_SGBRG10,
+	.num_planes = 1,
+	.buffer_size = 0,
+	.pixels_per_group = 64,
+	.bytes_per_group = { 80 },
+	.vertical_sub_sampling = { 1 },
+};
+
+const struct mtk_imgsys_format mtk_imgsys_format_srggb10 = {
+	.format = V4L2_PIX_FMT_MTISP_SRGGB10,
+	.num_planes = 1,
+	.buffer_size = 0,
+	.pixels_per_group = 64,
+	.bytes_per_group = { 80 },
+	.vertical_sub_sampling = { 1 },
+};
+
+const struct mtk_imgsys_format mtk_imgsys_format_sgrbg10 = {
+	.format = V4L2_PIX_FMT_MTISP_SGRBG10,
+	.num_planes = 1,
+	.buffer_size = 0,
+	.pixels_per_group = 64,
+	.bytes_per_group = { 80 },
+	.vertical_sub_sampling = { 1 },
+};
+
+const struct mtk_imgsys_format mtk_imgsys_format_aply8 = {
+	.format = V4L2_PIX_FMT_MTISP_APLY8,
+	.num_planes = 1,
+	.pixels_per_group = 1,
+	.bytes_per_group = { 1 },
+	.vertical_sub_sampling = { 1 },
+	.ext_data = SIZE_OF_APL_DATA,
+};
+
+const struct mtk_imgsys_format mtk_imgsys_format_metai = {
+	.format = V4L2_META_FMT_MTISP_TUN_PARAMS,
+	.num_planes = 1,
+	.buffer_size = SIZE_OF_TUNING_META,
+};
+
+const struct mtk_imgsys_format mtk_imgsys_format_stt = {
+	.format = V4L2_META_FMT_MTISP_STAT_PARAMS,
+	.num_planes = 1,
+	.buffer_size = SIZE_OF_STATISTICS_META,
+};
+
+const struct mtk_imgsys_format mtk_imgsys_format_ctrlmeta = {
+	.format = V4L2_META_FMT_MTISP_CTL_PARAMS,
+	.num_planes = 1,
+	.buffer_size = SIZE_OF_CTRL_META,
+};
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-formats.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-formats.h
new file mode 100644
index 000000000000..cbf8b2b414f8
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-formats.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * MediaTek ISP ImgSys formats
+ *
+ * Copyright (c) 2024 MediaTek Inc.
+ */
+
+#ifndef _MTK_IMGSYS_FORMATS_H_
+#define _MTK_IMGSYS_FORMATS_H_
+
+/**
+ * struct mtk_imgsys_format - MediaTek Image System format description
+ * @format: Pixel format identifier (e.g., V4L2_PIX_FMT_*).
+ * @num_planes: Number of planes in the image format. For example, 1 for
+ * single-plane formats, 2 or 3 for multi-plane formats like YUV420.
+ * @buffer_size: Total buffer size in bytes required to store the image data.
+ * @pixels_per_group: Number of pixels per group, which s defined as the
+ * minimum number of pixels (including padding) necessary in a row when the
+ * image has only one column of effective pixels.
+ * @bytes_per_group: Array specifying the number of bytes per group for each
+ * plane. The array size is 3 to support up to 3 planes.
+ * @vertical_sub_sampling: Array specifying the vertical subsampling factor for
+ * each plane. The array size is 3 to support up to 3 planes.
+ * @ext_data: Additional data or flags related to the image format.
+ *
+ * This structure is used to describe the format of images processed by the
+ * MediaTek Image System. It includes information about the pixel format,
+ * number of planes, buffer size, and other relevant details.
+ */
+struct mtk_imgsys_format {
+	u32 format;
+	u8 num_planes;
+	u32 buffer_size;
+	u32 pixels_per_group;
+	u32 bytes_per_group[3];
+	u32 vertical_sub_sampling[3];
+	u32 ext_data;
+};
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_nv12;
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_nv21;
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_grey;
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_2p012p;
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_2p010p;
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_y8;
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_y16;
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_y32;
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_warp2p;
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_sgbrg10;
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_srggb10;
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_sgrbg10;
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_aply8;
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_metai;
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_stt;
+
+extern const struct mtk_imgsys_format mtk_imgsys_format_ctrlmeta;
+
+#endif /* _MTK_IMGSYS_FORMATS_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_ops.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_ops.h
new file mode 100644
index 000000000000..6dc4b7b60832
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_ops.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_IMGSYS_MODULES_H_
+#define _MTK_IMGSYS_MODULES_H_
+
+/**
+ * enum mtk_imgsys_module
+ *
+ * Definition about supported hw modules
+ */
+enum mtk_imgsys_module {
+	IMGSYS_MOD_IMGMAIN = 0,
+	IMGSYS_MOD_WPE,
+	IMGSYS_MOD_TRAW,
+	IMGSYS_MOD_DIP,
+	IMGSYS_MOD_PQDIP,
+	IMGSYS_MOD_ME,
+	IMGSYS_MOD_MAX,
+};
+
+#endif /* _MTK_IMGSYS_MODULES_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.c
new file mode 100644
index 000000000000..94888682a939
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *         Holmes Chiou <holmes.chiou at mediatek.com>
+ *
+ */
+
+#include "mtk_imgsys-of.h"
+
+static void merge_module_pipelines(const struct mtk_imgsys_pipe_desc *imgsys_pipe,
+				   const struct cust_data *data)
+{
+	const struct mtk_imgsys_mod_pipe_desc *module_pipe;
+	unsigned int mod_num;
+	unsigned int i, j, k;
+
+	mod_num = data->mod_num;
+	k = 0;
+	for (i = 0; i < mod_num; i++) {
+		module_pipe = &data->module_pipes[i];
+		for (j = 0; j < module_pipe->node_num; j++) {
+			imgsys_pipe->queue_descs[k] = module_pipe->vnode_desc[j];
+			k++;
+		}
+	}
+}
+
+void init_imgsys_pipeline(const struct cust_data *data)
+{
+	const struct mtk_imgsys_pipe_desc *imgsys_pipe;
+	unsigned int i;
+
+	for (i = 0; i < data->pipe_num; i++) {
+		imgsys_pipe = &data->pipe_settings[i];
+		merge_module_pipelines(imgsys_pipe, data);
+	}
+}
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.h
new file mode 100644
index 000000000000..5088c9df704c
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *         Holmes Chiou <holmes.chiou at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_IMGSYS_OF_H_
+#define _MTK_IMGSYS_OF_H_
+
+#include <linux/clk.h>
+#include "mtk_imgsys-dev.h"
+
+/**
+ * struct mtk_imgsys_mod_pipe_desc - Description of a module's pipeline
+ * @vnode_desc: Pointer to an array of video device descriptors for the module.
+ * @node_num: Number of video nodes associated with this module.
+ */
+struct mtk_imgsys_mod_pipe_desc {
+	const struct mtk_imgsys_video_device_desc *vnode_desc;
+	unsigned int node_num;
+};
+
+/**
+ * struct cust_data - Custom data structure for image system configuration
+ * @clks: Pointer to an array of clock bulk data for the module.
+ * @clk_num: Number of clocks associated with this module.
+ * @module_pipes: Pointer to an array of module pipeline descriptions.
+ * @mod_num: Number of modules in the pipeline.
+ * @pipe_settings: Pointer to pipeline settings for the module.
+ * @pipe_num: Number of pipeline settings.
+ */
+struct cust_data {
+	struct clk_bulk_data *clks;
+	unsigned int clk_num;
+	const struct mtk_imgsys_mod_pipe_desc *module_pipes;
+	unsigned int mod_num;
+	const struct mtk_imgsys_pipe_desc *pipe_settings;
+	unsigned int pipe_num;
+};
+
+/**
+ * init_imgsys_pipeline - Initialize the video nodes in image system pipeline
+ * @data: Pointer to the custom data structure containing configuration
+ *  information.
+ *
+ * This function initializes the image system pipeline based on the provided
+ * custom data. It sets up the necessary modules's video nodes as defined in
+ * the cust_data structure.
+ */
+void init_imgsys_pipeline(const struct cust_data *data);
+
+#endif /* _MTK_IMGSYS_OF_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
new file mode 100644
index 000000000000..9cdcdb0a0200
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *
+ */
+
+#include "mtk_imgsys-sys.h"
+
+void mtk_imgsys_hw_enqueue(struct mtk_imgsys_dev *imgsys_dev,
+			   struct mtk_imgsys_request *req)
+{
+	/* Function implementation will be provided in subsequent patches */
+}
+
+int mtk_imgsys_hw_streamon(struct mtk_imgsys_pipe *pipe)
+{
+	/* Function implementation will be provided in subsequent patches */
+	return 0;
+}
+
+int mtk_imgsys_hw_streamoff(struct mtk_imgsys_pipe *pipe)
+{
+	/* Function implementation will be provided in subsequent patches */
+	return 0;
+}
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.h
new file mode 100644
index 000000000000..9f9b0b627305
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ */
+
+#ifndef _MTK_IMGSYS_SYS_H_
+#define _MTK_IMGSYS_SYS_H_
+
+#include "mtk_imgsys-dev.h"
+
+/*
+ * mtk_imgsys_hw_streamon - Start streaming on the ImgSys pipeline
+ * @pipe: Pointer to the ImgSys pipeline structure
+ *
+ * This function starts streaming on the specified ImgSys pipeline. It ensures
+ * that the pipeline is properly initialized and ready to process image data.
+ * This is typically used to begin image processing operations after the pipeline
+ * has been configured.
+ *
+ * Return: 0 on success, a negative error code on failure
+ */
+int mtk_imgsys_hw_streamon(struct mtk_imgsys_pipe *pipe);
+
+/*
+ * mtk_imgsys_hw_streamoff - Stop streaming on the ImgSys pipeline
+ * @pipe: Pointer to the ImgSys pipeline structure
+ *
+ * This function stops streaming on the specified ImgSys pipeline. It ensures
+ * that any ongoing image processing tasks are halted and the pipeline is
+ * properly shut down. This is typically used when the image processing
+ * operations are no longer needed or when the system is being reconfigured.
+ *
+ * Return: 0 on success, a negative error code on failure
+ */
+int mtk_imgsys_hw_streamoff(struct mtk_imgsys_pipe *pipe);
+
+/*
+ * mtk_imgsys_hw_enqueue - Enqueue a request to the ImgSys hardware
+ * @imgsys_dev: Pointer to the ImgSys device structure
+ * @req: Pointer to the ImgSys request structure
+ *
+ * This function enqueues a request to the ImgSys hardware for processing.
+ * The request contains information about the image processing tasks to be
+ * performed by the hardware. The function ensures that the request is properly
+ * queued and ready for execution by the ImgSys hardware.
+ */
+void mtk_imgsys_hw_enqueue(struct mtk_imgsys_dev *imgsys_dev,
+			   struct mtk_imgsys_request *req);
+
+#endif /* _MTK_IMGSYS_SYS_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
new file mode 100644
index 000000000000..cfd65858c751
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
@@ -0,0 +1,1684 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *
+ */
+#include <linux/platform_device.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/dma-mapping.h>
+#include <linux/vmalloc.h>
+#include <linux/videodev2.h>
+#include <media/videobuf2-dma-contig.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-event.h>
+#include "linux/mtkisp_imgsys.h"
+#include "mtk_imgsys-of.h"
+#include "mtk_imgsys-module_ops.h"
+#include "mtk_imgsys-vnode_id.h"
+#include "mtk_imgsys_v4l2_vnode.h"
+#include "mtk_imgsys-dev.h"
+#include "mtk_imgsys-sys.h"
+
+#define IMGSYS_MAX_BUFFERS	256
+#define IMGSYS_SUSPEND_TIME 3000 /* ms */
+
+static int mtk_imgsys_sd_subscribe_event(struct v4l2_subdev *subdev,
+					 struct v4l2_fh *fh,
+					 struct v4l2_event_subscription *sub)
+{
+	switch (sub->type) {
+	case V4L2_EVENT_FRAME_SYNC:
+		return v4l2_event_subscribe(fh, sub, 64, NULL);
+	default:
+		return -EINVAL;
+	}
+}
+
+static const struct v4l2_subdev_core_ops mtk_imgsys_subdev_core_ops = {
+	.subscribe_event = mtk_imgsys_sd_subscribe_event,
+	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
+};
+
+static int mtk_imgsys_subdev_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct mtk_imgsys_pipe *pipe = mtk_imgsys_subdev_to_pipe(sd);
+	int ret;
+
+	if (enable) {
+		ret = mtk_imgsys_hw_streamon(pipe);
+		if (ret)
+			dev_err(pipe->imgsys_dev->dev,
+				"%s: pipe(%d) stream on failed\n",
+				pipe->desc->name, pipe->desc->id);
+	} else {
+		ret = mtk_imgsys_hw_streamoff(pipe);
+		if (ret)
+			dev_err(pipe->imgsys_dev->dev,
+				"%s: pipe(%d) stream off failed\n",
+				pipe->desc->name, pipe->desc->id);
+	}
+
+	return ret;
+}
+
+static const struct v4l2_subdev_video_ops mtk_imgsys_subdev_video_ops = {
+	.s_stream = mtk_imgsys_subdev_s_stream,
+};
+
+static const struct v4l2_subdev_ops mtk_imgsys_subdev_ops = {
+	.core = &mtk_imgsys_subdev_core_ops,
+	.video = &mtk_imgsys_subdev_video_ops,
+};
+
+static int mtk_imgsys_link_setup(struct media_entity *entity,
+				 const struct media_pad *local,
+				 const struct media_pad *remote,
+				 u32 flags)
+{
+	struct mtk_imgsys_pipe *pipe =
+		container_of(entity, struct mtk_imgsys_pipe, subdev.entity);
+	u32 pad = local->index;
+
+	WARN_ON(entity->obj_type != MEDIA_ENTITY_TYPE_V4L2_SUBDEV);
+	WARN_ON(pad >= pipe->desc->total_queues);
+
+	mutex_lock(&pipe->lock);
+
+	if (flags & MEDIA_LNK_FL_ENABLED)
+		pipe->nodes_enabled++;
+	else
+		pipe->nodes_enabled--;
+
+	pipe->nodes[pad].flags &= ~MEDIA_LNK_FL_ENABLED;
+	pipe->nodes[pad].flags |= flags & MEDIA_LNK_FL_ENABLED;
+
+	dev_dbg(pipe->imgsys_dev->dev,
+		"%s: link setup, flags(0x%x), (%s)%d -->(%s)%d, nodes_enabled(0x%llx)\n",
+		pipe->desc->name, flags, local->entity->name, local->index,
+		remote->entity->name, remote->index, pipe->nodes_enabled);
+
+	mutex_unlock(&pipe->lock);
+
+	return 0;
+}
+
+static const struct media_entity_operations mtk_imgsys_media_ops = {
+	.link_setup = mtk_imgsys_link_setup,
+	.link_validate = v4l2_subdev_link_validate,
+};
+
+static int mtk_imgsys_vb2_meta_buf_prepare(struct vb2_buffer *vb)
+{
+	struct mtk_imgsys_pipe *pipe = vb2_get_drv_priv(vb->vb2_queue);
+	struct mtk_imgsys_video_device *node =
+					mtk_imgsys_vbq_to_node(vb->vb2_queue);
+	struct device *dev = pipe->imgsys_dev->dev;
+	const struct v4l2_format *fmt = &node->vdev_fmt;
+
+	if (vb->planes[0].length < fmt->fmt.meta.buffersize) {
+		dev_err(dev,
+			"%s:%s: size error(user:%d, required:%d)\n",
+			pipe->desc->name, node->desc->name,
+			vb->planes[0].length, fmt->fmt.meta.buffersize);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int mtk_imgsys_vb2_video_buf_prepare(struct vb2_buffer *vb)
+{
+	struct mtk_imgsys_pipe *pipe = vb2_get_drv_priv(vb->vb2_queue);
+	struct mtk_imgsys_video_device *node =
+					mtk_imgsys_vbq_to_node(vb->vb2_queue);
+	struct device *dev = pipe->imgsys_dev->dev;
+	const struct v4l2_format *fmt = &node->vdev_fmt;
+	unsigned int size;
+	int i;
+
+	for (i = 0; i < vb->num_planes; i++) {
+		size = fmt->fmt.pix_mp.plane_fmt[i].sizeimage;
+		if (vb->planes[i].length < size) {
+			dev_err(dev,
+				"%s:%s: size error(user:%d, required:%d)\n",
+				pipe->desc->name, node->desc->name,
+				vb->planes[i].length, size);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static int mtk_imgsys_vb2_buf_out_validate(struct vb2_buffer *vb)
+{
+	struct vb2_v4l2_buffer *v4l2_buf = to_vb2_v4l2_buffer(vb);
+
+	if (v4l2_buf->field == V4L2_FIELD_ANY)
+		v4l2_buf->field = V4L2_FIELD_NONE;
+
+	if (v4l2_buf->field != V4L2_FIELD_NONE)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int mtk_imgsys_vb2_meta_buf_init(struct vb2_buffer *vb)
+{
+	struct mtk_imgsys_dev_buffer *dev_buf =
+					mtk_imgsys_vb2_buf_to_dev_buf(vb);
+	struct mtk_imgsys_pipe *pipe = vb2_get_drv_priv(vb->vb2_queue);
+	struct mtk_imgsys_video_device *node =
+					mtk_imgsys_vbq_to_node(vb->vb2_queue);
+
+	/*
+	 * The meta buffers are allocated from the SCP reserved memory.
+	 * Setup the mapping to ImgSys device here.
+	 */
+	dev_buf->scp_daddr[0] = vb2_dma_contig_plane_dma_addr(vb, 0);
+	dev_buf->isp_daddr[0] =
+		dma_map_resource(pipe->imgsys_dev->dev,
+				 dev_buf->scp_daddr[0],
+				 vb->planes[0].length,
+				 DMA_BIDIRECTIONAL,
+				 DMA_ATTR_SKIP_CPU_SYNC);
+	if (dma_mapping_error(pipe->imgsys_dev->dev,
+			      dev_buf->isp_daddr[0])) {
+		dev_err(pipe->imgsys_dev->dev,
+			"%s:%s: failed to map buffer: s_daddr(%pad)\n",
+			pipe->desc->name, node->desc->name,
+			&dev_buf->scp_daddr[0]);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int mtk_imgsys_vb2_video_buf_init(struct vb2_buffer *vb)
+{
+	struct mtk_imgsys_dev_buffer *dev_buf =
+					mtk_imgsys_vb2_buf_to_dev_buf(vb);
+	unsigned int plane;
+
+	for (plane = 0; plane < vb->num_planes; ++plane)
+		dev_buf->isp_daddr[plane] = vb2_dma_contig_plane_dma_addr(vb, plane);
+
+	return 0;
+}
+
+static void mtk_imgsys_vb2_queue_meta_buf_cleanup(struct vb2_buffer *vb)
+{
+	struct mtk_imgsys_dev_buffer *dev_buf =
+					mtk_imgsys_vb2_buf_to_dev_buf(vb);
+	struct mtk_imgsys_pipe *pipe = vb2_get_drv_priv(vb->vb2_queue);
+
+	dma_unmap_resource(pipe->imgsys_dev->dev,
+			   dev_buf->isp_daddr[0],
+			   vb->planes[0].length, DMA_BIDIRECTIONAL,
+			   DMA_ATTR_SKIP_CPU_SYNC);
+}
+
+static void mtk_imgsys_vb2_buf_queue(struct vb2_buffer *vb)
+{
+	struct vb2_v4l2_buffer *b = to_vb2_v4l2_buffer(vb);
+	struct mtk_imgsys_dev_buffer *dev_buf =
+					mtk_imgsys_vb2_buf_to_dev_buf(vb);
+	struct mtk_imgsys_request *req = NULL;
+	struct mtk_imgsys_video_device *node =
+					mtk_imgsys_vbq_to_node(vb->vb2_queue);
+	int buf_count;
+
+	if (!vb->request)
+		return;
+
+	req = mtk_imgsys_media_req_to_imgsys_req(vb->request);
+
+	dev_buf->dev_fmt = node->dev_q.dev_fmt;
+	spin_lock(&node->buf_list_lock);
+	list_add_tail(&dev_buf->list, &node->buf_list);
+	spin_unlock(&node->buf_list_lock);
+
+	buf_count = atomic_dec_return(&req->buf_count);
+	if (!buf_count) {
+		dev_dbg(&node->vdev.dev,
+			"framo_no: (%d), reqfd-%d\n",
+			req->img_fparam.frame_no, b->request_fd);
+		req->request_fd = b->request_fd;
+		mutex_lock(&req->imgsys_pipe->lock);
+		mtk_imgsys_pipe_try_enqueue(req->imgsys_pipe);
+		mutex_unlock(&req->imgsys_pipe->lock);
+	}
+}
+
+static int mtk_imgsys_vb2_meta_queue_setup(struct vb2_queue *vq,
+					   unsigned int *num_buffers,
+					   unsigned int *num_planes,
+					   unsigned int sizes[],
+					   struct device *alloc_devs[])
+{
+	struct mtk_imgsys_video_device *node = mtk_imgsys_vbq_to_node(vq);
+	const struct v4l2_format *fmt = &node->vdev_fmt;
+
+	if (*num_planes)
+		return 0;
+
+	*num_planes = 1;
+	sizes[0] = fmt->fmt.meta.buffersize;
+
+	return 0;
+}
+
+static int mtk_imgsys_vb2_video_queue_setup(struct vb2_queue *vq,
+					    unsigned int *num_buffers,
+					    unsigned int *num_planes,
+					    unsigned int sizes[],
+					    struct device *alloc_devs[])
+{
+	struct mtk_imgsys_video_device *node = mtk_imgsys_vbq_to_node(vq);
+	const struct v4l2_format *fmt = &node->vdev_fmt;
+	int i;
+
+	if (*num_planes)
+		return 0;
+
+	*num_planes = fmt->fmt.pix_mp.num_planes;
+
+	for (i = 0; i < *num_planes; i++) {
+		sizes[i] = fmt->fmt.pix_mp.plane_fmt[i].sizeimage;
+		*num_buffers = clamp_val(*num_buffers, 1, IMGSYS_MAX_BUFFERS);
+	}
+	return 0;
+}
+
+static void mtk_imgsys_return_all_buffers(struct mtk_imgsys_pipe *pipe,
+					  struct mtk_imgsys_video_device *node,
+					  enum vb2_buffer_state state)
+{
+	struct mtk_imgsys_dev_buffer *b, *b0;
+
+	spin_lock(&node->buf_list_lock);
+	list_for_each_entry_safe(b, b0, &node->buf_list, list) {
+		list_del(&b->list);
+		vb2_buffer_done(&b->vbb.vb2_buf, state);
+	}
+	spin_unlock(&node->buf_list_lock);
+}
+
+static int mtk_imgsys_vb2_start_streaming(struct vb2_queue *vq,
+					  unsigned int count)
+{
+	struct mtk_imgsys_pipe *pipe = vb2_get_drv_priv(vq);
+	struct mtk_imgsys_video_device *node = mtk_imgsys_vbq_to_node(vq);
+	int ret;
+
+	if (!pipe->nodes_streaming) {
+		ret = media_pipeline_start(&node->vdev.entity.pads[0], &pipe->pipeline);
+		if (ret < 0) {
+			dev_info(pipe->imgsys_dev->dev,
+				 "%s:%s: media_pipeline_start failed(%d)\n",
+				 pipe->desc->name, node->desc->name, ret);
+			goto fail_return_bufs;
+		}
+	}
+
+	mutex_lock(&pipe->lock);
+	if (!(node->flags & MEDIA_LNK_FL_ENABLED)) {
+		dev_info(pipe->imgsys_dev->dev,
+			 "%s:%s: stream on failed, node is not enabled\n",
+			 pipe->desc->name, node->desc->name);
+
+		ret = -ENOLINK;
+		goto fail_stop_pipeline;
+	}
+
+	pipe->nodes_streaming++;
+	if (pipe->nodes_streaming == pipe->nodes_enabled) {
+		/* Start streaming of the whole pipeline */
+		ret = v4l2_subdev_call(&pipe->subdev, video, s_stream, 1);
+		if (ret < 0) {
+			dev_info(pipe->imgsys_dev->dev,
+				 "%s:%s: sub dev s_stream(1) failed(%d)\n",
+				 pipe->desc->name, node->desc->name, ret);
+
+			goto fail_stop_pipeline;
+		}
+	}
+
+	dev_dbg(pipe->imgsys_dev->dev,
+		"%s:%s:%s nodes_streaming(0x%llx), nodes_enable(0x%llx)\n",
+		__func__, pipe->desc->name, node->desc->name,
+		pipe->nodes_streaming, pipe->nodes_enabled);
+
+	mutex_unlock(&pipe->lock);
+
+	return 0;
+
+fail_stop_pipeline:
+	mutex_unlock(&pipe->lock);
+	media_pipeline_stop(&node->vdev.entity.pads[0]);
+
+fail_return_bufs:
+	mtk_imgsys_return_all_buffers(pipe, node, VB2_BUF_STATE_QUEUED);
+
+	return ret;
+}
+
+static void mtk_imgsys_vb2_stop_streaming(struct vb2_queue *vq)
+{
+	struct mtk_imgsys_pipe *pipe = vb2_get_drv_priv(vq);
+	struct mtk_imgsys_video_device *node = mtk_imgsys_vbq_to_node(vq);
+	int ret;
+
+	mutex_lock(&pipe->lock);
+
+	if (pipe->streaming) {
+		ret = v4l2_subdev_call(&pipe->subdev, video, s_stream, 0);
+		if (ret)
+			dev_info(pipe->imgsys_dev->dev,
+				 "%s:%s: sub dev s_stream(0) failed(%d)\n",
+				 pipe->desc->name, node->desc->name, ret);
+	}
+
+	pipe->nodes_streaming--;
+
+	if (!pipe->nodes_streaming)
+		media_pipeline_stop(&node->vdev.entity.pads[0]);
+
+	mtk_imgsys_return_all_buffers(pipe, node, VB2_BUF_STATE_ERROR);
+
+	mutex_unlock(&pipe->lock);
+}
+
+static void mtk_imgsys_vb2_request_complete(struct vb2_buffer *vb)
+{
+	struct mtk_imgsys_video_device *node =
+					mtk_imgsys_vbq_to_node(vb->vb2_queue);
+
+	v4l2_ctrl_request_complete(vb->req_obj.req,
+				   &node->ctrl_handler);
+}
+
+static const struct vb2_ops mtk_imgsys_vb2_meta_ops = {
+	.buf_queue = mtk_imgsys_vb2_buf_queue,
+	.queue_setup = mtk_imgsys_vb2_meta_queue_setup,
+	.buf_init = mtk_imgsys_vb2_meta_buf_init,
+	.buf_prepare  = mtk_imgsys_vb2_meta_buf_prepare,
+	.buf_out_validate = mtk_imgsys_vb2_buf_out_validate,
+	.buf_cleanup = mtk_imgsys_vb2_queue_meta_buf_cleanup,
+	.start_streaming = mtk_imgsys_vb2_start_streaming,
+	.stop_streaming = mtk_imgsys_vb2_stop_streaming,
+	.wait_prepare = vb2_ops_wait_prepare,
+	.wait_finish = vb2_ops_wait_finish,
+	.buf_request_complete = mtk_imgsys_vb2_request_complete,
+};
+
+static const struct vb2_ops mtk_imgsys_vb2_video_ops = {
+	.buf_queue = mtk_imgsys_vb2_buf_queue,
+	.queue_setup = mtk_imgsys_vb2_video_queue_setup,
+	.buf_init = mtk_imgsys_vb2_video_buf_init,
+	.buf_prepare  = mtk_imgsys_vb2_video_buf_prepare,
+	.buf_out_validate = mtk_imgsys_vb2_buf_out_validate,
+	.start_streaming = mtk_imgsys_vb2_start_streaming,
+	.stop_streaming = mtk_imgsys_vb2_stop_streaming,
+	.wait_prepare = vb2_ops_wait_prepare,
+	.wait_finish = vb2_ops_wait_finish,
+	.buf_request_complete = mtk_imgsys_vb2_request_complete,
+};
+
+static int mtk_imgsys_video_device_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+	struct mtk_imgsys_video_device *node =
+		container_of(ctrl->handler,
+			     struct mtk_imgsys_video_device, ctrl_handler);
+
+	switch (ctrl->id) {
+	case V4L2_CID_ROTATE:
+		node->rotation = ctrl->val;
+		break;
+	case V4L2_CID_VFLIP:
+		node->vflip = ctrl->val;
+		break;
+	case V4L2_CID_HFLIP:
+		node->hflip = ctrl->val;
+		break;
+	case V4L2_CID_MTK_IMG_RESIZE_RATIO:
+		node->resize_ratio = ctrl->val;
+		break;
+	default:
+		dev_dbg(&node->vdev.dev, "[%s] doesn't support ctrl(%d)\n",
+			node->desc->name, ctrl->id);
+		return -EINVAL;
+	}
+
+	node->rotation = ctrl->val;
+
+	return 0;
+}
+
+static const struct v4l2_ctrl_ops mtk_imgsys_video_device_ctrl_ops = {
+	.s_ctrl = mtk_imgsys_video_device_s_ctrl,
+};
+
+static int mtk_imgsys_vidioc_qbuf(struct file *file, void *priv,
+				  struct v4l2_buffer *buf)
+{
+	struct mtk_imgsys_pipe *pipe = video_drvdata(file);
+	struct mtk_imgsys_video_device *node = mtk_imgsys_file_to_node(file);
+	struct vb2_buffer *vb = node->dev_q.vbq.bufs[buf->index];
+	struct mtk_imgsys_dev_buffer *dev_buf =
+					mtk_imgsys_vb2_buf_to_dev_buf(vb);
+
+	if (!dev_buf)
+		return -EFAULT;
+
+	dev_buf->fmt = node->vdev_fmt;
+	dev_buf->rotation = node->rotation;
+	dev_buf->crop.c = node->crop;
+	dev_buf->compose = node->compose;
+	dev_buf->hflip = node->hflip;
+	dev_buf->vflip = node->vflip;
+	dev_buf->resize_ratio = node->resize_ratio;
+
+	return vb2_qbuf(node->vdev.queue, &pipe->imgsys_dev->mdev, buf);
+}
+
+static int mtk_imgsys_videoc_querycap(struct file *file, void *fh,
+				      struct v4l2_capability *cap)
+{
+	struct mtk_imgsys_pipe *pipe = video_drvdata(file);
+
+	strscpy(cap->driver, pipe->desc->name, sizeof(cap->driver));
+	strscpy(cap->card, pipe->desc->name, sizeof(cap->card));
+	snprintf(cap->bus_info, sizeof(cap->bus_info),
+		 "platform:%s", dev_name(pipe->imgsys_dev->mdev.dev));
+
+	return 0;
+}
+
+static int mtk_imgsys_videoc_try_fmt(struct file *file, void *fh,
+				     struct v4l2_format *f)
+{
+	struct mtk_imgsys_pipe *pipe = video_drvdata(file);
+	struct mtk_imgsys_video_device *node = mtk_imgsys_file_to_node(file);
+	const struct mtk_imgsys_dev_format *dev_fmt;
+	struct v4l2_format try_fmt;
+
+	memset(&try_fmt, 0, sizeof(try_fmt));
+
+	dev_fmt = mtk_imgsys_pipe_find_fmt(pipe, node,
+					   f->fmt.pix_mp.pixelformat);
+	if (!dev_fmt) {
+		dev_fmt = &node->desc->fmts[0];
+		dev_dbg(pipe->imgsys_dev->dev,
+			"%s:%s:%s: dev_fmt(%d) not found, use default(%d)\n",
+			__func__, pipe->desc->name, node->desc->name,
+			f->fmt.pix_mp.pixelformat, dev_fmt->fmt->format);
+	}
+
+	mtk_imgsys_pipe_try_fmt(node, &try_fmt, f, dev_fmt);
+	*f = try_fmt;
+
+	return 0;
+}
+
+static int mtk_imgsys_videoc_g_fmt(struct file *file, void *fh,
+				   struct v4l2_format *f)
+{
+	struct mtk_imgsys_video_device *node = mtk_imgsys_file_to_node(file);
+
+	*f = node->vdev_fmt;
+
+	return 0;
+}
+
+static int mtk_imgsys_videoc_s_fmt(struct file *file, void *fh,
+				   struct v4l2_format *f)
+{
+	struct mtk_imgsys_video_device *node = mtk_imgsys_file_to_node(file);
+	struct mtk_imgsys_pipe *pipe = video_drvdata(file);
+	const struct mtk_imgsys_dev_format *dev_fmt;
+
+	dev_fmt = mtk_imgsys_pipe_find_fmt(pipe, node,
+					   f->fmt.pix_mp.pixelformat);
+	if (!dev_fmt) {
+		dev_fmt = &node->desc->fmts[0];
+		dev_info(pipe->imgsys_dev->dev,
+			 "%s:%s:%s: dev_fmt(%d) not found, use default(%d)\n",
+			 __func__, pipe->desc->name, node->desc->name,
+			 f->fmt.pix_mp.pixelformat, dev_fmt->fmt->format);
+	}
+
+	memset(&node->vdev_fmt, 0, sizeof(node->vdev_fmt));
+
+	mtk_imgsys_pipe_try_fmt(node, &node->vdev_fmt, f, dev_fmt);
+	*f = node->vdev_fmt;
+
+	node->dev_q.dev_fmt = dev_fmt;
+	node->crop.left = 0; /* reset crop setting of nodes */
+	node->crop.top = 0;
+	node->crop.width = f->fmt.pix_mp.width;
+	node->crop.height = f->fmt.pix_mp.height;
+	node->compose.left = 0;
+	node->compose.top = 0;
+	node->compose.width = f->fmt.pix_mp.width;
+	node->compose.height = f->fmt.pix_mp.height;
+	if (node->resize_ratio_ctrl)
+		v4l2_ctrl_s_ctrl(node->resize_ratio_ctrl, 0);
+
+	return 0;
+}
+
+static int mtk_imgsys_videoc_enum_framesizes(struct file *file, void *priv,
+					     struct v4l2_frmsizeenum *sizes)
+{
+	struct mtk_imgsys_pipe *pipe = video_drvdata(file);
+	struct mtk_imgsys_video_device *node = mtk_imgsys_file_to_node(file);
+	const struct mtk_imgsys_dev_format *dev_fmt;
+
+	dev_fmt = mtk_imgsys_pipe_find_fmt(pipe, node, sizes->pixel_format);
+
+	if (!dev_fmt || sizes->index)
+		return -EINVAL;
+
+	sizes->type = node->desc->frmsizeenum->type;
+	sizes->stepwise.max_width =
+		node->desc->frmsizeenum->stepwise.max_width;
+	sizes->stepwise.min_width =
+		node->desc->frmsizeenum->stepwise.min_width;
+	sizes->stepwise.max_height =
+		node->desc->frmsizeenum->stepwise.max_height;
+	sizes->stepwise.min_height =
+		node->desc->frmsizeenum->stepwise.min_height;
+	sizes->stepwise.step_height =
+		node->desc->frmsizeenum->stepwise.step_height;
+	sizes->stepwise.step_width =
+		node->desc->frmsizeenum->stepwise.step_width;
+
+	return 0;
+}
+
+static int mtk_imgsys_videoc_enum_fmt(struct file *file, void *fh,
+				      struct v4l2_fmtdesc *f)
+{
+	struct mtk_imgsys_video_device *node = mtk_imgsys_file_to_node(file);
+
+	if (f->index >= node->desc->num_fmts)
+		return -EINVAL;
+
+	strscpy(f->description, node->desc->description, sizeof(f->description));
+	f->pixelformat = node->desc->fmts[f->index].fmt->format;
+	f->flags = 0;
+
+	return 0;
+}
+
+static int mtk_imgsys_meta_enum_format(struct file *file, void *fh,
+				       struct v4l2_fmtdesc *f)
+{
+	struct mtk_imgsys_video_device *node = mtk_imgsys_file_to_node(file);
+
+	if (f->index > 0)
+		return -EINVAL;
+
+	strscpy(f->description, node->desc->description, sizeof(f->description));
+
+	f->pixelformat = node->vdev_fmt.fmt.meta.dataformat;
+	f->flags = 0;
+
+	return 0;
+}
+
+static int mtk_imgsys_videoc_g_meta_fmt(struct file *file, void *fh,
+					struct v4l2_format *f)
+{
+	struct mtk_imgsys_video_device *node = mtk_imgsys_file_to_node(file);
+	*f = node->vdev_fmt;
+
+	return 0;
+}
+
+static int mtk_imgsys_videoc_s_meta_fmt(struct file *file, void *fh,
+					struct v4l2_format *f)
+{
+	struct mtk_imgsys_video_device *node = mtk_imgsys_file_to_node(file);
+	struct mtk_imgsys_pipe *pipe = video_drvdata(file);
+	const struct mtk_imgsys_dev_format *dev_fmt;
+
+	if (pipe->streaming || vb2_is_busy(&node->dev_q.vbq))
+		return -EBUSY;
+
+	dev_fmt = mtk_imgsys_pipe_find_fmt(pipe, node,
+					   f->fmt.meta.dataformat);
+	if (!dev_fmt) {
+		dev_fmt = &node->desc->fmts[0];
+		dev_info(pipe->imgsys_dev->dev,
+			 "%s:%s:%s: dev_fmt(%d) not found, use default(%d)\n",
+			 __func__, pipe->desc->name, node->desc->name,
+			 f->fmt.meta.dataformat, dev_fmt->fmt->format);
+	}
+
+	memset(&node->vdev_fmt, 0, sizeof(node->vdev_fmt));
+
+	f->fmt.meta.dataformat = dev_fmt->fmt->format;
+	f->fmt.meta.buffersize = dev_fmt->fmt->buffer_size;
+
+	node->dev_q.dev_fmt = dev_fmt;
+	node->vdev_fmt = *f;
+
+	return 0;
+}
+
+static int mtk_imgsys_g_selection(struct file *file, void *priv,
+				  struct v4l2_selection *s)
+{
+	struct mtk_imgsys_video_device *node = mtk_imgsys_file_to_node(file);
+
+	if (!node)
+		return -EINVAL;
+
+	if ((node->desc->buf_type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
+	     s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) ||
+	    (node->desc->buf_type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE &&
+	     s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE))
+		return -EINVAL;
+
+	switch (s->target) {
+	case V4L2_SEL_TGT_CROP:
+		s->r = node->crop;
+		break;
+	case V4L2_SEL_TGT_CROP_BOUNDS:
+	case V4L2_SEL_TGT_CROP_DEFAULT:
+		s->r.width = node->desc->default_width;
+		s->r.height = node->desc->default_width;
+		s->r.left = 0;
+		s->r.top = 0;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int mtk_imgsys_s_selection(struct file *file, void *priv,
+				  struct v4l2_selection *s)
+{
+	struct mtk_imgsys_video_device *node = mtk_imgsys_file_to_node(file);
+
+	if (!node)
+		return -EINVAL;
+
+	if ((node->desc->buf_type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
+	     s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) ||
+	    (node->desc->buf_type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE &&
+	     s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE))
+		return -EINVAL;
+
+	switch (s->target) {
+	case V4L2_SEL_TGT_CROP:
+		node->crop = s->r;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct v4l2_ioctl_ops mtk_imgsys_v4l2_video_out_ioctl_ops = {
+	.vidioc_querycap = mtk_imgsys_videoc_querycap,
+
+	.vidioc_enum_framesizes = mtk_imgsys_videoc_enum_framesizes,
+	.vidioc_enum_fmt_vid_out = mtk_imgsys_videoc_enum_fmt,
+	.vidioc_g_fmt_vid_out_mplane = mtk_imgsys_videoc_g_fmt,
+	.vidioc_s_fmt_vid_out_mplane = mtk_imgsys_videoc_s_fmt,
+	.vidioc_try_fmt_vid_out_mplane = mtk_imgsys_videoc_try_fmt,
+
+	.vidioc_g_selection = mtk_imgsys_g_selection,
+	.vidioc_s_selection = mtk_imgsys_s_selection,
+
+	.vidioc_reqbufs = vb2_ioctl_reqbufs,
+	.vidioc_create_bufs = vb2_ioctl_create_bufs,
+	.vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+	.vidioc_remove_bufs = vb2_ioctl_remove_bufs,
+	.vidioc_querybuf = vb2_ioctl_querybuf,
+	.vidioc_qbuf = mtk_imgsys_vidioc_qbuf,
+	.vidioc_dqbuf = vb2_ioctl_dqbuf,
+	.vidioc_streamon = vb2_ioctl_streamon,
+	.vidioc_streamoff = vb2_ioctl_streamoff,
+	.vidioc_expbuf = vb2_ioctl_expbuf,
+
+	.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
+	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+};
+
+static const struct v4l2_ioctl_ops mtk_imgsys_v4l2_video_cap_ioctl_ops = {
+	.vidioc_querycap = mtk_imgsys_videoc_querycap,
+
+	.vidioc_enum_framesizes = mtk_imgsys_videoc_enum_framesizes,
+	.vidioc_enum_fmt_vid_cap = mtk_imgsys_videoc_enum_fmt,
+	.vidioc_g_fmt_vid_cap_mplane = mtk_imgsys_videoc_g_fmt,
+	.vidioc_s_fmt_vid_cap_mplane = mtk_imgsys_videoc_s_fmt,
+	.vidioc_try_fmt_vid_cap_mplane = mtk_imgsys_videoc_try_fmt,
+
+	.vidioc_g_selection = mtk_imgsys_g_selection,
+	.vidioc_s_selection = mtk_imgsys_s_selection,
+
+	.vidioc_reqbufs = vb2_ioctl_reqbufs,
+	.vidioc_create_bufs = vb2_ioctl_create_bufs,
+	.vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+	.vidioc_remove_bufs = vb2_ioctl_remove_bufs,
+	.vidioc_querybuf = vb2_ioctl_querybuf,
+	.vidioc_qbuf = mtk_imgsys_vidioc_qbuf,
+	.vidioc_dqbuf = vb2_ioctl_dqbuf,
+	.vidioc_streamon = vb2_ioctl_streamon,
+	.vidioc_streamoff = vb2_ioctl_streamoff,
+	.vidioc_expbuf = vb2_ioctl_expbuf,
+
+	.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
+	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+};
+
+static const struct v4l2_ioctl_ops mtk_imgsys_v4l2_meta_out_ioctl_ops = {
+	.vidioc_querycap = mtk_imgsys_videoc_querycap,
+
+	.vidioc_enum_fmt_meta_out = mtk_imgsys_meta_enum_format,
+	.vidioc_g_fmt_meta_out = mtk_imgsys_videoc_g_meta_fmt,
+	.vidioc_s_fmt_meta_out = mtk_imgsys_videoc_s_meta_fmt,
+	.vidioc_try_fmt_meta_out = mtk_imgsys_videoc_g_meta_fmt,
+
+	.vidioc_reqbufs = vb2_ioctl_reqbufs,
+	.vidioc_create_bufs = vb2_ioctl_create_bufs,
+	.vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+	.vidioc_remove_bufs = vb2_ioctl_remove_bufs,
+	.vidioc_querybuf = vb2_ioctl_querybuf,
+	.vidioc_qbuf = mtk_imgsys_vidioc_qbuf,
+	.vidioc_dqbuf = vb2_ioctl_dqbuf,
+	.vidioc_streamon = vb2_ioctl_streamon,
+	.vidioc_streamoff = vb2_ioctl_streamoff,
+	.vidioc_expbuf = vb2_ioctl_expbuf,
+};
+
+static const struct v4l2_ioctl_ops mtk_imgsys_v4l2_meta_cap_ioctl_ops = {
+	.vidioc_querycap = mtk_imgsys_videoc_querycap,
+
+	.vidioc_enum_fmt_meta_cap = mtk_imgsys_meta_enum_format,
+	.vidioc_g_fmt_meta_cap = mtk_imgsys_videoc_g_meta_fmt,
+	.vidioc_s_fmt_meta_cap = mtk_imgsys_videoc_s_meta_fmt,
+	.vidioc_try_fmt_meta_cap = mtk_imgsys_videoc_g_meta_fmt,
+
+	.vidioc_reqbufs = vb2_ioctl_reqbufs,
+	.vidioc_create_bufs = vb2_ioctl_create_bufs,
+	.vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+	.vidioc_remove_bufs = vb2_ioctl_remove_bufs,
+	.vidioc_querybuf = vb2_ioctl_querybuf,
+	.vidioc_qbuf = mtk_imgsys_vidioc_qbuf,
+	.vidioc_dqbuf = vb2_ioctl_dqbuf,
+	.vidioc_streamon = vb2_ioctl_streamon,
+	.vidioc_streamoff = vb2_ioctl_streamoff,
+	.vidioc_expbuf = vb2_ioctl_expbuf,
+};
+
+static struct media_request *mtk_imgsys_request_alloc(struct media_device *mdev)
+{
+	struct mtk_imgsys_request *req;
+	struct mtk_imgsys_pipe *pipe;
+
+	pipe = &mtk_imgsys_mdev_to_dev(mdev)->imgsys_pipe;
+	req = vzalloc(sizeof(*req));
+	if (!req)
+		return NULL;
+
+	req->buf_map = vzalloc(pipe->desc->total_queues *
+			       sizeof(struct mtk_imgsys_dev_buffer *));
+	if (!req->buf_map)
+		goto error;
+
+	return &req->req;
+
+error:
+	vfree(req);
+	return NULL;
+}
+
+static void mtk_imgsys_request_free(struct media_request *req)
+{
+	struct mtk_imgsys_request *imgsys_req =
+					mtk_imgsys_media_req_to_imgsys_req(req);
+
+	vfree(imgsys_req->buf_map);
+	vfree(imgsys_req);
+}
+
+static int mtk_imgsys_vb2_request_validate(struct media_request *req)
+{
+	struct media_request_object *obj;
+	struct mtk_imgsys_dev *imgsys_dev = mtk_imgsys_mdev_to_dev(req->mdev);
+	struct mtk_imgsys_request *imgsys_req =
+					mtk_imgsys_media_req_to_imgsys_req(req);
+	struct mtk_imgsys_pipe *pipe = NULL;
+	struct mtk_imgsys_pipe *pipe_prev = NULL;
+	struct mtk_imgsys_dev_buffer **buf_map = imgsys_req->buf_map;
+	int buf_count = 0;
+	int i;
+
+	for (i = 0; i < imgsys_dev->imgsys_pipe.desc->total_queues; i++)
+		buf_map[i] = NULL;
+
+	list_for_each_entry(obj, &req->objects, list) {
+		struct vb2_buffer *vb;
+		struct mtk_imgsys_dev_buffer *dev_buf;
+		struct mtk_imgsys_video_device *node;
+
+		if (!vb2_request_object_is_buffer(obj))
+			continue;
+
+		vb = container_of(obj, struct vb2_buffer, req_obj);
+		node = mtk_imgsys_vbq_to_node(vb->vb2_queue);
+		pipe = vb2_get_drv_priv(vb->vb2_queue);
+		if (pipe_prev && pipe != pipe_prev) {
+			dev_dbg(imgsys_dev->dev,
+				"%s:%s:%s:found buf of different pipes(%p,%p)\n",
+				__func__, node->desc->name,
+				req->debug_str, pipe, pipe_prev);
+			return -EINVAL;
+		}
+
+		pipe_prev = pipe;
+		dev_buf = mtk_imgsys_vb2_buf_to_dev_buf(vb);
+		imgsys_req->buf_map[node->desc->id] = dev_buf;
+		buf_count++;
+
+		dev_dbg(pipe->imgsys_dev->dev,
+			"%s:%s: added buf(%p) to pipe-job(%p), buf_count(%d)\n",
+			pipe->desc->name, node->desc->name, dev_buf,
+			imgsys_req, buf_count);
+	}
+
+	if (!pipe) {
+		dev_dbg(imgsys_dev->dev,
+			"%s: no buffer in the request(%p)\n",
+			req->debug_str, req);
+
+		return -ENOENT;
+	}
+
+	atomic_set(&imgsys_req->buf_count, buf_count);
+	imgsys_req->id = mtk_imgsys_pipe_next_job_id(pipe);
+	imgsys_req->imgsys_pipe = pipe;
+	mtk_imgsys_pipe_debug_job(pipe, imgsys_req);
+
+	return vb2_request_validate(req);
+}
+
+static void mtk_imgsys_vb2_request_queue(struct media_request *req)
+{
+	struct mtk_imgsys_request *imgsys_req =
+					mtk_imgsys_media_req_to_imgsys_req(req);
+	struct mtk_imgsys_pipe *pipe = imgsys_req->imgsys_pipe;
+	unsigned long flag;
+
+	spin_lock_irqsave(&pipe->pending_job_lock, flag);
+	list_add_tail(&imgsys_req->list, &pipe->pipe_job_pending_list);
+	pipe->num_pending_jobs++;
+	dev_dbg(req->mdev->dev,
+		"%s:%s: current num of pending jobs(%d)\n",
+		__func__, pipe->desc->name, pipe->num_pending_jobs);
+	spin_unlock_irqrestore(&pipe->pending_job_lock, flag);
+	vb2_request_queue(req);
+}
+
+static const struct media_device_ops mtk_imgsys_media_req_ops = {
+	.req_validate = mtk_imgsys_vb2_request_validate,
+	.req_queue = mtk_imgsys_vb2_request_queue,
+	.req_alloc = mtk_imgsys_request_alloc,
+	.req_free = mtk_imgsys_request_free,
+};
+
+static const struct v4l2_file_operations mtk_imgsys_v4l2_fops = {
+	.unlocked_ioctl = video_ioctl2,
+	.open = v4l2_fh_open,
+	.release = vb2_fop_release,
+	.poll = vb2_fop_poll,
+	.mmap = vb2_fop_mmap,
+#ifdef CONFIG_COMPAT
+	.compat_ioctl32 = v4l2_compat_ioctl32,
+#endif
+};
+
+static int mtk_imgsys_dev_media_register(struct device *dev,
+					 struct media_device *media_dev)
+{
+	int ret;
+
+	media_dev->dev = dev;
+	strscpy(media_dev->model, MTK_IMGSYS_MEDIA_MODEL_NAME, sizeof(media_dev->model));
+	snprintf(media_dev->bus_info, sizeof(media_dev->bus_info),
+		 "platform:%s", dev_name(dev));
+	media_dev->hw_revision = 0;
+	media_dev->ops = &mtk_imgsys_media_req_ops;
+	media_device_init(media_dev);
+
+	ret = media_device_register(media_dev);
+	if (ret)
+		media_device_cleanup(media_dev);
+
+	return ret;
+}
+
+static int mtk_imgsys_video_device_v4l2_register(struct mtk_imgsys_pipe *pipe,
+						 struct mtk_imgsys_video_device *node)
+{
+	struct vb2_queue *vbq = &node->dev_q.vbq;
+	struct video_device *vdev = &node->vdev;
+	struct media_link *link;
+	int ret;
+
+	switch (node->desc->buf_type) {
+	case V4L2_BUF_TYPE_META_OUTPUT:
+		vbq->ops = &mtk_imgsys_vb2_meta_ops;
+		vdev->ioctl_ops = &mtk_imgsys_v4l2_meta_out_ioctl_ops;
+		break;
+	case V4L2_BUF_TYPE_META_CAPTURE:
+		vbq->ops = &mtk_imgsys_vb2_meta_ops;
+		vdev->ioctl_ops = &mtk_imgsys_v4l2_meta_cap_ioctl_ops;
+		break;
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
+		vbq->ops = &mtk_imgsys_vb2_video_ops;
+		vdev->ioctl_ops = &mtk_imgsys_v4l2_video_out_ioctl_ops;
+		break;
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
+		vbq->ops = &mtk_imgsys_vb2_video_ops;
+		vdev->ioctl_ops = &mtk_imgsys_v4l2_video_cap_ioctl_ops;
+		break;
+	default:
+		dev_info(pipe->imgsys_dev->dev,
+			 "unexpected buf_type %u\n", node->desc->buf_type);
+		return -EFAULT;
+	}
+
+	mutex_init(&node->dev_q.lock);
+	vdev->device_caps = node->desc->cap;
+	node->vdev_fmt.type = node->desc->buf_type;
+	mtk_imgsys_pipe_load_default_fmt(pipe, node, &node->vdev_fmt);
+
+	ret = media_entity_pads_init(&vdev->entity, 1, &node->vdev_pad);
+	if (ret) {
+		dev_info(pipe->imgsys_dev->dev,
+			 "failed initialize media entity (%d)\n", ret);
+		goto err_mutex_destroy;
+	}
+
+	node->vdev_pad.flags = V4L2_TYPE_IS_OUTPUT(node->desc->buf_type) ?
+		MEDIA_PAD_FL_SOURCE : MEDIA_PAD_FL_SINK;
+
+	vbq->type = node->vdev_fmt.type;
+	vbq->io_modes = VB2_MMAP | VB2_DMABUF;
+	vbq->mem_ops = &vb2_dma_contig_memops;
+	vbq->supports_requests = true;
+	vbq->requires_requests = true;
+	vbq->buf_struct_size = sizeof(struct mtk_imgsys_dev_buffer);
+	vbq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
+	vbq->min_queued_buffers = 0;
+	vbq->drv_priv = pipe;
+	vbq->lock = &node->dev_q.lock;
+	vbq->max_num_buffers = IMGSYS_MAX_BUFFERS;
+
+	ret = vb2_queue_init(vbq);
+	if (ret) {
+		dev_info(pipe->imgsys_dev->dev,
+			 "%s:%s:%s: failed to init vb2 queue(%d)\n",
+			 __func__, pipe->desc->name, node->desc->name,
+			 ret);
+		goto err_media_entity_cleanup;
+	}
+
+	strscpy(vbq->name, node->desc->name, sizeof(vbq->name));
+
+	snprintf(vdev->name, sizeof(vdev->name), "%s %s", pipe->desc->name,
+		 node->desc->name);
+	vdev->entity.name = vdev->name;
+	vdev->entity.function = MEDIA_ENT_F_IO_V4L;
+	vdev->entity.ops = NULL;
+	vdev->release = video_device_release_empty;
+	vdev->fops = &mtk_imgsys_v4l2_fops;
+	vdev->lock = &node->dev_q.lock;
+	if (node->desc->supports_ctrls)
+		vdev->ctrl_handler = &node->ctrl_handler;
+	else
+		vdev->ctrl_handler = NULL;
+	vdev->v4l2_dev = &pipe->imgsys_dev->v4l2_dev;
+	vdev->queue = &node->dev_q.vbq;
+	vdev->vfl_dir = V4L2_TYPE_IS_OUTPUT(node->desc->buf_type) ?
+		VFL_DIR_TX : VFL_DIR_RX;
+
+	vdev->queue->dev = pipe->imgsys_dev->dev;
+
+	if (node->desc->smem_alloc) {
+		vdev->queue->dev = pipe->imgsys_dev->smem_dev;
+		dev_dbg(pipe->imgsys_dev->dev,
+			"%s:%s: select smem_vb2_alloc_ctx(%p)\n",
+			pipe->desc->name, node->desc->name,
+			vdev->queue->dev);
+	} else {
+		vdev->queue->dev = pipe->imgsys_dev->dev;
+		dev_dbg(pipe->imgsys_dev->dev,
+			"%s:%s: select default_vb2_alloc_ctx(%p)\n",
+			pipe->desc->name, node->desc->name,
+			pipe->imgsys_dev->dev);
+	}
+
+	video_set_drvdata(vdev, pipe);
+
+	ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
+	if (ret) {
+		dev_info(pipe->imgsys_dev->dev,
+			 "failed to register video device (%d)\n", ret);
+		goto err_vb2_queue_release;
+	}
+	dev_dbg(pipe->imgsys_dev->dev, "registered vdev: %s\n",
+		vdev->name);
+
+	if (V4L2_TYPE_IS_OUTPUT(node->desc->buf_type))
+		ret = media_create_pad_link(&vdev->entity, 0,
+					    &pipe->subdev.entity,
+					    node->desc->id, node->flags);
+	else
+		ret = media_create_pad_link(&pipe->subdev.entity,
+					    node->desc->id, &vdev->entity,
+					    0, node->flags);
+	if (ret)
+		goto err_video_unregister_device;
+
+	vdev->intf_devnode = media_devnode_create(&pipe->imgsys_dev->mdev,
+						  MEDIA_INTF_T_V4L_VIDEO, 0,
+						  VIDEO_MAJOR, vdev->minor);
+	if (!vdev->intf_devnode) {
+		ret = -ENOMEM;
+		goto err_rm_links;
+	}
+
+	link = media_create_intf_link(&vdev->entity,
+				      &vdev->intf_devnode->intf,
+				      node->flags);
+	if (!link) {
+		ret = -ENOMEM;
+		goto err_rm_devnode;
+	}
+
+	return 0;
+
+err_rm_devnode:
+	media_devnode_remove(vdev->intf_devnode);
+
+err_rm_links:
+	media_entity_remove_links(&vdev->entity);
+
+err_video_unregister_device:
+	video_unregister_device(vdev);
+
+err_vb2_queue_release:
+	vb2_queue_release(&node->dev_q.vbq);
+
+err_media_entity_cleanup:
+	media_entity_cleanup(&node->vdev.entity);
+
+err_mutex_destroy:
+	mutex_destroy(&node->dev_q.lock);
+
+	return ret;
+}
+
+/******************************************************************************
+ * @array img_resize_ratio_menu
+ * @brief IMGSYS hardware supports multiple resizers.
+ *        - Any Ratio: Allows for any resize ratio, including
+ *          down 2, down 4, and down 42.
+ *        - Down 4: Specifically for downscaling by a factor of 4.
+ *        - Down 2: Specifically for downscaling by a factor of 2.
+ *        - Down42: Used for downscaling by a factor of 4 on the
+ *          first use, and by a factor of 2 on subsequent uses.
+ *        - NULL: Indicates the end of the menu options
+ ******************************************************************************/
+static const char * const img_resize_ratio_menu[] = {
+	"Any Ratio",
+	"Down 4",
+	"Down 2",
+	"Down 42",
+	NULL,
+};
+
+static const struct v4l2_ctrl_config cfg_mtk_resize_ratio = {
+	.ops = &mtk_imgsys_video_device_ctrl_ops,
+	.id = V4L2_CID_MTK_IMG_RESIZE_RATIO,
+	.name = "Image resize ratio",
+	.type = V4L2_CTRL_TYPE_MENU,
+	.max = 3,
+	.def = 0,
+	.qmenu = img_resize_ratio_menu,
+};
+
+static int mtk_imgsys_pipe_v4l2_ctrl_init(struct mtk_imgsys_pipe *imgsys_pipe)
+{
+	int i, ret;
+	struct mtk_imgsys_video_device *ctrl_node;
+
+	for (i = 0; i < MTK_IMGSYS_VIDEO_NODE_ID_TOTAL_NUM; i++) {
+		ctrl_node = &imgsys_pipe->nodes[i];
+		if (!ctrl_node->desc->supports_ctrls)
+			continue;
+
+		v4l2_ctrl_handler_init(&ctrl_node->ctrl_handler, 4);
+		v4l2_ctrl_new_std(&ctrl_node->ctrl_handler,
+				  &mtk_imgsys_video_device_ctrl_ops, V4L2_CID_ROTATE,
+				  0, 270, 90, 0);
+		v4l2_ctrl_new_std(&ctrl_node->ctrl_handler,
+				  &mtk_imgsys_video_device_ctrl_ops, V4L2_CID_VFLIP,
+				  0, 1, 1, 0);
+		v4l2_ctrl_new_std(&ctrl_node->ctrl_handler,
+				  &mtk_imgsys_video_device_ctrl_ops, V4L2_CID_HFLIP,
+				  0, 1, 1, 0);
+		ctrl_node->resize_ratio_ctrl =
+			v4l2_ctrl_new_custom(&ctrl_node->ctrl_handler,
+					     &cfg_mtk_resize_ratio, NULL);
+		ret = ctrl_node->ctrl_handler.error;
+		if (ret) {
+			dev_info(imgsys_pipe->imgsys_dev->dev,
+				 "%s create rotate ctrl failed:(%d)",
+				 ctrl_node->desc->name, ret);
+			goto err_free_ctrl_handlers;
+		}
+	}
+
+	return 0;
+
+err_free_ctrl_handlers:
+	for (; i >= 0; i--) {
+		ctrl_node = &imgsys_pipe->nodes[i];
+		if (!ctrl_node->desc->supports_ctrls)
+			continue;
+		v4l2_ctrl_handler_free(&ctrl_node->ctrl_handler);
+	}
+
+	return ret;
+}
+
+static void mtk_imgsys_pipe_v4l2_ctrl_release(struct mtk_imgsys_pipe *imgsys_pipe)
+{
+	struct mtk_imgsys_video_device *vdev;
+	int i;
+
+	for (i = 0; i < imgsys_pipe->desc->total_queues; ++i) {
+		vdev = &imgsys_pipe->nodes[i];
+		if (vdev->desc->supports_ctrls)
+			v4l2_ctrl_handler_free(&vdev->ctrl_handler);
+	}
+}
+
+static int mtk_imgsys_pipe_v4l2_register(struct mtk_imgsys_pipe *pipe,
+					 struct media_device *media_dev,
+					 struct v4l2_device *v4l2_dev)
+{
+	int i, ret;
+
+	ret = mtk_imgsys_pipe_v4l2_ctrl_init(pipe);
+	if (ret) {
+		dev_info(pipe->imgsys_dev->dev,
+			 "%s: failed(%d) to initialize ctrls\n",
+			 pipe->desc->name, ret);
+
+		return ret;
+	}
+
+	pipe->streaming = 0;
+
+	/* Initialize subdev media entity */
+	pipe->subdev_pads = devm_kcalloc(pipe->imgsys_dev->dev,
+					 pipe->desc->total_queues,
+					 sizeof(*pipe->subdev_pads),
+					 GFP_KERNEL);
+	if (!pipe->subdev_pads) {
+		dev_info(pipe->imgsys_dev->dev,
+			 "failed to alloc pipe->subdev_pads (%d)\n", ret);
+		ret = -ENOMEM;
+		goto err_release_ctrl;
+	}
+	ret = media_entity_pads_init(&pipe->subdev.entity,
+				     pipe->desc->total_queues,
+				     pipe->subdev_pads);
+	if (ret) {
+		dev_info(pipe->imgsys_dev->dev,
+			 "failed initialize subdev media entity (%d)\n", ret);
+		goto err_free_subdev_pads;
+	}
+
+	/* Initialize subdev */
+	v4l2_subdev_init(&pipe->subdev, &mtk_imgsys_subdev_ops);
+
+	pipe->subdev.entity.function =
+		MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
+	pipe->subdev.entity.ops = &mtk_imgsys_media_ops;
+	pipe->subdev.flags =
+		V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
+	pipe->subdev.ctrl_handler = NULL;
+
+	for (i = 0; i < pipe->desc->total_queues; i++)
+		pipe->subdev_pads[pipe->nodes[i].desc->id].flags =
+			V4L2_TYPE_IS_OUTPUT(pipe->nodes[i].desc->buf_type) ?
+			MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
+
+	snprintf(pipe->subdev.name, sizeof(pipe->subdev.name),
+		 "%s", pipe->desc->name);
+	v4l2_set_subdevdata(&pipe->subdev, pipe);
+
+	ret = v4l2_device_register_subdev(&pipe->imgsys_dev->v4l2_dev,
+					  &pipe->subdev);
+	if (ret) {
+		dev_info(pipe->imgsys_dev->dev,
+			 "failed initialize subdev (%d)\n", ret);
+		goto err_media_entity_cleanup;
+	}
+
+	dev_dbg(pipe->imgsys_dev->dev,
+		"register subdev: %s, ctrl_handler %p\n",
+		 pipe->subdev.name, pipe->subdev.ctrl_handler);
+
+	/* Create video nodes and links */
+	for (i = 0; i < pipe->desc->total_queues; i++) {
+		ret =
+			mtk_imgsys_video_device_v4l2_register(pipe,
+							      &pipe->nodes[i]);
+		if (ret)
+			goto err_unregister_subdev;
+	}
+
+	return 0;
+
+err_unregister_subdev:
+	v4l2_device_unregister_subdev(&pipe->subdev);
+
+err_media_entity_cleanup:
+	media_entity_cleanup(&pipe->subdev.entity);
+
+err_free_subdev_pads:
+	devm_kfree(pipe->imgsys_dev->dev, pipe->subdev_pads);
+
+err_release_ctrl:
+	mtk_imgsys_pipe_v4l2_ctrl_release(pipe);
+
+	return ret;
+}
+
+static void mtk_imgsys_pipe_v4l2_unregister(struct mtk_imgsys_pipe *pipe)
+{
+	unsigned int i;
+
+	for (i = 0; i < pipe->desc->total_queues; i++) {
+		video_unregister_device(&pipe->nodes[i].vdev);
+		vb2_queue_release(&pipe->nodes[i].dev_q.vbq);
+		media_entity_cleanup(&pipe->nodes[i].vdev.entity);
+		mutex_destroy(&pipe->nodes[i].dev_q.lock);
+	}
+
+	v4l2_device_unregister_subdev(&pipe->subdev);
+	media_entity_cleanup(&pipe->subdev.entity);
+	mtk_imgsys_pipe_v4l2_ctrl_release(pipe);
+}
+
+static void mtk_imgsys_dev_media_unregister(struct mtk_imgsys_dev *imgsys_dev)
+{
+	media_device_unregister(&imgsys_dev->mdev);
+	media_device_cleanup(&imgsys_dev->mdev);
+}
+
+static int mtk_imgsys_dev_v4l2_init(struct mtk_imgsys_dev *imgsys_dev)
+{
+	struct media_device *media_dev = &imgsys_dev->mdev;
+	struct v4l2_device *v4l2_dev = &imgsys_dev->v4l2_dev;
+	int ret;
+
+	ret = mtk_imgsys_dev_media_register(imgsys_dev->dev, media_dev);
+	if (ret) {
+		dev_info(imgsys_dev->dev,
+			 "%s: media device register failed(%d)\n",
+			 __func__, ret);
+		return ret;
+	}
+
+	v4l2_dev->mdev = media_dev;
+	v4l2_dev->ctrl_handler = NULL;
+
+	ret = v4l2_device_register(imgsys_dev->dev, v4l2_dev);
+	if (ret) {
+		dev_info(imgsys_dev->dev,
+			 "%s: v4l2 device register failed(%d)\n",
+			 __func__, ret);
+		goto err_release_media_device;
+	}
+
+	ret = mtk_imgsys_pipe_init(imgsys_dev,
+				   &imgsys_dev->imgsys_pipe,
+				   imgsys_dev->cust_pipes);
+	if (ret) {
+		dev_info(imgsys_dev->dev,
+			 "%s: init failed(%d)\n",
+			 imgsys_dev->imgsys_pipe.desc->name, ret);
+		goto err_release_pipe;
+	}
+
+	ret = mtk_imgsys_pipe_v4l2_register(&imgsys_dev->imgsys_pipe, &imgsys_dev->mdev,
+					    &imgsys_dev->v4l2_dev);
+	if (ret) {
+		dev_info(imgsys_dev->dev,
+			 "%s: failed(%d) to create V4L2 devices\n",
+			 imgsys_dev->imgsys_pipe.desc->name, ret);
+		goto err_register_pipe;
+	}
+
+	ret = v4l2_device_register_subdev_nodes(&imgsys_dev->v4l2_dev);
+	if (ret) {
+		dev_info(imgsys_dev->dev,
+			 "failed to register subdevs (%d)\n", ret);
+		goto err_register_pipe;
+	}
+
+	return 0;
+
+err_register_pipe:
+	mtk_imgsys_pipe_v4l2_unregister(&imgsys_dev->imgsys_pipe);
+err_release_pipe:
+	mtk_imgsys_pipe_release(&imgsys_dev->imgsys_pipe);
+
+	v4l2_device_unregister(v4l2_dev);
+
+err_release_media_device:
+	mtk_imgsys_dev_media_unregister(imgsys_dev);
+
+	return ret;
+}
+
+static void mtk_imgsys_dev_v4l2_release(struct mtk_imgsys_dev *imgsys_dev)
+{
+	mtk_imgsys_pipe_v4l2_unregister(&imgsys_dev->imgsys_pipe);
+	mtk_imgsys_pipe_release(&imgsys_dev->imgsys_pipe);
+	v4l2_device_unregister(&imgsys_dev->v4l2_dev);
+	mtk_imgsys_dev_media_unregister(imgsys_dev);
+}
+
+static int mtk_imgsys_of_rproc(struct mtk_imgsys_dev *imgsys,
+			       struct platform_device *pdev)
+{
+	struct device *dev = imgsys->dev;
+
+	imgsys->scp = scp_get(pdev);
+	if (!imgsys->scp) {
+		dev_err(dev, "failed to get scp device\n");
+		return -ENODEV;
+	}
+
+	imgsys->rproc_handle = scp_get_rproc(imgsys->scp);
+	dev_dbg(dev, "imgsys rproc_phandle: 0x%pK\n", imgsys->rproc_handle);
+	imgsys->smem_dev = scp_get_device(imgsys->scp);
+
+	return 0;
+}
+
+static int mtk_imgsys_probe(struct platform_device *pdev)
+{
+	struct mtk_imgsys_dev *imgsys_dev;
+	struct device **larb_devs;
+	struct device_link *link;
+	const struct cust_data *data;
+	struct resource *res;
+	int larbs_num, i;
+	int ret;
+
+	imgsys_dev = devm_kzalloc(&pdev->dev, sizeof(*imgsys_dev), GFP_KERNEL);
+	if (!imgsys_dev)
+		return -ENOMEM;
+
+	data = of_device_get_match_data(&pdev->dev);
+
+	init_imgsys_pipeline(data);
+
+	imgsys_dev->cust_pipes = data->pipe_settings;
+	imgsys_dev->dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "Failed to get memory resource\n");
+		return -ENODEV;
+	}
+	imgsys_dev->imgsys_resource = res;
+
+	dev_set_drvdata(&pdev->dev, imgsys_dev);
+
+	imgsys_dev->num_mods = data->mod_num;
+
+	/* Get Clocks */
+	imgsys_dev->clks = data->clks;
+	imgsys_dev->num_clks = data->clk_num;
+	ret = devm_clk_bulk_get(&pdev->dev, imgsys_dev->num_clks,
+				imgsys_dev->clks);
+	if (ret)
+		dev_info(&pdev->dev, "Failed to get clks:%d\n", ret);
+
+	/* DMA configuration */
+	if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(34)))
+		dev_info(&pdev->dev, "%s:No DMA available\n", __func__);
+
+	if (!pdev->dev.dma_parms) {
+		pdev->dev.dma_parms =
+			devm_kzalloc(imgsys_dev->dev, sizeof(*pdev->dev.dma_parms), GFP_KERNEL);
+	}
+	if (pdev->dev.dma_parms)
+		dma_set_max_seg_size(imgsys_dev->dev, UINT_MAX);
+
+	/* Get LARB Information */
+	larbs_num = of_count_phandle_with_args(pdev->dev.of_node,
+					       "mediatek,larbs", NULL);
+	dev_dbg(imgsys_dev->dev, "%d larbs to be added", larbs_num);
+	larb_devs = devm_kzalloc(&pdev->dev, sizeof(larb_devs) * larbs_num, GFP_KERNEL);
+	if (!larb_devs) {
+		ret = -ENOMEM;
+		goto err_free_dev_alloc;
+	}
+	for (i = 0; i < larbs_num; i++) {
+		struct device_node *larb_node;
+		struct platform_device *larb_pdev;
+
+		larb_node = of_parse_phandle(pdev->dev.of_node, "mediatek,larbs", i);
+		if (!larb_node) {
+			dev_info(imgsys_dev->dev,
+				 "%d larb node not found\n", i);
+			continue;
+		}
+
+		larb_pdev = of_find_device_by_node(larb_node);
+		if (!larb_pdev) {
+			of_node_put(larb_node);
+			dev_info(imgsys_dev->dev,
+				 "%d larb device not found\n", i);
+			continue;
+		}
+		of_node_put(larb_node);
+
+		link = device_link_add(&pdev->dev, &larb_pdev->dev,
+				       DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
+		if (!link)
+			dev_info(imgsys_dev->dev, "unable to link SMI LARB idx %d\n", i);
+
+		larb_devs[i] = &larb_pdev->dev;
+	}
+	imgsys_dev->larbs = larb_devs;
+	imgsys_dev->num_larbs = larbs_num;
+
+	/* Register rproc device */
+	if (mtk_imgsys_of_rproc(imgsys_dev, pdev)) {
+		ret = -EFAULT;
+		goto err_free_larb_alloc;
+	}
+
+	/* Imgsys device initialization */
+	ret = mtk_imgsys_dev_v4l2_init(imgsys_dev);
+	if (ret) {
+		dev_info(&pdev->dev, "v4l2 init failed(%d)\n", ret);
+
+		goto err_free_larb_alloc;
+	}
+
+	/* Enable power*/
+	pm_runtime_set_autosuspend_delay(&pdev->dev, IMGSYS_SUSPEND_TIME);
+	pm_runtime_use_autosuspend(&pdev->dev);
+	pm_runtime_enable(&pdev->dev);
+
+	return 0;
+
+err_free_larb_alloc:
+	devm_kfree(&pdev->dev, imgsys_dev->larbs);
+err_free_dev_alloc:
+	devm_kfree(&pdev->dev, imgsys_dev);
+	return ret;
+}
+
+static void mtk_imgsys_remove(struct platform_device *pdev)
+{
+	struct mtk_imgsys_dev *imgsys_dev = dev_get_drvdata(&pdev->dev);
+
+	pm_runtime_disable(&pdev->dev);
+	mtk_imgsys_dev_v4l2_release(imgsys_dev);
+	devm_kfree(&pdev->dev, imgsys_dev->larbs);
+	devm_kfree(&pdev->dev, imgsys_dev);
+}
+
+static int __maybe_unused mtk_imgsys_pm_suspend(struct device *dev)
+{
+	int ret;
+
+	if (pm_runtime_suspended(dev)) {
+		dev_info(dev, "%s: pm_runtime_suspended is true, no action\n",
+			 __func__);
+		return 0;
+	}
+
+	ret = pm_runtime_force_suspend(dev);
+	if (ret) {
+		dev_info(dev, "%s: pm_runtime_force_suspend failed:(%d)\n",
+			 __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __maybe_unused mtk_imgsys_pm_resume(struct device *dev)
+{
+	int ret;
+
+	if (pm_runtime_suspended(dev)) {
+		dev_info(dev, "%s: pm_runtime_suspended is true, no action\n",
+			 __func__);
+		return 0;
+	}
+
+	ret = pm_runtime_force_resume(dev);
+	if (ret) {
+		dev_info(dev, "%s: pm_runtime_force_resume failed:(%d)\n",
+			 __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __maybe_unused mtk_imgsys_runtime_suspend(struct device *dev)
+{
+	struct mtk_imgsys_dev *imgsys_dev = dev_get_drvdata(dev);
+
+	clk_bulk_disable_unprepare(imgsys_dev->num_clks,
+				   imgsys_dev->clks);
+
+	return 0;
+}
+
+static int __maybe_unused mtk_imgsys_runtime_resume(struct device *dev)
+{
+	struct mtk_imgsys_dev *imgsys_dev = dev_get_drvdata(dev);
+	int ret;
+
+	ret = clk_bulk_prepare_enable(imgsys_dev->num_clks,
+				      imgsys_dev->clks);
+	if (ret) {
+		dev_info(imgsys_dev->dev,
+			 "failed to enable dip clks(%d)\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct dev_pm_ops mtk_imgsys_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(mtk_imgsys_pm_suspend, mtk_imgsys_pm_resume)
+	SET_RUNTIME_PM_OPS(mtk_imgsys_runtime_suspend,
+			   mtk_imgsys_runtime_resume, NULL)
+};
+
+static struct clk_bulk_data imgsys_isp7_clks[] = {
+	{ .id = "IMGSYS_CG_IMG_TRAW0" },
+	{ .id = "IMGSYS_CG_IMG_TRAW1" },
+	{ .id = "IMGSYS_CG_IMG_VCORE_GALS" },
+	{ .id = "IMGSYS_CG_IMG_DIP0" },
+	{ .id = "IMGSYS_CG_IMG_WPE0" },
+	{ .id = "IMGSYS_CG_IMG_WPE1" },
+	{ .id = "IMGSYS_CG_IMG_WPE2" },
+	{ .id = "IMGSYS_CG_IMG_GALS" },
+	{ .id = "DIP_TOP_DIP_TOP" },
+	{ .id = "DIP_NR_DIP_NR" },
+	{ .id = "WPE1_CG_DIP1_WPE" },
+	{ .id = "WPE2_CG_DIP1_WPE" },
+	{ .id = "WPE3_CG_DIP1_WPE" },
+	{ .id = "ME_CG_IPE" },
+	{ .id = "ME_CG_IPE_TOP" },
+	{ .id = "ME_CG" },
+	{ .id = "ME_CG_LARB12" },
+};
+
+static const struct cust_data imgsys_data[] = {
+	[0] = {
+		.clks = imgsys_isp7_clks,
+		.clk_num = ARRAY_SIZE(imgsys_isp7_clks),
+		.module_pipes = module_pipe_isp7,
+		.mod_num = ARRAY_SIZE(module_pipe_isp7),
+		.pipe_settings = pipe_settings_isp7,
+		.pipe_num = ARRAY_SIZE(pipe_settings_isp7),
+	},
+};
+
+static const struct of_device_id mtk_imgsys_of_match[] = {
+	{ .compatible = "mediatek,mt8188-isp-imgsys", .data = (void *)&imgsys_data},
+	{}
+};
+MODULE_DEVICE_TABLE(of, mtk_imgsys_of_match);
+
+static struct platform_driver mtk_imgsys_driver = {
+	.probe   = mtk_imgsys_probe,
+	.remove  = mtk_imgsys_remove,
+	.driver  = {
+		.name = "mtk-imgsys",
+		.owner	= THIS_MODULE,
+		.pm = &mtk_imgsys_pm_ops,
+		.of_match_table = of_match_ptr(mtk_imgsys_of_match),
+	}
+};
+
+module_platform_driver(mtk_imgsys_driver);
+
+MODULE_AUTHOR("Frederic Chen <frederic.chen at mediatek.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MediaTek IMGSYS driver");
+
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-vnode_id.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-vnode_id.h
new file mode 100644
index 000000000000..4a418099d7c0
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-vnode_id.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *
+ */
+#ifndef _MTK_IMGSYS_VNODE_ID_H_
+#define _MTK_IMGSYS_VNODE_ID_H_
+
+/**
+ * enum imgsys_video_nodes_id - Enumeration of video node IDs for image system
+ *
+ * This enumeration defines the unique identifiers for various video nodes
+ * used in the image processing system. Each ID corresponds to a specific
+ * video node that can be utilized for different functionalities.
+ */
+enum imgsys_video_nodes_id {
+	/* IMGSYS_MODULE_TRAW */
+	MTK_IMGSYS_VIDEO_NODE_ID_TIMGI_OUT = 0,
+	MTK_IMGSYS_VIDEO_NODE_ID_METAI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_PDC_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_TYUVO_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_TYUV2O_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_TYUV3O_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_TYUV4O_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_TYUV5O_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_FEO_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_TIMGO_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_IMGSTATO_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_XTMEO_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_XTFDO_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_XTADLDBGO_CAPTURE,
+	/* IMGSYS_MODULE_DIP */
+	MTK_IMGSYS_VIDEO_NODE_ID_IMGI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_VIPI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_REC_DSI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_REC_DPI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_CNR_BLURMAPI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_LFEI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_RFEI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_TNRSI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_TNRWI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_TNRMI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_TNRCI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_TNRLI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_TNRVBI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_IMG2O_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_IMG3O_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_IMG4O_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_FMO_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_TNRSO_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_TNRWO_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_TNRMO_CAPTURE,
+	/* IMGSYS_MODULE_PQDIP */
+	MTK_IMGSYS_VIDEO_NODE_ID_PIMGI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_WROT_A_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_WROT_B_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_TCCSO_A_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_TCCSO_B_CAPTURE,
+	/* IMGSYS_MODULE_ME */
+	MTK_IMGSYS_VIDEO_NODE_ID_MEL0IMG0_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEL0IMG1_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEL1IMG0_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEL1IMG1_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEIMGSTATS_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEL0RMV_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEL1RMV_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEL0FMB_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEL1FMB_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEMIL_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEMMGMIL_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEL0WMV_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEL1WMV_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_MECONF_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEWMAP_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEFMV_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEFST_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_MELMI_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEL0WFMB_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_MEL1WFMB_CAPTURE,
+	/* IMGSYS_MODULE_WPE */
+	MTK_IMGSYS_VIDEO_NODE_ID_WWPEI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_WVECI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_WPSP_COEFI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_WWPEO_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_WMSKO_CAPTURE,
+	/* IMGSYS_MODULE_WPE_TNR */
+	MTK_IMGSYS_VIDEO_NODE_ID_WTWPEI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_WTVECI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_WTPSP_COEFI_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_WTWPEO_CAPTURE,
+	MTK_IMGSYS_VIDEO_NODE_ID_WTMSKO_CAPTURE,
+	/* other module video nodes to be added */
+	MTK_IMGSYS_VIDEO_NODE_ID_TUNING_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_CTRLMETA_OUT,
+	MTK_IMGSYS_VIDEO_NODE_ID_TOTAL_NUM,
+};
+
+#endif
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys_v4l2_vnode.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys_v4l2_vnode.h
new file mode 100644
index 000000000000..5a6f3220ab6b
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys_v4l2_vnode.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *
+ */
+#ifndef _MTK_IMGSYS_V4L2_VNODE_H_
+#define _MTK_IMGSYS_V4L2_VNODE_H_
+
+#include "mtk_imgsys-of.h"
+#include "mtk_imgsys-dev.h"
+#include "mtk_imgsys-formats.h"
+#include "modules/mtk_dip_v4l2_vnode.h"
+#include "modules/mtk_traw_v4l2_vnode.h"
+#include "modules/mtk_pqdip_v4l2_vnode.h"
+#include "modules/mtk_wpe_v4l2_vnode.h"
+#include "modules/mtk_me_v4l2_vnode.h"
+
+/**
+ * enum mtk_imgsys_module_id - Enumeration of image system module IDs
+ * @IMGSYS_MODULE_TRAW: Module for TRAW processing.
+ * @IMGSYS_MODULE_DIP: Module for DIP processing.
+ * @IMGSYS_MODULE_PQDIP: Module for PQDIP processing.
+ * @IMGSYS_MODULE_ME: Module for Motion Estimation (ME).
+ * @IMGSYS_MODULE_WPE: Module for WPE processing.
+ * @IMGSYS_MODULE_MAIN: Main module for image system.
+ * @IMGSYS_MODULE_NUM: Total number of image system modules.
+ */
+enum mtk_imgsys_module_id {
+	IMGSYS_MODULE_TRAW = 0,
+	IMGSYS_MODULE_DIP,
+	IMGSYS_MODULE_PQDIP,
+	IMGSYS_MODULE_ME,
+	IMGSYS_MODULE_WPE,
+	IMGSYS_MODULE_MAIN,
+	IMGSYS_MODULE_NUM,
+};
+
+/**
+ * struct mtk_imgsys_mod_pipe_desc - Pipe description for image system modules
+ * @vnode_desc: Pointer to the node descriptor array
+ * @node_num: Number of nodes in the descriptor array
+ *
+ * This structure defines the pipe description for each module in the MediaTek
+ * image system. It includes a pointer to the node descriptor array and the
+ * number of nodes in that array.
+ */
+static const struct mtk_imgsys_mod_pipe_desc module_pipe_isp7[] = {
+	[IMGSYS_MODULE_TRAW] = {
+		.vnode_desc = traw_setting,
+		.node_num = ARRAY_SIZE(traw_setting),
+	},
+	[IMGSYS_MODULE_DIP] = {
+		.vnode_desc = dip_setting,
+		.node_num = ARRAY_SIZE(dip_setting),
+	},
+	[IMGSYS_MODULE_PQDIP] = {
+		.vnode_desc = pqdip_setting,
+		.node_num = ARRAY_SIZE(pqdip_setting),
+	},
+	[IMGSYS_MODULE_ME] = {
+		.vnode_desc = me_setting,
+		.node_num = ARRAY_SIZE(me_setting),
+	},
+	[IMGSYS_MODULE_WPE] = {
+		.vnode_desc = wpe_setting,
+		.node_num = ARRAY_SIZE(wpe_setting),
+	},
+	[IMGSYS_MODULE_MAIN] = {
+		.vnode_desc = NULL,
+		.node_num = 0,
+	}
+};
+
+/* Tuning formats for MediaTek Image System */
+static const struct mtk_imgsys_dev_format tuning_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_metai,
+	},
+};
+
+/* Control metadata formats for MediaTek Image System */
+static const struct mtk_imgsys_dev_format ctrlmeta_fmts[] = {
+	{
+		.fmt = &mtk_imgsys_format_ctrlmeta,
+	},
+};
+
+/**
+ * queues_setting - Array to store video device descriptions for each module
+ * and meta in ImgSys
+ */
+static struct mtk_imgsys_video_device_desc
+queues_setting[MTK_IMGSYS_VIDEO_NODE_ID_TOTAL_NUM] = {
+	[MTK_IMGSYS_VIDEO_NODE_ID_TUNING_OUT] = {
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_TUNING_OUT,
+		.name = "Tuning",
+		.cap = V4L2_CAP_META_OUTPUT | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_META_OUTPUT,
+		.smem_alloc = 1,
+		.flags = 0,
+		.fmts = tuning_fmts,
+		.num_fmts = ARRAY_SIZE(tuning_fmts),
+		.dma_port = 0,
+		.frmsizeenum = &dip_in_frmsizeenum,
+		.description = "Tuning data",
+	},
+	[MTK_IMGSYS_VIDEO_NODE_ID_CTRLMETA_OUT] = {
+		.id = MTK_IMGSYS_VIDEO_NODE_ID_CTRLMETA_OUT,
+		.name = "CtrlMeta",
+		.cap = V4L2_CAP_META_OUTPUT | V4L2_CAP_STREAMING,
+		.buf_type = V4L2_BUF_TYPE_META_OUTPUT,
+		.smem_alloc = 1,
+		.flags = 0,
+		.fmts = ctrlmeta_fmts,
+		.num_fmts = ARRAY_SIZE(ctrlmeta_fmts),
+		.dma_port = 0,
+		.frmsizeenum = &dip_in_frmsizeenum,
+		.description = "Control meta data for flow control",
+	},
+};
+
+/**
+ * pipe_settings_isp7 - Array to store pipeline configurations for ISP7 in ImgSys
+ */
+static const struct mtk_imgsys_pipe_desc pipe_settings_isp7[] = {
+	{
+		.name = MTK_IMGSYS_MEDIA_MODEL_NAME,
+		.id = 0,
+		.queue_descs = queues_setting,
+		.total_queues = ARRAY_SIZE(queues_setting),
+	},
+};
+#endif
-- 
2.45.2



From olivia.wen at mediatek.com  Sat May 24 04:49:59 2025
From: olivia.wen at mediatek.com (Olivia Wen)
Date: Sat, 24 May 2025 19:49:59 +0800
Subject: [PATCH v1 07/10] media: mediatek: isp: Add CMDQ support for ImgSys driver
In-Reply-To: <20250524115144.3832748-1-olivia.wen@mediatek.com>
References: <20250524115144.3832748-1-olivia.wen@mediatek.com>
Message-ID: <20250524115144.3832748-8-olivia.wen@mediatek.com>

The ImgSys driver is implemented as a series of patches, with this patch
focusing on CMDQ (Command Queue) support for the MediaTek Image System
driver. CMDQ is essential for managing and executing hardware commands
efficiently, ensuring smooth operation of image processing tasks within
the ImgSys architecture.

Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
---
 .../mediatek/isp/isp_7x/imgsys/Makefile       |   1 +
 .../isp/isp_7x/imgsys/mtk_imgsys-cmdq-plat.h  | 502 +++++++++++++
 .../isp/isp_7x/imgsys/mtk_imgsys-cmdq.c       | 690 ++++++++++++++++++
 .../isp/isp_7x/imgsys/mtk_imgsys-cmdq.h       |  29 +
 .../isp_7x/imgsys/mtk_imgsys-module_common.h  |  20 +
 .../isp/isp_7x/imgsys/mtk_imgsys-sys.c        |   5 +
 6 files changed, 1247 insertions(+)
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-cmdq-plat.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-cmdq.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-cmdq.h

diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
index 26c8c1d39750..c0f0f3a0c38a 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
@@ -2,6 +2,7 @@
 #
 
 mtk_imgsys_util-objs := \
+mtk_imgsys-cmdq.o \
 mtk_imgsys-module_main.o \
 mtk_imgsys-of.o \
 mtk_imgsys-formats.o \
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-cmdq-plat.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-cmdq-plat.h
new file mode 100644
index 000000000000..801a12e70bac
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-cmdq-plat.h
@@ -0,0 +1,502 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Daniel Huang <daniel.huang at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_IMGSYS_CMDQ_PLAT_H_
+#define _MTK_IMGSYS_CMDQ_PLAT_H_
+
+#include "mtk_imgsys-cmdq.h"
+
+/* Maximum number of frame blocks for GCE recording */
+#define GCE_REC_MAX_FRAME_BLOCK	40
+
+/* Maximum number of tile blocks for GCE recording */
+#define GCE_REC_MAX_TILE_BLOCK	40
+
+/* Maximum number of label counts for GCE recording */
+#define GCE_REC_MAX_LABEL_COUNT	2048
+
+/* Maximum number of image system engines */
+#define IMGSYS_ENG_MAX 10
+
+/* Start address of the image system register */
+#define IMGSYS_REG_START 0x15000000
+
+/* End address of the image system register */
+#define IMGSYS_REG_END 0x1570FFFF
+
+/* Number of normal camera's thread */
+#define IMGSYS_NOR_THD 10
+
+/* Define the constants for buffer validation */
+#define HEADER_CODE	0x5A5A5A5A
+#define CHECK_PRE	0x55AA55AA
+#define CHECK_POST	0xAA55AA55
+#define FOOTER_CODE	0xA5A5A5A5
+
+/* Enumeration for Image System (IMGSYS) events */
+enum mtk_imgsys_event {
+	/* HW event */
+	/* TRAW frame done events */
+	IMGSYS_EVENT_TRAW0_CQ_THR_DONE_0 = 0,
+	IMGSYS_EVENT_TRAW0_CQ_THR_DONE_1,
+	IMGSYS_EVENT_TRAW0_CQ_THR_DONE_2,
+	IMGSYS_EVENT_TRAW0_CQ_THR_DONE_3,
+	IMGSYS_EVENT_TRAW0_CQ_THR_DONE_4,
+	IMGSYS_EVENT_TRAW0_CQ_THR_DONE_5,
+	IMGSYS_EVENT_TRAW0_CQ_THR_DONE_6,
+	IMGSYS_EVENT_TRAW0_CQ_THR_DONE_7,
+	IMGSYS_EVENT_TRAW0_CQ_THR_DONE_8,
+	IMGSYS_EVENT_TRAW0_CQ_THR_DONE_9,
+	/* LTRAW frame done events */
+	IMGSYS_EVENT_TRAW1_CQ_THR_DONE_0,
+	IMGSYS_EVENT_TRAW1_CQ_THR_DONE_1,
+	IMGSYS_EVENT_TRAW1_CQ_THR_DONE_2,
+	IMGSYS_EVENT_TRAW1_CQ_THR_DONE_3,
+	IMGSYS_EVENT_TRAW1_CQ_THR_DONE_4,
+	IMGSYS_EVENT_TRAW1_CQ_THR_DONE_5,
+	IMGSYS_EVENT_TRAW1_CQ_THR_DONE_6,
+	IMGSYS_EVENT_TRAW1_CQ_THR_DONE_7,
+	IMGSYS_EVENT_TRAW1_CQ_THR_DONE_8,
+	IMGSYS_EVENT_TRAW1_CQ_THR_DONE_9,
+	/* XTRAW frame done events */
+	IMGSYS_EVENT_XTRAW_CQ_THR_DONE_0,
+	IMGSYS_EVENT_XTRAW_CQ_THR_DONE_1,
+	IMGSYS_EVENT_XTRAW_CQ_THR_DONE_2,
+	IMGSYS_EVENT_XTRAW_CQ_THR_DONE_3,
+	IMGSYS_EVENT_XTRAW_CQ_THR_DONE_4,
+	IMGSYS_EVENT_XTRAW_CQ_THR_DONE_5,
+	IMGSYS_EVENT_XTRAW_CQ_THR_DONE_6,
+	IMGSYS_EVENT_XTRAW_CQ_THR_DONE_7,
+	IMGSYS_EVENT_XTRAW_CQ_THR_DONE_8,
+	IMGSYS_EVENT_XTRAW_CQ_THR_DONE_9,
+	/* DIP frame done events */
+	IMGSYS_EVENT_DIP_CQ_THR_DONE_0,
+	IMGSYS_EVENT_DIP_CQ_THR_DONE_1,
+	IMGSYS_EVENT_DIP_CQ_THR_DONE_2,
+	IMGSYS_EVENT_DIP_CQ_THR_DONE_3,
+	IMGSYS_EVENT_DIP_CQ_THR_DONE_4,
+	IMGSYS_EVENT_DIP_CQ_THR_DONE_5,
+	IMGSYS_EVENT_DIP_CQ_THR_DONE_6,
+	IMGSYS_EVENT_DIP_CQ_THR_DONE_7,
+	IMGSYS_EVENT_DIP_CQ_THR_DONE_8,
+	IMGSYS_EVENT_DIP_CQ_THR_DONE_9,
+	/* PQ_DIP_A frame done events */
+	IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_0,
+	IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_1,
+	IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_2,
+	IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_3,
+	IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_4,
+	IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_5,
+	IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_6,
+	IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_7,
+	IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_8,
+	IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_9,
+	/* PQ_DIP_B frame done events */
+	IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_0,
+	IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_1,
+	IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_2,
+	IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_3,
+	IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_4,
+	IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_5,
+	IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_6,
+	IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_7,
+	IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_8,
+	IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_9,
+	/* WPE_EIS frame done events */
+	IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_0,
+	IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_1,
+	IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_2,
+	IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_3,
+	IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_4,
+	IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_5,
+	IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_6,
+	IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_7,
+	IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_8,
+	IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_9,
+	/* WPE_TNR frame done events */
+	IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_0,
+	IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_1,
+	IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_2,
+	IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_3,
+	IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_4,
+	IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_5,
+	IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_6,
+	IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_7,
+	IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_8,
+	IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_9,
+	/* WPE_LITE frame done events */
+	IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_0,
+	IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_1,
+	IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_2,
+	IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_3,
+	IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_4,
+	IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_5,
+	IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_6,
+	IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_7,
+	IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_8,
+	IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_9,
+	/* ME done events */
+	IMGSYS_EVENT_IMGSYS_IPE_ME_DONE,
+	/* SW events */
+	IMGSYS_EVENT_SYNC_TOKEN_START,
+	IMGSYS_EVENT_SYNC_TOKEN_WPE_EIS = IMGSYS_EVENT_SYNC_TOKEN_START,
+	IMGSYS_EVENT_SYNC_TOKEN_WPE_TNR,
+	IMGSYS_EVENT_SYNC_TOKEN_WPE_LITE,
+	IMGSYS_EVENT_SYNC_TOKEN_TRAW,
+	IMGSYS_EVENT_SYNC_TOKEN_LTRAW,
+	IMGSYS_EVENT_SYNC_TOKEN_XTRAW,
+	IMGSYS_EVENT_SYNC_TOKEN_DIP,
+	IMGSYS_EVENT_SYNC_TOKEN_PQDIP_A,
+	IMGSYS_EVENT_SYNC_TOKEN_PQDIP_B,
+	IMGSYS_EVENT_SYNC_TOKEN_IPESYS_ME,
+	IMGSYS_EVENT_SYNC_TOKEN_APUSYS_APU,
+	IMGSYS_EVENT_SYNC_TOKEN_VSS_TRAW,
+	IMGSYS_EVENT_SYNC_TOKEN_VSS_LTRAW,
+	IMGSYS_EVENT_SYNC_TOKEN_VSS_XTRAW,
+	IMGSYS_EVENT_SYNC_TOKEN_VSS_DIP,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_START,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_1 = IMGSYS_EVENT_SYNC_TOKEN_POOL_START,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_2,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_3,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_4,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_5,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_6,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_7,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_8,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_9,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_10,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_11,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_12,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_13,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_14,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_15,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_16,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_17,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_18,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_19,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_20,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_21,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_22,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_23,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_24,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_25,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_26,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_27,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_28,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_29,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_30,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_31,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_32,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_33,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_34,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_35,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_36,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_37,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_38,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_39,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_40,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_41,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_42,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_43,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_44,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_45,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_46,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_47,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_48,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_49,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_50,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_51,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_52,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_53,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_54,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_55,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_56,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_57,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_58,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_59,
+	IMGSYS_EVENT_SYNC_TOKEN_POOL_60,
+	IMGSYS_EVENT_SYNC_TOKEN_END = IMGSYS_EVENT_SYNC_TOKEN_POOL_60,
+	IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_1,
+	IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_2,
+	IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_3,
+	IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_4,
+	IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_5,
+	IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_6,
+	IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_7,
+	IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_8,
+	IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_9,
+	IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_10,
+	IMGSYS_EVENT_SYNC_TOKEN_TZMP_ISP_WAIT,
+	IMGSYS_EVENT_SYNC_TOKEN_TZMP_ISP_SET,
+	IMGSYS_EVENT_MAX
+};
+
+/* Structure to represent an IMGSYS event */
+struct imgsys_event_table {
+	u16 event;
+	char dts_name[256];
+};
+
+/* Event table for Image System (IMGSYS) */
+static struct imgsys_event_table imgsys_event[] = {
+	/* TRAW frame done events */
+	{ IMGSYS_EVENT_TRAW0_CQ_THR_DONE_0, "traw_cq_thread0_frame_done"},
+	{ IMGSYS_EVENT_TRAW0_CQ_THR_DONE_1, "traw_cq_thread1_frame_done"},
+	{ IMGSYS_EVENT_TRAW0_CQ_THR_DONE_2, "traw_cq_thread2_frame_done"},
+	{ IMGSYS_EVENT_TRAW0_CQ_THR_DONE_3, "traw_cq_thread3_frame_done"},
+	{ IMGSYS_EVENT_TRAW0_CQ_THR_DONE_4, "traw_cq_thread4_frame_done"},
+	{ IMGSYS_EVENT_TRAW0_CQ_THR_DONE_5, "traw_cq_thread5_frame_done"},
+	{ IMGSYS_EVENT_TRAW0_CQ_THR_DONE_6, "traw_cq_thread6_frame_done"},
+	{ IMGSYS_EVENT_TRAW0_CQ_THR_DONE_7, "traw_cq_thread7_frame_done"},
+	{ IMGSYS_EVENT_TRAW0_CQ_THR_DONE_8, "traw_cq_thread8_frame_done"},
+	{ IMGSYS_EVENT_TRAW0_CQ_THR_DONE_9, "traw_cq_thread9_frame_done"},
+	/* LTRAW frame done events */
+	{ IMGSYS_EVENT_TRAW1_CQ_THR_DONE_0, "ltraw_cq_thread0_frame_done"},
+	{ IMGSYS_EVENT_TRAW1_CQ_THR_DONE_1, "ltraw_cq_thread1_frame_done"},
+	{ IMGSYS_EVENT_TRAW1_CQ_THR_DONE_2, "ltraw_cq_thread2_frame_done"},
+	{ IMGSYS_EVENT_TRAW1_CQ_THR_DONE_3, "ltraw_cq_thread3_frame_done"},
+	{ IMGSYS_EVENT_TRAW1_CQ_THR_DONE_4, "ltraw_cq_thread4_frame_done"},
+	{ IMGSYS_EVENT_TRAW1_CQ_THR_DONE_5, "ltraw_cq_thread5_frame_done"},
+	{ IMGSYS_EVENT_TRAW1_CQ_THR_DONE_6, "ltraw_cq_thread6_frame_done"},
+	{ IMGSYS_EVENT_TRAW1_CQ_THR_DONE_7, "ltraw_cq_thread7_frame_done"},
+	{ IMGSYS_EVENT_TRAW1_CQ_THR_DONE_8, "ltraw_cq_thread8_frame_done"},
+	{ IMGSYS_EVENT_TRAW1_CQ_THR_DONE_9, "ltraw_cq_thread9_frame_done"},
+	/* XTRAW frame done events */
+	{ IMGSYS_EVENT_XTRAW_CQ_THR_DONE_0, "xtraw_cq_thread0_frame_done"},
+	{ IMGSYS_EVENT_XTRAW_CQ_THR_DONE_1, "xtraw_cq_thread1_frame_done"},
+	{ IMGSYS_EVENT_XTRAW_CQ_THR_DONE_2, "xtraw_cq_thread2_frame_done"},
+	{ IMGSYS_EVENT_XTRAW_CQ_THR_DONE_3, "xtraw_cq_thread3_frame_done"},
+	{ IMGSYS_EVENT_XTRAW_CQ_THR_DONE_4, "xtraw_cq_thread4_frame_done"},
+	{ IMGSYS_EVENT_XTRAW_CQ_THR_DONE_5, "xtraw_cq_thread5_frame_done"},
+	{ IMGSYS_EVENT_XTRAW_CQ_THR_DONE_6, "xtraw_cq_thread6_frame_done"},
+	{ IMGSYS_EVENT_XTRAW_CQ_THR_DONE_7, "xtraw_cq_thread7_frame_done"},
+	{ IMGSYS_EVENT_XTRAW_CQ_THR_DONE_8, "xtraw_cq_thread8_frame_done"},
+	{ IMGSYS_EVENT_XTRAW_CQ_THR_DONE_9, "xtraw_cq_thread9_frame_done"},
+	/* DIP frame done events */
+	{ IMGSYS_EVENT_DIP_CQ_THR_DONE_0, "dip_cq_thread0_frame_done"},
+	{ IMGSYS_EVENT_DIP_CQ_THR_DONE_1, "dip_cq_thread1_frame_done"},
+	{ IMGSYS_EVENT_DIP_CQ_THR_DONE_2, "dip_cq_thread2_frame_done"},
+	{ IMGSYS_EVENT_DIP_CQ_THR_DONE_3, "dip_cq_thread3_frame_done"},
+	{ IMGSYS_EVENT_DIP_CQ_THR_DONE_4, "dip_cq_thread4_frame_done"},
+	{ IMGSYS_EVENT_DIP_CQ_THR_DONE_5, "dip_cq_thread5_frame_done"},
+	{ IMGSYS_EVENT_DIP_CQ_THR_DONE_6, "dip_cq_thread6_frame_done"},
+	{ IMGSYS_EVENT_DIP_CQ_THR_DONE_7, "dip_cq_thread7_frame_done"},
+	{ IMGSYS_EVENT_DIP_CQ_THR_DONE_8, "dip_cq_thread8_frame_done"},
+	{ IMGSYS_EVENT_DIP_CQ_THR_DONE_9, "dip_cq_thread9_frame_done"},
+	/* PQ_DIP_A frame done events */
+	{ IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_0, "pqa_cq_thread0_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_1, "pqa_cq_thread1_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_2, "pqa_cq_thread2_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_3, "pqa_cq_thread3_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_4, "pqa_cq_thread4_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_5, "pqa_cq_thread5_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_6, "pqa_cq_thread6_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_7, "pqa_cq_thread7_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_8, "pqa_cq_thread8_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_A_CQ_THR_DONE_9, "pqa_cq_thread9_frame_done"},
+	/* PQ_DIP_B frame done events */
+	{ IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_0, "pqb_cq_thread0_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_1, "pqb_cq_thread1_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_2, "pqb_cq_thread2_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_3, "pqb_cq_thread3_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_4, "pqb_cq_thread4_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_5, "pqb_cq_thread5_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_6, "pqb_cq_thread6_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_7, "pqb_cq_thread7_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_8, "pqb_cq_thread8_frame_done"},
+	{ IMGSYS_EVENT_PQDIP_B_CQ_THR_DONE_9, "pqb_cq_thread9_frame_done"},
+	/* WPE_EIS frame done events */
+	{ IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_0, "wpe_eis_cq_thread0_frame_done"},
+	{ IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_1, "wpe_eis_cq_thread1_frame_done"},
+	{ IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_2, "wpe_eis_cq_thread2_frame_done"},
+	{ IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_3, "wpe_eis_cq_thread3_frame_done"},
+	{ IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_4, "wpe_eis_cq_thread4_frame_done"},
+	{ IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_5, "wpe_eis_cq_thread5_frame_done"},
+	{ IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_6, "wpe_eis_cq_thread6_frame_done"},
+	{ IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_7, "wpe_eis_cq_thread7_frame_done"},
+	{ IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_8, "wpe_eis_cq_thread8_frame_done"},
+	{ IMGSYS_EVENT_WPE_EIS_CQ_THR_DONE_9, "wpe_eis_cq_thread9_frame_done"},
+	/* WPE_TNR frame done events */
+	{ IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_0, "wpe_tnr_cq_thread0_frame_done"},
+	{ IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_1, "wpe_tnr_cq_thread1_frame_done"},
+	{ IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_2, "wpe_tnr_cq_thread2_frame_done"},
+	{ IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_3, "wpe_tnr_cq_thread3_frame_done"},
+	{ IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_4, "wpe_tnr_cq_thread4_frame_done"},
+	{ IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_5, "wpe_tnr_cq_thread5_frame_done"},
+	{ IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_6, "wpe_tnr_cq_thread6_frame_done"},
+	{ IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_7, "wpe_tnr_cq_thread7_frame_done"},
+	{ IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_8, "wpe_tnr_cq_thread8_frame_done"},
+	{ IMGSYS_EVENT_WPE_TNR_CQ_THR_DONE_9, "wpe_tnr_cq_thread9_frame_done"},
+	/* WPE_LITE frame done events */
+	{ IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_0, "wpe_lite_cq_thread0_frame_done"},
+	{ IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_1, "wpe_lite_cq_thread1_frame_done"},
+	{ IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_2, "wpe_lite_cq_thread2_frame_done"},
+	{ IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_3, "wpe_lite_cq_thread3_frame_done"},
+	{ IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_4, "wpe_lite_cq_thread4_frame_done"},
+	{ IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_5, "wpe_lite_cq_thread5_frame_done"},
+	{ IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_6, "wpe_lite_cq_thread6_frame_done"},
+	{ IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_7, "wpe_lite_cq_thread7_frame_done"},
+	{ IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_8, "wpe_lite_cq_thread8_frame_done"},
+	{ IMGSYS_EVENT_WPE_LITE_CQ_THR_DONE_9, "wpe_lite_cq_thread9_frame_done"},
+	/* ME done events */
+	{ IMGSYS_EVENT_IMGSYS_IPE_ME_DONE, "me_done"},
+	/* SW events */
+	{ IMGSYS_EVENT_SYNC_TOKEN_WPE_EIS, "wpe_eis_sync_token"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_WPE_TNR, "wpe_tnr_sync_token"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_WPE_LITE, "wpe_lite_sync_token"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_TRAW, "traw_sync_token"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_LTRAW, "ltraw_sync_token"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_XTRAW, "xtraw_sync_token"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_DIP, "dip_sync_token"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_PQDIP_A, "pqdip_a_sync_token"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_PQDIP_B, "pqdip_b_sync_token"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_IPESYS_ME, "me_sync_token"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_APUSYS_APU, "apu_sync_token"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_VSS_TRAW, "vss_traw_sync_token"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_VSS_LTRAW, "vss_ltraw_sync_token"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_VSS_XTRAW, "vss_xtraw_sync_token"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_VSS_DIP, "vss_dip_sync_token"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_1, "sw_sync_token_pool_1"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_2, "sw_sync_token_pool_2"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_3, "sw_sync_token_pool_3"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_4, "sw_sync_token_pool_4"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_5, "sw_sync_token_pool_5"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_6, "sw_sync_token_pool_6"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_7, "sw_sync_token_pool_7"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_8, "sw_sync_token_pool_8"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_9, "sw_sync_token_pool_9"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_10, "sw_sync_token_pool_10"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_11, "sw_sync_token_pool_11"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_12, "sw_sync_token_pool_12"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_13, "sw_sync_token_pool_13"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_14, "sw_sync_token_pool_14"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_15, "sw_sync_token_pool_15"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_16, "sw_sync_token_pool_16"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_17, "sw_sync_token_pool_17"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_18, "sw_sync_token_pool_18"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_19, "sw_sync_token_pool_19"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_20, "sw_sync_token_pool_20"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_21, "sw_sync_token_pool_21"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_22, "sw_sync_token_pool_22"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_23, "sw_sync_token_pool_23"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_24, "sw_sync_token_pool_24"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_25, "sw_sync_token_pool_25"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_26, "sw_sync_token_pool_26"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_27, "sw_sync_token_pool_27"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_28, "sw_sync_token_pool_28"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_29, "sw_sync_token_pool_29"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_30, "sw_sync_token_pool_30"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_31, "sw_sync_token_pool_31"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_32, "sw_sync_token_pool_32"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_33, "sw_sync_token_pool_33"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_34, "sw_sync_token_pool_34"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_35, "sw_sync_token_pool_35"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_36, "sw_sync_token_pool_36"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_37, "sw_sync_token_pool_37"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_38, "sw_sync_token_pool_38"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_39, "sw_sync_token_pool_39"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_40, "sw_sync_token_pool_40"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_41, "sw_sync_token_pool_41"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_42, "sw_sync_token_pool_42"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_43, "sw_sync_token_pool_43"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_44, "sw_sync_token_pool_44"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_45, "sw_sync_token_pool_45"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_46, "sw_sync_token_pool_46"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_47, "sw_sync_token_pool_47"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_48, "sw_sync_token_pool_48"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_49, "sw_sync_token_pool_49"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_50, "sw_sync_token_pool_50"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_51, "sw_sync_token_pool_51"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_52, "sw_sync_token_pool_52"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_53, "sw_sync_token_pool_53"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_54, "sw_sync_token_pool_54"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_55, "sw_sync_token_pool_55"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_56, "sw_sync_token_pool_56"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_57, "sw_sync_token_pool_57"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_58, "sw_sync_token_pool_58"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_59, "sw_sync_token_pool_59"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_POOL_60, "sw_sync_token_pool_60"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_1, "sw_sync_token_camsys_pool_1"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_2, "sw_sync_token_camsys_pool_2"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_3, "sw_sync_token_camsys_pool_3"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_4, "sw_sync_token_camsys_pool_4"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_5, "sw_sync_token_camsys_pool_5"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_6, "sw_sync_token_camsys_pool_6"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_7, "sw_sync_token_camsys_pool_7"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_8, "sw_sync_token_camsys_pool_8"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_9, "sw_sync_token_camsys_pool_9"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_CAMSYS_POOL_10, "sw_sync_token_camsys_pool_10"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_TZMP_ISP_WAIT, "sw_sync_token_tzmp_isp_wait"},
+	{ IMGSYS_EVENT_SYNC_TOKEN_TZMP_ISP_SET, "sw_sync_token_tzmp_isp_set"},
+	{ IMGSYS_EVENT_MAX, "imgsys_event_max"},
+};
+
+/* Structure to record block information */
+struct block_record {
+	u32 label_min;	/* Minimum label value */
+	u32 label_max;	/* Maximum label value */
+	u32 label_count;	/* Count of labels */
+	u32 cmd_offset;	/* Offset of the command */
+	u32 cmd_length;	/* Length of the command */
+};
+
+/* Enumeration for GCE recording block types */
+enum gce_rec_block_enum {
+	GCE_REC_NONE_BLOCK = -1,	/* No block */
+	GCE_REC_FRAME_BLOCK = 0,	/* Frame block */
+	GCE_REC_TILE_BLOCK	/* Tile block */
+};
+
+/* Enumeration for GCE recording modes */
+enum gce_rec_mode_enum {
+	GCE_REC_APPEND_MODE = 0,	/* Append mode */
+	GCE_REC_REPLACE_MODE	/* Replace mode */
+};
+
+/**
+ *This structure is utilized by the SCP (Secondary Control Processor),
+ * which is another CPU in the system. It contains necessary information
+ * for managing software frames across different processing units.
+ */
+struct gce_recorder {
+	u32 header_code;	/* Header guard word */
+	u32 cmd_offset;	/* Command offset */
+	u32 check_pre;	/* Pre-check guard word */
+	u32 *p_output;	/* Output buffer pointer */
+	u32 check_post;	/* Post-check guard word */
+	u32 *p_buffer;	/* Buffer pointer */
+	u32 max_length;	/* Maximum length of the buffer */
+	u32 curr_length;	/* Current length of the buffer */
+
+	struct block_record frame_record[GCE_REC_MAX_FRAME_BLOCK]; /* Frame block records */
+	u32 frame_block;	/* Number of frame blocks */
+	u32 curr_frame;	/* Current frame block index */
+
+	struct block_record tile_record[GCE_REC_MAX_TILE_BLOCK];   /* Tile block records */
+	u32 tile_block;	/* Number of tile blocks */
+	u32 curr_tile;	/* Current tile block index */
+
+	enum gce_rec_block_enum curr_block;	/* Current block type */
+	enum gce_rec_mode_enum curr_mode;	/* Current recording mode */
+
+	u32 orig_index;	/* Original index */
+	u32 *p_orig_out;	/* Original output buffer pointer */
+	u32 curr_label;	/* Current label index */
+
+	enum gce_rec_block_enum label_block;	/* Current label block type */
+
+	u32 frame_label[GCE_REC_MAX_LABEL_COUNT];	/* Frame labels */
+	u32 frame_count;	/* Number of frame labels */
+
+	u32 tile_label[GCE_REC_MAX_LABEL_COUNT];  /* Tile labels */
+	u32 tile_count;	/* Number of tile labels */
+
+	u32 footer_code;	/* Footer guard word */
+};
+#endif /* _MTK_IMGSYS_CMDQ_PLAT_H_ */
+
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-cmdq.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-cmdq.c
new file mode 100644
index 000000000000..7628ade90b6b
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-cmdq.c
@@ -0,0 +1,690 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Daniel Huang <daniel.huang at mediatek.com>
+ *
+ */
+#include <linux/dma-mapping.h>
+#include <linux/mailbox_controller.h>
+#include <linux/math64.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+#include <linux/pm_opp.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <linux/vmalloc.h>
+#include "mtk_imgsys-cmdq.h"
+#include "mtk_imgsys-cmdq-plat.h"
+#include "mtk_imgsys-module_common.h"
+
+#define MAX_FRAME_IN_TASK 64
+#define CMDQ_BUF_SIZE 0x4000
+
+static struct workqueue_struct *imgsys_cmdq_wq;
+static u32 is_stream_off;
+
+/**
+ * enum mtk_imgsys_cmd - Commands for image system operations
+ * @IMGSYS_CMD_WRITE: Write operation
+ * @IMGSYS_CMD_POLL: Poll operation
+ * @IMGSYS_CMD_WAIT: Wait operation
+ * @IMGSYS_CMD_UPDATE: Update operation
+ * @IMGSYS_CMD_ACQUIRE: Acquire operation
+ * @IMGSYS_CMD_STOP: Stop operation
+ *
+ * This enumeration defines the various commands that determine how to use the
+ * cmdq API for image system operations.
+ */
+enum mtk_imgsys_cmd {
+	IMGSYS_CMD_WRITE,
+	IMGSYS_CMD_POLL,
+	IMGSYS_CMD_WAIT,
+	IMGSYS_CMD_UPDATE,
+	IMGSYS_CMD_ACQUIRE,
+	IMGSYS_CMD_STOP
+};
+
+/**
+ * struct access - Access parameters for image system commands
+ * @address: Memory address to access
+ * @value: Value to write to the memory address
+ * @mask: Mask for the value
+ *
+ * This structure defines the parameters for memory access operations used by
+ * IMGSYS_CMD_WRITE and IMGSYS_CMD_POLL commands.
+ */
+struct access {
+	u64 address;
+	u32 value;
+	u32 mask;
+} __packed;
+
+/**
+ * struct event - Event parameters for image system commands
+ * @event: Event identifier
+ * @action: Action to perform for the event
+ *
+ * This structure defines the parameters for event-based operations used by
+ * IMGSYS_CMD_WAIT, IMGSYS_CMD_UPDATE and IMGSYS_CMD_ACQUIRE commands.
+ */
+struct event {
+	u32 event;
+	u32 action;
+} __packed;
+
+/**
+ * struct command - Command structure for image system operations
+ * @opcode: Operation code (command)
+ * @param: Union of parameters for different commands
+ *     @write: Parameters for write command
+ *     @poll: Parameters for poll command
+ *     @wait: Parameters for wait command
+ *     @update: Parameters for update command
+ *     @acquire: Parameters for acquire command
+ *
+ * This structure is used to store the instructions and parameters for how to
+ * use the cmdq driver.
+ */
+struct command {
+	enum mtk_imgsys_cmd opcode;
+	union {
+		struct access write;
+		struct access poll;
+		struct event wait;
+		struct event update;
+		struct event acquire;
+	} param;
+} __packed;
+
+/**
+ * struct mtk_imgsys_cb_param - Callback parameters for image system commands
+ * @cmdq_cb_work: Work structure for command queue callback
+ * @pkt: Command packet
+ * @frm_info: Pointer to frame information
+ * @imgsys_dev: Pointer to image system device
+ * @clt: Pointer to command queue client
+ * @user_cmdq_cb: User-defined command queue callback function
+ * @err: Error code
+ * @frm_idx: Frame index
+ * @frm_num: Number of frames
+ * @blk_idx: Block index
+ * @blk_num: Number of blocks
+ * @is_earlycb: Indicates if it is an early callback
+ * @group_id: Group identifier
+ * @thd_idx: Thread index
+ * @task_id: Task identifier
+ * @task_num: Number of tasks
+ * @task_cnt: Task count
+ * @pkt_ofst: Array of packet offsets for frames in task
+ * @is_blk_last: Indicates if it is the last block
+ * @is_frm_last: Indicates if it is the last frame
+ * @is_task_last: Indicates if it is the last task
+ *
+ * This structure defines the parameters for callbacks related to
+ * image system commands.
+ */
+struct mtk_imgsys_cb_param {
+	struct work_struct cmdq_cb_work;
+	struct cmdq_pkt pkt;
+	struct swfrm_info *frm_info;
+	struct mtk_imgsys_dev *imgsys_dev;
+	struct cmdq_client *clt;
+	void (*user_cmdq_cb)(struct imgsys_cmdq_cb_data data);
+	s32 err;
+	u32 frm_idx;
+	u32 frm_num;
+	u32 blk_idx;
+	u32 blk_num;
+	u32 is_earlycb;
+	s32 group_id;
+	u32 thd_idx;
+	u32 task_id;
+	u32 task_num;
+	u32 task_cnt;
+	size_t pkt_ofst[MAX_FRAME_IN_TASK];
+	bool is_blk_last;
+	bool is_frm_last;
+	bool is_task_last;
+};
+
+static void imgsys_cmdq_task_cb(struct mbox_client *cl, void *mssg);
+static struct cmdq_client *imgsys_clt[IMGSYS_ENG_MAX];
+
+void imgsys_cmdq_init(struct mtk_imgsys_dev *imgsys_dev)
+{
+	struct device *dev = imgsys_dev->dev;
+	u32 idx = 0;
+
+	/* Only first user has to allocate the work queue */
+	if (!imgsys_cmdq_wq) {
+		imgsys_cmdq_wq =
+			alloc_ordered_workqueue("%s", __WQ_LEGACY |
+						WQ_MEM_RECLAIM |
+						WQ_FREEZABLE,
+						"imgsys_cmdq_cb_wq");
+		if (!imgsys_cmdq_wq) {
+			dev_dbg(imgsys_dev->dev,
+				"%s:allcate cmdq callback work queue fail!\n",
+				__func__);
+			return;
+		}
+	}
+
+	/* Request mailbox channels for each IMGSYS engine */
+	for (idx = 0; idx < IMGSYS_ENG_MAX; idx++) {
+		imgsys_clt[idx] = kzalloc(sizeof(*imgsys_clt[idx]), GFP_KERNEL);
+		if (!imgsys_clt[idx])
+			return;
+
+		imgsys_clt[idx]->client.dev = dev;
+		imgsys_clt[idx]->client.tx_block = false;
+		imgsys_clt[idx]->client.knows_txdone = true;
+		imgsys_clt[idx]->client.rx_callback = imgsys_cmdq_task_cb;
+		imgsys_clt[idx]->chan =
+		mbox_request_channel(&imgsys_clt[idx]->client, idx);
+	}
+
+	/* Parse events from dts */
+	for (idx = 0; idx < IMGSYS_EVENT_MAX; idx++)
+		of_property_read_u16(dev->of_node,
+				     imgsys_event[idx].dts_name,
+				     &imgsys_event[idx].event);
+}
+
+void imgsys_cmdq_release(struct mtk_imgsys_dev *imgsys_dev)
+{
+	u32 idx = 0;
+
+	/* Destroy cmdq client */
+	for (idx = 0; idx < IMGSYS_ENG_MAX; idx++) {
+		cmdq_mbox_destroy(imgsys_clt[idx]);
+		imgsys_clt[idx] = NULL;
+	}
+
+	/* Release work_quque */
+	flush_workqueue(imgsys_cmdq_wq);
+	destroy_workqueue(imgsys_cmdq_wq);
+	imgsys_cmdq_wq = NULL;
+}
+
+void imgsys_cmdq_streamon(struct mtk_imgsys_dev *imgsys_dev)
+{
+	dev_info(imgsys_dev->dev, "%s: cmdq stream on (%d)\n", __func__, is_stream_off);
+	is_stream_off = 0;
+}
+
+void imgsys_cmdq_streamoff(struct mtk_imgsys_dev *imgsys_dev)
+{
+	dev_info(imgsys_dev->dev, "%s: cmdq stream off (%d)\n", __func__, is_stream_off);
+	is_stream_off = 1;
+}
+
+static void imgsys_cmdq_cmd_dump(struct swfrm_info *frm_info, u32 frm_idx)
+{
+	struct gce_recorder *cmd_buf = NULL;
+	struct command *cmd = NULL;
+	u32 cmd_num = 0;
+	u32 cmd_idx = 0;
+
+	cmd_buf = (struct gce_recorder *)frm_info->user_info[frm_idx].g_swbuf;
+	cmd_num = cmd_buf->curr_length / sizeof(struct command);
+
+	if (sizeof(struct gce_recorder) != (u64)cmd_buf->cmd_offset) {
+		pr_info("%s: [ERROR] cmd offset is not match (0x%x/0x%zx)!\n",
+			__func__, cmd_buf->cmd_offset,
+			sizeof(struct gce_recorder));
+		return;
+	}
+
+	cmd = (struct command *)((char *)(frm_info->user_info[frm_idx].g_swbuf) +
+		(unsigned long)(cmd_buf->cmd_offset));
+
+	for (cmd_idx = 0; cmd_idx < cmd_num; cmd_idx++) {
+		switch (cmd[cmd_idx].opcode) {
+		case IMGSYS_CMD_WRITE:
+			pr_info("WRITE with addr(0x%08llx) value(0x%08x) mask(0x%08x)\n",
+				cmd[cmd_idx].param.write.address,
+				cmd[cmd_idx].param.write.value,
+				cmd[cmd_idx].param.write.mask);
+			break;
+		case IMGSYS_CMD_POLL:
+			pr_info("POLL with addr(0x%08llx) value(0x%08x) mask(0x%08x)\n",
+				cmd[cmd_idx].param.poll.address,
+				cmd[cmd_idx].param.poll.value,
+				cmd[cmd_idx].param.poll.mask);
+			break;
+		case IMGSYS_CMD_WAIT:
+			pr_info("WAIT event(%d/%d) action(%d)\n",
+				cmd[cmd_idx].param.wait.event,
+				imgsys_event[cmd[cmd_idx].param.wait.event].event,
+				cmd[cmd_idx].param.wait.action);
+			break;
+		case IMGSYS_CMD_UPDATE:
+			pr_info("UPDATE event(%d/%d) action(%d)\n",
+				cmd[cmd_idx].param.update.event,
+				imgsys_event[cmd[cmd_idx].param.update.event].event,
+				cmd[cmd_idx].param.update.action);
+			break;
+		case IMGSYS_CMD_ACQUIRE:
+			pr_info("ACQUIRE event(%d/%d) action(%d)\n",
+				cmd[cmd_idx].param.acquire.event,
+				imgsys_event[cmd[cmd_idx].param.acquire.event].event,
+				cmd[cmd_idx].param.acquire.action);
+			break;
+		case IMGSYS_CMD_STOP:
+			pr_info("%s: End Of Cmd!\n", __func__);
+			break;
+		default:
+			pr_info("%s: [ERROR]Not Support Cmd(%d)!\n",
+				__func__, cmd[cmd_idx].opcode);
+			break;
+		}
+	}
+}
+
+static void imgsys_cmdq_cb_work(struct work_struct *work)
+{
+	struct mtk_imgsys_cb_param *cb_param = NULL;
+	struct mtk_imgsys_dev *imgsys_dev = NULL;
+	u32 cb_frm_cnt;
+
+	cb_param = container_of(work, struct mtk_imgsys_cb_param, cmdq_cb_work);
+	imgsys_dev = cb_param->imgsys_dev;
+
+	if (cb_param->err != 0) {
+		pr_info("%s: [ERROR] cb(%p) cb_cnt(%d) req fd/no(%d/%d) error(%d).\n",
+			__func__, cb_param,
+			cb_param->frm_info->cb_frmcnt,
+			cb_param->frm_info->request_fd,
+			cb_param->frm_info->request_no,
+			cb_param->err);
+
+		pr_info("%s: Frame Info: frm(%d/%d) blk(%d/%d) earlycb(%d) lst(%d/%d/%d).\n",
+			__func__, cb_param->frm_idx, cb_param->frm_num,
+			cb_param->blk_idx, cb_param->blk_num, cb_param->is_earlycb,
+			cb_param->is_blk_last, cb_param->is_frm_last, cb_param->is_task_last);
+
+		pr_info("%s: CMDQ Info: task(%d/%d/%d) ofst(%zx/%zx/%zx/%zx/%zx).\n",
+			__func__, cb_param->task_id, cb_param->task_num, cb_param->task_cnt,
+			cb_param->pkt_ofst[0], cb_param->pkt_ofst[1], cb_param->pkt_ofst[2],
+			cb_param->pkt_ofst[3], cb_param->pkt_ofst[4]);
+	}
+
+	if (is_stream_off == 1)
+		pr_info("%s: [ERROR] cb(%p) pipe already streamoff(%d)!\n",
+			__func__, cb_param, is_stream_off);
+
+	cb_param->frm_info->cb_frmcnt++;
+	cb_frm_cnt = cb_param->frm_info->cb_frmcnt;
+
+	if (cb_param->is_blk_last && cb_param->user_cmdq_cb &&
+	    (cb_param->frm_info->total_taskcnt == cb_frm_cnt ||
+		cb_param->is_earlycb)) {
+		struct imgsys_cmdq_cb_data user_cb_data;
+
+		user_cb_data.cmdq_data.sta = cb_param->err;
+		user_cb_data.cmdq_data.pkt = NULL;
+		user_cb_data.data = (void *)cb_param->frm_info;
+		cb_param->user_cmdq_cb(user_cb_data);
+	}
+
+	cmdq_pkt_destroy(cb_param->clt, &cb_param->pkt);
+	vfree(cb_param);
+}
+
+static void imgsys_cmdq_task_cb(struct mbox_client *cl, void *mssg)
+{
+	struct cmdq_cb_data *data = mssg;
+	struct mtk_imgsys_cb_param *cb_param =
+		container_of(data->pkt, struct mtk_imgsys_cb_param, pkt);
+
+	struct mtk_imgsys_pipe *pipe;
+	u32 frm_idx = 0;
+
+	cb_param->err = data->sta;
+
+	pr_debug("%s: Receive cb(%p) with sta(%d) for frm(%d/%d)\n",
+		 __func__, cb_param, data->sta, cb_param->frm_idx,
+		 cb_param->frm_num);
+
+	if (cb_param->err != 0) {
+		frm_idx = cb_param->frm_idx;
+		pr_info("%s: [ERROR] cb(%p) error info(%d).\n",
+			__func__, cb_param, cb_param->err);
+
+		pr_info("%s: Frame Info: frm(%d/%d) blk(%d/%d) earlycb(%d) lst(%d/%d/%d).\n",
+			__func__, cb_param->frm_idx, cb_param->frm_num,
+			cb_param->blk_idx, cb_param->blk_num, cb_param->is_earlycb,
+			cb_param->is_blk_last, cb_param->is_frm_last, cb_param->is_task_last);
+
+		pr_info("%s: CMDQ Info: task(%d/%d/%d) ofst(%zx/%zx/%zx/%zx/%zx).\n",
+			__func__, cb_param->task_id, cb_param->task_num, cb_param->task_cnt,
+			cb_param->pkt_ofst[0], cb_param->pkt_ofst[1], cb_param->pkt_ofst[2],
+			cb_param->pkt_ofst[3], cb_param->pkt_ofst[4]);
+
+		if (is_stream_off == 1)
+			pr_info("%s: [ERROR] cb(%p) pipe had been turned off(%d)!\n",
+				__func__, cb_param, is_stream_off);
+
+		pipe = (struct mtk_imgsys_pipe *)cb_param->frm_info->pipe;
+		if (!pipe->streaming) {
+			pr_info("%s: [ERROR] cb(%p): pipe already streamoff\n",
+				__func__, cb_param);
+		}
+
+		imgsys_cmdq_cmd_dump(cb_param->frm_info, frm_idx);
+	}
+
+	INIT_WORK(&cb_param->cmdq_cb_work, imgsys_cmdq_cb_work);
+	queue_work(imgsys_cmdq_wq, &cb_param->cmdq_cb_work);
+}
+
+static int imgsys_cmdq_parser(struct cmdq_pkt *pkt,
+			      struct command *cmd, u32 cmd_num)
+{
+	bool stop = false;
+	int count = 0;
+	u32 event_id;
+
+	do {
+		switch (cmd->opcode) {
+		case IMGSYS_CMD_WRITE:
+			if (cmd->param.write.address < IMGSYS_REG_START ||
+			    cmd->param.write.address > IMGSYS_REG_END) {
+				pr_info("%s: [ERROR] WRITE: wrong address(0x%08llx)!\n",
+					__func__, cmd->param.poll.address);
+				return -1;
+			}
+			pr_debug("%s: WRITE with addr(0x%08llx) value(0x%08x) mask(0x%08x)\n",
+				 __func__, cmd->param.write.address,
+				 cmd->param.write.value,
+				 cmd->param.write.mask);
+
+			cmdq_pkt_assign(pkt, CMDQ_THR_SPR_IDX0,
+					CMDQ_ADDR_HIGH(cmd->param.write.address));
+			if (cmd->param.write.mask != GENMASK(31, 0))
+				cmdq_pkt_write_s_mask_value(pkt, CMDQ_THR_SPR_IDX0,
+							    CMDQ_ADDR_LOW(cmd->param.write.address),
+							    cmd->param.write.value,
+							    cmd->param.write.mask);
+			else
+				cmdq_pkt_write_s_value(pkt, CMDQ_THR_SPR_IDX0,
+						       CMDQ_ADDR_LOW(cmd->param.write.address),
+						       cmd->param.write.value);
+			break;
+		case IMGSYS_CMD_POLL:
+			if (cmd->param.poll.address < IMGSYS_REG_START ||
+			    cmd->param.poll.address > IMGSYS_REG_END) {
+				pr_info("%s: [ERROR] POLL: wrong address(0x%08llx)!\n",
+					__func__, cmd->param.poll.address);
+				return -1;
+			}
+			pr_debug("%s: POLL with addr(0x%08llx) value(0x%08x) mask(0x%08x)\n",
+				 __func__, cmd->param.poll.address,
+				 cmd->param.poll.value, cmd->param.poll.mask);
+
+			cmdq_pkt_poll_addr(pkt, cmd->param.poll.address,
+					   cmd->param.poll.value,
+					   cmd->param.poll.mask);
+			break;
+		case IMGSYS_CMD_WAIT:
+			event_id = cmd->param.wait.event;
+			if (event_id >= IMGSYS_EVENT_MAX) {
+				pr_info("%s: [ERROR] WAIT: wrong event(%d)!\n",
+					__func__, event_id);
+				return -1;
+			}
+			pr_debug("%s: WAIT event(%d/%d) action(%d)\n",
+				 __func__, event_id,
+				 imgsys_event[event_id].event,
+				 cmd->param.wait.action);
+
+			if (cmd->param.wait.action == 1)
+				cmdq_pkt_wfe(pkt, imgsys_event[event_id].event, true);
+			else if (cmd->param.wait.action == 0)
+				cmdq_pkt_wfe(pkt, imgsys_event[event_id].event, false);
+
+			break;
+		case IMGSYS_CMD_UPDATE:
+			event_id = cmd->param.update.event;
+			if (event_id >= IMGSYS_EVENT_MAX) {
+				pr_info("%s: [ERROR] UPDATE: wrong event(%d)!\n",
+					__func__, event_id);
+				return -1;
+			}
+
+			pr_debug("%s: UPDATE event(%d/%d) action(%d)\n",
+				 __func__, event_id,
+				 imgsys_event[event_id].event,
+				 cmd->param.update.action);
+
+			if (cmd->param.update.action == 1)
+				cmdq_pkt_set_event(pkt, imgsys_event[event_id].event);
+			else if (cmd->param.update.action == 0)
+				cmdq_pkt_clear_event(pkt, imgsys_event[event_id].event);
+
+			break;
+		case IMGSYS_CMD_ACQUIRE:
+			event_id = cmd->param.acquire.event;
+			if (event_id >= IMGSYS_EVENT_MAX) {
+				pr_info("%s: [ERROR] ACQUIRE: wrong event(%d)!\n",
+					__func__, event_id);
+				return -1;
+			}
+
+			pr_debug("%s: ACQUIRE event(%d/%d) action(%d)\n",
+				 __func__, event_id,
+				 imgsys_event[event_id].event,
+				 cmd->param.acquire.action);
+
+			cmdq_pkt_acquire_event(pkt, imgsys_event[event_id].event);
+			break;
+		case IMGSYS_CMD_STOP:
+			pr_debug("%s: End Of Cmd!\n", __func__);
+			stop = true;
+			break;
+		default:
+			pr_info("%s: [ERROR] Not Support Cmd(%d)!\n", __func__, cmd->opcode);
+			return -1;
+		}
+		cmd++;
+		count++;
+	} while ((!stop) && (count < cmd_num));
+
+	return count;
+}
+
+int imgsys_cmdq_sendtask(struct mtk_imgsys_dev *imgsys_dev,
+			 struct swfrm_info *frm_info,
+			 void (*cmdq_cb)(struct imgsys_cmdq_cb_data data))
+{
+	struct cmdq_client *clt = NULL;
+	struct gce_recorder *cmd_buf = NULL;
+	struct command *cmd = NULL;
+	struct mtk_imgsys_cb_param *cb_param = NULL;
+	u32 cmd_num = 0;
+	u32 cmd_idx = 0;
+	u32 blk_idx = 0; /* For Vss block cnt */
+	u32 thd_idx = 0;
+	u32 hw_comb = 0;
+	int ret = 0, ret_flush = 0;
+	u32 frm_num = 0, frm_idx = 0;
+	bool is_pack = 0;
+	u32 task_idx = 0;
+	u32 task_id = 0;
+	u32 task_num = 0;
+	u32 task_cnt = 0;
+	size_t pkt_ofst[MAX_FRAME_IN_TASK] = {0};
+
+	frm_num = frm_info->total_frmnum;
+	frm_info->cb_frmcnt = 0;
+	frm_info->total_taskcnt = 0;
+
+	for (frm_idx = 0; frm_idx < frm_num; frm_idx++) {
+		cmd_buf = (struct gce_recorder *)frm_info->user_info[frm_idx].g_swbuf;
+
+		/* Validate the GCE recorder structure */
+		if (cmd_buf->header_code != HEADER_CODE ||
+		    cmd_buf->check_pre != CHECK_PRE ||
+		    cmd_buf->check_post != CHECK_POST ||
+		    cmd_buf->footer_code != FOOTER_CODE) {
+			pr_info("%s: Incorrect guard word: %08x/%08x/%08x/%08x",
+				__func__, cmd_buf->header_code, cmd_buf->check_pre,
+				cmd_buf->check_post, cmd_buf->footer_code);
+			return -1;
+		}
+
+		cmd_num = cmd_buf->curr_length / sizeof(struct command);
+		cmd = (struct command *)((char *)frm_info->user_info[frm_idx].g_swbuf
+		      + (unsigned long)cmd_buf->cmd_offset);
+
+		hw_comb = frm_info->user_info[frm_idx].hw_comb;
+
+		if (is_pack == 0) {
+			if (frm_info->group_id == -1) {
+				/* Choose cmdq_client base on hw scenario */
+				for (thd_idx = 0; thd_idx < IMGSYS_ENG_MAX; thd_idx++) {
+					if (hw_comb & 0x1) {
+						clt = imgsys_clt[thd_idx];
+						pr_debug("%s: mbox thread (%d, %p)\n",
+							 __func__, thd_idx, clt);
+						pr_debug("%s: frm(%d/%d)\n",
+							 __func__, frm_idx, frm_num);
+						break;
+					}
+					hw_comb = hw_comb >> 1;
+				}
+				/* This segment can be removed since user had set dependency */
+				if (frm_info->user_info[frm_idx].hw_comb & IMGSYS_ENG_DIP) {
+					thd_idx = 4;
+					clt = imgsys_clt[thd_idx];
+				}
+			} else {
+				if (frm_info->group_id >= 0 &&
+				    frm_info->group_id < IMGSYS_NOR_THD) {
+					thd_idx = frm_info->group_id;
+					clt = imgsys_clt[thd_idx];
+				} else {
+					pr_info("%s: [ERROR] Group id(%d) is not in range(%d).\n",
+						__func__, frm_info->group_id, IMGSYS_NOR_THD);
+					pr_info("%s: [ERROR] Frame Info: frm(%d/%d) hw_comb(%d).\n",
+						__func__, frm_idx, frm_num,
+						frm_info->user_info[frm_idx].hw_comb);
+					return -1;
+				}
+			}
+
+			/* This is work around for low latency flow. */
+			/* If we change to request base,			 */
+			/* we don't have to take this condition into account.	*/
+			if (frm_info->sync_id != -1) {
+				thd_idx = 0;
+				clt = imgsys_clt[thd_idx];
+			}
+
+			if (!clt) {
+				pr_info("%s: [ERROR] No HW Found (0x%x) for frm(%d/%d)!\n",
+					__func__, frm_info->user_info[frm_idx].hw_comb,
+					frm_idx, frm_num);
+				return -1;
+			}
+		}
+
+		cmd_idx = 0;
+
+		for (blk_idx = 0; blk_idx < cmd_buf->frame_block; blk_idx++) {
+			if (is_pack == 0) {
+				/* Prepare cb param */
+				cb_param = vzalloc(sizeof(*cb_param));
+				if (!cb_param)
+					return -1;
+
+				/* create pkt and hook clt as pkt's private data */
+				if (cmdq_pkt_create(clt, &cb_param->pkt, CMDQ_BUF_SIZE)) {
+					vfree(cb_param);
+					pr_info("%s: [ERROR] Id %d imgsys_create_pkt fail!\n",
+						__func__, blk_idx);
+					return -1;
+				}
+			}
+
+			ret = imgsys_cmdq_parser(&cb_param->pkt, &cmd[cmd_idx], cmd_num);
+
+			if (ret < 0) {
+				pr_info("%s: [ERROR] Parsing fail. cmd(%d/%d) frm(%d/%d/%d)\n",
+					__func__, cmd_idx, cmd[cmd_idx].opcode,
+					blk_idx, frm_idx, frm_num);
+
+				cmdq_pkt_destroy(clt, &cb_param->pkt);
+				vfree(cb_param);
+				goto sendtask_done;
+			}
+			cmd_idx += ret;
+
+			/* Check for packing gce task */
+			pkt_ofst[task_cnt] = cb_param->pkt.cmd_buf_size - CMDQ_INST_SIZE;
+			task_cnt++;
+			if (frm_info->user_info[frm_idx].is_time_shared ||
+			    frm_info->user_info[frm_idx].is_earlycb ||
+			    frm_idx + 1 == frm_num) {
+				task_num++;
+				cb_param->frm_info = frm_info;
+				cb_param->frm_idx = frm_idx;
+				cb_param->frm_num = frm_num;
+				cb_param->user_cmdq_cb = cmdq_cb;
+				if ((blk_idx + 1) == cmd_buf->frame_block)
+					cb_param->is_blk_last = 1;
+				else
+					cb_param->is_blk_last = 0;
+				if ((frm_idx + 1) == frm_num)
+					cb_param->is_frm_last = 1;
+				else
+					cb_param->is_frm_last = 0;
+				cb_param->blk_idx = blk_idx;
+				cb_param->blk_num = cmd_buf->frame_block;
+				cb_param->is_earlycb = frm_info->user_info[frm_idx].is_earlycb;
+				cb_param->group_id = frm_info->group_id;
+				cb_param->imgsys_dev = imgsys_dev;
+				cb_param->thd_idx = thd_idx;
+				cb_param->clt = clt;
+				cb_param->task_cnt = task_cnt;
+				for (task_idx = 0; task_idx < task_cnt; task_idx++)
+					cb_param->pkt_ofst[task_idx] = pkt_ofst[task_idx];
+				task_cnt = 0;
+				cb_param->task_id = task_id;
+				task_id++;
+				if (cb_param->is_blk_last && cb_param->is_frm_last) {
+					cb_param->is_task_last = 1;
+					cb_param->task_num = task_num;
+					frm_info->total_taskcnt = task_num;
+				} else {
+					cb_param->is_task_last = 0;
+					cb_param->task_num = 0;
+				}
+
+				/* flush synchronized, block API */
+				cmdq_pkt_eoc(&cb_param->pkt);
+				cmdq_pkt_jump_rel(&cb_param->pkt, CMDQ_INST_SIZE,
+						  cmdq_get_shift_pa(clt->chan));
+				dma_sync_single_for_device(clt->chan->mbox->dev,
+							   cb_param->pkt.pa_base,
+							   cb_param->pkt.cmd_buf_size,
+							   DMA_TO_DEVICE);
+
+				mbox_send_message(clt->chan, &cb_param->pkt);
+				mbox_client_txdone(clt->chan, 0);
+				if (ret_flush < 0)
+					pr_info("%s: [ERROR] Frame(%d/%d) flushing fail(%d).\n",
+						__func__, ret_flush, frm_idx, frm_num);
+				is_pack = 0;
+			} else {
+				dev_info(imgsys_dev->dev, "%s:is_pack = 1", __func__);
+				is_pack = 1;
+			}
+		}
+	}
+
+sendtask_done:
+	return 0;
+}
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-cmdq.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-cmdq.h
new file mode 100644
index 000000000000..47bbd6735d0b
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-cmdq.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ *
+ * Author: Daniel Huang <daniel.huang at mediatek.com>
+ *
+ */
+#ifndef _MTK_IMGSYS_CMDQ_H_
+#define _MTK_IMGSYS_CMDQ_H_
+
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+#include "mtk_imgsys-dev.h"
+
+/* Structure to hold command queue callback data */
+struct imgsys_cmdq_cb_data {
+	struct cmdq_cb_data cmdq_data; /* Command queue data */
+	void *data;                    /* Additional data */
+};
+
+void imgsys_cmdq_streamon(struct mtk_imgsys_dev *imgsys_dev);
+void imgsys_cmdq_streamoff(struct mtk_imgsys_dev *imgsys_dev);
+void imgsys_cmdq_init(struct mtk_imgsys_dev *imgsys_dev);
+void imgsys_cmdq_release(struct mtk_imgsys_dev *imgsys_dev);
+int imgsys_cmdq_sendtask(struct mtk_imgsys_dev *imgsys_dev,
+			 struct swfrm_info *frm_info,
+			 void (*cmdq_cb)(struct imgsys_cmdq_cb_data data));
+
+#endif /* _MTK_IMGSYS_CMDQ_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_common.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_common.h
index dd02a8fa28d4..3918e360a5a0 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_common.h
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_common.h
@@ -39,6 +39,26 @@
 #define CQ_THRX_CTL_MODE	BIT(4)
 #define CQ_THRX_CTL			(CQ_THRX_CTL_EN | CQ_THRX_CTL_MODE)
 
+/**
+ * enum mtk_imgsys_engine_bitmask - Bitmasks for supported hardware engines
+ *
+ * This enumeration defines the bitmasks for the supported hardware engines in
+ * the image system.
+ */
+enum mtk_imgsys_engine_bitmask {
+	IMGSYS_ENG_WPE_EIS	=	0x00000001, /* Bitmask for WPE EIS engine */
+	IMGSYS_ENG_WPE_TNR	=	0x00000002, /* Bitmask for WPE TNR engine */
+	IMGSYS_ENG_WPE_LITE	=	0x00000004, /* Bitmask for WPE Lite engine */
+	IMGSYS_ENG_TRAW		=	0x00000020, /* Bitmask for TRAW engine */
+	IMGSYS_ENG_LTR		=	0x00000040, /* Bitmask for LTR engine */
+	IMGSYS_ENG_XTR		=	0x00000080, /* Bitmask for XTR engine */
+	IMGSYS_ENG_DIP		=	0x00000100, /* Bitmask for DIP engine */
+	IMGSYS_ENG_PQDIP_A	=	0x00000200, /* Bitmask for PQDIP A engine */
+	IMGSYS_ENG_PQDIP_B	=	0x00000400, /* Bitmask for PQDIP B engine */
+	IMGSYS_ENG_ME		=	0x00000800, /* Bitmask for ME engine */
+	IMGSYS_ENG_MAX_NUM	=	0x00001000 /* Maximum bitmask value */
+};
+
 /**
  * enum mtk_imgsys_reg_id
  *
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
index 9f118491b37d..184f0e3a4d3b 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
@@ -9,6 +9,7 @@
 #include <linux/pm_runtime.h>
 #include "mtk_imgsys-sys.h"
 #include "mtk_imgsys-dev.h"
+#include "mtk_imgsys-cmdq.h"
 
 static int mtk_imgsys_hw_connect(struct mtk_imgsys_dev *imgsys_dev)
 {
@@ -26,6 +27,8 @@ static int mtk_imgsys_hw_connect(struct mtk_imgsys_dev *imgsys_dev)
 
 	kref_init(&imgsys_dev->init_kref);
 
+	/* calling cmdq stream on */
+	imgsys_cmdq_streamon(imgsys_dev);
 	return 0;
 }
 
@@ -43,6 +46,8 @@ static void module_uninit(struct kref *kref)
 
 static void mtk_imgsys_hw_disconnect(struct mtk_imgsys_dev *imgsys_dev)
 {
+	/* calling cmdq stream off */
+	imgsys_cmdq_streamoff(imgsys_dev);
 	kref_put(&imgsys_dev->init_kref, module_uninit);
 }
 
-- 
2.45.2



From olivia.wen at mediatek.com  Sat May 24 04:50:01 2025
From: olivia.wen at mediatek.com (Olivia Wen)
Date: Sat, 24 May 2025 19:50:01 +0800
Subject: [PATCH v1 09/10] media: mediatek: isp: Add image processing flow
In-Reply-To: <20250524115144.3832748-1-olivia.wen@mediatek.com>
References: <20250524115144.3832748-1-olivia.wen@mediatek.com>
Message-ID: <20250524115144.3832748-10-olivia.wen@mediatek.com>

The ImgSys driver is implemented as a series of patches, with this patch
focusing on the image processing flow for the MediaTek ImgSys driver.
It is a crucial part of the ImgSys architecture, controlling the flow of
operations from the user applications to the hardware. The ImgSys driver
manages various components (e.g. SCP, CMDQ) and processes to ensure
efficient image processing.

Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
---
 .../mediatek/isp/isp_7x/imgsys/Makefile       |   2 +
 .../isp/isp_7x/imgsys/mtk_header_desc.h       | 101 ++++
 .../isp/isp_7x/imgsys/mtk_imgsys-dev.c        |  61 +++
 .../isp/isp_7x/imgsys/mtk_imgsys-dev.h        | 139 +++++-
 .../isp/isp_7x/imgsys/mtk_imgsys-gce_work.c   |  82 +++
 .../isp/isp_7x/imgsys/mtk_imgsys-gce_work.h   |  37 ++
 .../isp/isp_7x/imgsys/mtk_imgsys-sys.c        | 468 +++++++++++++++++-
 .../isp/isp_7x/imgsys/mtk_imgsys-v4l2.c       | 128 ++++-
 .../isp/isp_7x/imgsys/mtk_imgsys-work_buf.c   | 113 +++++
 .../isp/isp_7x/imgsys/mtk_imgsys-work_buf.h   |  55 ++
 10 files changed, 1169 insertions(+), 17 deletions(-)
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-gce_work.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-gce_work.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-work_buf.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-work_buf.h

diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
index 29c18c773fdc..3aa53e8bfc6d 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
@@ -2,6 +2,8 @@
 #
 
 mtk_imgsys_util-objs := \
+mtk_imgsys-work_buf.o \
+mtk_imgsys-gce_work.o \
 mtk_imgsys-cmdq.o \
 mtk_imgsys-scp.o \
 mtk_imgsys-module_main.o \
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_header_desc.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_header_desc.h
index 50c2e3c3395b..673e84aad362 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_header_desc.h
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_header_desc.h
@@ -9,6 +9,39 @@
 
 #include <linux/videodev2.h>
 
+#define IMGBUF_MAX_PLANES	3 /* Maximum number of planes in an image buffer */
+#define IMG_MAX_HW_DMAS		72 /* Maximum number of hardware DMAs */
+
+/**
+ * struct v4l2_ext_plane - Extended plane information
+ * @offset: Offset within the DMA buffer
+ * @phyaddr: Physical address of the DMA buffer
+ * @isp_addr: ISP (Image Signal Processor) address
+ * @size: Size of the plane
+ */
+struct v4l2_ext_plane {
+	union {
+		struct {
+			__u32 offset;    /* Offset within the DMA buffer */
+			__u64 phyaddr;   /* Physical address of the DMA buffer */
+		} dma_buf;
+	} m;
+	__u64 isp_addr;           /* ISP (Image Signal Processor) address */
+	__u64 size;               /* Size of the plane */
+};
+
+/**
+ * struct v4l2_ext_buffer - Extended V4L2 buffer
+ * @planes: Array of extended plane information
+ * @num_planes: Number of planes
+ * @reserved: Reserved for future use
+ */
+struct v4l2_ext_buffer {
+	struct v4l2_ext_plane	planes[IMGBUF_MAX_PLANES];
+	__u32			num_planes;
+	__u64			reserved[2];
+};
+
 /**
  * struct mtk_imgsys_crop - Crop parameters for MediaTek Image System
  * @c: Rectangle defining the crop area
@@ -25,4 +58,72 @@ struct mtk_imgsys_crop {
 	struct v4l2_fract   height_subpix; /* Sub-pixel adjustment for the height */
 };
 
+/**
+ * struct plane_pix_format - Pixel format for a single plane
+ * @sizeimage: Size of the image in bytes
+ * @bytesperline: Number of bytes per line
+ */
+struct plane_pix_format {
+	__u32 sizeimage;
+	__u32 bytesperline;
+} __packed;
+
+/**
+ * struct pix_format_mplane - Multi-plane pixel format
+ * @width: Width of the image
+ * @height: Height of the image
+ * @pixelformat: Pixel format identifier
+ * @plane_fmt: Array of pixel formats for each plane
+ */
+struct pix_format_mplane {
+	__u32 width;
+	__u32 height;
+	__u32 pixelformat;
+	struct plane_pix_format plane_fmt[IMGBUF_MAX_PLANES];
+} __packed;
+
+/**
+ * struct frameparams - Frame parameters for MediaTek Image System
+ * @buf: Extended buffer information
+ * @fmt: Multi-plane pixel format
+ * @crop: Crop parameters
+ * @rotation: Rotation angle
+ * @hflip: Horizontal flip flag
+ * @vflip: Vertical flip flag
+ * @resizeratio: Resize ratio
+ */
+struct frameparams {
+	struct v4l2_ext_buffer buf;          /* Extended buffer information */
+	struct pix_format_mplane fmt;        /* Multi-plane pixel format */
+	struct mtk_imgsys_crop crop;         /* Crop parameters */
+	__u32 rotation;                      /* Rotation angle */
+	__u32 hflip;                         /* Horizontal flip flag */
+	__u32 vflip;                         /* Vertical flip flag */
+	__u8  resizeratio;                   /* Resize ratio */
+};
+
+/**
+ * struct header_desc_norm - Header description for normal camera case
+ * @fparams_num: Number of frame parameters
+ * @fparams: Frame parameters
+ */
+struct header_desc_norm {
+	__u32 fparams_num;
+	struct frameparams fparams;
+};
+
+/**
+ * struct singlenode_desc_norm - Single node description for normal camera case
+ * @dmas_enable: Array indicating enabled DMA channels
+ * @dmas: Array of DMA header descriptions
+ * @tuning_meta: Tuning metadata header description
+ * @ctrl_meta: Control metadata header description
+ */
+struct singlenode_desc_norm {
+	__u8 dmas_enable[IMG_MAX_HW_DMAS];
+	struct header_desc_norm dmas[IMG_MAX_HW_DMAS];
+	struct header_desc_norm tuning_meta;
+	struct header_desc_norm ctrl_meta;
+};
+
 #endif
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.c
index 28a35a3226a2..a52f1cf93d47 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.c
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.c
@@ -83,6 +83,67 @@ int mtk_imgsys_pipe_next_job_id(struct mtk_imgsys_pipe *pipe)
 	return (global_job_id & 0x0000FFFF) | (pipe->desc->id << 16);
 }
 
+struct mtk_imgsys_request *
+mtk_imgsys_pipe_get_running_job(struct mtk_imgsys_pipe *pipe, int id)
+{
+	struct mtk_imgsys_request *req;
+	unsigned long flag;
+
+	spin_lock_irqsave(&pipe->running_job_lock, flag);
+	list_for_each_entry(req,
+			    &pipe->pipe_job_running_list, list) {
+		if (req->id == id) {
+			spin_unlock_irqrestore(&pipe->running_job_lock, flag);
+			return req;
+		}
+	}
+	spin_unlock_irqrestore(&pipe->running_job_lock, flag);
+
+	return NULL;
+}
+
+void mtk_imgsys_pipe_remove_job(struct mtk_imgsys_request *req)
+{
+	unsigned long flag;
+
+	spin_lock_irqsave(&req->imgsys_pipe->running_job_lock, flag);
+	list_del(&req->list);
+	req->imgsys_pipe->num_jobs--;
+	spin_unlock_irqrestore(&req->imgsys_pipe->running_job_lock, flag);
+
+	dev_dbg(req->imgsys_pipe->imgsys_dev->dev,
+		"%s:%s:req->id(%d),num of running jobs(%d) entry(%p)\n", __func__,
+		req->imgsys_pipe->desc->name, req->id,
+		req->imgsys_pipe->num_jobs, &req->list);
+}
+
+void mtk_imgsys_pipe_job_finish(struct mtk_imgsys_request *req,
+				enum vb2_buffer_state vbf_state)
+{
+	struct mtk_imgsys_pipe *pipe = req->imgsys_pipe;
+	int i;
+
+	if (req->req.state != MEDIA_REQUEST_STATE_QUEUED) {
+		dev_info(pipe->imgsys_dev->dev, "%s: req %d 0x%lx flushed in state(%d)", __func__,
+			 req->request_fd, (unsigned long)&req->req, req->req.state);
+		return;
+	}
+
+	for (i = 0; i < pipe->desc->total_queues; i++) {
+		struct mtk_imgsys_dev_buffer *dev_buf = req->buf_map[i];
+		struct mtk_imgsys_video_device *node;
+
+		if (!dev_buf)
+			continue;
+
+		node = mtk_imgsys_vbq_to_node(dev_buf->vbb.vb2_buf.vb2_queue);
+		spin_lock(&node->buf_list_lock);
+		list_del(&dev_buf->list);
+		spin_unlock(&node->buf_list_lock);
+		vb2_buffer_done(&dev_buf->vbb.vb2_buf, vbf_state);
+	}
+}
+
 void mtk_imgsys_pipe_debug_job(struct mtk_imgsys_pipe *pipe,
 			       struct mtk_imgsys_request *req)
 {
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.h
index b8c30cb32b97..effee4a3b616 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.h
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.h
@@ -25,6 +25,8 @@
 #include <media/videobuf2-v4l2.h>
 #include "mtk_imgsys-module_ops.h"
 #include "mtk_header_desc.h"
+#include "mtk-img-ipi.h"
+#include "mtk_imgsys-work_buf.h"
 
 #define MTK_IMGSYS_MEDIA_MODEL_NAME	"MTK-ISP-DIP-V4L2"
 
@@ -38,6 +40,31 @@
 #define MTK_IMGSYS_CAPTURE_MAX_WIDTH		5376U
 #define MTK_IMGSYS_CAPTURE_MAX_HEIGHT		4032U
 
+/**
+ * MTK_IMGSYS_JOB_TIMEOUT_MS - Defines the job timeout in milliseconds.
+ *
+ * This macro calculates the timeout for image system jobs based on the frame rate
+ * (30 frames per second) and the number of working buffers. The timeout is set to
+ * three times the duration of all working buffers.
+ */
+#define MTK_IMGSYS_JOB_TIMEOUT_MS	(1000 / 30 * IMGSYS_WORKING_BUF_NUM * 3)
+
+/**
+ * struct mtk_imgsys_hw_working_buf_list - Represents a list of hardware
+ * working buffers
+ *
+ * @list: List head for linking multiple buffer lists
+ * @lock: Spinlock to protect the list
+ *
+ * This structure represents a list of hardware working buffers used in the
+ * MediaTek Image System. It includes a list head for linking multiple buffer
+ * lists and a spinlock to protect the list from concurrent access.
+ */
+struct mtk_imgsys_hw_working_buf_list {
+	struct list_head list;
+	spinlock_t lock; /* protect the list of working buf */
+};
+
 /**
  * struct mtk_imgsys_dev_format - Device format for MediaTek Image System
  * @fmt: Pointer to the Image System format structure
@@ -274,6 +301,7 @@ struct mtk_imgsys_pipe {
  * @imgsys_pipe: Image system pipeline configuration structure.
  * @cust_pipes: Pointer to custom pipeline descriptors.
  * @modules: Pointer to image system module operations.
+ * @num_mods: Number of modules in the image system.
  * @clks: Array of clock bulk data for managing multiple clocks.
  * @num_clks: Number of clocks in the clock array.
  * @larbs: Array of device pointers for managing LARB (local arbiter).
@@ -281,9 +309,18 @@ struct mtk_imgsys_pipe {
  * @scp: Pointer to the SCP (System Control Processor) structure.
  * @rproc_handle: Handle for remote processor interface.
  * @smem_dev: Device structure for shared memory operations.
- * @num_mods: Number of modules in the image system.
+ * @working_bufs: Array of hardware working buffers.
+ * @free_working_bufs: List of free working buffers.
+ * @composer_wq: Workqueue for composing tasks in image processing.
+ * @runner_wq: Workqueue for running tasks in image processing.
+ * @gcecb_wq: Workqueue for handling GCE callback tasks.
+ * @work_pool: Pool of GCE callback work structures.
+ * @flushing_waitq: Wait queue for flushing operations.
+ * @num_composing: Atomic counter for tracking composing operations.
+ * @imgsys_enqueue_cnt: Atomic counter for enqueued image system requests.
  * @init_kref: Reference counter for initialization tracking.
  * @hw_op_lock: Mutex for serializing hardware operations.
+ * @sem: Semaphore to limit the maximum number of requests sent to SCP.
  * @stream_cnt: Counter for active streams, increased on stream on.
  */
 struct mtk_imgsys_dev {
@@ -298,6 +335,7 @@ struct mtk_imgsys_dev {
 	const struct mtk_imgsys_pipe_desc *cust_pipes;
 	/* Imgsys Moudles Information */
 	const struct module_ops *modules;
+	int num_mods;
 	/* Clock Information */
 	struct clk_bulk_data *clks;
 	int num_clks;
@@ -308,11 +346,22 @@ struct mtk_imgsys_dev {
 	struct mtk_scp *scp;
 	struct rproc *rproc_handle;
 	struct device *smem_dev;
-	/* Number of modules */
-	int num_mods;
+	/* Working Buffers */
+	struct mtk_imgsys_hw_working_buf *working_bufs;
+	struct mtk_imgsys_hw_working_buf_list free_working_bufs;
+	/* Workqueues for ImgSys */
+	struct workqueue_struct *composer_wq;
+	struct workqueue_struct *runner_wq;
+	/* GCE (Generic Command Engine) Callback Workqueue */
+	struct workqueue_struct *gcecb_wq;
+	struct gce_cb_work_pool *work_pool;
 	/* Synchronization and Flow Control */
+	wait_queue_head_t flushing_waitq;
+	atomic_t num_composing;
+	atomic_t imgsys_enqueue_cnt;
 	struct kref init_kref;
 	struct mutex hw_op_lock; /* Protect HW operations */
+	struct semaphore sem;
 	int stream_cnt;
 };
 
@@ -360,10 +409,74 @@ struct mtk_imgsys_request {
 	struct mtk_imgsys_dev_buffer **buf_map;
 	struct list_head list;
 	struct req_frameparam img_fparam;
+	struct work_struct composer_work;
+	struct work_struct runner_work;
+	struct mtk_imgsys_hw_working_buf *working_buf;
+	struct swfrm_info *swfrm_info;
 	atomic_t buf_count;
 	int request_fd;
 };
 
+/**
+ * struct swfrm_info - Information about software frame
+ * @req_sbuf_goft: GCE buffer offset
+ * @req_sbuf_kva: GCE buffer virtual address
+ * @swfrminfo_ridx: Ring index of the swfrminfo (referenced by SCP)
+ * @request_fd: Enqueued request file descriptor in V4L2 kernel framework
+ * @request_no: Request number from middleware
+ * @frame_no: Frame number from middleware
+ * @frm_owner: Frame owner identifier from middleware
+ * @fps: Frames per second
+ * @cb_frmcnt: Frame counter
+ * @total_taskcnt: Total task count
+ * @req_vaddr: Kernel request virtual address
+ * @sync_id: Synchronization identifier for camera/image synchronization
+ * @total_frmnum: Total frame number in the current request
+ * @user_info: Array of user information from SCP to kernel
+ * @is_earlycb: Indicates if the request is separated by early callback hint
+ * @earlycb_idx: Frame index for early callback
+ * @is_lastfrm: Indicates if the request is separated by last frame
+ * @group_id: Group identifier for selecting GCE thread
+ * @req: Pointer to mtk_imgsys_request
+ * @pipe: Pointer to pipe mtk_imgsys_pipe
+ * @fail_uinfo_idx: Failed index in user_info
+ * @hw_hang: Indicates if the current failure is caused by hardware hang
+ * @ndd_swfrm_info: Pointer to NDD (Normal data dump) software frame information
+ *
+ * This structure contains detailed information about a software frame,
+ * including various identifiers, addresses, and status flags.
+ */
+struct swfrm_info {
+	u32 req_sbuf_goft;
+	void *req_sbuf_kva;
+	int swfrminfo_ridx;
+	int request_fd;
+	int request_no;
+	int frame_no;
+	u64 frm_owner;
+	int fps;
+	int cb_frmcnt;
+	int total_taskcnt;
+	u64 req_vaddr;
+	int sync_id;
+	int total_frmnum;
+	struct img_swfrm_info user_info[TMAX];
+	u8 is_earlycb;
+	int earlycb_idx;
+	u8 is_lastfrm;
+	s8 group_id;
+	void *req;
+	void *pipe;
+	u32 fail_uinfo_idx;
+	s8 hw_hang;
+	void *ndd_swfrm_info;
+} __attribute((__packed__));
+static inline struct mtk_imgsys_pipe*
+mtk_imgsys_dev_get_pipe(struct mtk_imgsys_dev *imgsys_dev)
+{
+	return &imgsys_dev->imgsys_pipe;
+}
+
 static inline struct mtk_imgsys_video_device*
 mtk_imgsys_file_to_node(struct file *file)
 {
@@ -401,6 +514,18 @@ mtk_imgsys_media_req_to_imgsys_req(struct media_request *req)
 	return container_of(req, struct mtk_imgsys_request, req);
 }
 
+static inline struct mtk_imgsys_request*
+mtk_imgsys_composer_work_to_req(struct work_struct *composer_work)
+{
+	return container_of(composer_work, struct mtk_imgsys_request, composer_work);
+}
+
+static inline struct mtk_imgsys_request*
+mtk_imgsys_runner_work_to_req(struct work_struct *runner_work)
+{
+	return container_of(runner_work, struct mtk_imgsys_request, runner_work);
+}
+
 static inline int mtk_imgsys_buf_is_meta(u32 type)
 {
 	return type == V4L2_BUF_TYPE_META_CAPTURE ||
@@ -413,8 +538,16 @@ int mtk_imgsys_pipe_init(struct mtk_imgsys_dev *imgsys_dev,
 
 int mtk_imgsys_pipe_release(struct mtk_imgsys_pipe *pipe);
 
+struct mtk_imgsys_request *
+mtk_imgsys_pipe_get_running_job(struct mtk_imgsys_pipe *pipe, int id);
+
+void mtk_imgsys_pipe_remove_job(struct mtk_imgsys_request *req);
+
 int mtk_imgsys_pipe_next_job_id(struct mtk_imgsys_pipe *pipe);
 
+void mtk_imgsys_pipe_job_finish(struct mtk_imgsys_request *req,
+				enum vb2_buffer_state vbf_state);
+
 void mtk_imgsys_pipe_debug_job(struct mtk_imgsys_pipe *pipe,
 			       struct mtk_imgsys_request *req);
 
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-gce_work.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-gce_work.c
new file mode 100644
index 000000000000..ef86410e3d23
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-gce_work.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "mtk_imgsys-scp.h"
+#include "mtk_imgsys-gce_work.h"
+
+static void cmdq_cb_done_worker(struct work_struct *work)
+{
+	struct mtk_imgsys_pipe *pipe;
+	struct swfrm_info *gwfrm_info = NULL;
+	struct gce_cb_work *gwork;
+	struct img_sw_buffer swbuf_data = {0};
+
+	gwork = container_of(work, struct gce_cb_work, work);
+	gwfrm_info = gwork->req_sbuf_kva;
+
+	pipe = gwork->pipe;
+	if (!pipe->streaming)
+		return;
+
+	/* send to SCP after frame done & del node from list */
+	swbuf_data.offset = gwfrm_info->req_sbuf_goft;
+	imgsys_scp_send(pipe->imgsys_dev, IPI_IMGSYS_DEQUE_DONE_ID,
+			&swbuf_data, sizeof(struct img_sw_buffer),
+			gwork->reqfd, 1);
+
+	gce_cb_work_free(pipe->imgsys_dev->work_pool, gwork);
+}
+
+int gce_cb_work_pool_init(struct mtk_imgsys_dev *imgsys_dev)
+{
+	int i;
+	struct gce_cb_work_pool *work_pool;
+
+	work_pool = kmalloc(sizeof(*work_pool), GFP_KERNEL);
+	if (!work_pool)
+		return -ENOMEM;
+	imgsys_dev->work_pool = work_pool;
+
+	spin_lock_init(&work_pool->lock);
+	INIT_LIST_HEAD(&work_pool->free_list);
+
+	for (i = 0; i < MTK_IMGSYS_GCE_CB_MAX_WORK_ITEMS; i++) {
+		INIT_WORK(&work_pool->work_items[i].work, cmdq_cb_done_worker);
+		atomic_set(&work_pool->work_items[i].state, WORK_INIT);
+		work_pool->work_items[i].work_idx = i;
+		list_add_tail(&work_pool->work_items[i].list, &work_pool->free_list);
+	}
+	return 0;
+}
+
+struct gce_cb_work *gce_cb_work_allocate(struct gce_cb_work_pool *pool)
+{
+	struct gce_cb_work *gwork = NULL;
+
+	spin_lock(&pool->lock);
+	if (list_empty(&pool->free_list)) {
+		spin_unlock(&pool->lock);
+		return NULL;
+	}
+
+	gwork = list_first_entry(&pool->free_list, struct gce_cb_work, list);
+	list_del(&gwork->list);
+	spin_unlock(&pool->lock);
+
+	atomic_set(&gwork->state, WORK_ALLOC);
+
+	return gwork;
+}
+
+void gce_cb_work_free(struct gce_cb_work_pool *pool, struct gce_cb_work *gwork)
+{
+	atomic_set(&gwork->state, WORK_FREE);
+
+	spin_lock(&pool->lock);
+	list_add_tail(&gwork->list, &pool->free_list);
+	spin_unlock(&pool->lock);
+}
+
+void gce_cb_work_pool_release(struct mtk_imgsys_dev *imgsys_dev)
+{
+	kfree(imgsys_dev->work_pool);
+}
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-gce_work.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-gce_work.h
new file mode 100644
index 000000000000..ba80b952f38e
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-gce_work.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _MTK_IMGSYS_GCE_WORK_H_
+#define _MTK_IMGSYS_GCE_WORK_H_
+
+#define MTK_IMGSYS_GCE_CB_MAX_WORK_ITEMS	60
+
+enum mtk_imgsys_gce_cb_work_state {
+	WORK_INIT,
+	WORK_ALLOC,
+	WORK_COMPLETED,
+	WORK_FREE
+};
+
+struct gce_cb_work {
+	struct work_struct work;
+	atomic_t state;
+	u32 work_idx;
+	u32 reqfd;
+	void *req_sbuf_kva;
+	void *pipe;
+	struct list_head list;
+	wait_queue_head_t wait_queue;
+};
+
+struct gce_cb_work_pool {
+	struct gce_cb_work work_items[MTK_IMGSYS_GCE_CB_MAX_WORK_ITEMS];
+	struct list_head free_list;
+	spinlock_t lock; /* protect the free_list */
+};
+
+int gce_cb_work_pool_init(struct mtk_imgsys_dev *imgsys_dev);
+struct gce_cb_work *gce_cb_work_allocate(struct gce_cb_work_pool *pool);
+void gce_cb_work_free(struct gce_cb_work_pool *pool, struct gce_cb_work *gwork);
+void gce_cb_work_pool_release(struct mtk_imgsys_dev *imgsys_dev);
+
+#endif /* _MTK_IMGSYS_GCE_WORK_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
index 184f0e3a4d3b..36088a5bda8e 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
@@ -3,17 +3,261 @@
  * Copyright (c) 2021 MediaTek Inc.
  *
  * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *         Holmes Chiou <holmes.chiou at mediatek.com>
  *
  */
 
 #include <linux/pm_runtime.h>
 #include "mtk_imgsys-sys.h"
 #include "mtk_imgsys-dev.h"
+#include "mtk_imgsys-scp.h"
 #include "mtk_imgsys-cmdq.h"
+#include "mtk_imgsys-work_buf.h"
+#include "mtk_imgsys-gce_work.h"
+#include "mtk_header_desc.h"
+#include "mtk_imgsys_v4l2_vnode.h"
+
+#define FRAME_STATE_INIT		0
+#define FRAME_STATE_HW_TIMEOUT		1
+
+static void mtk_imgsys_notify(struct mtk_imgsys_request *req, uint64_t frm_owner)
+{
+	struct mtk_imgsys_dev *imgsys_dev = req->imgsys_pipe->imgsys_dev;
+	struct mtk_imgsys_pipe *pipe = req->imgsys_pipe;
+	struct req_frameparam *iparam = &req->img_fparam;
+	enum vb2_buffer_state vbf_state;
+
+	if (!mtk_imgsys_pipe_get_running_job(pipe, req->id))
+		goto out;
+
+	if (iparam->state != FRAME_STATE_HW_TIMEOUT)
+		vbf_state = VB2_BUF_STATE_DONE;
+	else
+		vbf_state = VB2_BUF_STATE_ERROR;
+
+	atomic_dec(&imgsys_dev->num_composing);
+
+	mtk_imgsys_hw_working_buf_free(imgsys_dev, req->working_buf);
+	req->working_buf = NULL;
+	mtk_imgsys_pipe_remove_job(req);
+	if (vbf_state == VB2_BUF_STATE_DONE)
+		mtk_imgsys_pipe_job_finish(req, vbf_state);
+
+	wake_up(&imgsys_dev->flushing_waitq);
+	dev_dbg(imgsys_dev->dev,
+		"%s:%s:(reqfd-%d) , frame_no(%d) frm_owner(%s) finished\n",
+		__func__, pipe->desc->name, req->request_fd, iparam->frame_no,
+		((char *)(&frm_owner)));
+
+out:
+	media_request_put(&req->req);
+}
+
+static void imgsys_cmdq_cb_func(struct imgsys_cmdq_cb_data data)
+{
+	struct mtk_imgsys_pipe *pipe;
+	struct mtk_imgsys_request *req;
+	struct mtk_imgsys_dev *imgsys_dev;
+	struct swfrm_info *swfrminfo_cb;
+	struct gce_cb_work *gwork;
+
+	swfrminfo_cb = data.data;
+	pipe = (struct mtk_imgsys_pipe *)swfrminfo_cb->pipe;
+	if (!pipe->streaming) {
+		pr_info("%s pipe already streamoff\n", __func__);
+		return;
+	}
+
+	req = (struct mtk_imgsys_request *)(swfrminfo_cb->req);
+	if (!req) {
+		pr_info("%s NULL request Address\n", __func__);
+		return;
+	}
+
+	imgsys_dev = req->imgsys_pipe->imgsys_dev;
+	dev_dbg(imgsys_dev->dev, "%s:(reqfd-%d)frame_no(%d) +", __func__,
+		req->request_fd,
+		req->img_fparam.frame_no);
+
+	if (swfrminfo_cb->hw_hang >= 0)
+		req->img_fparam.state = FRAME_STATE_HW_TIMEOUT;
+
+	mtk_imgsys_notify(req, swfrminfo_cb->frm_owner);
+
+	if (swfrminfo_cb->hw_hang < 0) {
+		gwork = gce_cb_work_allocate(imgsys_dev->work_pool);
+		if (!gwork)
+			return;
+
+		gwork->reqfd = swfrminfo_cb->request_fd;
+		gwork->req_sbuf_kva = swfrminfo_cb->req_sbuf_kva;
+		gwork->pipe = swfrminfo_cb->pipe;
+		init_waitqueue_head(&gwork->wait_queue);
+
+		queue_work(req->imgsys_pipe->imgsys_dev->gcecb_wq, &gwork->work);
+	}
+}
+
+static void imgsys_runner_func(struct work_struct *work)
+{
+	struct mtk_imgsys_request *req = mtk_imgsys_runner_work_to_req(work);
+	struct mtk_imgsys_dev *imgsys_dev = req->imgsys_pipe->imgsys_dev;
+	struct swfrm_info *frm_info;
+	int ret;
+
+	frm_info = req->swfrm_info;
+
+	ret = imgsys_cmdq_sendtask(imgsys_dev, frm_info, imgsys_cmdq_cb_func);
+	if (ret)
+		dev_info(imgsys_dev->dev,
+			 "%s: imgsys_cmdq_sendtask fail(%d)\n", __func__, ret);
+}
+
+/* processing IPI_IMGSYS_FRAME_ID, share data is struct img_sw_buffer*/
+static void imgsys_scp_handler(void *data, unsigned int len, void *priv)
+{
+	struct share_buf *scp_msg = (struct share_buf *)data;
+	struct mtk_imgsys_pipe *pipe;
+	struct mtk_imgsys_request *req;
+	struct mtk_imgsys_dev *imgsys_dev = (struct mtk_imgsys_dev *)priv;
+	struct img_sw_buffer *swbuf_data;
+	struct swfrm_info *swfrm_info;
+	int i = 0;
+	void *gce_virt;
+	int total_framenum = 0;
+
+	if (!data) {
+		WARN_ONCE(!data, "%s: failed due to NULL data\n", __func__);
+		return;
+	}
+
+	/* this function just handles id IPI_IMGSYS_FRAME_ID */
+	if (scp_msg->id != IPI_IMGSYS_FRAME_ID) {
+		dev_dbg(imgsys_dev->dev,
+			"%s: get invalid IPI ID(%d)\n", __func__, scp_msg->id);
+		return;
+	}
+
+	if (WARN_ONCE(scp_msg->len != sizeof(struct img_sw_buffer),
+		      "%s: len(%d) not match img_sw_buffer\n", __func__, len))
+		return;
+
+	swbuf_data = (struct img_sw_buffer *)scp_msg->share_data;
+	gce_virt = imgsys_scp_get_reserve_mem_virt(IMG_MEM_G_ID);
+	if (!gce_virt) {
+		pr_info("%s: invalid gce_virt(%p)\n",
+			__func__, gce_virt);
+		return;
+	}
+
+	swfrm_info = (struct swfrm_info *)(gce_virt + (swbuf_data->offset));
+	if ((int)swbuf_data->offset < 0 ||
+	    swbuf_data->offset > imgsys_scp_get_reserve_mem_size(IMG_MEM_G_ID)) {
+		pr_info("%s: invalid swbuf_data->offset(%d), max(%llu)\n",
+			__func__, swbuf_data->offset,
+			(u64)imgsys_scp_get_reserve_mem_size(IMG_MEM_G_ID));
+		return;
+	}
+
+	swfrm_info->req_sbuf_goft = swbuf_data->offset;
+	swfrm_info->req_sbuf_kva = gce_virt + (swbuf_data->offset);
+
+	pipe = mtk_imgsys_dev_get_pipe(imgsys_dev);
+	if (!pipe) {
+		dev_info(imgsys_dev->dev,
+			 "%s: get invalid img_ipi_frameparam from firmware\n",
+			 __func__);
+		return;
+	}
+
+	req = (struct mtk_imgsys_request *)(uintptr_t)swfrm_info->req_vaddr;
+	if (!req) {
+		WARN_ONCE(!req, "%s: frame_no(%d) is lost\n", __func__, req->id);
+		return;
+	}
+
+	if (!req->working_buf) {
+		dev_dbg(imgsys_dev->dev,
+			"%s: (reqfd-%d) composing\n",
+			__func__, req->request_fd);
+	}
+
+	swfrm_info->req = (void *)req;
+	swfrm_info->pipe = (void *)pipe;
+	swfrm_info->cb_frmcnt = 0;
+	swfrm_info->total_taskcnt = 0;
+	swfrm_info->hw_hang = -1;
+	total_framenum = swfrm_info->total_frmnum;
+
+	if (total_framenum < 0 || total_framenum > TMAX) {
+		dev_info(imgsys_dev->dev,
+			 "%s:unexpected total_framenum (%d -> %d), MAX (%d/%d)\n",
+			 __func__, swfrm_info->total_frmnum,
+			 total_framenum,
+			 TMAX, TMAX);
+		return;
+	}
+
+	for (i = 0 ; i < total_framenum ; i++) {
+		swfrm_info->user_info[i].g_swbuf =
+			gce_virt + (swfrm_info->user_info[i].sw_goft);
+	}
+
+	req->swfrm_info = swfrm_info;
+
+	up(&imgsys_dev->sem);
+
+	INIT_WORK(&req->runner_work, imgsys_runner_func);
+	queue_work(req->imgsys_pipe->imgsys_dev->runner_wq,
+		   &req->runner_work);
+}
+
+static int mtk_imgsys_hw_flush_pipe_jobs(struct mtk_imgsys_pipe *pipe)
+{
+	struct mtk_imgsys_request *req;
+	struct list_head job_list = LIST_HEAD_INIT(job_list);
+	unsigned long flag;
+	int num;
+	int ret;
+
+	spin_lock_irqsave(&pipe->running_job_lock, flag);
+	list_splice_init(&pipe->pipe_job_running_list, &job_list);
+	pipe->num_jobs = 0;
+	spin_unlock_irqrestore(&pipe->running_job_lock, flag);
+
+	num = atomic_read(&pipe->imgsys_dev->num_composing);
+	ret = wait_event_timeout(pipe->imgsys_dev->flushing_waitq, !(num),
+				 msecs_to_jiffies(MTK_IMGSYS_JOB_TIMEOUT_MS));
+	if (!ret && num) {
+		dev_info(pipe->imgsys_dev->dev,
+			 "flushing is aborted, num(%d)\n", num);
+		return -EINVAL;
+	}
+
+	list_for_each_entry(req, &job_list, list)
+		mtk_imgsys_pipe_job_finish(req, VB2_BUF_STATE_ERROR);
+
+	dev_dbg(pipe->imgsys_dev->dev,
+		"%s: wakeup num(%d)\n", __func__, num);
+	return 0;
+}
+
+static void module_uninit(struct kref *kref)
+{
+	struct mtk_imgsys_dev *imgsys_dev;
+	int i;
+
+	imgsys_dev = container_of(kref, struct mtk_imgsys_dev, init_kref);
+
+	for (i = 0; i < (imgsys_dev->num_mods); i++)
+		if (imgsys_dev->modules[i].uninit)
+			imgsys_dev->modules[i].uninit(imgsys_dev);
+}
 
 static int mtk_imgsys_hw_connect(struct mtk_imgsys_dev *imgsys_dev)
 {
 	int ret, i;
+	struct img_init_info info;
 
 	ret = pm_runtime_get_sync(imgsys_dev->dev);
 	if (ret < 0) {
@@ -23,38 +267,228 @@ static int mtk_imgsys_hw_connect(struct mtk_imgsys_dev *imgsys_dev)
 
 	/* Set default value for hardware modules */
 	for (i = 0; i < (imgsys_dev->num_mods); i++)
-		imgsys_dev->modules[i].init(imgsys_dev);
+		if (imgsys_dev->modules[i].init)
+			imgsys_dev->modules[i].init(imgsys_dev);
 
 	kref_init(&imgsys_dev->init_kref);
 
+	ret = imgsys_scp_alloc_reserve_mem(imgsys_dev);
+	if (ret) {
+		dev_err(imgsys_dev->dev, "%s: imgsys_scp_alloc_reserve_mem failed %d\n",
+			__func__, ret);
+		return -EBUSY;
+	}
+
+	/* IMGSYS HW INIT */
+	memset(&info, 0, sizeof(info));
+	info.header_version = HEADER_VER;
+	info.frameparam_size = sizeof(struct img_ipi_frameparam);
+
+	imgsys_scp_get_reserve_mem_info(&info);
+
+	imgsys_scp_init(imgsys_dev, imgsys_scp_handler);
+
+	ret = imgsys_scp_send(imgsys_dev, IPI_IMGSYS_INIT_ID,
+			      (void *)&info, sizeof(info), 0, 1);
+
+	if (ret) {
+		dev_err(imgsys_dev->dev, "%s: send IPI_IMGSYS_INIT_ID failed %d\n",
+			__func__, ret);
+		return -EBUSY;
+	}
+
 	/* calling cmdq stream on */
 	imgsys_cmdq_streamon(imgsys_dev);
+
 	return 0;
 }
 
-static void module_uninit(struct kref *kref)
+static void mtk_imgsys_hw_disconnect(struct mtk_imgsys_dev *imgsys_dev)
 {
-	struct mtk_imgsys_dev *imgsys_dev;
+	int ret;
+	struct img_init_info info = {0};
+
+	imgsys_scp_send(imgsys_dev, IPI_IMGSYS_DEINIT_ID,
+			(void *)&info, sizeof(info), 0, 1);
+
+	imgsys_scp_deinit(imgsys_dev);
+	/* calling cmdq stream off */
+	imgsys_cmdq_streamoff(imgsys_dev);
+
+	/* RELEASE IMGSYS WORKING BUFFER FIRST */
+	ret = imgsys_scp_free_reserve_mem(imgsys_dev);
+	if (ret) {
+		dev_info(imgsys_dev->dev,
+			 "%s: imgsys_scp_free_reserve_mem failed(%d)\n",
+			 __func__, ret);
+	}
+
+	pm_runtime_put_sync(imgsys_dev->dev);
+
+	kref_put(&imgsys_dev->init_kref, module_uninit);
+}
+
+static void imgsys_fill_img_buf(struct mtk_imgsys_dev_buffer *dev_buf,
+				struct header_desc_norm *desc_norm,
+				struct mtk_imgsys_request *req)
+{
+	struct frameparams *buf_info = &desc_norm->fparams;
 	int i;
 
-	imgsys_dev = container_of(kref, struct mtk_imgsys_dev, init_kref);
+	desc_norm->fparams_num = 1;
 
-	for (i = 0; i < (imgsys_dev->num_mods); i++)
-		if (imgsys_dev->modules[i].uninit)
-			imgsys_dev->modules[i].uninit(imgsys_dev);
+	buf_info->buf.num_planes = dev_buf->fmt.fmt.pix_mp.num_planes;
+	buf_info->fmt.width = dev_buf->fmt.fmt.pix_mp.width;
+	buf_info->fmt.height = dev_buf->fmt.fmt.pix_mp.height;
+	buf_info->fmt.pixelformat = dev_buf->fmt.fmt.pix_mp.pixelformat;
+	buf_info->crop = dev_buf->crop;
+	buf_info->rotation = dev_buf->rotation;
+	buf_info->hflip = dev_buf->hflip;
+	buf_info->vflip = dev_buf->vflip;
+	buf_info->resizeratio = dev_buf->resize_ratio;
+
+	for (i = 0; i < buf_info->buf.num_planes; i++) {
+		buf_info->buf.planes[i].m.dma_buf.offset =
+			dev_buf->vbb.planes[i].data_offset;
+		buf_info->buf.planes[i].isp_addr = dev_buf->isp_daddr[i];
+		buf_info->buf.planes[i].size = dev_buf->vbb.vb2_buf.planes[i].length;
+		buf_info->fmt.plane_fmt[i].sizeimage =
+			dev_buf->vbb.vb2_buf.planes[i].min_length;
+		buf_info->fmt.plane_fmt[i].bytesperline =
+			dev_buf->fmt.fmt.pix_mp.plane_fmt[i].bytesperline;
+	}
 }
 
-static void mtk_imgsys_hw_disconnect(struct mtk_imgsys_dev *imgsys_dev)
+static void imgsys_fill_meta_buf(struct mtk_imgsys_dev_buffer *dev_buf,
+				 struct header_desc_norm *desc_norm,
+				 struct mtk_imgsys_request *req)
 {
-	/* calling cmdq stream off */
-	imgsys_cmdq_streamoff(imgsys_dev);
-	kref_put(&imgsys_dev->init_kref, module_uninit);
+	struct frameparams *buf_info = &desc_norm->fparams;
+
+	memset(&buf_info->buf, 0, sizeof(buf_info->buf));
+
+	desc_norm->fparams_num = 1;
+
+	buf_info->buf.num_planes = 1;
+
+	buf_info->fmt.width = dev_buf->fmt.fmt.meta.buffersize;
+	buf_info->fmt.height = 1;
+	buf_info->fmt.pixelformat = dev_buf->fmt.fmt.meta.dataformat;
+	buf_info->fmt.plane_fmt[0].sizeimage = dev_buf->fmt.fmt.meta.buffersize;
+	buf_info->fmt.plane_fmt[0].bytesperline = dev_buf->fmt.fmt.meta.buffersize;
+	buf_info->buf.planes[0].isp_addr = dev_buf->isp_daddr[0];
+	buf_info->buf.planes[0].size = dev_buf->vbb.vb2_buf.planes[0].length;
+	buf_info->buf.planes[0].m.dma_buf.phyaddr = dev_buf->scp_daddr[0];
+}
+
+static void imgsys_fill_buf_info(int idx, struct mtk_imgsys_dev_buffer *dev_buf,
+				 struct singlenode_desc_norm *sd_norm,
+				 struct mtk_imgsys_request *req)
+{
+	if (!dev_buf)
+		return;
+
+	if (idx < 0 || idx >= IMG_MAX_HW_DMAS)
+		return;
+
+	sd_norm->dmas_enable[idx] = 1;
+
+	switch (idx) {
+	case MTK_IMGSYS_VIDEO_NODE_ID_TUNING_OUT:
+		imgsys_fill_meta_buf(dev_buf, &sd_norm->tuning_meta, req);
+		break;
+	case MTK_IMGSYS_VIDEO_NODE_ID_CTRLMETA_OUT:
+		imgsys_fill_meta_buf(dev_buf, &sd_norm->ctrl_meta, req);
+		break;
+	case MTK_IMGSYS_VIDEO_NODE_ID_METAI_OUT:
+	case MTK_IMGSYS_VIDEO_NODE_ID_FEO_CAPTURE:
+	case MTK_IMGSYS_VIDEO_NODE_ID_IMGSTATO_CAPTURE:
+		imgsys_fill_meta_buf(dev_buf, &sd_norm->dmas[idx], req);
+		break;
+	default:
+		imgsys_fill_img_buf(dev_buf, &sd_norm->dmas[idx], req);
+		break;
+	}
+}
+
+static void imgsys_fill_singledev_buf(struct mtk_imgsys_request *req)
+{
+	struct mtk_imgsys_hw_working_buf *buf = req->working_buf;
+	int i;
+
+	if (!buf)
+		return;
+
+	memset(buf->sd_norm, 0, sizeof(*buf->sd_norm));
+	for (i = 0; i < req->imgsys_pipe->desc->total_queues; i++)
+		imgsys_fill_buf_info(i, req->buf_map[i], buf->sd_norm, req);
+}
+
+static void imgsys_composer_workfunc(struct work_struct *work)
+{
+	struct mtk_imgsys_request *req = mtk_imgsys_composer_work_to_req(work);
+	struct mtk_imgsys_dev *imgsys_dev = req->imgsys_pipe->imgsys_dev;
+	struct img_ipi_param ipi_param;
+	int ret;
+
+	imgsys_fill_singledev_buf(req);
+
+	dev_dbg(imgsys_dev->dev,
+		"%s:(reqfd-%d) to send frame_no(%d)\n",
+		__func__, req->request_fd,
+		req->img_fparam.frame_no);
+	media_request_get(&req->req);
+
+	if (down_interruptible(&imgsys_dev->sem))
+		return;
+
+	ipi_param.req_addr_va = (u64)(uintptr_t)req;
+	ipi_param.frm_param.offset = 0;
+	ipi_param.frm_param.scp_addr = req->working_buf->scp_daddr;
+
+	mutex_lock(&imgsys_dev->hw_op_lock);
+	atomic_inc(&imgsys_dev->num_composing);
+
+	ret = imgsys_scp_send(imgsys_dev, IPI_IMGSYS_FRAME_ID,
+			      &ipi_param, sizeof(ipi_param),
+			      req->request_fd, 0);
+
+	if (ret) {
+		dev_info(imgsys_dev->dev,
+			 "frame_no(%d) send SCP_IPI_DIP_FRAME failed %d\n",
+			 req->img_fparam.frame_no, ret);
+		mtk_imgsys_pipe_remove_job(req);
+		mtk_imgsys_hw_working_buf_free(imgsys_dev, req->working_buf);
+		req->working_buf = NULL;
+		mtk_imgsys_pipe_job_finish(req, VB2_BUF_STATE_ERROR);
+		wake_up(&imgsys_dev->flushing_waitq);
+	}
+	mutex_unlock(&imgsys_dev->hw_op_lock);
+
+	dev_dbg(imgsys_dev->dev, "%s:(reqfd-%d) sent\n", __func__,
+		req->request_fd);
 }
 
 void mtk_imgsys_hw_enqueue(struct mtk_imgsys_dev *imgsys_dev,
 			   struct mtk_imgsys_request *req)
 {
-	/* Function implementation will be provided in subsequent patches */
+	struct req_frameparam *frameparam = &req->img_fparam;
+
+	req->working_buf = mtk_imgsys_hw_working_buf_alloc(imgsys_dev);
+	if (!req->working_buf) {
+		dev_info(imgsys_dev->dev,
+			 "%s:req(%p): no free working buffer available\n",
+			 req->imgsys_pipe->desc->name, req);
+		return;
+	}
+
+	frameparam->state = FRAME_STATE_INIT;
+	frameparam->frame_no =
+			atomic_inc_return(&imgsys_dev->imgsys_enqueue_cnt);
+
+	INIT_WORK(&req->composer_work, imgsys_composer_workfunc);
+	queue_work(req->imgsys_pipe->imgsys_dev->composer_wq,
+		   &req->composer_work);
 }
 
 int mtk_imgsys_hw_streamon(struct mtk_imgsys_pipe *pipe)
@@ -72,10 +506,13 @@ int mtk_imgsys_hw_streamon(struct mtk_imgsys_pipe *pipe)
 			mutex_unlock(&imgsys_dev->hw_op_lock);
 			return ret;
 		}
+		INIT_LIST_HEAD(&pipe->pipe_job_running_list);
 	}
 	imgsys_dev->stream_cnt++;
+	atomic_set(&imgsys_dev->num_composing, 0);
 	mutex_unlock(&imgsys_dev->hw_op_lock);
 
+	pipe->streaming = 1;
 	dev_dbg(pipe->imgsys_dev->dev,
 		"%s:%s: stream on, id(%d), stream cnt(%d)\n",
 		__func__, pipe->desc->name, pipe->desc->id, imgsys_dev->stream_cnt);
@@ -86,11 +523,18 @@ int mtk_imgsys_hw_streamon(struct mtk_imgsys_pipe *pipe)
 int mtk_imgsys_hw_streamoff(struct mtk_imgsys_pipe *pipe)
 {
 	struct mtk_imgsys_dev *imgsys_dev = pipe->imgsys_dev;
+	int ret;
 
 	dev_dbg(pipe->imgsys_dev->dev,
 		"%s:%s: stream off, id(%d), stream cnt(%d)\n",
 		__func__, pipe->desc->name, pipe->desc->id, imgsys_dev->stream_cnt);
 
+	pipe->streaming = 0;
+
+	ret = mtk_imgsys_hw_flush_pipe_jobs(pipe);
+	if (ret)
+		return ret;
+
 	mutex_lock(&imgsys_dev->hw_op_lock);
 	imgsys_dev->stream_cnt--;
 	if (!imgsys_dev->stream_cnt)
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
index e25f17b98649..ea2ce03c2619 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
@@ -5,6 +5,7 @@
  * Author: Frederic Chen <frederic.chen at mediatek.com>
  *
  */
+
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
 #include <linux/of_device.h>
@@ -12,6 +13,7 @@
 #include <linux/pm_runtime.h>
 #include <linux/dma-mapping.h>
 #include <linux/vmalloc.h>
+#include <linux/remoteproc/mtk_scp.h>
 #include <linux/videodev2.h>
 #include <media/videobuf2-dma-contig.h>
 #include <media/v4l2-ioctl.h>
@@ -29,6 +31,9 @@
 #include "mtk_imgsys_v4l2_vnode.h"
 #include "mtk_imgsys-dev.h"
 #include "mtk_imgsys-sys.h"
+#include "mtk_imgsys-cmdq.h"
+#include "mtk_imgsys-work_buf.h"
+#include "mtk_imgsys-gce_work.h"
 
 #define IMGSYS_MAX_BUFFERS	256
 #define IMGSYS_SUSPEND_TIME 3000 /* ms */
@@ -1467,6 +1472,77 @@ static void mtk_imgsys_dev_v4l2_release(struct mtk_imgsys_dev *imgsys_dev)
 	mtk_imgsys_dev_media_unregister(imgsys_dev);
 }
 
+static int mtk_imgsys_res_init(struct platform_device *pdev,
+			       struct mtk_imgsys_dev *imgsys_dev)
+{
+	int ret;
+
+	imgsys_dev->gcecb_wq =
+		alloc_ordered_workqueue("%s",
+					__WQ_LEGACY | WQ_MEM_RECLAIM |
+					WQ_FREEZABLE,
+					"imgsys_mdp_callback");
+	if (!imgsys_dev->gcecb_wq) {
+		dev_err(imgsys_dev->dev,
+			"%s: unable to alloc mdpcb workqueue\n", __func__);
+		return -ENOMEM;
+	}
+
+	imgsys_dev->composer_wq =
+		alloc_ordered_workqueue("%s",
+					__WQ_LEGACY | WQ_MEM_RECLAIM |
+					WQ_FREEZABLE | WQ_HIGHPRI,
+					"imgsys_composer");
+	if (!imgsys_dev->composer_wq) {
+		dev_err(imgsys_dev->dev,
+			"%s: unable to alloc composer workqueue\n", __func__);
+		ret = -ENOMEM;
+		goto destroy_gcecb_wq;
+	}
+
+	imgsys_dev->runner_wq =
+		alloc_ordered_workqueue("%s",
+					__WQ_LEGACY | WQ_MEM_RECLAIM |
+					WQ_FREEZABLE | WQ_HIGHPRI,
+					"imgsys_runner");
+	if (!imgsys_dev->runner_wq) {
+		dev_err(imgsys_dev->dev,
+			"%s: unable to alloc runner workqueue\n", __func__);
+		ret = -ENOMEM;
+		goto destroy_composer_wq;
+	}
+
+	init_waitqueue_head(&imgsys_dev->flushing_waitq);
+
+	return 0;
+
+destroy_composer_wq:
+	destroy_workqueue(imgsys_dev->composer_wq);
+
+destroy_gcecb_wq:
+	destroy_workqueue(imgsys_dev->gcecb_wq);
+
+	return ret;
+}
+
+static void mtk_imgsys_res_release(struct mtk_imgsys_dev *imgsys_dev)
+{
+	flush_workqueue(imgsys_dev->gcecb_wq);
+	destroy_workqueue(imgsys_dev->gcecb_wq);
+	imgsys_dev->gcecb_wq = NULL;
+
+	flush_workqueue(imgsys_dev->composer_wq);
+	destroy_workqueue(imgsys_dev->composer_wq);
+	imgsys_dev->composer_wq = NULL;
+
+	flush_workqueue(imgsys_dev->runner_wq);
+	destroy_workqueue(imgsys_dev->runner_wq);
+	imgsys_dev->runner_wq = NULL;
+
+	atomic_set(&imgsys_dev->num_composing, 0);
+	atomic_set(&imgsys_dev->imgsys_enqueue_cnt, 0);
+}
+
 static int mtk_imgsys_of_rproc(struct mtk_imgsys_dev *imgsys,
 			       struct platform_device *pdev)
 {
@@ -1519,6 +1595,8 @@ static int mtk_imgsys_probe(struct platform_device *pdev)
 	imgsys_dev->num_mods = data->mod_num;
 	imgsys_dev->stream_cnt = 0;
 	mutex_init(&imgsys_dev->hw_op_lock);
+	atomic_set(&imgsys_dev->imgsys_enqueue_cnt, 0);
+	atomic_set(&imgsys_dev->num_composing, 0);
 
 	/* Get Clocks */
 	imgsys_dev->clks = data->clks;
@@ -1592,6 +1670,33 @@ static int mtk_imgsys_probe(struct platform_device *pdev)
 		goto err_free_larb_alloc;
 	}
 
+	/* Initializing resource for ImgSys */
+	ret = mtk_imgsys_res_init(pdev, imgsys_dev);
+	if (ret) {
+		dev_info(imgsys_dev->dev,
+			 "%s: mtk_imgsys_res_init failed(%d)\n", __func__, ret);
+
+		ret = -EBUSY;
+		goto err_release_deinit_v4l2;
+	}
+
+	ret = mtk_imgsys_hw_working_buf_pool_init(imgsys_dev);
+	if (ret) {
+		dev_info(&pdev->dev, "working buffer init failed(%d)\n", ret);
+		goto err_release_deinit_v4l2;
+	}
+
+	/* Initializing resource for CMDQ driver */
+	imgsys_cmdq_init(imgsys_dev);
+
+	sema_init(&imgsys_dev->sem, MTK_IMGSYS_GCE_CB_MAX_WORK_ITEMS);
+
+	ret = gce_cb_work_pool_init(imgsys_dev);
+	if (ret) {
+		dev_info(&pdev->dev, "gce callback work pool init failed(%d)\n", ret);
+		goto err_release_working_buf_pool;
+	}
+
 	/* Enable power*/
 	pm_runtime_set_autosuspend_delay(&pdev->dev, IMGSYS_SUSPEND_TIME);
 	pm_runtime_use_autosuspend(&pdev->dev);
@@ -1600,11 +1705,15 @@ static int mtk_imgsys_probe(struct platform_device *pdev)
 	ret = platform_driver_register(&mtk_imgsys_larb_driver);
 	if (ret) {
 		dev_info(imgsys_dev->dev, "register mtk_imgsys_larb_driver fail\n");
-		goto err_release_deinit_v4l2;
+		goto err_free_gce_cb_work_pool_alloc;
 	}
 
 	return 0;
 
+err_free_gce_cb_work_pool_alloc:
+	gce_cb_work_pool_release(imgsys_dev);
+err_release_working_buf_pool:
+	mtk_imgsys_hw_working_buf_pool_release(imgsys_dev);
 err_release_deinit_v4l2:
 	mtk_imgsys_dev_v4l2_release(imgsys_dev);
 err_free_larb_alloc:
@@ -1618,17 +1727,32 @@ static void mtk_imgsys_remove(struct platform_device *pdev)
 {
 	struct mtk_imgsys_dev *imgsys_dev = dev_get_drvdata(&pdev->dev);
 
+	mtk_imgsys_res_release(imgsys_dev);
 	pm_runtime_disable(&pdev->dev);
 	platform_driver_unregister(&mtk_imgsys_larb_driver);
 	mtk_imgsys_dev_v4l2_release(imgsys_dev);
+	mtk_imgsys_hw_working_buf_pool_release(imgsys_dev);
+	gce_cb_work_pool_release(imgsys_dev);
 	mutex_destroy(&imgsys_dev->hw_op_lock);
+	imgsys_cmdq_release(imgsys_dev);
 	devm_kfree(&pdev->dev, imgsys_dev->larbs);
 	devm_kfree(&pdev->dev, imgsys_dev);
 }
 
 static int __maybe_unused mtk_imgsys_pm_suspend(struct device *dev)
 {
-	int ret;
+	struct mtk_imgsys_dev *imgsys_dev = dev_get_drvdata(dev);
+	int ret, num;
+
+	num = atomic_read(&imgsys_dev->num_composing);
+	ret = wait_event_timeout(imgsys_dev->flushing_waitq, !(num),
+				 msecs_to_jiffies(MTK_IMGSYS_JOB_TIMEOUT_MS));
+	if (!ret && num) {
+		dev_info(dev, "%s: flushing SCP job timeout, num(%d)\n",
+			 __func__, num);
+
+		return -EBUSY;
+	}
 
 	if (pm_runtime_suspended(dev)) {
 		dev_info(dev, "%s: pm_runtime_suspended is true, no action\n",
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-work_buf.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-work_buf.c
new file mode 100644
index 000000000000..5f220bbe8f3f
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-work_buf.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *         Holmes Chiou <holmes.chiou at mediatek.com>
+ *
+ */
+
+#include "mtk_imgsys-work_buf.h"
+
+int mtk_imgsys_hw_working_buf_pool_init(struct mtk_imgsys_dev *imgsys_dev)
+{
+	struct mtk_imgsys_hw_working_buf *buf;
+	void *sd;
+	dma_addr_t scp_addr, isp_daddr;
+	size_t size = sizeof(struct singlenode_desc_norm);
+	int i;
+
+	if (imgsys_dev->working_bufs)
+		return 0;
+
+	INIT_LIST_HEAD(&imgsys_dev->free_working_bufs.list);
+	spin_lock_init(&imgsys_dev->free_working_bufs.lock);
+
+	imgsys_dev->working_bufs = kmalloc_array(IMGSYS_WORKING_BUF_NUM, sizeof(*buf), GFP_KERNEL);
+	if (!imgsys_dev->working_bufs)
+		return -ENOMEM;
+
+	sd = dma_alloc_coherent(imgsys_dev->smem_dev,
+				size * IMGSYS_WORKING_BUF_NUM,
+				&scp_addr, GFP_KERNEL);
+	if (!sd)
+		goto err_alloc;
+
+	isp_daddr = dma_map_resource(imgsys_dev->dev,
+				     scp_addr,
+				     size * IMGSYS_WORKING_BUF_NUM,
+				     DMA_TO_DEVICE, 0);
+	if (!isp_daddr)
+		goto err_map;
+
+	for (i = 0; i < IMGSYS_WORKING_BUF_NUM; i++) {
+		buf = &imgsys_dev->working_bufs[i];
+
+		buf->sd_norm = sd;
+		buf->isp_daddr = isp_daddr;
+		buf->scp_daddr = scp_addr;
+
+		sd += size;
+		isp_daddr += size;
+		scp_addr += size;
+
+		list_add_tail(&buf->list,
+			      &imgsys_dev->free_working_bufs.list);
+	}
+
+	return 0;
+
+err_map:
+	dma_free_coherent(imgsys_dev->dev,
+			  sizeof(struct singlenode_desc_norm),
+			  sd, scp_addr);
+err_alloc:
+	kfree(imgsys_dev->working_bufs);
+
+	return -ENOMEM;
+}
+
+struct mtk_imgsys_hw_working_buf*
+mtk_imgsys_hw_working_buf_alloc(struct mtk_imgsys_dev *imgsys_dev)
+{
+	struct mtk_imgsys_hw_working_buf *working_buf;
+
+	spin_lock(&imgsys_dev->free_working_bufs.lock);
+	if (list_empty(&imgsys_dev->free_working_bufs.list)) {
+		spin_unlock(&imgsys_dev->free_working_bufs.lock);
+		return NULL;
+	}
+
+	working_buf = list_first_entry(&imgsys_dev->free_working_bufs.list,
+				       struct mtk_imgsys_hw_working_buf,
+				       list);
+	list_del(&working_buf->list);
+	spin_unlock(&imgsys_dev->free_working_bufs.lock);
+
+	return working_buf;
+}
+
+void mtk_imgsys_hw_working_buf_free(struct mtk_imgsys_dev *imgsys_dev,
+				    struct mtk_imgsys_hw_working_buf *working_buf)
+{
+	if (!working_buf)
+		return;
+
+	spin_lock(&imgsys_dev->free_working_bufs.lock);
+	list_add_tail(&working_buf->list,
+		      &imgsys_dev->free_working_bufs.list);
+	spin_unlock(&imgsys_dev->free_working_bufs.lock);
+}
+
+void mtk_imgsys_hw_working_buf_pool_release(struct mtk_imgsys_dev *imgsys_dev)
+{
+	struct mtk_imgsys_hw_working_buf *buf = &imgsys_dev->working_bufs[0];
+
+	dma_unmap_resource(imgsys_dev->dev, buf->isp_daddr,
+			   sizeof(struct singlenode_desc_norm) * IMGSYS_WORKING_BUF_NUM,
+			   DMA_TO_DEVICE, 0);
+	dma_free_coherent(imgsys_dev->dev,
+			  sizeof(struct singlenode_desc_norm) * IMGSYS_WORKING_BUF_NUM,
+			  buf->sd_norm, buf->scp_daddr);
+	kfree(imgsys_dev->working_bufs);
+}
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-work_buf.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-work_buf.h
new file mode 100644
index 000000000000..d54b02e6dfa8
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-work_buf.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *         Holmes Chiou <holmes.chiou at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_IMGSYS_WORK_BUF_H_
+#define _MTK_IMGSYS_WORK_BUF_H_
+
+#include <linux/clk.h>
+#include <linux/dma-buf.h>
+#include <linux/scatterlist.h>
+#include "mtk_header_desc.h"
+#include "mtk_imgsys-dev.h"
+
+#define IMGSYS_WORKING_BUF_NUM		32
+
+/**
+ * struct mtk_imgsys_hw_working_buf - Represents a hardware working buffer
+ * @sd_norm: Pointer to the single node descriptor normalized structure
+ * @dbuf: Pointer to the DMA buffer
+ * @attach: Pointer to the DMA buffer attachment
+ * @sgt: Pointer to the scatter-gather table
+ * @scp_daddr: Physical address for SCP (System Control Processor)
+ * @isp_daddr: Virtual address for ISP (Image Signal Processor)
+ * @list: List head for linking multiple buffers
+ *
+ * This structure represents a hardware working buffer used in the MediaTek
+ * Image System. It includes pointers to various buffer-related structures
+ * and addresses, as well as a list head for linking multiple buffers.
+ */
+struct mtk_imgsys_hw_working_buf {
+	struct singlenode_desc_norm *sd_norm;
+	struct dma_buf *dbuf;
+	struct dma_buf_attachment *attach;
+	struct sg_table *sgt;
+	dma_addr_t scp_daddr;
+	dma_addr_t isp_daddr;
+	struct list_head list;
+};
+
+int mtk_imgsys_hw_working_buf_pool_init(struct mtk_imgsys_dev *imgsys_dev);
+
+struct mtk_imgsys_hw_working_buf*
+mtk_imgsys_hw_working_buf_alloc(struct mtk_imgsys_dev *imgsys_dev);
+
+void mtk_imgsys_hw_working_buf_free(struct mtk_imgsys_dev *imgsys_dev,
+				    struct mtk_imgsys_hw_working_buf *working_buf);
+
+void mtk_imgsys_hw_working_buf_pool_release(struct mtk_imgsys_dev *imgsys_dev);
+
+#endif /* _MTK_IMGSYS_WORK_BUF_H_ */
-- 
2.45.2



From olivia.wen at mediatek.com  Sat May 24 04:50:02 2025
From: olivia.wen at mediatek.com (Olivia Wen)
Date: Sat, 24 May 2025 19:50:02 +0800
Subject: [PATCH v1 10/10] media: mediatek: isp: Add normal data dump flow
In-Reply-To: <20250524115144.3832748-1-olivia.wen@mediatek.com>
References: <20250524115144.3832748-1-olivia.wen@mediatek.com>
Message-ID: <20250524115144.3832748-11-olivia.wen@mediatek.com>

The ImgSys driver is implemented as a series of patches, with this patch
focusing on the  normal data dump flow. It is for debugging purposes
within the MediaTek Image System (ImgSys) driver. The data dump
functionality is essential for diagnosing issues, tracking the flow of
data, and ensuring the proper operation of image processing tasks.

Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
---
 .../mediatek/isp/isp_7x/imgsys/Makefile       |   2 +
 .../isp_7x/imgsys/modules/mtk_imgsys-dip.c    |  47 +++
 .../isp_7x/imgsys/modules/mtk_imgsys-dip.h    |   3 +
 .../isp/isp_7x/imgsys/modules/mtk_imgsys-me.c |  65 ++++
 .../isp/isp_7x/imgsys/modules/mtk_imgsys-me.h |  30 ++
 .../isp_7x/imgsys/modules/mtk_imgsys-pqdip.c  |  52 +++
 .../isp_7x/imgsys/modules/mtk_imgsys-pqdip.h  |   3 +
 .../isp_7x/imgsys/modules/mtk_imgsys-traw.c   |  55 +++
 .../isp_7x/imgsys/modules/mtk_imgsys-traw.h   |   3 +
 .../isp_7x/imgsys/modules/mtk_imgsys-wpe.c    |  60 +++
 .../isp_7x/imgsys/modules/mtk_imgsys-wpe.h    |   3 +
 .../mediatek/isp/isp_7x/imgsys/mtk-img-ipi.h  |   8 +
 .../isp/isp_7x/imgsys/mtk_imgsys-gce_work.c   |   4 +
 .../isp_7x/imgsys/mtk_imgsys-module_main.c    |   4 +
 .../isp/isp_7x/imgsys/mtk_imgsys-module_ops.h |  11 +
 .../isp_7x/imgsys/mtk_imgsys-ndd_debugfs.c    | 342 ++++++++++++++++++
 .../isp_7x/imgsys/mtk_imgsys-ndd_debugfs.h    |  64 ++++
 .../isp/isp_7x/imgsys/mtk_imgsys-sys.c        |  11 +
 .../isp/isp_7x/imgsys/mtk_imgsys-v4l2.c       |   7 +
 19 files changed, 774 insertions(+)
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-me.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-me.h
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-ndd_debugfs.c
 create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-ndd_debugfs.h

diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
index 3aa53e8bfc6d..16044a280d5c 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
@@ -2,6 +2,7 @@
 #
 
 mtk_imgsys_util-objs := \
+mtk_imgsys-ndd_debugfs.o \
 mtk_imgsys-work_buf.o \
 mtk_imgsys-gce_work.o \
 mtk_imgsys-cmdq.o \
@@ -14,6 +15,7 @@ mtk_imgsys-sys.o \
 mtk_imgsys-v4l2.o
 
 mtk_imgsys_hw_isp-objs := \
+modules/mtk_imgsys-me.o \
 modules/mtk_imgsys-dip.o \
 modules/mtk_imgsys-traw.o \
 modules/mtk_imgsys-pqdip.o \
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.c
index 1cc1f3e87e8b..d9563d5a177a 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.c
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.c
@@ -10,6 +10,7 @@
 #include <linux/device.h>
 #include <linux/of_address.h>
 #include "../mtk_imgsys-module_common.h"
+#include "../mtk_imgsys-scp.h"
 #include "mtk_imgsys-dip.h"
 
 /********************************************************************
@@ -42,6 +43,8 @@
 #define DIPCQ_D1A_DIPCQ_CQ_THR17_CTL 0x318
 #define DIPCQ_D1A_DIPCQ_CQ_THR18_CTL 0x328
 
+#define DIP_REG_RANGE  0x17000
+
 #define DIP_INIT_ARRAY_COUNT	ARRAY_SIZE(mtk_imgsys_dip_init_ary)
 
 /********************************************************************
@@ -103,6 +106,50 @@ void imgsys_dip_init(struct mtk_imgsys_dev *imgsys_dev)
 }
 EXPORT_SYMBOL_GPL(imgsys_dip_init);
 
+void imgsys_dip_ndd_dump(struct mtk_imgsys_dev *imgsys_dev,
+			 struct imgsys_ndd_frm_dump_info *frm_dump_info)
+{
+	char *dip_name;
+	char file_name[NDD_FP_SIZE] = "\0";
+	ssize_t ret;
+	void *cq_va;
+
+	if (frm_dump_info->eng_e != IMGSYS_NDD_ENG_DIP)
+		return;
+
+	cq_va = imgsys_scp_get_reserve_mem_virt(DIP_MEM_C_ID);
+	if (!cq_va)
+		return;
+
+	cq_va += frm_dump_info->cq_ofst[frm_dump_info->eng_e];
+
+	dip_name = "REG_DIP_dip.reg";
+	ret = snprintf(file_name, sizeof(file_name), "%s%s", frm_dump_info->fp, dip_name);
+	if (ret < 0 || ret >= sizeof(file_name)) {
+		dev_err(imgsys_dev->dev, "wrong dip ndd file name %s\n", file_name);
+		return;
+	}
+
+	if (frm_dump_info->user_buffer) {
+		ret = copy_to_user(frm_dump_info->user_buffer, file_name, sizeof(file_name));
+		if (ret)
+			return;
+		frm_dump_info->user_buffer += sizeof(file_name);
+
+		ret = copy_to_user(frm_dump_info->user_buffer, cq_va, 0x9000);
+		if (ret)
+			return;
+		frm_dump_info->user_buffer += 0x48000 + 0x9000;
+
+		ret = copy_to_user(frm_dump_info->user_buffer,
+				   cq_va + 0x9000, DIP_REG_RANGE - 0x9000);
+		if (ret)
+			return;
+		frm_dump_info->user_buffer += DIP_REG_RANGE - 0x9000;
+	}
+}
+EXPORT_SYMBOL_GPL(imgsys_dip_ndd_dump);
+
 void imgsys_dip_uninit(struct mtk_imgsys_dev *imgsys_dev)
 {
 	unsigned int hw_idx;
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.h
index 22b4a7c3616d..1f0b85f1faba 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.h
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-dip.h
@@ -10,8 +10,11 @@
 #define _MTK_DIP_DIP_H_
 
 #include "../mtk_imgsys-dev.h"
+#include "../mtk_imgsys-ndd_debugfs.h"
 
 void imgsys_dip_init(struct mtk_imgsys_dev *imgsys_dev);
+void imgsys_dip_ndd_dump(struct mtk_imgsys_dev *imgsys_dev,
+			 struct imgsys_ndd_frm_dump_info *frm_dump_info);
 void imgsys_dip_uninit(struct mtk_imgsys_dev *imgsys_dev);
 
 #endif /* _MTK_DIP_DIP_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-me.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-me.c
new file mode 100644
index 000000000000..dacb3d591a71
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-me.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *         Holmes Chiou <holmes.chiou at mediatek.com>
+ *
+ */
+#include <linux/of_address.h>
+#include <linux/uaccess.h>
+#include "mtk_imgsys-me.h"
+
+#define ME_REG_RANGE 0xA20
+
+void imgsys_me_ndd_dump(struct mtk_imgsys_dev *imgsys_dev,
+			struct imgsys_ndd_frm_dump_info *frm_dump_info)
+{
+	char *me_name;
+	char file_name[NDD_FP_SIZE] = "\0";
+	void __iomem *reg_va;
+	ssize_t ret;
+
+	if (frm_dump_info->eng_e != IMGSYS_NDD_ENG_ME)
+		return;
+
+	reg_va = ioremap(frm_dump_info->cq_ofst[frm_dump_info->eng_e], ME_REG_RANGE);
+	if (!reg_va)
+		return;
+
+	me_name = "REG_ME_me.reg";
+
+	ret = snprintf(file_name, sizeof(file_name), "%s%s", frm_dump_info->fp, me_name);
+	if (ret < 0 || ret >= sizeof(file_name)) {
+		iounmap(reg_va);
+		return;
+	}
+
+	if (frm_dump_info->user_buffer) {
+		ret = copy_to_user(frm_dump_info->user_buffer, file_name, sizeof(file_name));
+		if (ret) {
+			iounmap(reg_va);
+			return;
+		}
+		frm_dump_info->user_buffer += sizeof(file_name);
+
+		void *kernel_buffer = kmalloc(ME_REG_RANGE, GFP_KERNEL);
+
+		if (!kernel_buffer) {
+			iounmap(reg_va);
+			return;
+		}
+
+		memcpy_fromio(kernel_buffer, reg_va, ME_REG_RANGE);
+		ret = copy_to_user(frm_dump_info->user_buffer, kernel_buffer, ME_REG_RANGE);
+		kfree(kernel_buffer);
+		if (ret != 0) {
+			iounmap(reg_va);
+			return;
+		}
+		frm_dump_info->user_buffer += ME_REG_RANGE;
+	}
+
+	iounmap(reg_va);
+}
+EXPORT_SYMBOL(imgsys_me_ndd_dump);
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-me.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-me.h
new file mode 100644
index 000000000000..10ed0153b740
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-me.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Frederic Chen <frederic.chen at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_IMGSYS_ME_H_
+#define _MTK_IMGSYS_ME_H_
+
+#include "../mtk_imgsys-dev.h"
+#include "../mtk_imgsys-ndd_debugfs.h"
+
+/**
+ * imgsys_me_ndd_dump - Dump the frame information for debugging.
+ * @imgsys_dev: Pointer to the mtk_imgsys_dev structure representing the ISP image
+ * processing device.
+ * @frm_dump_info: Pointer to the imgsys_ndd_frm_dump_info structure containing
+ * frame dump information.
+ *
+ * This function dumps the NDD (Normal Data Dump) frame information for debugging
+ * purposes. It provides insights into the frame data processed by the ISP image
+ * processing device, which can help in identifying issues related to frame
+ * handling.
+ */
+void imgsys_me_ndd_dump(struct mtk_imgsys_dev *imgsys_dev,
+			struct imgsys_ndd_frm_dump_info *frm_dump_info);
+
+#endif /* _MTK_IMGSYS_ME_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.c
index d1d3507555d9..f1f688b13ba5 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.c
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.c
@@ -9,6 +9,7 @@
 #include <linux/device.h>
 #include <linux/of_address.h>
 #include "../mtk_imgsys-module_common.h"
+#include "../mtk_imgsys-scp.h"
 #include "mtk_imgsys-pqdip.h"
 
 /********************************************************************
@@ -40,6 +41,8 @@
 #define DIPCQ_P1A_REG_DIPCQ_CQ_THR17_CTL		0x0318
 #define DIPCQ_P1A_REG_DIPCQ_CQ_THR18_CTL		0x0328
 
+#define PQDIP_REG_RANGE	0x6000
+
 #define PQDIP_INIT_ARRAY_COUNT	ARRAY_SIZE(mtk_imgsys_pqdip_init_ary)
 
 /********************************************************************
@@ -100,6 +103,55 @@ void imgsys_pqdip_init(struct mtk_imgsys_dev *imgsys_dev)
 }
 EXPORT_SYMBOL_GPL(imgsys_pqdip_init);
 
+void imgsys_pqdip_ndd_dump(struct mtk_imgsys_dev *imgsys_dev,
+			   struct imgsys_ndd_frm_dump_info *frm_dump_info)
+{
+	char *pqdip_name;
+	char file_name[NDD_FP_SIZE] = "\0";
+	ssize_t ret;
+	void *cq_va;
+
+	if (frm_dump_info->eng_e != IMGSYS_NDD_ENG_PQDIP_A &&
+	    frm_dump_info->eng_e != IMGSYS_NDD_ENG_PQDIP_B)
+		return;
+
+	cq_va = imgsys_scp_get_reserve_mem_virt(PQDIP_MEM_C_ID);
+	if (!cq_va)
+		return;
+
+	cq_va += frm_dump_info->cq_ofst[frm_dump_info->eng_e];
+
+	switch (frm_dump_info->eng_e) {
+	case IMGSYS_NDD_ENG_PQDIP_A:
+		pqdip_name = "REG_PQDIP_A_pqdipa.reg";
+		break;
+	case IMGSYS_NDD_ENG_PQDIP_B:
+		pqdip_name = "REG_PQDIP_B_pqdipb.reg";
+		break;
+	default:
+		return;
+	}
+
+	ret = snprintf(file_name, sizeof(file_name), "%s%s", frm_dump_info->fp, pqdip_name);
+	if (ret < 0 || ret >= sizeof(file_name)) {
+		dev_err(imgsys_dev->dev, "wrong dip ndd file name %s\n", file_name);
+		return;
+	}
+
+	if (frm_dump_info->user_buffer) {
+		ret = copy_to_user(frm_dump_info->user_buffer, file_name, sizeof(file_name));
+		if (ret)
+			return;
+		frm_dump_info->user_buffer += sizeof(file_name);
+
+		ret = copy_to_user(frm_dump_info->user_buffer, cq_va, PQDIP_REG_RANGE);
+		if (ret)
+			return;
+		frm_dump_info->user_buffer += PQDIP_REG_RANGE;
+	}
+}
+EXPORT_SYMBOL_GPL(imgsys_pqdip_ndd_dump);
+
 void imgsys_pqdip_uninit(struct mtk_imgsys_dev *imgsys_dev)
 {
 	unsigned int hw_idx;
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.h
index 00f93d536181..09bc51a1c15d 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.h
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-pqdip.h
@@ -10,8 +10,11 @@
 #define _MTK_IMGSYS_PQDIP_H_
 
 #include "../mtk_imgsys-dev.h"
+#include "../mtk_imgsys-ndd_debugfs.h"
 
 void imgsys_pqdip_init(struct mtk_imgsys_dev *imgsys_dev);
+void imgsys_pqdip_ndd_dump(struct mtk_imgsys_dev *imgsys_dev,
+			   struct imgsys_ndd_frm_dump_info *frm_dump_info);
 void imgsys_pqdip_uninit(struct mtk_imgsys_dev *imgsys_dev);
 
 #endif /* _MTK_IMGSYS_PQDIP_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.c
index 292f0ad09c46..90597f3a776a 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.c
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.c
@@ -9,6 +9,7 @@
 #include <linux/device.h>
 #include <linux/of_address.h>
 #include "../mtk_imgsys-module_common.h"
+#include "../mtk_imgsys-scp.h"
 #include "mtk_imgsys-traw.h"
 
 /********************************************************************
@@ -16,6 +17,8 @@
  ********************************************************************/
 #define TRAWCTL_INT1_EN 0x00A0
 
+#define TRAW_REG_RANGE 0xC000
+
 #define TRAW_INIT_ARRAY_COUNT	ARRAY_SIZE(mtk_imgsys_traw_init_ary)
 
 /********************************************************************
@@ -53,6 +56,58 @@ void imgsys_traw_init(struct mtk_imgsys_dev *imgsys_dev)
 }
 EXPORT_SYMBOL_GPL(imgsys_traw_init);
 
+void imgsys_traw_ndd_dump(struct mtk_imgsys_dev *imgsys_dev,
+			  struct imgsys_ndd_frm_dump_info *frm_dump_info)
+{
+	const char *traw_name;
+	char file_name[NDD_FP_SIZE] = "\0";
+	ssize_t ret;
+	void *cq_va;
+
+	if (frm_dump_info->eng_e > IMGSYS_NDD_ENG_XTR ||
+	    frm_dump_info->eng_e < IMGSYS_NDD_ENG_TRAW)
+		return;
+
+	switch (frm_dump_info->eng_e) {
+	case IMGSYS_NDD_ENG_TRAW:
+		traw_name = "REG_TRAW_traw.reg";
+		break;
+	case IMGSYS_NDD_ENG_LTR:
+		traw_name = "REG_LTRAW_ltraw.reg";
+		break;
+	case IMGSYS_NDD_ENG_XTR:
+		traw_name = "REG_XTRAW_xtraw.reg";
+		break;
+	default:
+		return;
+	}
+
+	cq_va = imgsys_scp_get_reserve_mem_virt(TRAW_MEM_C_ID);
+	if (!cq_va)
+		return;
+
+	cq_va += frm_dump_info->cq_ofst[frm_dump_info->eng_e];
+
+	ret = snprintf(file_name, sizeof(file_name), "%s%s", frm_dump_info->fp, traw_name);
+	if (ret < 0 || ret >= sizeof(file_name)) {
+		dev_err(imgsys_dev->dev, "wrong traw ndd file name %s\n", file_name);
+		return;
+	}
+
+	if (frm_dump_info->user_buffer) {
+		ret = copy_to_user(frm_dump_info->user_buffer, file_name, sizeof(file_name));
+		if (ret)
+			return;
+		frm_dump_info->user_buffer += sizeof(file_name);
+
+		ret = copy_to_user(frm_dump_info->user_buffer, cq_va, TRAW_REG_RANGE);
+		if (ret)
+			return;
+		frm_dump_info->user_buffer += TRAW_REG_RANGE;
+	}
+}
+EXPORT_SYMBOL_GPL(imgsys_traw_ndd_dump);
+
 void imgsys_traw_uninit(struct mtk_imgsys_dev *imgsys_dev)
 {
 	unsigned int hw_idx;
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.h
index f3727216b58c..57881bc2e191 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.h
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-traw.h
@@ -10,8 +10,11 @@
 #define _MTK_IMGSYS_TRAW_H_
 
 #include "../mtk_imgsys-dev.h"
+#include "../mtk_imgsys-ndd_debugfs.h"
 
 void imgsys_traw_init(struct mtk_imgsys_dev *imgsys_dev);
+void imgsys_traw_ndd_dump(struct mtk_imgsys_dev *imgsys_dev,
+			  struct imgsys_ndd_frm_dump_info *frm_dump_info);
 void imgsys_traw_uninit(struct mtk_imgsys_dev *imgsys_dev);
 
 #endif /* _MTK_IMGSYS_TRAW_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.c
index b19d61529b80..276af83a9ec2 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.c
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.c
@@ -9,6 +9,7 @@
 #include <linux/device.h>
 #include <linux/of_address.h>
 #include "../mtk_imgsys-module_common.h"
+#include "../mtk_imgsys-scp.h"
 #include "mtk_imgsys-wpe.h"
 
 /********************************************************************
@@ -41,6 +42,10 @@
 #define DIPCQ_W1A_DIPCQ_CQ_THR13_CTL_OFFSET 0x0BD8
 #define DIPCQ_W1A_DIPCQ_CQ_THR14_CTL_OFFSET 0x0BE8
 
+#define WPE_REG_RANGE	0x1000
+#define WPE_PSP_END_OFST	0x554
+#define WPE_COEF_END_OFST	0x5D8
+
 #define WPE_INIT_ARRAY_COUNT	ARRAY_SIZE(mtk_imgsys_wpe_init_ary)
 /********************************************************************
  * Global Variable
@@ -101,6 +106,61 @@ void imgsys_wpe_init(struct mtk_imgsys_dev *imgsys_dev)
 }
 EXPORT_SYMBOL_GPL(imgsys_wpe_init);
 
+void imgsys_wpe_ndd_dump(struct mtk_imgsys_dev *imgsys_dev,
+			 struct imgsys_ndd_frm_dump_info *frm_dump_info)
+{
+	char file_name[NDD_FP_SIZE] = "\0";
+	void *cq_va, *psp_va;
+	u64 psp_ofst;
+	ssize_t ret;
+
+	if (frm_dump_info->eng_e > IMGSYS_NDD_ENG_WPE_LITE)
+		return;
+
+	if (!frm_dump_info->user_buffer)
+		return;
+
+	cq_va = imgsys_scp_get_reserve_mem_virt(WPE_MEM_C_ID);
+	if (!cq_va)
+		return;
+
+	cq_va += frm_dump_info->cq_ofst[frm_dump_info->eng_e];
+
+	psp_va = imgsys_scp_get_reserve_mem_virt(WPE_MEM_C_ID);
+	if (!psp_va)
+		return;
+
+	psp_ofst = frm_dump_info->wpe_psp_ofst[frm_dump_info->eng_e];
+	psp_va += psp_ofst;
+
+	ret = snprintf(file_name, sizeof(file_name),
+		       "%s%s", frm_dump_info->fp, frm_dump_info->wpe_fp);
+	if (ret < 0 || ret >= sizeof(file_name))
+		return;
+
+	ret = copy_to_user(frm_dump_info->user_buffer, file_name, sizeof(file_name));
+	frm_dump_info->user_buffer += sizeof(file_name);
+
+	if (psp_ofst != 0) {
+		ret = copy_to_user(frm_dump_info->user_buffer,
+				   cq_va, WPE_PSP_END_OFST);
+		frm_dump_info->user_buffer += WPE_PSP_END_OFST;
+
+		ret = copy_to_user(frm_dump_info->user_buffer,
+				   psp_va, WPE_COEF_END_OFST - WPE_PSP_END_OFST);
+		frm_dump_info->user_buffer += (WPE_COEF_END_OFST - WPE_PSP_END_OFST);
+
+		ret = copy_to_user(frm_dump_info->user_buffer,
+				   cq_va + WPE_COEF_END_OFST, WPE_REG_RANGE - WPE_COEF_END_OFST);
+		frm_dump_info->user_buffer += (WPE_REG_RANGE - WPE_COEF_END_OFST);
+	} else {
+		ret = copy_to_user(frm_dump_info->user_buffer,
+				   cq_va, WPE_REG_RANGE);
+		frm_dump_info->user_buffer += WPE_REG_RANGE;
+	}
+}
+EXPORT_SYMBOL_GPL(imgsys_wpe_ndd_dump);
+
 void imgsys_wpe_uninit(struct mtk_imgsys_dev *imgsys_dev)
 {
 	unsigned int hw_idx;
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.h
index 6001575265e6..77b713bbe499 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.h
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_imgsys-wpe.h
@@ -10,8 +10,11 @@
 #define _MTK_IMGSYS_WPE_H_
 
 #include "../mtk_imgsys-dev.h"
+#include "../mtk_imgsys-ndd_debugfs.h"
 
 void imgsys_wpe_init(struct mtk_imgsys_dev *imgsys_dev);
+void imgsys_wpe_ndd_dump(struct mtk_imgsys_dev *imgsys_dev,
+			 struct imgsys_ndd_frm_dump_info *frm_dump_info);
 void imgsys_wpe_uninit(struct mtk_imgsys_dev *imgsys_dev);
 
 #endif /* _MTK_IMGSYS_WPE_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk-img-ipi.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk-img-ipi.h
index 850f6ec99a96..705d8c35ff55 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk-img-ipi.h
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk-img-ipi.h
@@ -81,6 +81,10 @@ struct img_init_info {
  * @is_earlycb: Indicates if early callback is enabled
  * @sw_goft: offset of GCE buffer
  * @g_swbuf: virtual address of GCE buffer
+ * @ndd_cq_ofst: NDD CQ offset
+ * @ndd_wpe_psp_ofst: NDD WPE PSP offset
+ * @ndd_wpe_fp: NDD WPE file path
+ * @ndd_fp: NDD file path
  *
  * These fields are primarily set by SCP (System Control Processor) and used by
  * the kernel for processing and verifing data.
@@ -92,6 +96,10 @@ struct img_swfrm_info {
 	u8 is_earlycb;
 	u64 sw_goft;
 	void *g_swbuf;
+	u64 ndd_cq_ofst[IMG_MAX_HW];
+	u64 ndd_wpe_psp_ofst[WPE_ENG_NUM];
+	char ndd_wpe_fp[64];
+	char ndd_fp[256];
 } __packed;
 
 /**
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-gce_work.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-gce_work.c
index ef86410e3d23..7e5b7cd383f9 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-gce_work.c
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-gce_work.c
@@ -2,6 +2,7 @@
 
 #include "mtk_imgsys-scp.h"
 #include "mtk_imgsys-gce_work.h"
+#include "mtk_imgsys-ndd_debugfs.h"
 
 static void cmdq_cb_done_worker(struct work_struct *work)
 {
@@ -17,6 +18,9 @@ static void cmdq_cb_done_worker(struct work_struct *work)
 	if (!pipe->streaming)
 		return;
 
+	if (gwfrm_info->user_info[0].ndd_fp[0] != '\0')
+		wait_event(gwork->wait_queue, atomic_read(&gwork->state) == WORK_COMPLETED);
+
 	/* send to SCP after frame done & del node from list */
 	swbuf_data.offset = gwfrm_info->req_sbuf_goft;
 	imgsys_scp_send(pipe->imgsys_dev, IPI_IMGSYS_DEQUE_DONE_ID,
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_main.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_main.c
index 5daa8f863bd2..c31ada82afcd 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_main.c
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_main.c
@@ -10,6 +10,7 @@
 #include <linux/of_address.h>
 #include "mtk_imgsys-module_common.h"
 #include "mtk_imgsys-module_main.h"
+#include "mtk_imgsys-ndd_debugfs.h"
 
 /********************************************************************
  * Global Define
@@ -147,6 +148,7 @@ void imgsys_main_init(struct mtk_imgsys_dev *imgsys_dev)
 	}
 
 	imgsys_main_hw_init(imgsys_dev);
+	imgsys_ndd_debugfs_init(imgsys_dev);
 }
 
 void imgsys_main_uninit(struct mtk_imgsys_dev *imgsys_dev)
@@ -180,4 +182,6 @@ void imgsys_main_uninit(struct mtk_imgsys_dev *imgsys_dev)
 		iounmap(dip2_reg_base);
 		dip2_reg_base = NULL;
 	}
+
+	imgsys_ndd_debugfs_uninit(imgsys_dev);
 }
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_ops.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_ops.h
index a2eea8f4fb3c..1dc28993bc09 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_ops.h
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_ops.h
@@ -25,14 +25,23 @@ enum mtk_imgsys_module {
 };
 
 struct mtk_imgsys_dev;
+struct imgsys_ndd_frm_dump_info;
 
 /**
  * struct module_ops - Operations for a specific module in the MediaTek Image System
+ *
  * @module_id: Identifier for the module.
  * @init: Function pointer to initialize the module.
  *        This function sets the default values for various software-related
  *        parameters and ensures that the module is ready for operation.
  *        Example function: imgsys_dip_init
+ * @ndddump: Function pointer to perform a dump of the module's frame information.
+ *           This function is responsible for dumping frame-related information.
+ *           It is typically used for debugging and diagnostic purposes to analyze
+ *           the state of the system and the frames being processed.
+ *           The dumped information can be used to trace issues or verify the
+ *           correctness of the frame processing pipeline.
+ *           Example function: imgsys_dip_ndd_dump
  * @uninit: Function pointer to uninitialize the module.
  *          This function resets various software-related parameters to ensure
  *          the module is properly cleaned up and ready for shutdown.
@@ -48,6 +57,8 @@ struct mtk_imgsys_dev;
 struct module_ops {
 	int module_id;
 	void (*init)(struct mtk_imgsys_dev *imgsys_dev);
+	void (*ndddump)(struct mtk_imgsys_dev *imgsys_dev,
+			struct imgsys_ndd_frm_dump_info *frm_dump_info);
 	void (*uninit)(struct mtk_imgsys_dev *imgsys_dev);
 };
 #endif /* _MTK_IMGSYS_MODULES_H_ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-ndd_debugfs.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-ndd_debugfs.c
new file mode 100644
index 000000000000..d0c1168fbd06
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-ndd_debugfs.c
@@ -0,0 +1,342 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Christopher Chen <christopher.chen at mediatek.com>
+ *
+ */
+
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/of_address.h>
+#include <linux/pm_runtime.h>
+#include <linux/remoteproc.h>
+#include <linux/uaccess.h>
+#include <soc/mediatek/smi.h>
+#include "mtk_imgsys-ndd_debugfs.h"
+#include "mtk_imgsys-module_common.h"
+#include "mtk_imgsys-gce_work.h"
+
+#define WPE_ENG_NUM		3
+#define TRAW_ENG_NUM	3
+#define DIP_ENG_NUM		1
+#define PQDIP_ENG_NUM	2
+#define ME_ENG_NUM		1
+
+#define WPE_NDD_SIZE	0x1000
+#define TRAW_NDD_SIZE	0xC000
+#define DIP_NDD_SIZE	0x5F000
+#define PQDIP_NDD_SIZE	0x6000
+#define ME_NDD_SIZE		0xA20
+
+struct ndd_request_t {
+	int fd;
+	struct list_head list;
+} __packed;
+
+struct user_ndd_requests_t {
+	struct list_head ndd_req_list; /* ndd_request_t list */
+	struct mutex lock; /* protect the ndd_req_list list*/
+};
+
+struct ndd_frame_info_t {
+	struct list_head ndd_swfrm_list; /* ndd_swfrm_info_t list */
+	struct mutex lock; /* protect the ndd_swfrm_list list*/
+};
+
+struct ndd_wpe_info_t {
+	char fp[NDD_FP_SIZE];
+	u8 data[WPE_NDD_SIZE];
+};
+
+struct ndd_traw_info_t {
+	char fp[NDD_FP_SIZE];
+	u8 data[TRAW_NDD_SIZE];
+};
+
+struct ndd_dip_info_t {
+	char fp[NDD_FP_SIZE];
+	u8 data[DIP_NDD_SIZE];
+};
+
+struct ndd_pqdip_info_t {
+	char fp[NDD_FP_SIZE];
+	u8 data[PQDIP_NDD_SIZE];
+};
+
+struct ndd_me_info_t {
+	char fp[NDD_FP_SIZE];
+	u8 data[ME_NDD_SIZE];
+};
+
+struct ndd_frm_info_t {
+	struct ndd_wpe_info_t	wpe[WPE_ENG_NUM];
+	struct ndd_traw_info_t	traw[TRAW_ENG_NUM];
+	struct ndd_dip_info_t	dip[DIP_ENG_NUM];
+	struct ndd_pqdip_info_t	pqdip[PQDIP_ENG_NUM];
+	struct ndd_me_info_t	me[ME_ENG_NUM];
+} __packed;
+
+static struct ndd_frame_info_t *ndd_frames;
+
+#if defined(CONFIG_DEBUG_FS)
+#define DEBUGFS_DIR "mtk_imgsys_debug"
+#define DEBUGFS_FILE "mtk_imgsys_ndd"
+#define FILE_PERMISSIONS 0644
+
+static struct dentry *debugfs_dir, *debugfs_file;
+static struct user_ndd_requests_t *ndd_reqs;
+
+static ssize_t debugfs_write(struct file *file, const char __user *user_buffer,
+			     size_t count, loff_t *ppos)
+{
+	char buffer[64];
+	int ret;
+	struct ndd_request_t *current_request;
+
+	if (count >= sizeof(buffer))
+		return -EINVAL;
+
+	if (copy_from_user(buffer, user_buffer, count))
+		return -EFAULT;
+
+	buffer[count] = '\0';
+
+	current_request = kmalloc(sizeof(*current_request), GFP_KERNEL);
+	if (!current_request)
+		return -ENOMEM;
+
+	ret = sscanf(buffer, "fd=%d", &current_request->fd);
+	if (ret != 1)
+		return -EINVAL;
+
+	mutex_lock(&ndd_reqs->lock);
+	list_add_tail(&current_request->list, &ndd_reqs->ndd_req_list);
+	mutex_unlock(&ndd_reqs->lock);
+
+	*ppos += count;
+
+	return count;
+}
+
+static void imgsys_ndd_dump_routine(struct mtk_imgsys_dev *imgsys_dev,
+				    struct imgsys_ndd_frm_dump_info *frm_dump_info)
+{
+	int i = 0;
+	int mid = 0;
+	unsigned int hw_num = 0x1;
+	unsigned int module_copy_ofst = 0;
+	const struct module_ops *imgsys_modules = imgsys_dev->modules;
+
+	dev_dbg(imgsys_dev->dev,
+		"%s: hw comb set: 0x%x\n", __func__, frm_dump_info->hw_comb);
+
+	for (i = 0; hw_num < IMGSYS_ENG_MAX_NUM; i++, hw_num = (0x1 << i)) {
+		switch (hw_num) {
+		case IMGSYS_ENG_WPE_EIS:
+		case IMGSYS_ENG_WPE_TNR:
+		case IMGSYS_ENG_WPE_LITE:
+			module_copy_ofst = (NDD_FP_SIZE + WPE_NDD_SIZE);
+			mid = IMGSYS_MOD_WPE;
+			break;
+		case IMGSYS_ENG_TRAW:
+		case IMGSYS_ENG_LTR:
+		case IMGSYS_ENG_XTR:
+			module_copy_ofst = (NDD_FP_SIZE + TRAW_NDD_SIZE);
+			mid = IMGSYS_MOD_TRAW;
+			break;
+		case IMGSYS_ENG_DIP:
+			module_copy_ofst = (NDD_FP_SIZE + DIP_NDD_SIZE);
+			mid = IMGSYS_MOD_DIP;
+			break;
+		case IMGSYS_ENG_PQDIP_A:
+		case IMGSYS_ENG_PQDIP_B:
+			module_copy_ofst = (NDD_FP_SIZE + PQDIP_NDD_SIZE);
+			mid = IMGSYS_MOD_PQDIP;
+			break;
+		case IMGSYS_ENG_ME:
+			module_copy_ofst = (NDD_FP_SIZE + ME_NDD_SIZE);
+			mid = IMGSYS_MOD_ME;
+			break;
+		default:
+			dev_err(imgsys_dev->dev, "%s get wrong hw id %d\n", __func__, hw_num);
+			break;
+		}
+
+		if (frm_dump_info->hw_comb & hw_num) {
+			frm_dump_info->eng_e = i;
+			if (imgsys_modules[mid].ndddump &&
+			    frm_dump_info->eng_e <= IMGSYS_NDD_ENG_ME)
+				imgsys_modules[mid].ndddump(imgsys_dev, frm_dump_info);
+		} else {
+			if (frm_dump_info->user_buffer)
+				frm_dump_info->user_buffer += module_copy_ofst;
+			else
+				frm_dump_info->user_buffer = NULL;
+		}
+
+		if ((frm_dump_info->hw_comb >> i) == 0)
+			return;
+	}
+}
+
+static ssize_t debugfs_read(struct file *file, char __user *user_buffer,
+			    size_t count, loff_t *ppos)
+{
+	struct ndd_swfrm_info_t *cur_ndd_swfrm = NULL, *swfrm_temp = NULL;
+	struct ndd_request_t *cur_user_req = NULL, *req_temp = NULL;
+	struct img_swfrm_info *subfrm_info = NULL;
+	struct imgsys_ndd_frm_dump_info frm_dump_info = { 0 };
+	struct gce_cb_work_pool *work_pool = NULL;
+	ssize_t read_count = 0;
+	size_t buffer_size = count;
+	bool found = false;
+	int frm, ret = 0;
+	u32 gce_cb_work_idx = MTK_IMGSYS_GCE_CB_MAX_WORK_ITEMS;
+
+	mutex_lock(&ndd_frames->lock);
+
+	list_for_each_entry_safe(cur_ndd_swfrm, swfrm_temp, &ndd_frames->ndd_swfrm_list, list) {
+		mutex_lock(&ndd_reqs->lock);
+		list_for_each_entry_safe(cur_user_req, req_temp, &ndd_reqs->ndd_req_list, list) {
+			if (cur_ndd_swfrm->gwfrm_info &&
+			    cur_ndd_swfrm->gwfrm_info->request_fd == cur_user_req->fd) {
+				found = true;
+				break;
+			}
+		}
+		mutex_unlock(&ndd_reqs->lock);
+
+		if (found) {
+			for (frm = 0; frm < cur_ndd_swfrm->gwfrm_info->total_frmnum; frm++) {
+				subfrm_info = &cur_ndd_swfrm->gwfrm_info->user_info[frm];
+				memset(&frm_dump_info, 0, sizeof(frm_dump_info));
+
+				if (buffer_size < sizeof(struct ndd_frm_info_t)) {
+					ret = -ENOMEM;
+					goto out;
+				}
+
+				if (subfrm_info->ndd_fp[0] == '\0')
+					continue;
+
+				frm_dump_info.user_buffer = user_buffer +
+					sizeof(struct ndd_frm_info_t) * frm;
+				frm_dump_info.hw_comb = subfrm_info->hw_comb;
+				frm_dump_info.cq_ofst = subfrm_info->ndd_cq_ofst;
+				frm_dump_info.wpe_psp_ofst = subfrm_info->ndd_wpe_psp_ofst;
+				frm_dump_info.wpe_fp = subfrm_info->ndd_wpe_fp;
+				frm_dump_info.fp = subfrm_info->ndd_fp;
+
+				imgsys_ndd_dump_routine(cur_ndd_swfrm->imgsys_dev, &frm_dump_info);
+				read_count += sizeof(struct ndd_frm_info_t);
+				buffer_size -= sizeof(struct ndd_frm_info_t);
+			}
+
+			work_pool = cur_ndd_swfrm->imgsys_dev->work_pool;
+			do {
+				gce_cb_work_idx = atomic_read(&cur_ndd_swfrm->gce_cb_work_idx);
+			} while (gce_cb_work_idx == MTK_IMGSYS_GCE_CB_MAX_WORK_ITEMS);
+			atomic_set(&work_pool->work_items[gce_cb_work_idx].state, WORK_COMPLETED);
+			wake_up(&work_pool->work_items[gce_cb_work_idx].wait_queue);
+
+			list_del(&cur_ndd_swfrm->list);
+			kfree(cur_ndd_swfrm);
+			cur_ndd_swfrm = NULL;
+			list_del(&cur_user_req->list);
+			kfree(cur_user_req);
+			cur_user_req = NULL;
+			break;
+		}
+	}
+
+	if (!found)
+		ret = -ENOENT;
+out:
+	mutex_unlock(&ndd_frames->lock);
+
+	return ret == 0 ? read_count : ret;
+}
+
+static const struct file_operations debugfs_fops = {
+	.write = debugfs_write,
+	.read = debugfs_read,
+};
+
+void imgsys_ndd_debugfs_init(struct mtk_imgsys_dev *imgsys_dev)
+{
+	debugfs_dir = debugfs_create_dir(DEBUGFS_DIR, NULL);
+	if (!debugfs_dir) {
+		dev_err(imgsys_dev->dev, "%s Failed to create debugfs dir\n", __func__);
+		return;
+	}
+
+	debugfs_file = debugfs_create_file(DEBUGFS_FILE, FILE_PERMISSIONS,
+					   debugfs_dir, NULL, &debugfs_fops);
+	if (!debugfs_file) {
+		dev_err(imgsys_dev->dev, "%s Failed to create debugfs file\n", __func__);
+		return;
+	}
+
+	ndd_frames = kmalloc(sizeof(*ndd_frames), GFP_KERNEL);
+	if (!ndd_frames)
+		return;
+	INIT_LIST_HEAD(&ndd_frames->ndd_swfrm_list);
+	mutex_init(&ndd_frames->lock);
+
+	ndd_reqs = kmalloc(sizeof(*ndd_reqs), GFP_KERNEL);
+	if (!ndd_reqs)
+		return;
+	INIT_LIST_HEAD(&ndd_reqs->ndd_req_list);
+	mutex_init(&ndd_reqs->lock);
+}
+EXPORT_SYMBOL_GPL(imgsys_ndd_debugfs_init);
+
+void imgsys_ndd_debugfs_uninit(struct mtk_imgsys_dev *imgsys_dev)
+{
+	struct ndd_request_t *req, *tmp;
+
+	debugfs_remove(debugfs_file);
+	debugfs_remove(debugfs_dir);
+
+	mutex_lock(&ndd_reqs->lock);
+	list_for_each_entry_safe(req, tmp, &ndd_reqs->ndd_req_list, list) {
+		list_del(&req->list);
+		kfree(req);
+	}
+	mutex_unlock(&ndd_reqs->lock);
+	kfree(ndd_reqs);
+
+	mutex_lock(&ndd_frames->lock);
+	list_for_each_entry_safe(req, tmp, &ndd_frames->ndd_swfrm_list, list) {
+		list_del(&req->list);
+		kfree(req);
+	}
+	mutex_unlock(&ndd_frames->lock);
+	kfree(ndd_frames);
+}
+EXPORT_SYMBOL_GPL(imgsys_ndd_debugfs_uninit);
+#endif
+
+void imgsys_ndd_swfrm_list_add(struct mtk_imgsys_dev *imgsys_dev,
+			       struct swfrm_info *gwfrm_info)
+{
+	struct ndd_swfrm_info_t *new_ndd_swfrm;
+
+	new_ndd_swfrm = kzalloc(sizeof(*new_ndd_swfrm), GFP_KERNEL);
+	if (!new_ndd_swfrm)
+		return;
+
+	new_ndd_swfrm->imgsys_dev = imgsys_dev;
+	new_ndd_swfrm->gwfrm_info = gwfrm_info;
+	atomic_set(&new_ndd_swfrm->gce_cb_work_idx, MTK_IMGSYS_GCE_CB_MAX_WORK_ITEMS);
+
+	gwfrm_info->ndd_swfrm_info = (void *)new_ndd_swfrm;
+
+	mutex_lock(&ndd_frames->lock);
+	list_add_tail(&new_ndd_swfrm->list, &ndd_frames->ndd_swfrm_list);
+	mutex_unlock(&ndd_frames->lock);
+}
+EXPORT_SYMBOL_GPL(imgsys_ndd_swfrm_list_add);
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-ndd_debugfs.h b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-ndd_debugfs.h
new file mode 100644
index 000000000000..f45cacc7bfff
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-ndd_debugfs.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ *
+ * Author: Christopher Chen <christopher.chen at mediatek.com>
+ *
+ */
+
+#ifndef _MTK_IMGSYS_NDD_DEBUGFS_H_
+#define _MTK_IMGSYS_NDD_DEBUGFS_H_
+
+#include "mtk_imgsys-dev.h"
+
+#define NDD_FP_SIZE 256 /* NDD file path size */
+
+enum mtk_imgsys_ndd_eng {
+	IMGSYS_NDD_ENG_WPE_EIS	= 0,
+	IMGSYS_NDD_ENG_WPE_TNR	= 1,
+	IMGSYS_NDD_ENG_WPE_LITE	= 2,
+	IMGSYS_NDD_ENG_ADL_A	= 3,
+	IMGSYS_NDD_ENG_ADL_B	= 4,
+	IMGSYS_NDD_ENG_TRAW	= 5,
+	IMGSYS_NDD_ENG_LTR	= 6,
+	IMGSYS_NDD_ENG_XTR	= 7,
+	IMGSYS_NDD_ENG_DIP	= 8,
+	IMGSYS_NDD_ENG_PQDIP_A	= 9,
+	IMGSYS_NDD_ENG_PQDIP_B	= 10,
+	IMGSYS_NDD_ENG_ME	= 11,
+	IMGSYS_NDD_ENG_MAX_NUM	= 12
+};
+
+struct imgsys_ndd_frm_dump_info {
+	char __user *user_buffer;
+	unsigned int hw_comb;
+	enum mtk_imgsys_ndd_eng eng_e;
+	u64 *cq_ofst;
+	u64 *wpe_psp_ofst;
+	char *wpe_fp;
+	char *fp;
+};
+
+struct ndd_swfrm_info_t {
+	struct mtk_imgsys_dev *imgsys_dev;
+	struct swfrm_info *gwfrm_info;
+	struct list_head list;
+	atomic_t gce_cb_work_idx;
+} __packed;
+
+#if defined(CONFIG_DEBUG_FS)
+void imgsys_ndd_debugfs_init(struct mtk_imgsys_dev *imgsys_dev);
+void imgsys_ndd_debugfs_uninit(struct mtk_imgsys_dev *imgsys_dev);
+#else
+static inline void imgsys_ndd_debugfs_init(struct mtk_imgsys_dev *imgsys_dev)
+{
+}
+
+static inline void imgsys_ndd_debugfs_uninit(struct mtk_imgsys_dev *imgsys_dev)
+{
+}
+#endif
+void imgsys_ndd_swfrm_list_add(struct mtk_imgsys_dev *imgsys_dev,
+			       struct swfrm_info *gwfrm_info);
+#endif /* _MTK_IMGSYS_DEBUG_H_ */
+
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
index 36088a5bda8e..a87b254cd114 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
@@ -16,6 +16,7 @@
 #include "mtk_imgsys-gce_work.h"
 #include "mtk_header_desc.h"
 #include "mtk_imgsys_v4l2_vnode.h"
+#include "mtk_imgsys-ndd_debugfs.h"
 
 #define FRAME_STATE_INIT		0
 #define FRAME_STATE_HW_TIMEOUT		1
@@ -60,6 +61,7 @@ static void imgsys_cmdq_cb_func(struct imgsys_cmdq_cb_data data)
 	struct mtk_imgsys_dev *imgsys_dev;
 	struct swfrm_info *swfrminfo_cb;
 	struct gce_cb_work *gwork;
+	struct ndd_swfrm_info_t *ndd_swfrm;
 
 	swfrminfo_cb = data.data;
 	pipe = (struct mtk_imgsys_pipe *)swfrminfo_cb->pipe;
@@ -94,6 +96,12 @@ static void imgsys_cmdq_cb_func(struct imgsys_cmdq_cb_data data)
 		gwork->pipe = swfrminfo_cb->pipe;
 		init_waitqueue_head(&gwork->wait_queue);
 
+		if (swfrminfo_cb->user_info[0].ndd_fp[0] != '\0') {
+			ndd_swfrm = (struct ndd_swfrm_info_t *)swfrminfo_cb->ndd_swfrm_info;
+			if (ndd_swfrm)
+				atomic_set(&ndd_swfrm->gce_cb_work_idx, gwork->work_idx);
+		}
+
 		queue_work(req->imgsys_pipe->imgsys_dev->gcecb_wq, &gwork->work);
 	}
 }
@@ -207,6 +215,9 @@ static void imgsys_scp_handler(void *data, unsigned int len, void *priv)
 
 	up(&imgsys_dev->sem);
 
+	if (swfrm_info->user_info[0].ndd_fp[0] != '\0')
+		imgsys_ndd_swfrm_list_add(imgsys_dev, swfrm_info);
+
 	INIT_WORK(&req->runner_work, imgsys_runner_func);
 	queue_work(req->imgsys_pipe->imgsys_dev->runner_wq,
 		   &req->runner_work);
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
index ea2ce03c2619..b0088d4de69c 100644
--- a/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
+++ b/drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
@@ -26,6 +26,7 @@
 #include "modules/mtk_imgsys-traw.h"
 #include "modules/mtk_imgsys-pqdip.h"
 #include "modules/mtk_imgsys-wpe.h"
+#include "modules/mtk_imgsys-me.h"
 #include "mtk_imgsys-of.h"
 #include "mtk_imgsys-vnode_id.h"
 #include "mtk_imgsys_v4l2_vnode.h"
@@ -1846,31 +1847,37 @@ static const struct module_ops imgsys_isp7_modules[] = {
 	[IMGSYS_MOD_IMGMAIN] = {
 		.module_id = IMGSYS_MOD_IMGMAIN,
 		.init = imgsys_main_init,
+		.ndddump = NULL,
 		.uninit = imgsys_main_uninit,
 	},
 	[IMGSYS_MOD_WPE] = {
 		.module_id = IMGSYS_MOD_WPE,
 		.init = imgsys_wpe_init,
+		.ndddump = imgsys_wpe_ndd_dump,
 		.uninit = imgsys_wpe_uninit,
 	},
 	[IMGSYS_MOD_TRAW] = {
 		.module_id = IMGSYS_MOD_TRAW,
 		.init = imgsys_traw_init,
+		.ndddump = imgsys_traw_ndd_dump,
 		.uninit = imgsys_traw_uninit,
 	},
 	[IMGSYS_MOD_DIP] = {
 		.module_id = IMGSYS_MOD_DIP,
 		.init = imgsys_dip_init,
+		.ndddump = imgsys_dip_ndd_dump,
 		.uninit = imgsys_dip_uninit,
 	},
 	[IMGSYS_MOD_PQDIP] = {
 		.module_id = IMGSYS_MOD_PQDIP,
 		.init = imgsys_pqdip_init,
+		.ndddump = imgsys_pqdip_ndd_dump,
 		.uninit = imgsys_pqdip_uninit,
 	},
 	[IMGSYS_MOD_ME] = {
 		.module_id = IMGSYS_MOD_ME,
 		.init = NULL,
+		.ndddump = imgsys_me_ndd_dump,
 		.uninit = NULL,
 	},
 };
-- 
2.45.2



From daniel at fooishbar.org  Sat May 24 05:47:13 2025
From: daniel at fooishbar.org (Daniel Stone)
Date: Sat, 24 May 2025 13:47:13 +0100
Subject: [PATCH] drm/mediatek: Add wait_event_timeout when disabling plane
In-Reply-To: <20250522085149.3361598-1-jason-jh.lin@mediatek.com>
References: <20250522085149.3361598-1-jason-jh.lin@mediatek.com>
Message-ID: <CAPj87rNV_48pQF+gv3HEx+-n1WvKOoX2u_HRW5w8DrgEAigk9w@mail.gmail.com>

Hi Jason,

On Thu, 22 May 2025 at 09:52, Jason-JH Lin <jason-jh.lin at mediatek.com> wrote:
> Our hardware registers are set through GCE, not by the CPU.
> DRM might assume the hardware is disabled immediately after calling
> atomic_disable() of drm_plane, but it is only truly disabled after the
> GCE IRQ is triggered.
>
> Additionally, the cursor plane in DRM uses async_commit, so DRM will
> not wait for vblank and will free the buffer immediately after calling
> atomic_disable().
>
> To prevent the framebuffer from being freed before the layer disable
> settings are configured into the hardware, which can cause an IOMMU
> fault error, a wait_event_timeout has been added to wait for the
> ddp_cmdq_cb() callback,indicating that the GCE IRQ has been triggered.

Waiting up to 500ms for each plane to be disabled is ... not ideal.
Especially as multiple planes can be disabled at once. This may happen
dynamically during runtime, e.g. when a video is playing and a user
moves their cursor over the plane to make the UI controls visible.

I think this should be handled through the atomic_commit() handler,
with asynchronous tracking of the state, instead of the hard block
here.

Cheers,
Daniel


From robh at kernel.org  Sat May 24 06:37:41 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Sat, 24 May 2025 08:37:41 -0500
Subject: [PATCH v1 01/10] dt-bindings: media: Add MediaTek mt8188
 ImgSys components
In-Reply-To: <20250524115144.3832748-2-olivia.wen@mediatek.com>
References: <20250524115144.3832748-1-olivia.wen@mediatek.com>
 <20250524115144.3832748-2-olivia.wen@mediatek.com>
Message-ID: <174809386038.549652.1263468272508643617.robh@kernel.org>


On Sat, 24 May 2025 19:49:53 +0800, Olivia Wen wrote:
> Introduce more Image System (ImgSys) components present in MT8188.
> 
> Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
> ---
>  .../bindings/media/mediatek,imgsys.yaml       | 180 ++++++++++++++++++
>  1 file changed, 180 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/mediatek,imgsys.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/media/mediatek,imgsys.example.dtb: imgsys-fw at 15000000 (mediatek,mt8188-isp-imgsys): reg: [[0, 352321536], [0, 16384], [0, 352452608], [0, 65536], [0, 352583680], [0, 65536], [0, 358875136], [0, 65536], [0, 353370112], [0, 65536], [0, 353697792], [0, 65536], [0, 354484224], [0, 65536], [0, 357629952], [0, 65536], [0, 354418688], [0, 65536], [0, 357564416], [0, 65536], [0, 358612992], [0, 65536], [0, 354549760], [0, 256], [0, 355598336], [0, 65536], [0, 357695488], [0, 256], [0, 358744064], [0, 256], [0, 353435648], [0, 256], [0, 353566720], [0, 256]] is too long
	from schema $id: http://devicetree.org/schemas/media/mediatek,imgsys.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250524115144.3832748-2-olivia.wen at mediatek.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.



From robh at kernel.org  Sat May 24 06:37:43 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Sat, 24 May 2025 08:37:43 -0500
Subject: [PATCH v1 02/10] dt-bindings: media: Add MT8188 ImgSys's LARB
In-Reply-To: <20250524115144.3832748-3-olivia.wen@mediatek.com>
References: <20250524115144.3832748-1-olivia.wen@mediatek.com>
 <20250524115144.3832748-3-olivia.wen@mediatek.com>
Message-ID: <174809386113.549698.18274088720500456314.robh@kernel.org>


On Sat, 24 May 2025 19:49:54 +0800, Olivia Wen wrote:
> This patch adds support for the MT8188 Image System's Local Arbiter
> (LARB) in the device tree bindings. The LARB is a crucial component in
> MediaTek's ImgSys architecture, responsible for managing memory access
> and arbitration between various hardware modules.
> 
> Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
> ---
>  .../bindings/media/mediatek,imgsys-larbs.yaml | 75 +++++++++++++++++++
>  1 file changed, 75 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/mediatek,imgsys-larbs.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/media/mediatek,imgsys-larbs.example.dtb: /example-0/imgsys-l11b: failed to match any schema with compatible: ['mediatek,mt8188-imgsys-larb']

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250524115144.3832748-3-olivia.wen at mediatek.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.



From krzk at kernel.org  Sat May 24 21:55:36 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Sun, 25 May 2025 06:55:36 +0200
Subject: [PATCH v1 02/10] dt-bindings: media: Add MT8188 ImgSys's LARB
In-Reply-To: <20250524115144.3832748-3-olivia.wen@mediatek.com>
References: <20250524115144.3832748-1-olivia.wen@mediatek.com>
 <20250524115144.3832748-3-olivia.wen@mediatek.com>
Message-ID: <1e18c066-dc4c-4f54-a784-8edbfdd7b5d0@kernel.org>

On 24/05/2025 13:49, Olivia Wen wrote:
> This patch adds support for the MT8188 Image System's Local Arbiter
> (LARB) in the device tree bindings. The LARB is a crucial component in
> MediaTek's ImgSys architecture, responsible for managing memory access
> and arbitration between various hardware modules.
> 
> Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
> ---
>  .../bindings/media/mediatek,imgsys-larbs.yaml | 75 +++++++++++++++++++

Your patchset wasn't tested, so I won't do full review. Be sure you test
it prior sending. Few nits below:

Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters


>  1 file changed, 75 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/mediatek,imgsys-larbs.yaml
> 
> diff --git a/Documentation/devicetree/bindings/media/mediatek,imgsys-larbs.yaml b/Documentation/devicetree/bindings/media/mediatek,imgsys-larbs.yaml
> new file mode 100644
> index 000000000000..d2966c64ddb6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,imgsys-larbs.yaml

Filename equal to compatible.

> @@ -0,0 +1,75 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,imgsys-larbs.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: LARB Information for MediaTek Camera Image System Hardware
> +
> +maintainers:
> +  - Olivia Wen <olivia.wen at mediatek.com>
> +
> +description:
> +  Detailed configuration for MediaTek Camera Image System's Local Arbiter
> +  (LARB) hardware integration.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - mediatek,mt8188-imgsys-larbs
> +
> +  iommus:
> +    minItems: 1
> +    maxItems: 30

This cannot be flexible. List the items, unless it is somehow obvious.


> +
> +  '#address-cells':
> +    const: 2
> +
> +  '#size-cells':
> +    const: 2

These are useless.

> +
> +required:
> +  - compatible
> +  - iommus
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
> +
> +    imgsys-l11b {

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation


> +        compatible = "mediatek,mt8188-imgsys-larb";
> +        #address-cells = <2>;
> +        #size-cells = <2>;

Why?

> +        iommus = <&vpp_iommu M4U_PORT_L11B_WPE_RDMA_0>,
> +             <&vpp_iommu M4U_PORT_L11B_WPE_RDMA_1>,

Fix alignment.



Best regards,
Krzysztof


From krzysztof.kozlowski at linaro.org  Sat May 24 22:16:40 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Sun, 25 May 2025 07:16:40 +0200
Subject: [PATCH] media: dt-bindings: mediatek: Constrain iommus
Message-ID: <20250525051639.68753-2-krzysztof.kozlowski@linaro.org>

Lists should have fixed constraints, because binding must be specific in
respect to hardware.  Add missing constraints to number of iommus in
Mediatek media devices.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 .../bindings/display/mediatek/mediatek,ovl-2l.yaml           | 5 ++---
 .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml   | 5 ++---
 .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml  | 4 +---
 .../devicetree/bindings/display/mediatek/mediatek,wdma.yaml  | 4 +---
 4 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
index bacdfe7d08a6..ac0d924a451b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
@@ -45,9 +45,8 @@ properties:
       - description: OVL-2L Clock
 
   iommus:
-    description:
-      This property should point to the respective IOMMU block with master port as argument,
-      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+    minItems: 1
+    maxItems: 2
 
   mediatek,gce-client-reg:
     description: The register of client driver can be configured by gce with
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
index 4f110635afb6..c0fd0a91c4d8 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -65,9 +65,8 @@ properties:
       - description: OVL Clock
 
   iommus:
-    description:
-      This property should point to the respective IOMMU block with master port as argument,
-      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+    minItems: 1
+    maxItems: 2
 
   mediatek,gce-client-reg:
     description: The register of client driver can be configured by gce with
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
index 878f676b581f..7e5234def39a 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@ -64,9 +64,7 @@ properties:
       - description: RDMA Clock
 
   iommus:
-    description:
-      This property should point to the respective IOMMU block with master port as argument,
-      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+    maxItems: 1
 
   mediatek,rdma-fifo-size:
     description:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
index a3a2b71a4523..276868c0fde7 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
@@ -43,9 +43,7 @@ properties:
       - description: WDMA Clock
 
   iommus:
-    description:
-      This property should point to the respective IOMMU block with master port as argument,
-      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+    maxItems: 1
 
   mediatek,gce-client-reg:
     description: The register of client driver can be configured by gce with
-- 
2.45.2



From pmenzel at molgen.mpg.de  Sat May 24 23:01:04 2025
From: pmenzel at molgen.mpg.de (Paul Menzel)
Date: Sun, 25 May 2025 08:01:04 +0200
Subject: MT8183: Only maximum resolution 1280x720?
Message-ID: <c8a64686-f1a2-44f1-9d13-fd5b4f923e0f@molgen.mpg.de>

Dear Linux folks,


On the older MT8183 device Lenovo IdeaPad Duet Chromebook, running 
ChromeOS with their Linux 5.10.x, connecting a 1920x1080 Dell monitor to 
a USB-C adapter using HDMI, only the resolution of 1280x720 is 
configured, although the adapter also support 1920x1080. It happens with 
all adapters, for example, LMP USB-C mini Dock [1].

I reported it to the Chromium OS issue tracker [1], and the last comment is:

> It seems the display pipeline for the internal display (DSI) has
> higher clock rate. Also, the resolution support depends on the
> refresh rate as well, so the claimed 2400x1080 might only work on
> lower refresh rate.
> 
> For the external display, the display modes are mostly rejected by
> the pre-defined max_clock_khz in mtk_dpi.c:
> https://elixir.bootlin.com/linux/v6.11.4/source/drivers/gpu/drm/mediatek/mtk_dpi.c#L940

Can you confirm this? The font rendering seems not so good in the lower 
resolution, and strangely, playing movies these seem to be rendered in 
higher resolution (or the monitor or hardware does a good job in 
up-scaling).


Kind regards,

Paul


[1]: https://lmp-adapter.com/product/lmp-usb-c-mini-dock/
[2]: https://issuetracker.google.com/issues/295666708


From Deren.Wu at mediatek.com  Sat May 24 23:11:21 2025
From: Deren.Wu at mediatek.com (Deren Wu)
Date: Sun, 25 May 2025 14:11:21 +0800
Subject: [PATCH 1/2] wifi: mt76: mt7925: prevent NULL pointer dereference in mt7925_sta_set_decap_offload()
Message-ID: <35aedbffa050e98939264300407a52ba4e236d52.1748149855.git.deren.wu@mediatek.com>

From: Deren Wu <deren.wu at mediatek.com>

Add a NULL check for msta->vif before accessing its members to prevent
a kernel panic in AP mode deployment. This also fix the issue reported
in [1].

The crash occurs when this function is triggered before the station is
fully initialized. The call trace shows a page fault at
mt7925_sta_set_decap_offload() due to accessing resources when msta->vif
is NULL.

Fix this by adding an early return if msta->vif is NULL and also check
wcid.sta is ready. This ensures we only proceed with decap offload
configuration when the station's state is properly initialized.

[14739.655703] Unable to handle kernel paging request at virtual address ffffffffffffffa0
[14739.811820] CPU: 0 UID: 0 PID: 895854 Comm: hostapd Tainted: G
[14739.821394] Tainted: [C]=CRAP, [O]=OOT_MODULE
[14739.825746] Hardware name: Raspberry Pi 4 Model B Rev 1.1 (DT)
[14739.831577] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[14739.838538] pc : mt7925_sta_set_decap_offload+0xc0/0x1b8 [mt7925_common]
[14739.845271] lr : mt7925_sta_set_decap_offload+0x58/0x1b8 [mt7925_common]
[14739.851985] sp : ffffffc085efb500
[14739.855295] x29: ffffffc085efb500 x28: 0000000000000000 x27: ffffff807803a158
[14739.862436] x26: ffffff8041ececb8 x25: 0000000000000001 x24: 0000000000000001
[14739.869577] x23: 0000000000000001 x22: 0000000000000008 x21: ffffff8041ecea88
[14739.876715] x20: ffffff8041c19ca0 x19: ffffff8078031fe0 x18: 0000000000000000
[14739.883853] x17: 0000000000000000 x16: ffffffe2aeac1110 x15: 000000559da48080
[14739.890991] x14: 0000000000000001 x13: 0000000000000000 x12: 0000000000000000
[14739.898130] x11: 0a10020001008e88 x10: 0000000000001a50 x9 : ffffffe26457bfa0
[14739.905269] x8 : ffffff8042013bb0 x7 : ffffff807fb6cbf8 x6 : dead000000000100
[14739.912407] x5 : dead000000000122 x4 : ffffff80780326c8 x3 : 0000000000000000
[14739.919546] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffffff8041ececb8
[14739.926686] Call trace:
[14739.929130]  mt7925_sta_set_decap_offload+0xc0/0x1b8 [mt7925_common]
[14739.935505]  ieee80211_check_fast_rx+0x19c/0x510 [mac80211]
[14739.941344]  _sta_info_move_state+0xe4/0x510 [mac80211]
[14739.946860]  sta_info_move_state+0x1c/0x30 [mac80211]
[14739.952116]  sta_apply_auth_flags.constprop.0+0x90/0x1b0 [mac80211]
[14739.958708]  sta_apply_parameters+0x234/0x5e0 [mac80211]
[14739.964332]  ieee80211_add_station+0xdc/0x190 [mac80211]
[14739.969950]  nl80211_new_station+0x46c/0x670 [cfg80211]
[14739.975516]  genl_family_rcv_msg_doit+0xdc/0x150
[14739.980158]  genl_rcv_msg+0x218/0x298
[14739.983830]  netlink_rcv_skb+0x64/0x138
[14739.987670]  genl_rcv+0x40/0x60
[14739.990816]  netlink_unicast+0x314/0x380
[14739.994742]  netlink_sendmsg+0x198/0x3f0
[14739.998664]  __sock_sendmsg+0x64/0xc0
[14740.002324]  ____sys_sendmsg+0x260/0x298
[14740.006242]  ___sys_sendmsg+0xb4/0x110

Cc: stable at vger.kernel.org
Link: https://github.com/morrownr/USB-WiFi/issues/603 [1]
Fixes: b859ad65309a ("wifi: mt76: mt7925: add link handling in mt7925_sta_set_decap_offload")
Signed-off-by: Deren Wu <deren.wu at mediatek.com>
---
 drivers/net/wireless/mediatek/mt76/mt7925/main.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/main.c b/drivers/net/wireless/mediatek/mt76/mt7925/main.c
index 94b0099dcd41..320011fc3073 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/main.c
@@ -1603,6 +1603,9 @@ static void mt7925_sta_set_decap_offload(struct ieee80211_hw *hw,
 	unsigned long valid = mvif->valid_links;
 	u8 i;
 
+	if (!msta->vif)
+		return;
+
 	mt792x_mutex_acquire(dev);
 
 	valid = ieee80211_vif_is_mld(vif) ? mvif->valid_links : BIT(0);
@@ -1617,6 +1620,9 @@ static void mt7925_sta_set_decap_offload(struct ieee80211_hw *hw,
 		else
 			clear_bit(MT_WCID_FLAG_HDR_TRANS, &mlink->wcid.flags);
 
+		if (!mlink->wcid.sta)
+			continue;
+
 		mt7925_mcu_wtbl_update_hdr_trans(dev, vif, sta, i);
 	}
 
-- 
2.18.0



From Deren.Wu at mediatek.com  Sat May 24 23:11:22 2025
From: Deren.Wu at mediatek.com (Deren Wu)
Date: Sun, 25 May 2025 14:11:22 +0800
Subject: [PATCH 2/2] wifi: mt76: mt7921: prevent decap offload config before STA initialization
In-Reply-To: <35aedbffa050e98939264300407a52ba4e236d52.1748149855.git.deren.wu@mediatek.com>
References: <35aedbffa050e98939264300407a52ba4e236d52.1748149855.git.deren.wu@mediatek.com>
Message-ID: <f23a72ba7a3c1ad38ba9e13bb54ef21d6ef44ffb.1748149855.git.deren.wu@mediatek.com>

From: Deren Wu <deren.wu at mediatek.com>

The decap offload configuration should only be applied after the STA has
been successfully initialized. Attempting to configure it earlier can lead
to corruption of the MAC configuration in the chip's hardware state.

Add an early check for `msta->deflink.wcid.sta` to ensure the station peer
is properly initialized before proceeding with decapsulation offload
configuration.

Cc: stable at vger.kernel.org
Fixes: 24299fc869f7 ("mt76: mt7921: enable rx header traslation offload")
Signed-off-by: Deren Wu <deren.wu at mediatek.com>
---
 drivers/net/wireless/mediatek/mt76/mt7921/main.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/main.c b/drivers/net/wireless/mediatek/mt76/mt7921/main.c
index 1fffa43379b2..77f73ae1d7ec 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7921/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7921/main.c
@@ -1180,6 +1180,9 @@ static void mt7921_sta_set_decap_offload(struct ieee80211_hw *hw,
 	struct mt792x_sta *msta = (struct mt792x_sta *)sta->drv_priv;
 	struct mt792x_dev *dev = mt792x_hw_dev(hw);
 
+	if (!msta->deflink.wcid.sta)
+		return;
+
 	mt792x_mutex_acquire(dev);
 
 	if (enabled)
-- 
2.18.0



From christophe.jaillet at wanadoo.fr  Sun May 25 02:40:04 2025
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Sun, 25 May 2025 11:40:04 +0200
Subject: [PATCH] thermal: Constify struct thermal_zone_device_ops
Message-ID: <5bba3bf0139e2418b306a0f9a2f1f81ef49e88a6.1748165978.git.christophe.jaillet@wanadoo.fr>

'struct thermal_zone_device_ops' are not modified in these drivers.

Constifying these structures moves some data to a read-only section, so
increases overall security, especially when the structure holds some
function pointers.

On a x86_64, with allmodconfig, as an example:
Before:
======
   text	   data	    bss	    dec	    hex	filename
  28116	   5168	    128	  33412	   8284	drivers/thermal/armada_thermal.o

After:
=====
   text	   data	    bss	    dec	    hex	filename
  28244	   5040	    128	  33412	   8284	drivers/thermal/armada_thermal.o

Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
---
Compile tested only
---
 drivers/thermal/armada_thermal.c                        | 2 +-
 drivers/thermal/da9062-thermal.c                        | 2 +-
 drivers/thermal/dove_thermal.c                          | 2 +-
 drivers/thermal/imx_thermal.c                           | 2 +-
 drivers/thermal/intel/int340x_thermal/int3400_thermal.c | 2 +-
 drivers/thermal/kirkwood_thermal.c                      | 2 +-
 drivers/thermal/mediatek/lvts_thermal.c                 | 2 +-
 drivers/thermal/renesas/rcar_thermal.c                  | 2 +-
 drivers/thermal/spear_thermal.c                         | 2 +-
 drivers/thermal/st/st_thermal.c                         | 2 +-
 drivers/thermal/testing/zone.c                          | 2 +-
 11 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c
index 9bff21068721..c2fbdb534f61 100644
--- a/drivers/thermal/armada_thermal.c
+++ b/drivers/thermal/armada_thermal.c
@@ -408,7 +408,7 @@ static int armada_get_temp_legacy(struct thermal_zone_device *thermal,
 	return ret;
 }
 
-static struct thermal_zone_device_ops legacy_ops = {
+static const struct thermal_zone_device_ops legacy_ops = {
 	.get_temp = armada_get_temp_legacy,
 };
 
diff --git a/drivers/thermal/da9062-thermal.c b/drivers/thermal/da9062-thermal.c
index 2077e85ef5ca..a8d4b766ba21 100644
--- a/drivers/thermal/da9062-thermal.c
+++ b/drivers/thermal/da9062-thermal.c
@@ -137,7 +137,7 @@ static int da9062_thermal_get_temp(struct thermal_zone_device *z,
 	return 0;
 }
 
-static struct thermal_zone_device_ops da9062_thermal_ops = {
+static const struct thermal_zone_device_ops da9062_thermal_ops = {
 	.get_temp	= da9062_thermal_get_temp,
 };
 
diff --git a/drivers/thermal/dove_thermal.c b/drivers/thermal/dove_thermal.c
index f9157a47156b..723bc72f0626 100644
--- a/drivers/thermal/dove_thermal.c
+++ b/drivers/thermal/dove_thermal.c
@@ -106,7 +106,7 @@ static int dove_get_temp(struct thermal_zone_device *thermal,
 	return 0;
 }
 
-static struct thermal_zone_device_ops ops = {
+static const struct thermal_zone_device_ops ops = {
 	.get_temp = dove_get_temp,
 };
 
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index bab52e6b3b15..38c993d1bcb3 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -361,7 +361,7 @@ static bool imx_should_bind(struct thermal_zone_device *tz,
 	return trip->type == THERMAL_TRIP_PASSIVE;
 }
 
-static struct thermal_zone_device_ops imx_tz_ops = {
+static const struct thermal_zone_device_ops imx_tz_ops = {
 	.should_bind = imx_should_bind,
 	.get_temp = imx_get_temp,
 	.change_mode = imx_change_mode,
diff --git a/drivers/thermal/intel/int340x_thermal/int3400_thermal.c b/drivers/thermal/intel/int340x_thermal/int3400_thermal.c
index 0e07693ecf59..5736638c586b 100644
--- a/drivers/thermal/intel/int340x_thermal/int3400_thermal.c
+++ b/drivers/thermal/intel/int340x_thermal/int3400_thermal.c
@@ -515,7 +515,7 @@ static int int3400_thermal_change_mode(struct thermal_zone_device *thermal,
 	return result;
 }
 
-static struct thermal_zone_device_ops int3400_thermal_ops = {
+static const struct thermal_zone_device_ops int3400_thermal_ops = {
 	.get_temp = int3400_thermal_get_temp,
 	.change_mode = int3400_thermal_change_mode,
 };
diff --git a/drivers/thermal/kirkwood_thermal.c b/drivers/thermal/kirkwood_thermal.c
index 7c2265231668..4619e090f756 100644
--- a/drivers/thermal/kirkwood_thermal.c
+++ b/drivers/thermal/kirkwood_thermal.c
@@ -48,7 +48,7 @@ static int kirkwood_get_temp(struct thermal_zone_device *thermal,
 	return 0;
 }
 
-static struct thermal_zone_device_ops ops = {
+static const struct thermal_zone_device_ops ops = {
 	.get_temp = kirkwood_get_temp,
 };
 
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index 985925147ac0..acce8fde2cba 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -571,7 +571,7 @@ static irqreturn_t lvts_irq_handler(int irq, void *data)
 	return iret;
 }
 
-static struct thermal_zone_device_ops lvts_ops = {
+static const struct thermal_zone_device_ops lvts_ops = {
 	.get_temp = lvts_get_temp,
 	.set_trips = lvts_set_trips,
 };
diff --git a/drivers/thermal/renesas/rcar_thermal.c b/drivers/thermal/renesas/rcar_thermal.c
index 00a66ee0a5b0..fdd7afdc4ff6 100644
--- a/drivers/thermal/renesas/rcar_thermal.c
+++ b/drivers/thermal/renesas/rcar_thermal.c
@@ -277,7 +277,7 @@ static int rcar_thermal_get_temp(struct thermal_zone_device *zone, int *temp)
 	return rcar_thermal_get_current_temp(priv, temp);
 }
 
-static struct thermal_zone_device_ops rcar_thermal_zone_ops = {
+static const struct thermal_zone_device_ops rcar_thermal_zone_ops = {
 	.get_temp	= rcar_thermal_get_temp,
 };
 
diff --git a/drivers/thermal/spear_thermal.c b/drivers/thermal/spear_thermal.c
index bb96be947521..603dadcd3df5 100644
--- a/drivers/thermal/spear_thermal.c
+++ b/drivers/thermal/spear_thermal.c
@@ -41,7 +41,7 @@ static inline int thermal_get_temp(struct thermal_zone_device *thermal,
 	return 0;
 }
 
-static struct thermal_zone_device_ops ops = {
+static const struct thermal_zone_device_ops ops = {
 	.get_temp = thermal_get_temp,
 };
 
diff --git a/drivers/thermal/st/st_thermal.c b/drivers/thermal/st/st_thermal.c
index a14a37d54698..1470ca519def 100644
--- a/drivers/thermal/st/st_thermal.c
+++ b/drivers/thermal/st/st_thermal.c
@@ -132,7 +132,7 @@ static int st_thermal_get_temp(struct thermal_zone_device *th, int *temperature)
 	return 0;
 }
 
-static struct thermal_zone_device_ops st_tz_ops = {
+static const struct thermal_zone_device_ops st_tz_ops = {
 	.get_temp	= st_thermal_get_temp,
 };
 
diff --git a/drivers/thermal/testing/zone.c b/drivers/thermal/testing/zone.c
index 1f4e450100e2..4257d813d572 100644
--- a/drivers/thermal/testing/zone.c
+++ b/drivers/thermal/testing/zone.c
@@ -381,7 +381,7 @@ static int tt_zone_get_temp(struct thermal_zone_device *tz, int *temp)
 	return 0;
 }
 
-static struct thermal_zone_device_ops tt_zone_ops = {
+static const struct thermal_zone_device_ops tt_zone_ops = {
 	.get_temp = tt_zone_get_temp,
 };
 
-- 
2.49.0



From niklas.soderlund at ragnatech.se  Sun May 25 03:19:50 2025
From: niklas.soderlund at ragnatech.se (Niklas =?utf-8?Q?S=C3=B6derlund?=)
Date: Sun, 25 May 2025 12:19:50 +0200
Subject: [PATCH] thermal: Constify struct thermal_zone_device_ops
In-Reply-To: <5bba3bf0139e2418b306a0f9a2f1f81ef49e88a6.1748165978.git.christophe.jaillet@wanadoo.fr>
References: <5bba3bf0139e2418b306a0f9a2f1f81ef49e88a6.1748165978.git.christophe.jaillet@wanadoo.fr>
Message-ID: <20250525101950.GE600042@ragnatech.se>

Hi Christophe,

Thanks for your work.

On 2025-05-25 11:40:04 +0200, Christophe JAILLET wrote:
> 'struct thermal_zone_device_ops' are not modified in these drivers.
> 
> Constifying these structures moves some data to a read-only section, so
> increases overall security, especially when the structure holds some
> function pointers.
> 
> On a x86_64, with allmodconfig, as an example:
> Before:
> ======
>    text	   data	    bss	    dec	    hex	filename
>   28116	   5168	    128	  33412	   8284	drivers/thermal/armada_thermal.o
> 
> After:
> =====
>    text	   data	    bss	    dec	    hex	filename
>   28244	   5040	    128	  33412	   8284	drivers/thermal/armada_thermal.o
> 
> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
> ---
> Compile tested only
> ---
>  drivers/thermal/armada_thermal.c                        | 2 +-
>  drivers/thermal/da9062-thermal.c                        | 2 +-
>  drivers/thermal/dove_thermal.c                          | 2 +-
>  drivers/thermal/imx_thermal.c                           | 2 +-
>  drivers/thermal/intel/int340x_thermal/int3400_thermal.c | 2 +-
>  drivers/thermal/kirkwood_thermal.c                      | 2 +-
>  drivers/thermal/mediatek/lvts_thermal.c                 | 2 +-
>  drivers/thermal/renesas/rcar_thermal.c                  | 2 +-

For R-Car,

Reviewed-by: Niklas S?derlund <niklas.soderlund+renesas at ragnatech.se>

>  drivers/thermal/spear_thermal.c                         | 2 +-
>  drivers/thermal/st/st_thermal.c                         | 2 +-
>  drivers/thermal/testing/zone.c                          | 2 +-
>  11 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c
> index 9bff21068721..c2fbdb534f61 100644
> --- a/drivers/thermal/armada_thermal.c
> +++ b/drivers/thermal/armada_thermal.c
> @@ -408,7 +408,7 @@ static int armada_get_temp_legacy(struct thermal_zone_device *thermal,
>  	return ret;
>  }
>  
> -static struct thermal_zone_device_ops legacy_ops = {
> +static const struct thermal_zone_device_ops legacy_ops = {
>  	.get_temp = armada_get_temp_legacy,
>  };
>  
> diff --git a/drivers/thermal/da9062-thermal.c b/drivers/thermal/da9062-thermal.c
> index 2077e85ef5ca..a8d4b766ba21 100644
> --- a/drivers/thermal/da9062-thermal.c
> +++ b/drivers/thermal/da9062-thermal.c
> @@ -137,7 +137,7 @@ static int da9062_thermal_get_temp(struct thermal_zone_device *z,
>  	return 0;
>  }
>  
> -static struct thermal_zone_device_ops da9062_thermal_ops = {
> +static const struct thermal_zone_device_ops da9062_thermal_ops = {
>  	.get_temp	= da9062_thermal_get_temp,
>  };
>  
> diff --git a/drivers/thermal/dove_thermal.c b/drivers/thermal/dove_thermal.c
> index f9157a47156b..723bc72f0626 100644
> --- a/drivers/thermal/dove_thermal.c
> +++ b/drivers/thermal/dove_thermal.c
> @@ -106,7 +106,7 @@ static int dove_get_temp(struct thermal_zone_device *thermal,
>  	return 0;
>  }
>  
> -static struct thermal_zone_device_ops ops = {
> +static const struct thermal_zone_device_ops ops = {
>  	.get_temp = dove_get_temp,
>  };
>  
> diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
> index bab52e6b3b15..38c993d1bcb3 100644
> --- a/drivers/thermal/imx_thermal.c
> +++ b/drivers/thermal/imx_thermal.c
> @@ -361,7 +361,7 @@ static bool imx_should_bind(struct thermal_zone_device *tz,
>  	return trip->type == THERMAL_TRIP_PASSIVE;
>  }
>  
> -static struct thermal_zone_device_ops imx_tz_ops = {
> +static const struct thermal_zone_device_ops imx_tz_ops = {
>  	.should_bind = imx_should_bind,
>  	.get_temp = imx_get_temp,
>  	.change_mode = imx_change_mode,
> diff --git a/drivers/thermal/intel/int340x_thermal/int3400_thermal.c b/drivers/thermal/intel/int340x_thermal/int3400_thermal.c
> index 0e07693ecf59..5736638c586b 100644
> --- a/drivers/thermal/intel/int340x_thermal/int3400_thermal.c
> +++ b/drivers/thermal/intel/int340x_thermal/int3400_thermal.c
> @@ -515,7 +515,7 @@ static int int3400_thermal_change_mode(struct thermal_zone_device *thermal,
>  	return result;
>  }
>  
> -static struct thermal_zone_device_ops int3400_thermal_ops = {
> +static const struct thermal_zone_device_ops int3400_thermal_ops = {
>  	.get_temp = int3400_thermal_get_temp,
>  	.change_mode = int3400_thermal_change_mode,
>  };
> diff --git a/drivers/thermal/kirkwood_thermal.c b/drivers/thermal/kirkwood_thermal.c
> index 7c2265231668..4619e090f756 100644
> --- a/drivers/thermal/kirkwood_thermal.c
> +++ b/drivers/thermal/kirkwood_thermal.c
> @@ -48,7 +48,7 @@ static int kirkwood_get_temp(struct thermal_zone_device *thermal,
>  	return 0;
>  }
>  
> -static struct thermal_zone_device_ops ops = {
> +static const struct thermal_zone_device_ops ops = {
>  	.get_temp = kirkwood_get_temp,
>  };
>  
> diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
> index 985925147ac0..acce8fde2cba 100644
> --- a/drivers/thermal/mediatek/lvts_thermal.c
> +++ b/drivers/thermal/mediatek/lvts_thermal.c
> @@ -571,7 +571,7 @@ static irqreturn_t lvts_irq_handler(int irq, void *data)
>  	return iret;
>  }
>  
> -static struct thermal_zone_device_ops lvts_ops = {
> +static const struct thermal_zone_device_ops lvts_ops = {
>  	.get_temp = lvts_get_temp,
>  	.set_trips = lvts_set_trips,
>  };
> diff --git a/drivers/thermal/renesas/rcar_thermal.c b/drivers/thermal/renesas/rcar_thermal.c
> index 00a66ee0a5b0..fdd7afdc4ff6 100644
> --- a/drivers/thermal/renesas/rcar_thermal.c
> +++ b/drivers/thermal/renesas/rcar_thermal.c
> @@ -277,7 +277,7 @@ static int rcar_thermal_get_temp(struct thermal_zone_device *zone, int *temp)
>  	return rcar_thermal_get_current_temp(priv, temp);
>  }
>  
> -static struct thermal_zone_device_ops rcar_thermal_zone_ops = {
> +static const struct thermal_zone_device_ops rcar_thermal_zone_ops = {
>  	.get_temp	= rcar_thermal_get_temp,
>  };
>  
> diff --git a/drivers/thermal/spear_thermal.c b/drivers/thermal/spear_thermal.c
> index bb96be947521..603dadcd3df5 100644
> --- a/drivers/thermal/spear_thermal.c
> +++ b/drivers/thermal/spear_thermal.c
> @@ -41,7 +41,7 @@ static inline int thermal_get_temp(struct thermal_zone_device *thermal,
>  	return 0;
>  }
>  
> -static struct thermal_zone_device_ops ops = {
> +static const struct thermal_zone_device_ops ops = {
>  	.get_temp = thermal_get_temp,
>  };
>  
> diff --git a/drivers/thermal/st/st_thermal.c b/drivers/thermal/st/st_thermal.c
> index a14a37d54698..1470ca519def 100644
> --- a/drivers/thermal/st/st_thermal.c
> +++ b/drivers/thermal/st/st_thermal.c
> @@ -132,7 +132,7 @@ static int st_thermal_get_temp(struct thermal_zone_device *th, int *temperature)
>  	return 0;
>  }
>  
> -static struct thermal_zone_device_ops st_tz_ops = {
> +static const struct thermal_zone_device_ops st_tz_ops = {
>  	.get_temp	= st_thermal_get_temp,
>  };
>  
> diff --git a/drivers/thermal/testing/zone.c b/drivers/thermal/testing/zone.c
> index 1f4e450100e2..4257d813d572 100644
> --- a/drivers/thermal/testing/zone.c
> +++ b/drivers/thermal/testing/zone.c
> @@ -381,7 +381,7 @@ static int tt_zone_get_temp(struct thermal_zone_device *tz, int *temp)
>  	return 0;
>  }
>  
> -static struct thermal_zone_device_ops tt_zone_ops = {
> +static const struct thermal_zone_device_ops tt_zone_ops = {
>  	.get_temp = tt_zone_get_temp,
>  };
>  
> -- 
> 2.49.0
> 

-- 
Kind Regards,
Niklas S?derlund


From daniel at fooishbar.org  Sun May 25 03:48:44 2025
From: daniel at fooishbar.org (Daniel Stone)
Date: Sun, 25 May 2025 11:48:44 +0100
Subject: [PATCH] media: dt-bindings: mediatek: Constrain iommus
In-Reply-To: <20250525051639.68753-2-krzysztof.kozlowski@linaro.org>
References: <20250525051639.68753-2-krzysztof.kozlowski@linaro.org>
Message-ID: <CAPj87rMjAv-UphvFuQjop60o=wHrkfs4-XOM=JqH7f8Kk5dyVg@mail.gmail.com>

On Sun, 25 May 2025 at 06:16, Krzysztof Kozlowski
<krzysztof.kozlowski at linaro.org> wrote:
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> @@ -45,9 +45,8 @@ properties:
>        - description: OVL-2L Clock
>
>    iommus:
> -    description:
> -      This property should point to the respective IOMMU block with master port as argument,
> -      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> +    minItems: 1
> +    maxItems: 2

The comment removals are not documented in the commit message, and
it's not clear why removing information and references would be a good
thing.

Please see https://www.kernel.org/doc/html/latest/process/submitting-patches.html
for information on how to submit good-quality patches that can be
better reviwed by maintainers.


From krzk at kernel.org  Sun May 25 03:51:50 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Sun, 25 May 2025 12:51:50 +0200
Subject: [PATCH] media: dt-bindings: mediatek: Constrain iommus
In-Reply-To: <CAPj87rMjAv-UphvFuQjop60o=wHrkfs4-XOM=JqH7f8Kk5dyVg@mail.gmail.com>
References: <20250525051639.68753-2-krzysztof.kozlowski@linaro.org>
 <CAPj87rMjAv-UphvFuQjop60o=wHrkfs4-XOM=JqH7f8Kk5dyVg@mail.gmail.com>
Message-ID: <e462cdc4-7243-4cef-bd1d-a0ef551b3a87@kernel.org>

On 25/05/2025 12:48, Daniel Stone wrote:
> On Sun, 25 May 2025 at 06:16, Krzysztof Kozlowski
> <krzysztof.kozlowski at linaro.org> wrote:
>> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
>> @@ -45,9 +45,8 @@ properties:
>>        - description: OVL-2L Clock
>>
>>    iommus:
>> -    description:
>> -      This property should point to the respective IOMMU block with master port as argument,
>> -      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
>> +    minItems: 1
>> +    maxItems: 2
> 
> The comment removals are not documented in the commit message, and
> it's not clear why removing information and references would be a good
> thing.
It's obvious, isn't? The consumer shall not define which provider has to
use or how many cells provider has.

Best regards,
Krzysztof


From aford173 at gmail.com  Sun May 25 05:58:49 2025
From: aford173 at gmail.com (Adam Ford)
Date: Sun, 25 May 2025 07:58:49 -0500
Subject: [PATCH 01/34] drm: convert many bridge drivers from
 devm_kzalloc() to devm_drm_bridge_alloc() API
In-Reply-To: <20250407-drm-bridge-convert-to-alloc-api-v1-1-42113ff8d9c0@bootlin.com>
References: <20250407-drm-bridge-convert-to-alloc-api-v1-0-42113ff8d9c0@bootlin.com>
 <20250407-drm-bridge-convert-to-alloc-api-v1-1-42113ff8d9c0@bootlin.com>
Message-ID: <CAHCN7xKefTM-iDTLimJxr18FaSSa0h+C2og9PmjQQyTQWWhs1g@mail.gmail.com>

On Mon, Apr 7, 2025 at 9:24?AM Luca Ceresoli <luca.ceresoli at bootlin.com> wrote:
>
> devm_drm_bridge_alloc() is the new API to be used for allocating (and
> partially initializing) a private driver struct embedding a struct
> drm_bridge.
>
> For many drivers having a simple code flow in the probe function, this
> commit does a mass conversion automatically with the following semantic
> patch. The changes have been reviewed manually for correctness as well as
> to find any false positives.
>
>   @@
>   type T;
>   identifier C;
>   identifier BR;
>   expression DEV;
>   expression FUNCS;
>   @@
>   -T *C;
>   +T *C;
>    ...
>   (
>   -C = devm_kzalloc(DEV, ...);
>   -if (!C)
>   -    return -ENOMEM;
>   +C = devm_drm_bridge_alloc(DEV, T, BR, FUNCS);
>   +if (IS_ERR(C))
>   +     return PTR_ERR(C);
>   |
>   -C = devm_kzalloc(DEV, ...);
>   -if (!C)
>   -    return ERR_PTR(-ENOMEM);
>   +C = devm_drm_bridge_alloc(DEV, T, BR, FUNCS);
>   +if (IS_ERR(C))
>   +     return C;
>   )
>    ...
>   -C->BR.funcs = FUNCS;
>
> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
>


For fsl-ldb.c:

Tested-by: Adam Ford <aford173 at gmail.com> # imx8mp-beacon-kit


> ---
>
> Cc: Adam Ford <aford173 at gmail.com>
> Cc: Adrien Grassein <adrien.grassein at gmail.com>
> Cc: Aleksandr Mishin <amishin at t-argos.ru>
> Cc: Andy Yan <andy.yan at rock-chips.com>
> Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Cc: Benson Leung <bleung at chromium.org>
> Cc: Biju Das <biju.das.jz at bp.renesas.com>
> Cc: Christoph Fritz <chf.fritz at googlemail.com>
> Cc: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
> Cc: Detlev Casanova <detlev.casanova at collabora.com>
> Cc: Dharma Balasubiramani <dharma.b at microchip.com>
> Cc: Guenter Roeck <groeck at chromium.org>
> Cc: Heiko Stuebner <heiko at sntech.de>
> Cc: Jani Nikula <jani.nikula at intel.com>
> Cc: Janne Grunau <j at jannau.net>
> Cc: Jerome Brunet <jbrunet at baylibre.com>
> Cc: Jesse Van Gavere <jesseevg at gmail.com>
> Cc: Kevin Hilman <khilman at baylibre.com>
> Cc: Kieran Bingham <kieran.bingham+renesas at ideasonboard.com>
> Cc: Liu Ying <victor.liu at nxp.com>
> Cc: Manikandan Muralidharan <manikandan.m at microchip.com>
> Cc: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
> Cc: Matthias Brugger <matthias.bgg at gmail.com>
> Cc: Philipp Zabel <p.zabel at pengutronix.de>
> Cc: Phong LE <ple at baylibre.com>
> Cc: Sasha Finkelstein <fnkl.kernel at gmail.com>
> Cc: Sugar Zhang <sugar.zhang at rock-chips.com>
> Cc: Sui Jingfeng <sui.jingfeng at linux.dev>
> Cc: Tomi Valkeinen <tomi.valkeinen+renesas at ideasonboard.com>
> Cc: Vitalii Mordan <mordan at ispras.ru>
> ---
>  drivers/gpu/drm/adp/adp-mipi.c                      |  8 ++++----
>  drivers/gpu/drm/bridge/adv7511/adv7511_drv.c        |  9 ++++-----
>  drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c  |  9 ++++-----
>  drivers/gpu/drm/bridge/aux-bridge.c                 |  9 ++++-----
>  drivers/gpu/drm/bridge/aux-hpd-bridge.c             |  9 +++++----
>  drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c |  8 ++++----
>  drivers/gpu/drm/bridge/chipone-icn6211.c            |  9 ++++-----
>  drivers/gpu/drm/bridge/chrontel-ch7033.c            |  8 ++++----
>  drivers/gpu/drm/bridge/cros-ec-anx7688.c            |  9 ++++-----
>  drivers/gpu/drm/bridge/fsl-ldb.c                    |  7 +++----
>  drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c      |  9 ++++-----
>  drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c        | 10 ++++------
>  drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c     |  8 ++++----
>  drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c        |  8 ++++----
>  drivers/gpu/drm/bridge/ite-it6263.c                 |  9 ++++-----
>  drivers/gpu/drm/bridge/ite-it6505.c                 |  9 ++++-----
>  drivers/gpu/drm/bridge/ite-it66121.c                |  9 ++++-----
>  drivers/gpu/drm/bridge/lontium-lt8912b.c            |  9 ++++-----
>  drivers/gpu/drm/bridge/lontium-lt9211.c             |  8 +++-----
>  drivers/gpu/drm/bridge/lontium-lt9611.c             |  9 ++++-----
>  drivers/gpu/drm/bridge/lvds-codec.c                 |  9 ++++-----
>  drivers/gpu/drm/bridge/microchip-lvds.c             |  8 ++++----
>  drivers/gpu/drm/bridge/nwl-dsi.c                    |  8 ++++----
>  drivers/gpu/drm/bridge/parade-ps8622.c              |  9 ++++-----
>  drivers/gpu/drm/bridge/parade-ps8640.c              |  9 ++++-----
>  drivers/gpu/drm/bridge/sii9234.c                    |  9 ++++-----
>  drivers/gpu/drm/bridge/sil-sii8620.c                |  9 ++++-----
>  drivers/gpu/drm/bridge/simple-bridge.c              | 10 ++++------
>  drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c        |  8 ++++----
>  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c       |  8 ++++----
>  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c      |  8 ++++----
>  drivers/gpu/drm/bridge/tc358762.c                   |  9 ++++-----
>  drivers/gpu/drm/bridge/tc358764.c                   |  9 ++++-----
>  drivers/gpu/drm/bridge/tc358768.c                   |  9 ++++-----
>  drivers/gpu/drm/bridge/tc358775.c                   |  9 ++++-----
>  drivers/gpu/drm/bridge/thc63lvd1024.c               |  8 ++++----
>  drivers/gpu/drm/bridge/ti-dlpc3433.c                |  9 ++++-----
>  drivers/gpu/drm/bridge/ti-tdp158.c                  |  8 ++++----
>  drivers/gpu/drm/bridge/ti-tfp410.c                  |  9 ++++-----
>  drivers/gpu/drm/bridge/ti-tpd12s015.c               |  9 ++++-----
>  drivers/gpu/drm/mediatek/mtk_dp.c                   |  9 ++++-----
>  drivers/gpu/drm/mediatek/mtk_dpi.c                  |  9 ++++-----
>  drivers/gpu/drm/mediatek/mtk_dsi.c                  |  9 ++++-----
>  drivers/gpu/drm/mediatek/mtk_hdmi.c                 |  9 ++++-----
>  drivers/gpu/drm/meson/meson_encoder_cvbs.c          | 12 ++++++------
>  drivers/gpu/drm/meson/meson_encoder_dsi.c           | 12 ++++++------
>  drivers/gpu/drm/meson/meson_encoder_hdmi.c          | 12 ++++++------
>  drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c         |  9 ++++-----
>  drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c      | 10 ++++------
>  49 files changed, 201 insertions(+), 237 deletions(-)
>
> diff --git a/drivers/gpu/drm/adp/adp-mipi.c b/drivers/gpu/drm/adp/adp-mipi.c
> index 2b60128e2c693e9f85affff569cc57cdb6f47909..cba7d32150a98d78d07a25b1822dec6bf2f08f65 100644
> --- a/drivers/gpu/drm/adp/adp-mipi.c
> +++ b/drivers/gpu/drm/adp/adp-mipi.c
> @@ -229,9 +229,10 @@ static int adp_mipi_probe(struct platform_device *pdev)
>  {
>         struct adp_mipi_drv_private *adp;
>
> -       adp = devm_kzalloc(&pdev->dev, sizeof(*adp), GFP_KERNEL);
> -       if (!adp)
> -               return -ENOMEM;
> +       adp = devm_drm_bridge_alloc(&pdev->dev, struct adp_mipi_drv_private,
> +                                   bridge, &adp_dsi_bridge_funcs);
> +       if (IS_ERR(adp))
> +               return PTR_ERR(adp);
>
>         adp->mipi = devm_platform_ioremap_resource(pdev, 0);
>         if (IS_ERR(adp->mipi)) {
> @@ -241,7 +242,6 @@ static int adp_mipi_probe(struct platform_device *pdev)
>
>         adp->dsi.dev = &pdev->dev;
>         adp->dsi.ops = &adp_dsi_host_ops;
> -       adp->bridge.funcs = &adp_dsi_bridge_funcs;
>         adp->bridge.of_node = pdev->dev.of_node;
>         adp->bridge.type = DRM_MODE_CONNECTOR_DSI;
>         dev_set_drvdata(&pdev->dev, adp);
> diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> index 1257009e850c1b20184cfaea5b6a4440e75e10d7..4411987cd85109b83e3d4d45e842ee9cf8d21aab 100644
> --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> @@ -1224,9 +1224,10 @@ static int adv7511_probe(struct i2c_client *i2c)
>         if (!dev->of_node)
>                 return -EINVAL;
>
> -       adv7511 = devm_kzalloc(dev, sizeof(*adv7511), GFP_KERNEL);
> -       if (!adv7511)
> -               return -ENOMEM;
> +       adv7511 = devm_drm_bridge_alloc(dev, struct adv7511, bridge,
> +                                       &adv7511_bridge_funcs);
> +       if (IS_ERR(adv7511))
> +               return PTR_ERR(adv7511);
>
>         adv7511->i2c_main = i2c;
>         adv7511->powered = false;
> @@ -1326,8 +1327,6 @@ static int adv7511_probe(struct i2c_client *i2c)
>         ret = adv7511_cec_init(dev, adv7511);
>         if (ret)
>                 goto err_unregister_cec;
> -
> -       adv7511->bridge.funcs = &adv7511_bridge_funcs;
>         adv7511->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID;
>         if (adv7511->i2c_main->irq)
>                 adv7511->bridge.ops |= DRM_BRIDGE_OP_HPD;
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> index a83020d6576f78372056069947783a626acf64b1..ba0fc149a9e722a53da6027a851bf62262ba64b2 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> @@ -1193,9 +1193,10 @@ static int anx78xx_i2c_probe(struct i2c_client *client)
>         bool found = false;
>         int err;
>
> -       anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL);
> -       if (!anx78xx)
> -               return -ENOMEM;
> +       anx78xx = devm_drm_bridge_alloc(&client->dev, struct anx78xx, bridge,
> +                                       &anx78xx_bridge_funcs);
> +       if (IS_ERR(anx78xx))
> +               return PTR_ERR(anx78xx);
>
>         pdata = &anx78xx->pdata;
>
> @@ -1306,8 +1307,6 @@ static int anx78xx_i2c_probe(struct i2c_client *client)
>                 goto err_poweroff;
>         }
>
> -       anx78xx->bridge.funcs = &anx78xx_bridge_funcs;
> -
>         drm_bridge_add(&anx78xx->bridge);
>
>         /* If cable is pulled out, just poweroff and wait for HPD event */
> diff --git a/drivers/gpu/drm/bridge/aux-bridge.c b/drivers/gpu/drm/bridge/aux-bridge.c
> index c179b86d208f70d95b41e6f2157b78f97bac4d8d..ea9109bdbe088da4ea3411845bf6f27a50e2cebf 100644
> --- a/drivers/gpu/drm/bridge/aux-bridge.c
> +++ b/drivers/gpu/drm/bridge/aux-bridge.c
> @@ -109,17 +109,16 @@ static int drm_aux_bridge_probe(struct auxiliary_device *auxdev,
>  {
>         struct drm_aux_bridge_data *data;
>
> -       data = devm_kzalloc(&auxdev->dev, sizeof(*data), GFP_KERNEL);
> -       if (!data)
> -               return -ENOMEM;
> +       data = devm_drm_bridge_alloc(&auxdev->dev, struct drm_aux_bridge_data,
> +                                    bridge, &drm_aux_bridge_funcs);
> +       if (IS_ERR(data))
> +               return PTR_ERR(data);
>
>         data->dev = &auxdev->dev;
>         data->next_bridge = devm_drm_of_get_bridge(&auxdev->dev, auxdev->dev.of_node, 0, 0);
>         if (IS_ERR(data->next_bridge))
>                 return dev_err_probe(&auxdev->dev, PTR_ERR(data->next_bridge),
>                                      "failed to acquire drm_bridge\n");
> -
> -       data->bridge.funcs = &drm_aux_bridge_funcs;
>         data->bridge.of_node = data->dev->of_node;
>
>         /* passthrough data, allow everything */
> diff --git a/drivers/gpu/drm/bridge/aux-hpd-bridge.c b/drivers/gpu/drm/bridge/aux-hpd-bridge.c
> index b3f588b71a7d7ad5c2ee7b07c39079bc5ba34cee..3eb411f874e41b322f732649bd2074c5d8422566 100644
> --- a/drivers/gpu/drm/bridge/aux-hpd-bridge.c
> +++ b/drivers/gpu/drm/bridge/aux-hpd-bridge.c
> @@ -171,12 +171,13 @@ static int drm_aux_hpd_bridge_probe(struct auxiliary_device *auxdev,
>  {
>         struct drm_aux_hpd_bridge_data *data;
>
> -       data = devm_kzalloc(&auxdev->dev, sizeof(*data), GFP_KERNEL);
> -       if (!data)
> -               return -ENOMEM;
> +       data = devm_drm_bridge_alloc(&auxdev->dev,
> +                                    struct drm_aux_hpd_bridge_data, bridge,
> +                                    &drm_aux_hpd_bridge_funcs);
> +       if (IS_ERR(data))
> +               return PTR_ERR(data);
>
>         data->dev = &auxdev->dev;
> -       data->bridge.funcs = &drm_aux_hpd_bridge_funcs;
>         data->bridge.of_node = dev_get_platdata(data->dev);
>         data->bridge.ops = DRM_BRIDGE_OP_HPD;
>         data->bridge.type = id->driver_data;
> diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> index b431e7efd1f0d749320ea15b6f1f5ca13fc72800..cb5f5a8c539a471290df8435d4c2e3ed696b38d4 100644
> --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> @@ -2389,9 +2389,10 @@ static int cdns_mhdp_probe(struct platform_device *pdev)
>         int ret;
>         int irq;
>
> -       mhdp = devm_kzalloc(dev, sizeof(*mhdp), GFP_KERNEL);
> -       if (!mhdp)
> -               return -ENOMEM;
> +       mhdp = devm_drm_bridge_alloc(dev, struct cdns_mhdp_device, bridge,
> +                                    &cdns_mhdp_bridge_funcs);
> +       if (IS_ERR(mhdp))
> +               return PTR_ERR(mhdp);
>
>         clk = devm_clk_get_enabled(dev, NULL);
>         if (IS_ERR(clk)) {
> @@ -2481,7 +2482,6 @@ static int cdns_mhdp_probe(struct platform_device *pdev)
>         mhdp->display_fmt.bpc = 8;
>
>         mhdp->bridge.of_node = pdev->dev.of_node;
> -       mhdp->bridge.funcs = &cdns_mhdp_bridge_funcs;
>         mhdp->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
>                            DRM_BRIDGE_OP_HPD;
>         mhdp->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
> diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c b/drivers/gpu/drm/bridge/chipone-icn6211.c
> index 634c5b0306679d2e68798c2b9013aae4491dd44c..9989c6a6f3414295788e77d561ee5b807abc602e 100644
> --- a/drivers/gpu/drm/bridge/chipone-icn6211.c
> +++ b/drivers/gpu/drm/bridge/chipone-icn6211.c
> @@ -691,17 +691,16 @@ static int chipone_common_probe(struct device *dev, struct chipone **icnr)
>         struct chipone *icn;
>         int ret;
>
> -       icn = devm_kzalloc(dev, sizeof(struct chipone), GFP_KERNEL);
> -       if (!icn)
> -               return -ENOMEM;
> +       icn = devm_drm_bridge_alloc(dev, struct chipone, bridge,
> +                                   &chipone_bridge_funcs);
> +       if (IS_ERR(icn))
> +               return PTR_ERR(icn);
>
>         icn->dev = dev;
>
>         ret = chipone_parse_dt(icn);
>         if (ret)
>                 return ret;
> -
> -       icn->bridge.funcs = &chipone_bridge_funcs;
>         icn->bridge.type = DRM_MODE_CONNECTOR_DPI;
>         icn->bridge.of_node = dev->of_node;
>
> diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c b/drivers/gpu/drm/bridge/chrontel-ch7033.c
> index 210c45c1efd48f5b541bf73da66a169c27e110b2..ab92747933568bfba77da45219e019408029f297 100644
> --- a/drivers/gpu/drm/bridge/chrontel-ch7033.c
> +++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
> @@ -536,9 +536,10 @@ static int ch7033_probe(struct i2c_client *client)
>         unsigned int val;
>         int ret;
>
> -       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> -       if (!priv)
> -               return -ENOMEM;
> +       priv = devm_drm_bridge_alloc(dev, struct ch7033_priv, bridge,
> +                                    &ch7033_bridge_funcs);
> +       if (IS_ERR(priv))
> +               return PTR_ERR(priv);
>
>         dev_set_drvdata(dev, priv);
>
> @@ -575,7 +576,6 @@ static int ch7033_probe(struct i2c_client *client)
>         }
>
>         INIT_LIST_HEAD(&priv->bridge.list);
> -       priv->bridge.funcs = &ch7033_bridge_funcs;
>         priv->bridge.of_node = dev->of_node;
>         drm_bridge_add(&priv->bridge);
>
> diff --git a/drivers/gpu/drm/bridge/cros-ec-anx7688.c b/drivers/gpu/drm/bridge/cros-ec-anx7688.c
> index c8abd9920fee956cf049bcb09827d658b7939333..ab539143f71059e202baced47091cfc1c9174b7c 100644
> --- a/drivers/gpu/drm/bridge/cros-ec-anx7688.c
> +++ b/drivers/gpu/drm/bridge/cros-ec-anx7688.c
> @@ -103,9 +103,10 @@ static int cros_ec_anx7688_bridge_probe(struct i2c_client *client)
>         u8 buffer[4];
>         int ret;
>
> -       anx7688 = devm_kzalloc(dev, sizeof(*anx7688), GFP_KERNEL);
> -       if (!anx7688)
> -               return -ENOMEM;
> +       anx7688 = devm_drm_bridge_alloc(dev, struct cros_ec_anx7688, bridge,
> +                                       &cros_ec_anx7688_bridge_funcs);
> +       if (IS_ERR(anx7688))
> +               return PTR_ERR(anx7688);
>
>         anx7688->client = client;
>         i2c_set_clientdata(client, anx7688);
> @@ -152,8 +153,6 @@ static int cros_ec_anx7688_bridge_probe(struct i2c_client *client)
>                 /* Warn, but not fail, for backwards compatibility */
>                 DRM_WARN("Old ANX7688 FW version (0x%04x), not filtering\n",
>                          fw_version);
> -
> -       anx7688->bridge.funcs = &cros_ec_anx7688_bridge_funcs;
>         drm_bridge_add(&anx7688->bridge);
>
>         return 0;
> diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
> index 2cb6dfc7a6d3dbdd620a35345204f8fb9cae6651..5c3cf37200bcee1db285c97e2b463c9355ee6acb 100644
> --- a/drivers/gpu/drm/bridge/fsl-ldb.c
> +++ b/drivers/gpu/drm/bridge/fsl-ldb.c
> @@ -298,16 +298,15 @@ static int fsl_ldb_probe(struct platform_device *pdev)
>         struct fsl_ldb *fsl_ldb;
>         int dual_link;
>
> -       fsl_ldb = devm_kzalloc(dev, sizeof(*fsl_ldb), GFP_KERNEL);
> -       if (!fsl_ldb)
> -               return -ENOMEM;
> +       fsl_ldb = devm_drm_bridge_alloc(dev, struct fsl_ldb, bridge, &funcs);
> +       if (IS_ERR(fsl_ldb))
> +               return PTR_ERR(fsl_ldb);
>
>         fsl_ldb->devdata = of_device_get_match_data(dev);
>         if (!fsl_ldb->devdata)
>                 return -EINVAL;
>
>         fsl_ldb->dev = &pdev->dev;
> -       fsl_ldb->bridge.funcs = &funcs;
>         fsl_ldb->bridge.of_node = dev->of_node;
>
>         fsl_ldb->clk = devm_clk_get(dev, "ldb");
> diff --git a/drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c b/drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c
> index f072c6ed39ef183b10518b43bd6d979bc89e36f9..1e30a581645c56baa9aac38deed73425984b3cc9 100644
> --- a/drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c
> +++ b/drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c
> @@ -59,9 +59,10 @@ struct drm_bridge *devm_imx_drm_legacy_bridge(struct device *dev,
>         struct imx_legacy_bridge *imx_bridge;
>         int ret;
>
> -       imx_bridge = devm_kzalloc(dev, sizeof(*imx_bridge), GFP_KERNEL);
> -       if (!imx_bridge)
> -               return ERR_PTR(-ENOMEM);
> +       imx_bridge = devm_drm_bridge_alloc(dev, struct imx_legacy_bridge,
> +                                          base, &imx_legacy_bridge_funcs);
> +       if (IS_ERR(imx_bridge))
> +               return imx_bridge;
>
>         ret = of_get_drm_display_mode(np,
>                                       &imx_bridge->mode,
> @@ -71,8 +72,6 @@ struct drm_bridge *devm_imx_drm_legacy_bridge(struct device *dev,
>                 return ERR_PTR(ret);
>
>         imx_bridge->mode.type |= DRM_MODE_TYPE_DRIVER;
> -
> -       imx_bridge->base.funcs = &imx_legacy_bridge_funcs;
>         imx_bridge->base.of_node = np;
>         imx_bridge->base.ops = DRM_BRIDGE_OP_MODES;
>         imx_bridge->base.type = type;
> diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
> index 8a4fd7d77a8d516b3b46f41cf07d2633d23bde12..18b60bb60e0042a1d031283fecf95c4b7a9312e1 100644
> --- a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
> +++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
> @@ -140,9 +140,10 @@ static int imx8mp_hdmi_pvi_probe(struct platform_device *pdev)
>         struct device_node *remote;
>         struct imx8mp_hdmi_pvi *pvi;
>
> -       pvi = devm_kzalloc(&pdev->dev, sizeof(*pvi), GFP_KERNEL);
> -       if (!pvi)
> -               return -ENOMEM;
> +       pvi = devm_drm_bridge_alloc(&pdev->dev, struct imx8mp_hdmi_pvi,
> +                                   bridge, &imx_hdmi_pvi_bridge_funcs);
> +       if (IS_ERR(pvi))
> +               return PTR_ERR(pvi);
>
>         platform_set_drvdata(pdev, pvi);
>         pvi->dev = &pdev->dev;
> @@ -164,9 +165,6 @@ static int imx8mp_hdmi_pvi_probe(struct platform_device *pdev)
>                                      "could not find next bridge\n");
>
>         pm_runtime_enable(&pdev->dev);
> -
> -       /* Register the bridge. */
> -       pvi->bridge.funcs = &imx_hdmi_pvi_bridge_funcs;
>         pvi->bridge.of_node = pdev->dev.of_node;
>         pvi->bridge.timings = pvi->next_bridge->timings;
>
> diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
> index e092c9ea99b0224802919ff84b448acb53508951..e5943506981dfb8f113c94ad52ddbba52e00ec3f 100644
> --- a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
> +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
> @@ -327,9 +327,10 @@ static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev)
>         struct device_node *np = dev->of_node;
>         int ret;
>
> -       pl = devm_kzalloc(dev, sizeof(*pl), GFP_KERNEL);
> -       if (!pl)
> -               return -ENOMEM;
> +       pl = devm_drm_bridge_alloc(dev, struct imx8qxp_pixel_link, bridge,
> +                                  &imx8qxp_pixel_link_bridge_funcs);
> +       if (IS_ERR(pl))
> +               return PTR_ERR(pl);
>
>         ret = imx_scu_get_handle(&pl->ipc_handle);
>         if (ret) {
> @@ -384,7 +385,6 @@ static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev)
>         platform_set_drvdata(pdev, pl);
>
>         pl->bridge.driver_private = pl;
> -       pl->bridge.funcs = &imx8qxp_pixel_link_bridge_funcs;
>         pl->bridge.of_node = np;
>
>         drm_bridge_add(&pl->bridge);
> diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
> index da138ab51b3bd2c6ebd3780c09818891d5320092..111310acab2ce403a62a47ecbe9d9dd372c75ecd 100644
> --- a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
> +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
> @@ -392,9 +392,10 @@ static int imx8qxp_pxl2dpi_bridge_probe(struct platform_device *pdev)
>         struct device_node *np = dev->of_node;
>         int ret;
>
> -       p2d = devm_kzalloc(dev, sizeof(*p2d), GFP_KERNEL);
> -       if (!p2d)
> -               return -ENOMEM;
> +       p2d = devm_drm_bridge_alloc(dev, struct imx8qxp_pxl2dpi, bridge,
> +                                   &imx8qxp_pxl2dpi_bridge_funcs);
> +       if (IS_ERR(p2d))
> +               return PTR_ERR(p2d);
>
>         p2d->regmap = syscon_node_to_regmap(np->parent);
>         if (IS_ERR(p2d->regmap)) {
> @@ -441,7 +442,6 @@ static int imx8qxp_pxl2dpi_bridge_probe(struct platform_device *pdev)
>         pm_runtime_enable(dev);
>
>         p2d->bridge.driver_private = p2d;
> -       p2d->bridge.funcs = &imx8qxp_pxl2dpi_bridge_funcs;
>         p2d->bridge.of_node = np;
>
>         drm_bridge_add(&p2d->bridge);
> diff --git a/drivers/gpu/drm/bridge/ite-it6263.c b/drivers/gpu/drm/bridge/ite-it6263.c
> index a3a63a977b0a8487ad38fc08e0eed08672f4d41a..a417b25a65e8369177d4bb09d179a865f6187adc 100644
> --- a/drivers/gpu/drm/bridge/ite-it6263.c
> +++ b/drivers/gpu/drm/bridge/ite-it6263.c
> @@ -816,9 +816,10 @@ static int it6263_probe(struct i2c_client *client)
>         struct it6263 *it;
>         int ret;
>
> -       it = devm_kzalloc(dev, sizeof(*it), GFP_KERNEL);
> -       if (!it)
> -               return -ENOMEM;
> +       it = devm_drm_bridge_alloc(dev, struct it6263, bridge,
> +                                  &it6263_bridge_funcs);
> +       if (IS_ERR(it))
> +               return PTR_ERR(it);
>
>         it->dev = dev;
>         it->hdmi_i2c = client;
> @@ -865,8 +866,6 @@ static int it6263_probe(struct i2c_client *client)
>         it6263_hdmi_config(it);
>
>         i2c_set_clientdata(client, it);
> -
> -       it->bridge.funcs = &it6263_bridge_funcs;
>         it->bridge.of_node = dev->of_node;
>         /* IT6263 chip doesn't support HPD interrupt. */
>         it->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
> diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c
> index 1383d1e21afea1acb46b7bd28860908b58832dbc..bf2e854210233bcecd1be582ef092370bd652412 100644
> --- a/drivers/gpu/drm/bridge/ite-it6505.c
> +++ b/drivers/gpu/drm/bridge/ite-it6505.c
> @@ -3583,9 +3583,10 @@ static int it6505_i2c_probe(struct i2c_client *client)
>         struct extcon_dev *extcon;
>         int err;
>
> -       it6505 = devm_kzalloc(&client->dev, sizeof(*it6505), GFP_KERNEL);
> -       if (!it6505)
> -               return -ENOMEM;
> +       it6505 = devm_drm_bridge_alloc(&client->dev, struct it6505, bridge,
> +                                      &it6505_bridge_funcs);
> +       if (IS_ERR(it6505))
> +               return PTR_ERR(it6505);
>
>         mutex_init(&it6505->extcon_lock);
>         mutex_init(&it6505->mode_lock);
> @@ -3659,8 +3660,6 @@ static int it6505_i2c_probe(struct i2c_client *client)
>         it6505->aux.dev = dev;
>         it6505->aux.transfer = it6505_aux_transfer;
>         drm_dp_aux_init(&it6505->aux);
> -
> -       it6505->bridge.funcs = &it6505_bridge_funcs;
>         it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
>         it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
>                              DRM_BRIDGE_OP_HPD;
> diff --git a/drivers/gpu/drm/bridge/ite-it66121.c b/drivers/gpu/drm/bridge/ite-it66121.c
> index 7b110ae532918d2d6f91ebc5f747c38e7e77dc07..aee88436d72e3c1c8d8f6b62ab04a8d9be10b413 100644
> --- a/drivers/gpu/drm/bridge/ite-it66121.c
> +++ b/drivers/gpu/drm/bridge/ite-it66121.c
> @@ -1516,9 +1516,10 @@ static int it66121_probe(struct i2c_client *client)
>                 return -ENXIO;
>         }
>
> -       ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
> -       if (!ctx)
> -               return -ENOMEM;
> +       ctx = devm_drm_bridge_alloc(dev, struct it66121_ctx, bridge,
> +                                   &it66121_bridge_funcs);
> +       if (IS_ERR(ctx))
> +               return PTR_ERR(ctx);
>
>         ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
>         if (!ep)
> @@ -1576,8 +1577,6 @@ static int it66121_probe(struct i2c_client *client)
>             (device_ids[1] << 8 | device_ids[0]) != ctx->info->pid) {
>                 return -ENODEV;
>         }
> -
> -       ctx->bridge.funcs = &it66121_bridge_funcs;
>         ctx->bridge.of_node = dev->of_node;
>         ctx->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
>         ctx->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID;
> diff --git a/drivers/gpu/drm/bridge/lontium-lt8912b.c b/drivers/gpu/drm/bridge/lontium-lt8912b.c
> index 3e49d855b3648880cea9bce5f3f04fbb6f838a45..c2a07f7c83fa1e0aefbbbcc855367adc6140f34d 100644
> --- a/drivers/gpu/drm/bridge/lontium-lt8912b.c
> +++ b/drivers/gpu/drm/bridge/lontium-lt8912b.c
> @@ -761,9 +761,10 @@ static int lt8912_probe(struct i2c_client *client)
>         int ret = 0;
>         struct device *dev = &client->dev;
>
> -       lt = devm_kzalloc(dev, sizeof(struct lt8912), GFP_KERNEL);
> -       if (!lt)
> -               return -ENOMEM;
> +       lt = devm_drm_bridge_alloc(dev, struct lt8912, bridge,
> +                                  &lt8912_bridge_funcs);
> +       if (IS_ERR(lt))
> +               return PTR_ERR(lt);
>
>         lt->dev = dev;
>         lt->i2c_client[0] = client;
> @@ -777,8 +778,6 @@ static int lt8912_probe(struct i2c_client *client)
>                 goto err_i2c;
>
>         i2c_set_clientdata(client, lt);
> -
> -       lt->bridge.funcs = &lt8912_bridge_funcs;
>         lt->bridge.of_node = dev->of_node;
>         lt->bridge.ops = (DRM_BRIDGE_OP_EDID |
>                           DRM_BRIDGE_OP_DETECT);
> diff --git a/drivers/gpu/drm/bridge/lontium-lt9211.c b/drivers/gpu/drm/bridge/lontium-lt9211.c
> index 9b2dac9bd63c5afd4ffbafafdbbb1230549bc36f..97026fa66c5d39d49cf50ad69f707a84d584b76d 100644
> --- a/drivers/gpu/drm/bridge/lontium-lt9211.c
> +++ b/drivers/gpu/drm/bridge/lontium-lt9211.c
> @@ -727,9 +727,9 @@ static int lt9211_probe(struct i2c_client *client)
>         struct lt9211 *ctx;
>         int ret;
>
> -       ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
> -       if (!ctx)
> -               return -ENOMEM;
> +       ctx = devm_drm_bridge_alloc(dev, struct lt9211, bridge, &lt9211_funcs);
> +       if (IS_ERR(ctx))
> +               return PTR_ERR(ctx);
>
>         ctx->dev = dev;
>
> @@ -754,8 +754,6 @@ static int lt9211_probe(struct i2c_client *client)
>
>         dev_set_drvdata(dev, ctx);
>         i2c_set_clientdata(client, ctx);
> -
> -       ctx->bridge.funcs = &lt9211_funcs;
>         ctx->bridge.of_node = dev->of_node;
>         drm_bridge_add(&ctx->bridge);
>
> diff --git a/drivers/gpu/drm/bridge/lontium-lt9611.c b/drivers/gpu/drm/bridge/lontium-lt9611.c
> index 53987e826ccd3368e94a1d7563354d359ebcbb17..602c89e3e39f3133c94434aec91e0d688737dd63 100644
> --- a/drivers/gpu/drm/bridge/lontium-lt9611.c
> +++ b/drivers/gpu/drm/bridge/lontium-lt9611.c
> @@ -1072,9 +1072,10 @@ static int lt9611_probe(struct i2c_client *client)
>                 return -ENODEV;
>         }
>
> -       lt9611 = devm_kzalloc(dev, sizeof(*lt9611), GFP_KERNEL);
> -       if (!lt9611)
> -               return -ENOMEM;
> +       lt9611 = devm_drm_bridge_alloc(dev, struct lt9611, bridge,
> +                                      &lt9611_bridge_funcs);
> +       if (IS_ERR(lt9611))
> +               return PTR_ERR(lt9611);
>
>         lt9611->dev = dev;
>         lt9611->client = client;
> @@ -1126,8 +1127,6 @@ static int lt9611_probe(struct i2c_client *client)
>
>         /* Disable Audio InfoFrame, enabled by default */
>         regmap_update_bits(lt9611->regmap, 0x843d, LT9611_INFOFRAME_AUDIO, 0);
> -
> -       lt9611->bridge.funcs = &lt9611_bridge_funcs;
>         lt9611->bridge.of_node = client->dev.of_node;
>         lt9611->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
>                              DRM_BRIDGE_OP_HPD | DRM_BRIDGE_OP_MODES |
> diff --git a/drivers/gpu/drm/bridge/lvds-codec.c b/drivers/gpu/drm/bridge/lvds-codec.c
> index 1646e454e0b0b558d00f9421f15bb7084e2aa45a..e6a7147e141b64fc77dfef03a737ee599a0ecd10 100644
> --- a/drivers/gpu/drm/bridge/lvds-codec.c
> +++ b/drivers/gpu/drm/bridge/lvds-codec.c
> @@ -118,9 +118,10 @@ static int lvds_codec_probe(struct platform_device *pdev)
>         u32 val;
>         int ret;
>
> -       lvds_codec = devm_kzalloc(dev, sizeof(*lvds_codec), GFP_KERNEL);
> -       if (!lvds_codec)
> -               return -ENOMEM;
> +       lvds_codec = devm_drm_bridge_alloc(dev, struct lvds_codec, bridge,
> +                                          &funcs);
> +       if (IS_ERR(lvds_codec))
> +               return PTR_ERR(lvds_codec);
>
>         lvds_codec->dev = &pdev->dev;
>         lvds_codec->connector_type = (uintptr_t)of_device_get_match_data(dev);
> @@ -156,8 +157,6 @@ static int lvds_codec_probe(struct platform_device *pdev)
>         if (IS_ERR(lvds_codec->panel_bridge))
>                 return PTR_ERR(lvds_codec->panel_bridge);
>
> -       lvds_codec->bridge.funcs = &funcs;
> -
>         /*
>          * Decoder input LVDS format is a property of the decoder chip or even
>          * its strapping. Handle data-mapping the same way lvds-panel does. In
> diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/bridge/microchip-lvds.c
> index 1d4ae0097df847d9f93c79eecff0c4587ae331ba..9f4ff82bc6b49010f8727da3b367f5a744a28edc 100644
> --- a/drivers/gpu/drm/bridge/microchip-lvds.c
> +++ b/drivers/gpu/drm/bridge/microchip-lvds.c
> @@ -157,9 +157,10 @@ static int mchp_lvds_probe(struct platform_device *pdev)
>         if (!dev->of_node)
>                 return -ENODEV;
>
> -       lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
> -       if (!lvds)
> -               return -ENOMEM;
> +       lvds = devm_drm_bridge_alloc(&pdev->dev, struct mchp_lvds, bridge,
> +                                    &mchp_lvds_bridge_funcs);
> +       if (IS_ERR(lvds))
> +               return PTR_ERR(lvds);
>
>         lvds->dev = dev;
>
> @@ -192,7 +193,6 @@ static int mchp_lvds_probe(struct platform_device *pdev)
>
>         lvds->bridge.of_node = dev->of_node;
>         lvds->bridge.type = DRM_MODE_CONNECTOR_LVDS;
> -       lvds->bridge.funcs = &mchp_lvds_bridge_funcs;
>
>         dev_set_drvdata(dev, lvds);
>         ret = devm_pm_runtime_enable(dev);
> diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
> index 55912ae11f46a1d551e11f93a306a8a00ef3f7d8..2f7429b24fc20db104dec17182f1119c6c75e600 100644
> --- a/drivers/gpu/drm/bridge/nwl-dsi.c
> +++ b/drivers/gpu/drm/bridge/nwl-dsi.c
> @@ -1149,9 +1149,10 @@ static int nwl_dsi_probe(struct platform_device *pdev)
>         struct nwl_dsi *dsi;
>         int ret;
>
> -       dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
> -       if (!dsi)
> -               return -ENOMEM;
> +       dsi = devm_drm_bridge_alloc(dev, struct nwl_dsi, bridge,
> +                                   &nwl_dsi_bridge_funcs);
> +       if (IS_ERR(dsi))
> +               return PTR_ERR(dsi);
>
>         dsi->dev = dev;
>
> @@ -1180,7 +1181,6 @@ static int nwl_dsi_probe(struct platform_device *pdev)
>                 dsi->quirks = (uintptr_t)attr->data;
>
>         dsi->bridge.driver_private = dsi;
> -       dsi->bridge.funcs = &nwl_dsi_bridge_funcs;
>         dsi->bridge.of_node = dev->of_node;
>         dsi->bridge.timings = &nwl_dsi_timings;
>         dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
> diff --git a/drivers/gpu/drm/bridge/parade-ps8622.c b/drivers/gpu/drm/bridge/parade-ps8622.c
> index 8726fefc5c654e49bce029d943d241789ca4f802..81aa8dc8ee12af8b55f42d4786b44b3b90266491 100644
> --- a/drivers/gpu/drm/bridge/parade-ps8622.c
> +++ b/drivers/gpu/drm/bridge/parade-ps8622.c
> @@ -449,9 +449,10 @@ static int ps8622_probe(struct i2c_client *client)
>         struct drm_bridge *panel_bridge;
>         int ret;
>
> -       ps8622 = devm_kzalloc(dev, sizeof(*ps8622), GFP_KERNEL);
> -       if (!ps8622)
> -               return -ENOMEM;
> +       ps8622 = devm_drm_bridge_alloc(dev, struct ps8622_bridge, bridge,
> +                                      &ps8622_bridge_funcs);
> +       if (IS_ERR(ps8622))
> +               return PTR_ERR(ps8622);
>
>         panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0);
>         if (IS_ERR(panel_bridge))
> @@ -508,8 +509,6 @@ static int ps8622_probe(struct i2c_client *client)
>                 ps8622->bl->props.max_brightness = PS8622_MAX_BRIGHTNESS;
>                 ps8622->bl->props.brightness = PS8622_MAX_BRIGHTNESS;
>         }
> -
> -       ps8622->bridge.funcs = &ps8622_bridge_funcs;
>         ps8622->bridge.type = DRM_MODE_CONNECTOR_LVDS;
>         ps8622->bridge.of_node = dev->of_node;
>         drm_bridge_add(&ps8622->bridge);
> diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c
> index 2422ff68c1042bd8eaa6821ff387d4faad47c550..d58ff094ddc7536acf04211367b9482e487b877a 100644
> --- a/drivers/gpu/drm/bridge/parade-ps8640.c
> +++ b/drivers/gpu/drm/bridge/parade-ps8640.c
> @@ -636,9 +636,10 @@ static int ps8640_probe(struct i2c_client *client)
>         int ret;
>         u32 i;
>
> -       ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
> -       if (!ps_bridge)
> -               return -ENOMEM;
> +       ps_bridge = devm_drm_bridge_alloc(dev, struct ps8640, bridge,
> +                                         &ps8640_bridge_funcs);
> +       if (IS_ERR(ps_bridge))
> +               return PTR_ERR(ps_bridge);
>
>         mutex_init(&ps_bridge->aux_lock);
>
> @@ -661,8 +662,6 @@ static int ps8640_probe(struct i2c_client *client)
>                                                GPIOD_OUT_HIGH);
>         if (IS_ERR(ps_bridge->gpio_reset))
>                 return PTR_ERR(ps_bridge->gpio_reset);
> -
> -       ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
>         ps_bridge->bridge.of_node = dev->of_node;
>         ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP;
>
> diff --git a/drivers/gpu/drm/bridge/sii9234.c b/drivers/gpu/drm/bridge/sii9234.c
> index cd7837c9a6e00b572a3fb65e5e0c9fa884555a73..487f355144a0e615298a3dd176b936885c2a8f33 100644
> --- a/drivers/gpu/drm/bridge/sii9234.c
> +++ b/drivers/gpu/drm/bridge/sii9234.c
> @@ -888,9 +888,10 @@ static int sii9234_probe(struct i2c_client *client)
>         struct device *dev = &client->dev;
>         int ret;
>
> -       ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
> -       if (!ctx)
> -               return -ENOMEM;
> +       ctx = devm_drm_bridge_alloc(dev, struct sii9234, bridge,
> +                                   &sii9234_bridge_funcs);
> +       if (IS_ERR(ctx))
> +               return PTR_ERR(ctx);
>
>         ctx->dev = dev;
>         mutex_init(&ctx->lock);
> @@ -920,8 +921,6 @@ static int sii9234_probe(struct i2c_client *client)
>                 return ret;
>
>         i2c_set_clientdata(client, ctx);
> -
> -       ctx->bridge.funcs = &sii9234_bridge_funcs;
>         ctx->bridge.of_node = dev->of_node;
>         drm_bridge_add(&ctx->bridge);
>
> diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c
> index 3af650dc92a1612ca88fe378319519546b79901f..7de6f0ec4ec2372f633cf1d73853c73fd9caf175 100644
> --- a/drivers/gpu/drm/bridge/sil-sii8620.c
> +++ b/drivers/gpu/drm/bridge/sil-sii8620.c
> @@ -2291,9 +2291,10 @@ static int sii8620_probe(struct i2c_client *client)
>         struct sii8620 *ctx;
>         int ret;
>
> -       ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
> -       if (!ctx)
> -               return -ENOMEM;
> +       ctx = devm_drm_bridge_alloc(dev, struct sii8620, bridge,
> +                                   &sii8620_bridge_funcs);
> +       if (IS_ERR(ctx))
> +               return PTR_ERR(ctx);
>
>         ctx->dev = dev;
>         mutex_init(&ctx->lock);
> @@ -2335,8 +2336,6 @@ static int sii8620_probe(struct i2c_client *client)
>         }
>
>         i2c_set_clientdata(client, ctx);
> -
> -       ctx->bridge.funcs = &sii8620_bridge_funcs;
>         ctx->bridge.of_node = dev->of_node;
>         drm_bridge_add(&ctx->bridge);
>
> diff --git a/drivers/gpu/drm/bridge/simple-bridge.c b/drivers/gpu/drm/bridge/simple-bridge.c
> index 70db5b99e5bb84f099ec54cf62abbda53475311d..f9be4eafadfd1e4229161375e47da95a3075b090 100644
> --- a/drivers/gpu/drm/bridge/simple-bridge.c
> +++ b/drivers/gpu/drm/bridge/simple-bridge.c
> @@ -168,9 +168,10 @@ static int simple_bridge_probe(struct platform_device *pdev)
>         struct simple_bridge *sbridge;
>         struct device_node *remote;
>
> -       sbridge = devm_kzalloc(&pdev->dev, sizeof(*sbridge), GFP_KERNEL);
> -       if (!sbridge)
> -               return -ENOMEM;
> +       sbridge = devm_drm_bridge_alloc(&pdev->dev, struct simple_bridge,
> +                                       bridge, &simple_bridge_bridge_funcs);
> +       if (IS_ERR(sbridge))
> +               return PTR_ERR(sbridge);
>
>         sbridge->info = of_device_get_match_data(&pdev->dev);
>
> @@ -202,9 +203,6 @@ static int simple_bridge_probe(struct platform_device *pdev)
>         if (IS_ERR(sbridge->enable))
>                 return dev_err_probe(&pdev->dev, PTR_ERR(sbridge->enable),
>                                      "Unable to retrieve enable GPIO\n");
> -
> -       /* Register the bridge. */
> -       sbridge->bridge.funcs = &simple_bridge_bridge_funcs;
>         sbridge->bridge.of_node = pdev->dev.of_node;
>         sbridge->bridge.timings = sbridge->info->timings;
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
> index 6166f197e37b552cb8a52b7b0d23ffc632f54557..81aa3a4a0090e9183402c1b2df7e4dd8f7963b9f 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
> @@ -1045,9 +1045,10 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
>                 return ERR_PTR(-ENODEV);
>         }
>
> -       hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
> -       if (!hdmi)
> -               return ERR_PTR(-ENOMEM);
> +       hdmi = devm_drm_bridge_alloc(dev, struct dw_hdmi_qp, bridge,
> +                                    &dw_hdmi_qp_bridge_funcs);
> +       if (IS_ERR(hdmi))
> +               return hdmi;
>
>         hdmi->dev = dev;
>
> @@ -1073,7 +1074,6 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
>                 return ERR_PTR(ret);
>
>         hdmi->bridge.driver_private = hdmi;
> -       hdmi->bridge.funcs = &dw_hdmi_qp_bridge_funcs;
>         hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT |
>                            DRM_BRIDGE_OP_EDID |
>                            DRM_BRIDGE_OP_HDMI |
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index b08ada920a501d6a62f39581944a87019f5e5c15..ef578489a6d1c86506df43a26211aa0e5c585e23 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -1194,9 +1194,10 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>         struct dw_mipi_dsi *dsi;
>         int ret;
>
> -       dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
> -       if (!dsi)
> -               return ERR_PTR(-ENOMEM);
> +       dsi = devm_drm_bridge_alloc(dev, struct dw_mipi_dsi, bridge,
> +                                   &dw_mipi_dsi_bridge_funcs);
> +       if (IS_ERR(dsi))
> +               return dsi;
>
>         dsi->dev = dev;
>         dsi->plat_data = plat_data;
> @@ -1265,7 +1266,6 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>         }
>
>         dsi->bridge.driver_private = dsi;
> -       dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
>         dsi->bridge.of_node = pdev->dev.of_node;
>
>         return dsi;
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
> index c76f5f2e74d14bd372f969c6c7832aa57f80772b..981d711876cf5eee1467c2fc9ed125141aa8dc14 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
> @@ -914,9 +914,10 @@ __dw_mipi_dsi2_probe(struct platform_device *pdev,
>         struct dw_mipi_dsi2 *dsi2;
>         int ret;
>
> -       dsi2 = devm_kzalloc(dev, sizeof(*dsi2), GFP_KERNEL);
> -       if (!dsi2)
> -               return ERR_PTR(-ENOMEM);
> +       dsi2 = devm_drm_bridge_alloc(dev, struct dw_mipi_dsi2, bridge,
> +                                    &dw_mipi_dsi2_bridge_funcs);
> +       if (IS_ERR(dsi2))
> +               return dsi2;
>
>         dsi2->dev = dev;
>         dsi2->plat_data = plat_data;
> @@ -981,7 +982,6 @@ __dw_mipi_dsi2_probe(struct platform_device *pdev,
>         }
>
>         dsi2->bridge.driver_private = dsi2;
> -       dsi2->bridge.funcs = &dw_mipi_dsi2_bridge_funcs;
>         dsi2->bridge.of_node = pdev->dev.of_node;
>
>         return dsi2;
> diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc358762.c
> index edf01476f2ef6e05ef2c144ff4467e7f6babc4c6..690f4c5a6fb113a6d5947a364922605d28d33edf 100644
> --- a/drivers/gpu/drm/bridge/tc358762.c
> +++ b/drivers/gpu/drm/bridge/tc358762.c
> @@ -265,9 +265,10 @@ static int tc358762_probe(struct mipi_dsi_device *dsi)
>         struct tc358762 *ctx;
>         int ret;
>
> -       ctx = devm_kzalloc(dev, sizeof(struct tc358762), GFP_KERNEL);
> -       if (!ctx)
> -               return -ENOMEM;
> +       ctx = devm_drm_bridge_alloc(dev, struct tc358762, bridge,
> +                                   &tc358762_bridge_funcs);
> +       if (IS_ERR(ctx))
> +               return PTR_ERR(ctx);
>
>         mipi_dsi_set_drvdata(dsi, ctx);
>
> @@ -287,8 +288,6 @@ static int tc358762_probe(struct mipi_dsi_device *dsi)
>         ret = tc358762_configure_regulators(ctx);
>         if (ret < 0)
>                 return ret;
> -
> -       ctx->bridge.funcs = &tc358762_bridge_funcs;
>         ctx->bridge.type = DRM_MODE_CONNECTOR_DPI;
>         ctx->bridge.of_node = dev->of_node;
>         ctx->bridge.pre_enable_prev_first = true;
> diff --git a/drivers/gpu/drm/bridge/tc358764.c b/drivers/gpu/drm/bridge/tc358764.c
> index 3f76c890fad9ffa50dc02f289a37378332830516..c54a6e571daccfbce8eeb34e6e38faa7895642df 100644
> --- a/drivers/gpu/drm/bridge/tc358764.c
> +++ b/drivers/gpu/drm/bridge/tc358764.c
> @@ -347,9 +347,10 @@ static int tc358764_probe(struct mipi_dsi_device *dsi)
>         struct tc358764 *ctx;
>         int ret;
>
> -       ctx = devm_kzalloc(dev, sizeof(struct tc358764), GFP_KERNEL);
> -       if (!ctx)
> -               return -ENOMEM;
> +       ctx = devm_drm_bridge_alloc(dev, struct tc358764, bridge,
> +                                   &tc358764_bridge_funcs);
> +       if (IS_ERR(ctx))
> +               return PTR_ERR(ctx);
>
>         mipi_dsi_set_drvdata(dsi, ctx);
>
> @@ -367,8 +368,6 @@ static int tc358764_probe(struct mipi_dsi_device *dsi)
>         ret = tc358764_configure_regulators(ctx);
>         if (ret < 0)
>                 return ret;
> -
> -       ctx->bridge.funcs = &tc358764_bridge_funcs;
>         ctx->bridge.of_node = dev->of_node;
>         ctx->bridge.pre_enable_prev_first = true;
>
> diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c
> index 063f217a17b6cf32e9793b8a96a5ac6128584098..1868026b3ee012edc700f1994c88777765161651 100644
> --- a/drivers/gpu/drm/bridge/tc358768.c
> +++ b/drivers/gpu/drm/bridge/tc358768.c
> @@ -1287,9 +1287,10 @@ static int tc358768_i2c_probe(struct i2c_client *client)
>         if (!np)
>                 return -ENODEV;
>
> -       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> -       if (!priv)
> -               return -ENOMEM;
> +       priv = devm_drm_bridge_alloc(dev, struct tc358768_priv, bridge,
> +                                    &tc358768_bridge_funcs);
> +       if (IS_ERR(priv))
> +               return PTR_ERR(priv);
>
>         dev_set_drvdata(dev, priv);
>         priv->dev = dev;
> @@ -1320,8 +1321,6 @@ static int tc358768_i2c_probe(struct i2c_client *client)
>
>         priv->dsi_host.dev = dev;
>         priv->dsi_host.ops = &tc358768_dsi_host_ops;
> -
> -       priv->bridge.funcs = &tc358768_bridge_funcs;
>         priv->bridge.timings = &default_tc358768_timings;
>         priv->bridge.of_node = np;
>
> diff --git a/drivers/gpu/drm/bridge/tc358775.c b/drivers/gpu/drm/bridge/tc358775.c
> index 1b10e6ee1724ffb4bb8946f86d2f18e53428381a..b7d5ef377049656efeaca96abc5f68e61de1ee1e 100644
> --- a/drivers/gpu/drm/bridge/tc358775.c
> +++ b/drivers/gpu/drm/bridge/tc358775.c
> @@ -659,9 +659,10 @@ static int tc_probe(struct i2c_client *client)
>         struct tc_data *tc;
>         int ret;
>
> -       tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
> -       if (!tc)
> -               return -ENOMEM;
> +       tc = devm_drm_bridge_alloc(dev, struct tc_data, bridge,
> +                                  &tc_bridge_funcs);
> +       if (IS_ERR(tc))
> +               return PTR_ERR(tc);
>
>         tc->dev = dev;
>         tc->i2c = client;
> @@ -700,8 +701,6 @@ static int tc_probe(struct i2c_client *client)
>                 dev_err(dev, "cannot get reset-gpios %d\n", ret);
>                 return ret;
>         }
> -
> -       tc->bridge.funcs = &tc_bridge_funcs;
>         tc->bridge.of_node = dev->of_node;
>         tc->bridge.pre_enable_prev_first = true;
>         drm_bridge_add(&tc->bridge);
> diff --git a/drivers/gpu/drm/bridge/thc63lvd1024.c b/drivers/gpu/drm/bridge/thc63lvd1024.c
> index e2fc78adebcf22f0d8cdb484078e37b748b776c6..2cb7cd0c060824256bbfa511f833cc00437d318b 100644
> --- a/drivers/gpu/drm/bridge/thc63lvd1024.c
> +++ b/drivers/gpu/drm/bridge/thc63lvd1024.c
> @@ -181,9 +181,10 @@ static int thc63_probe(struct platform_device *pdev)
>         struct thc63_dev *thc63;
>         int ret;
>
> -       thc63 = devm_kzalloc(&pdev->dev, sizeof(*thc63), GFP_KERNEL);
> -       if (!thc63)
> -               return -ENOMEM;
> +       thc63 = devm_drm_bridge_alloc(&pdev->dev, struct thc63_dev, bridge,
> +                                     &thc63_bridge_func);
> +       if (IS_ERR(thc63))
> +               return PTR_ERR(thc63);
>
>         thc63->dev = &pdev->dev;
>         platform_set_drvdata(pdev, thc63);
> @@ -208,7 +209,6 @@ static int thc63_probe(struct platform_device *pdev)
>
>         thc63->bridge.driver_private = thc63;
>         thc63->bridge.of_node = pdev->dev.of_node;
> -       thc63->bridge.funcs = &thc63_bridge_func;
>         thc63->bridge.timings = &thc63->timings;
>
>         drm_bridge_add(&thc63->bridge);
> diff --git a/drivers/gpu/drm/bridge/ti-dlpc3433.c b/drivers/gpu/drm/bridge/ti-dlpc3433.c
> index 47638d1c96ec5ad999604c8c7e8839ff85936d98..fdde52208c7c1f17b5fb2ac306fd3011cb1bb427 100644
> --- a/drivers/gpu/drm/bridge/ti-dlpc3433.c
> +++ b/drivers/gpu/drm/bridge/ti-dlpc3433.c
> @@ -348,9 +348,10 @@ static int dlpc3433_probe(struct i2c_client *client)
>         struct dlpc *dlpc;
>         int ret;
>
> -       dlpc = devm_kzalloc(dev, sizeof(*dlpc), GFP_KERNEL);
> -       if (!dlpc)
> -               return -ENOMEM;
> +       dlpc = devm_drm_bridge_alloc(dev, struct dlpc, bridge,
> +                                    &dlpc_bridge_funcs);
> +       if (IS_ERR(dlpc))
> +               return PTR_ERR(dlpc);
>
>         dlpc->dev = dev;
>
> @@ -364,8 +365,6 @@ static int dlpc3433_probe(struct i2c_client *client)
>
>         dev_set_drvdata(dev, dlpc);
>         i2c_set_clientdata(client, dlpc);
> -
> -       dlpc->bridge.funcs = &dlpc_bridge_funcs;
>         dlpc->bridge.of_node = dev->of_node;
>         drm_bridge_add(&dlpc->bridge);
>
> diff --git a/drivers/gpu/drm/bridge/ti-tdp158.c b/drivers/gpu/drm/bridge/ti-tdp158.c
> index cca75443f0121e39527a6cecf711eff2c0d507b5..27053d020df7c6fabbd5ce631b46c3f2358f12b2 100644
> --- a/drivers/gpu/drm/bridge/ti-tdp158.c
> +++ b/drivers/gpu/drm/bridge/ti-tdp158.c
> @@ -68,9 +68,10 @@ static int tdp158_probe(struct i2c_client *client)
>         struct tdp158 *tdp158;
>         struct device *dev = &client->dev;
>
> -       tdp158 = devm_kzalloc(dev, sizeof(*tdp158), GFP_KERNEL);
> -       if (!tdp158)
> -               return -ENOMEM;
> +       tdp158 = devm_drm_bridge_alloc(dev, struct tdp158, bridge,
> +                                      &tdp158_bridge_funcs);
> +       if (IS_ERR(tdp158))
> +               return PTR_ERR(tdp158);
>
>         tdp158->next = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
>         if (IS_ERR(tdp158->next))
> @@ -89,7 +90,6 @@ static int tdp158_probe(struct i2c_client *client)
>                 return dev_err_probe(dev, PTR_ERR(tdp158->enable), "enable");
>
>         tdp158->bridge.of_node = dev->of_node;
> -       tdp158->bridge.funcs = &tdp158_bridge_funcs;
>         tdp158->bridge.driver_private = tdp158;
>         tdp158->dev = dev;
>
> diff --git a/drivers/gpu/drm/bridge/ti-tfp410.c b/drivers/gpu/drm/bridge/ti-tfp410.c
> index e15d232ddbac55c6f5f966471a6c63f9c29a06c1..a62c43fba854032790055751b713abb012ee0cc6 100644
> --- a/drivers/gpu/drm/bridge/ti-tfp410.c
> +++ b/drivers/gpu/drm/bridge/ti-tfp410.c
> @@ -341,14 +341,13 @@ static int tfp410_init(struct device *dev, bool i2c)
>                 return -ENXIO;
>         }
>
> -       dvi = devm_kzalloc(dev, sizeof(*dvi), GFP_KERNEL);
> -       if (!dvi)
> -               return -ENOMEM;
> +       dvi = devm_drm_bridge_alloc(dev, struct tfp410, bridge,
> +                                   &tfp410_bridge_funcs);
> +       if (IS_ERR(dvi))
> +               return PTR_ERR(dvi);
>
>         dvi->dev = dev;
>         dev_set_drvdata(dev, dvi);
> -
> -       dvi->bridge.funcs = &tfp410_bridge_funcs;
>         dvi->bridge.of_node = dev->of_node;
>         dvi->bridge.timings = &dvi->timings;
>         dvi->bridge.type = DRM_MODE_CONNECTOR_DVID;
> diff --git a/drivers/gpu/drm/bridge/ti-tpd12s015.c b/drivers/gpu/drm/bridge/ti-tpd12s015.c
> index 1c289051a5987e0aec4c286ef4c01ee1a2f9421f..f4d63171da54776e5b314595b6a028fdb819e4a8 100644
> --- a/drivers/gpu/drm/bridge/ti-tpd12s015.c
> +++ b/drivers/gpu/drm/bridge/ti-tpd12s015.c
> @@ -116,13 +116,12 @@ static int tpd12s015_probe(struct platform_device *pdev)
>         struct gpio_desc *gpio;
>         int ret;
>
> -       tpd = devm_kzalloc(&pdev->dev, sizeof(*tpd), GFP_KERNEL);
> -       if (!tpd)
> -               return -ENOMEM;
> +       tpd = devm_drm_bridge_alloc(&pdev->dev, struct tpd12s015_device,
> +                                   bridge, &tpd12s015_bridge_funcs);
> +       if (IS_ERR(tpd))
> +               return PTR_ERR(tpd);
>
>         platform_set_drvdata(pdev, tpd);
> -
> -       tpd->bridge.funcs = &tpd12s015_bridge_funcs;
>         tpd->bridge.of_node = pdev->dev.of_node;
>         tpd->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
>         tpd->bridge.ops = DRM_BRIDGE_OP_DETECT;
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
> index 4523cc0a2db8cd8b57183e11140b8a6584e95a34..9f0e28e0750185871c268e227b5b10d5cba0abdb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> @@ -2725,9 +2725,10 @@ static int mtk_dp_probe(struct platform_device *pdev)
>         struct device *dev = &pdev->dev;
>         int ret;
>
> -       mtk_dp = devm_kzalloc(dev, sizeof(*mtk_dp), GFP_KERNEL);
> -       if (!mtk_dp)
> -               return -ENOMEM;
> +       mtk_dp = devm_drm_bridge_alloc(dev, struct mtk_dp, bridge,
> +                                      &mtk_dp_bridge_funcs);
> +       if (IS_ERR(mtk_dp))
> +               return PTR_ERR(mtk_dp);
>
>         mtk_dp->dev = dev;
>         mtk_dp->data = (struct mtk_dp_data *)of_device_get_match_data(dev);
> @@ -2784,8 +2785,6 @@ static int mtk_dp_probe(struct platform_device *pdev)
>         ret = mtk_dp_register_phy(mtk_dp);
>         if (ret)
>                 return ret;
> -
> -       mtk_dp->bridge.funcs = &mtk_dp_bridge_funcs;
>         mtk_dp->bridge.of_node = dev->of_node;
>         mtk_dp->bridge.type = mtk_dp->data->bridge_type;
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 6b96ed4fc8614569e53f76fe3e52507c7dc1249c..09c3b00507542aab18ded89bb885b2dc64f2b208 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -1021,9 +1021,10 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>         struct mtk_dpi *dpi;
>         int ret;
>
> -       dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
> -       if (!dpi)
> -               return -ENOMEM;
> +       dpi = devm_drm_bridge_alloc(dev, struct mtk_dpi, bridge,
> +                                   &mtk_dpi_bridge_funcs);
> +       if (IS_ERR(dpi))
> +               return PTR_ERR(dpi);
>
>         dpi->dev = dev;
>         dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev);
> @@ -1074,8 +1075,6 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>                 return dpi->irq;
>
>         platform_set_drvdata(pdev, dpi);
> -
> -       dpi->bridge.funcs = &mtk_dpi_bridge_funcs;
>         dpi->bridge.of_node = dev->of_node;
>         dpi->bridge.type = DRM_MODE_CONNECTOR_DPI;
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index cd2fbd8487c55930bf3abd1c3131153469e5166a..1733643ba00b845bcadda2aafce3afb8a3be6f8b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -1196,9 +1196,10 @@ static int mtk_dsi_probe(struct platform_device *pdev)
>         int irq_num;
>         int ret;
>
> -       dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
> -       if (!dsi)
> -               return -ENOMEM;
> +       dsi = devm_drm_bridge_alloc(dev, struct mtk_dsi, bridge,
> +                                   &mtk_dsi_bridge_funcs);
> +       if (IS_ERR(dsi))
> +               return PTR_ERR(dsi);
>
>         dsi->driver_data = of_device_get_match_data(dev);
>
> @@ -1245,8 +1246,6 @@ static int mtk_dsi_probe(struct platform_device *pdev)
>         init_waitqueue_head(&dsi->irq_wait_queue);
>
>         platform_set_drvdata(pdev, dsi);
> -
> -       dsi->bridge.funcs = &mtk_dsi_bridge_funcs;
>         dsi->bridge.of_node = dev->of_node;
>         dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index e753b8e2d91b9471df00678c5ad66e6adec6c36d..58f4db4afbfc6bbef745210c730032433e03526b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1688,9 +1688,10 @@ static int mtk_hdmi_probe(struct platform_device *pdev)
>         struct device *dev = &pdev->dev;
>         int ret;
>
> -       hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
> -       if (!hdmi)
> -               return -ENOMEM;
> +       hdmi = devm_drm_bridge_alloc(dev, struct mtk_hdmi, bridge,
> +                                    &mtk_hdmi_bridge_funcs);
> +       if (IS_ERR(hdmi))
> +               return PTR_ERR(hdmi);
>
>         hdmi->dev = dev;
>         hdmi->conf = of_device_get_match_data(dev);
> @@ -1716,8 +1717,6 @@ static int mtk_hdmi_probe(struct platform_device *pdev)
>         if (ret)
>                 return dev_err_probe(dev, ret,
>                                      "Failed to register audio driver\n");
> -
> -       hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
>         hdmi->bridge.of_node = pdev->dev.of_node;
>         hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
>                          | DRM_BRIDGE_OP_HPD;
> diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
> index c9678dc68fa142882e2beb24fe81185fbdef733b..24a96b0a9e31de8f23192fd36c9515c65c4d87d3 100644
> --- a/drivers/gpu/drm/meson/meson_encoder_cvbs.c
> +++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
> @@ -227,9 +227,12 @@ int meson_encoder_cvbs_probe(struct meson_drm *priv)
>         struct device_node *remote;
>         int ret;
>
> -       meson_encoder_cvbs = devm_kzalloc(priv->dev, sizeof(*meson_encoder_cvbs), GFP_KERNEL);
> -       if (!meson_encoder_cvbs)
> -               return -ENOMEM;
> +       meson_encoder_cvbs = devm_drm_bridge_alloc(priv->dev,
> +                                                  struct meson_encoder_cvbs,
> +                                                  bridge,
> +                                                  &meson_encoder_cvbs_bridge_funcs);
> +       if (IS_ERR(meson_encoder_cvbs))
> +               return PTR_ERR(meson_encoder_cvbs);
>
>         /* CVBS Connector Bridge */
>         remote = of_graph_get_remote_node(priv->dev->of_node, 0, 0);
> @@ -243,9 +246,6 @@ int meson_encoder_cvbs_probe(struct meson_drm *priv)
>         if (!meson_encoder_cvbs->next_bridge)
>                 return dev_err_probe(priv->dev, -EPROBE_DEFER,
>                                      "Failed to find CVBS Connector bridge\n");
> -
> -       /* CVBS Encoder Bridge */
> -       meson_encoder_cvbs->bridge.funcs = &meson_encoder_cvbs_bridge_funcs;
>         meson_encoder_cvbs->bridge.of_node = priv->dev->of_node;
>         meson_encoder_cvbs->bridge.type = DRM_MODE_CONNECTOR_Composite;
>         meson_encoder_cvbs->bridge.ops = DRM_BRIDGE_OP_MODES;
> diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.c b/drivers/gpu/drm/meson/meson_encoder_dsi.c
> index 3db518e5f95d324c218b730e0948c3dc845382bd..b98264801ee6ec45a1b9af1c5082d605b9b34aa4 100644
> --- a/drivers/gpu/drm/meson/meson_encoder_dsi.c
> +++ b/drivers/gpu/drm/meson/meson_encoder_dsi.c
> @@ -106,9 +106,12 @@ int meson_encoder_dsi_probe(struct meson_drm *priv)
>         struct device_node *remote;
>         int ret;
>
> -       meson_encoder_dsi = devm_kzalloc(priv->dev, sizeof(*meson_encoder_dsi), GFP_KERNEL);
> -       if (!meson_encoder_dsi)
> -               return -ENOMEM;
> +       meson_encoder_dsi = devm_drm_bridge_alloc(priv->dev,
> +                                                 struct meson_encoder_dsi,
> +                                                 bridge,
> +                                                 &meson_encoder_dsi_bridge_funcs);
> +       if (IS_ERR(meson_encoder_dsi))
> +               return PTR_ERR(meson_encoder_dsi);
>
>         /* DSI Transceiver Bridge */
>         remote = of_graph_get_remote_node(priv->dev->of_node, 2, 0);
> @@ -121,9 +124,6 @@ int meson_encoder_dsi_probe(struct meson_drm *priv)
>         if (!meson_encoder_dsi->next_bridge)
>                 return dev_err_probe(priv->dev, -EPROBE_DEFER,
>                                      "Failed to find DSI transceiver bridge\n");
> -
> -       /* DSI Encoder Bridge */
> -       meson_encoder_dsi->bridge.funcs = &meson_encoder_dsi_bridge_funcs;
>         meson_encoder_dsi->bridge.of_node = priv->dev->of_node;
>         meson_encoder_dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
>
> diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
> index 5f02695aafd1aa8444cd936a36e8f3a8010881a0..abb335ec469576817f5095dd02a58b3fe63827dd 100644
> --- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c
> +++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
> @@ -373,9 +373,12 @@ int meson_encoder_hdmi_probe(struct meson_drm *priv)
>         struct device_node *remote;
>         int ret;
>
> -       meson_encoder_hdmi = devm_kzalloc(priv->dev, sizeof(*meson_encoder_hdmi), GFP_KERNEL);
> -       if (!meson_encoder_hdmi)
> -               return -ENOMEM;
> +       meson_encoder_hdmi = devm_drm_bridge_alloc(priv->dev,
> +                                                  struct meson_encoder_hdmi,
> +                                                  bridge,
> +                                                  &meson_encoder_hdmi_bridge_funcs);
> +       if (IS_ERR(meson_encoder_hdmi))
> +               return PTR_ERR(meson_encoder_hdmi);
>
>         /* HDMI Transceiver Bridge */
>         remote = of_graph_get_remote_node(priv->dev->of_node, 1, 0);
> @@ -390,9 +393,6 @@ int meson_encoder_hdmi_probe(struct meson_drm *priv)
>                                     "Failed to find HDMI transceiver bridge\n");
>                 goto err_put_node;
>         }
> -
> -       /* HDMI Encoder Bridge */
> -       meson_encoder_hdmi->bridge.funcs = &meson_encoder_hdmi_bridge_funcs;
>         meson_encoder_hdmi->bridge.of_node = priv->dev->of_node;
>         meson_encoder_hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
>         meson_encoder_hdmi->bridge.interlace_allowed = true;
> diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c b/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
> index a9145253294fcaef6bae4e1406a781f6d710d357..b90c90f31e86ef81bf60827ae9bcb9d3f8fca6e4 100644
> --- a/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
> @@ -878,9 +878,10 @@ static int rcar_lvds_probe(struct platform_device *pdev)
>         struct rcar_lvds *lvds;
>         int ret;
>
> -       lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
> -       if (lvds == NULL)
> -               return -ENOMEM;
> +       lvds = devm_drm_bridge_alloc(&pdev->dev, struct rcar_lvds, bridge,
> +                                    &rcar_lvds_bridge_ops);
> +       if (IS_ERR(lvds))
> +               return PTR_ERR(lvds);
>
>         platform_set_drvdata(pdev, lvds);
>
> @@ -894,8 +895,6 @@ static int rcar_lvds_probe(struct platform_device *pdev)
>         ret = rcar_lvds_parse_dt(lvds);
>         if (ret < 0)
>                 return ret;
> -
> -       lvds->bridge.funcs = &rcar_lvds_bridge_ops;
>         lvds->bridge.of_node = pdev->dev.of_node;
>
>         lvds->mmio = devm_platform_ioremap_resource(pdev, 0);
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> index 96c014449547b4042d7568573fde876b5b39bd04..83e7bc735798a89942b5f288df3f53b47c1e334b 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> @@ -701,9 +701,10 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
>         u32 txsetr;
>         int ret;
>
> -       dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
> -       if (!dsi)
> -               return -ENOMEM;
> +       dsi = devm_drm_bridge_alloc(&pdev->dev, struct rzg2l_mipi_dsi, bridge,
> +                                   &rzg2l_mipi_dsi_bridge_ops);
> +       if (IS_ERR(dsi))
> +               return PTR_ERR(dsi);
>
>         platform_set_drvdata(pdev, dsi);
>         dsi->dev = &pdev->dev;
> @@ -759,9 +760,6 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
>         dsi->num_data_lanes = min(((txsetr >> 16) & 3) + 1, num_data_lanes);
>         rzg2l_mipi_dsi_dphy_exit(dsi);
>         pm_runtime_put(dsi->dev);
> -
> -       /* Initialize the DRM bridge. */
> -       dsi->bridge.funcs = &rzg2l_mipi_dsi_bridge_ops;
>         dsi->bridge.of_node = dsi->dev->of_node;
>
>         /* Init host device */
>
> --
> 2.49.0
>


From wiagn233 at outlook.com  Sun May 25 06:42:13 2025
From: wiagn233 at outlook.com (Shengyu Qu)
Date: Sun, 25 May 2025 21:42:13 +0800
Subject: [PATCH v10 RESEND] wifi: mt76: mt7915: add wds support when wed
 is enabled
In-Reply-To: <OSZPR01MB84342A0E21AAD111ED7AF6B198B82@OSZPR01MB8434.jpnprd01.prod.outlook.com>
References: <OSZPR01MB84342A0E21AAD111ED7AF6B198B82@OSZPR01MB8434.jpnprd01.prod.outlook.com>
Message-ID: <TYCPR01MB84372AF48E9D74AD3F9DC242989AA@TYCPR01MB8437.jpnprd01.prod.outlook.com>

Ping again.

? 2025/4/21 22:04, Shengyu Qu ??:
> The current WED only supports 256 wcid, whereas mt7986 can support up to
> 512 entries, so firmware provides a rule to get sta_info by DA when wcid
> is set to 0x3ff by txd. Also, WED provides a register to overwrite txd
> wcid, that is, wcid[9:8] can be overwritten by 0x3 and wcid[7:0] is set
> to 0xff by host driver.
> 
> However, firmware is unable to get sta_info from DA as DA != RA for
> 4addr cases, so firmware and wifi host driver both use wcid (256 - 271)
> and (768 ~ 783) for sync up to get correct sta_info.
> 
> Currently WDS+WED config is completely broken on MT7986/7981 devices if
> without this patch.
> 
> Reviewed-by: Ping-Ke Shih <pkshih at realtek.com>
> Tested-by: Sujuan Chen <sujuan.chen at mediatek.com>
> Co-developed-by: Bo Jiao <bo.jiao at mediatek.com>
> Signed-off-by: Bo Jiao <bo.jiao at mediatek.com>
> Signed-off-by: Sujuan Chen <sujuan.chen at mediatek.com>
> Signed-off-by: Shengyu Qu <wiagn233 at outlook.com>
> ---
> Changes since v1:
>   - Drop duplicate setting in mmio
>   - Reduce the patch size by redefining mt76_wcid_alloc
> Changes since v2:
>   - Rework wds wcid getting flow
> Changes since v3:
>   - Rebase to next-20240703
>   - Sync with downstream patch
> Changes since v4:
>   - Rebase to next-20240802
> Changes since v5:
>   - Fixed build test error reported by robot
>   - Rebase to next-20240805
> Changes since v6:
>   - Fix potential race conditions on tx/rx packets during the transition
>   - Rebase to Felix's newest codebase
> Changes since v7:
>   - Fix build fail
> Changes since v8:
>   - Changed code as Shih advised
> Changes since v9:
>   - Changed code as Shih advised
>   - Moved mt76_wcid_alloc to mt76.h
> ---
>   drivers/net/wireless/mediatek/mt76/mt76.h     | 15 ++++++
>   .../net/wireless/mediatek/mt76/mt7915/main.c  | 53 +++++++++++++++++--
>   .../net/wireless/mediatek/mt76/mt7915/mcu.c   | 18 +++++--
>   .../net/wireless/mediatek/mt76/mt7915/mcu.h   |  1 +
>   drivers/net/wireless/mediatek/mt76/util.c     | 37 +++++++++++--
>   drivers/net/wireless/mediatek/mt76/util.h     |  2 +-
>   6 files changed, 115 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/net/wireless/mediatek/mt76/mt76.h b/drivers/net/wireless/mediatek/mt76/mt76.h
> index d7cd467b812f..7f590854959e 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt76.h
> +++ b/drivers/net/wireless/mediatek/mt76/mt76.h
> @@ -28,6 +28,9 @@
>   
>   #define MT76_TOKEN_FREE_THR	64
>   
> +#define MT76_WED_WDS_MIN    256
> +#define MT76_WED_WDS_MAX    272
> +
>   #define MT_QFLAG_WED_RING	GENMASK(1, 0)
>   #define MT_QFLAG_WED_TYPE	GENMASK(4, 2)
>   #define MT_QFLAG_WED		BIT(5)
> @@ -73,6 +76,12 @@ enum mt76_wed_type {
>   	MT76_WED_RRO_Q_IND,
>   };
>   
> +enum mt76_wed_state {
> +	MT76_WED_DEFAULT,
> +	MT76_WED_ACTIVE,
> +	MT76_WED_WDS_ACTIVE,
> +};
> +
>   struct mt76_bus_ops {
>   	u32 (*rr)(struct mt76_dev *dev, u32 offset);
>   	void (*wr)(struct mt76_dev *dev, u32 offset, u32 val);
> @@ -1169,6 +1178,12 @@ void mt76_wed_dma_reset(struct mt76_dev *dev);
>   int mt76_wed_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
>   			  struct net_device *netdev, enum tc_setup_type type,
>   			  void *type_data);
> +
> +static inline int mt76_wcid_alloc(u32 *mask, int size)
> +{
> +	return __mt76_wcid_alloc(mask, size, MT76_WED_DEFAULT);
> +}
> +
>   #ifdef CONFIG_NET_MEDIATEK_SOC_WED
>   u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size);
>   int mt76_wed_offload_enable(struct mtk_wed_device *wed);
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/main.c b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
> index 3aa31c5cefa6..fcbf4f971026 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7915/main.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
> @@ -744,9 +744,16 @@ int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
>   	struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
>   	struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
>   	bool ext_phy = mvif->phy != &dev->phy;
> +	u8 flags = MT76_WED_DEFAULT;
>   	int idx;
>   
> -	idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA);
> +	if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
> +	    !is_mt7915(&dev->mt76)) {
> +		flags = test_bit(MT_WCID_FLAG_4ADDR, &msta->wcid.flags) ?
> +		       MT76_WED_WDS_ACTIVE : MT76_WED_ACTIVE;
> +	}
> +
> +	idx = __mt76_wcid_alloc(mdev->wcid_mask, MT7915_WTBL_STA, flags);
>   	if (idx < 0)
>   		return -ENOSPC;
>   
> @@ -1271,6 +1278,11 @@ static void mt7915_sta_set_4addr(struct ieee80211_hw *hw,
>   {
>   	struct mt7915_dev *dev = mt7915_hw_dev(hw);
>   	struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
> +	int min = MT76_WED_WDS_MIN, max = MT76_WED_WDS_MAX;
> +	struct ieee80211_sta *pre_sta;
> +	struct mt7915_sta *pre_msta;
> +	u8 flags = MT76_WED_DEFAULT;
> +	int tmp_idx;
>   
>   	if (enabled)
>   		set_bit(MT_WCID_FLAG_4ADDR, &msta->wcid.flags);
> @@ -1280,6 +1292,37 @@ static void mt7915_sta_set_4addr(struct ieee80211_hw *hw,
>   	if (!msta->wcid.sta)
>   		return;
>   
> +	if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
> +	    !is_mt7915(&dev->mt76) &&
> +	    (msta->wcid.idx < min || msta->wcid.idx > max - 1)) {
> +		pre_sta = kmemdup(sta, sizeof(*sta) + sizeof(*msta), GFP_KERNEL | __GFP_ZERO);
> +		if (!pre_sta)
> +			goto error_alloc;
> +		pre_msta = (struct mt7915_sta *)pre_sta->drv_priv;
> +
> +		flags = test_bit(MT_WCID_FLAG_4ADDR, &msta->wcid.flags) ?
> +			MT76_WED_WDS_ACTIVE : MT76_WED_ACTIVE;
> +
> +		tmp_idx = __mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA, flags);
> +		if (tmp_idx < 0)
> +			goto error_wcid;
> +		pre_msta->wcid.idx = (u16)tmp_idx;
> +		mt7915_mac_sta_add(&dev->mt76, vif, pre_sta);
> +		rcu_assign_pointer(dev->mt76.wcid[tmp_idx], &msta->wcid);
> +
> +		tmp_idx = msta->wcid.idx;
> +		msta->wcid.idx = pre_msta->wcid.idx;
> +		pre_msta->wcid.idx = (u16)tmp_idx;
> +		rcu_assign_pointer(dev->mt76.wcid[tmp_idx], NULL);
> +
> +		synchronize_rcu();
> +		mt7915_mac_sta_remove(&dev->mt76, vif, pre_sta);
> +
> +error_wcid:
> +		kfree(pre_sta);
> +	}
> +
> +error_alloc:
>   	mt76_connac_mcu_wtbl_update_hdr_trans(&dev->mt76, vif, sta);
>   }
>   
> @@ -1726,15 +1769,19 @@ mt7915_net_fill_forward_path(struct ieee80211_hw *hw,
>   	if (!mtk_wed_device_active(wed))
>   		return -ENODEV;
>   
> -	if (msta->wcid.idx > 0xff)
> +	if (msta->wcid.idx > MT7915_WTBL_STA)
>   		return -EIO;
>   
>   	path->type = DEV_PATH_MTK_WDMA;
>   	path->dev = ctx->dev;
>   	path->mtk_wdma.wdma_idx = wed->wdma_idx;
>   	path->mtk_wdma.bss = mvif->mt76.idx;
> -	path->mtk_wdma.wcid = is_mt7915(&dev->mt76) ? msta->wcid.idx : 0x3ff;
>   	path->mtk_wdma.queue = phy != &dev->phy;
> +	if (test_bit(MT_WCID_FLAG_4ADDR, &msta->wcid.flags) ||
> +	    is_mt7915(&dev->mt76))
> +		path->mtk_wdma.wcid = msta->wcid.idx;
> +	else
> +		path->mtk_wdma.wcid = 0x3ff;
>   
>   	ctx->dev = NULL;
>   
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
> index 427542777abc..61a854d2c416 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
> @@ -2403,10 +2403,20 @@ int mt7915_mcu_init_firmware(struct mt7915_dev *dev)
>   
>   	mt76_connac_mcu_del_wtbl_all(&dev->mt76);
>   
> -	if ((mtk_wed_device_active(&dev->mt76.mmio.wed) &&
> -	     is_mt7915(&dev->mt76)) ||
> -	    !mtk_wed_get_rx_capa(&dev->mt76.mmio.wed))
> -		mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(CAPABILITY), 0, 0, 0);
> +#if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED)
> +	if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
> +		if (is_mt7915(&dev->mt76) ||
> +		    !mtk_wed_get_rx_capa(&dev->mt76.mmio.wed))
> +			ret = mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(CAPABILITY),
> +						0, 0, 0);
> +		else
> +			ret = mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
> +						MCU_WA_PARAM_WED_VERSION,
> +						dev->mt76.mmio.wed.rev_id, 0);
> +		if (ret)
> +			return ret;
> +	}
> +#endif
>   
>   	ret = mt7915_mcu_set_mwds(dev, 1);
>   	if (ret)
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h
> index 086ad89ecd91..989f24cb49eb 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h
> +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h
> @@ -278,6 +278,7 @@ enum {
>   	MCU_WA_PARAM_PDMA_RX = 0x04,
>   	MCU_WA_PARAM_CPU_UTIL = 0x0b,
>   	MCU_WA_PARAM_RED = 0x0e,
> +	MCU_WA_PARAM_WED_VERSION = 0x32,
>   	MCU_WA_PARAM_RED_SETTING = 0x40,
>   };
>   
> diff --git a/drivers/net/wireless/mediatek/mt76/util.c b/drivers/net/wireless/mediatek/mt76/util.c
> index 95b3dc96e4c4..e80bef2b33a1 100644
> --- a/drivers/net/wireless/mediatek/mt76/util.c
> +++ b/drivers/net/wireless/mediatek/mt76/util.c
> @@ -42,8 +42,10 @@ bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
>   }
>   EXPORT_SYMBOL_GPL(____mt76_poll_msec);
>   
> -int mt76_wcid_alloc(u32 *mask, int size)
> +int __mt76_wcid_alloc(u32 *mask, int size, u8 flag)
>   {
> +	int max = MT76_WED_WDS_MAX;
> +	int min = MT76_WED_WDS_MIN;
>   	int i, idx = 0, cur;
>   
>   	for (i = 0; i < DIV_ROUND_UP(size, 32); i++) {
> @@ -53,16 +55,45 @@ int mt76_wcid_alloc(u32 *mask, int size)
>   
>   		idx--;
>   		cur = i * 32 + idx;
> -		if (cur >= size)
> +
> +		switch (flag) {
> +		case MT76_WED_ACTIVE:
> +			if (cur >= min && cur < max)
> +				continue;
> +
> +			if (cur >= size) {
> +				u32 end = max - min - 1;
> +
> +				i = min / 32;
> +				idx = ffs(~mask[i] & GENMASK(end, 0));
> +				if (!idx)
> +					goto error;
> +				idx--;
> +				cur = min + idx;
> +			}
> +
>   			break;
> +		case MT76_WED_WDS_ACTIVE:
> +			if (cur < min)
> +				continue;
> +			if (cur >= max)
> +				goto error;
> +
> +			break;
> +		default:
> +			if (cur >= size)
> +				goto error;
> +			break;
> +		}
>   
>   		mask[i] |= BIT(idx);
>   		return cur;
>   	}
>   
> +error:
>   	return -1;
>   }
> -EXPORT_SYMBOL_GPL(mt76_wcid_alloc);
> +EXPORT_SYMBOL_GPL(__mt76_wcid_alloc);
>   
>   int mt76_get_min_avg_rssi(struct mt76_dev *dev, u8 phy_idx)
>   {
> diff --git a/drivers/net/wireless/mediatek/mt76/util.h b/drivers/net/wireless/mediatek/mt76/util.h
> index 260965dde94c..fe95a847182e 100644
> --- a/drivers/net/wireless/mediatek/mt76/util.h
> +++ b/drivers/net/wireless/mediatek/mt76/util.h
> @@ -27,7 +27,7 @@ enum {
>   #define MT76_INCR(_var, _size) \
>   	(_var = (((_var) + 1) % (_size)))
>   
> -int mt76_wcid_alloc(u32 *mask, int size);
> +int __mt76_wcid_alloc(u32 *mask, int size, u8 flags);
>   
>   static inline void
>   mt76_wcid_mask_set(u32 *mask, int idx)

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From patchwork-bot+netdevbpf at kernel.org  Sun May 25 09:30:27 2025
From: patchwork-bot+netdevbpf at kernel.org (patchwork-bot+netdevbpf at kernel.org)
Date: Sun, 25 May 2025 16:30:27 +0000
Subject: [PATCH net-next] net: ethernet: mtk_eth_soc: Correct spelling
In-Reply-To: <20250520-mtk-spell-v1-1-2b0d5b4a4528@kernel.org>
References: <20250520-mtk-spell-v1-1-2b0d5b4a4528@kernel.org>
Message-ID: <174819062775.4171016.10242834560334242547.git-patchwork-notify@kernel.org>

Hello:

This patch was applied to netdev/net-next.git (main)
by David S. Miller <davem at davemloft.net>:

On Tue, 20 May 2025 15:33:33 +0100 you wrote:
> Correct spelling of platforms, various, and initial.
> As flagged by codespell.
> 
> Signed-off-by: Simon Horman <horms at kernel.org>
> ---
>  drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++--
>  drivers/net/ethernet/mediatek/mtk_wed.c     | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)

Here is the summary with links:
  - [net-next] net: ethernet: mtk_eth_soc: Correct spelling
    https://git.kernel.org/netdev/net-next/c/d09a8a4ab578

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html




From aford173 at gmail.com  Sun May 25 12:40:46 2025
From: aford173 at gmail.com (Adam Ford)
Date: Sun, 25 May 2025 14:40:46 -0500
Subject: [PATCH v3 02/22] drm: convert many bridge drivers from
 devm_kzalloc() to devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-2-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
 <20250509-drm-bridge-convert-to-alloc-api-v3-2-b8bc1f16d7aa@bootlin.com>
Message-ID: <CAHCN7xLPxmaZcOESvaU2W1gX4o1z-1A_atq4jZdrpAH5Wmht+g@mail.gmail.com>

On Fri, May 9, 2025 at 8:56?AM Luca Ceresoli <luca.ceresoli at bootlin.com> wrote:
>
> devm_drm_bridge_alloc() is the new API to be used for allocating (and
> partially initializing) a private driver struct embedding a struct
> drm_bridge.
>
> For many drivers having a simple code flow in the probe function, this
> commit does a mass conversion automatically with the following semantic
> patch. The changes have been reviewed manually for correctness as well as
> to find any false positives.
>
> The patch has been applied with the explicit exclusion of bridge/panel.c,
> handled by a separate patch.
>
> After applying the semantic patch, manually fixed these issues:
>
>  - 4 drivers need ERR_CAST() instead of PTR_ERR() as the function calling
>    devm_drm_bridge_alloc() returns a pointer
>  - re-added empty lines and comments that the script had removed but that
>    should stay
>
>   @@
>   type T;
>   identifier C;
>   identifier BR;
>   expression DEV;
>   expression FUNCS;
>   @@
>   -T *C;
>   +T *C;
>    ...
>   (
>   -C = devm_kzalloc(DEV, ...);
>   -if (!C)
>   -    return -ENOMEM;
>   +C = devm_drm_bridge_alloc(DEV, T, BR, FUNCS);
>   +if (IS_ERR(C))
>   +     return PTR_ERR(C);
>   |
>   -C = devm_kzalloc(DEV, ...);
>   -if (!C)
>   -    return ERR_PTR(-ENOMEM);
>   +C = devm_drm_bridge_alloc(DEV, T, BR, FUNCS);
>   +if (IS_ERR(C))
>   +     return PTR_ERR(C);
>   )
>    ...
>   -C->BR.funcs = FUNCS;
>
> Reviewed-by: Manikandan Muralidharan <manikandan.m at microchip.com> # microchip-lvds.c
> Reviewed-by: Douglas Anderson <dianders at chromium.org> # parade-ps8640
> Tested-by: Douglas Anderson <dianders at chromium.org> # parade-ps8640
> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
> ---
>
> Cc: Adam Ford <aford173 at gmail.com>
> Cc: Adrien Grassein <adrien.grassein at gmail.com>
> Cc: Aleksandr Mishin <amishin at t-argos.ru>
> Cc: Andy Yan <andy.yan at rock-chips.com>
> Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Cc: Benson Leung <bleung at chromium.org>
> Cc: Biju Das <biju.das.jz at bp.renesas.com>
> Cc: Christoph Fritz <chf.fritz at googlemail.com>
> Cc: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
> Cc: Detlev Casanova <detlev.casanova at collabora.com>
> Cc: Dharma Balasubiramani <dharma.b at microchip.com>
> Cc: Guenter Roeck <groeck at chromium.org>
> Cc: Heiko Stuebner <heiko at sntech.de>
> Cc: Jani Nikula <jani.nikula at intel.com>
> Cc: Janne Grunau <j at jannau.net>
> Cc: Jerome Brunet <jbrunet at baylibre.com>
> Cc: Jesse Van Gavere <jesseevg at gmail.com>
> Cc: Kevin Hilman <khilman at baylibre.com>
> Cc: Kieran Bingham <kieran.bingham+renesas at ideasonboard.com>
> Cc: Liu Ying <victor.liu at nxp.com>
> Cc: Manikandan Muralidharan <manikandan.m at microchip.com>
> Cc: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
> Cc: Matthias Brugger <matthias.bgg at gmail.com>
> Cc: Philipp Zabel <p.zabel at pengutronix.de>
> Cc: Phong LE <ple at baylibre.com>
> Cc: Sasha Finkelstein <fnkl.kernel at gmail.com>
> Cc: Sugar Zhang <sugar.zhang at rock-chips.com>
> Cc: Sui Jingfeng <sui.jingfeng at linux.dev>
> Cc: Tomi Valkeinen <tomi.valkeinen+renesas at ideasonboard.com>
> Cc: Vitalii Mordan <mordan at ispras.ru>
>
> Changed in v3:
> - manually replaced PTR_ERR() with ERR_CAST() in the 4 cases where the
>   return value is not int
> - manually added empty lines and comments that the spatch had removed
>   inappropriately
> - improved commit message
>
> Changed in v2:
> - added missing PTR_ERR() in the second spatch alternative
> ---
>  drivers/gpu/drm/adp/adp-mipi.c                      |  8 ++++----
>  drivers/gpu/drm/bridge/adv7511/adv7511_drv.c        |  8 ++++----
>  drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c  |  9 ++++-----
>  drivers/gpu/drm/bridge/aux-bridge.c                 |  8 ++++----
>  drivers/gpu/drm/bridge/aux-hpd-bridge.c             |  9 +++++----
>  drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c |  8 ++++----
>  drivers/gpu/drm/bridge/chipone-icn6211.c            |  8 ++++----
>  drivers/gpu/drm/bridge/chrontel-ch7033.c            |  8 ++++----
>  drivers/gpu/drm/bridge/cros-ec-anx7688.c            |  8 ++++----
>  drivers/gpu/drm/bridge/fsl-ldb.c                    |  7 +++----
>  drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c      |  8 ++++----
>  drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c        |  8 ++++----

For: imx8mp-hdmi-pvi.c and adv7511_drv.c

Tested-by: Adam Ford <aford173 at gmail.com> #imx8mp-beacon-kit

>  drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c     |  8 ++++----
>  drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c        |  8 ++++----
>  drivers/gpu/drm/bridge/ite-it6263.c                 |  8 ++++----
>  drivers/gpu/drm/bridge/ite-it6505.c                 |  8 ++++----
>  drivers/gpu/drm/bridge/ite-it66121.c                |  8 ++++----
>  drivers/gpu/drm/bridge/lontium-lt8912b.c            |  8 ++++----
>  drivers/gpu/drm/bridge/lontium-lt9211.c             |  7 +++----
>  drivers/gpu/drm/bridge/lontium-lt9611.c             |  8 ++++----
>  drivers/gpu/drm/bridge/lvds-codec.c                 |  9 ++++-----
>  drivers/gpu/drm/bridge/microchip-lvds.c             |  8 ++++----
>  drivers/gpu/drm/bridge/nwl-dsi.c                    |  8 ++++----
>  drivers/gpu/drm/bridge/parade-ps8622.c              |  8 ++++----
>  drivers/gpu/drm/bridge/parade-ps8640.c              |  8 ++++----
>  drivers/gpu/drm/bridge/sii9234.c                    |  8 ++++----
>  drivers/gpu/drm/bridge/sil-sii8620.c                |  8 ++++----
>  drivers/gpu/drm/bridge/simple-bridge.c              |  8 ++++----
>  drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c        |  8 ++++----
>  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c       |  8 ++++----
>  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c      |  8 ++++----
>  drivers/gpu/drm/bridge/tc358762.c                   |  8 ++++----
>  drivers/gpu/drm/bridge/tc358764.c                   |  8 ++++----
>  drivers/gpu/drm/bridge/tc358768.c                   |  8 ++++----
>  drivers/gpu/drm/bridge/tc358775.c                   |  8 ++++----
>  drivers/gpu/drm/bridge/thc63lvd1024.c               |  8 ++++----
>  drivers/gpu/drm/bridge/ti-dlpc3433.c                |  8 ++++----
>  drivers/gpu/drm/bridge/ti-tdp158.c                  |  8 ++++----
>  drivers/gpu/drm/bridge/ti-tfp410.c                  |  8 ++++----
>  drivers/gpu/drm/bridge/ti-tpd12s015.c               |  8 ++++----
>  drivers/gpu/drm/mediatek/mtk_dp.c                   |  8 ++++----
>  drivers/gpu/drm/mediatek/mtk_dpi.c                  |  8 ++++----
>  drivers/gpu/drm/mediatek/mtk_dsi.c                  |  8 ++++----
>  drivers/gpu/drm/mediatek/mtk_hdmi.c                 |  8 ++++----
>  drivers/gpu/drm/meson/meson_encoder_cvbs.c          | 10 ++++++----
>  drivers/gpu/drm/meson/meson_encoder_dsi.c           | 10 ++++++----
>  drivers/gpu/drm/meson/meson_encoder_hdmi.c          | 10 ++++++----
>  drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c         |  8 ++++----
>  drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c      |  8 ++++----
>  49 files changed, 201 insertions(+), 198 deletions(-)
>
> diff --git a/drivers/gpu/drm/adp/adp-mipi.c b/drivers/gpu/drm/adp/adp-mipi.c
> index 2b60128e2c693e9f85affff569cc57cdb6f47909..cba7d32150a98d78d07a25b1822dec6bf2f08f65 100644
> --- a/drivers/gpu/drm/adp/adp-mipi.c
> +++ b/drivers/gpu/drm/adp/adp-mipi.c
> @@ -229,9 +229,10 @@ static int adp_mipi_probe(struct platform_device *pdev)
>  {
>         struct adp_mipi_drv_private *adp;
>
> -       adp = devm_kzalloc(&pdev->dev, sizeof(*adp), GFP_KERNEL);
> -       if (!adp)
> -               return -ENOMEM;
> +       adp = devm_drm_bridge_alloc(&pdev->dev, struct adp_mipi_drv_private,
> +                                   bridge, &adp_dsi_bridge_funcs);
> +       if (IS_ERR(adp))
> +               return PTR_ERR(adp);
>
>         adp->mipi = devm_platform_ioremap_resource(pdev, 0);
>         if (IS_ERR(adp->mipi)) {
> @@ -241,7 +242,6 @@ static int adp_mipi_probe(struct platform_device *pdev)
>
>         adp->dsi.dev = &pdev->dev;
>         adp->dsi.ops = &adp_dsi_host_ops;
> -       adp->bridge.funcs = &adp_dsi_bridge_funcs;
>         adp->bridge.of_node = pdev->dev.of_node;
>         adp->bridge.type = DRM_MODE_CONNECTOR_DSI;
>         dev_set_drvdata(&pdev->dev, adp);
> diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> index 1257009e850c1b20184cfaea5b6a4440e75e10d7..8d7b007ea203d0d8be8f5b145f8531e23294dacc 100644
> --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> @@ -1224,9 +1224,10 @@ static int adv7511_probe(struct i2c_client *i2c)
>         if (!dev->of_node)
>                 return -EINVAL;
>
> -       adv7511 = devm_kzalloc(dev, sizeof(*adv7511), GFP_KERNEL);
> -       if (!adv7511)
> -               return -ENOMEM;
> +       adv7511 = devm_drm_bridge_alloc(dev, struct adv7511, bridge,
> +                                       &adv7511_bridge_funcs);
> +       if (IS_ERR(adv7511))
> +               return PTR_ERR(adv7511);
>
>         adv7511->i2c_main = i2c;
>         adv7511->powered = false;
> @@ -1327,7 +1328,6 @@ static int adv7511_probe(struct i2c_client *i2c)
>         if (ret)
>                 goto err_unregister_cec;
>
> -       adv7511->bridge.funcs = &adv7511_bridge_funcs;
>         adv7511->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID;
>         if (adv7511->i2c_main->irq)
>                 adv7511->bridge.ops |= DRM_BRIDGE_OP_HPD;
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> index a83020d6576f78372056069947783a626acf64b1..ba0fc149a9e722a53da6027a851bf62262ba64b2 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> @@ -1193,9 +1193,10 @@ static int anx78xx_i2c_probe(struct i2c_client *client)
>         bool found = false;
>         int err;
>
> -       anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL);
> -       if (!anx78xx)
> -               return -ENOMEM;
> +       anx78xx = devm_drm_bridge_alloc(&client->dev, struct anx78xx, bridge,
> +                                       &anx78xx_bridge_funcs);
> +       if (IS_ERR(anx78xx))
> +               return PTR_ERR(anx78xx);
>
>         pdata = &anx78xx->pdata;
>
> @@ -1306,8 +1307,6 @@ static int anx78xx_i2c_probe(struct i2c_client *client)
>                 goto err_poweroff;
>         }
>
> -       anx78xx->bridge.funcs = &anx78xx_bridge_funcs;
> -
>         drm_bridge_add(&anx78xx->bridge);
>
>         /* If cable is pulled out, just poweroff and wait for HPD event */
> diff --git a/drivers/gpu/drm/bridge/aux-bridge.c b/drivers/gpu/drm/bridge/aux-bridge.c
> index c179b86d208f70d95b41e6f2157b78f97bac4d8d..5b219e3b87b1df9fc4aaf2c8a6e78bac8f894628 100644
> --- a/drivers/gpu/drm/bridge/aux-bridge.c
> +++ b/drivers/gpu/drm/bridge/aux-bridge.c
> @@ -109,9 +109,10 @@ static int drm_aux_bridge_probe(struct auxiliary_device *auxdev,
>  {
>         struct drm_aux_bridge_data *data;
>
> -       data = devm_kzalloc(&auxdev->dev, sizeof(*data), GFP_KERNEL);
> -       if (!data)
> -               return -ENOMEM;
> +       data = devm_drm_bridge_alloc(&auxdev->dev, struct drm_aux_bridge_data,
> +                                    bridge, &drm_aux_bridge_funcs);
> +       if (IS_ERR(data))
> +               return PTR_ERR(data);
>
>         data->dev = &auxdev->dev;
>         data->next_bridge = devm_drm_of_get_bridge(&auxdev->dev, auxdev->dev.of_node, 0, 0);
> @@ -119,7 +120,6 @@ static int drm_aux_bridge_probe(struct auxiliary_device *auxdev,
>                 return dev_err_probe(&auxdev->dev, PTR_ERR(data->next_bridge),
>                                      "failed to acquire drm_bridge\n");
>
> -       data->bridge.funcs = &drm_aux_bridge_funcs;
>         data->bridge.of_node = data->dev->of_node;
>
>         /* passthrough data, allow everything */
> diff --git a/drivers/gpu/drm/bridge/aux-hpd-bridge.c b/drivers/gpu/drm/bridge/aux-hpd-bridge.c
> index b3f588b71a7d7ad5c2ee7b07c39079bc5ba34cee..3eb411f874e41b322f732649bd2074c5d8422566 100644
> --- a/drivers/gpu/drm/bridge/aux-hpd-bridge.c
> +++ b/drivers/gpu/drm/bridge/aux-hpd-bridge.c
> @@ -171,12 +171,13 @@ static int drm_aux_hpd_bridge_probe(struct auxiliary_device *auxdev,
>  {
>         struct drm_aux_hpd_bridge_data *data;
>
> -       data = devm_kzalloc(&auxdev->dev, sizeof(*data), GFP_KERNEL);
> -       if (!data)
> -               return -ENOMEM;
> +       data = devm_drm_bridge_alloc(&auxdev->dev,
> +                                    struct drm_aux_hpd_bridge_data, bridge,
> +                                    &drm_aux_hpd_bridge_funcs);
> +       if (IS_ERR(data))
> +               return PTR_ERR(data);
>
>         data->dev = &auxdev->dev;
> -       data->bridge.funcs = &drm_aux_hpd_bridge_funcs;
>         data->bridge.of_node = dev_get_platdata(data->dev);
>         data->bridge.ops = DRM_BRIDGE_OP_HPD;
>         data->bridge.type = id->driver_data;
> diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> index b431e7efd1f0d749320ea15b6f1f5ca13fc72800..cb5f5a8c539a471290df8435d4c2e3ed696b38d4 100644
> --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> @@ -2389,9 +2389,10 @@ static int cdns_mhdp_probe(struct platform_device *pdev)
>         int ret;
>         int irq;
>
> -       mhdp = devm_kzalloc(dev, sizeof(*mhdp), GFP_KERNEL);
> -       if (!mhdp)
> -               return -ENOMEM;
> +       mhdp = devm_drm_bridge_alloc(dev, struct cdns_mhdp_device, bridge,
> +                                    &cdns_mhdp_bridge_funcs);
> +       if (IS_ERR(mhdp))
> +               return PTR_ERR(mhdp);
>
>         clk = devm_clk_get_enabled(dev, NULL);
>         if (IS_ERR(clk)) {
> @@ -2481,7 +2482,6 @@ static int cdns_mhdp_probe(struct platform_device *pdev)
>         mhdp->display_fmt.bpc = 8;
>
>         mhdp->bridge.of_node = pdev->dev.of_node;
> -       mhdp->bridge.funcs = &cdns_mhdp_bridge_funcs;
>         mhdp->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
>                            DRM_BRIDGE_OP_HPD;
>         mhdp->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
> diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c b/drivers/gpu/drm/bridge/chipone-icn6211.c
> index 634c5b0306679d2e68798c2b9013aae4491dd44c..814713c5bea97dcdc2b847d2f266a567ef40e981 100644
> --- a/drivers/gpu/drm/bridge/chipone-icn6211.c
> +++ b/drivers/gpu/drm/bridge/chipone-icn6211.c
> @@ -691,9 +691,10 @@ static int chipone_common_probe(struct device *dev, struct chipone **icnr)
>         struct chipone *icn;
>         int ret;
>
> -       icn = devm_kzalloc(dev, sizeof(struct chipone), GFP_KERNEL);
> -       if (!icn)
> -               return -ENOMEM;
> +       icn = devm_drm_bridge_alloc(dev, struct chipone, bridge,
> +                                   &chipone_bridge_funcs);
> +       if (IS_ERR(icn))
> +               return PTR_ERR(icn);
>
>         icn->dev = dev;
>
> @@ -701,7 +702,6 @@ static int chipone_common_probe(struct device *dev, struct chipone **icnr)
>         if (ret)
>                 return ret;
>
> -       icn->bridge.funcs = &chipone_bridge_funcs;
>         icn->bridge.type = DRM_MODE_CONNECTOR_DPI;
>         icn->bridge.of_node = dev->of_node;
>
> diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c b/drivers/gpu/drm/bridge/chrontel-ch7033.c
> index 210c45c1efd48f5b541bf73da66a169c27e110b2..ab92747933568bfba77da45219e019408029f297 100644
> --- a/drivers/gpu/drm/bridge/chrontel-ch7033.c
> +++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
> @@ -536,9 +536,10 @@ static int ch7033_probe(struct i2c_client *client)
>         unsigned int val;
>         int ret;
>
> -       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> -       if (!priv)
> -               return -ENOMEM;
> +       priv = devm_drm_bridge_alloc(dev, struct ch7033_priv, bridge,
> +                                    &ch7033_bridge_funcs);
> +       if (IS_ERR(priv))
> +               return PTR_ERR(priv);
>
>         dev_set_drvdata(dev, priv);
>
> @@ -575,7 +576,6 @@ static int ch7033_probe(struct i2c_client *client)
>         }
>
>         INIT_LIST_HEAD(&priv->bridge.list);
> -       priv->bridge.funcs = &ch7033_bridge_funcs;
>         priv->bridge.of_node = dev->of_node;
>         drm_bridge_add(&priv->bridge);
>
> diff --git a/drivers/gpu/drm/bridge/cros-ec-anx7688.c b/drivers/gpu/drm/bridge/cros-ec-anx7688.c
> index c8abd9920fee956cf049bcb09827d658b7939333..a35dae9b56e247d43cac317d8bf1f904d5e7435e 100644
> --- a/drivers/gpu/drm/bridge/cros-ec-anx7688.c
> +++ b/drivers/gpu/drm/bridge/cros-ec-anx7688.c
> @@ -103,9 +103,10 @@ static int cros_ec_anx7688_bridge_probe(struct i2c_client *client)
>         u8 buffer[4];
>         int ret;
>
> -       anx7688 = devm_kzalloc(dev, sizeof(*anx7688), GFP_KERNEL);
> -       if (!anx7688)
> -               return -ENOMEM;
> +       anx7688 = devm_drm_bridge_alloc(dev, struct cros_ec_anx7688, bridge,
> +                                       &cros_ec_anx7688_bridge_funcs);
> +       if (IS_ERR(anx7688))
> +               return PTR_ERR(anx7688);
>
>         anx7688->client = client;
>         i2c_set_clientdata(client, anx7688);
> @@ -153,7 +154,6 @@ static int cros_ec_anx7688_bridge_probe(struct i2c_client *client)
>                 DRM_WARN("Old ANX7688 FW version (0x%04x), not filtering\n",
>                          fw_version);
>
> -       anx7688->bridge.funcs = &cros_ec_anx7688_bridge_funcs;
>         drm_bridge_add(&anx7688->bridge);
>
>         return 0;
> diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
> index 2cb6dfc7a6d3dbdd620a35345204f8fb9cae6651..5c3cf37200bcee1db285c97e2b463c9355ee6acb 100644
> --- a/drivers/gpu/drm/bridge/fsl-ldb.c
> +++ b/drivers/gpu/drm/bridge/fsl-ldb.c
> @@ -298,16 +298,15 @@ static int fsl_ldb_probe(struct platform_device *pdev)
>         struct fsl_ldb *fsl_ldb;
>         int dual_link;
>
> -       fsl_ldb = devm_kzalloc(dev, sizeof(*fsl_ldb), GFP_KERNEL);
> -       if (!fsl_ldb)
> -               return -ENOMEM;
> +       fsl_ldb = devm_drm_bridge_alloc(dev, struct fsl_ldb, bridge, &funcs);
> +       if (IS_ERR(fsl_ldb))
> +               return PTR_ERR(fsl_ldb);
>
>         fsl_ldb->devdata = of_device_get_match_data(dev);
>         if (!fsl_ldb->devdata)
>                 return -EINVAL;
>
>         fsl_ldb->dev = &pdev->dev;
> -       fsl_ldb->bridge.funcs = &funcs;
>         fsl_ldb->bridge.of_node = dev->of_node;
>
>         fsl_ldb->clk = devm_clk_get(dev, "ldb");
> diff --git a/drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c b/drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c
> index f072c6ed39ef183b10518b43bd6d979bc89e36f9..989bc497b05071af2a92c750d907addcfe783858 100644
> --- a/drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c
> +++ b/drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c
> @@ -59,9 +59,10 @@ struct drm_bridge *devm_imx_drm_legacy_bridge(struct device *dev,
>         struct imx_legacy_bridge *imx_bridge;
>         int ret;
>
> -       imx_bridge = devm_kzalloc(dev, sizeof(*imx_bridge), GFP_KERNEL);
> -       if (!imx_bridge)
> -               return ERR_PTR(-ENOMEM);
> +       imx_bridge = devm_drm_bridge_alloc(dev, struct imx_legacy_bridge,
> +                                          base, &imx_legacy_bridge_funcs);
> +       if (IS_ERR(imx_bridge))
> +               return ERR_CAST(imx_bridge);
>
>         ret = of_get_drm_display_mode(np,
>                                       &imx_bridge->mode,
> @@ -72,7 +73,6 @@ struct drm_bridge *devm_imx_drm_legacy_bridge(struct device *dev,
>
>         imx_bridge->mode.type |= DRM_MODE_TYPE_DRIVER;
>
> -       imx_bridge->base.funcs = &imx_legacy_bridge_funcs;
>         imx_bridge->base.of_node = np;
>         imx_bridge->base.ops = DRM_BRIDGE_OP_MODES;
>         imx_bridge->base.type = type;
> diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
> index 8a4fd7d77a8d516b3b46f41cf07d2633d23bde12..3a6f8587a257c3ceacefbed1b37024289617b7c1 100644
> --- a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
> +++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
> @@ -140,9 +140,10 @@ static int imx8mp_hdmi_pvi_probe(struct platform_device *pdev)
>         struct device_node *remote;
>         struct imx8mp_hdmi_pvi *pvi;
>
> -       pvi = devm_kzalloc(&pdev->dev, sizeof(*pvi), GFP_KERNEL);
> -       if (!pvi)
> -               return -ENOMEM;
> +       pvi = devm_drm_bridge_alloc(&pdev->dev, struct imx8mp_hdmi_pvi,
> +                                   bridge, &imx_hdmi_pvi_bridge_funcs);
> +       if (IS_ERR(pvi))
> +               return PTR_ERR(pvi);
>
>         platform_set_drvdata(pdev, pvi);
>         pvi->dev = &pdev->dev;
> @@ -166,7 +167,6 @@ static int imx8mp_hdmi_pvi_probe(struct platform_device *pdev)
>         pm_runtime_enable(&pdev->dev);
>
>         /* Register the bridge. */
> -       pvi->bridge.funcs = &imx_hdmi_pvi_bridge_funcs;
>         pvi->bridge.of_node = pdev->dev.of_node;
>         pvi->bridge.timings = pvi->next_bridge->timings;
>
> diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
> index e092c9ea99b0224802919ff84b448acb53508951..e5943506981dfb8f113c94ad52ddbba52e00ec3f 100644
> --- a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
> +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
> @@ -327,9 +327,10 @@ static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev)
>         struct device_node *np = dev->of_node;
>         int ret;
>
> -       pl = devm_kzalloc(dev, sizeof(*pl), GFP_KERNEL);
> -       if (!pl)
> -               return -ENOMEM;
> +       pl = devm_drm_bridge_alloc(dev, struct imx8qxp_pixel_link, bridge,
> +                                  &imx8qxp_pixel_link_bridge_funcs);
> +       if (IS_ERR(pl))
> +               return PTR_ERR(pl);
>
>         ret = imx_scu_get_handle(&pl->ipc_handle);
>         if (ret) {
> @@ -384,7 +385,6 @@ static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev)
>         platform_set_drvdata(pdev, pl);
>
>         pl->bridge.driver_private = pl;
> -       pl->bridge.funcs = &imx8qxp_pixel_link_bridge_funcs;
>         pl->bridge.of_node = np;
>
>         drm_bridge_add(&pl->bridge);
> diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
> index da138ab51b3bd2c6ebd3780c09818891d5320092..111310acab2ce403a62a47ecbe9d9dd372c75ecd 100644
> --- a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
> +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
> @@ -392,9 +392,10 @@ static int imx8qxp_pxl2dpi_bridge_probe(struct platform_device *pdev)
>         struct device_node *np = dev->of_node;
>         int ret;
>
> -       p2d = devm_kzalloc(dev, sizeof(*p2d), GFP_KERNEL);
> -       if (!p2d)
> -               return -ENOMEM;
> +       p2d = devm_drm_bridge_alloc(dev, struct imx8qxp_pxl2dpi, bridge,
> +                                   &imx8qxp_pxl2dpi_bridge_funcs);
> +       if (IS_ERR(p2d))
> +               return PTR_ERR(p2d);
>
>         p2d->regmap = syscon_node_to_regmap(np->parent);
>         if (IS_ERR(p2d->regmap)) {
> @@ -441,7 +442,6 @@ static int imx8qxp_pxl2dpi_bridge_probe(struct platform_device *pdev)
>         pm_runtime_enable(dev);
>
>         p2d->bridge.driver_private = p2d;
> -       p2d->bridge.funcs = &imx8qxp_pxl2dpi_bridge_funcs;
>         p2d->bridge.of_node = np;
>
>         drm_bridge_add(&p2d->bridge);
> diff --git a/drivers/gpu/drm/bridge/ite-it6263.c b/drivers/gpu/drm/bridge/ite-it6263.c
> index a3a63a977b0a8487ad38fc08e0eed08672f4d41a..c4eedf643f39e9b91efeb5a6214bf2fe6f2c040a 100644
> --- a/drivers/gpu/drm/bridge/ite-it6263.c
> +++ b/drivers/gpu/drm/bridge/ite-it6263.c
> @@ -816,9 +816,10 @@ static int it6263_probe(struct i2c_client *client)
>         struct it6263 *it;
>         int ret;
>
> -       it = devm_kzalloc(dev, sizeof(*it), GFP_KERNEL);
> -       if (!it)
> -               return -ENOMEM;
> +       it = devm_drm_bridge_alloc(dev, struct it6263, bridge,
> +                                  &it6263_bridge_funcs);
> +       if (IS_ERR(it))
> +               return PTR_ERR(it);
>
>         it->dev = dev;
>         it->hdmi_i2c = client;
> @@ -866,7 +867,6 @@ static int it6263_probe(struct i2c_client *client)
>
>         i2c_set_clientdata(client, it);
>
> -       it->bridge.funcs = &it6263_bridge_funcs;
>         it->bridge.of_node = dev->of_node;
>         /* IT6263 chip doesn't support HPD interrupt. */
>         it->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
> diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c
> index 1383d1e21afea1acb46b7bd28860908b58832dbc..b0dc9280d870c4864d43984999238e8a34bf47df 100644
> --- a/drivers/gpu/drm/bridge/ite-it6505.c
> +++ b/drivers/gpu/drm/bridge/ite-it6505.c
> @@ -3583,9 +3583,10 @@ static int it6505_i2c_probe(struct i2c_client *client)
>         struct extcon_dev *extcon;
>         int err;
>
> -       it6505 = devm_kzalloc(&client->dev, sizeof(*it6505), GFP_KERNEL);
> -       if (!it6505)
> -               return -ENOMEM;
> +       it6505 = devm_drm_bridge_alloc(&client->dev, struct it6505, bridge,
> +                                      &it6505_bridge_funcs);
> +       if (IS_ERR(it6505))
> +               return PTR_ERR(it6505);
>
>         mutex_init(&it6505->extcon_lock);
>         mutex_init(&it6505->mode_lock);
> @@ -3660,7 +3661,6 @@ static int it6505_i2c_probe(struct i2c_client *client)
>         it6505->aux.transfer = it6505_aux_transfer;
>         drm_dp_aux_init(&it6505->aux);
>
> -       it6505->bridge.funcs = &it6505_bridge_funcs;
>         it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
>         it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
>                              DRM_BRIDGE_OP_HPD;
> diff --git a/drivers/gpu/drm/bridge/ite-it66121.c b/drivers/gpu/drm/bridge/ite-it66121.c
> index 7b110ae532918d2d6f91ebc5f747c38e7e77dc07..6494f0842793829b7658b330338767e5b38a1115 100644
> --- a/drivers/gpu/drm/bridge/ite-it66121.c
> +++ b/drivers/gpu/drm/bridge/ite-it66121.c
> @@ -1516,9 +1516,10 @@ static int it66121_probe(struct i2c_client *client)
>                 return -ENXIO;
>         }
>
> -       ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
> -       if (!ctx)
> -               return -ENOMEM;
> +       ctx = devm_drm_bridge_alloc(dev, struct it66121_ctx, bridge,
> +                                   &it66121_bridge_funcs);
> +       if (IS_ERR(ctx))
> +               return PTR_ERR(ctx);
>
>         ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
>         if (!ep)
> @@ -1577,7 +1578,6 @@ static int it66121_probe(struct i2c_client *client)
>                 return -ENODEV;
>         }
>
> -       ctx->bridge.funcs = &it66121_bridge_funcs;
>         ctx->bridge.of_node = dev->of_node;
>         ctx->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
>         ctx->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID;
> diff --git a/drivers/gpu/drm/bridge/lontium-lt8912b.c b/drivers/gpu/drm/bridge/lontium-lt8912b.c
> index 3e49d855b3648880cea9bce5f3f04fbb6f838a45..bd83228b0f0eb49062ee84f62f8ae50b78bbfb0e 100644
> --- a/drivers/gpu/drm/bridge/lontium-lt8912b.c
> +++ b/drivers/gpu/drm/bridge/lontium-lt8912b.c
> @@ -761,9 +761,10 @@ static int lt8912_probe(struct i2c_client *client)
>         int ret = 0;
>         struct device *dev = &client->dev;
>
> -       lt = devm_kzalloc(dev, sizeof(struct lt8912), GFP_KERNEL);
> -       if (!lt)
> -               return -ENOMEM;
> +       lt = devm_drm_bridge_alloc(dev, struct lt8912, bridge,
> +                                  &lt8912_bridge_funcs);
> +       if (IS_ERR(lt))
> +               return PTR_ERR(lt);
>
>         lt->dev = dev;
>         lt->i2c_client[0] = client;
> @@ -778,7 +779,6 @@ static int lt8912_probe(struct i2c_client *client)
>
>         i2c_set_clientdata(client, lt);
>
> -       lt->bridge.funcs = &lt8912_bridge_funcs;
>         lt->bridge.of_node = dev->of_node;
>         lt->bridge.ops = (DRM_BRIDGE_OP_EDID |
>                           DRM_BRIDGE_OP_DETECT);
> diff --git a/drivers/gpu/drm/bridge/lontium-lt9211.c b/drivers/gpu/drm/bridge/lontium-lt9211.c
> index 9b2dac9bd63c5afd4ffbafafdbbb1230549bc36f..399fa7eebd49cc3fe9e812517fc3e8ed25004086 100644
> --- a/drivers/gpu/drm/bridge/lontium-lt9211.c
> +++ b/drivers/gpu/drm/bridge/lontium-lt9211.c
> @@ -727,9 +727,9 @@ static int lt9211_probe(struct i2c_client *client)
>         struct lt9211 *ctx;
>         int ret;
>
> -       ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
> -       if (!ctx)
> -               return -ENOMEM;
> +       ctx = devm_drm_bridge_alloc(dev, struct lt9211, bridge, &lt9211_funcs);
> +       if (IS_ERR(ctx))
> +               return PTR_ERR(ctx);
>
>         ctx->dev = dev;
>
> @@ -755,7 +755,6 @@ static int lt9211_probe(struct i2c_client *client)
>         dev_set_drvdata(dev, ctx);
>         i2c_set_clientdata(client, ctx);
>
> -       ctx->bridge.funcs = &lt9211_funcs;
>         ctx->bridge.of_node = dev->of_node;
>         drm_bridge_add(&ctx->bridge);
>
> diff --git a/drivers/gpu/drm/bridge/lontium-lt9611.c b/drivers/gpu/drm/bridge/lontium-lt9611.c
> index a35a8b8ca89c2cc138a7cb4de01c796c6211d655..d6ee79c1e42771174ee01f17448f1a8fff70b63f 100644
> --- a/drivers/gpu/drm/bridge/lontium-lt9611.c
> +++ b/drivers/gpu/drm/bridge/lontium-lt9611.c
> @@ -1072,9 +1072,10 @@ static int lt9611_probe(struct i2c_client *client)
>                 return -ENODEV;
>         }
>
> -       lt9611 = devm_kzalloc(dev, sizeof(*lt9611), GFP_KERNEL);
> -       if (!lt9611)
> -               return -ENOMEM;
> +       lt9611 = devm_drm_bridge_alloc(dev, struct lt9611, bridge,
> +                                      &lt9611_bridge_funcs);
> +       if (IS_ERR(lt9611))
> +               return PTR_ERR(lt9611);
>
>         lt9611->dev = dev;
>         lt9611->client = client;
> @@ -1127,7 +1128,6 @@ static int lt9611_probe(struct i2c_client *client)
>         /* Disable Audio InfoFrame, enabled by default */
>         regmap_update_bits(lt9611->regmap, 0x843d, LT9611_INFOFRAME_AUDIO, 0);
>
> -       lt9611->bridge.funcs = &lt9611_bridge_funcs;
>         lt9611->bridge.of_node = client->dev.of_node;
>         lt9611->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
>                              DRM_BRIDGE_OP_HPD | DRM_BRIDGE_OP_MODES |
> diff --git a/drivers/gpu/drm/bridge/lvds-codec.c b/drivers/gpu/drm/bridge/lvds-codec.c
> index 1646e454e0b0b558d00f9421f15bb7084e2aa45a..e6a7147e141b64fc77dfef03a737ee599a0ecd10 100644
> --- a/drivers/gpu/drm/bridge/lvds-codec.c
> +++ b/drivers/gpu/drm/bridge/lvds-codec.c
> @@ -118,9 +118,10 @@ static int lvds_codec_probe(struct platform_device *pdev)
>         u32 val;
>         int ret;
>
> -       lvds_codec = devm_kzalloc(dev, sizeof(*lvds_codec), GFP_KERNEL);
> -       if (!lvds_codec)
> -               return -ENOMEM;
> +       lvds_codec = devm_drm_bridge_alloc(dev, struct lvds_codec, bridge,
> +                                          &funcs);
> +       if (IS_ERR(lvds_codec))
> +               return PTR_ERR(lvds_codec);
>
>         lvds_codec->dev = &pdev->dev;
>         lvds_codec->connector_type = (uintptr_t)of_device_get_match_data(dev);
> @@ -156,8 +157,6 @@ static int lvds_codec_probe(struct platform_device *pdev)
>         if (IS_ERR(lvds_codec->panel_bridge))
>                 return PTR_ERR(lvds_codec->panel_bridge);
>
> -       lvds_codec->bridge.funcs = &funcs;
> -
>         /*
>          * Decoder input LVDS format is a property of the decoder chip or even
>          * its strapping. Handle data-mapping the same way lvds-panel does. In
> diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/bridge/microchip-lvds.c
> index 1d4ae0097df847d9f93c79eecff0c4587ae331ba..9f4ff82bc6b49010f8727da3b367f5a744a28edc 100644
> --- a/drivers/gpu/drm/bridge/microchip-lvds.c
> +++ b/drivers/gpu/drm/bridge/microchip-lvds.c
> @@ -157,9 +157,10 @@ static int mchp_lvds_probe(struct platform_device *pdev)
>         if (!dev->of_node)
>                 return -ENODEV;
>
> -       lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
> -       if (!lvds)
> -               return -ENOMEM;
> +       lvds = devm_drm_bridge_alloc(&pdev->dev, struct mchp_lvds, bridge,
> +                                    &mchp_lvds_bridge_funcs);
> +       if (IS_ERR(lvds))
> +               return PTR_ERR(lvds);
>
>         lvds->dev = dev;
>
> @@ -192,7 +193,6 @@ static int mchp_lvds_probe(struct platform_device *pdev)
>
>         lvds->bridge.of_node = dev->of_node;
>         lvds->bridge.type = DRM_MODE_CONNECTOR_LVDS;
> -       lvds->bridge.funcs = &mchp_lvds_bridge_funcs;
>
>         dev_set_drvdata(dev, lvds);
>         ret = devm_pm_runtime_enable(dev);
> diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
> index 55912ae11f46a1d551e11f93a306a8a00ef3f7d8..2f7429b24fc20db104dec17182f1119c6c75e600 100644
> --- a/drivers/gpu/drm/bridge/nwl-dsi.c
> +++ b/drivers/gpu/drm/bridge/nwl-dsi.c
> @@ -1149,9 +1149,10 @@ static int nwl_dsi_probe(struct platform_device *pdev)
>         struct nwl_dsi *dsi;
>         int ret;
>
> -       dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
> -       if (!dsi)
> -               return -ENOMEM;
> +       dsi = devm_drm_bridge_alloc(dev, struct nwl_dsi, bridge,
> +                                   &nwl_dsi_bridge_funcs);
> +       if (IS_ERR(dsi))
> +               return PTR_ERR(dsi);
>
>         dsi->dev = dev;
>
> @@ -1180,7 +1181,6 @@ static int nwl_dsi_probe(struct platform_device *pdev)
>                 dsi->quirks = (uintptr_t)attr->data;
>
>         dsi->bridge.driver_private = dsi;
> -       dsi->bridge.funcs = &nwl_dsi_bridge_funcs;
>         dsi->bridge.of_node = dev->of_node;
>         dsi->bridge.timings = &nwl_dsi_timings;
>         dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
> diff --git a/drivers/gpu/drm/bridge/parade-ps8622.c b/drivers/gpu/drm/bridge/parade-ps8622.c
> index 8726fefc5c654e49bce029d943d241789ca4f802..f879a1df077d25d0c5121e51aa067f511a41a9bd 100644
> --- a/drivers/gpu/drm/bridge/parade-ps8622.c
> +++ b/drivers/gpu/drm/bridge/parade-ps8622.c
> @@ -449,9 +449,10 @@ static int ps8622_probe(struct i2c_client *client)
>         struct drm_bridge *panel_bridge;
>         int ret;
>
> -       ps8622 = devm_kzalloc(dev, sizeof(*ps8622), GFP_KERNEL);
> -       if (!ps8622)
> -               return -ENOMEM;
> +       ps8622 = devm_drm_bridge_alloc(dev, struct ps8622_bridge, bridge,
> +                                      &ps8622_bridge_funcs);
> +       if (IS_ERR(ps8622))
> +               return PTR_ERR(ps8622);
>
>         panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0);
>         if (IS_ERR(panel_bridge))
> @@ -509,7 +510,6 @@ static int ps8622_probe(struct i2c_client *client)
>                 ps8622->bl->props.brightness = PS8622_MAX_BRIGHTNESS;
>         }
>
> -       ps8622->bridge.funcs = &ps8622_bridge_funcs;
>         ps8622->bridge.type = DRM_MODE_CONNECTOR_LVDS;
>         ps8622->bridge.of_node = dev->of_node;
>         drm_bridge_add(&ps8622->bridge);
> diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c
> index 2422ff68c1042bd8eaa6821ff387d4faad47c550..825777a5758f67b5bdaa5f9de2e0e4f597f0f7a4 100644
> --- a/drivers/gpu/drm/bridge/parade-ps8640.c
> +++ b/drivers/gpu/drm/bridge/parade-ps8640.c
> @@ -636,9 +636,10 @@ static int ps8640_probe(struct i2c_client *client)
>         int ret;
>         u32 i;
>
> -       ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
> -       if (!ps_bridge)
> -               return -ENOMEM;
> +       ps_bridge = devm_drm_bridge_alloc(dev, struct ps8640, bridge,
> +                                         &ps8640_bridge_funcs);
> +       if (IS_ERR(ps_bridge))
> +               return PTR_ERR(ps_bridge);
>
>         mutex_init(&ps_bridge->aux_lock);
>
> @@ -662,7 +663,6 @@ static int ps8640_probe(struct i2c_client *client)
>         if (IS_ERR(ps_bridge->gpio_reset))
>                 return PTR_ERR(ps_bridge->gpio_reset);
>
> -       ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
>         ps_bridge->bridge.of_node = dev->of_node;
>         ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP;
>
> diff --git a/drivers/gpu/drm/bridge/sii9234.c b/drivers/gpu/drm/bridge/sii9234.c
> index cd7837c9a6e00b572a3fb65e5e0c9fa884555a73..bb1bed03eb5b7ae67f752c0d593dc54131e9e370 100644
> --- a/drivers/gpu/drm/bridge/sii9234.c
> +++ b/drivers/gpu/drm/bridge/sii9234.c
> @@ -888,9 +888,10 @@ static int sii9234_probe(struct i2c_client *client)
>         struct device *dev = &client->dev;
>         int ret;
>
> -       ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
> -       if (!ctx)
> -               return -ENOMEM;
> +       ctx = devm_drm_bridge_alloc(dev, struct sii9234, bridge,
> +                                   &sii9234_bridge_funcs);
> +       if (IS_ERR(ctx))
> +               return PTR_ERR(ctx);
>
>         ctx->dev = dev;
>         mutex_init(&ctx->lock);
> @@ -921,7 +922,6 @@ static int sii9234_probe(struct i2c_client *client)
>
>         i2c_set_clientdata(client, ctx);
>
> -       ctx->bridge.funcs = &sii9234_bridge_funcs;
>         ctx->bridge.of_node = dev->of_node;
>         drm_bridge_add(&ctx->bridge);
>
> diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c
> index 3af650dc92a1612ca88fe378319519546b79901f..9e48ad39e1cc995768d767c27b8116d7baa2f47e 100644
> --- a/drivers/gpu/drm/bridge/sil-sii8620.c
> +++ b/drivers/gpu/drm/bridge/sil-sii8620.c
> @@ -2291,9 +2291,10 @@ static int sii8620_probe(struct i2c_client *client)
>         struct sii8620 *ctx;
>         int ret;
>
> -       ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
> -       if (!ctx)
> -               return -ENOMEM;
> +       ctx = devm_drm_bridge_alloc(dev, struct sii8620, bridge,
> +                                   &sii8620_bridge_funcs);
> +       if (IS_ERR(ctx))
> +               return PTR_ERR(ctx);
>
>         ctx->dev = dev;
>         mutex_init(&ctx->lock);
> @@ -2336,7 +2337,6 @@ static int sii8620_probe(struct i2c_client *client)
>
>         i2c_set_clientdata(client, ctx);
>
> -       ctx->bridge.funcs = &sii8620_bridge_funcs;
>         ctx->bridge.of_node = dev->of_node;
>         drm_bridge_add(&ctx->bridge);
>
> diff --git a/drivers/gpu/drm/bridge/simple-bridge.c b/drivers/gpu/drm/bridge/simple-bridge.c
> index 70db5b99e5bb84f099ec54cf62abbda53475311d..c66bd913e33ae311a980251348199889ef5b99af 100644
> --- a/drivers/gpu/drm/bridge/simple-bridge.c
> +++ b/drivers/gpu/drm/bridge/simple-bridge.c
> @@ -168,9 +168,10 @@ static int simple_bridge_probe(struct platform_device *pdev)
>         struct simple_bridge *sbridge;
>         struct device_node *remote;
>
> -       sbridge = devm_kzalloc(&pdev->dev, sizeof(*sbridge), GFP_KERNEL);
> -       if (!sbridge)
> -               return -ENOMEM;
> +       sbridge = devm_drm_bridge_alloc(&pdev->dev, struct simple_bridge,
> +                                       bridge, &simple_bridge_bridge_funcs);
> +       if (IS_ERR(sbridge))
> +               return PTR_ERR(sbridge);
>
>         sbridge->info = of_device_get_match_data(&pdev->dev);
>
> @@ -204,7 +205,6 @@ static int simple_bridge_probe(struct platform_device *pdev)
>                                      "Unable to retrieve enable GPIO\n");
>
>         /* Register the bridge. */
> -       sbridge->bridge.funcs = &simple_bridge_bridge_funcs;
>         sbridge->bridge.of_node = pdev->dev.of_node;
>         sbridge->bridge.timings = sbridge->info->timings;
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
> index 5e5f8c2f95be1f5c4633f1093b17a00f9425bb37..94dddaf49b3c1fa115f376e5cf1c2f515f2594ea 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
> @@ -1045,9 +1045,10 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
>                 return ERR_PTR(-ENODEV);
>         }
>
> -       hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
> -       if (!hdmi)
> -               return ERR_PTR(-ENOMEM);
> +       hdmi = devm_drm_bridge_alloc(dev, struct dw_hdmi_qp, bridge,
> +                                    &dw_hdmi_qp_bridge_funcs);
> +       if (IS_ERR(hdmi))
> +               return ERR_CAST(hdmi);
>
>         hdmi->dev = dev;
>
> @@ -1073,7 +1074,6 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
>                 return ERR_PTR(ret);
>
>         hdmi->bridge.driver_private = hdmi;
> -       hdmi->bridge.funcs = &dw_hdmi_qp_bridge_funcs;
>         hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT |
>                            DRM_BRIDGE_OP_EDID |
>                            DRM_BRIDGE_OP_HDMI |
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index b08ada920a501d6a62f39581944a87019f5e5c15..c0dc0f2976b92f5a4eb2416de8f510ec7214e562 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -1194,9 +1194,10 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>         struct dw_mipi_dsi *dsi;
>         int ret;
>
> -       dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
> -       if (!dsi)
> -               return ERR_PTR(-ENOMEM);
> +       dsi = devm_drm_bridge_alloc(dev, struct dw_mipi_dsi, bridge,
> +                                   &dw_mipi_dsi_bridge_funcs);
> +       if (IS_ERR(dsi))
> +               return ERR_CAST(dsi);
>
>         dsi->dev = dev;
>         dsi->plat_data = plat_data;
> @@ -1265,7 +1266,6 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>         }
>
>         dsi->bridge.driver_private = dsi;
> -       dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
>         dsi->bridge.of_node = pdev->dev.of_node;
>
>         return dsi;
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
> index c76f5f2e74d14bd372f969c6c7832aa57f80772b..fc91aca95d126ae37726ccd939fdc8657151ca81 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
> @@ -914,9 +914,10 @@ __dw_mipi_dsi2_probe(struct platform_device *pdev,
>         struct dw_mipi_dsi2 *dsi2;
>         int ret;
>
> -       dsi2 = devm_kzalloc(dev, sizeof(*dsi2), GFP_KERNEL);
> -       if (!dsi2)
> -               return ERR_PTR(-ENOMEM);
> +       dsi2 = devm_drm_bridge_alloc(dev, struct dw_mipi_dsi2, bridge,
> +                                    &dw_mipi_dsi2_bridge_funcs);
> +       if (IS_ERR(dsi2))
> +               return ERR_CAST(dsi2);
>
>         dsi2->dev = dev;
>         dsi2->plat_data = plat_data;
> @@ -981,7 +982,6 @@ __dw_mipi_dsi2_probe(struct platform_device *pdev,
>         }
>
>         dsi2->bridge.driver_private = dsi2;
> -       dsi2->bridge.funcs = &dw_mipi_dsi2_bridge_funcs;
>         dsi2->bridge.of_node = pdev->dev.of_node;
>
>         return dsi2;
> diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc358762.c
> index edf01476f2ef6e05ef2c144ff4467e7f6babc4c6..98df3e667d4aac48c19c82c8bc9e116b36a4cec8 100644
> --- a/drivers/gpu/drm/bridge/tc358762.c
> +++ b/drivers/gpu/drm/bridge/tc358762.c
> @@ -265,9 +265,10 @@ static int tc358762_probe(struct mipi_dsi_device *dsi)
>         struct tc358762 *ctx;
>         int ret;
>
> -       ctx = devm_kzalloc(dev, sizeof(struct tc358762), GFP_KERNEL);
> -       if (!ctx)
> -               return -ENOMEM;
> +       ctx = devm_drm_bridge_alloc(dev, struct tc358762, bridge,
> +                                   &tc358762_bridge_funcs);
> +       if (IS_ERR(ctx))
> +               return PTR_ERR(ctx);
>
>         mipi_dsi_set_drvdata(dsi, ctx);
>
> @@ -288,7 +289,6 @@ static int tc358762_probe(struct mipi_dsi_device *dsi)
>         if (ret < 0)
>                 return ret;
>
> -       ctx->bridge.funcs = &tc358762_bridge_funcs;
>         ctx->bridge.type = DRM_MODE_CONNECTOR_DPI;
>         ctx->bridge.of_node = dev->of_node;
>         ctx->bridge.pre_enable_prev_first = true;
> diff --git a/drivers/gpu/drm/bridge/tc358764.c b/drivers/gpu/drm/bridge/tc358764.c
> index 3f76c890fad9ffa50dc02f289a37378332830516..084e9d898e226ecfa618a3c91c0786d2f83fa51b 100644
> --- a/drivers/gpu/drm/bridge/tc358764.c
> +++ b/drivers/gpu/drm/bridge/tc358764.c
> @@ -347,9 +347,10 @@ static int tc358764_probe(struct mipi_dsi_device *dsi)
>         struct tc358764 *ctx;
>         int ret;
>
> -       ctx = devm_kzalloc(dev, sizeof(struct tc358764), GFP_KERNEL);
> -       if (!ctx)
> -               return -ENOMEM;
> +       ctx = devm_drm_bridge_alloc(dev, struct tc358764, bridge,
> +                                   &tc358764_bridge_funcs);
> +       if (IS_ERR(ctx))
> +               return PTR_ERR(ctx);
>
>         mipi_dsi_set_drvdata(dsi, ctx);
>
> @@ -368,7 +369,6 @@ static int tc358764_probe(struct mipi_dsi_device *dsi)
>         if (ret < 0)
>                 return ret;
>
> -       ctx->bridge.funcs = &tc358764_bridge_funcs;
>         ctx->bridge.of_node = dev->of_node;
>         ctx->bridge.pre_enable_prev_first = true;
>
> diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c
> index 063f217a17b6cf32e9793b8a96a5ac6128584098..fbdc44e162293f2f9b090bc956604184a2a406b2 100644
> --- a/drivers/gpu/drm/bridge/tc358768.c
> +++ b/drivers/gpu/drm/bridge/tc358768.c
> @@ -1287,9 +1287,10 @@ static int tc358768_i2c_probe(struct i2c_client *client)
>         if (!np)
>                 return -ENODEV;
>
> -       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> -       if (!priv)
> -               return -ENOMEM;
> +       priv = devm_drm_bridge_alloc(dev, struct tc358768_priv, bridge,
> +                                    &tc358768_bridge_funcs);
> +       if (IS_ERR(priv))
> +               return PTR_ERR(priv);
>
>         dev_set_drvdata(dev, priv);
>         priv->dev = dev;
> @@ -1321,7 +1322,6 @@ static int tc358768_i2c_probe(struct i2c_client *client)
>         priv->dsi_host.dev = dev;
>         priv->dsi_host.ops = &tc358768_dsi_host_ops;
>
> -       priv->bridge.funcs = &tc358768_bridge_funcs;
>         priv->bridge.timings = &default_tc358768_timings;
>         priv->bridge.of_node = np;
>
> diff --git a/drivers/gpu/drm/bridge/tc358775.c b/drivers/gpu/drm/bridge/tc358775.c
> index 1b10e6ee1724ffb4bb8946f86d2f18e53428381a..366b12db0e7cbfb45b3dfc2a83a7af580cfde41f 100644
> --- a/drivers/gpu/drm/bridge/tc358775.c
> +++ b/drivers/gpu/drm/bridge/tc358775.c
> @@ -659,9 +659,10 @@ static int tc_probe(struct i2c_client *client)
>         struct tc_data *tc;
>         int ret;
>
> -       tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
> -       if (!tc)
> -               return -ENOMEM;
> +       tc = devm_drm_bridge_alloc(dev, struct tc_data, bridge,
> +                                  &tc_bridge_funcs);
> +       if (IS_ERR(tc))
> +               return PTR_ERR(tc);
>
>         tc->dev = dev;
>         tc->i2c = client;
> @@ -701,7 +702,6 @@ static int tc_probe(struct i2c_client *client)
>                 return ret;
>         }
>
> -       tc->bridge.funcs = &tc_bridge_funcs;
>         tc->bridge.of_node = dev->of_node;
>         tc->bridge.pre_enable_prev_first = true;
>         drm_bridge_add(&tc->bridge);
> diff --git a/drivers/gpu/drm/bridge/thc63lvd1024.c b/drivers/gpu/drm/bridge/thc63lvd1024.c
> index e2fc78adebcf22f0d8cdb484078e37b748b776c6..2cb7cd0c060824256bbfa511f833cc00437d318b 100644
> --- a/drivers/gpu/drm/bridge/thc63lvd1024.c
> +++ b/drivers/gpu/drm/bridge/thc63lvd1024.c
> @@ -181,9 +181,10 @@ static int thc63_probe(struct platform_device *pdev)
>         struct thc63_dev *thc63;
>         int ret;
>
> -       thc63 = devm_kzalloc(&pdev->dev, sizeof(*thc63), GFP_KERNEL);
> -       if (!thc63)
> -               return -ENOMEM;
> +       thc63 = devm_drm_bridge_alloc(&pdev->dev, struct thc63_dev, bridge,
> +                                     &thc63_bridge_func);
> +       if (IS_ERR(thc63))
> +               return PTR_ERR(thc63);
>
>         thc63->dev = &pdev->dev;
>         platform_set_drvdata(pdev, thc63);
> @@ -208,7 +209,6 @@ static int thc63_probe(struct platform_device *pdev)
>
>         thc63->bridge.driver_private = thc63;
>         thc63->bridge.of_node = pdev->dev.of_node;
> -       thc63->bridge.funcs = &thc63_bridge_func;
>         thc63->bridge.timings = &thc63->timings;
>
>         drm_bridge_add(&thc63->bridge);
> diff --git a/drivers/gpu/drm/bridge/ti-dlpc3433.c b/drivers/gpu/drm/bridge/ti-dlpc3433.c
> index 47638d1c96ec5ad999604c8c7e8839ff85936d98..b07f7c9d5890967a6db7bb01a9695abc809babbd 100644
> --- a/drivers/gpu/drm/bridge/ti-dlpc3433.c
> +++ b/drivers/gpu/drm/bridge/ti-dlpc3433.c
> @@ -348,9 +348,10 @@ static int dlpc3433_probe(struct i2c_client *client)
>         struct dlpc *dlpc;
>         int ret;
>
> -       dlpc = devm_kzalloc(dev, sizeof(*dlpc), GFP_KERNEL);
> -       if (!dlpc)
> -               return -ENOMEM;
> +       dlpc = devm_drm_bridge_alloc(dev, struct dlpc, bridge,
> +                                    &dlpc_bridge_funcs);
> +       if (IS_ERR(dlpc))
> +               return PTR_ERR(dlpc);
>
>         dlpc->dev = dev;
>
> @@ -365,7 +366,6 @@ static int dlpc3433_probe(struct i2c_client *client)
>         dev_set_drvdata(dev, dlpc);
>         i2c_set_clientdata(client, dlpc);
>
> -       dlpc->bridge.funcs = &dlpc_bridge_funcs;
>         dlpc->bridge.of_node = dev->of_node;
>         drm_bridge_add(&dlpc->bridge);
>
> diff --git a/drivers/gpu/drm/bridge/ti-tdp158.c b/drivers/gpu/drm/bridge/ti-tdp158.c
> index cca75443f0121e39527a6cecf711eff2c0d507b5..27053d020df7c6fabbd5ce631b46c3f2358f12b2 100644
> --- a/drivers/gpu/drm/bridge/ti-tdp158.c
> +++ b/drivers/gpu/drm/bridge/ti-tdp158.c
> @@ -68,9 +68,10 @@ static int tdp158_probe(struct i2c_client *client)
>         struct tdp158 *tdp158;
>         struct device *dev = &client->dev;
>
> -       tdp158 = devm_kzalloc(dev, sizeof(*tdp158), GFP_KERNEL);
> -       if (!tdp158)
> -               return -ENOMEM;
> +       tdp158 = devm_drm_bridge_alloc(dev, struct tdp158, bridge,
> +                                      &tdp158_bridge_funcs);
> +       if (IS_ERR(tdp158))
> +               return PTR_ERR(tdp158);
>
>         tdp158->next = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
>         if (IS_ERR(tdp158->next))
> @@ -89,7 +90,6 @@ static int tdp158_probe(struct i2c_client *client)
>                 return dev_err_probe(dev, PTR_ERR(tdp158->enable), "enable");
>
>         tdp158->bridge.of_node = dev->of_node;
> -       tdp158->bridge.funcs = &tdp158_bridge_funcs;
>         tdp158->bridge.driver_private = tdp158;
>         tdp158->dev = dev;
>
> diff --git a/drivers/gpu/drm/bridge/ti-tfp410.c b/drivers/gpu/drm/bridge/ti-tfp410.c
> index e15d232ddbac55c6f5f966471a6c63f9c29a06c1..549e8e8edeb4f2f27d86a86fa0312e727380ecd9 100644
> --- a/drivers/gpu/drm/bridge/ti-tfp410.c
> +++ b/drivers/gpu/drm/bridge/ti-tfp410.c
> @@ -341,14 +341,14 @@ static int tfp410_init(struct device *dev, bool i2c)
>                 return -ENXIO;
>         }
>
> -       dvi = devm_kzalloc(dev, sizeof(*dvi), GFP_KERNEL);
> -       if (!dvi)
> -               return -ENOMEM;
> +       dvi = devm_drm_bridge_alloc(dev, struct tfp410, bridge,
> +                                   &tfp410_bridge_funcs);
> +       if (IS_ERR(dvi))
> +               return PTR_ERR(dvi);
>
>         dvi->dev = dev;
>         dev_set_drvdata(dev, dvi);
>
> -       dvi->bridge.funcs = &tfp410_bridge_funcs;
>         dvi->bridge.of_node = dev->of_node;
>         dvi->bridge.timings = &dvi->timings;
>         dvi->bridge.type = DRM_MODE_CONNECTOR_DVID;
> diff --git a/drivers/gpu/drm/bridge/ti-tpd12s015.c b/drivers/gpu/drm/bridge/ti-tpd12s015.c
> index 1c289051a5987e0aec4c286ef4c01ee1a2f9421f..0919364e80d1f69b95a99e76daa915bee0b43d45 100644
> --- a/drivers/gpu/drm/bridge/ti-tpd12s015.c
> +++ b/drivers/gpu/drm/bridge/ti-tpd12s015.c
> @@ -116,13 +116,13 @@ static int tpd12s015_probe(struct platform_device *pdev)
>         struct gpio_desc *gpio;
>         int ret;
>
> -       tpd = devm_kzalloc(&pdev->dev, sizeof(*tpd), GFP_KERNEL);
> -       if (!tpd)
> -               return -ENOMEM;
> +       tpd = devm_drm_bridge_alloc(&pdev->dev, struct tpd12s015_device,
> +                                   bridge, &tpd12s015_bridge_funcs);
> +       if (IS_ERR(tpd))
> +               return PTR_ERR(tpd);
>
>         platform_set_drvdata(pdev, tpd);
>
> -       tpd->bridge.funcs = &tpd12s015_bridge_funcs;
>         tpd->bridge.of_node = pdev->dev.of_node;
>         tpd->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
>         tpd->bridge.ops = DRM_BRIDGE_OP_DETECT;
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
> index b2408abb9d491bf25773d4dcc1be73c89cf208ce..bb80686a70e17dc79daa724b44e781a81ce4de85 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> @@ -2725,9 +2725,10 @@ static int mtk_dp_probe(struct platform_device *pdev)
>         struct device *dev = &pdev->dev;
>         int ret;
>
> -       mtk_dp = devm_kzalloc(dev, sizeof(*mtk_dp), GFP_KERNEL);
> -       if (!mtk_dp)
> -               return -ENOMEM;
> +       mtk_dp = devm_drm_bridge_alloc(dev, struct mtk_dp, bridge,
> +                                      &mtk_dp_bridge_funcs);
> +       if (IS_ERR(mtk_dp))
> +               return PTR_ERR(mtk_dp);
>
>         mtk_dp->dev = dev;
>         mtk_dp->data = (struct mtk_dp_data *)of_device_get_match_data(dev);
> @@ -2785,7 +2786,6 @@ static int mtk_dp_probe(struct platform_device *pdev)
>         if (ret)
>                 return ret;
>
> -       mtk_dp->bridge.funcs = &mtk_dp_bridge_funcs;
>         mtk_dp->bridge.of_node = dev->of_node;
>         mtk_dp->bridge.type = mtk_dp->data->bridge_type;
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 0f3b1ef8e497354edaf0a56e24660bf356fe01ac..9669bf4b80a14086159ae245ed51dd587b514bfb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -1179,9 +1179,10 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>         struct mtk_dpi *dpi;
>         int ret;
>
> -       dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
> -       if (!dpi)
> -               return -ENOMEM;
> +       dpi = devm_drm_bridge_alloc(dev, struct mtk_dpi, bridge,
> +                                   &mtk_dpi_bridge_funcs);
> +       if (IS_ERR(dpi))
> +               return PTR_ERR(dpi);
>
>         dpi->dev = dev;
>         dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev);
> @@ -1233,7 +1234,6 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>
>         platform_set_drvdata(pdev, dpi);
>
> -       dpi->bridge.funcs = &mtk_dpi_bridge_funcs;
>         dpi->bridge.of_node = dev->of_node;
>         dpi->bridge.type = DRM_MODE_CONNECTOR_DPI;
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 4fe1f38a3c4b7fcbbdbf7f6a82f66c9e2b546c02..d7726091819c4762698b41060b3d4d8d27940238 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -1196,9 +1196,10 @@ static int mtk_dsi_probe(struct platform_device *pdev)
>         int irq_num;
>         int ret;
>
> -       dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
> -       if (!dsi)
> -               return -ENOMEM;
> +       dsi = devm_drm_bridge_alloc(dev, struct mtk_dsi, bridge,
> +                                   &mtk_dsi_bridge_funcs);
> +       if (IS_ERR(dsi))
> +               return PTR_ERR(dsi);
>
>         dsi->driver_data = of_device_get_match_data(dev);
>
> @@ -1246,7 +1247,6 @@ static int mtk_dsi_probe(struct platform_device *pdev)
>
>         platform_set_drvdata(pdev, dsi);
>
> -       dsi->bridge.funcs = &mtk_dsi_bridge_funcs;
>         dsi->bridge.of_node = dev->of_node;
>         dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index c9d0c335c519d405d480ffdc2feaa5b847c0e1bb..76aecad116bad23384db438ee2649f5f0b31ae50 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1690,9 +1690,10 @@ static int mtk_hdmi_probe(struct platform_device *pdev)
>         struct device *dev = &pdev->dev;
>         int ret;
>
> -       hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
> -       if (!hdmi)
> -               return -ENOMEM;
> +       hdmi = devm_drm_bridge_alloc(dev, struct mtk_hdmi, bridge,
> +                                    &mtk_hdmi_bridge_funcs);
> +       if (IS_ERR(hdmi))
> +               return PTR_ERR(hdmi);
>
>         hdmi->dev = dev;
>         hdmi->conf = of_device_get_match_data(dev);
> @@ -1719,7 +1720,6 @@ static int mtk_hdmi_probe(struct platform_device *pdev)
>                 return dev_err_probe(dev, ret,
>                                      "Failed to register audio driver\n");
>
> -       hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
>         hdmi->bridge.of_node = pdev->dev.of_node;
>         hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
>                          | DRM_BRIDGE_OP_HPD;
> diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
> index c9678dc68fa142882e2beb24fe81185fbdef733b..dc374bfc5951c0f13fc28f44325aa845ab590056 100644
> --- a/drivers/gpu/drm/meson/meson_encoder_cvbs.c
> +++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
> @@ -227,9 +227,12 @@ int meson_encoder_cvbs_probe(struct meson_drm *priv)
>         struct device_node *remote;
>         int ret;
>
> -       meson_encoder_cvbs = devm_kzalloc(priv->dev, sizeof(*meson_encoder_cvbs), GFP_KERNEL);
> -       if (!meson_encoder_cvbs)
> -               return -ENOMEM;
> +       meson_encoder_cvbs = devm_drm_bridge_alloc(priv->dev,
> +                                                  struct meson_encoder_cvbs,
> +                                                  bridge,
> +                                                  &meson_encoder_cvbs_bridge_funcs);
> +       if (IS_ERR(meson_encoder_cvbs))
> +               return PTR_ERR(meson_encoder_cvbs);
>
>         /* CVBS Connector Bridge */
>         remote = of_graph_get_remote_node(priv->dev->of_node, 0, 0);
> @@ -245,7 +248,6 @@ int meson_encoder_cvbs_probe(struct meson_drm *priv)
>                                      "Failed to find CVBS Connector bridge\n");
>
>         /* CVBS Encoder Bridge */
> -       meson_encoder_cvbs->bridge.funcs = &meson_encoder_cvbs_bridge_funcs;
>         meson_encoder_cvbs->bridge.of_node = priv->dev->of_node;
>         meson_encoder_cvbs->bridge.type = DRM_MODE_CONNECTOR_Composite;
>         meson_encoder_cvbs->bridge.ops = DRM_BRIDGE_OP_MODES;
> diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.c b/drivers/gpu/drm/meson/meson_encoder_dsi.c
> index 3db518e5f95d324c218b730e0948c3dc845382bd..6c6624f9ba24a182900215d65b3ad7ab8aab6cf8 100644
> --- a/drivers/gpu/drm/meson/meson_encoder_dsi.c
> +++ b/drivers/gpu/drm/meson/meson_encoder_dsi.c
> @@ -106,9 +106,12 @@ int meson_encoder_dsi_probe(struct meson_drm *priv)
>         struct device_node *remote;
>         int ret;
>
> -       meson_encoder_dsi = devm_kzalloc(priv->dev, sizeof(*meson_encoder_dsi), GFP_KERNEL);
> -       if (!meson_encoder_dsi)
> -               return -ENOMEM;
> +       meson_encoder_dsi = devm_drm_bridge_alloc(priv->dev,
> +                                                 struct meson_encoder_dsi,
> +                                                 bridge,
> +                                                 &meson_encoder_dsi_bridge_funcs);
> +       if (IS_ERR(meson_encoder_dsi))
> +               return PTR_ERR(meson_encoder_dsi);
>
>         /* DSI Transceiver Bridge */
>         remote = of_graph_get_remote_node(priv->dev->of_node, 2, 0);
> @@ -123,7 +126,6 @@ int meson_encoder_dsi_probe(struct meson_drm *priv)
>                                      "Failed to find DSI transceiver bridge\n");
>
>         /* DSI Encoder Bridge */
> -       meson_encoder_dsi->bridge.funcs = &meson_encoder_dsi_bridge_funcs;
>         meson_encoder_dsi->bridge.of_node = priv->dev->of_node;
>         meson_encoder_dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
>
> diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
> index 040c04b5dff9f0d4e2875e344c076bb8ab635c76..5a0d37a257f53c22165fad1a32e3c7522b8dd7f1 100644
> --- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c
> +++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
> @@ -376,9 +376,12 @@ int meson_encoder_hdmi_probe(struct meson_drm *priv)
>         struct device_node *remote;
>         int ret;
>
> -       meson_encoder_hdmi = devm_kzalloc(priv->dev, sizeof(*meson_encoder_hdmi), GFP_KERNEL);
> -       if (!meson_encoder_hdmi)
> -               return -ENOMEM;
> +       meson_encoder_hdmi = devm_drm_bridge_alloc(priv->dev,
> +                                                  struct meson_encoder_hdmi,
> +                                                  bridge,
> +                                                  &meson_encoder_hdmi_bridge_funcs);
> +       if (IS_ERR(meson_encoder_hdmi))
> +               return PTR_ERR(meson_encoder_hdmi);
>
>         /* HDMI Transceiver Bridge */
>         remote = of_graph_get_remote_node(priv->dev->of_node, 1, 0);
> @@ -395,7 +398,6 @@ int meson_encoder_hdmi_probe(struct meson_drm *priv)
>         }
>
>         /* HDMI Encoder Bridge */
> -       meson_encoder_hdmi->bridge.funcs = &meson_encoder_hdmi_bridge_funcs;
>         meson_encoder_hdmi->bridge.of_node = priv->dev->of_node;
>         meson_encoder_hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
>         meson_encoder_hdmi->bridge.interlace_allowed = true;
> diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c b/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
> index a9145253294fcaef6bae4e1406a781f6d710d357..af58b814e5887f2e231338c1d87feedf4db5e754 100644
> --- a/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
> @@ -878,9 +878,10 @@ static int rcar_lvds_probe(struct platform_device *pdev)
>         struct rcar_lvds *lvds;
>         int ret;
>
> -       lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
> -       if (lvds == NULL)
> -               return -ENOMEM;
> +       lvds = devm_drm_bridge_alloc(&pdev->dev, struct rcar_lvds, bridge,
> +                                    &rcar_lvds_bridge_ops);
> +       if (IS_ERR(lvds))
> +               return PTR_ERR(lvds);
>
>         platform_set_drvdata(pdev, lvds);
>
> @@ -895,7 +896,6 @@ static int rcar_lvds_probe(struct platform_device *pdev)
>         if (ret < 0)
>                 return ret;
>
> -       lvds->bridge.funcs = &rcar_lvds_bridge_ops;
>         lvds->bridge.of_node = pdev->dev.of_node;
>
>         lvds->mmio = devm_platform_ioremap_resource(pdev, 0);
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> index dc6ab012cdb69f92a33da69638aef3fc6fdfa46c..8ba0dde8d48227944263159313e184e581d9cb58 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> @@ -701,9 +701,10 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
>         u32 txsetr;
>         int ret;
>
> -       dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
> -       if (!dsi)
> -               return -ENOMEM;
> +       dsi = devm_drm_bridge_alloc(&pdev->dev, struct rzg2l_mipi_dsi, bridge,
> +                                   &rzg2l_mipi_dsi_bridge_ops);
> +       if (IS_ERR(dsi))
> +               return PTR_ERR(dsi);
>
>         platform_set_drvdata(pdev, dsi);
>         dsi->dev = &pdev->dev;
> @@ -761,7 +762,6 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
>         pm_runtime_put(dsi->dev);
>
>         /* Initialize the DRM bridge. */
> -       dsi->bridge.funcs = &rzg2l_mipi_dsi_bridge_ops;
>         dsi->bridge.of_node = dsi->dev->of_node;
>
>         /* Init host device */
>
> --
> 2.49.0
>


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From ck.hu at mediatek.com  Sun May 25 19:13:13 2025
From: ck.hu at mediatek.com (=?utf-8?B?Q0sgSHUgKOiDoeS/iuWFiSk=?=)
Date: Mon, 26 May 2025 02:13:13 +0000
Subject: [PATCH v1 03/10] uapi: linux: Add MediaTek Imgsys user API
In-Reply-To: <20250524115144.3832748-4-olivia.wen@mediatek.com>
References: <20250524115144.3832748-1-olivia.wen@mediatek.com>
	 <20250524115144.3832748-4-olivia.wen@mediatek.com>
Message-ID: <67e956df4cc0b2b9609e5f9366aff9b42bffc75e.camel@mediatek.com>

On Sat, 2025-05-24 at 19:49 +0800, Olivia Wen wrote:
> Add controls and formats for MediaTek Imgsys processing
> 
> Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
> ---
>  include/uapi/linux/mtkisp_imgsys.h | 215 +++++++++++++++++++++++++++++
>  1 file changed, 215 insertions(+)
>  create mode 100644 include/uapi/linux/mtkisp_imgsys.h
> 
> diff --git a/include/uapi/linux/mtkisp_imgsys.h b/include/uapi/linux/mtkisp_imgsys.h
> new file mode 100644
> index 000000000000..c7528c8bf4a2
> --- /dev/null
> +++ b/include/uapi/linux/mtkisp_imgsys.h
> @@ -0,0 +1,215 @@
> +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
> +/*
> + * MediaTek ISP imgsys User space API
> + *
> + * Copyright (c) 2024 MediaTek Inc.
> + */
> +
> +#ifndef _MTKISP_IMGSYS_USER_H
> +#define _MTKISP_IMGSYS_USER_H
> +
> +#include <linux/v4l2-controls.h>
> +
> +/******************************************************/
> +/*            MediaTek ISP imgsys controls            */
> +/******************************************************/
> +
> +/* The base for the MediaTek imgsys driver controls */
> +/* We reserve 48 controls for this driver. */
> +#define V4L2_CID_USER_MTK_IMG_BASE		(V4L2_CID_USER_BASE + 0x1100)
> +
> +/**
> + * Define a control identifier, V4L2_CID_MTK_IMG_RESIZE_RATIO, for setting the
> + * image processing resize ratio for MediaTek chip. This identifier allows
> + * adjustment of the image resize ratio to accommodate various display or
> + * processing needs. ImgSys hardware supports multiple resizers, including
> + * any ratio, downscaling by factors of 2, 4, and 42, with NULL indicating
> + * the end of menu options.
> + */
> +#define V4L2_CID_MTK_IMG_RESIZE_RATIO	(V4L2_CID_USER_MTK_IMG_BASE + 34)
> +
> +/******************************************************/
> +/*       Vendor specific - MediaTek ISP formats       */
> +/******************************************************/
> +
> +/* MediaTek warp map 32-bit, 2 plane */
> +#define V4L2_PIX_FMT_WARP2P      v4l2_fourcc('M', 'W', '2', 'P')
> +/* YUV-10bit packed 4:2:0 2plane, (Y)(UV)  */

Pixel format should define in include/uapi/linux/videodev2.h
Add document to describe the detail of V4L2_PIX_FMT_WARP2P. [1] is the example document for V4L2_META_FMT_RPI_FE_CFG.
There are many document in Documentation/userspace-api/media/v4l/ for your reference.

[1] https://patchwork.kernel.org/project/linux-media/patch/20241003-rp1-cfe-v6-1-d6762edd98a8 at ideasonboard.com/

> +#define V4L2_PIX_FMT_YUV_2P010P    v4l2_fourcc('U', '0', '2', 'A')
> +/* YUV-12bit packed 4:2:0 2plane, (Y)(UV)  */

Ditto.

> +#define V4L2_PIX_FMT_YUV_2P012P    v4l2_fourcc('U', '0', '2', 'C')
> +/* Y-32bit */

Ditto.

> +#define V4L2_PIX_FMT_MTISP_Y32   v4l2_fourcc('M', 'T', '3', '2')
> +/* Y-16bit */

Ditto.

> +#define V4L2_PIX_FMT_MTISP_Y16   v4l2_fourcc('M', 'T', '1', '6')
> +/* Y-8bit */

Ditto.

> +#define V4L2_PIX_FMT_MTISP_Y8   v4l2_fourcc('M', 'T', '0', '8')
> +
> +/**
> + * Describes the MediaTek APLY8(V4L2_PIX_FMT_MTISP_APLY8) format, which includes
> + * Y-8bit image data and appends APL(Average Pixel Level) data utilized by the
> + * ME(motion estimation) hardware to the end of the image.
> + *
> + * The hardware ME generates motion vectors by processing two consecutive frames,
> + * referred to as the previous and current frames, to enhance graphic processing.
> + * The diagram is shown below.
> + *
> + *                                     +------------------+
> + *  the thumbnail of previous frame -> |                  |
> + *  (include the L0 frame and L1 frame)|                  |
> + *                                     |        ME        | -> motion vectors
> + *  the thumbnail of current frame  -> |                  |
> + *  (include the L0 frame and L1 frame)|                  |
> + *                                     +------------------+
> + *
> + * To accelerate computation, the two images will be resized into two different
> + * smaller images, referred to as L0 frame, L1 frame and APL data.
> + * The L1 frame is a scaled-down version of the L0 frame, reduced to one-fourth
> + * of its original size containing APL data.
> + *
> + *                                     +------------------+
> + *                previous L0 frame -> |                  |
> + *                previous L1 frame -> |                  |
> + *                (include APL data)   |                  |
> + *                                     |        ME        | -> motion vectors
> + *                current L0 frame  -> |                  |
> + *                current L1 frame  -> |                  |
> + *                (include APL data)   |                  |
> + *                                     +------------------+
> + *
> + * Each frame size:
> + *    the width of L0 frame (L0_wd) = 576 (fixed value)
> + *    the height of L0 frame (L0_ht) =
> + *    16 pixels align((the width of original image * L0_wd) / the height of original image)
> + *    the width of L1 frame (L1_wd) = L0_wd / 4
> + *    the height of L1 frame (L1_ht) = L0_ht / 4
> + *
> + * Buffer size:
> + *    line_size = width * bytes_per_pixel(1)
> + *    stride with 16 bytes alignment = ((line_size + 15) / 16) * 16
> + *    buffer_size = stride with 16 bytes alignment * height + APL data(16 bytes)
> + *
> + * And the memory layout should be followed as
> + *
> + *  @code
> + *           APLY8
> + *    +------------------+
> + *    |     Y Plane      |
> + *    |    Bit Stream    |
> + *    +------------------+
> + *    |      APL data    |
> + *    +------------------+
> + *  @endcode
> + *
> + *  @note The APL data size is 16 bytes.The caller SHOULD NOT modify it.
> + */
> +/* Y-8bit image data and append the APL data */
> +#define V4L2_PIX_FMT_MTISP_APLY8   v4l2_fourcc('M', 'T', 'A', '8')

Ditto.

> +
> +/*  Packed 10-bit  */
> +#define V4L2_PIX_FMT_MTISP_SBGGR10  v4l2_fourcc('M', 'B', 'B', 'A')
> +#define V4L2_PIX_FMT_MTISP_SGBRG10  v4l2_fourcc('M', 'B', 'G', 'A')
> +#define V4L2_PIX_FMT_MTISP_SGRBG10  v4l2_fourcc('M', 'B', 'g', 'A')
> +#define V4L2_PIX_FMT_MTISP_SRGGB10  v4l2_fourcc('M', 'B', 'R', 'A')

Ditto.

> +
> +/* Vendor specific - MediaTek ISP parameters for firmware */
> +/* ISP tuning parameters */
> +#define V4L2_META_FMT_MTISP_TUN_PARAMS  v4l2_fourcc('M', 'T', 'f', 't')
> +/* ISP statistics parameters */
> +#define V4L2_META_FMT_MTISP_STAT_PARAMS v4l2_fourcc('M', 'T', 'f', 's')
> +/* ISP controlling parameters */
> +#define V4L2_META_FMT_MTISP_CTL_PARAMS  v4l2_fourcc('M', 'T', 'f', 'c')

Ditto.

> +
> +/*****************************************************************************/
> +/* Define sizes for various formats used in the MediaTek image system driver */
> +/*****************************************************************************/
> +/**
> + * SIZE_OF_APL_DATA - Size of the APL (Average Pixel Level) data
> + *
> + * This constant defines the size of the APL data, which is 16 bytes.
> + * The APL data is appended to the image format defined by
> + * V4L2_PIX_FMT_MTISP_APLY8. This format includes 8-bit Y image data
> + * followed by the APL data, which is utilized by the motion estimation
> + * hardware for enhanced processing. The APL data provides important
> + * information about the average pixel levels, which can be critical
> + * for various image processing tasks.
> + */
> +#define SIZE_OF_APL_DATA 16 /* Size of APL data used by V4L2_PIX_FMT_MTISP_APLY8 */
> +
> +/**
> + * MediaTek Tuning Metadata Buffer for Image Processing Modules
> + *
> + * This definition is used for format V4L2_META_FMT_MTISP_TUN_PARAMS.
> + * This buffer contains essential tuning information for the MediaTek camera,
> + * including:
> + * - Sensor tuning settings

Ditto.

> + * - Digital gain for adjusting image brightness

Ditto.

> + * - White balance gain

Ditto.

> + *
> + * Note: The individual fields of the tuning metadata structure are not exposed
> + * to the kernel. The kernel only requires the size of the tuning metadata
> + * for memory allocation and management purposes. This encapsulation provides
> + * flexibility in implementing the tuning metadata without impacting the
> + * kernel's interface.
> + */
> + #define SIZE_OF_TUNING_META 219352
> +
> +/**
> + * MediaTek Control Metadata Buffer for Image Processing Modules
> + *
> + * This definition is used for format V4L2_META_FMT_MTISP_CTL_PARAMS.
> + * The control metadata buffer aggregates control information for multiple
> + * image processing modules, including TRAW, DIP, PQDIP, ME, WPE, and ADL.
> + * It facilitates the configuration and management of these modules by
> + * encapsulating relevant parameters and settings required for processing
> + * image data efficiently. This structure serves as a central point for
> + * coordinating the operation of different hardware components in the image
> + * processing pipeline.
> + *
> + * Note: The individual fields of the control metadata structure are not exposed
> + * to the kernel. The kernel only requires the size of the control metadata
> + * for memory allocation and management purposes. This encapsulation provides
> + * flexibility in implementing the control metadata without impacting the
> + * kernel's interface.

How user space to generate these control meta data?
Add document about how generating these control meta data.

> + */
> +#define SIZE_OF_COMMON_CTRL       688
> +#define SIZE_OF_WPE_CTRL          240
> +#define SIZE_OF_TRAW_CTRL         120
> +#define SIZE_OF_DIP_CTRL          112
> +#define SIZE_OF_PQDIP_CTRL        112
> +#define SIZE_OF_ME_CTRL           8
> +#define SIZE_OF_ADL_CTRL          64
> +#define SIZE_OF_YUFO_META_INFO_WPE 4228
> +#define SIZE_OF_YUFO_META_INFO_DIP 4228
> +
> +#define SIZE_OF_CTRL_META ( \
> +	SIZE_OF_COMMON_CTRL + \
> +	SIZE_OF_WPE_CTRL + \
> +	SIZE_OF_TRAW_CTRL + \
> +	SIZE_OF_DIP_CTRL + \
> +	SIZE_OF_PQDIP_CTRL + \
> +	SIZE_OF_ME_CTRL + \
> +	SIZE_OF_ADL_CTRL + \
> +	SIZE_OF_YUFO_META_INFO_WPE + \
> +	SIZE_OF_YUFO_META_INFO_DIP \
> +)
> +
> +/**
> + * MediaTek Statistics Metadata Buffer for Image Processing Modules
> + *
> + * This definition is used for format V4L2_META_FMT_MTISP_STAT_PARAMS.
> + * This buffer contains essential statistics information for the MediaTek camera,
> + * including:
> + * - Readiness and corresponding values for tone and contrast statistics
> + * - Motion estimation (ME) statistics
> + * - ME feature match blocks statistics
> + *
> + * Note: The individual fields of the statistics buffer structure are not exposed
> + * to the kernel. The kernel only requires the size of the statistics metadata
> + * for memory allocation and management purposes. This encapsulation provides
> + * flexibility in implementing the statistics metadata without impacting the
> + * kernel's interface.

How user space to generate these statistics meta data?
Add document about how generating these statistics meta data.

Regards,
CK

> + */
> + #define SIZE_OF_STATISTICS_META 88
> +
> +#endif /* _MTKISP_IMGSYS_USER_H */


From Jason-JH.Lin at mediatek.com  Sun May 25 20:23:07 2025
From: Jason-JH.Lin at mediatek.com (=?utf-8?B?SmFzb24tSkggTGluICjmnpfnnb/npaUp?=)
Date: Mon, 26 May 2025 03:23:07 +0000
Subject: [PATCH] drm/mediatek: Add wait_event_timeout when disabling plane
In-Reply-To: <CAPj87rNV_48pQF+gv3HEx+-n1WvKOoX2u_HRW5w8DrgEAigk9w@mail.gmail.com>
References: <20250522085149.3361598-1-jason-jh.lin@mediatek.com>
	 <CAPj87rNV_48pQF+gv3HEx+-n1WvKOoX2u_HRW5w8DrgEAigk9w@mail.gmail.com>
Message-ID: <90827603384e6cb15d798630cd7c6f3d5fc4d205.camel@mediatek.com>

Hi Daniel,

Thanks for the review.

On Sat, 2025-05-24 at 13:47 +0100, Daniel Stone wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Hi Jason,
> 
> On Thu, 22 May 2025 at 09:52, Jason-JH Lin
> <jason-jh.lin at mediatek.com> wrote:
> > Our hardware registers are set through GCE, not by the CPU.
> > DRM might assume the hardware is disabled immediately after calling
> > atomic_disable() of drm_plane, but it is only truly disabled after
> > the
> > GCE IRQ is triggered.
> > 
> > Additionally, the cursor plane in DRM uses async_commit, so DRM
> > will
> > not wait for vblank and will free the buffer immediately after
> > calling
> > atomic_disable().
> > 
> > To prevent the framebuffer from being freed before the layer
> > disable
> > settings are configured into the hardware, which can cause an IOMMU
> > fault error, a wait_event_timeout has been added to wait for the
> > ddp_cmdq_cb() callback,indicating that the GCE IRQ has been
> > triggered.
> 
> Waiting up to 500ms for each plane to be disabled is ... not ideal.

It a timeout it won't really wait up to 500ms. I can shrink the timeout
to 1 VSYNC because it must be less than 16.666ms (depend on encoder's
timing).
But it's enough to free the framebuffer at this moment.

> Especially as multiple planes can be disabled at once. This may
> happen
> dynamically during runtime, e.g. when a video is playing and a user
> moves their cursor over the plane to make the UI controls visible.

The video layer will be disabled or video layer and UI layer will be
swapped by the atomic_comit() with drm_pending_vblank_event in this
case.

> 
> I think this should be handled through the atomic_commit() handler,
> with asynchronous tracking of the state, instead of the hard block
> here.

In my case, I encounter the UI process is killed and all the
framebuffer are set to NULL to each plane.

The log is shown as below:

// After the process is killed
// framebuffer(0xf9c00000) of UI layer0 will be freed after ddp_cmdq_cb

[   55.996903] mtk_plane_atomic_disable 296: idx:0, addr=0xf9c00000
[   55.996923] mtk_crtc_update_config 980: needs_vblank=1
[   56.001300] mtk_gem_free_object 110: dma_va = 00000000b49ad5c8,
dma_iova = 0x00000000fb980000, size = 262144
[   56.001538] ddp_cmdq_cb 533: need_vblank:1, sta:0
[   56.017297] mtk_gem_free_object 110: dma_va = 000000003f29e25b,
dma_iova = 0x00000000fb000000, size = 9216000
[   56.017553] mtk_gem_free_object 110: dma_va = 000000000fb130cb,
dma_iova = 0x00000000fa600000, size = 9216000
[   56.017750] mtk_gem_free_object 110: dma_va = 00000000f786f524,
dma_iova = 0x00000000f9c00000, size = 9216000

...

// framebuffer(0xfb9c0000) of cursor layer3 will be freed before
ddp_cmdq_cb

[   62.851250] mtk_plane_atomic_disable 296: idx:3, addr=0xfb9c0000
[   62.851263] mtk_crtc_update_config 980: needs_vblank=0
[   62.851273] mtk_gem_free_object 110: dma_va = 00000000716d147d,
dma_iova = 0x00000000fb9c0000, size = 262144
[   62.851442] arm-smmu-v3 30800000.iommu: TBU_id-0-
fault_id:0x40c(0x40c), TF read in NORMAL world, iova:0xfb9c5000, 
sid:144, ssid:0, ssidv:0, secsidv:0
[   62.851453] arm-smmu-v3 30800000.iommu: event 0x10 received:
[   62.851457] arm-smmu-v3 30800000.iommu:      0x0000009000000010
[   62.851461] arm-smmu-v3 30800000.iommu:      0x0000020800000000
[   62.851464] arm-smmu-v3 30800000.iommu:      0x00000000fb9c5000
[   62.851467] arm-smmu-v3 30800000.iommu:      0x0000000000000000
...
[   62.854666] ddp_cmdq_cb 533: need_vblank:1, sta:-103
[   62.854691] mtk_crtc_update_config 980: needs_vblank=1
[   62.867886] ddp_cmdq_cb 533: need_vblank:1, sta:0

---

After applying this path:

// framebuffer(0xfb9c0000) of cursor layer3 will be freed after
ddp_cmdq_cb
[ 1106.422478] mtk_plane_atomic_disable 296: idx:3, addr=0xfb9c0000
[ 1106.422487] ddp_cmdq_cb 533: need_vblank:0, sta:-103
[ 1106.422508] mtk_crtc_update_config 980: needs_vblank=0
[ 1106.434976] ddp_cmdq_cb 533: need_vblank:0, sta:0
[ 1106.435027] mtk_plane_atomic_disable 308: idx:3 done!
[ 1106.435052] mtk_crtc_update_config 980: needs_vblank=0
[ 1106.435077] mtk_gem_free_object 110: dma_va = 0000000075285c43,
dma_iova = 0x00000000fb9c0000, size = 262144

---

We have already tracking the async state for cursor layer3 in
atomic_commit(), but it seems its framebuffer will still be freed
before ddp_cmdq_cb.

Do you have any ideal rather than adding a hard block in
mtk_plane_atomic_disable()?

Regards,
Jason-JH Lin

> 
> Cheers,
> Daniel


From jianhua.lin at mediatek.com  Sun May 25 23:30:44 2025
From: jianhua.lin at mediatek.com (Jianhua Lin)
Date: Mon, 26 May 2025 14:30:44 +0800
Subject: [PATCH v2 1/1] media: mediatek: jpeg: add compatible for MT8188 SoC
Message-ID: <20250526063044.1513-1-jianhua.lin@mediatek.com>

Add jpeg decoder and encoder compatible for MediaTek MT8188 SoC,
and enable support_34bit.

Signed-off-by: Jianhua Lin <jianhua.lin at mediatek.com>
---
Changes compared with v1:
- Update the dependent commit information only.

This patch depends on the following commit:
[1]
Commit: https://git.linuxtv.org/media.git/commit/?id=7560349ee0d9441642da6d38c3822d08fffdd2fb
Title: [PATCH] media: mediatek: jpeg: support 34bits

The above commit introduces a new variable 'support_34bit', that is required 
for enable 34-bit iova support in this patch. Without the changes in this commit,
it will not work and cause compile error.

 .../platform/mediatek/jpeg/mtk_jpeg_core.c    | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 23692cd91e2c..0ed1c352bc0f 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1869,6 +1869,10 @@ static struct clk_bulk_data mtk_jpeg_clocks[] = {
 	{ .id = "jpgenc" },
 };
 
+static struct clk_bulk_data mtk_jpeg_dec_clocks[] = {
+	{ .id = "jpgdec" },
+};
+
 static struct clk_bulk_data mt8173_jpeg_dec_clocks[] = {
 	{ .id = "jpgdec-smi" },
 	{ .id = "jpgdec" },
@@ -1931,6 +1935,38 @@ static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata = {
 	.jpeg_worker = mtk_jpegdec_worker,
 };
 
+static const struct mtk_jpeg_variant mtk8188_jpegenc_drvdata = {
+	.clks = mtk_jpeg_clocks,
+	.num_clks = ARRAY_SIZE(mtk_jpeg_clocks),
+	.formats = mtk_jpeg_enc_formats,
+	.num_formats = MTK_JPEG_ENC_NUM_FORMATS,
+	.qops = &mtk_jpeg_enc_qops,
+	.irq_handler = mtk_jpeg_enc_irq,
+	.hw_reset = mtk_jpeg_enc_reset,
+	.m2m_ops = &mtk_jpeg_enc_m2m_ops,
+	.dev_name = "mtk-jpeg-enc",
+	.ioctl_ops = &mtk_jpeg_enc_ioctl_ops,
+	.out_q_default_fourcc = V4L2_PIX_FMT_YUYV,
+	.cap_q_default_fourcc = V4L2_PIX_FMT_JPEG,
+	.support_34bit = true,
+};
+
+static const struct mtk_jpeg_variant mtk8188_jpegdec_drvdata = {
+	.clks = mtk_jpeg_dec_clocks,
+	.num_clks = ARRAY_SIZE(mtk_jpeg_dec_clocks),
+	.formats = mtk_jpeg_dec_formats,
+	.num_formats = MTK_JPEG_DEC_NUM_FORMATS,
+	.qops = &mtk_jpeg_dec_qops,
+	.irq_handler = mtk_jpeg_dec_irq,
+	.hw_reset = mtk_jpeg_dec_reset,
+	.m2m_ops = &mtk_jpeg_dec_m2m_ops,
+	.dev_name = "mtk-jpeg-dec",
+	.ioctl_ops = &mtk_jpeg_dec_ioctl_ops,
+	.out_q_default_fourcc = V4L2_PIX_FMT_JPEG,
+	.cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M,
+	.support_34bit = true,
+};
+
 static const struct of_device_id mtk_jpeg_match[] = {
 	{
 		.compatible = "mediatek,mt8173-jpgdec",
@@ -1952,6 +1988,14 @@ static const struct of_device_id mtk_jpeg_match[] = {
 		.compatible = "mediatek,mt8195-jpgdec",
 		.data = &mtk8195_jpegdec_drvdata,
 	},
+	{
+		.compatible = "mediatek,mt8188-jpgenc",
+		.data = &mtk8188_jpegenc_drvdata,
+	},
+	{
+		.compatible = "mediatek,mt8188-jpgdec",
+		.data = &mtk8188_jpegdec_drvdata,
+	},
 	{},
 };
 
-- 
2.46.0



From ck.hu at mediatek.com  Mon May 26 00:16:45 2025
From: ck.hu at mediatek.com (=?utf-8?B?Q0sgSHUgKOiDoeS/iuWFiSk=?=)
Date: Mon, 26 May 2025 07:16:45 +0000
Subject: [PATCH v1 04/10] media: mediatek: isp: Add V4L2 flow support for
 ImgSys driver
In-Reply-To: <20250524115144.3832748-5-olivia.wen@mediatek.com>
References: <20250524115144.3832748-1-olivia.wen@mediatek.com>
	 <20250524115144.3832748-5-olivia.wen@mediatek.com>
Message-ID: <07ce826311b73276bc30d29c141b24223319c932.camel@mediatek.com>

On Sat, 2025-05-24 at 19:49 +0800, Olivia Wen wrote:
> The ImgSys driver is implemented as a series of patches, with this patch
> focusing on the V4L2 flow. The MediaTek's Image System (ImgSys), also
> known as ISP Pass2. ImgSys is a memory-to-memory hardware device
> designed for advanced image processing tasks. It is composed of multiple
> hardware components, including TRAW, DIP, PQDIP, ME, and WPE.
> 
> TRAW (Tile RAW):
> - Provides multiple downscaled resizers to support multi-scale noise
>   reduction.
> - Supports RAW/RGB format conversion.
> 
> DIP (Digital Image Processing) and PQDIP (Picture Quality DIP):
> - Supports such as temporal and spatial noise reduction (TNR/SNR),
>   edge enhancement (EE), and sharpness (SHP).
> - PQDIP also supports image scaling and rotation.
> 
> ME (Motion Estimation):
> - Supports motion estimation between two consecutive frames.
> 
> WPE (Warping Engine):
> - Handles image warping and de-warping processes.
> 
> The ImgSys driver, primarily utilized for Google Chromebook products,
> uses Multi-Frame Combined Noise Reduction technology to enhance image
> quality.
> 
> Below is a simplified architecture of the ImgSys driver:
> User -> V4L2 Framework -> ImgSys Driver
>      -> SCP (It packages the hardware settings into commands)
>      -> ImgSys Driver
>      -> CMDQ (The packaged commands are sent to the hardware via GCE)
>      -> Hardware

You break this driver into multiple patches by these function block,
but this would make reviewer (include me) hard to review.
The better way is

1. Add imgsys driver with basic function (include v4l2 framework, scp, cmdq. The basic function may be downscale and format convert only)
2. Add DIP function
3. Add ME function
4. Add WPE function

Let the first patch as simple as possible but it should work.

> 
> Signed-off-by: Olivia Wen <olivia.wen at mediatek.com>
> ---
>  drivers/media/platform/mediatek/Kconfig       |    1 +
>  drivers/media/platform/mediatek/Makefile      |    1 +
>  drivers/media/platform/mediatek/isp/Kconfig   |   23 +
>  .../platform/mediatek/isp/isp_7x/Makefile     |    6 +
>  .../mediatek/isp/isp_7x/imgsys/Makefile       |   11 +
>  .../imgsys/modules/mtk_dip_v4l2_vnode.h       |  594 ++++++
>  .../isp_7x/imgsys/modules/mtk_me_v4l2_vnode.h |  386 ++++
>  .../imgsys/modules/mtk_pqdip_v4l2_vnode.h     |  149 ++
>  .../imgsys/modules/mtk_traw_v4l2_vnode.h      |  371 ++++
>  .../imgsys/modules/mtk_wpe_v4l2_vnode.h       |  317 ++++
>  .../isp/isp_7x/imgsys/mtk_header_desc.h       |   28 +
>  .../isp/isp_7x/imgsys/mtk_imgsys-dev.c        |  238 +++
>  .../isp/isp_7x/imgsys/mtk_imgsys-dev.h        |  427 +++++
>  .../isp/isp_7x/imgsys/mtk_imgsys-formats.c    |  139 ++
>  .../isp/isp_7x/imgsys/mtk_imgsys-formats.h    |   72 +
>  .../isp/isp_7x/imgsys/mtk_imgsys-module_ops.h |   27 +
>  .../isp/isp_7x/imgsys/mtk_imgsys-of.c         |   39 +
>  .../isp/isp_7x/imgsys/mtk_imgsys-of.h         |   55 +
>  .../isp/isp_7x/imgsys/mtk_imgsys-sys.c        |   27 +
>  .../isp/isp_7x/imgsys/mtk_imgsys-sys.h        |   50 +
>  .../isp/isp_7x/imgsys/mtk_imgsys-v4l2.c       | 1684 +++++++++++++++++
>  .../isp/isp_7x/imgsys/mtk_imgsys-vnode_id.h   |  100 +
>  .../isp/isp_7x/imgsys/mtk_imgsys_v4l2_vnode.h |  135 ++
>  23 files changed, 4880 insertions(+)
>  create mode 100644 drivers/media/platform/mediatek/isp/Kconfig
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/Makefile
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/Makefile
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_dip_v4l2_vnode.h
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_me_v4l2_vnode.h
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_pqdip_v4l2_vnode.h
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_traw_v4l2_vnode.h
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/modules/mtk_wpe_v4l2_vnode.h
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_header_desc.h
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.c
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-dev.h
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-formats.c
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-formats.h
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-module_ops.h
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.c
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-of.h
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.c
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-sys.h
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-v4l2.c
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys-vnode_id.h
>  create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/imgsys/mtk_imgsys_v4l2_vnode.h

Place these files in drivers/media/platform/mediatek/imgsys.
This is the first SoC which support imgsys driver so it's not necessary to use so deep folder structure.

Regards,
CK



From luca.ceresoli at bootlin.com  Mon May 26 00:20:24 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Mon, 26 May 2025 09:20:24 +0200
Subject: [PATCH v2 30/34] drm/bridge: imx8qxp-pixel-combiner: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <67252c36-8b31-4c40-9d89-4f502da4a087@nxp.com>
References: <20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b@bootlin.com>
 <20250424-drm-bridge-convert-to-alloc-api-v2-30-8f91a404d86b@bootlin.com>
 <553d62ed-976a-4e17-9678-cdc3d40ce4a7@nxp.com>
 <20250430112944.1b39caab@booty>
 <f71d18d2-4271-4bb9-b54f-0e5a585778f3@nxp.com>
 <20250506224720.5cbcf3e1@booty>
 <67252c36-8b31-4c40-9d89-4f502da4a087@nxp.com>
Message-ID: <20250526092024.48cae4ae@booty>

Hello Liu,

On Thu, 22 May 2025 11:01:13 +0800
Liu Ying <victor.liu at nxp.com> wrote:

> On 05/07/2025, Luca Ceresoli wrote:
> 
> [...]
> 
> >> After looking into this patch and patch 31(though I've already provided my A-b)
> >> more closely, I think the imx8qxp_pc and imx8{qm,qxp}_ldb main structures
> >> should have the same life time with the embedded DRM bridges, because for
> >> example the clk_apb clock in struct imx8qxp_pc would be accessed by the
> >> imx8qxp_pc_bridge_mode_set DRM bridge callback.  But, IIUC, your patches extend
> >> the life time for the embedded channel/bridge structures only, but not for the
> >> main structures.  What do you think ?  
> > 
> > I see you concern, but I'm sure the change I'm introducing is not
> > creating the problem you are concerned about.
> > 
> > The key aspect is that my patch is merely changing the lifetime of the
> > _allocation_ of the drm_bridge, not its usage. On drm_bridge_remove()
> > the bridge is removed from its encoder chain and it is completely not
> > reachable, both before and after my patch. With my patch it is not  
> 
> drm_bridge_remove() only removes a bridge from the global bridge_list defined
> in drm_bridge.c.  drm_bridge_detach() is the one which removes a bridge from
> it's encoder chain.  It looks like you wrongly thought drm_bridge_remove()
> is drm_bridge_detach().

Indeed my sentence was inaccurate, sorry about that.

> So, even if drm_bridge_remove() is called, the removed
> bridge could still be in it's encoder chain, hence an atomic commit could still
> access the allocated bridge(with lifetime extended) and the clock_apb clock
> for example in struct imx8qxp_pc could also be accessed.  That's why I think
> the main structures should have the same lifetime with the allocated bridge.

As the long-term goal is to allow bridges to be hot-removable,
decoupling the lifetime of the various components is a necessary step.
Definitely it will open other issues, and especially the removal during
atomic updates. This has been discussed already, and there is a
proposed plan to handle it.

First, here is the grand plan (mentioned in the v3 cover letter):

 1. ? add refcounting to DRM bridges (struct drm_bridge)
 2. handle gracefully atomic updates during bridge removal
 3. avoid DSI host drivers to have dangling pointers to DSI devices
 4. finally, let bridges be removable (depends on 1+2+3)

We are now at step 1. Your concern, as I understand it, will be
addressed at step 2. Bridges won't be removable until step 4, so the
current changes are not introducing a misbehavior but rather preparing
the ground with all the necessary infrastructure changes.

Step 2 was discussed in the past [0], and the idea proposed by Maxime
is to introduce a "gone" or "unplugged" flag and drm_bridge_enter() /
drm_bridge_exit() functions. The principle is the same as struct
drm_device.unplugged and drm_dev_enter/exit().

In a nutshell the idea is:

 - drm_bridge.unplugged is initialized to false
 - drm_bridge_enter() returns false if drm_bridge.unplugged == true
 - any code holding a pointer to the bridge (including the bridge driver
   itself) and operating on the bridge (including removal) needs to do:
     if (drm_bridge_enter()) {
         do something;
         drm_bridge_exit();
     }
 - when the bridge is removed, the driver removal function sets
   dev_bridge.unplugged = true

The "do something" above includes any access to device resources,
including clocks (and clk_apb).

In other words, two pieces of code can not access the bridge structure
at the same time. This includes bridge removal VS any atomic operations.

Do you think this addresses your concern?


For you to have a better picture of the path, here's an additional
clarification about drm_bridge_attach/detach() and
drm_bridge_add/remove(). As part of step 1 of the grand plan, both of
them will drm_bridge_get/put() the bridge, so that no bridge is freed
if it is either in the global bridge_list or in any encoder chain.

Patches for this are already approved by Maxime [1][2]. They cannot be
applied until all bridge drivers have been converted to the new
devm_drm_bridge_alloc() API, so they depend on this series to be
completely applied. We are getting pretty close: as of now the entire
series has been applied except for this and another driver.

[0] https://lore.kernel.org/all/20250129125153.35d0487a at booty/t/#u
[1] https://patchwork.freedesktop.org/patch/643095/
[2] https://patchwork.freedesktop.org/patch/643096/

Best regards,
Luca

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


From miquel.raynal at bootlin.com  Mon May 26 00:29:16 2025
From: miquel.raynal at bootlin.com (Miquel Raynal)
Date: Mon, 26 May 2025 09:29:16 +0200
Subject: [PATCH] thermal: Constify struct thermal_zone_device_ops
In-Reply-To: <5bba3bf0139e2418b306a0f9a2f1f81ef49e88a6.1748165978.git.christophe.jaillet@wanadoo.fr>
	(Christophe JAILLET's message of "Sun, 25 May 2025 11:40:04 +0200")
References: <5bba3bf0139e2418b306a0f9a2f1f81ef49e88a6.1748165978.git.christophe.jaillet@wanadoo.fr>
Message-ID: <87v7pn3k4z.fsf@bootlin.com>

Hello,

On 25/05/2025 at 11:40:04 +02, Christophe JAILLET <christophe.jaillet at wanadoo.fr> wrote:

> 'struct thermal_zone_device_ops' are not modified in these drivers.
>
> Constifying these structures moves some data to a read-only section, so
> increases overall security, especially when the structure holds some
> function pointers.
>
> On a x86_64, with allmodconfig, as an example:
> Before:
> ======
>    text	   data	    bss	    dec	    hex	filename
>   28116	   5168	    128	  33412	   8284	drivers/thermal/armada_thermal.o
>
> After:
> =====
>    text	   data	    bss	    dec	    hex	filename
>   28244	   5040	    128	  33412	   8284	drivers/thermal/armada_thermal.o
>
> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
> ---
> Compile tested only
> ---
>  drivers/thermal/armada_thermal.c                        | 2 +-

Reviewed-by: Miquel Raynal <miquel.raynal at bootlin.com> # For Armada

Thanks,
Miqu?l


From SkyLake.Huang at mediatek.com  Mon May 26 02:10:19 2025
From: SkyLake.Huang at mediatek.com (Sky Huang)
Date: Mon, 26 May 2025 17:10:19 +0800
Subject: [PATCH net-next] net: phy: mtk-2p5ge: Add LED support for MT7988
Message-ID: <20250526091019.16096-1-SkyLake.Huang@mediatek.com>

From: Sky Huang <skylake.huang at mediatek.com>

Add LED support for MT7988's built-in 2.5Gphy. LED hardware has almost
the same design with MT7981's/MT7988's built-in GbE. So hook the same
helper function here.

Before mtk_phy_leds_state_init(), set correct default values of LED0
and LED1.

Signed-off-by: Sky Huang <skylake.huang at mediatek.com>
Reviewed-by: Andrew Lunn <andrew at lunn.ch>
---
This patch is reviewed already:
https://www.spinics.net/lists/netdev/msg1094289.html
---
 drivers/net/phy/mediatek/mtk-2p5ge.c | 104 +++++++++++++++++++++++++--
 1 file changed, 98 insertions(+), 6 deletions(-)

diff --git a/drivers/net/phy/mediatek/mtk-2p5ge.c b/drivers/net/phy/mediatek/mtk-2p5ge.c
index e147eab52..de8a41a18 100644
--- a/drivers/net/phy/mediatek/mtk-2p5ge.c
+++ b/drivers/net/phy/mediatek/mtk-2p5ge.c
@@ -249,8 +249,80 @@ static int mt798x_2p5ge_phy_get_rate_matching(struct phy_device *phydev,
 	return RATE_MATCH_PAUSE;
 }
 
+static const unsigned long supported_triggers =
+	BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
+	BIT(TRIGGER_NETDEV_LINK)        |
+	BIT(TRIGGER_NETDEV_LINK_10)     |
+	BIT(TRIGGER_NETDEV_LINK_100)    |
+	BIT(TRIGGER_NETDEV_LINK_1000)   |
+	BIT(TRIGGER_NETDEV_LINK_2500)   |
+	BIT(TRIGGER_NETDEV_RX)          |
+	BIT(TRIGGER_NETDEV_TX);
+
+static int mt798x_2p5ge_phy_led_blink_set(struct phy_device *phydev, u8 index,
+					  unsigned long *delay_on,
+					  unsigned long *delay_off)
+{
+	bool blinking = false;
+	int err = 0;
+
+	err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking);
+	if (err < 0)
+		return err;
+
+	err = mtk_phy_hw_led_blink_set(phydev, index, blinking);
+	if (err)
+		return err;
+
+	if (blinking)
+		mtk_phy_hw_led_on_set(phydev, index, MTK_2P5GPHY_LED_ON_MASK,
+				      false);
+
+	return 0;
+}
+
+static int mt798x_2p5ge_phy_led_brightness_set(struct phy_device *phydev,
+					       u8 index,
+					       enum led_brightness value)
+{
+	int err;
+
+	err = mtk_phy_hw_led_blink_set(phydev, index, false);
+	if (err)
+		return err;
+
+	return mtk_phy_hw_led_on_set(phydev, index, MTK_2P5GPHY_LED_ON_MASK,
+				     (value != LED_OFF));
+}
+
+static int mt798x_2p5ge_phy_led_hw_is_supported(struct phy_device *phydev,
+						u8 index, unsigned long rules)
+{
+	return mtk_phy_led_hw_is_supported(phydev, index, rules,
+					   supported_triggers);
+}
+
+static int mt798x_2p5ge_phy_led_hw_control_get(struct phy_device *phydev,
+					       u8 index, unsigned long *rules)
+{
+	return mtk_phy_led_hw_ctrl_get(phydev, index, rules,
+				       MTK_2P5GPHY_LED_ON_SET,
+				       MTK_2P5GPHY_LED_RX_BLINK_SET,
+				       MTK_2P5GPHY_LED_TX_BLINK_SET);
+};
+
+static int mt798x_2p5ge_phy_led_hw_control_set(struct phy_device *phydev,
+					       u8 index, unsigned long rules)
+{
+	return mtk_phy_led_hw_ctrl_set(phydev, index, rules,
+				       MTK_2P5GPHY_LED_ON_SET,
+				       MTK_2P5GPHY_LED_RX_BLINK_SET,
+				       MTK_2P5GPHY_LED_TX_BLINK_SET);
+};
+
 static int mt798x_2p5ge_phy_probe(struct phy_device *phydev)
 {
+	struct mtk_socphy_priv *priv;
 	struct pinctrl *pinctrl;
 	int ret;
 
@@ -273,19 +345,34 @@ static int mt798x_2p5ge_phy_probe(struct phy_device *phydev)
 	if (ret < 0)
 		return ret;
 
-	/* Setup LED */
+	/* Setup LED. On default, LED0 is on/off when link is up/down. As for
+	 * LED1, it blinks as tx/rx transmission takes place.
+	 */
 	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
-			 MTK_PHY_LED_ON_POLARITY | MTK_PHY_LED_ON_LINK10 |
-			 MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK1000 |
-			 MTK_PHY_LED_ON_LINK2500);
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
-			 MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX);
+			 MTK_PHY_LED_ON_POLARITY | MTK_2P5GPHY_LED_ON_SET);
+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL,
+			   MTK_2P5GPHY_LED_TX_BLINK_SET |
+			   MTK_2P5GPHY_LED_RX_BLINK_SET);
+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
+			   MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX |
+			   MTK_2P5GPHY_LED_ON_SET);
+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL,
+			 MTK_2P5GPHY_LED_TX_BLINK_SET |
+			 MTK_2P5GPHY_LED_RX_BLINK_SET);
 
 	/* Switch pinctrl after setting polarity to avoid bogus blinking */
 	pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
 	if (IS_ERR(pinctrl))
 		dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
 
+	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv),
+			    GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	phydev->priv = priv;
+
+	mtk_phy_leds_state_init(phydev);
+
 	return 0;
 }
 
@@ -303,6 +390,11 @@ static struct phy_driver mtk_2p5gephy_driver[] = {
 		.resume = genphy_resume,
 		.read_page = mtk_phy_read_page,
 		.write_page = mtk_phy_write_page,
+		.led_blink_set = mt798x_2p5ge_phy_led_blink_set,
+		.led_brightness_set = mt798x_2p5ge_phy_led_brightness_set,
+		.led_hw_is_supported = mt798x_2p5ge_phy_led_hw_is_supported,
+		.led_hw_control_get = mt798x_2p5ge_phy_led_hw_control_get,
+		.led_hw_control_set = mt798x_2p5ge_phy_led_hw_control_set,
 	},
 };
 
-- 
2.45.2



From jianhua.lin at mediatek.com  Mon May 26 02:17:34 2025
From: jianhua.lin at mediatek.com (Jianhua Lin)
Date: Mon, 26 May 2025 17:17:34 +0800
Subject: No subject
Message-ID: <20250526091734.4591-1-jianhua.lin@mediatek.com>

From: Jianhua Lin <jianhua.lin at mediatek.com>
Date: Thu, 17 Apr 2025 11:28:00 +0800
Subject: [PATCH v2 1/1] media: mediatek: jpeg: fix buffer alignment

The JPEG encoder image stride register must be MCU aligned.
For YUV422, it's 32-byte aligned, and for YUV420, it's
16-byte aligned.

The minimal DCT block size is 8x8, so the vertical buffer
alignment for YUV422 is 8-byte aligned, and for YUV420,
it's 16-byte aligned.

Signed-off-by: Jianhua Lin <jianhua.lin at mediatek.com>
---
Changes compared with v1:
- Fix the side effects of v1
  when encoding YUV420 with resolution 720x480, the ouput image is abnormal.
- Fix signed-off-by

 .../platform/mediatek/jpeg/mtk_jpeg_core.c    | 44 ++++++++++++-------
 1 file changed, 29 insertions(+), 15 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 834d2a354692..f01a81feb692 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -40,8 +40,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_enc_formats[] = {
 		.h_sample	= {4, 4},
 		.v_sample	= {4, 2},
 		.colplanes	= 2,
-		.h_align	= 4,
-		.v_align	= 4,
+		.h_align	= 16,
+		.v_align	= 16,
 		.flags		= MTK_JPEG_FMT_FLAG_OUTPUT,
 	},
 	{
@@ -50,8 +50,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_enc_formats[] = {
 		.h_sample	= {4, 4},
 		.v_sample	= {4, 2},
 		.colplanes	= 2,
-		.h_align	= 4,
-		.v_align	= 4,
+		.h_align	= 16,
+		.v_align	= 16,
 		.flags		= MTK_JPEG_FMT_FLAG_OUTPUT,
 	},
 	{
@@ -60,8 +60,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_enc_formats[] = {
 		.h_sample	= {8},
 		.v_sample	= {4},
 		.colplanes	= 1,
-		.h_align	= 5,
-		.v_align	= 3,
+		.h_align	= 32,
+		.v_align	= 8,
 		.flags		= MTK_JPEG_FMT_FLAG_OUTPUT,
 	},
 	{
@@ -70,8 +70,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_enc_formats[] = {
 		.h_sample	= {8},
 		.v_sample	= {4},
 		.colplanes	= 1,
-		.h_align	= 5,
-		.v_align	= 3,
+		.h_align	= 32,
+		.v_align	= 8,
 		.flags		= MTK_JPEG_FMT_FLAG_OUTPUT,
 	},
 };
@@ -87,8 +87,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_dec_formats[] = {
 		.h_sample	= {4, 2, 2},
 		.v_sample	= {4, 2, 2},
 		.colplanes	= 3,
-		.h_align	= 5,
-		.v_align	= 4,
+		.h_align	= 16,
+		.v_align	= 16,
 		.flags		= MTK_JPEG_FMT_FLAG_CAPTURE,
 	},
 	{
@@ -96,8 +96,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_dec_formats[] = {
 		.h_sample	= {4, 2, 2},
 		.v_sample	= {4, 4, 4},
 		.colplanes	= 3,
-		.h_align	= 5,
-		.v_align	= 3,
+		.h_align	= 32,
+		.v_align	= 8,
 		.flags		= MTK_JPEG_FMT_FLAG_CAPTURE,
 	},
 };
@@ -260,6 +260,7 @@ static int mtk_jpeg_try_fmt_mplane(struct v4l2_pix_format_mplane *pix_mp,
 				   struct mtk_jpeg_fmt *fmt)
 {
 	int i;
+	u32 h_align;
 
 	pix_mp->field = V4L2_FIELD_NONE;
 
@@ -283,9 +284,15 @@ static int mtk_jpeg_try_fmt_mplane(struct v4l2_pix_format_mplane *pix_mp,
 	}
 
 	/* other fourcc */
+	if (pix_mp->pixelformat == V4L2_PIX_FMT_YUYV ||
+	    pix_mp->pixelformat == V4L2_PIX_FMT_YVYU)
+		h_align = fmt->h_align / 2;
+	else
+		h_align = fmt->h_align;
+
 	pix_mp->height = clamp(round_up(pix_mp->height, fmt->v_align),
 			       MTK_JPEG_MIN_HEIGHT, MTK_JPEG_MAX_HEIGHT);
-	pix_mp->width = clamp(round_up(pix_mp->width, fmt->h_align),
+	pix_mp->width = clamp(round_up(pix_mp->width, h_align),
 			      MTK_JPEG_MIN_WIDTH, MTK_JPEG_MAX_WIDTH);
 
 	for (i = 0; i < fmt->colplanes; i++) {
@@ -293,8 +300,15 @@ static int mtk_jpeg_try_fmt_mplane(struct v4l2_pix_format_mplane *pix_mp,
 		u32 stride = pix_mp->width * fmt->h_sample[i] / 4;
 		u32 h = pix_mp->height * fmt->v_sample[i] / 4;
 
-		pfmt->bytesperline = stride;
-		pfmt->sizeimage = stride * h;
+		if (pix_mp->pixelformat == V4L2_PIX_FMT_YUYV ||
+		    pix_mp->pixelformat == V4L2_PIX_FMT_YVYU) {
+			stride = round_up(stride, fmt->h_align);
+			pfmt->bytesperline = stride;
+			pfmt->sizeimage = stride * h;
+		} else {
+			pfmt->bytesperline = stride;
+			pfmt->sizeimage = stride * h;
+		}
 	}
 	return 0;
 }
-- 
2.46.0



From jianhua.lin at mediatek.com  Mon May 26 02:31:09 2025
From: jianhua.lin at mediatek.com (Jianhua Lin)
Date: Mon, 26 May 2025 17:31:09 +0800
Subject: No subject
Message-ID: <20250526093109.4681-1-jianhua.lin@mediatek.com>

From: Jianhua Lin <jianhua.lin at mediatek.com>
Date: Thu, 17 Apr 2025 11:28:00 +0800
Subject: [PATCH v3 1/1] media: mediatek: jpeg: fix buffer alignment

The JPEG encoder image stride register must be MCU aligned.
For YUV422, it's 32-byte aligned, and for YUV420, it's
16-byte aligned.

The minimal DCT block size is 8x8, so the vertical buffer
alignment for YUV422 is 8-byte aligned, and for YUV420,
it's 16-byte aligned.

Signed-off-by: Jianhua Lin <jianhua.lin at mediatek.com>
---
Changes compared with v2:
- Add missing subject

Changes compared with v1:
- Fix the side effects of v1
  when encoding YUV420 with resolution 720x480, the ouput image is abnormal.
- Fix signed-off-by

 .../platform/mediatek/jpeg/mtk_jpeg_core.c    | 44 ++++++++++++-------
 1 file changed, 29 insertions(+), 15 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 834d2a354692..f01a81feb692 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -40,8 +40,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_enc_formats[] = {
 		.h_sample	= {4, 4},
 		.v_sample	= {4, 2},
 		.colplanes	= 2,
-		.h_align	= 4,
-		.v_align	= 4,
+		.h_align	= 16,
+		.v_align	= 16,
 		.flags		= MTK_JPEG_FMT_FLAG_OUTPUT,
 	},
 	{
@@ -50,8 +50,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_enc_formats[] = {
 		.h_sample	= {4, 4},
 		.v_sample	= {4, 2},
 		.colplanes	= 2,
-		.h_align	= 4,
-		.v_align	= 4,
+		.h_align	= 16,
+		.v_align	= 16,
 		.flags		= MTK_JPEG_FMT_FLAG_OUTPUT,
 	},
 	{
@@ -60,8 +60,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_enc_formats[] = {
 		.h_sample	= {8},
 		.v_sample	= {4},
 		.colplanes	= 1,
-		.h_align	= 5,
-		.v_align	= 3,
+		.h_align	= 32,
+		.v_align	= 8,
 		.flags		= MTK_JPEG_FMT_FLAG_OUTPUT,
 	},
 	{
@@ -70,8 +70,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_enc_formats[] = {
 		.h_sample	= {8},
 		.v_sample	= {4},
 		.colplanes	= 1,
-		.h_align	= 5,
-		.v_align	= 3,
+		.h_align	= 32,
+		.v_align	= 8,
 		.flags		= MTK_JPEG_FMT_FLAG_OUTPUT,
 	},
 };
@@ -87,8 +87,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_dec_formats[] = {
 		.h_sample	= {4, 2, 2},
 		.v_sample	= {4, 2, 2},
 		.colplanes	= 3,
-		.h_align	= 5,
-		.v_align	= 4,
+		.h_align	= 16,
+		.v_align	= 16,
 		.flags		= MTK_JPEG_FMT_FLAG_CAPTURE,
 	},
 	{
@@ -96,8 +96,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_dec_formats[] = {
 		.h_sample	= {4, 2, 2},
 		.v_sample	= {4, 4, 4},
 		.colplanes	= 3,
-		.h_align	= 5,
-		.v_align	= 3,
+		.h_align	= 32,
+		.v_align	= 8,
 		.flags		= MTK_JPEG_FMT_FLAG_CAPTURE,
 	},
 };
@@ -260,6 +260,7 @@ static int mtk_jpeg_try_fmt_mplane(struct v4l2_pix_format_mplane *pix_mp,
 				   struct mtk_jpeg_fmt *fmt)
 {
 	int i;
+	u32 h_align;
 
 	pix_mp->field = V4L2_FIELD_NONE;
 
@@ -283,9 +284,15 @@ static int mtk_jpeg_try_fmt_mplane(struct v4l2_pix_format_mplane *pix_mp,
 	}
 
 	/* other fourcc */
+	if (pix_mp->pixelformat == V4L2_PIX_FMT_YUYV ||
+	    pix_mp->pixelformat == V4L2_PIX_FMT_YVYU)
+		h_align = fmt->h_align / 2;
+	else
+		h_align = fmt->h_align;
+
 	pix_mp->height = clamp(round_up(pix_mp->height, fmt->v_align),
 			       MTK_JPEG_MIN_HEIGHT, MTK_JPEG_MAX_HEIGHT);
-	pix_mp->width = clamp(round_up(pix_mp->width, fmt->h_align),
+	pix_mp->width = clamp(round_up(pix_mp->width, h_align),
 			      MTK_JPEG_MIN_WIDTH, MTK_JPEG_MAX_WIDTH);
 
 	for (i = 0; i < fmt->colplanes; i++) {
@@ -293,8 +300,15 @@ static int mtk_jpeg_try_fmt_mplane(struct v4l2_pix_format_mplane *pix_mp,
 		u32 stride = pix_mp->width * fmt->h_sample[i] / 4;
 		u32 h = pix_mp->height * fmt->v_sample[i] / 4;
 
-		pfmt->bytesperline = stride;
-		pfmt->sizeimage = stride * h;
+		if (pix_mp->pixelformat == V4L2_PIX_FMT_YUYV ||
+		    pix_mp->pixelformat == V4L2_PIX_FMT_YVYU) {
+			stride = round_up(stride, fmt->h_align);
+			pfmt->bytesperline = stride;
+			pfmt->sizeimage = stride * h;
+		} else {
+			pfmt->bytesperline = stride;
+			pfmt->sizeimage = stride * h;
+		}
 	}
 	return 0;
 }
-- 
2.46.0



From jianhua.lin at mediatek.com  Mon May 26 02:36:24 2025
From: jianhua.lin at mediatek.com (Jianhua Lin)
Date: Mon, 26 May 2025 17:36:24 +0800
Subject: [PATCH v3 1/1] media: mediatek: jpeg: fix buffer alignment
Message-ID: <20250526093624.4760-1-jianhua.lin@mediatek.com>

The JPEG encoder image stride register must be MCU aligned.
For YUV422, it's 32-byte aligned, and for YUV420, it's
16-byte aligned.

The minimal DCT block size is 8x8, so the vertical buffer
alignment for YUV422 is 8-byte aligned, and for YUV420,
it's 16-byte aligned.

Signed-off-by: Jianhua Lin <jianhua.lin at mediatek.com>
---
Changes compared with v2:
- Add missing subject

Changes compared with v1:
- Fix the side effects of v1
  when encoding YUV420 with resolution 720x480, the ouput image is abnormal.
- Fix signed-off-by

 .../platform/mediatek/jpeg/mtk_jpeg_core.c    | 44 ++++++++++++-------
 1 file changed, 29 insertions(+), 15 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 834d2a354692..f01a81feb692 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -40,8 +40,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_enc_formats[] = {
 		.h_sample	= {4, 4},
 		.v_sample	= {4, 2},
 		.colplanes	= 2,
-		.h_align	= 4,
-		.v_align	= 4,
+		.h_align	= 16,
+		.v_align	= 16,
 		.flags		= MTK_JPEG_FMT_FLAG_OUTPUT,
 	},
 	{
@@ -50,8 +50,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_enc_formats[] = {
 		.h_sample	= {4, 4},
 		.v_sample	= {4, 2},
 		.colplanes	= 2,
-		.h_align	= 4,
-		.v_align	= 4,
+		.h_align	= 16,
+		.v_align	= 16,
 		.flags		= MTK_JPEG_FMT_FLAG_OUTPUT,
 	},
 	{
@@ -60,8 +60,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_enc_formats[] = {
 		.h_sample	= {8},
 		.v_sample	= {4},
 		.colplanes	= 1,
-		.h_align	= 5,
-		.v_align	= 3,
+		.h_align	= 32,
+		.v_align	= 8,
 		.flags		= MTK_JPEG_FMT_FLAG_OUTPUT,
 	},
 	{
@@ -70,8 +70,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_enc_formats[] = {
 		.h_sample	= {8},
 		.v_sample	= {4},
 		.colplanes	= 1,
-		.h_align	= 5,
-		.v_align	= 3,
+		.h_align	= 32,
+		.v_align	= 8,
 		.flags		= MTK_JPEG_FMT_FLAG_OUTPUT,
 	},
 };
@@ -87,8 +87,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_dec_formats[] = {
 		.h_sample	= {4, 2, 2},
 		.v_sample	= {4, 2, 2},
 		.colplanes	= 3,
-		.h_align	= 5,
-		.v_align	= 4,
+		.h_align	= 16,
+		.v_align	= 16,
 		.flags		= MTK_JPEG_FMT_FLAG_CAPTURE,
 	},
 	{
@@ -96,8 +96,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_dec_formats[] = {
 		.h_sample	= {4, 2, 2},
 		.v_sample	= {4, 4, 4},
 		.colplanes	= 3,
-		.h_align	= 5,
-		.v_align	= 3,
+		.h_align	= 32,
+		.v_align	= 8,
 		.flags		= MTK_JPEG_FMT_FLAG_CAPTURE,
 	},
 };
@@ -260,6 +260,7 @@ static int mtk_jpeg_try_fmt_mplane(struct v4l2_pix_format_mplane *pix_mp,
 				   struct mtk_jpeg_fmt *fmt)
 {
 	int i;
+	u32 h_align;
 
 	pix_mp->field = V4L2_FIELD_NONE;
 
@@ -283,9 +284,15 @@ static int mtk_jpeg_try_fmt_mplane(struct v4l2_pix_format_mplane *pix_mp,
 	}
 
 	/* other fourcc */
+	if (pix_mp->pixelformat == V4L2_PIX_FMT_YUYV ||
+	    pix_mp->pixelformat == V4L2_PIX_FMT_YVYU)
+		h_align = fmt->h_align / 2;
+	else
+		h_align = fmt->h_align;
+
 	pix_mp->height = clamp(round_up(pix_mp->height, fmt->v_align),
 			       MTK_JPEG_MIN_HEIGHT, MTK_JPEG_MAX_HEIGHT);
-	pix_mp->width = clamp(round_up(pix_mp->width, fmt->h_align),
+	pix_mp->width = clamp(round_up(pix_mp->width, h_align),
 			      MTK_JPEG_MIN_WIDTH, MTK_JPEG_MAX_WIDTH);
 
 	for (i = 0; i < fmt->colplanes; i++) {
@@ -293,8 +300,15 @@ static int mtk_jpeg_try_fmt_mplane(struct v4l2_pix_format_mplane *pix_mp,
 		u32 stride = pix_mp->width * fmt->h_sample[i] / 4;
 		u32 h = pix_mp->height * fmt->v_sample[i] / 4;
 
-		pfmt->bytesperline = stride;
-		pfmt->sizeimage = stride * h;
+		if (pix_mp->pixelformat == V4L2_PIX_FMT_YUYV ||
+		    pix_mp->pixelformat == V4L2_PIX_FMT_YVYU) {
+			stride = round_up(stride, fmt->h_align);
+			pfmt->bytesperline = stride;
+			pfmt->sizeimage = stride * h;
+		} else {
+			pfmt->bytesperline = stride;
+			pfmt->sizeimage = stride * h;
+		}
 	}
 	return 0;
 }
-- 
2.46.0



From mason-cw.chang at mediatek.com  Mon May 26 03:26:56 2025
From: mason-cw.chang at mediatek.com (Mason Chang)
Date: Mon, 26 May 2025 18:26:56 +0800
Subject: [PATCH 0/3] thermal/drivers/mediatek/lvts_thermal: add mt7988 lvts commands
Message-ID: <20250526102659.30225-1-mason-cw.chang@mediatek.com>

Add the LVTS commands for Mediatek Filogic 880/MT7988.

This series fixes severely abnormal and inaccurate LVTS temperature
readings when using the default commands.

Signed-off-by: Mason Chang <mason-cw.chang at mediatek.com>

Mason Chang (3):
  thermal/drivers/mediatek/lvts_thermal: change lvts commands array to
    static const
  thermal/drivers/mediatek/lvts_thermal: add lvts commands and their
    sizes to driver data
  thermal/drivers/mediatek/lvts_thermal: add mt7988 lvts commands

 drivers/thermal/mediatek/lvts_thermal.c | 74 ++++++++++++++++++++-----
 1 file changed, 61 insertions(+), 13 deletions(-)

-- 
2.45.2



From mason-cw.chang at mediatek.com  Mon May 26 03:26:57 2025
From: mason-cw.chang at mediatek.com (Mason Chang)
Date: Mon, 26 May 2025 18:26:57 +0800
Subject: [PATCH 1/3] thermal/drivers/mediatek/lvts_thermal: change lvts commands array to static const
In-Reply-To: <20250526102659.30225-1-mason-cw.chang@mediatek.com>
References: <20250526102659.30225-1-mason-cw.chang@mediatek.com>
Message-ID: <20250526102659.30225-2-mason-cw.chang@mediatek.com>

Change the LVTS commands array to static const in preparation for
adding different commands.

Signed-off-by: Mason Chang <mason-cw.chang at mediatek.com>
---
 drivers/thermal/mediatek/lvts_thermal.c | 29 +++++++++++++------------
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index 985925147..7e4f56831 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -96,6 +96,17 @@
 
 #define LVTS_MINIMUM_THRESHOLD		20000
 
+static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 };
+/*
+ * Write device mask: 0xC1030000
+ */
+static const u32 default_init_cmds[] = {
+	0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
+	0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
+	0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
+	0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
+};
+
 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
 static int golden_temp_offset;
 
@@ -902,7 +913,7 @@ static void lvts_ctrl_monitor_enable(struct device *dev, struct lvts_ctrl *lvts_
  * each write in the configuration register must be separated by a
  * delay of 2 us.
  */
-static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds)
+static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, const u32 *cmds, int nr_cmds)
 {
 	int i;
 
@@ -985,9 +996,9 @@ static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable)
 
 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
 {
-	u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 };
+	u32 id;
 
-	lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
+	lvts_write_config(lvts_ctrl, default_conn_cmds, ARRAY_SIZE(default_conn_cmds));
 
 	/*
 	 * LVTS_ID : Get ID and status of the thermal controller
@@ -1006,17 +1017,7 @@ static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
 
 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl)
 {
-	/*
-	 * Write device mask: 0xC1030000
-	 */
-	u32 cmds[] = {
-		0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
-		0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
-		0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
-		0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
-	};
-
-	lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
+	lvts_write_config(lvts_ctrl, default_init_cmds, ARRAY_SIZE(default_init_cmds));
 
 	return 0;
 }
-- 
2.45.2



From mason-cw.chang at mediatek.com  Mon May 26 03:26:58 2025
From: mason-cw.chang at mediatek.com (Mason Chang)
Date: Mon, 26 May 2025 18:26:58 +0800
Subject: [PATCH 2/3] thermal/drivers/mediatek/lvts_thermal: add lvts commands and their sizes to driver data
In-Reply-To: <20250526102659.30225-1-mason-cw.chang@mediatek.com>
References: <20250526102659.30225-1-mason-cw.chang@mediatek.com>
Message-ID: <20250526102659.30225-3-mason-cw.chang@mediatek.com>

Add LVTS commands and their sizes to driver data in preparation for
adding different commands.

Signed-off-by: Mason Chang <mason-cw.chang at mediatek.com>
---
 drivers/thermal/mediatek/lvts_thermal.c | 65 ++++++++++++++++++++-----
 1 file changed, 52 insertions(+), 13 deletions(-)

diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index 7e4f56831..5b7bf29a7 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -96,17 +96,6 @@
 
 #define LVTS_MINIMUM_THRESHOLD		20000
 
-static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 };
-/*
- * Write device mask: 0xC1030000
- */
-static const u32 default_init_cmds[] = {
-	0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
-	0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
-	0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
-	0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
-};
-
 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
 static int golden_temp_offset;
 
@@ -136,7 +125,11 @@ struct lvts_ctrl_data {
 
 struct lvts_data {
 	const struct lvts_ctrl_data *lvts_ctrl;
+	const u32 *conn_cmd;
+	const u32 *init_cmd;
 	int num_lvts_ctrl;
+	int num_conn_cmd;
+	int num_init_cmd;
 	int temp_factor;
 	int temp_offset;
 	int gt_calib_bit_offset;
@@ -996,9 +989,10 @@ static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable)
 
 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
 {
+	const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
 	u32 id;
 
-	lvts_write_config(lvts_ctrl, default_conn_cmds, ARRAY_SIZE(default_conn_cmds));
+	lvts_write_config(lvts_ctrl, lvts_data->conn_cmd, lvts_data->num_conn_cmd);
 
 	/*
 	 * LVTS_ID : Get ID and status of the thermal controller
@@ -1017,7 +1011,9 @@ static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
 
 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl)
 {
-	lvts_write_config(lvts_ctrl, default_init_cmds, ARRAY_SIZE(default_init_cmds));
+	const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
+
+	lvts_write_config(lvts_ctrl, lvts_data->init_cmd, lvts_data->num_init_cmd);
 
 	return 0;
 }
@@ -1446,6 +1442,17 @@ static int lvts_resume(struct device *dev)
 	return 0;
 }
 
+static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 };
+/*
+ * Write device mask: 0xC1030000
+ */
+static const u32 default_init_cmds[] = {
+	0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
+	0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
+	0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
+	0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
+};
+
 /*
  * The MT8186 calibration data is stored as packed 3-byte little-endian
  * values using a weird layout that makes sense only when viewed as a 32-bit
@@ -1740,7 +1747,11 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
 
 static const struct lvts_data mt7988_lvts_ap_data = {
 	.lvts_ctrl	= mt7988_lvts_ap_data_ctrl,
+	.conn_cmd	= default_conn_cmds,
+	.init_cmd	= default_init_cmds,
 	.num_lvts_ctrl	= ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
+	.num_conn_cmd	= ARRAY_SIZE(default_conn_cmds),
+	.num_init_cmd	= ARRAY_SIZE(default_init_cmds),
 	.temp_factor	= LVTS_COEFF_A_MT7988,
 	.temp_offset	= LVTS_COEFF_B_MT7988,
 	.gt_calib_bit_offset = 24,
@@ -1748,7 +1759,11 @@ static const struct lvts_data mt7988_lvts_ap_data = {
 
 static const struct lvts_data mt8186_lvts_data = {
 	.lvts_ctrl	= mt8186_lvts_data_ctrl,
+	.conn_cmd	= default_conn_cmds,
+	.init_cmd	= default_init_cmds,
 	.num_lvts_ctrl	= ARRAY_SIZE(mt8186_lvts_data_ctrl),
+	.num_conn_cmd	= ARRAY_SIZE(default_conn_cmds),
+	.num_init_cmd	= ARRAY_SIZE(default_init_cmds),
 	.temp_factor	= LVTS_COEFF_A_MT7988,
 	.temp_offset	= LVTS_COEFF_B_MT7988,
 	.gt_calib_bit_offset = 24,
@@ -1757,7 +1772,11 @@ static const struct lvts_data mt8186_lvts_data = {
 
 static const struct lvts_data mt8188_lvts_mcu_data = {
 	.lvts_ctrl	= mt8188_lvts_mcu_data_ctrl,
+	.conn_cmd	= default_conn_cmds,
+	.init_cmd	= default_init_cmds,
 	.num_lvts_ctrl	= ARRAY_SIZE(mt8188_lvts_mcu_data_ctrl),
+	.num_conn_cmd	= ARRAY_SIZE(default_conn_cmds),
+	.num_init_cmd	= ARRAY_SIZE(default_init_cmds),
 	.temp_factor	= LVTS_COEFF_A_MT8195,
 	.temp_offset	= LVTS_COEFF_B_MT8195,
 	.gt_calib_bit_offset = 20,
@@ -1766,7 +1785,11 @@ static const struct lvts_data mt8188_lvts_mcu_data = {
 
 static const struct lvts_data mt8188_lvts_ap_data = {
 	.lvts_ctrl	= mt8188_lvts_ap_data_ctrl,
+	.conn_cmd	= default_conn_cmds,
+	.init_cmd	= default_init_cmds,
 	.num_lvts_ctrl	= ARRAY_SIZE(mt8188_lvts_ap_data_ctrl),
+	.num_conn_cmd	= ARRAY_SIZE(default_conn_cmds),
+	.num_init_cmd	= ARRAY_SIZE(default_init_cmds),
 	.temp_factor	= LVTS_COEFF_A_MT8195,
 	.temp_offset	= LVTS_COEFF_B_MT8195,
 	.gt_calib_bit_offset = 20,
@@ -1775,7 +1798,11 @@ static const struct lvts_data mt8188_lvts_ap_data = {
 
 static const struct lvts_data mt8192_lvts_mcu_data = {
 	.lvts_ctrl	= mt8192_lvts_mcu_data_ctrl,
+	.conn_cmd	= default_conn_cmds,
+	.init_cmd	= default_init_cmds,
 	.num_lvts_ctrl	= ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
+	.num_conn_cmd	= ARRAY_SIZE(default_conn_cmds),
+	.num_init_cmd	= ARRAY_SIZE(default_init_cmds),
 	.temp_factor	= LVTS_COEFF_A_MT8195,
 	.temp_offset	= LVTS_COEFF_B_MT8195,
 	.gt_calib_bit_offset = 24,
@@ -1784,7 +1811,11 @@ static const struct lvts_data mt8192_lvts_mcu_data = {
 
 static const struct lvts_data mt8192_lvts_ap_data = {
 	.lvts_ctrl	= mt8192_lvts_ap_data_ctrl,
+	.conn_cmd	= default_conn_cmds,
+	.init_cmd	= default_init_cmds,
 	.num_lvts_ctrl	= ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
+	.num_conn_cmd	= ARRAY_SIZE(default_conn_cmds),
+	.num_init_cmd	= ARRAY_SIZE(default_init_cmds),
 	.temp_factor	= LVTS_COEFF_A_MT8195,
 	.temp_offset	= LVTS_COEFF_B_MT8195,
 	.gt_calib_bit_offset = 24,
@@ -1793,7 +1824,11 @@ static const struct lvts_data mt8192_lvts_ap_data = {
 
 static const struct lvts_data mt8195_lvts_mcu_data = {
 	.lvts_ctrl	= mt8195_lvts_mcu_data_ctrl,
+	.conn_cmd	= default_conn_cmds,
+	.init_cmd	= default_init_cmds,
 	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
+	.num_conn_cmd	= ARRAY_SIZE(default_conn_cmds),
+	.num_init_cmd	= ARRAY_SIZE(default_init_cmds),
 	.temp_factor	= LVTS_COEFF_A_MT8195,
 	.temp_offset	= LVTS_COEFF_B_MT8195,
 	.gt_calib_bit_offset = 24,
@@ -1802,7 +1837,11 @@ static const struct lvts_data mt8195_lvts_mcu_data = {
 
 static const struct lvts_data mt8195_lvts_ap_data = {
 	.lvts_ctrl	= mt8195_lvts_ap_data_ctrl,
+	.conn_cmd	= default_conn_cmds,
+	.init_cmd	= default_init_cmds,
 	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
+	.num_conn_cmd	= ARRAY_SIZE(default_conn_cmds),
+	.num_init_cmd	= ARRAY_SIZE(default_init_cmds),
 	.temp_factor	= LVTS_COEFF_A_MT8195,
 	.temp_offset	= LVTS_COEFF_B_MT8195,
 	.gt_calib_bit_offset = 24,
-- 
2.45.2



From mason-cw.chang at mediatek.com  Mon May 26 03:26:59 2025
From: mason-cw.chang at mediatek.com (Mason Chang)
Date: Mon, 26 May 2025 18:26:59 +0800
Subject: [PATCH 3/3] thermal/drivers/mediatek/lvts_thermal: add mt7988 lvts commands
In-Reply-To: <20250526102659.30225-1-mason-cw.chang@mediatek.com>
References: <20250526102659.30225-1-mason-cw.chang@mediatek.com>
Message-ID: <20250526102659.30225-4-mason-cw.chang@mediatek.com>

These commands are necessary to avoid severely abnormal and inaccurate
temperature readings that are caused by using the default commands.

Signed-off-by: Mason Chang <mason-cw.chang at mediatek.com>
---
 drivers/thermal/mediatek/lvts_thermal.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index 5b7bf29a7..4d49482f0 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -1443,6 +1443,8 @@ static int lvts_resume(struct device *dev)
 }
 
 static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 };
+static const u32 mt7988_conn_cmds[] = { 0xC103FFFF, 0xC502FC55 };
+
 /*
  * Write device mask: 0xC1030000
  */
@@ -1453,6 +1455,12 @@ static const u32 default_init_cmds[] = {
 	0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
 };
 
+static const u32 mt7988_init_cmds[] = {
+	0xC1030300, 0xC1030420, 0xC1030500, 0xC10307A6, 0xC1030CFC,
+	0xC1030A8C, 0xC103098D, 0xC10308F1, 0xC1030B04, 0xC1030E01,
+	0xC10306B8
+};
+
 /*
  * The MT8186 calibration data is stored as packed 3-byte little-endian
  * values using a weird layout that makes sense only when viewed as a 32-bit
@@ -1747,11 +1755,11 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
 
 static const struct lvts_data mt7988_lvts_ap_data = {
 	.lvts_ctrl	= mt7988_lvts_ap_data_ctrl,
-	.conn_cmd	= default_conn_cmds,
-	.init_cmd	= default_init_cmds,
+	.conn_cmd	= mt7988_conn_cmds,
+	.init_cmd	= mt7988_init_cmds,
 	.num_lvts_ctrl	= ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
-	.num_conn_cmd	= ARRAY_SIZE(default_conn_cmds),
-	.num_init_cmd	= ARRAY_SIZE(default_init_cmds),
+	.num_conn_cmd	= ARRAY_SIZE(mt7988_conn_cmds),
+	.num_init_cmd	= ARRAY_SIZE(mt7988_init_cmds),
 	.temp_factor	= LVTS_COEFF_A_MT7988,
 	.temp_offset	= LVTS_COEFF_B_MT7988,
 	.gt_calib_bit_offset = 24,
-- 
2.45.2



From louisalexis.eyraud at collabora.com  Mon May 26 03:45:27 2025
From: louisalexis.eyraud at collabora.com (Louis-Alexis Eyraud)
Date: Mon, 26 May 2025 12:45:27 +0200
Subject: [PATCH] arm64: dts: mediatek: mt8395-genio-1200-evk: Enable Audio
 DSP and sound card
Message-ID: <20250526-mt8395-genio-1200-evk-sound-v1-1-142fb15292c5@collabora.com>

Add in the mt8395-genio-1200-evk devicetree the memory regions for the
Audio DSP (ADSP) and Audio Front-End (AFE), and a sound card node
configured to use the ADSP.
This enables audio output through the 3.5mm headphone jacks (speaker or
earphone), available on the board.

Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>
---
Tested on a Mediatek Genio 1200-EVK board with a kernel
based on linux-next (tag: next-20250526).
---
 .../boot/dts/mediatek/mt8395-genio-1200-evk.dts    | 46 +++++++++++++++++++++-
 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
index be5e5f339e811728e91b1ffec45ada25f9b0208b..9f0734731b5ef3c6b86693a389adc399707d5212 100644
--- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
@@ -79,9 +79,21 @@ bl31_secmon_mem: memory at 54600000 {
 			reg = <0 0x54600000 0x0 0x200000>;
 		};
 
-		snd_dma_mem: memory at 60000000 {
+		adsp_mem: memory at 60000000 {
 			compatible = "shared-dma-pool";
-			reg = <0 0x60000000 0 0x1100000>;
+			reg = <0 0x60000000 0 0xf00000>;
+			no-map;
+		};
+
+		afe_dma_mem: memory at 60f00000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x60f00000 0 0x100000>;
+			no-map;
+		};
+
+		adsp_dma_mem: memory at 61000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x61000000 0 0x100000>;
 			no-map;
 		};
 
@@ -179,6 +191,16 @@ wifi_fixed_3v3: regulator-2 {
 	};
 };
 
+&adsp {
+	memory-region = <&adsp_dma_mem>, <&adsp_mem>;
+	status = "okay";
+};
+
+&afe {
+	memory-region = <&afe_dma_mem>;
+	status = "okay";
+};
+
 &disp_pwm0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&disp_pwm0_pins>;
@@ -976,6 +998,26 @@ &scp {
 	status = "okay";
 };
 
+&sound {
+	compatible = "mediatek,mt8195_mt6359";
+	model = "mt8395-evk";
+	pinctrl-names = "default";
+	pinctrl-0 = <&audio_default_pins>;
+	audio-routing =
+		"Headphone", "Headphone L",
+		"Headphone", "Headphone R";
+	mediatek,adsp = <&adsp>;
+	status = "okay";
+
+	headphone-dai-link {
+		link-name = "DL_SRC_BE";
+
+		codec {
+			sound-dai = <&pmic 0>;
+		};
+	};
+};
+
 &spi1 {
 	pinctrl-0 = <&spi1_pins>;
 	pinctrl-names = "default";

---
base-commit: 22d449bcd69e66f25fe847b678738950dcf9301e
change-id: 20250521-mt8395-genio-1200-evk-sound-5a88bcfa3e0c

Best regards,
-- 
Louis-Alexis Eyraud <louisalexis.eyraud at collabora.com>



From miquel.raynal at bootlin.com  Mon May 26 05:25:21 2025
From: miquel.raynal at bootlin.com (Miquel Raynal)
Date: Mon, 26 May 2025 14:25:21 +0200
Subject: [PATCH nand/next] mtd: nand: spi: Use write_cache first and
 then update_cache in write operation
In-Reply-To: <CAJsYDVKiMeYY2rw_BxuW4BAxvMcq5hDwzhiPoAR=tkXzZpRYiw@mail.gmail.com>
	(Chuanhong Guo's message of "Tue, 29 Apr 2025 19:58:05 +0800")
References: <20241119093949.3014-1-SkyLake.Huang@mediatek.com>
	<871pymtab3.fsf@bootlin.com>
	<c1e2d8ea-1b37-479d-8239-cb9bf0efdcaf@gmail.com>
	<87bjsfv0x1.fsf@bootlin.com>
	<CAJsYDVKiMeYY2rw_BxuW4BAxvMcq5hDwzhiPoAR=tkXzZpRYiw@mail.gmail.com>
Message-ID: <87sekry2xa.fsf@bootlin.com>

Hello Chuanhong,

>> >>> Before applying this patch, write operation uses only 34H(update_cache):
>> >>> [78.937720] OP code: 0x34, addr val: 0x0, data nbytes: 1020, data 1st byte: 0xa5
>> >>> [78.945297] OP code: 0x34, addr val: 0x3fc, data nbytes: 1020, data 1st byte: 0xa5
>> >>> [78.954251] OP code: 0x34, addr val: 0x7f8, data nbytes: 72, data 1st byte: 0xa5
>> >>> [78.962966] OP code: 0x10, addr val: 0x300
>> >>> [78.968816] OP code: 0x34, addr val: 0x0, data nbytes: 1020, data 1st byte: 0xff
>> >>> [78.977233] OP code: 0x34, addr val: 0x3fc, data nbytes: 1020, data 1st byte: 0xff
>> >>> [78.985124] OP code: 0x34, addr val: 0x7f8, data nbytes: 72, data 1st byte: 0xff
>> >>> [78.992527] OP code: 0x10, addr val: 0x301
>> >>> [78.996981] OP code: 0x34, addr val: 0x0, data nbytes: 1020, data 1st byte: 0xff
>> >>> [79.004416] OP code: 0x34, addr val: 0x3fc, data nbytes: 1020, data 1st byte: 0xff
>> >>> [79.012031] OP code: 0x34, addr val: 0x7f8, data nbytes: 72, data 1st byte: 0xff
>> >>> [79.019435] OP code: 0x10, addr val: 0x302
>> >> I am sorry but above you said that we should not perform:
>> >>      0x32, 0x32, 0x32...
>> >> because the second time it would clear the cache again. And here
>> >> you tell us that actually the core already handles that by performing
>> >> instead:
>> >>      0x34, 0x34, 0x34...
>> >> So what is the problem?
>> >> Or maybe I misunderstood the issue, but I think Chuanhong raised an
>> >> issue that is already solved? Isn't it?
>> >>
>> >
>> > The issue is that the FORESEE NANDs require the first cache writing
>> > instruction to be WRITE_CACHE instead of UPDATE_CACHE. i.e. it needs a
>> > command sequence of:
>> >     0x32, 0x34, 0x34, 0x34...
>>
>> So Foresee NANDs do not support update_cache, why are they advertised in
>> the first place? Could you we have a less impacting solution for the
>> other NANDs?
>>
>> > This patch does exactly that, making the first instruction issued 0x32.
>> > It should be applied to fix the issue above.
>>
>> My understanding is that this is very specific to FORESEE NANDs and you
>> are changing this for all NANDs. I have fears that it will break
>> everywhere else.
>
> I just checked a few datasheets of SPI-NANDs from
> Toshiba/Winbond/Etron/ESMT/GigaDevice/Macronix.
> All of them specify the programming sequence to be:
> write_enable->write_cache->update_cache if needed->
> program_execute->poll status.
> Some of them mentions that the only difference between write_cache
> and update_cache is whether the page cache is cleared before
> writing (Winbond), while others don't specifically say that.
>
> The original sequence doesn't seem to be following any manufacturers'
> instructions. We just haven't run into any problems until this FORESEE
> one.

That is what I am saying. It currently works, and we may encounter
silent failures all around because of this change, even if it might be
theoretically correct. Anyhow, we have these templates (both write and
update) so let's try to re-use them.

However I dislike the current implementation which changes the global
wdesc template and puts it back. Can you please propose something cleaner?

Thanks,
Miqu?l


From mikhail.kshevetskiy at iopsys.eu  Mon May 26 05:31:23 2025
From: mikhail.kshevetskiy at iopsys.eu (Mikhail Kshevetskiy)
Date: Mon, 26 May 2025 15:31:23 +0300
Subject: [PATCH v3] arm64: dts: mediatek: mt7986-bpi-r3: Change fan PWM value for mid speed
Message-ID: <20250526123123.2515967-1-mikhail.kshevetskiy@iopsys.eu>

Popular cheap PWM fans for this machine, like the ones coming in
heatsink+fan combos will not work properly at the currently defined
medium speed. Trying different pwm setting using a command

  echo $value > /sys/devices/platform/pwm-fan/hwmon/hwmon1/pwm1

I found:

  pwm1 value     fan rotation speed   cpu temperature     notes
  -----------------------------------------------------------------
    0            maximal              31.5 Celsius        too noisy
   40            optimal              35.2 Celsius        no noise hearable
   95            minimal
   above 95      does not rotate      55.5 Celsius
  -----------------------------------------------------------------

Thus only cpu-active-high and cpu-active-low modes are usable.
I think this is wrong.

This patch fixes cpu-active-medium settings for bpi-r3 board.

I know, the patch is not ideal as it can break pwm fan for some users.
Likely this is the only official mt7986-bpi-r3 heatsink+fan solution
available on the market.

This patch may not be enough. Users may wants to tweak their thermal_zone0
trip points, thus tuning fan rotation speed depending on cpu temperature.
That can be done on the base of the following example:

  === example =========
  # cpu temperature below 25 Celsius degrees, no rotation
  echo 25000 > /sys/class/thermal/thermal_zone0/trip_point_4_temp
  # cpu temperature in [25..32] Celsius degrees, normal rotation speed
  echo 32000 > /sys/class/thermal/thermal_zone0/trip_point_3_temp
  # cpu temperature above 50 Celsius degrees, max rotation speed
  echo 50000 > /sys/class/thermal/thermal_zone0/trip_point_2_temp
  =====================

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy at iopsys.eu>

---
>From Frank Wunderlich <frank-w at public-files.de>
Date: 04.03.2025
>
> sorry for delay
>
> i have the fan from sinovoip and that was working for me, but if your fan only works with new values, i have no point against this change.

Frank, does it means that you are signed off this patch?

Changes from v1 to v2:
 * improve patch description

Changes from v2 to v3:
 * added question to Frank Wunderlich
---
 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
index ed79ad1ae871..b0cc0cbdff0f 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
@@ -42,7 +42,7 @@ fan: pwm-fan {
 		compatible = "pwm-fan";
 		#cooling-cells = <2>;
 		/* cooling level (0, 1, 2) - pwm inverted */
-		cooling-levels = <255 96 0>;
+		cooling-levels = <255 40 0>;
 		pwms = <&pwm 0 10000>;
 		status = "okay";
 	};
-- 
2.47.2



From frank-w at public-files.de  Mon May 26 07:20:13 2025
From: frank-w at public-files.de (Frank Wunderlich)
Date: Mon, 26 May 2025 16:20:13 +0200
Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v3=5D_arm64=3A_dts=3A_mediatek=3A_mt7986?=
 =?US-ASCII?Q?-bpi-r3=3A_Change_fan_PWM_value_for_mid_speed?=
In-Reply-To: <20250526123123.2515967-1-mikhail.kshevetskiy@iopsys.eu>
References: <20250526123123.2515967-1-mikhail.kshevetskiy@iopsys.eu>
Message-ID: <B06376CB-BE3F-4645-8A4D-A9C67CDCA3EC@public-files.de>

Am 26. Mai 2025 14:31:23 MESZ schrieb Mikhail Kshevetskiy <mikhail.kshevetskiy at iopsys.eu>:
>Popular cheap PWM fans for this machine, like the ones coming in
>heatsink+fan combos will not work properly at the currently defined
>medium speed. Trying different pwm setting using a command
>
>  echo $value > /sys/devices/platform/pwm-fan/hwmon/hwmon1/pwm1
>
>I found:
>
>  pwm1 value     fan rotation speed   cpu temperature     notes
>  -----------------------------------------------------------------
>    0            maximal              31.5 Celsius        too noisy
>   40            optimal              35.2 Celsius        no noise hearable
>   95            minimal
>   above 95      does not rotate      55.5 Celsius
>  -----------------------------------------------------------------
>
>Thus only cpu-active-high and cpu-active-low modes are usable.
>I think this is wrong.
>
>This patch fixes cpu-active-medium settings for bpi-r3 board.
>
>I know, the patch is not ideal as it can break pwm fan for some users.
>Likely this is the only official mt7986-bpi-r3 heatsink+fan solution
>available on the market.
>
>This patch may not be enough. Users may wants to tweak their thermal_zone0
>trip points, thus tuning fan rotation speed depending on cpu temperature.
>That can be done on the base of the following example:
>
>  === example =========
>  # cpu temperature below 25 Celsius degrees, no rotation
>  echo 25000 > /sys/class/thermal/thermal_zone0/trip_point_4_temp
>  # cpu temperature in [25..32] Celsius degrees, normal rotation speed
>  echo 32000 > /sys/class/thermal/thermal_zone0/trip_point_3_temp
>  # cpu temperature above 50 Celsius degrees, max rotation speed
>  echo 50000 > /sys/class/thermal/thermal_zone0/trip_point_2_temp
>  =====================
>
>Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy at iopsys.eu>
>
>---
>From Frank Wunderlich <frank-w at public-files.de>
>Date: 04.03.2025
>>
>> sorry for delay
>>
>> i have the fan from sinovoip and that was working for me, but if your fan only works with new values, i have no point against this change.
>
>Frank, does it means that you are signed off this patch?

Let it count as

Acked-by: Frank Wunderlich <frank-w at public-files.de>

Because i cannot test these values,as i only have 1 pwm fan for r3 in my main router :p
Maybe R4 fan works too,but not yet tested.

Not sure if the complete testcase has to be in the commit description,but this is maintainers decision.

>Changes from v1 to v2:
> * improve patch description
>
>Changes from v2 to v3:
> * added question to Frank Wunderlich
>---
> arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
>index ed79ad1ae871..b0cc0cbdff0f 100644
>--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
>+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
>@@ -42,7 +42,7 @@ fan: pwm-fan {
> 		compatible = "pwm-fan";
> 		#cooling-cells = <2>;
> 		/* cooling level (0, 1, 2) - pwm inverted */
>-		cooling-levels = <255 96 0>;
>+		cooling-levels = <255 40 0>;
> 		pwms = <&pwm 0 10000>;
> 		status = "okay";
> 	};


regards Frank


From conor at kernel.org  Mon May 26 07:29:53 2025
From: conor at kernel.org (Conor Dooley)
Date: Mon, 26 May 2025 15:29:53 +0100
Subject: [PATCH] media: dt-bindings: mediatek: Constrain iommus
In-Reply-To: <20250525051639.68753-2-krzysztof.kozlowski@linaro.org>
References: <20250525051639.68753-2-krzysztof.kozlowski@linaro.org>
Message-ID: <20250526-churn-survey-92e4ac835db3@spud>

On Sun, May 25, 2025 at 07:16:40AM +0200, Krzysztof Kozlowski wrote:
> Lists should have fixed constraints, because binding must be specific in
> respect to hardware.  Add missing constraints to number of iommus in
> Mediatek media devices.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Acked-by: Conor Dooley <conor.dooley at microchip.com>
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From kory.maincent at bootlin.com  Mon May 26 08:04:46 2025
From: kory.maincent at bootlin.com (Kory Maincent)
Date: Mon, 26 May 2025 17:04:46 +0200
Subject: [PATCH V5] nvmem: add explicit config option to read old syntax
 fixed OF cells
In-Reply-To: <20230927204446.4231-1-zajec5@gmail.com>
References: <20230927204446.4231-1-zajec5@gmail.com>
Message-ID: <20250526170446.1190e046@kmaincent-XPS-13-7390>

Le Wed, 27 Sep 2023 22:44:46 +0200,
Rafa? Mi?ecki <zajec5 at gmail.com> a ?crit :

> From: Rafa? Mi?ecki <rafal at milecki.pl>
> 
> Binding for fixed NVMEM cells defined directly as NVMEM device subnodes
> has been deprecated. It has been replaced by the "fixed-layout" NVMEM
> layout binding.
> 
> New syntax is meant to be clearer and should help avoiding imprecise
> bindings.
> 
> NVMEM subsystem already supports the new binding. It should be a good
> idea to limit support for old syntax to existing drivers that actually
> support & use it (we can't break backward compatibility!). That way we
> additionally encourage new bindings & drivers to ignore deprecated
> binding.
> 
> It wasn't clear (to me) if rtc and w1 code actually uses old syntax
> fixed cells. I enabled them to don't risk any breakage.

Hello,

Was there a reason to not add the legacy flag to all the drivers that was
supporting nvmem at the time nvmem fixed layout was supported?

I just faced a nvmem layout regression on board with an at24 eeprom.

Commit: 27f699e578b1 nvmem: core: add support for fixed cells *layout*
$ git grep nvmem_config drivers/ | cut -d ':' -f 1 | sort -u
drivers/hwmon/pmbus/adm1266.c
drivers/iio/pressure/bmp280-core.c
drivers/media/i2c/ov2740.c
drivers/media/i2c/video-i2c.c
drivers/misc/eeprom/at24.c
drivers/misc/eeprom/at25.c
drivers/misc/eeprom/eeprom_93xx46.c
drivers/mtd/mtdcore.c
drivers/nvmem/apple-efuses.c
drivers/nvmem/bcm-ocotp.c
drivers/nvmem/brcm_nvram.c
drivers/nvmem/core.c
drivers/nvmem/imx-iim.c
drivers/nvmem/imx-ocotp.c
drivers/nvmem/imx-ocotp-ele.c
drivers/nvmem/imx-ocotp-scu.c
drivers/nvmem/jz4780-efuse.c
drivers/nvmem/lan9662-otpc.c
drivers/nvmem/layerscape-sfp.c
drivers/nvmem/lpc18xx_eeprom.c
drivers/nvmem/lpc18xx_otp.c
drivers/nvmem/meson-efuse.c
drivers/nvmem/meson-mx-efuse.c
drivers/nvmem/microchip-otpc.c
drivers/nvmem/mtk-efuse.c
drivers/nvmem/mxs-ocotp.c
drivers/nvmem/nintendo-otp.c
drivers/nvmem/qcom-spmi-sdam.c
drivers/nvmem/qfprom.c
drivers/nvmem/rave-sp-eeprom.c
drivers/nvmem/rmem.c
drivers/nvmem/rockchip-efuse.c
drivers/nvmem/rockchip-otp.c
drivers/nvmem/sc27xx-efuse.c
drivers/nvmem/snvs_lpgpr.c
drivers/nvmem/sprd-efuse.c
drivers/nvmem/stm32-romem.c
drivers/nvmem/sunplus-ocotp.c
drivers/nvmem/sunxi_sid.c
drivers/nvmem/u-boot-env.c
drivers/nvmem/uniphier-efuse.c
drivers/nvmem/vf610-ocotp.c
drivers/nvmem/zynqmp_nvmem.c
drivers/rtc/nvmem.c
drivers/rtc/rtc-abx80x.c
drivers/rtc/rtc-cmos.c
drivers/rtc/rtc-ds1305.c
drivers/rtc/rtc-ds1307.c
drivers/rtc/rtc-ds1343.c
drivers/rtc/rtc-ds1511.c
drivers/rtc/rtc-ds1553.c
drivers/rtc/rtc-ds1685.c
drivers/rtc/rtc-ds1742.c
drivers/rtc/rtc-ds3232.c
drivers/rtc/rtc-isl12026.c
drivers/rtc/rtc-isl1208.c
drivers/rtc/rtc-m48t59.c
drivers/rtc/rtc-m48t86.c
drivers/rtc/rtc-meson.c
drivers/rtc/rtc-omap.c
drivers/rtc/rtc-pcf2127.c
drivers/rtc/rtc-pcf85063.c
drivers/rtc/rtc-pcf85363.c
drivers/rtc/rtc-rp5c01.c
drivers/rtc/rtc-rv3028.c
drivers/rtc/rtc-rv3029c2.c
drivers/rtc/rtc-rv3032.c
drivers/rtc/rtc-rv8803.c
drivers/rtc/rtc-rx8581.c
drivers/rtc/rtc-stk17ta8.c
drivers/rtc/rtc-sun6i.c
drivers/rtc/rtc-ti-k3.c
drivers/soc/atmel/sfr.c
drivers/soc/tegra/fuse/fuse-tegra.c
drivers/thunderbolt/nvm.c
drivers/w1/slaves/w1_ds250x.c

-- 
K?ry Maincent, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com


From patchwork-bot+netdevbpf at kernel.org  Mon May 26 08:40:35 2025
From: patchwork-bot+netdevbpf at kernel.org (patchwork-bot+netdevbpf at kernel.org)
Date: Mon, 26 May 2025 15:40:35 +0000
Subject: [PATCH net-next v3 0/4] Add the capability to consume SRAM for
 hwfd descriptor queue in airoha_eth driver
In-Reply-To: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
References: <20250521-airopha-desc-sram-v3-0-a6e9b085b4f0@kernel.org>
Message-ID: <174827403500.961666.15762374544120433912.git-patchwork-notify@kernel.org>

Hello:

This series was applied to netdev/net-next.git (main)
by Paolo Abeni <pabeni at redhat.com>:

On Wed, 21 May 2025 09:16:35 +0200 you wrote:
> In order to improve packet processing and packet forwarding
> performances, EN7581 SoC supports consuming SRAM instead of DRAM for hw
> forwarding descriptors queue. For downlink hw accelerated traffic
> request to consume SRAM memory for hw forwarding descriptors queue.
> Moreover, in some configurations QDMA blocks require a contiguous block
> of system memory for hwfd buffers queue. Introduce the capability to
> allocate hw buffers forwarding queue via the reserved-memory DTS
> property instead of running dmam_alloc_coherent().
> 
> [...]

Here is the summary with links:
  - [net-next,v3,1/4] dt-bindings: net: airoha: Add EN7581 memory-region property
    https://git.kernel.org/netdev/net-next/c/2d13b45f8086
  - [net-next,v3,2/4] net: airoha: Do not store hfwd references in airoha_qdma struct
    https://git.kernel.org/netdev/net-next/c/09aa788f98da
  - [net-next,v3,3/4] net: airoha: Add the capability to allocate hwfd buffers via reserved-memory
    https://git.kernel.org/netdev/net-next/c/3a1ce9e3d01b
  - [net-next,v3,4/4] net: airoha: Add the capability to allocate hfwd descriptors in SRAM
    https://git.kernel.org/netdev/net-next/c/c683e378c090

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html




From pabeni at redhat.com  Mon May 26 08:55:03 2025
From: pabeni at redhat.com (Paolo Abeni)
Date: Mon, 26 May 2025 17:55:03 +0200
Subject: [PATCH net-next] net: phy: mtk-2p5ge: Add LED support for MT7988
In-Reply-To: <20250526091019.16096-1-SkyLake.Huang@mediatek.com>
References: <20250526091019.16096-1-SkyLake.Huang@mediatek.com>
Message-ID: <edb8881d-0cac-4f7e-b358-299bb30b5f27@redhat.com>

On 5/26/25 11:10 AM, Sky Huang wrote:
> From: Sky Huang <skylake.huang at mediatek.com>
> 
> Add LED support for MT7988's built-in 2.5Gphy. LED hardware has almost
> the same design with MT7981's/MT7988's built-in GbE. So hook the same
> helper function here.
> 
> Before mtk_phy_leds_state_init(), set correct default values of LED0
> and LED1.
> 
> Signed-off-by: Sky Huang <skylake.huang at mediatek.com>
> Reviewed-by: Andrew Lunn <andrew at lunn.ch>

## Form letter - net-next-closed

The merge window for v6.16 has begun and therefore net-next is closed
for new drivers, features, code refactoring and optimizations. We are
currently accepting bug fixes only.

Please repost when net-next reopens after June 8th.

RFC patches sent for review only are obviously welcome at any time.



From victor.liu at nxp.com  Mon May 26 18:42:11 2025
From: victor.liu at nxp.com (Liu Ying)
Date: Tue, 27 May 2025 09:42:11 +0800
Subject: [PATCH v2 30/34] drm/bridge: imx8qxp-pixel-combiner: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250526092024.48cae4ae@booty>
References: <20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b@bootlin.com>
 <20250424-drm-bridge-convert-to-alloc-api-v2-30-8f91a404d86b@bootlin.com>
 <553d62ed-976a-4e17-9678-cdc3d40ce4a7@nxp.com>
 <20250430112944.1b39caab@booty>
 <f71d18d2-4271-4bb9-b54f-0e5a585778f3@nxp.com>
 <20250506224720.5cbcf3e1@booty>
 <67252c36-8b31-4c40-9d89-4f502da4a087@nxp.com>
 <20250526092024.48cae4ae@booty>
Message-ID: <0a88178f-a3f1-4aa1-94e9-6050330ff168@nxp.com>

On 05/26/2025, Luca Ceresoli wrote:
> Hello Liu,

Hi Luca,

> 
> On Thu, 22 May 2025 11:01:13 +0800
> Liu Ying <victor.liu at nxp.com> wrote:
> 
>> On 05/07/2025, Luca Ceresoli wrote:
>>
>> [...]
>>
>>>> After looking into this patch and patch 31(though I've already provided my A-b)
>>>> more closely, I think the imx8qxp_pc and imx8{qm,qxp}_ldb main structures
>>>> should have the same life time with the embedded DRM bridges, because for
>>>> example the clk_apb clock in struct imx8qxp_pc would be accessed by the
>>>> imx8qxp_pc_bridge_mode_set DRM bridge callback.  But, IIUC, your patches extend
>>>> the life time for the embedded channel/bridge structures only, but not for the
>>>> main structures.  What do you think ?  
>>>
>>> I see you concern, but I'm sure the change I'm introducing is not
>>> creating the problem you are concerned about.
>>>
>>> The key aspect is that my patch is merely changing the lifetime of the
>>> _allocation_ of the drm_bridge, not its usage. On drm_bridge_remove()
>>> the bridge is removed from its encoder chain and it is completely not
>>> reachable, both before and after my patch. With my patch it is not  
>>
>> drm_bridge_remove() only removes a bridge from the global bridge_list defined
>> in drm_bridge.c.  drm_bridge_detach() is the one which removes a bridge from
>> it's encoder chain.  It looks like you wrongly thought drm_bridge_remove()
>> is drm_bridge_detach().
> 
> Indeed my sentence was inaccurate, sorry about that.
> 
>> So, even if drm_bridge_remove() is called, the removed
>> bridge could still be in it's encoder chain, hence an atomic commit could still
>> access the allocated bridge(with lifetime extended) and the clock_apb clock
>> for example in struct imx8qxp_pc could also be accessed.  That's why I think
>> the main structures should have the same lifetime with the allocated bridge.
> 
> As the long-term goal is to allow bridges to be hot-removable,
> decoupling the lifetime of the various components is a necessary step.
> Definitely it will open other issues, and especially the removal during
> atomic updates. This has been discussed already, and there is a
> proposed plan to handle it.
> 
> First, here is the grand plan (mentioned in the v3 cover letter):
> 
>  1. ? add refcounting to DRM bridges (struct drm_bridge)
>  2. handle gracefully atomic updates during bridge removal
>  3. avoid DSI host drivers to have dangling pointers to DSI devices
>  4. finally, let bridges be removable (depends on 1+2+3)
> 
> We are now at step 1. Your concern, as I understand it, will be
> addressed at step 2. Bridges won't be removable until step 4, so the
> current changes are not introducing a misbehavior but rather preparing
> the ground with all the necessary infrastructure changes.
> 
> Step 2 was discussed in the past [0], and the idea proposed by Maxime
> is to introduce a "gone" or "unplugged" flag and drm_bridge_enter() /
> drm_bridge_exit() functions. The principle is the same as struct
> drm_device.unplugged and drm_dev_enter/exit().
> 
> In a nutshell the idea is:
> 
>  - drm_bridge.unplugged is initialized to false
>  - drm_bridge_enter() returns false if drm_bridge.unplugged == true
>  - any code holding a pointer to the bridge (including the bridge driver
>    itself) and operating on the bridge (including removal) needs to do:
>      if (drm_bridge_enter()) {
>          do something;
>          drm_bridge_exit();
>      }
>  - when the bridge is removed, the driver removal function sets
>    dev_bridge.unplugged = true
> 
> The "do something" above includes any access to device resources,
> including clocks (and clk_apb).
> 
> In other words, two pieces of code can not access the bridge structure
> at the same time. This includes bridge removal VS any atomic operations.
> 
> Do you think this addresses your concern?

Yes, drm_bridge_{enter,exit} address it.

> 
> 
> For you to have a better picture of the path, here's an additional
> clarification about drm_bridge_attach/detach() and
> drm_bridge_add/remove(). As part of step 1 of the grand plan, both of
> them will drm_bridge_get/put() the bridge, so that no bridge is freed
> if it is either in the global bridge_list or in any encoder chain.
> 
> Patches for this are already approved by Maxime [1][2]. They cannot be
> applied until all bridge drivers have been converted to the new
> devm_drm_bridge_alloc() API, so they depend on this series to be
> completely applied. We are getting pretty close: as of now the entire
> series has been applied except for this and another driver.
> 
> [0] https://lore.kernel.org/all/20250129125153.35d0487a at booty/t/#u
> [1] https://patchwork.freedesktop.org/patch/643095/
> [2] https://patchwork.freedesktop.org/patch/643096/
> 
> Best regards,
> Luca
> 

-- 
Regards,
Liu Ying


From victor.liu at nxp.com  Mon May 26 18:48:05 2025
From: victor.liu at nxp.com (Liu Ying)
Date: Tue, 27 May 2025 09:48:05 +0800
Subject: [PATCH v3 18/22] drm/bridge: imx8qxp-pixel-combiner: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-18-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
 <20250509-drm-bridge-convert-to-alloc-api-v3-18-b8bc1f16d7aa@bootlin.com>
Message-ID: <f11206e5-4c59-411e-bb91-2d50befbe930@nxp.com>

On 05/09/2025, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> This driver embeds an array of channels in the main struct, and each
> channel embeds a drm_bridge. This prevents dynamic, refcount-based
> deallocation of the bridges.
> 
> To make the new, dynamic bridge allocation possible:
> 
>  * change the array of channels into an array of channel pointers
>  * allocate each channel using devm_drm_bridge_alloc()
>  * adapt the code wherever using the channels
>  * remove the is_available flag, now "ch != NULL" is equivalent
> 
> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
> 
> ---
> 
> Cc: Liu Ying <victor.liu at nxp.com>
> 
> Changes in v3:
> - fix NULL pointer deref in .remove and remove is_available bool
> 
> Changes in v2: none
> ---
>  .../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c    | 27 +++++++++++-----------
>  1 file changed, 14 insertions(+), 13 deletions(-)

Reviewed-by: Liu Ying <victor.liu at nxp.com>


From dan.carpenter at linaro.org  Mon May 26 22:55:38 2025
From: dan.carpenter at linaro.org (Dan Carpenter)
Date: Tue, 27 May 2025 08:55:38 +0300
Subject: [PATCH next] wifi: mt76: mt7925: fix off by one in
 mt7925_mcu_hw_scan()
Message-ID: <aDVT2tPhG_8T0Qla@stanley.mountain>

The ssid->ssids[] and sreq->ssids[] arrays have MT7925_RNR_SCAN_MAX_BSSIDS
elements so this >= needs to be > to prevent an out of bounds access.

Fixes: 8284815ca161 ("wifi: mt76: mt7925: add RNR scan support for 6GHz")
Signed-off-by: Dan Carpenter <dan.carpenter at linaro.org>
---
Please review this one carefully.  I'm less sure about the second chunk.
Also maybe we should just delete this condition or check sreq->n_ssids
instead?

 drivers/net/wireless/mediatek/mt76/mt7925/mcu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
index b8542be0d945..16f3cc58a192 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
@@ -2866,7 +2866,7 @@ int mt7925_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
 	for (i = 0; i < sreq->n_ssids; i++) {
 		if (!sreq->ssids[i].ssid_len)
 			continue;
-		if (i > MT7925_RNR_SCAN_MAX_BSSIDS)
+		if (i >= MT7925_RNR_SCAN_MAX_BSSIDS)
 			break;
 
 		ssid->ssids[i].ssid_len = cpu_to_le32(sreq->ssids[i].ssid_len);
@@ -2883,7 +2883,7 @@ int mt7925_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
 		mt76_connac_mcu_build_rnr_scan_param(mdev, sreq);
 
 		for (j = 0; j < mdev->rnr.bssid_num; j++) {
-			if (j > MT7925_RNR_SCAN_MAX_BSSIDS)
+			if (j >= MT7925_RNR_SCAN_MAX_BSSIDS)
 				break;
 
 			tlv = mt76_connac_mcu_add_tlv(skb, UNI_SCAN_BSSID,
-- 
2.47.2



From ck.hu at mediatek.com  Mon May 26 23:24:13 2025
From: ck.hu at mediatek.com (=?utf-8?B?Q0sgSHUgKOiDoeS/iuWFiSk=?=)
Date: Tue, 27 May 2025 06:24:13 +0000
Subject: [PATCH 3/5] drm/mediatek: Add dvo driver for mt8196
In-Reply-To: <20250418065313.8972-4-bincai.liu@mediatek.com>
References: <20250418065313.8972-1-bincai.liu@mediatek.com>
	 <20250418065313.8972-4-bincai.liu@mediatek.com>
Message-ID: <e272210e5bcaf073fbbf4f1779c76d6f7a978d82.camel@mediatek.com>

On Fri, 2025-04-18 at 14:52 +0800, Bincai Liu wrote:
> Add code to support dvo for mt8196.

Say something about dvo.
I don't know what is dvo.

> 
> Signed-off-by: Bincai Liu <bincai.liu at mediatek.com>
> ---

[snip]

>  
> +enum mtk_dpi_golden_setting_level {
> +	MTK_DPI_FHD_60FPS_1920 = 0,
> +	MTK_DPI_FHD_60FPS_2180,
> +	MTK_DPI_FHD_60FPS_2400,
> +	MTK_DPI_FHD_60FPS_2520,
> +	MTK_DPI_FHD_90FPS,
> +	MTK_DPI_FHD_120FPS,
> +	MTK_DPI_WQHD_60FPS,
> +	MTK_DPI_WQHD_120FPS,
> +	MTK_DPI_8K_30FPS,
> +	MTK_DPI_GSL_MAX,
> +};
> +
> +enum mtk_dpi_type {
> +	MTK_DISP_DPI = 0,
> +	MTK_DSIP_DVO,
> +};
> +
> +struct mtk_dpi_gs_info {
> +	u32 dpi_buf_sodi_high;
> +	u32 dpi_buf_sodi_low;
> +};
> +
>  struct mtk_dpi {
>  	struct drm_encoder encoder;
>  	struct drm_bridge bridge;
> @@ -73,6 +96,7 @@ struct mtk_dpi {
>  	struct clk *engine_clk;
>  	struct clk *pixel_clk;
>  	struct clk *tvd_clk;
> +	struct clk *hf_fdpi_clk;
>  	int irq;
>  	struct drm_display_mode mode;
>  	const struct mtk_dpi_conf *conf;
> @@ -85,6 +109,7 @@ struct mtk_dpi {
>  	struct pinctrl_state *pins_dpi;
>  	u32 output_fmt;
>  	int refcount;
> +	enum mtk_dpi_golden_setting_level gs_level;

Drop this.

>  };
>  
>  static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b)
> @@ -171,6 +196,13 @@ struct mtk_dpi_conf {
>  	bool edge_cfg_in_mmsys;
>  	bool clocked_by_hdmi;
>  	bool output_1pixel;
> +	u32 out_np_sel;

Drop this.

> +	u8 dpi_ver;
> +};
> +
> +static struct mtk_dpi_gs_info mtk_dpi_gs[MTK_DPI_GSL_MAX] = {
> +	[MTK_DPI_FHD_60FPS_1920] = {6880, 511},
> +	[MTK_DPI_8K_30FPS] = {5255, 3899},
>  };

Drop this.

>  
>  static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
> @@ -208,6 +240,86 @@ static void mtk_dpi_disable(struct mtk_dpi *dpi)
>  	mtk_dpi_mask(dpi, DPI_EN, 0, EN);
>  }
>  
> +static void mtk_dpi_irq_enable(struct mtk_dpi *dpi)
> +{
> +	mtk_dpi_mask(dpi, DPI_INTEN, INT_VDE_END_EN, INT_VDE_END_EN);
> +}
> +
> +static void mtk_dpi_info_queue_start(struct mtk_dpi *dpi)
> +{
> +	mtk_dpi_mask(dpi, DPI_TGEN_INFOQ_LATENCY, 0,
> +		     INFOQ_START_LATENCY_MASK | INFOQ_END_LATENCY_MASK);
> +}
> +
> +static void mtk_dpi_buffer_ctrl(struct mtk_dpi *dpi)
> +{
> +	mtk_dpi_mask(dpi, DPI_BUF_CON0, DISP_BUF_EN, DISP_BUF_EN);
> +	mtk_dpi_mask(dpi, DPI_BUF_CON0, FIFO_UNDERFLOW_DONE_BLOCK, FIFO_UNDERFLOW_DONE_BLOCK);
> +}
> +
> +static void mtk_dpi_trailing_blank_setting(struct mtk_dpi *dpi)
> +{
> +	mtk_dpi_mask(dpi, DPI_TGEN_V_LAST_TRAILING_BLANK, 0x20, V_LAST_TRAILING_BLANK_MASK);
> +	mtk_dpi_mask(dpi, DPI_TGEN_OUTPUT_DELAY_LINE, 0x20, EXT_TG_DLY_LINE_MASK);
> +}
> +
> +static void mtk_dpi_get_gs_level(struct mtk_dpi *dpi)
> +{
> +	struct drm_display_mode *mode = &dpi->mode;
> +	enum mtk_dpi_golden_setting_level *gsl = &dpi->gs_level;
> +
> +	if (mode->hdisplay == 1920 && mode->vdisplay == 1080)
> +		*gsl = MTK_DPI_FHD_60FPS_1920;
> +	else
> +		*gsl = MTK_DPI_8K_30FPS;
> +}

Drop this function.

> +
> +static void mtk_dpi_golden_setting(struct mtk_dpi *dpi)

Change the function name to mtk_dpi_sod()

> +{
> +	struct mtk_dpi_gs_info *gs_info = NULL;
> +
> +	if (dpi->gs_level >= MTK_DPI_GSL_MAX) {
> +		dev_info(dpi->dev, "%s invalid gs_level %d\n",
> +			 __func__, dpi->gs_level);
> +		return;
> +	}
> +
> +	gs_info = &mtk_dpi_gs[dpi->gs_level];
> +
> +	mtk_dpi_mask(dpi, DPI_BUF_SODI_HIGHT, gs_info->dpi_buf_sodi_high, GENMASK(31, 0));
> +	mtk_dpi_mask(dpi, DPI_BUF_SODI_LOW, gs_info->dpi_buf_sodi_low, GENMASK(31, 0));

The golden setting has only two case, so drop the golden setting array.

	struct drm_display_mode *mode = &dpi->mode;

if (mode->hdisplay == 1920 && mode->vdisplay == 1080) {
	mtk_dpi_mask(dpi, DPI_BUF_SODI_HIGHT, 6880, GENMASK(31, 0));
	mtk_dpi_mask(dpi, DPI_BUF_SODI_LOW, 511, GENMASK(31, 0));
} else {
	mtk_dpi_mask(dpi, DPI_BUF_SODI_HIGHT, 5255, GENMASK(31, 0));
	mtk_dpi_mask(dpi, DPI_BUF_SODI_LOW, 3899, GENMASK(31, 0));
}

> +}
> +
> +static void mtk_dpi_shadow_ctrl(struct mtk_dpi *dpi)
> +{
> +	mtk_dpi_mask(dpi, DPI_SHADOW_CTRL, 0, BYPASS_SHADOW);
> +	mtk_dpi_mask(dpi, DPI_SHADOW_CTRL, FORCE_COMMIT, FORCE_COMMIT);
> +}
> +
> +static void mtk_dpi_config_timing(struct mtk_dpi *dpi,
> +				 struct mtk_dpi_sync_param *hsync,
> +				 struct mtk_dpi_sync_param *vsync)
> +{
> +	mtk_dpi_mask(dpi, DPI_TGEN_H0,
> +		     hsync->sync_width << HSYNC,
> +		     dpi->conf->dimension_mask << HSYNC);
> +	mtk_dpi_mask(dpi, DPI_TGEN_H0,
> +		     hsync->front_porch << DPI_HFP,
> +		     dpi->conf->dimension_mask << DPI_HFP);
> +	mtk_dpi_mask(dpi, DPI_TGEN_H1,
> +		     (hsync->back_porch + hsync->sync_width) << HSYNC2ACT,
> +		     dpi->conf->dimension_mask << HSYNC2ACT);
> +	mtk_dpi_mask(dpi, DPI_TGEN_V0,
> +		     vsync->sync_width << VSYNC,
> +		     dpi->conf->dimension_mask << VSYNC);
> +	mtk_dpi_mask(dpi, DPI_TGEN_V0,
> +		     vsync->front_porch << VFP,
> +		     dpi->conf->dimension_mask << VFP);
> +	mtk_dpi_mask(dpi, DPI_TGEN_V1,
> +		     (vsync->back_porch + vsync->sync_width) << VSYNC2ACT,
> +		     dpi->conf->dimension_mask << VSYNC2ACT);
> +}
> +
>  static void mtk_dpi_config_hsync(struct mtk_dpi *dpi,
>  				 struct mtk_dpi_sync_param *sync)
>  {
> @@ -296,10 +408,27 @@ static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter)
>  
>  static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height)
>  {
> -	mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE,
> -		     dpi->conf->hvsize_mask << HSIZE);
> -	mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE,
> -		     dpi->conf->hvsize_mask << VSIZE);
> +	if (dpi->conf->dpi_ver == MTK_DSIP_DVO) {
> +		mtk_dpi_mask(dpi, DPI_SRC_SIZE, width << SRC_HSIZE,
> +			dpi->conf->hvsize_mask << SRC_HSIZE);
> +		mtk_dpi_mask(dpi, DPI_SRC_SIZE, height << SRC_VSIZE,
> +			dpi->conf->hvsize_mask << SRC_VSIZE);
> +
> +		mtk_dpi_mask(dpi, DPI_PIC_SIZE, width << PIC_HSIZE,
> +			dpi->conf->hvsize_mask << PIC_HSIZE);
> +		mtk_dpi_mask(dpi, DPI_PIC_SIZE, height << PIC_VSIZE,
> +			dpi->conf->hvsize_mask << PIC_VSIZE);
> +
> +		mtk_dpi_mask(dpi, DPI_TGEN_H1, (width / dpi->conf->pixels_per_iter) << HACT,
> +			dpi->conf->hvsize_mask << HACT);
> +		mtk_dpi_mask(dpi, DPI_TGEN_V1, height << VACT,
> +			dpi->conf->hvsize_mask << VACT);
> +	} else {
> +		mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE,
> +			dpi->conf->hvsize_mask << HSIZE);
> +		mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE,
> +			dpi->conf->hvsize_mask << VSIZE);
> +	}
>  }
>  
>  static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi)
> @@ -501,6 +630,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi)
>  	clk_disable_unprepare(dpi->pixel_clk);
>  	clk_disable_unprepare(dpi->tvd_clk);
>  	clk_disable_unprepare(dpi->engine_clk);
> +	clk_disable_unprepare(dpi->hf_fdpi_clk);
>  }
>  
>  static int mtk_dpi_power_on(struct mtk_dpi *dpi)
> @@ -528,8 +658,16 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
>  		goto err_pixel;
>  	}
>  
> +	ret = clk_prepare_enable(dpi->hf_fdpi_clk);
> +	if (ret) {
> +		dev_err(dpi->dev, "Failed to enable hf_fdpi_clk clock: %d\n", ret);
> +		goto err_hf_fdpi_clk;
> +	}
> +
>  	return 0;
>  
> +err_hf_fdpi_clk:
> +	clk_disable_unprepare(dpi->hf_fdpi_clk);

You fail to prepare enable dpi->hf_fdpi_clk,
so you don't need to disable unprepare it.

clk_disable_unprepare(dpi->pixel_clk);

>  err_pixel:
>  	clk_disable_unprepare(dpi->tvd_clk);
>  err_engine:
> @@ -610,7 +748,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
>  			    MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
>  	dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ?
>  			    MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
> -
>  	/*
>  	 * Depending on the IP version, we may output a different amount of
>  	 * pixels for each iteration: divide the clock by this number and
> @@ -643,14 +780,18 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
>  	}
>  	mtk_dpi_sw_reset(dpi, true);
>  	mtk_dpi_config_pol(dpi, &dpi_pol);
> +	if (dpi->conf->dpi_ver == MTK_DSIP_DVO) {
> +		mtk_dpi_irq_enable(dpi);

This driver has no irq handler, so drop this.

> +		mtk_dpi_config_timing(dpi, &hsync, &vsync_lodd);
> +	} else {
> +		mtk_dpi_config_hsync(dpi, &hsync);
> +		mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd);
> +		mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd);
> +		mtk_dpi_config_vsync_leven(dpi, &vsync_leven);
> +		mtk_dpi_config_vsync_reven(dpi, &vsync_reven);
> +		mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK));
> +	}
>  
> -	mtk_dpi_config_hsync(dpi, &hsync);
> -	mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd);
> -	mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd);
> -	mtk_dpi_config_vsync_leven(dpi, &vsync_leven);
> -	mtk_dpi_config_vsync_reven(dpi, &vsync_reven);
> -
> -	mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK));
>  	mtk_dpi_config_interface(dpi, !!(vm.flags &
>  					 DISPLAY_FLAGS_INTERLACED));
>  	if (vm.flags & DISPLAY_FLAGS_INTERLACED)
> @@ -658,26 +799,41 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
>  	else
>  		mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive);
>  
> -	mtk_dpi_config_channel_limit(dpi);
> -	mtk_dpi_config_bit_num(dpi, dpi->bit_num);
> -	mtk_dpi_config_channel_swap(dpi, dpi->channel_swap);
> -	mtk_dpi_config_color_format(dpi, dpi->color_format);
> -	if (dpi->conf->support_direct_pin) {
> -		mtk_dpi_config_yc_map(dpi, dpi->yc_map);
> -		mtk_dpi_config_2n_h_fre(dpi);
> -
> -		/* DPI can connect to either an external bridge or the internal HDMI encoder */
> -		if (dpi->conf->output_1pixel)
> -			mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN);
> -		else
> -			mtk_dpi_dual_edge(dpi);
> -
> -		mtk_dpi_config_disable_edge(dpi);
> -	}
> -	if (dpi->conf->input_2p_en_bit) {
> -		mtk_dpi_mask(dpi, DPI_CON, dpi->conf->input_2p_en_bit,
> -			     dpi->conf->input_2p_en_bit);
> +	if (dpi->conf->dpi_ver == MTK_DSIP_DVO) {
> +		mtk_dpi_info_queue_start(dpi);
> +		mtk_dpi_buffer_ctrl(dpi);
> +		mtk_dpi_trailing_blank_setting(dpi);
> +		mtk_dpi_get_gs_level(dpi);
> +		mtk_dpi_golden_setting(dpi);
> +		mtk_dpi_shadow_ctrl(dpi);
> +		mtk_dpi_mask(dpi, DPI_OUTPUT_SET, dpi->conf->out_np_sel, OUT_NP_SEL);

Up to now, only mt8196 dvo set DPI_OUTPUT_SET, so it's not necessary to have a private data to store out_np_sel.

#define DPI_OUTPUT_SET		0x18
#define DPI_OUTPUT_SET_XXX		2
#define OUT_NP_SEL			GENMASK(1, 0)

mtk_dpi_mask(dpi, DPI_OUTPUT_SET, DPI_OUTPUT_SET_XXX, OUT_NP_SEL);

> +	} else {
> +		mtk_dpi_config_channel_limit(dpi);
> +		mtk_dpi_config_bit_num(dpi, dpi->bit_num);
> +		mtk_dpi_config_channel_swap(dpi, dpi->channel_swap);
> +		mtk_dpi_config_color_format(dpi, dpi->color_format);
> +		if (dpi->conf->support_direct_pin) {
> +			mtk_dpi_config_yc_map(dpi, dpi->yc_map);
> +			mtk_dpi_config_2n_h_fre(dpi);
> +
> +			/*
> +			 * DPI can connect to either an external bridge
> +			 * or the internal HDMI encoder
> +			 */
> +			if (dpi->conf->output_1pixel)
> +				mtk_dpi_mask(dpi, DPI_CON,
> +						  DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN);
> +			else
> +				mtk_dpi_dual_edge(dpi);
> +
> +			mtk_dpi_config_disable_edge(dpi);
> +		}
> +		if (dpi->conf->input_2p_en_bit) {
> +			mtk_dpi_mask(dpi, DPI_CON, dpi->conf->input_2p_en_bit,
> +				dpi->conf->input_2p_en_bit);
> +		}
>  	}
> +
>  	mtk_dpi_sw_reset(dpi, false);
>  
>  	return 0;
> @@ -700,7 +856,7 @@ static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
>  	}
>  
>  	output_fmts = kcalloc(dpi->conf->num_output_fmts, sizeof(*output_fmts),
> -			     GFP_KERNEL);
> +			      GFP_KERNEL);

This is not related to the title. Separate this to a refinement patch.

>  	if (!output_fmts)
>  		return NULL;
>  
> @@ -1173,6 +1329,20 @@ static const struct mtk_dpi_conf mt8195_dpintf_conf = {
>  	.input_2p_en_bit = DPINTF_INPUT_2P_EN,
>  };
>  
> +static const struct mtk_dpi_conf mt8196_conf = {
> +	.dpi_factor = dpi_factor_mt8195_dp_intf,
> +	.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf),
> +	.out_np_sel = 0x2,
> +	.reg_h_fre_con = 0xb0,
> +	.max_clock_khz = 1330000,
> +	.output_fmts = mt8195_output_fmts,
> +	.num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
> +	.pixels_per_iter = 4,
> +	.dimension_mask = DPINTF_HPW_MASK,
> +	.hvsize_mask = PIC_HSIZE_MASK,
> +	.dpi_ver = MTK_DSIP_DVO,
> +};
> +
>  static int mtk_dpi_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> @@ -1227,6 +1397,11 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>  		return dev_err_probe(dev, PTR_ERR(dpi->tvd_clk),
>  				     "Failed to get tvdpll clock\n");
>  
> +	dpi->hf_fdpi_clk = devm_clk_get_optional(dev, "hf_fdvo_clk");
> +	if (IS_ERR(dpi->hf_fdpi_clk))
> +		return dev_err_probe(dev, PTR_ERR(dpi->hf_fdpi_clk),
> +				     "Failed to get hf_fdpi_clk clock\n");
> +
>  	dpi->irq = platform_get_irq(pdev, 0);
>  	if (dpi->irq < 0)
>  		return dpi->irq;
> @@ -1262,6 +1437,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
>  	{ .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf },
>  	{ .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf },
>  	{ .compatible = "mediatek,mt8195-dpi", .data = &mt8195_conf },
> +	{ .compatible = "mediatek,mt8196-edp-dvo", .data = &mt8196_conf },
>  	{ /* sentinel */ },
>  };
>  MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index 23eeefce8fd2..3e2a64c2bca0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -16,6 +16,7 @@
>  #define INT_VSYNC_EN			BIT(0)
>  #define INT_VDE_EN			BIT(1)
>  #define INT_UNDERFLOW_EN		BIT(2)
> +#define INT_VDE_END_EN			BIT(4)
>  
>  #define DPI_INTSTA		0x0C
>  #define INT_VSYNC_STA			BIT(0)
> @@ -240,6 +241,71 @@
>  #define MATRIX_SEL_RGB_TO_JPEG		0
>  #define MATRIX_SEL_RGB_TO_BT601		2
>  
> +#define DPI_TGEN_INFOQ_LATENCY	0x80
> +#define INFOQ_START_LATENCY		0
> +#define INFOQ_START_LATENCY_MASK	(0xffff << 0)
> +#define INFOQ_END_LATENCY		16
> +#define INFOQ_END_LATENCY_MASK		(0xffff << 16)
> +
> +#define DPI_BUF_CON0		0x220
> +#define DISP_BUF_EN			BIT(0)
> +#define FIFO_UNDERFLOW_DONE_BLOCK	BIT(4)
> +
> +#define DPI_TGEN_V_LAST_TRAILING_BLANK	0x6c
> +#define V_LAST_TRAILING_BLANK			0
> +#define V_LAST_TRAILING_BLANK_MASK		(0xffff << 0)
> +
> +#define DPI_TGEN_OUTPUT_DELAY_LINE	0x7c
> +#define EXT_TG_DLY_LINE				0
> +#define EXT_TG_DLY_LINE_MASK			(0xffff << 0)
> +
> +#define DPI_SHADOW_CTRL			0x190
> +#define FORCE_COMMIT				BIT(0)
> +#define BYPASS_SHADOW				BIT(1)
> +#define READ_WRK_REG				BIT(2)
> +
> +#define DPI_BUF_SODI_HIGHT		0x230
> +#define DPI_BUF_SODI_LOW		0x234
> +
> +#define DPI_OUTPUT_SET		0x18
> +#define OUT_NP_SEL			(0x3 << 0)
> +
> +#define DPI_SRC_SIZE		0x20
> +#define SRC_HSIZE			0
> +#define SRC_HSIZE_MASK			(0xffff << 0)
> +#define SRC_VSIZE			16
> +#define SRC_VSIZE_MASK			(0xffff << 16)
> +
> +#define DPI_PIC_SIZE		0x24
> +#define PIC_HSIZE			0
> +#define PIC_HSIZE_MASK			(0xffff << 0)
> +#define PIC_VSIZE			16
> +#define PIC_VSIZE_MASK			(0xffff << 16)
> +
> +#define DPI_TGEN_H0		0x50
> +#define DPI_HFP				0
> +#define DPI_HFP_MASK			(0xffff << 0)
> +#define HSYNC				16
> +#define HSYNC_MASK			(0xffff << 16)
> +
> +#define DPI_TGEN_H1		0x54
> +#define HSYNC2ACT			0
> +#define HSYNC2ACT_MASK			(0xffff << 0)
> +#define HACT				16
> +#define HACT_MASK			(0xffff << 16)
> +
> +#define DPI_TGEN_V0		0x58
> +#define VFP				0
> +#define VFP_MASK			(0xffff << 0)
> +#define VSYNC				16
> +#define VSYNC_MASK			(0xffff << 16)
> +
> +#define DPI_TGEN_V1		0x5c
> +#define VSYNC2ACT			0
> +#define VSYNC2ACT_MASK			(0xffff << 0)
> +#define VACT				16
> +#define VACT_MASK			(0xffff << 16)
> +
>  #define DPI_PATTERN0		0xf00
>  #define DPI_PAT_EN			BIT(0)
>  #define DPI_PAT_SEL			GENMASK(6, 4)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 74158b9d6503..870d97c023ed 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -830,6 +830,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DSI },
>  	{ .compatible = "mediatek,mt8188-dsi",
>  	  .data = (void *)MTK_DSI },
> +	{ .compatible = "mediatek,mt8196-edp-dvo",
> +	  .data = (void *)MTK_DVO },
>  	{ }
>  };
>  
> @@ -1176,7 +1178,8 @@ static int mtk_drm_probe(struct platform_device *pdev)
>  		    comp_type == MTK_DISP_RDMA ||
>  		    comp_type == MTK_DP_INTF ||
>  		    comp_type == MTK_DPI ||
> -		    comp_type == MTK_DSI) {
> +		    comp_type == MTK_DSI ||
> +		    comp_type == MTK_DVO) {

DVO is a kind of DPI, so why not reuse DPI and drop DVO?

Regards,
CK

>  			dev_info(dev, "Adding component match for %pOF\n",
>  				 node);
>  			drm_of_component_match_add(dev, &match, component_compare_of,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 675cdc90a440..6d2796148813 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -79,6 +79,7 @@ extern struct platform_driver mtk_disp_ovl_driver;
>  extern struct platform_driver mtk_disp_rdma_driver;
>  extern struct platform_driver mtk_dpi_driver;
>  extern struct platform_driver mtk_dsi_driver;
> +extern struct platform_driver mtk_dvo_driver;
>  extern struct platform_driver mtk_ethdr_driver;
>  extern struct platform_driver mtk_mdp_rdma_driver;
>  extern struct platform_driver mtk_padding_driver;


From luca.ceresoli at bootlin.com  Tue May 27 02:27:25 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Tue, 27 May 2025 11:27:25 +0200
Subject: [PATCH v3 02/22] drm: convert many bridge drivers from
 devm_kzalloc() to devm_drm_bridge_alloc() API
In-Reply-To: <CAHCN7xLPxmaZcOESvaU2W1gX4o1z-1A_atq4jZdrpAH5Wmht+g@mail.gmail.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
	<20250509-drm-bridge-convert-to-alloc-api-v3-2-b8bc1f16d7aa@bootlin.com>
	<CAHCN7xLPxmaZcOESvaU2W1gX4o1z-1A_atq4jZdrpAH5Wmht+g@mail.gmail.com>
Message-ID: <20250527112725.3736e415@booty>

Hello Adam,

On Sun, 25 May 2025 14:40:46 -0500
Adam Ford <aford173 at gmail.com> wrote:

> For: imx8mp-hdmi-pvi.c and adv7511_drv.c
> 
> Tested-by: Adam Ford <aford173 at gmail.com> #imx8mp-beacon-kit

Thanks for your testing, on the v1 as well!

Sadly your Tested-by tag won't be in the commit because the patch had
already been applied, but it is useful per se, and in the records
anyway.

Kind regards,
Luca

-- 
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


From luca.ceresoli at bootlin.com  Tue May 27 03:21:22 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Tue, 27 May 2025 12:21:22 +0200
Subject: (subset) [PATCH v3 00/22] drm: convert all bridges to
 devm_drm_bridge_alloc()
In-Reply-To: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
References: <20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa@bootlin.com>
Message-ID: <174834128290.138143.12049855352148769197.b4-ty@bootlin.com>


On Fri, 09 May 2025 15:53:26 +0200, Luca Ceresoli wrote:
> devm_drm_bridge_alloc() [0] is the new API to allocate and initialize a DRM
> bridge, and the only one supported from now on. It is the first milestone
> towards removal of bridges from a still existing DRM pipeline without
> use-after-free.
> 
> The steps in the grand plan [1] are:
> 
> [...]

Applied, thanks!

[18/22] drm/bridge: imx8qxp-pixel-combiner: convert to devm_drm_bridge_alloc() API
        commit: 99764593528f9e0ee9509f9e4a4eb21db99d0681

Best regards,
-- 
Luca Ceresoli <luca.ceresoli at bootlin.com>



From ck.hu at mediatek.com  Tue May 27 03:24:09 2025
From: ck.hu at mediatek.com (=?utf-8?B?Q0sgSHUgKOiDoeS/iuWFiSk=?=)
Date: Tue, 27 May 2025 10:24:09 +0000
Subject: [PATCH 4/5] drm/mediatek: Add eDP driver for mt8196
In-Reply-To: <20250418065313.8972-5-bincai.liu@mediatek.com>
References: <20250418065313.8972-1-bincai.liu@mediatek.com>
	 <20250418065313.8972-5-bincai.liu@mediatek.com>
Message-ID: <5f99e6d96e54b451b4fb261c2cd5790b8949f554.camel@mediatek.com>

On Fri, 2025-04-18 at 14:52 +0800, Bincai Liu wrote:
> Add code to support eDP 1.4 driver for mt8196.
> 
> Signed-off-by: Bincai Liu <bincai.liu at mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dp.c     | 484 ++++++++++++++++++++++----
>  drivers/gpu/drm/mediatek/mtk_dp_reg.h | 126 +++++++
>  2 files changed, 550 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
> index b2408abb9d49..159ab5ebb9d2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> @@ -35,6 +35,9 @@
>  
>  #include "mtk_dp_reg.h"
>  
> +#define EDP_VIDEO_UNMUTE		0x22
> +#define EDP_VIDEO_UNMUTE_VAL		0xfefd
> +#define MTK_SIP_DP_CONTROL		(0x82000523 | 0x40000000)
>  #define MTK_DP_SIP_CONTROL_AARCH32	MTK_SIP_SMC_CMD(0x523)
>  #define MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE	(BIT(0) | BIT(5))
>  #define MTK_DP_SIP_ATF_VIDEO_UNMUTE	BIT(5)
> @@ -51,6 +54,7 @@
>  #define MTK_DP_TRAIN_DOWNSCALE_RETRY 10
>  #define MTK_DP_VERSION 0x11
>  #define MTK_DP_SDP_AUI 0x4
> +#define EDP_REINIT_TIMES 4
>  
>  enum {
>  	MTK_DP_CAL_GLB_BIAS_TRIM = 0,
> @@ -102,6 +106,7 @@ struct mtk_dp {
>  	bool enabled;
>  	bool need_debounce;
>  	int irq;
> +	int swing_value;
>  	u8 max_lanes;
>  	u8 max_linkrate;
>  	u8 rx_cap[DP_RECEIVER_CAP_SIZE];
> @@ -110,6 +115,8 @@ struct mtk_dp {
>  	/* irq_thread_lock is used to protect irq_thread_handle */
>  	spinlock_t irq_thread_lock;
>  
> +	struct clk *power_clk;
> +
>  	struct device *dev;
>  	struct drm_bridge bridge;
>  	struct drm_bridge *next_bridge;
> @@ -124,6 +131,7 @@ struct mtk_dp {
>  	struct platform_device *phy_dev;
>  	struct phy *phy;
>  	struct regmap *regs;
> +	struct regmap *phy_regs;
>  	struct timer_list debounce_timer;
>  
>  	/* For audio */
> @@ -134,6 +142,9 @@ struct mtk_dp {
>  	struct device *codec_dev;
>  	/* protect the plugged_cb as it's used in both bridge ops and audio */
>  	struct mutex update_plugged_status_lock;
> +	/* For edp power control */
> +	void __iomem *pwr_regs;
> +	u32 retry_times;
>  };
>  
>  struct mtk_dp_data {
> @@ -143,6 +154,7 @@ struct mtk_dp_data {
>  	bool audio_supported;
>  	bool audio_pkt_in_hblank_area;
>  	u16 audio_m_div2_bit;
> +	u32 edp_ver;
>  };
>  
>  static const struct mtk_dp_efuse_fmt mt8188_dp_efuse_fmt[MTK_DP_CAL_MAX] = {
> @@ -402,6 +414,16 @@ static const struct regmap_config mtk_dp_regmap_config = {
>  	.name = "mtk-dp-registers",
>  };
>  
> +static const struct regmap_config mtk_edp_phy_regmap_config = {
> +	.reg_bits = 32,
> +	.val_bits = 32,
> +	.reg_stride = 4,
> +	.max_register = SEC_OFFSET + 0x90,
> +	.name = "mtk-edp-phy-registers",
> +};
> +
> +static int mtk_dp_poweron(struct mtk_dp *mtk_dp);
> +
>  static struct mtk_dp *mtk_dp_from_bridge(struct drm_bridge *b)
>  {
>  	return container_of(b, struct mtk_dp, bridge);
> @@ -459,6 +481,26 @@ static void mtk_dp_bulk_16bit_write(struct mtk_dp *mtk_dp, u32 offset, u8 *buf,
>  	}
>  }
>  
> +static void mtk_edp_pm_ctl(struct mtk_dp *mtk_dp, bool enable)
> +{
> +	/* DISP_EDPTX_PWR_CON udelay 10us to ensure that the power state is stable */
> +	udelay(10);
> +	if (enable) {
> +		/* Enable subsys clock, just set bit4 to 0 */
> +		writel(readl(mtk_dp->pwr_regs) & ~DISP_EDPTX_PWR_CLK_DIS, mtk_dp->pwr_regs);
> +		udelay(1);
> +		/* Subsys power-on reset, firstly set bit0 to 0 and then set bit0 to 1 */
> +		writel(readl(mtk_dp->pwr_regs) & ~DISP_EDPTX_PWR_RST_B, mtk_dp->pwr_regs);
> +		udelay(1);
> +		writel(readl(mtk_dp->pwr_regs) | DISP_EDPTX_PWR_RST_B, mtk_dp->pwr_regs);
> +	} else {
> +		writel(readl(mtk_dp->pwr_regs) & ~DISP_EDPTX_PWR_RST_B, mtk_dp->pwr_regs);
> +		udelay(1);
> +		writel(readl(mtk_dp->pwr_regs) | DISP_EDPTX_PWR_CLK_DIS, mtk_dp->pwr_regs);
> +	}
> +	udelay(10);
> +}
> +
>  static void mtk_dp_msa_bypass_enable(struct mtk_dp *mtk_dp, bool enable)
>  {
>  	u32 mask = HTOTAL_SEL_DP_ENC0_P0 | VTOTAL_SEL_DP_ENC0_P0 |
> @@ -514,9 +556,14 @@ static void mtk_dp_set_msa(struct mtk_dp *mtk_dp)
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_315C,
>  			   vm->hsync_len,
>  			   PGEN_HSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK);
> -	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3160,
> -			   vm->hback_porch + vm->hsync_len,
> -			   PGEN_HFDE_START_DP_ENC0_P0_MASK);
> +	if (mtk_dp->data->edp_ver)

I would like a name about what it does rather than a version number.
It seem this is to add horizontal front porch to PGEN_HFDE_START_DP_ENC0_P0_MASK.
Maybe the name should be

if (mtk_dp->data->xxx_hfp) {
 

> +		mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3160,
> +				   vm->hback_porch + vm->hsync_len + vm->hfront_porch,
> +				   PGEN_HFDE_START_DP_ENC0_P0_MASK);
> +	else
> +		mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3160,
> +				   vm->hback_porch + vm->hsync_len,
> +				   PGEN_HFDE_START_DP_ENC0_P0_MASK);
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3164,
>  			   vm->hactive,
>  			   PGEN_HFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK);
> @@ -531,9 +578,14 @@ static void mtk_dp_set_msa(struct mtk_dp *mtk_dp)
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3170,
>  			   vm->vsync_len,
>  			   PGEN_VSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK);
> -	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3174,
> -			   vm->vback_porch + vm->vsync_len,
> -			   PGEN_VFDE_START_DP_ENC0_P0_MASK);
> +	if (mtk_dp->data->edp_ver)

I would like a name about what it does rather than a version number.
It seem this is to add vertical front porch to PGEN_VFDE_START_DP_ENC0_P0_MASK.
Maybe the name should be

if (mtk_dp->data->xxx_vfp) {

> +		mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3174,
> +				   vm->vback_porch + vm->vsync_len +  vm->vfront_porch,
> +				   PGEN_VFDE_START_DP_ENC0_P0_MASK);
> +	else
> +		mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3174,
> +				   vm->vback_porch + vm->vsync_len,
> +				   PGEN_VFDE_START_DP_ENC0_P0_MASK);
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3178,
>  			   vm->vactive,
>  			   PGEN_VFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK);
> @@ -543,7 +595,7 @@ static int mtk_dp_set_color_format(struct mtk_dp *mtk_dp,
>  				   enum dp_pixelformat color_format)
>  {
>  	u32 val;
> -	u32 misc0_color;
> +	u32 misc0_color = 0;

Drop this.

>  
>  	switch (color_format) {
>  	case DP_PIXELFORMAT_YUV422:
> @@ -554,6 +606,9 @@ static int mtk_dp_set_color_format(struct mtk_dp *mtk_dp,
>  		val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB;
>  		misc0_color = DP_COLOR_FORMAT_RGB;
>  		break;
> +	case DP_PIXELFORMAT_YUV420:
> +		val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR420;


After you drop misc0_color = 0, then add below statement.
But I feel it's weird that color format is RGB.

		misc0_color = DP_COLOR_FORMAT_RGB;

This register also exist in mt8188 and mt8195 edp, so this modification is not only about mt8196.
Separate this to an independent patch.

> +		break;
>  	default:
>  		drm_warn(mtk_dp->drm_dev, "Unsupported color format: %d\n",
>  			 color_format);
> @@ -612,7 +667,8 @@ static void mtk_dp_setup_encoder(struct mtk_dp *mtk_dp)
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3364,
>  			   FIFO_READ_START_POINT_DP_ENC1_P0_VAL << 12,
>  			   FIFO_READ_START_POINT_DP_ENC1_P0_MASK);
> -	mtk_dp_write(mtk_dp, MTK_DP_ENC1_P0_3368, DP_ENC1_P0_3368_VAL);
> +	if (!mtk_dp->data->edp_ver)

I would like a name about what it does rather than a version number.
Give it a meaningful name.

> +		mtk_dp_write(mtk_dp, MTK_DP_ENC1_P0_3368, DP_ENC1_P0_3368_VAL);
>  }
>  
>  static void mtk_dp_pg_enable(struct mtk_dp *mtk_dp, bool enable)
> @@ -972,8 +1028,8 @@ static void mtk_dp_set_swing_pre_emphasis(struct mtk_dp *mtk_dp, int lane_num,
>  	u32 lane_shift = lane_num * DP_TX1_VOLT_SWING_SHIFT;
>  
>  	dev_dbg(mtk_dp->dev,
> -		"link training: swing_val = 0x%x, pre-emphasis = 0x%x\n",
> -		swing_val, preemphasis);
> +		"link training: swing_val = 0x%x, pre-emphasis = 0x%x lane_num = %d\n",
> +		swing_val, preemphasis, lane_num);
>  
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_SWING_EMP,
>  			   swing_val << (DP_TX0_VOLT_SWING_SHIFT + lane_shift),
> @@ -981,6 +1037,28 @@ static void mtk_dp_set_swing_pre_emphasis(struct mtk_dp *mtk_dp, int lane_num,
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_SWING_EMP,
>  			   preemphasis << (DP_TX0_PRE_EMPH_SHIFT + lane_shift),
>  			   DP_TX0_PRE_EMPH_MASK << lane_shift);
> +	if (mtk_dp->data->edp_ver && mtk_dp->phy_regs) {
> +		/* set swing and pre */
> +		switch (lane_num) {
> +		case 0:
> +		case 1:
> +		case 2:
> +		case 3:
> +			regmap_update_bits(mtk_dp->phy_regs,
> +					   PHYD_DIG_DRV_FORCE_LANE(lane_num),
> +					   EDP_TX_LN_VOLT_SWING_VAL_FLDMASK |
> +					   EDP_TX_LN_PRE_EMPH_VAL_FLDMASK,
> +					   swing_val << 1 |
> +					   preemphasis << 3);

In struct phy_ops {}, it has configure member, and you could pass lanes and pre in that interface.
I'm not sure swing_val could be passed by that interface or not.
If not, maybe add new parameter for swing_val.

> +			break;
> +		default:
> +			break;
> +		}
> +		if (preemphasis != 0)
> +			mtk_dp_update_bits(mtk_dp, RG_DSI_DEM_EN,
> +					   DSI_DE_EMPHASIS_ENABLE,
> +					   DSI_DE_EMPHASIS_ENABLE);
> +	}
>  }
>  
>  static void mtk_dp_reset_swing_pre_emphasis(struct mtk_dp *mtk_dp)
> @@ -1039,6 +1117,44 @@ static void mtk_dp_hwirq_enable(struct mtk_dp *mtk_dp, bool enable)
>  
>  static void mtk_dp_initialize_settings(struct mtk_dp *mtk_dp)
>  {
> +	if (mtk_dp->data->edp_ver) {

I would like a name about what it does rather than a version number.
Give it a meaningful name.

> +		mtk_dp_update_bits(mtk_dp, REG_3F04_DP_ENC_P0_3, 0,
> +				   FRAME_START_MARKER_0_DP_ENC_P0_3_MASK);
> +		mtk_dp_update_bits(mtk_dp, REG_3F08_DP_ENC_P0_3,
> +				   FRAME_START_MARKER_1_DP_ENC_P0_3,
> +				   FRAME_START_MARKER_1_DP_ENC_P0_3_MASK);
> +		mtk_dp_update_bits(mtk_dp, REG_3F0C_DP_ENC_P0_3,
> +				   FRAME_END_MARKER_0_DP_ENC_P0_3,
> +				   FRAME_END_MARKER_0_DP_ENC_P0_3_MASK);
> +		mtk_dp_update_bits(mtk_dp, REG_3F10_DP_ENC_P0_3,
> +				   FRAME_END_MARKER_1_DP_ENC_P0_3,
> +				   FRAME_END_MARKER_1_DP_ENC_P0_3_MASK);
> +
> +		mtk_dp_update_bits(mtk_dp, REG_33C0_DP_ENCODER1_P0, 0,
> +				   SDP_TESTBUS_SEL_DP_ENC_MASK);
> +		mtk_dp_update_bits(mtk_dp, REG_33C0_DP_ENCODER1_P0,
> +				   SDP_TESTBUS_SEL_BIT4_DP_ENC,
> +				   SDP_TESTBUS_SEL_BIT4_DP_ENC_MASK);
> +		mtk_dp_update_bits(mtk_dp, REG_33C4_DP_ENCODER1_P0,
> +				   DP_TX_ENCODER_TESTBUS_SEL_DP_ENC,
> +				   DP_TX_ENCODER_TESTBUS_SEL_DP_ENC_MASK);
> +		mtk_dp_update_bits(mtk_dp, REG_3F28_DP_ENC_P0_3,
> +				   DP_TX_SDP_PSR_AS_TESTBUS,
> +				   DP_TX_SDP_PSR_AS_TESTBUS_MASK);
> +		mtk_dp_update_bits(mtk_dp, DP_TX_TOP_RESET_AND_PROBE,
> +				   RG_SW_RST,
> +				   RG_SW_RST_MASK);
> +		mtk_dp_update_bits(mtk_dp, DP_TX_TOP_RESET_AND_PROBE,
> +				   RG_PROBE_LOW_SEL,
> +				   RG_PROBE_LOW_SEL_MASK);
> +		mtk_dp_update_bits(mtk_dp, DP_TX_TOP_RESET_AND_PROBE,
> +				   RG_PROBE_LOW_HIGH_SWAP,
> +				   RG_PROBE_LOW_HIGH_SWAP_MASK);
> +
> +		mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_IRQ_MASK,
> +				   ENCODER_IRQ_MSK | TRANS_IRQ_MSK,
> +				   ENCODER_IRQ_MSK | TRANS_IRQ_MSK);
> +	}
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_342C,
>  			   XTAL_FREQ_DP_TRANS_P0_DEFAULT,
>  			   XTAL_FREQ_DP_TRANS_P0_MASK);
> @@ -1057,27 +1173,34 @@ static void mtk_dp_initialize_settings(struct mtk_dp *mtk_dp)
>  static void mtk_dp_initialize_hpd_detect_settings(struct mtk_dp *mtk_dp)
>  {
>  	u32 val;
> -	/* Debounce threshold */
> -	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,
> -			   8, HPD_DEB_THD_DP_TRANS_P0_MASK);
>  
> -	val = (HPD_INT_THD_DP_TRANS_P0_LOWER_500US |
> -	       HPD_INT_THD_DP_TRANS_P0_UPPER_1100US) << 4;
> -	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,
> -			   val, HPD_INT_THD_DP_TRANS_P0_MASK);
> +	if (mtk_dp->data->edp_ver) {

I would like a name about what it does rather than a version number.
Give it a meaningful name.

> +		mtk_dp_update_bits(mtk_dp, REG_364C_AUX_TX_P0,
> +				   HPD_INT_THD_FLDMASK_VAL << 4,
> +				   HPD_INT_THD_FLDMASK);
> +	} else {
> +		/* Debounce threshold */
> +		mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,
> +				   8, HPD_DEB_THD_DP_TRANS_P0_MASK);
>  
> -	/*
> -	 * Connect threshold 1.5ms + 5 x 0.1ms = 2ms
> -	 * Disconnect threshold 1.5ms + 5 x 0.1ms = 2ms
> -	 */
> -	val = (5 << 8) | (5 << 12);
> -	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,
> -			   val,
> -			   HPD_DISC_THD_DP_TRANS_P0_MASK |
> -			   HPD_CONN_THD_DP_TRANS_P0_MASK);
> -	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3430,
> -			   HPD_INT_THD_ECO_DP_TRANS_P0_HIGH_BOUND_EXT,
> -			   HPD_INT_THD_ECO_DP_TRANS_P0_MASK);
> +		val = (HPD_INT_THD_DP_TRANS_P0_LOWER_500US |
> +		       HPD_INT_THD_DP_TRANS_P0_UPPER_1100US) << 4;
> +		mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,
> +				   val, HPD_INT_THD_DP_TRANS_P0_MASK);
> +
> +		/*
> +		 * Connect threshold 1.5ms + 5 x 0.1ms = 2ms
> +		 * Disconnect threshold 1.5ms + 5 x 0.1ms = 2ms
> +		 */
> +		val = (5 << 8) | (5 << 12);
> +		mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,
> +				   val,
> +				   HPD_DISC_THD_DP_TRANS_P0_MASK |
> +				   HPD_CONN_THD_DP_TRANS_P0_MASK);
> +		mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3430,
> +				   HPD_INT_THD_ECO_DP_TRANS_P0_HIGH_BOUND_EXT,
> +				   HPD_INT_THD_ECO_DP_TRANS_P0_MASK);
> +	}
>  }
>  
>  static void mtk_dp_initialize_aux_settings(struct mtk_dp *mtk_dp)
> @@ -1088,6 +1211,10 @@ static void mtk_dp_initialize_aux_settings(struct mtk_dp *mtk_dp)
>  			   AUX_TIMEOUT_THR_AUX_TX_P0_MASK);
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3658,
>  			   0, AUX_TX_OV_EN_AUX_TX_P0_MASK);
> +	if (mtk_dp->data->edp_ver)

I would like a name about what it does rather than a version number.
Give it a meaningful name.

> +		mtk_dp_update_bits(mtk_dp, REG_36A0_AUX_TX_P0,
> +				   DP_TX_INIT_MASK_15_TO_2,
> +				   DP_TX_INIT_MASK_15_TO_2_MASK);
>  	/* 25 for 26M */
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3634,
>  			   AUX_TX_OVER_SAMPLE_RATE_FOR_26M << 8,
> @@ -1104,6 +1231,46 @@ static void mtk_dp_initialize_aux_settings(struct mtk_dp *mtk_dp)
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3690,
>  			   RX_REPLY_COMPLETE_MODE_AUX_TX_P0,
>  			   RX_REPLY_COMPLETE_MODE_AUX_TX_P0);
> +
> +	if (mtk_dp->data->edp_ver) {

Ditto.

> +		/*Con Thd = 1.5ms+Vx0.1ms*/
> +		mtk_dp_update_bits(mtk_dp, REG_367C_AUX_TX_P0,
> +				   HPD_CONN_THD_AUX_TX_P0_FLDMASK_POS << 6,
> +				   HPD_CONN_THD_AUX_TX_P0_FLDMASK);
> +		/*DisCon Thd = 1.5ms+Vx0.1ms*/
> +		mtk_dp_update_bits(mtk_dp, REG_37A0_AUX_TX_P0,
> +				   HPD_DISC_THD_AUX_TX_P0_FLDMASK_POS << 4,
> +				   HPD_DISC_THD_AUX_TX_P0_FLDMASK);
> +		mtk_dp_update_bits(mtk_dp, REG_3FF8_DP_ENC_P0_3,
> +				   XTAL_FREQ_FOR_PSR_DP_ENC_P0_3_VALUE << 9,
> +				   XTAL_FREQ_FOR_PSR_DP_ENC_P0_3_MASK);
> +		mtk_dp_update_bits(mtk_dp, REG_366C_AUX_TX_P0,
> +				   XTAL_FREQ_DP_TX_AUX_366C_VALUE << 8,
> +				   XTAL_FREQ_DP_TX_AUX_366C_MASK);
> +	}
> +}
> +
> +static void mtk_edp_phyd_wait_aux_ldo_ready(struct mtk_dp *mtk_dp,
> +					    unsigned long wait_us)
> +{
> +	int ret = 0;
> +	u32 val = 0x0;
> +	u32 mask = RGS_BG_CORE_EN_READY | RGS_AUX_LDO_EN_READY;
> +
> +	if (mtk_dp->phy_regs) {
> +		ret = regmap_read_poll_timeout(mtk_dp->phy_regs,
> +					       DP_PHY_DIG_GLB_STATUS_0,
> +					       val, !!(val & mask),
> +					       wait_us / 100, wait_us);

Could this waiting be placed in phy driver?
In phy_init() or phy_configure()?

> +	} else {
> +		ret = regmap_read_poll_timeout(mtk_dp->regs,
> +					       DP_PHY_DIG_GLB_STATUS_0,
> +					       val, !!(val & mask),
> +					       wait_us / 100, wait_us);
> +	}
> +
> +	if (ret)
> +		dev_err(mtk_dp->dev, "%s AUX not ready\n", __func__);
>  }
>  
>  static void mtk_dp_initialize_digital_settings(struct mtk_dp *mtk_dp)
> @@ -1115,15 +1282,63 @@ static void mtk_dp_initialize_digital_settings(struct mtk_dp *mtk_dp)
>  			   BS2BS_MODE_DP_ENC1_P0_VAL << 12,
>  			   BS2BS_MODE_DP_ENC1_P0_MASK);
>  
> +	if (mtk_dp->data->edp_ver) {

I would like a name about what it does rather than a version number.
Give it a meaningful name.

> +		/* dp I-mode enable */
> +		mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000,
> +				   DP_I_MODE_ENABLE, DP_I_MODE_ENABLE);
> +		/*symbol_cnt_reset */
> +		mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000,
> +				   REG_BS_SYMBOL_CNT_RESET,
> +				   REG_BS_SYMBOL_CNT_RESET);
> +		mtk_dp_update_bits(mtk_dp, REG_3368_DP_ENCODER1_P0,
> +				   VIDEO_SRAM_FIFO_CNT_RESET_SEL_VALUE,
> +				   VIDEO_SRAM_FIFO_CNT_RESET_SEL_MASK);
> +		mtk_dp_update_bits(mtk_dp, REG_3368_DP_ENCODER1_P0,
> +				   BS_FOLLOW_SEL_DP_ENC0_P0,
> +				   BS_FOLLOW_SEL_DP_ENC0_P0);
> +		/*[5:0]video sram start address*/
> +		mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,
> +				   SRAM_START_READ_THRD_DP_ENC0_P0_VALUE,
> +				   SRAM_START_READ_THRD_DP_ENC0_P0_MASK);
> +		/* reg_psr_patgen_avt_en disable psr pattern */
> +		mtk_dp_update_bits(mtk_dp, REG_3F80_DP_ENC_P0_3,
> +				   0, PSR_PATGEN_AVT_EN_FLDMASK);
> +		/* phy D enable */
> +		mtk_dp_update_bits(mtk_dp, REG_3F44_DP_ENC_P0_3,
> +				   PHY_PWR_STATE_OW_EN_DP_ENC_P0_3,
> +				   PHY_PWR_STATE_OW_EN_DP_ENC_P0_3_MASK);
> +		mtk_dp_update_bits(mtk_dp, REG_3F44_DP_ENC_P0_3,
> +				   ALL_POWER_ON,
> +				   PHY_PWR_STATE_OW_VALUE_DP_ENC_P0_3_MASK);
> +		mtk_edp_phyd_wait_aux_ldo_ready(mtk_dp, 100000);
> +		mtk_dp_update_bits(mtk_dp, REG_3F44_DP_ENC_P0_3,
> +				   0, PHY_PWR_STATE_OW_EN_DP_ENC_P0_3_MASK);
> +
> +		mtk_dp_update_bits(mtk_dp, REG_3FF8_DP_ENC_P0_3,
> +				   PHY_STATE_W_1_DP_ENC_P0_3,
> +				   PHY_STATE_W_1_DP_ENC_P0_3_MASK);
> +		/* reg_dvo_on_ow_en */
> +		mtk_dp_update_bits(mtk_dp, REG_3FF8_DP_ENC_P0_3,
> +				   DVO_ON_W_1_FLDMASK,
> +				   DVO_ON_W_1_FLDMASK);
> +	}
>  	/* dp tx encoder reset all sw */
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,
>  			   DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0,
>  			   DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0);
> +	if (mtk_dp->data->edp_ver) {

Ditto.

> +		mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004, 0,
> +				   DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0);
> +		mtk_dp_update_bits(mtk_dp, REG_3FF8_DP_ENC_P0_3,
> +				   PHY_STATE_RESET_ALL_VALUE,
> +				   PHY_STATE_RESET_ALL_MASK);
> +	}
>  
>  	/* Wait for sw reset to complete */
>  	usleep_range(1000, 5000);
> -	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,
> -			   0, DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0);
> +	if (!mtk_dp->data->edp_ver)

Ditto.

> +		mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004, 0,
> +				   DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0);
>  }
>  
>  static void mtk_dp_digital_sw_reset(struct mtk_dp *mtk_dp)
> @@ -1152,6 +1367,19 @@ static void mtk_dp_sdp_path_reset(struct mtk_dp *mtk_dp)
>  
>  static void mtk_dp_set_lanes(struct mtk_dp *mtk_dp, int lanes)
>  {
> +	if (mtk_dp->data->edp_ver) {

Ditto.

> +		mtk_dp_update_bits(mtk_dp, REG_3F44_DP_ENC_P0_3,
> +				   PHY_PWR_STATE_OW_EN_DP_ENC_P0_3,
> +				   PHY_PWR_STATE_OW_EN_DP_ENC_P0_3_MASK);
> +		mtk_dp_update_bits(mtk_dp, REG_3F44_DP_ENC_P0_3,
> +				   BIAS_POWER_ON,
> +				   PHY_PWR_STATE_OW_VALUE_DP_ENC_P0_3_MASK);
> +
> +		mtk_edp_phyd_wait_aux_ldo_ready(mtk_dp, 100000);
> +
> +		mtk_dp_update_bits(mtk_dp, REG_3F44_DP_ENC_P0_3,
> +				   0, PHY_PWR_STATE_OW_EN_DP_ENC_P0_3_MASK);
> +	}
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35F0,
>  			   lanes == 0 ? 0 : DP_TRANS_DUMMY_RW_0,
>  			   DP_TRANS_DUMMY_RW_0_MASK);
> @@ -1266,15 +1494,20 @@ static int mtk_dp_phy_configure(struct mtk_dp *mtk_dp,
>  			.ssc = mtk_dp->train_info.sink_ssc,
>  		}
>  	};
> -
> -	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, DP_PWR_STATE_BANDGAP,
> -			   DP_PWR_STATE_MASK);
> +	if (!mtk_dp->data->edp_ver)

Ditto.

> +		mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
> +				   DP_PWR_STATE_BANDGAP, DP_PWR_STATE_MASK);
>  
>  	ret = phy_configure(mtk_dp->phy, &phy_opts);
>  	if (ret)
>  		return ret;
>  
>  	mtk_dp_set_calibration_data(mtk_dp);
> +	/* Turn on phy power after phy configure */
> +	if (mtk_dp->data->edp_ver)

Ditto.

> +		mtk_dp_update_bits(mtk_dp, REG_3FF8_DP_ENC_P0_3,
> +				   PHY_STATE_W_1_DP_ENC_P0_3,
> +				   PHY_STATE_W_1_DP_ENC_P0_3_MASK);
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
>  			   DP_PWR_STATE_BANDGAP_TPLL_LANE, DP_PWR_STATE_MASK);
>  
> @@ -1326,16 +1559,20 @@ static void mtk_dp_video_mute(struct mtk_dp *mtk_dp, bool enable)
>  	struct arm_smccc_res res;
>  	u32 val = VIDEO_MUTE_SEL_DP_ENC0_P0 |
>  		  (enable ? VIDEO_MUTE_SW_DP_ENC0_P0 : 0);
> +	u32 smmc_para;
>  
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000,
>  			   val,
>  			   VIDEO_MUTE_SEL_DP_ENC0_P0 |
>  			   VIDEO_MUTE_SW_DP_ENC0_P0);
> -
> -	arm_smccc_smc(MTK_DP_SIP_CONTROL_AARCH32,
> -		      mtk_dp->data->smc_cmd, enable,
> -		      0, 0, 0, 0, 0, &res);
> -
> +	if (mtk_dp->data->edp_ver) {

Ditto.

> +		smmc_para = (EDP_VIDEO_UNMUTE << 16) | enable;
> +		arm_smccc_smc(MTK_SIP_DP_CONTROL, EDP_VIDEO_UNMUTE, enable,
> +			      smmc_para, EDP_VIDEO_UNMUTE_VAL, 0, 0, 0, &res);
> +	} else {
> +		arm_smccc_smc(MTK_DP_SIP_CONTROL_AARCH32,
> +			      mtk_dp->data->smc_cmd, enable, 0, 0, 0, 0, 0, &res);
> +	}
>  	dev_dbg(mtk_dp->dev, "smc cmd: 0x%x, p1: %s, ret: 0x%lx-0x%lx\n",
>  		mtk_dp->data->smc_cmd, enable ? "enable" : "disable", res.a0, res.a1);
>  }
> @@ -1410,6 +1647,16 @@ static void mtk_dp_power_enable(struct mtk_dp *mtk_dp)
>  static void mtk_dp_power_disable(struct mtk_dp *mtk_dp)
>  {
>  	mtk_dp_write(mtk_dp, MTK_DP_TOP_PWR_STATE, 0);
> +	if (mtk_dp->data->edp_ver) {

Ditto.

> +		mtk_dp_update_bits(mtk_dp, REG_3F44_DP_ENC_P0_3,
> +				   PHY_PWR_STATE_OW_EN_DP_ENC_P0_3,
> +				   PHY_PWR_STATE_OW_EN_DP_ENC_P0_3_MASK);
> +		mtk_dp_update_bits(mtk_dp, REG_3F44_DP_ENC_P0_3,
> +				   ALL_POWER_OFF,
> +				   PHY_PWR_STATE_OW_VALUE_DP_ENC_P0_3_MASK);
> +		mtk_dp_update_bits(mtk_dp, REG_3F44_DP_ENC_P0_3,
> +				   0, PHY_PWR_STATE_OW_EN_DP_ENC_P0_3_MASK);
> +	}
>  
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_0034,
>  			   DA_CKM_CKTX0_EN_FORCE_EN, DA_CKM_CKTX0_EN_FORCE_EN);
> @@ -1424,9 +1671,13 @@ static void mtk_dp_initialize_priv_data(struct mtk_dp *mtk_dp)
>  {
>  	bool plugged_in = (mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP);
>  
> -	mtk_dp->train_info.link_rate = DP_LINK_BW_5_4;
> +	if (mtk_dp->data->edp_ver)

Ditto.

> +		mtk_dp->train_info.link_rate = DP_LINK_BW_8_1;
> +	else
> +		mtk_dp->train_info.link_rate = DP_LINK_BW_5_4;
>  	mtk_dp->train_info.lane_count = mtk_dp->max_lanes;
>  	mtk_dp->train_info.cable_plugged_in = plugged_in;
> +	mtk_dp->train_info.sink_ssc = false;
>  
>  	mtk_dp->info.format = DP_PIXELFORMAT_RGB;
>  	memset(&mtk_dp->info.vm, 0, sizeof(struct videomode));
> @@ -1545,11 +1796,15 @@ static void mtk_dp_train_update_swing_pre(struct mtk_dp *mtk_dp, int lanes,
>  		int index = lane / 2;
>  		int shift = lane % 2 ? DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 0;
>  
> -		swing = (dpcd_adjust_req[index] >> shift) &
> -			DP_ADJUST_VOLTAGE_SWING_LANE0_MASK;
> +		if (mtk_dp->swing_value != 0) {
> +			swing = mtk_dp->swing_value;
> +		} else {
> +			swing = (dpcd_adjust_req[index] >> shift) &
> +				DP_ADJUST_VOLTAGE_SWING_LANE0_MASK;
> +		}
>  		preemphasis = ((dpcd_adjust_req[index] >> shift) &
> -			       DP_ADJUST_PRE_EMPHASIS_LANE0_MASK) >>
> -			      DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT;
> +				DP_ADJUST_PRE_EMPHASIS_LANE0_MASK) >>
> +				DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT;

It seems this just modify indent.
Separate this to an refinement patch.

>  		val = swing << DP_TRAIN_VOLTAGE_SWING_SHIFT |
>  		      preemphasis << DP_TRAIN_PRE_EMPHASIS_SHIFT;
>  
> @@ -1969,6 +2224,11 @@ static void mtk_dp_init_port(struct mtk_dp *mtk_dp)
>  	mtk_dp_initialize_hpd_detect_settings(mtk_dp);
>  
>  	mtk_dp_digital_sw_reset(mtk_dp);
> +
> +	if (mtk_dp->data->edp_ver)

I would like a name about what it does rather than a version number.
Give it a meaningful name.

> +		mtk_dp_update_bits(mtk_dp, EDP_TX_TOP_CLKGEN_0,
> +				   EDP_TX_TOP_CLKGEN_REST_VALUE,
> +				   EDP_TX_TOP_CLKGEN_REST_MASK);
>  }
>  
>  static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev)
> @@ -2047,9 +2307,15 @@ static int mtk_dp_wait_hpd_asserted(struct drm_dp_aux *mtk_aux, unsigned long wa
>  	u32 val;
>  	int ret;
>  
> -	ret = regmap_read_poll_timeout(mtk_dp->regs, MTK_DP_TRANS_P0_3414,
> -				       val, !!(val & HPD_DB_DP_TRANS_P0_MASK),
> -				       wait_us / 100, wait_us);
> +	if (mtk_dp->data->edp_ver)

Ditto.

> +		ret = regmap_read_poll_timeout(mtk_dp->regs, REG_364C_AUX_TX_P0,
> +					       val, !!(val & HPD_STATUS_DP_AUX_TX_P0_MASK),
> +					       wait_us / 100, wait_us);
> +	else
> +		ret = regmap_read_poll_timeout(mtk_dp->regs, MTK_DP_TRANS_P0_3414,
> +					       val, !!(val & HPD_DB_DP_TRANS_P0_MASK),
> +					       wait_us / 100, wait_us);
> +
>  	if (ret) {
>  		mtk_dp->train_info.cable_plugged_in = false;
>  		return ret;
> @@ -2072,7 +2338,10 @@ static int mtk_dp_dt_parse(struct mtk_dp *mtk_dp,
>  	struct device_node *endpoint;
>  	struct device *dev = &pdev->dev;
>  	int ret;
> +	int level;
> +	struct resource *regs;
>  	void __iomem *base;
> +	void __iomem *phy_base;
>  	u32 linkrate;
>  	int len;
>  
> @@ -2084,6 +2353,22 @@ static int mtk_dp_dt_parse(struct mtk_dp *mtk_dp,
>  	if (IS_ERR(mtk_dp->regs))
>  		return PTR_ERR(mtk_dp->regs);
>  
> +	phy_base = devm_platform_ioremap_resource(pdev, 1);
> +	if (!IS_ERR_OR_NULL(phy_base)) {
> +		mtk_dp->phy_regs = devm_regmap_init_mmio(dev, phy_base,
> +					&mtk_edp_phy_regmap_config);
> +		if (IS_ERR(mtk_dp->phy_regs))
> +			mtk_dp->phy_regs = NULL;
> +	}
> +
> +	regs = platform_get_resource(pdev, IORESOURCE_MEM, 2);

You does not define this in binding document.
You should define it in binding document first then you could use it.

> +	if (!IS_ERR_OR_NULL(regs)) {
> +		mtk_dp->pwr_regs = devm_ioremap(&pdev->dev, regs->start, 0x4);
> +		if (IS_ERR(mtk_dp->pwr_regs))
> +			dev_err(dev, "Failed to get pwr_regs: %ld\n",
> +				PTR_ERR(mtk_dp->pwr_regs));
> +	}
> +
>  	endpoint = of_graph_get_endpoint_by_regs(pdev->dev.of_node, 1, -1);
>  	len = of_property_count_elems_of_size(endpoint,
>  					      "data-lanes", sizeof(u32));
> @@ -2102,6 +2387,11 @@ static int mtk_dp_dt_parse(struct mtk_dp *mtk_dp,
>  
>  	mtk_dp->max_linkrate = drm_dp_link_rate_to_bw_code(linkrate * 100);
>  
> +	if (of_get_property(dev->of_node, "swing-level", &level)) {

You does not define this property in binding document, so drop this.
If you want to use this, define it in binding document first.

> +		of_property_read_u32(dev->of_node,
> +				     "swing-level", &mtk_dp->swing_value);
> +	}
> +
>  	return 0;
>  }
>  
> @@ -2672,17 +2962,28 @@ static int mtk_dp_register_phy(struct mtk_dp *mtk_dp)
>  {
>  	struct device *dev = mtk_dp->dev;
>  
> -	mtk_dp->phy_dev = platform_device_register_data(dev, "mediatek-dp-phy",
> -							PLATFORM_DEVID_AUTO,
> -							&mtk_dp->regs,
> -							sizeof(struct regmap *));
> +	if (mtk_dp->phy_regs)
> +		mtk_dp->phy_dev = platform_device_register_data(dev,
> +					"mediatek-edp-phy",
> +					PLATFORM_DEVID_AUTO,
> +					&mtk_dp->phy_regs,
> +					sizeof(struct regmap *));
> +	else
> +		mtk_dp->phy_dev = platform_device_register_data(dev,
> +					"mediatek-dp-phy",
> +					PLATFORM_DEVID_AUTO,
> +					&mtk_dp->regs,
> +					sizeof(struct regmap *));
>  	if (IS_ERR(mtk_dp->phy_dev))
>  		return dev_err_probe(dev, PTR_ERR(mtk_dp->phy_dev),
>  				     "Failed to create device mediatek-dp-phy\n");
>  
>  	mtk_dp_get_calibration_data(mtk_dp);
>  
> -	mtk_dp->phy = devm_phy_get(&mtk_dp->phy_dev->dev, "dp");
> +	if (mtk_dp->data->edp_ver)
> +		mtk_dp->phy = devm_phy_get(&mtk_dp->phy_dev->dev, "edp");
> +	else
> +		mtk_dp->phy = devm_phy_get(&mtk_dp->phy_dev->dev, "dp");
>  	if (IS_ERR(mtk_dp->phy)) {
>  		platform_device_unregister(mtk_dp->phy_dev);
>  		return dev_err_probe(dev, PTR_ERR(mtk_dp->phy), "Failed to get phy\n");
> @@ -2770,6 +3071,20 @@ static int mtk_dp_probe(struct platform_device *pdev)
>  	mtk_dp->aux.wait_hpd_asserted = mtk_dp_wait_hpd_asserted;
>  	drm_dp_aux_init(&mtk_dp->aux);
>  
> +	mtk_dp->power_clk = devm_clk_get_optional(dev, NULL);

In binding document, it does not define clk, so drop this.
If you want to use it, define it in binding document first.

Regards,
CK

> +	if (IS_ERR(mtk_dp->power_clk)) {
> +		dev_info(dev, "Failed to get optional clock power_clk\n");
> +		mtk_dp->power_clk = NULL;
> +	}
> +
> +	if (mtk_dp->power_clk)
> +		clk_prepare_enable(mtk_dp->power_clk);
> +
> +	pm_runtime_enable(dev);
> +	pm_runtime_get_sync(dev);
> +	if (mtk_dp->pwr_regs)
> +		mtk_edp_pm_ctl(mtk_dp, true);
> +
>  	platform_set_drvdata(pdev, mtk_dp);
>  
>  	if (mtk_dp->data->audio_supported) {
> @@ -2795,10 +3110,13 @@ static int mtk_dp_probe(struct platform_device *pdev)
>  		 * properly close the eDP port to avoid stalls and then
>  		 * reinitialize, reset and power on the AUX block.
>  		 */
> -		mtk_dp_set_idle_pattern(mtk_dp, true);
> -		mtk_dp_initialize_aux_settings(mtk_dp);
> -		mtk_dp_power_enable(mtk_dp);
> -
> +		if (mtk_dp->data->edp_ver) {
> +			mtk_dp_poweron(mtk_dp);
> +		} else {
> +			mtk_dp_set_idle_pattern(mtk_dp, true);
> +			mtk_dp_initialize_aux_settings(mtk_dp);
> +			mtk_dp_power_enable(mtk_dp);
> +		}
>  		/* Disable HW interrupts: we don't need any for eDP */
>  		mtk_dp_hwirq_enable(mtk_dp, false);
>  
> @@ -2835,8 +3153,8 @@ static int mtk_dp_probe(struct platform_device *pdev)
>  			return dev_err_probe(dev, ret, "Failed to add bridge\n");
>  	}
>  
> -	pm_runtime_enable(dev);
> -	pm_runtime_get_sync(dev);
> +	dev_dbg(dev, "%s power.usage_count %d\n",
> +		__func__, atomic_read(&dev->power.usage_count));
>  
>  	return 0;
>  }
> 


From daniel at fooishbar.org  Tue May 27 06:36:37 2025
From: daniel at fooishbar.org (Daniel Stone)
Date: Tue, 27 May 2025 14:36:37 +0100
Subject: [PATCH] media: dt-bindings: mediatek: Constrain iommus
In-Reply-To: <e462cdc4-7243-4cef-bd1d-a0ef551b3a87@kernel.org>
References: <20250525051639.68753-2-krzysztof.kozlowski@linaro.org>
 <CAPj87rMjAv-UphvFuQjop60o=wHrkfs4-XOM=JqH7f8Kk5dyVg@mail.gmail.com> <e462cdc4-7243-4cef-bd1d-a0ef551b3a87@kernel.org>
Message-ID: <CAPj87rNZPub=hEs+86JNfR-iqiuRYGGGKGsYyXtE1aUt8dEyUA@mail.gmail.com>

Hi,

On Sun, 25 May 2025 at 11:51, Krzysztof Kozlowski <krzk at kernel.org> wrote:
> On 25/05/2025 12:48, Daniel Stone wrote:
> > On Sun, 25 May 2025 at 06:16, Krzysztof Kozlowski
> > <krzysztof.kozlowski at linaro.org> wrote:
> >> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> >> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> >> @@ -45,9 +45,8 @@ properties:
> >>        - description: OVL-2L Clock
> >>
> >>    iommus:
> >> -    description:
> >> -      This property should point to the respective IOMMU block with master port as argument,
> >> -      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> >> +    minItems: 1
> >> +    maxItems: 2
> >
> > The comment removals are not documented in the commit message, and
> > it's not clear why removing information and references would be a good
> > thing.
> It's obvious, isn't? The consumer shall not define which provider has to
> use or how many cells provider has.

If you feel the change is good, then document it in the commit
message, and ideally also use separate commits rather than throwing in
unrelated changes into a commit which does not explain anything.
Again, the kernel documentation explains how you can structure your
commits in a better way.

Cheers,
Daniel


From lorenzo at kernel.org  Tue May 27 07:22:57 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Tue, 27 May 2025 16:22:57 +0200
Subject: [PATCH net-next 1/2] net: airoha: Initialize PPE UPDMEM
 source-mac table
In-Reply-To: <20250523-b4-airoha-flowtable-pppoe-v1-1-8584401568e0@kernel.org>
References: <20250523-b4-airoha-flowtable-pppoe-v1-0-8584401568e0@kernel.org>
 <20250523-b4-airoha-flowtable-pppoe-v1-1-8584401568e0@kernel.org>
Message-ID: <aDXKwWzmE1YSg67u@lore-desk>

> UPDMEM source-mac table is a key-value map used to store devices mac
> addresses according to the port identifier. UPDMEM source mac table is
> used during IPv6 traffic hw acceleration since PPE entries, for space
> constraints, do not contain the full source mac address but just the
> identifier in the UPDMEM source-mac table.

This patch has now a conflict with the following commit:
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c683e378c0907e66cee939145edf936c254ff1e3

Since this is actually a fix, I can repost targeting net tree as soon as
it is aligned to net-next.

Regards,
Lorenzo

> 
> Fixes: 00a7678310fe ("net: airoha: Introduce flowtable offload support")
> Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
> ---
>  drivers/net/ethernet/airoha/airoha_eth.c  |  2 ++
>  drivers/net/ethernet/airoha/airoha_eth.h  |  1 +
>  drivers/net/ethernet/airoha/airoha_ppe.c  | 25 ++++++++++++++++++++++++-
>  drivers/net/ethernet/airoha/airoha_regs.h | 10 ++++++++++
>  4 files changed, 37 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index 0d627e511266d94e079e8a87d2f812fb14b4ad07..e4c67c7bbf215d448640f978cd0d9d50abd73644 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -92,6 +92,8 @@ static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
>  	val = (addr[3] << 16) | (addr[4] << 8) | addr[5];
>  	airoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), val);
>  	airoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), val);
> +
> +	airoha_ppe_init_upd_mem(port);
>  }
>  
>  static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr,
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
> index 531a3c49c1562a986111a1ce1c215c8751c16e09..a951246c0171e14497b510d3029fc0a7f891efe6 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.h
> +++ b/drivers/net/ethernet/airoha/airoha_eth.h
> @@ -611,6 +611,7 @@ void airoha_ppe_check_skb(struct airoha_ppe *ppe, struct sk_buff *skb,
>  int airoha_ppe_setup_tc_block_cb(struct net_device *dev, void *type_data);
>  int airoha_ppe_init(struct airoha_eth *eth);
>  void airoha_ppe_deinit(struct airoha_eth *eth);
> +void airoha_ppe_init_upd_mem(struct airoha_gdm_port *port);
>  struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe,
>  						  u32 hash);
>  void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash,
> diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
> index 2d273937f19cf304ab4b821241fdc3ea93604f0e..1d5a04eb82a6645e2b6a22ff4e694275ef1727d8 100644
> --- a/drivers/net/ethernet/airoha/airoha_ppe.c
> +++ b/drivers/net/ethernet/airoha/airoha_ppe.c
> @@ -223,6 +223,7 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
>  	int dsa_port = airoha_get_dsa_port(&dev);
>  	struct airoha_foe_mac_info_common *l2;
>  	u32 qdata, ports_pad, val;
> +	u8 smac_id = 0xf;
>  
>  	memset(hwe, 0, sizeof(*hwe));
>  
> @@ -251,6 +252,7 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
>  		else
>  			pse_port = 2; /* uplink relies on GDM2 loopback */
>  		val |= FIELD_PREP(AIROHA_FOE_IB2_PSE_PORT, pse_port);
> +		smac_id = port->id;
>  	}
>  
>  	if (is_multicast_ether_addr(data->eth.h_dest))
> @@ -285,7 +287,7 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
>  		hwe->ipv4.l2.src_mac_lo =
>  			get_unaligned_be16(data->eth.h_source + 4);
>  	} else {
> -		l2->src_mac_hi = FIELD_PREP(AIROHA_FOE_MAC_SMAC_ID, 0xf);
> +		l2->src_mac_hi = FIELD_PREP(AIROHA_FOE_MAC_SMAC_ID, smac_id);
>  	}
>  
>  	if (data->vlan.num) {
> @@ -1232,6 +1234,27 @@ void airoha_ppe_check_skb(struct airoha_ppe *ppe, struct sk_buff *skb,
>  	airoha_ppe_foe_insert_entry(ppe, skb, hash);
>  }
>  
> +void airoha_ppe_init_upd_mem(struct airoha_gdm_port *port)
> +{
> +	struct airoha_eth *eth = port->qdma->eth;
> +	struct net_device *dev = port->dev;
> +	const u8 *addr = dev->dev_addr;
> +	u32 val;
> +
> +	val = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
> +	airoha_fe_wr(eth, REG_UPDMEM_DATA(0), val);
> +	airoha_fe_wr(eth, REG_UPDMEM_CTRL(0),
> +		     FIELD_PREP(PPE_UPDMEM_ADDR_MASK, port->id) |
> +		     PPE_UPDMEM_WR_MASK | PPE_UPDMEM_REQ_MASK);
> +
> +	val = (addr[0] << 8) | addr[1];
> +	airoha_fe_wr(eth, REG_UPDMEM_DATA(0), val);
> +	airoha_fe_wr(eth, REG_UPDMEM_CTRL(0),
> +		     FIELD_PREP(PPE_UPDMEM_ADDR_MASK, port->id) |
> +		     FIELD_PREP(PPE_UPDMEM_OFFSET_MASK, 1) |
> +		     PPE_UPDMEM_WR_MASK | PPE_UPDMEM_REQ_MASK);
> +}
> +
>  int airoha_ppe_init(struct airoha_eth *eth)
>  {
>  	struct airoha_ppe *ppe;
> diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
> index d931530fc96fb00ada36a6ad37fa295865a6f0a8..04187eb40ec674ec5a4ccfc968bb4bd579a53095 100644
> --- a/drivers/net/ethernet/airoha/airoha_regs.h
> +++ b/drivers/net/ethernet/airoha/airoha_regs.h
> @@ -313,6 +313,16 @@
>  #define REG_PPE_RAM_BASE(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x320)
>  #define REG_PPE_RAM_ENTRY(_m, _n)		(REG_PPE_RAM_BASE(_m) + ((_n) << 2))
>  
> +#define REG_UPDMEM_CTRL(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x370)
> +#define PPE_UPDMEM_ACK_MASK			BIT(31)
> +#define PPE_UPDMEM_ADDR_MASK			GENMASK(11, 8)
> +#define PPE_UPDMEM_OFFSET_MASK			GENMASK(7, 4)
> +#define PPE_UPDMEM_SEL_MASK			GENMASK(3, 2)
> +#define PPE_UPDMEM_WR_MASK			BIT(1)
> +#define PPE_UPDMEM_REQ_MASK			BIT(0)
> +
> +#define REG_UPDMEM_DATA(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x374)
> +
>  #define REG_FE_GDM_TX_OK_PKT_CNT_H(_n)		(GDM_BASE(_n) + 0x280)
>  #define REG_FE_GDM_TX_OK_BYTE_CNT_H(_n)		(GDM_BASE(_n) + 0x284)
>  #define REG_FE_GDM_TX_ETH_PKT_CNT_H(_n)		(GDM_BASE(_n) + 0x288)
> 
> -- 
> 2.49.0
> 
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From robh at kernel.org  Tue May 27 12:28:24 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Tue, 27 May 2025 14:28:24 -0500
Subject: [PATCH v2 01/14] dt-bindings: net: mediatek,net: update for
 mt7988
In-Reply-To: <20250516180147.10416-2-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
 <20250516180147.10416-2-linux@fw-web.de>
Message-ID: <174837410385.1090056.12670391327460010323.robh@kernel.org>


On Fri, 16 May 2025 20:01:31 +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w at public-files.de>
> 
> Update binding for mt7988 which has 3 gmac and 2 reg items.
> 
> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> ---
> v2:
> - change reg to list of items
> ---
>  .../devicetree/bindings/net/mediatek,net.yaml          | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh at kernel.org>



From robh at kernel.org  Tue May 27 12:29:11 2025
From: robh at kernel.org (Rob Herring (Arm))
Date: Tue, 27 May 2025 14:29:11 -0500
Subject: [PATCH v2 03/14] dt-bindings: net: dsa: mediatek,mt7530: add
 internal mdio bus
In-Reply-To: <20250516180147.10416-5-linux@fw-web.de>
References: <20250516180147.10416-1-linux@fw-web.de>
 <20250516180147.10416-5-linux@fw-web.de>
Message-ID: <174837415111.1091232.14774319774329934407.robh@kernel.org>


On Fri, 16 May 2025 20:01:34 +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w at public-files.de>
> 
> Mt7988 buildin switch has own mdio bus where ge-phys are connected.
> Add related property for this.
> 
> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> ---
> v2:
> - change from patternproperty to property
> - add unevaluatedProperties and mediatek,pio subproperty
> ---
>  .../devicetree/bindings/net/dsa/mediatek,mt7530.yaml   | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh at kernel.org>



From vincent at systemli.org  Tue May 27 13:53:24 2025
From: vincent at systemli.org (nick)
Date: Tue, 27 May 2025 22:53:24 +0200
Subject: [BUG] Stale FDB entries after WLAN roaming with mt7530 DSA on
 untagged ports
Message-ID: <b5e2c58a-9f1b-4295-83e2-53b38f0ef005@systemli.org>

Hi,
OpenWrt users are observing an issue on OpenWrt (22.03+) with the mt7530 DSA
switch, where roaming wireless clients leave behind stale FDB entries when
using *untagged* VLAN ports. The client's MAC address remains associated
with both the old and new AP interfaces, causing traffic to be misrouted
or dropped until the stale entry expires.

People describe the steps to reproduce it differently; however, I share what
I observe, and the result is the same.

Steps to reproduce:
1. Bridge WLAN to a VLAN via mt7530 DSA, using *untagged* ports.
2. Connect a wireless client to AP1 (mt7530 switch).
3. Roam the client to AP2 (no mt7530 switch).
4. Roam back to AP1 (now connectivity breaks).
5. Observe that AP1 (where the client is now connected) FDB still lists the
 ?? client MAC on the ethernet, e.g. dev lan4 vlan 40 self (pointing to AP2)
 ?? and the wlan interface, but does not route traffic to the wlan (dev
 ?? wlan5-ff used 127/0 master br-dhcp). So two entries are available.

Topology diagram illustrating the setup:

 ??????????????? +--------+?????? +------+
 ??????????????? | Router |?????? | AP2? |
 ??????????????? | (DHCP) |?????? +------+
 ??????????????? +--------+?????????? |
 ???????????????????? \?????????????? |
 ????????????????????? \???????????? /
 ?????????????????????? \?????????? /
 ???????????????????? +---------------+
 ???????????????????? |???? AP1?????? |
 ???????????????????? |?? mt7530 DSA? |
 ???????????????????? +---------------+

Expected behavior:
The FDB should update immediately to reflect the new interface.

Actual behavior:
The stale entry persists, breaking connectivity until it times out.

Notes:
- This connectivity breakdown does *not* occur using tagged ports; only
 ? untagged ports are affected.
- It did not occur with `swconfig` (pre-DSA switch framework).
- For some users, a user-space FDB cleanup script worked (however, it does
 ? not work for me).
- The issue is still present with kernel version 6.12 (latest tested).

More discussion and technical details can be found here:
https://github.com/openwrt/openwrt/issues/11650

Any help or insights would be greatly appreciated. This issue has been
present for quite a long time, and that?s why I?m reaching out for help
via this mailing list.

Best regards,
Nick


From bvanassche at acm.org  Tue May 27 14:38:00 2025
From: bvanassche at acm.org (Bart Van Assche)
Date: Tue, 27 May 2025 14:38:00 -0700
Subject: [PATCH v6] ufs: core: Add HID support
In-Reply-To: <20250523064604.800-1-tanghuan@vivo.com>
References: <20250523064604.800-1-tanghuan@vivo.com>
Message-ID: <ae392b24-9096-45d4-a138-a6fb64dffaec@acm.org>

On 5/22/25 11:46 PM, Huan Tang wrote:
> Follow JESD220G, support HID(Host Initiated Defragmentation)
> through sysfs, the relevant sysfs nodes are as follows:
> 	1.analysis_trigger
> 	2.defrag_trigger
> 	3.fragmented_size
> 	4.defrag_size
> 	5.progress_ratio
> 	6.state
> The detailed definition	of the six nodes can be	found in the sysfs
> documentation.
> 
> HID's execution policy is given to user-space.
> 
> Signed-off-by: Huan Tang <tanghuan at vivo.com>
> Signed-off-by: Wenxing Cheng <wenxing.cheng at vivo.com>
> Suggested-by: Bart Van Assche <bvanassche at acm.org>
> Reviewed-by: Peter Wang <peter.wang at mediatek.com>
> Reviewed-by: Bean Huo <huobean at gmail.com>

Reviewed-by: Bart Van Assche <bvanassche at acm.org>


From ansuelsmth at gmail.com  Tue May 27 15:20:32 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Wed, 28 May 2025 00:20:32 +0200
Subject: [PATCH 0/6] pinctrl: Add Airoha AN7583 support
Message-ID: <20250527222040.32000-1-ansuelsmth@gmail.com>

This small series introduce support for Airoha AN7583 pinctrl
support.

Most of the changes are generalization and cleanup of the Airoha
pinctrl driver. These are needed as all the array in the inner
function were hardcoded to EN7581 and didn't reference stuff
from the priv groups.

Everything is changed to match_data and priv struct so
adding AN7583 is just a matter of adding the structs.

Also the schema is generalized where needed to address
for the small difference between AN7583 and EN7581.

While converting it, it was also found an additional copy-paste
error for the PHY LEDs pins.

Christian Marangi (6):
  pinctrl: airoha: fix wrong PHY LED mux value for LED1 GPIO46
  pinctrl: mediatek: airoha: generalize pins/group/function/confs
    handling
  pinctrl: airoha: convert PHY LED GPIO to macro
  pinctrl: airoha: convert PWM GPIO to macro
  dt-bindings: pinctrl: airoha: Document AN7583 Pin Controller
  pinctrl: airoha: add support for Airoha AN7583 PINs

 .../pinctrl/airoha,en7581-pinctrl.yaml        |  297 +-
 drivers/pinctrl/mediatek/pinctrl-airoha.c     | 2497 +++++++++--------
 2 files changed, 1489 insertions(+), 1305 deletions(-)

-- 
2.48.1



From ansuelsmth at gmail.com  Tue May 27 15:20:33 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Wed, 28 May 2025 00:20:33 +0200
Subject: [PATCH 1/6] pinctrl: airoha: fix wrong PHY LED mux value for LED1 GPIO46
In-Reply-To: <20250527222040.32000-1-ansuelsmth@gmail.com>
References: <20250527222040.32000-1-ansuelsmth@gmail.com>
Message-ID: <20250527222040.32000-2-ansuelsmth@gmail.com>

In all the MUX value for LED1 GPIO46 there is a Copy-Paste error where
the MUX value is set to LED0_MODE_MASK instead of LED1_MODE_MASK.

This wasn't notice as there were no board that made use of the
secondary PHY LED but looking at the internal Documentation the actual
value should be LED1_MODE_MASK similar to the other GPIO entry.

Fix the wrong value to apply the correct MUX configuration.

Cc: stable at vger.kernel.org
Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/pinctrl/mediatek/pinctrl-airoha.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
index b97b28ebb37a..8ef7f88477aa 100644
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
@@ -1752,8 +1752,8 @@ static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
 		.regmap[0] = {
 			AIROHA_FUNC_MUX,
 			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN3_LED0_MODE_MASK,
-			GPIO_LAN3_LED0_MODE_MASK
+			GPIO_LAN3_LED1_MODE_MASK,
+			GPIO_LAN3_LED1_MODE_MASK
 		},
 		.regmap[1] = {
 			AIROHA_FUNC_MUX,
@@ -1816,8 +1816,8 @@ static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
 		.regmap[0] = {
 			AIROHA_FUNC_MUX,
 			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN3_LED0_MODE_MASK,
-			GPIO_LAN3_LED0_MODE_MASK
+			GPIO_LAN3_LED1_MODE_MASK,
+			GPIO_LAN3_LED1_MODE_MASK
 		},
 		.regmap[1] = {
 			AIROHA_FUNC_MUX,
@@ -1880,8 +1880,8 @@ static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
 		.regmap[0] = {
 			AIROHA_FUNC_MUX,
 			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN3_LED0_MODE_MASK,
-			GPIO_LAN3_LED0_MODE_MASK
+			GPIO_LAN3_LED1_MODE_MASK,
+			GPIO_LAN3_LED1_MODE_MASK
 		},
 		.regmap[1] = {
 			AIROHA_FUNC_MUX,
@@ -1944,8 +1944,8 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
 		.regmap[0] = {
 			AIROHA_FUNC_MUX,
 			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN3_LED0_MODE_MASK,
-			GPIO_LAN3_LED0_MODE_MASK
+			GPIO_LAN3_LED1_MODE_MASK,
+			GPIO_LAN3_LED1_MODE_MASK
 		},
 		.regmap[1] = {
 			AIROHA_FUNC_MUX,
-- 
2.48.1



From ansuelsmth at gmail.com  Tue May 27 15:20:34 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Wed, 28 May 2025 00:20:34 +0200
Subject: [PATCH 2/6] pinctrl: mediatek: airoha: generalize pins/group/function/confs handling
In-Reply-To: <20250527222040.32000-1-ansuelsmth@gmail.com>
References: <20250527222040.32000-1-ansuelsmth@gmail.com>
Message-ID: <20250527222040.32000-3-ansuelsmth@gmail.com>

In preparation for support of Airoha AN7583, generalize
pins/group/function/confs handling and move them in match_data.
Inner function will base the values on the pinctrl priv struct instead of
relying on hardcoded struct.

This permits to use different PIN data while keeping the same logic.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/pinctrl/mediatek/pinctrl-airoha.c | 569 ++++++++++++----------
 1 file changed, 319 insertions(+), 250 deletions(-)

diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
index 8ef7f88477aa..8af9109db992 100644
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
@@ -30,20 +30,20 @@
 #include "../pinconf.h"
 #include "../pinmux.h"
 
-#define PINCTRL_PIN_GROUP(id)						\
-	PINCTRL_PINGROUP(#id, id##_pins, ARRAY_SIZE(id##_pins))
+#define PINCTRL_PIN_GROUP(id, table)					\
+	PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))
 
-#define PINCTRL_FUNC_DESC(id)						\
+#define PINCTRL_FUNC_DESC(id, table)					\
 	{								\
 		.desc = {						\
 			.func = {					\
-				.name = #id,				\
-				.groups = id##_groups,			\
-				.ngroups = ARRAY_SIZE(id##_groups),	\
+				.name = id,				\
+				.groups = table##_groups,		\
+				.ngroups = ARRAY_SIZE(table##_groups),	\
 			}						\
 		},							\
-		.groups = id##_func_group,				\
-		.group_size = ARRAY_SIZE(id##_func_group),		\
+		.groups = table##_func_group,				\
+		.group_size = ARRAY_SIZE(table##_func_group),		\
 	}
 
 #define PINCTRL_CONF_DESC(p, offset, mask)				\
@@ -359,16 +359,46 @@ struct airoha_pinctrl_gpiochip {
 	u32 irq_type[AIROHA_NUM_PINS];
 };
 
+struct airoha_pinctrl_confs_info {
+	const struct airoha_pinctrl_conf *confs;
+	unsigned int num_confs;
+};
+
+enum airoha_pinctrl_confs_type {
+	AIROHA_PINCTRL_CONFS_PULLUP,
+	AIROHA_PINCTRL_CONFS_PULLDOWN,
+	AIROHA_PINCTRL_CONFS_DRIVE_E2,
+	AIROHA_PINCTRL_CONFS_DRIVE_E4,
+	AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
+
+	AIROHA_PINCTRL_CONFS_MAX,
+};
+
 struct airoha_pinctrl {
 	struct pinctrl_dev *ctrl;
 
+	struct pinctrl_desc desc;
+	const struct pingroup *grps;
+	const struct airoha_pinctrl_func *funcs;
+	const struct airoha_pinctrl_confs_info *confs_info;
+
 	struct regmap *chip_scu;
 	struct regmap *regmap;
 
 	struct airoha_pinctrl_gpiochip gpiochip;
 };
 
-static struct pinctrl_pin_desc airoha_pinctrl_pins[] = {
+struct airoha_pinctrl_match_data {
+	const struct pinctrl_pin_desc *pins;
+	const unsigned int num_pins;
+	const struct pingroup *grps;
+	const unsigned int num_grps;
+	const struct airoha_pinctrl_func *funcs;
+	const unsigned int num_funcs;
+	const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
+};
+
+static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
 	PINCTRL_PIN(0, "uart1_txd"),
 	PINCTRL_PIN(1, "uart1_rxd"),
 	PINCTRL_PIN(2, "i2c_scl"),
@@ -429,172 +459,172 @@ static struct pinctrl_pin_desc airoha_pinctrl_pins[] = {
 	PINCTRL_PIN(63, "pcie_reset2"),
 };
 
-static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 };
-static const int pon_tod_1pps_pins[] = { 46 };
-static const int gsw_tod_1pps_pins[] = { 46 };
-static const int sipo_pins[] = { 16, 17 };
-static const int sipo_rclk_pins[] = { 16, 17, 43 };
-static const int mdio_pins[] = { 14, 15 };
-static const int uart2_pins[] = { 48, 55 };
-static const int uart2_cts_rts_pins[] = { 46, 47 };
-static const int hsuart_pins[] = { 28, 29 };
-static const int hsuart_cts_rts_pins[] = { 26, 27 };
-static const int uart4_pins[] = { 38, 39 };
-static const int uart5_pins[] = { 18, 19 };
-static const int i2c0_pins[] = { 2, 3 };
-static const int i2c1_pins[] = { 14, 15 };
-static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
-static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
-static const int i2s_pins[] = { 26, 27, 28, 29 };
-static const int pcm1_pins[] = { 22, 23, 24, 25 };
-static const int pcm2_pins[] = { 18, 19, 20, 21 };
-static const int spi_quad_pins[] = { 32, 33 };
-static const int spi_pins[] = { 4, 5, 6, 7 };
-static const int spi_cs1_pins[] = { 34 };
-static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
-static const int pcm_spi_int_pins[] = { 14 };
-static const int pcm_spi_rst_pins[] = { 15 };
-static const int pcm_spi_cs1_pins[] = { 43 };
-static const int pcm_spi_cs2_pins[] = { 40 };
-static const int pcm_spi_cs2_p128_pins[] = { 40 };
-static const int pcm_spi_cs2_p156_pins[] = { 40 };
-static const int pcm_spi_cs3_pins[] = { 41 };
-static const int pcm_spi_cs4_pins[] = { 42 };
-static const int emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
-static const int pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
-static const int gpio0_pins[] = { 13 };
-static const int gpio1_pins[] = { 14 };
-static const int gpio2_pins[] = { 15 };
-static const int gpio3_pins[] = { 16 };
-static const int gpio4_pins[] = { 17 };
-static const int gpio5_pins[] = { 18 };
-static const int gpio6_pins[] = { 19 };
-static const int gpio7_pins[] = { 20 };
-static const int gpio8_pins[] = { 21 };
-static const int gpio9_pins[] = { 22 };
-static const int gpio10_pins[] = { 23 };
-static const int gpio11_pins[] = { 24 };
-static const int gpio12_pins[] = { 25 };
-static const int gpio13_pins[] = { 26 };
-static const int gpio14_pins[] = { 27 };
-static const int gpio15_pins[] = { 28 };
-static const int gpio16_pins[] = { 29 };
-static const int gpio17_pins[] = { 30 };
-static const int gpio18_pins[] = { 31 };
-static const int gpio19_pins[] = { 32 };
-static const int gpio20_pins[] = { 33 };
-static const int gpio21_pins[] = { 34 };
-static const int gpio22_pins[] = { 35 };
-static const int gpio23_pins[] = { 36 };
-static const int gpio24_pins[] = { 37 };
-static const int gpio25_pins[] = { 38 };
-static const int gpio26_pins[] = { 39 };
-static const int gpio27_pins[] = { 40 };
-static const int gpio28_pins[] = { 41 };
-static const int gpio29_pins[] = { 42 };
-static const int gpio30_pins[] = { 43 };
-static const int gpio31_pins[] = { 44 };
-static const int gpio33_pins[] = { 46 };
-static const int gpio34_pins[] = { 47 };
-static const int gpio35_pins[] = { 48 };
-static const int gpio36_pins[] = { 49 };
-static const int gpio37_pins[] = { 50 };
-static const int gpio38_pins[] = { 51 };
-static const int gpio39_pins[] = { 52 };
-static const int gpio40_pins[] = { 53 };
-static const int gpio41_pins[] = { 54 };
-static const int gpio42_pins[] = { 55 };
-static const int gpio43_pins[] = { 56 };
-static const int gpio44_pins[] = { 57 };
-static const int gpio45_pins[] = { 58 };
-static const int gpio46_pins[] = { 59 };
-static const int pcie_reset0_pins[] = { 61 };
-static const int pcie_reset1_pins[] = { 62 };
-static const int pcie_reset2_pins[] = { 63 };
-
-static const struct pingroup airoha_pinctrl_groups[] = {
-	PINCTRL_PIN_GROUP(pon),
-	PINCTRL_PIN_GROUP(pon_tod_1pps),
-	PINCTRL_PIN_GROUP(gsw_tod_1pps),
-	PINCTRL_PIN_GROUP(sipo),
-	PINCTRL_PIN_GROUP(sipo_rclk),
-	PINCTRL_PIN_GROUP(mdio),
-	PINCTRL_PIN_GROUP(uart2),
-	PINCTRL_PIN_GROUP(uart2_cts_rts),
-	PINCTRL_PIN_GROUP(hsuart),
-	PINCTRL_PIN_GROUP(hsuart_cts_rts),
-	PINCTRL_PIN_GROUP(uart4),
-	PINCTRL_PIN_GROUP(uart5),
-	PINCTRL_PIN_GROUP(i2c0),
-	PINCTRL_PIN_GROUP(i2c1),
-	PINCTRL_PIN_GROUP(jtag_udi),
-	PINCTRL_PIN_GROUP(jtag_dfd),
-	PINCTRL_PIN_GROUP(i2s),
-	PINCTRL_PIN_GROUP(pcm1),
-	PINCTRL_PIN_GROUP(pcm2),
-	PINCTRL_PIN_GROUP(spi),
-	PINCTRL_PIN_GROUP(spi_quad),
-	PINCTRL_PIN_GROUP(spi_cs1),
-	PINCTRL_PIN_GROUP(pcm_spi),
-	PINCTRL_PIN_GROUP(pcm_spi_int),
-	PINCTRL_PIN_GROUP(pcm_spi_rst),
-	PINCTRL_PIN_GROUP(pcm_spi_cs1),
-	PINCTRL_PIN_GROUP(pcm_spi_cs2_p128),
-	PINCTRL_PIN_GROUP(pcm_spi_cs2_p156),
-	PINCTRL_PIN_GROUP(pcm_spi_cs2),
-	PINCTRL_PIN_GROUP(pcm_spi_cs3),
-	PINCTRL_PIN_GROUP(pcm_spi_cs4),
-	PINCTRL_PIN_GROUP(emmc),
-	PINCTRL_PIN_GROUP(pnand),
-	PINCTRL_PIN_GROUP(gpio0),
-	PINCTRL_PIN_GROUP(gpio1),
-	PINCTRL_PIN_GROUP(gpio2),
-	PINCTRL_PIN_GROUP(gpio3),
-	PINCTRL_PIN_GROUP(gpio4),
-	PINCTRL_PIN_GROUP(gpio5),
-	PINCTRL_PIN_GROUP(gpio6),
-	PINCTRL_PIN_GROUP(gpio7),
-	PINCTRL_PIN_GROUP(gpio8),
-	PINCTRL_PIN_GROUP(gpio9),
-	PINCTRL_PIN_GROUP(gpio10),
-	PINCTRL_PIN_GROUP(gpio11),
-	PINCTRL_PIN_GROUP(gpio12),
-	PINCTRL_PIN_GROUP(gpio13),
-	PINCTRL_PIN_GROUP(gpio14),
-	PINCTRL_PIN_GROUP(gpio15),
-	PINCTRL_PIN_GROUP(gpio16),
-	PINCTRL_PIN_GROUP(gpio17),
-	PINCTRL_PIN_GROUP(gpio18),
-	PINCTRL_PIN_GROUP(gpio19),
-	PINCTRL_PIN_GROUP(gpio20),
-	PINCTRL_PIN_GROUP(gpio21),
-	PINCTRL_PIN_GROUP(gpio22),
-	PINCTRL_PIN_GROUP(gpio23),
-	PINCTRL_PIN_GROUP(gpio24),
-	PINCTRL_PIN_GROUP(gpio25),
-	PINCTRL_PIN_GROUP(gpio26),
-	PINCTRL_PIN_GROUP(gpio27),
-	PINCTRL_PIN_GROUP(gpio28),
-	PINCTRL_PIN_GROUP(gpio29),
-	PINCTRL_PIN_GROUP(gpio30),
-	PINCTRL_PIN_GROUP(gpio31),
-	PINCTRL_PIN_GROUP(gpio33),
-	PINCTRL_PIN_GROUP(gpio34),
-	PINCTRL_PIN_GROUP(gpio35),
-	PINCTRL_PIN_GROUP(gpio36),
-	PINCTRL_PIN_GROUP(gpio37),
-	PINCTRL_PIN_GROUP(gpio38),
-	PINCTRL_PIN_GROUP(gpio39),
-	PINCTRL_PIN_GROUP(gpio40),
-	PINCTRL_PIN_GROUP(gpio41),
-	PINCTRL_PIN_GROUP(gpio42),
-	PINCTRL_PIN_GROUP(gpio43),
-	PINCTRL_PIN_GROUP(gpio44),
-	PINCTRL_PIN_GROUP(gpio45),
-	PINCTRL_PIN_GROUP(gpio46),
-	PINCTRL_PIN_GROUP(pcie_reset0),
-	PINCTRL_PIN_GROUP(pcie_reset1),
-	PINCTRL_PIN_GROUP(pcie_reset2),
+static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
+static const int en7581_pon_tod_1pps_pins[] = { 46 };
+static const int en7581_gsw_tod_1pps_pins[] = { 46 };
+static const int en7581_sipo_pins[] = { 16, 17 };
+static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
+static const int en7581_mdio_pins[] = { 14, 15 };
+static const int en7581_uart2_pins[] = { 48, 55 };
+static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
+static const int en7581_hsuart_pins[] = { 28, 29 };
+static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
+static const int en7581_uart4_pins[] = { 38, 39 };
+static const int en7581_uart5_pins[] = { 18, 19 };
+static const int en7581_i2c0_pins[] = { 2, 3 };
+static const int en7581_i2c1_pins[] = { 14, 15 };
+static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
+static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
+static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
+static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
+static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
+static const int en7581_spi_quad_pins[] = { 32, 33 };
+static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
+static const int en7581_spi_cs1_pins[] = { 34 };
+static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
+static const int en7581_pcm_spi_int_pins[] = { 14 };
+static const int en7581_pcm_spi_rst_pins[] = { 15 };
+static const int en7581_pcm_spi_cs1_pins[] = { 43 };
+static const int en7581_pcm_spi_cs2_pins[] = { 40 };
+static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
+static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
+static const int en7581_pcm_spi_cs3_pins[] = { 41 };
+static const int en7581_pcm_spi_cs4_pins[] = { 42 };
+static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
+static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
+static const int en7581_gpio0_pins[] = { 13 };
+static const int en7581_gpio1_pins[] = { 14 };
+static const int en7581_gpio2_pins[] = { 15 };
+static const int en7581_gpio3_pins[] = { 16 };
+static const int en7581_gpio4_pins[] = { 17 };
+static const int en7581_gpio5_pins[] = { 18 };
+static const int en7581_gpio6_pins[] = { 19 };
+static const int en7581_gpio7_pins[] = { 20 };
+static const int en7581_gpio8_pins[] = { 21 };
+static const int en7581_gpio9_pins[] = { 22 };
+static const int en7581_gpio10_pins[] = { 23 };
+static const int en7581_gpio11_pins[] = { 24 };
+static const int en7581_gpio12_pins[] = { 25 };
+static const int en7581_gpio13_pins[] = { 26 };
+static const int en7581_gpio14_pins[] = { 27 };
+static const int en7581_gpio15_pins[] = { 28 };
+static const int en7581_gpio16_pins[] = { 29 };
+static const int en7581_gpio17_pins[] = { 30 };
+static const int en7581_gpio18_pins[] = { 31 };
+static const int en7581_gpio19_pins[] = { 32 };
+static const int en7581_gpio20_pins[] = { 33 };
+static const int en7581_gpio21_pins[] = { 34 };
+static const int en7581_gpio22_pins[] = { 35 };
+static const int en7581_gpio23_pins[] = { 36 };
+static const int en7581_gpio24_pins[] = { 37 };
+static const int en7581_gpio25_pins[] = { 38 };
+static const int en7581_gpio26_pins[] = { 39 };
+static const int en7581_gpio27_pins[] = { 40 };
+static const int en7581_gpio28_pins[] = { 41 };
+static const int en7581_gpio29_pins[] = { 42 };
+static const int en7581_gpio30_pins[] = { 43 };
+static const int en7581_gpio31_pins[] = { 44 };
+static const int en7581_gpio33_pins[] = { 46 };
+static const int en7581_gpio34_pins[] = { 47 };
+static const int en7581_gpio35_pins[] = { 48 };
+static const int en7581_gpio36_pins[] = { 49 };
+static const int en7581_gpio37_pins[] = { 50 };
+static const int en7581_gpio38_pins[] = { 51 };
+static const int en7581_gpio39_pins[] = { 52 };
+static const int en7581_gpio40_pins[] = { 53 };
+static const int en7581_gpio41_pins[] = { 54 };
+static const int en7581_gpio42_pins[] = { 55 };
+static const int en7581_gpio43_pins[] = { 56 };
+static const int en7581_gpio44_pins[] = { 57 };
+static const int en7581_gpio45_pins[] = { 58 };
+static const int en7581_gpio46_pins[] = { 59 };
+static const int en7581_pcie_reset0_pins[] = { 61 };
+static const int en7581_pcie_reset1_pins[] = { 62 };
+static const int en7581_pcie_reset2_pins[] = { 63 };
+
+static const struct pingroup en7581_pinctrl_groups[] = {
+	PINCTRL_PIN_GROUP("pon", en7581_pon),
+	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
+	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
+	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
+	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
+	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
+	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
+	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
+	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
+	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
+	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
+	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
+	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
+	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
+	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
+	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
+	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
+	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
+	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
+	PINCTRL_PIN_GROUP("spi", en7581_spi),
+	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
+	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
+	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
+	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
+	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
+	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
+	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
+	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
+	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
+	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
+	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
+	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
+	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
+	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
+	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
+	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
+	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
+	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
+	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
+	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
+	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
+	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
+	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
+	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
+	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
+	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
+	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
+	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
+	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
+	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
+	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
+	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
+	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
+	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
+	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
+	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
+	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
+	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
+	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
+	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
+	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
+	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
+	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
+	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
+	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
+	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
+	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
+	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
+	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
+	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
+	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
+	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
+	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
+	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
+	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
+	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
+	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
+	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
+	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
+	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
+	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
+	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
 };
 
 static const char *const pon_groups[] = { "pon" };
@@ -1957,33 +1987,33 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
 	},
 };
 
-static const struct airoha_pinctrl_func airoha_pinctrl_funcs[] = {
-	PINCTRL_FUNC_DESC(pon),
-	PINCTRL_FUNC_DESC(tod_1pps),
-	PINCTRL_FUNC_DESC(sipo),
-	PINCTRL_FUNC_DESC(mdio),
-	PINCTRL_FUNC_DESC(uart),
-	PINCTRL_FUNC_DESC(i2c),
-	PINCTRL_FUNC_DESC(jtag),
-	PINCTRL_FUNC_DESC(pcm),
-	PINCTRL_FUNC_DESC(spi),
-	PINCTRL_FUNC_DESC(pcm_spi),
-	PINCTRL_FUNC_DESC(i2s),
-	PINCTRL_FUNC_DESC(emmc),
-	PINCTRL_FUNC_DESC(pnand),
-	PINCTRL_FUNC_DESC(pcie_reset),
-	PINCTRL_FUNC_DESC(pwm),
-	PINCTRL_FUNC_DESC(phy1_led0),
-	PINCTRL_FUNC_DESC(phy2_led0),
-	PINCTRL_FUNC_DESC(phy3_led0),
-	PINCTRL_FUNC_DESC(phy4_led0),
-	PINCTRL_FUNC_DESC(phy1_led1),
-	PINCTRL_FUNC_DESC(phy2_led1),
-	PINCTRL_FUNC_DESC(phy3_led1),
-	PINCTRL_FUNC_DESC(phy4_led1),
+static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
+	PINCTRL_FUNC_DESC("pon", pon),
+	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+	PINCTRL_FUNC_DESC("sipo", sipo),
+	PINCTRL_FUNC_DESC("mdio", mdio),
+	PINCTRL_FUNC_DESC("uart", uart),
+	PINCTRL_FUNC_DESC("i2c", i2c),
+	PINCTRL_FUNC_DESC("jtag", jtag),
+	PINCTRL_FUNC_DESC("pcm", pcm),
+	PINCTRL_FUNC_DESC("spi", spi),
+	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
+	PINCTRL_FUNC_DESC("i2s", i2s),
+	PINCTRL_FUNC_DESC("emmc", emmc),
+	PINCTRL_FUNC_DESC("pnand", pnand),
+	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+	PINCTRL_FUNC_DESC("pwm", pwm),
+	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
+	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
+	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
+	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
+	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
+	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
+	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
 };
 
-static const struct airoha_pinctrl_conf airoha_pinctrl_pullup_conf[] = {
+static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
 	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
 	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
 	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
@@ -2044,7 +2074,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_pullup_conf[] = {
 	PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
 };
 
-static const struct airoha_pinctrl_conf airoha_pinctrl_pulldown_conf[] = {
+static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
 	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
 	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
 	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
@@ -2105,7 +2135,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_pulldown_conf[] = {
 	PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
 };
 
-static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e2_conf[] = {
+static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
 	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
 	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
 	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
@@ -2166,7 +2196,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e2_conf[] = {
 	PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
 };
 
-static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e4_conf[] = {
+static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
 	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
 	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
 	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
@@ -2227,7 +2257,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e4_conf[] = {
 	PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
 };
 
-static const struct airoha_pinctrl_conf airoha_pinctrl_pcie_rst_od_conf[] = {
+static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
 	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
 	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
 	PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
@@ -2548,12 +2578,17 @@ airoha_pinctrl_get_conf_reg(const struct airoha_pinctrl_conf *conf,
 }
 
 static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,
-				   const struct airoha_pinctrl_conf *conf,
-				   int conf_size, int pin, u32 *val)
+				   enum airoha_pinctrl_confs_type conf_type,
+				   int pin, u32 *val)
 {
+	const struct airoha_pinctrl_confs_info *confs_info;
 	const struct airoha_pinctrl_reg *reg;
 
-	reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
+	confs_info = &pinctrl->confs_info[conf_type];
+
+	reg = airoha_pinctrl_get_conf_reg(confs_info->confs,
+					  confs_info->num_confs,
+					  pin);
 	if (!reg)
 		return -EINVAL;
 
@@ -2566,12 +2601,17 @@ static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,
 }
 
 static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
-				   const struct airoha_pinctrl_conf *conf,
-				   int conf_size, int pin, u32 val)
+				   enum airoha_pinctrl_confs_type conf_type,
+				   int pin, u32 val)
 {
+	const struct airoha_pinctrl_confs_info *confs_info;
 	const struct airoha_pinctrl_reg *reg = NULL;
 
-	reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
+	confs_info = &pinctrl->confs_info[conf_type];
+
+	reg = airoha_pinctrl_get_conf_reg(confs_info->confs,
+					  confs_info->num_confs,
+					  pin);
 	if (!reg)
 		return -EINVAL;
 
@@ -2584,44 +2624,34 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
 }
 
 #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pullup_conf,		\
-				ARRAY_SIZE(airoha_pinctrl_pullup_conf),		\
+	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
 				(pin), (val))
 #define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pulldown_conf,	\
-				ARRAY_SIZE(airoha_pinctrl_pulldown_conf),	\
+	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,	\
 				(pin), (val))
 #define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e2_conf,	\
-				ARRAY_SIZE(airoha_pinctrl_drive_e2_conf),	\
+	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,	\
 				(pin), (val))
 #define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e4_conf,	\
-				ARRAY_SIZE(airoha_pinctrl_drive_e4_conf),	\
+	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,	\
 				(pin), (val))
 #define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf,	\
-				ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf),	\
+	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,	\
 				(pin), (val))
 #define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pullup_conf,		\
-				ARRAY_SIZE(airoha_pinctrl_pullup_conf),		\
+	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
 				(pin), (val))
 #define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pulldown_conf,	\
-				ARRAY_SIZE(airoha_pinctrl_pulldown_conf),	\
+	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,	\
 				(pin), (val))
 #define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e2_conf,	\
-				ARRAY_SIZE(airoha_pinctrl_drive_e2_conf),	\
+	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,	\
 				(pin), (val))
 #define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e4_conf,	\
-				ARRAY_SIZE(airoha_pinctrl_drive_e4_conf),	\
+	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,	\
 				(pin), (val))
 #define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf,	\
-				ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf),	\
+	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,	\
 				(pin), (val))
 
 static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
@@ -2798,12 +2828,13 @@ static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev,
 static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev,
 				    unsigned int group, unsigned long *config)
 {
+	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 	u32 cur_config = 0;
 	int i;
 
-	for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
+	for (i = 0; i < pinctrl->grps[group].npins; i++) {
 		if (airoha_pinconf_get(pctrl_dev,
-				       airoha_pinctrl_groups[group].pins[i],
+				       pinctrl->grps[group].pins[i],
 				       config))
 			return -EOPNOTSUPP;
 
@@ -2820,13 +2851,14 @@ static int airoha_pinconf_group_set(struct pinctrl_dev *pctrl_dev,
 				    unsigned int group, unsigned long *configs,
 				    unsigned int num_configs)
 {
+	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 	int i;
 
-	for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
+	for (i = 0; i < pinctrl->grps[group].npins; i++) {
 		int err;
 
 		err = airoha_pinconf_set(pctrl_dev,
-					 airoha_pinctrl_groups[group].pins[i],
+					 pinctrl->grps[group].pins[i],
 					 configs, num_configs);
 		if (err)
 			return err;
@@ -2852,23 +2884,16 @@ static const struct pinctrl_ops airoha_pctlops = {
 	.dt_free_map = pinconf_generic_dt_free_map,
 };
 
-static struct pinctrl_desc airoha_pinctrl_desc = {
-	.name = KBUILD_MODNAME,
-	.owner = THIS_MODULE,
-	.pctlops = &airoha_pctlops,
-	.pmxops = &airoha_pmxops,
-	.confops = &airoha_confops,
-	.pins = airoha_pinctrl_pins,
-	.npins = ARRAY_SIZE(airoha_pinctrl_pins),
-};
-
 static int airoha_pinctrl_probe(struct platform_device *pdev)
 {
+	const struct airoha_pinctrl_match_data *data;
 	struct device *dev = &pdev->dev;
 	struct airoha_pinctrl *pinctrl;
 	struct regmap *map;
 	int err, i;
 
+	data = device_get_match_data(dev);
+
 	pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
 	if (!pinctrl)
 		return -ENOMEM;
@@ -2883,14 +2908,23 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
 
 	pinctrl->chip_scu = map;
 
-	err = devm_pinctrl_register_and_init(dev, &airoha_pinctrl_desc,
+	/* Init pinctrl desc struct */
+	pinctrl->desc.name = KBUILD_MODNAME;
+	pinctrl->desc.owner = THIS_MODULE,
+	pinctrl->desc.pctlops = &airoha_pctlops,
+	pinctrl->desc.pmxops = &airoha_pmxops,
+	pinctrl->desc.confops = &airoha_confops,
+	pinctrl->desc.pins = data->pins,
+	pinctrl->desc.npins = data->num_pins,
+
+	err = devm_pinctrl_register_and_init(dev, &pinctrl->desc,
 					     pinctrl, &pinctrl->ctrl);
 	if (err)
 		return err;
 
 	/* build pin groups */
-	for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_groups); i++) {
-		const struct pingroup *grp = &airoha_pinctrl_groups[i];
+	for (i = 0; i < data->num_grps; i++) {
+		const struct pingroup *grp = &data->grps[i];
 
 		err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name,
 						grp->pins, grp->npins,
@@ -2903,10 +2937,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
 	}
 
 	/* build functions */
-	for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_funcs); i++) {
+	for (i = 0; i < data->num_funcs; i++) {
 		const struct airoha_pinctrl_func *func;
 
-		func = &airoha_pinctrl_funcs[i];
+		func = &data->funcs[i];
 		err = pinmux_generic_add_function(pinctrl->ctrl,
 						  func->desc.func.name,
 						  func->desc.func.groups,
@@ -2919,6 +2953,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
 		}
 	}
 
+	pinctrl->grps = data->grps;
+	pinctrl->funcs = data->funcs;
+	pinctrl->confs_info = data->confs_info;
+
 	err = pinctrl_enable(pinctrl->ctrl);
 	if (err)
 		return err;
@@ -2927,8 +2965,39 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
 	return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
 }
 
+static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
+	.pins = en7581_pinctrl_pins,
+	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
+	.grps = en7581_pinctrl_groups,
+	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
+	.funcs = en7581_pinctrl_funcs,
+	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
+	.confs_info = {
+		[AIROHA_PINCTRL_CONFS_PULLUP] = {
+			.confs = en7581_pinctrl_pullup_conf,
+			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+			.confs = en7581_pinctrl_pulldown_conf,
+			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+			.confs = en7581_pinctrl_drive_e2_conf,
+			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+			.confs = en7581_pinctrl_drive_e4_conf,
+			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+			.confs = en7581_pinctrl_pcie_rst_od_conf,
+			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
+		},
+	},
+};
+
 static const struct of_device_id airoha_pinctrl_of_match[] = {
-	{ .compatible = "airoha,en7581-pinctrl" },
+	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
-- 
2.48.1



From ansuelsmth at gmail.com  Tue May 27 15:20:35 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Wed, 28 May 2025 00:20:35 +0200
Subject: [PATCH 3/6] pinctrl: airoha: convert PHY LED GPIO to macro
In-Reply-To: <20250527222040.32000-1-ansuelsmth@gmail.com>
References: <20250527222040.32000-1-ansuelsmth@gmail.com>
Message-ID: <20250527222040.32000-4-ansuelsmth@gmail.com>

PHY LED GPIO pinctrl struct definition is very similar across the
different 4 PHY and 2 LED and it can be generelized to a macro.

To reduce code size, convert them to a common macro.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/pinctrl/mediatek/pinctrl-airoha.c | 570 ++++------------------
 1 file changed, 82 insertions(+), 488 deletions(-)

diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
index 8af9109db992..2b532334d759 100644
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
@@ -1475,516 +1475,110 @@ static const struct airoha_pinctrl_func_group pwm_func_group[] = {
 	},
 };
 
+#define AIROHA_PINCTRL_PHY_LED(gpio, mux_val, map_mask, map_val)	\
+	{								\
+		.name = (gpio),						\
+		.regmap[0] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_GPIO_2ND_I2C_MODE,				\
+			(mux_val),					\
+			(mux_val),					\
+		},							\
+		.regmap[1] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_LAN_LED0_MAPPING,				\
+			(map_mask),					\
+			(map_val),					\
+		},							\
+		.regmap_size = 2,					\
+	}
+
 static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
-	{
-		.name = "gpio33",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN0_LED0_MODE_MASK,
-			GPIO_LAN0_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN0_LED_MAPPING_MASK,
-			LAN0_PHY_LED_MAP(0)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio34",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN1_LED0_MODE_MASK,
-			GPIO_LAN1_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN1_LED_MAPPING_MASK,
-			LAN1_PHY_LED_MAP(0)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio35",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN2_LED0_MODE_MASK,
-			GPIO_LAN2_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN2_LED_MAPPING_MASK,
-			LAN2_PHY_LED_MAP(0)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio42",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN3_LED0_MODE_MASK,
-			GPIO_LAN3_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN3_LED_MAPPING_MASK,
-			LAN3_PHY_LED_MAP(0)
-		},
-		.regmap_size = 2,
-	},
+	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
 };
 
 static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
-	{
-		.name = "gpio33",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN0_LED0_MODE_MASK,
-			GPIO_LAN0_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN0_LED_MAPPING_MASK,
-			LAN0_PHY_LED_MAP(1)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio34",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN1_LED0_MODE_MASK,
-			GPIO_LAN1_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN1_LED_MAPPING_MASK,
-			LAN1_PHY_LED_MAP(1)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio35",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN2_LED0_MODE_MASK,
-			GPIO_LAN2_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN2_LED_MAPPING_MASK,
-			LAN2_PHY_LED_MAP(1)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio42",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN3_LED0_MODE_MASK,
-			GPIO_LAN3_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN3_LED_MAPPING_MASK,
-			LAN3_PHY_LED_MAP(1)
-		},
-		.regmap_size = 2,
-	},
+	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
 };
 
 static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
-	{
-		.name = "gpio33",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN0_LED0_MODE_MASK,
-			GPIO_LAN0_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN0_LED_MAPPING_MASK,
-			LAN0_PHY_LED_MAP(2)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio34",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN1_LED0_MODE_MASK,
-			GPIO_LAN1_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN1_LED_MAPPING_MASK,
-			LAN1_PHY_LED_MAP(2)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio35",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN2_LED0_MODE_MASK,
-			GPIO_LAN2_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN2_LED_MAPPING_MASK,
-			LAN2_PHY_LED_MAP(2)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio42",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN3_LED0_MODE_MASK,
-			GPIO_LAN3_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN3_LED_MAPPING_MASK,
-			LAN3_PHY_LED_MAP(2)
-		},
-		.regmap_size = 2,
-	},
+	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
 };
 
 static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
-	{
-		.name = "gpio33",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN0_LED0_MODE_MASK,
-			GPIO_LAN0_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN0_LED_MAPPING_MASK,
-			LAN0_PHY_LED_MAP(3)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio34",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN1_LED0_MODE_MASK,
-			GPIO_LAN1_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN1_LED_MAPPING_MASK,
-			LAN1_PHY_LED_MAP(3)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio35",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN2_LED0_MODE_MASK,
-			GPIO_LAN2_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN2_LED_MAPPING_MASK,
-			LAN2_PHY_LED_MAP(3)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio42",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN3_LED0_MODE_MASK,
-			GPIO_LAN3_LED0_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED0_MAPPING,
-			LAN3_LED_MAPPING_MASK,
-			LAN3_PHY_LED_MAP(3)
-		},
-		.regmap_size = 2,
-	},
+	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
 };
 
 static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
-	{
-		.name = "gpio43",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN0_LED1_MODE_MASK,
-			GPIO_LAN0_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN0_LED_MAPPING_MASK,
-			LAN0_PHY_LED_MAP(0)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio44",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN1_LED1_MODE_MASK,
-			GPIO_LAN1_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN1_LED_MAPPING_MASK,
-			LAN1_PHY_LED_MAP(0)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio45",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN2_LED1_MODE_MASK,
-			GPIO_LAN2_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN2_LED_MAPPING_MASK,
-			LAN2_PHY_LED_MAP(0)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio46",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN3_LED1_MODE_MASK,
-			GPIO_LAN3_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN3_LED_MAPPING_MASK,
-			LAN3_PHY_LED_MAP(0)
-		},
-		.regmap_size = 2,
-	},
+	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
 };
 
 static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
-	{
-		.name = "gpio43",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN0_LED1_MODE_MASK,
-			GPIO_LAN0_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN0_LED_MAPPING_MASK,
-			LAN0_PHY_LED_MAP(1)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio44",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN1_LED1_MODE_MASK,
-			GPIO_LAN1_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN1_LED_MAPPING_MASK,
-			LAN1_PHY_LED_MAP(1)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio45",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN2_LED1_MODE_MASK,
-			GPIO_LAN2_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN2_LED_MAPPING_MASK,
-			LAN2_PHY_LED_MAP(1)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio46",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN3_LED1_MODE_MASK,
-			GPIO_LAN3_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN3_LED_MAPPING_MASK,
-			LAN3_PHY_LED_MAP(1)
-		},
-		.regmap_size = 2,
-	},
+	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
 };
 
 static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
-	{
-		.name = "gpio43",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN0_LED1_MODE_MASK,
-			GPIO_LAN0_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN0_LED_MAPPING_MASK,
-			LAN0_PHY_LED_MAP(2)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio44",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN1_LED1_MODE_MASK,
-			GPIO_LAN1_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN1_LED_MAPPING_MASK,
-			LAN1_PHY_LED_MAP(2)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio45",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN2_LED1_MODE_MASK,
-			GPIO_LAN2_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN2_LED_MAPPING_MASK,
-			LAN2_PHY_LED_MAP(2)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio46",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN3_LED1_MODE_MASK,
-			GPIO_LAN3_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN3_LED_MAPPING_MASK,
-			LAN3_PHY_LED_MAP(2)
-		},
-		.regmap_size = 2,
-	},
+	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
 };
 
 static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
-	{
-		.name = "gpio43",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN0_LED1_MODE_MASK,
-			GPIO_LAN0_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN0_LED_MAPPING_MASK,
-			LAN0_PHY_LED_MAP(3)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio44",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN1_LED1_MODE_MASK,
-			GPIO_LAN1_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN1_LED_MAPPING_MASK,
-			LAN1_PHY_LED_MAP(3)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio45",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN2_LED1_MODE_MASK,
-			GPIO_LAN2_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN2_LED_MAPPING_MASK,
-			LAN2_PHY_LED_MAP(3)
-		},
-		.regmap_size = 2,
-	}, {
-		.name = "gpio46",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_LAN3_LED1_MODE_MASK,
-			GPIO_LAN3_LED1_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_LAN_LED1_MAPPING,
-			LAN3_LED_MAPPING_MASK,
-			LAN3_PHY_LED_MAP(3)
-		},
-		.regmap_size = 2,
-	},
+	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
 };
 
 static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
-- 
2.48.1



From ansuelsmth at gmail.com  Tue May 27 15:20:36 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Wed, 28 May 2025 00:20:36 +0200
Subject: [PATCH 4/6] pinctrl: airoha: convert PWM GPIO to macro
In-Reply-To: <20250527222040.32000-1-ansuelsmth@gmail.com>
References: <20250527222040.32000-1-ansuelsmth@gmail.com>
Message-ID: <20250527222040.32000-5-ansuelsmth@gmail.com>

The PWM GPIO struct definition follow the same pattern for every GPIO
pin hence it can be converted to a macro.

Create 2 macro one for normal mux and one for ext mux and convert all
the entry to these new macro to reduce code size.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/pinctrl/mediatek/pinctrl-airoha.c | 465 ++++------------------
 1 file changed, 68 insertions(+), 397 deletions(-)

diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
index 2b532334d759..8c8d5b598f4f 100644
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
@@ -1075,404 +1075,75 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
 };
 
 /* PWM */
+#define AIROHA_PINCTRL_PWM(gpio, mux_val)		\
+	{						\
+		.name = (gpio),				\
+		.regmap[0] = {				\
+			AIROHA_FUNC_PWM_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG,	\
+			(mux_val),			\
+			(mux_val)			\
+		},					\
+		.regmap_size = 1,			\
+	}						\
+
+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)		\
+	{						\
+		.name = (gpio),				\
+		.regmap[0] = {				\
+			AIROHA_FUNC_PWM_EXT_MUX,	\
+			REG_GPIO_FLASH_MODE_CFG_EXT,	\
+			(mux_val),			\
+			(mux_val)			\
+		},					\
+		.regmap_size = 1,			\
+	}						\
+
 static const struct airoha_pinctrl_func_group pwm_func_group[] = {
-	{
-		.name = "gpio0",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO0_FLASH_MODE_CFG,
-			GPIO0_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio1",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO1_FLASH_MODE_CFG,
-			GPIO1_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio2",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO2_FLASH_MODE_CFG,
-			GPIO2_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio3",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO3_FLASH_MODE_CFG,
-			GPIO3_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio4",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO4_FLASH_MODE_CFG,
-			GPIO4_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio5",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO5_FLASH_MODE_CFG,
-			GPIO5_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio6",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO6_FLASH_MODE_CFG,
-			GPIO6_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio7",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO7_FLASH_MODE_CFG,
-			GPIO7_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio8",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO8_FLASH_MODE_CFG,
-			GPIO8_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio9",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO9_FLASH_MODE_CFG,
-			GPIO9_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio10",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO10_FLASH_MODE_CFG,
-			GPIO10_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio11",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO11_FLASH_MODE_CFG,
-			GPIO11_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio12",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO12_FLASH_MODE_CFG,
-			GPIO12_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio13",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO13_FLASH_MODE_CFG,
-			GPIO13_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio14",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO14_FLASH_MODE_CFG,
-			GPIO14_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio15",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_MUX,
-			REG_GPIO_FLASH_MODE_CFG,
-			GPIO15_FLASH_MODE_CFG,
-			GPIO15_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio16",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO16_FLASH_MODE_CFG,
-			GPIO16_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio17",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO17_FLASH_MODE_CFG,
-			GPIO17_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio18",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO18_FLASH_MODE_CFG,
-			GPIO18_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio19",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO19_FLASH_MODE_CFG,
-			GPIO19_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio20",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO20_FLASH_MODE_CFG,
-			GPIO20_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio21",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO21_FLASH_MODE_CFG,
-			GPIO21_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio22",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO22_FLASH_MODE_CFG,
-			GPIO22_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio23",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO23_FLASH_MODE_CFG,
-			GPIO23_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio24",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO24_FLASH_MODE_CFG,
-			GPIO24_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio25",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO25_FLASH_MODE_CFG,
-			GPIO25_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio26",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO26_FLASH_MODE_CFG,
-			GPIO26_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio27",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO27_FLASH_MODE_CFG,
-			GPIO27_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio28",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO28_FLASH_MODE_CFG,
-			GPIO28_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio29",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO29_FLASH_MODE_CFG,
-			GPIO29_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio30",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO30_FLASH_MODE_CFG,
-			GPIO30_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio31",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO31_FLASH_MODE_CFG,
-			GPIO31_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio36",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO36_FLASH_MODE_CFG,
-			GPIO36_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio37",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO37_FLASH_MODE_CFG,
-			GPIO37_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio38",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO38_FLASH_MODE_CFG,
-			GPIO38_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio39",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO39_FLASH_MODE_CFG,
-			GPIO39_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio40",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO40_FLASH_MODE_CFG,
-			GPIO40_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio41",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO41_FLASH_MODE_CFG,
-			GPIO41_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio42",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO42_FLASH_MODE_CFG,
-			GPIO42_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio43",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO43_FLASH_MODE_CFG,
-			GPIO43_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio44",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO44_FLASH_MODE_CFG,
-			GPIO44_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio45",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO45_FLASH_MODE_CFG,
-			GPIO45_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio46",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO46_FLASH_MODE_CFG,
-			GPIO46_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gpio47",
-		.regmap[0] = {
-			AIROHA_FUNC_PWM_EXT_MUX,
-			REG_GPIO_FLASH_MODE_CFG_EXT,
-			GPIO47_FLASH_MODE_CFG,
-			GPIO47_FLASH_MODE_CFG
-		},
-		.regmap_size = 1,
-	},
+	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG),
 };
 
 #define AIROHA_PINCTRL_PHY_LED(gpio, mux_val, map_mask, map_val)	\
-- 
2.48.1



From ansuelsmth at gmail.com  Tue May 27 15:20:37 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Wed, 28 May 2025 00:20:37 +0200
Subject: [PATCH 5/6] dt-bindings: pinctrl: airoha: Document AN7583 Pin Controller
In-Reply-To: <20250527222040.32000-1-ansuelsmth@gmail.com>
References: <20250527222040.32000-1-ansuelsmth@gmail.com>
Message-ID: <20250527222040.32000-6-ansuelsmth@gmail.com>

Document Airoha AN7583 Pin Controller based on Airoha EN7581 with some
minor difference on some function group.

Make the PHY LEDs, pcie_reset and PCM SPI function dependent of the
compatible and define the different group for AN7583.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 .../pinctrl/airoha,en7581-pinctrl.yaml        | 297 ++++++++++++------
 1 file changed, 207 insertions(+), 90 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
index 21fd4f1ba78b..38511ad2f9e6 100644
--- a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
@@ -4,17 +4,19 @@
 $id: http://devicetree.org/schemas/pinctrl/airoha,en7581-pinctrl.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Airoha EN7581 Pin Controller
+title: Airoha EN7581/AN7583 Pin Controller
 
 maintainers:
   - Lorenzo Bianconi <lorenzo at kernel.org>
 
 description:
-  The Airoha's EN7581 Pin controller is used to control SoC pins.
+  The Airoha's EN7581/AN7583 Pin controller is used to control SoC pins.
 
 properties:
   compatible:
-    const: airoha,en7581-pinctrl
+    enum:
+      - airoha,en7581-pinctrl
+      - airoha,an7583-pinctrl
 
   interrupts:
     maxItems: 1
@@ -32,9 +34,6 @@ properties:
   '#interrupt-cells':
     const: 2
 
-allOf:
-  - $ref: pinctrl.yaml#
-
 required:
   - compatible
   - interrupts
@@ -151,18 +150,6 @@ patternProperties:
                   items:
                     enum: [spi_quad, spi_cs1]
                   maxItems: 2
-          - if:
-              properties:
-                function:
-                  const: pcm_spi
-            then:
-              properties:
-                groups:
-                  items:
-                    enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1,
-                           pcm_spi_cs2_p156, pcm_spi_cs2_p128, pcm_spi_cs3,
-                           pcm_spi_cs4]
-                  maxItems: 7
           - if:
               properties:
                 function:
@@ -187,14 +174,6 @@ patternProperties:
               properties:
                 groups:
                   enum: [pnand]
-          - if:
-              properties:
-                function:
-                  const: pcie_reset
-            then:
-              properties:
-                groups:
-                  enum: [pcie_reset0, pcie_reset1, pcie_reset2]
           - if:
               properties:
                 function:
@@ -209,70 +188,6 @@ patternProperties:
                          gpio26, gpio27, gpio28, gpio29, gpio30, gpio31,
                          gpio36, gpio37, gpio38, gpio39, gpio40, gpio41,
                          gpio42, gpio43, gpio44, gpio45, gpio46, gpio47]
-          - if:
-              properties:
-                function:
-                  const: phy1_led0
-            then:
-              properties:
-                groups:
-                  enum: [gpio33, gpio34, gpio35, gpio42]
-          - if:
-              properties:
-                function:
-                  const: phy2_led0
-            then:
-              properties:
-                groups:
-                  enum: [gpio33, gpio34, gpio35, gpio42]
-          - if:
-              properties:
-                function:
-                  const: phy3_led0
-            then:
-              properties:
-                groups:
-                  enum: [gpio33, gpio34, gpio35, gpio42]
-          - if:
-              properties:
-                function:
-                  const: phy4_led0
-            then:
-              properties:
-                groups:
-                  enum: [gpio33, gpio34, gpio35, gpio42]
-          - if:
-              properties:
-                function:
-                  const: phy1_led1
-            then:
-              properties:
-                groups:
-                  enum: [gpio43, gpio44, gpio45, gpio46]
-          - if:
-              properties:
-                function:
-                  const: phy2_led1
-            then:
-              properties:
-                groups:
-                  enum: [gpio43, gpio44, gpio45, gpio46]
-          - if:
-              properties:
-                function:
-                  const: phy3_led1
-            then:
-              properties:
-                groups:
-                  enum: [gpio43, gpio44, gpio45, gpio46]
-          - if:
-              properties:
-                function:
-                  const: phy4_led1
-            then:
-              properties:
-                groups:
-                  enum: [gpio43, gpio44, gpio45, gpio46]
 
         additionalProperties: false
 
@@ -331,6 +246,208 @@ patternProperties:
 
 additionalProperties: false
 
+allOf:
+  - $ref: pinctrl.yaml#
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: airoha,en7581-pinctrl
+    then:
+      patternProperties:
+        '-pins$':
+          type: object
+
+          patternProperties:
+            '^mux(-|$)':
+              type: object
+
+              allOf:
+                - if:
+                    properties:
+                      function:
+                        const: pcm_spi
+                  then:
+                    properties:
+                      groups:
+                        items:
+                          enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1,
+                                 pcm_spi_cs2_p156, pcm_spi_cs2_p128, pcm_spi_cs3,
+                                 pcm_spi_cs4]
+                        maxItems: 7
+                - if:
+                    properties:
+                      function:
+                        const: pcie_reset
+                  then:
+                    properties:
+                      groups:
+                        enum: [pcie_reset0, pcie_reset1, pcie_reset2]
+                - if:
+                    properties:
+                      function:
+                        const: phy1_led0
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio33, gpio34, gpio35, gpio42]
+                - if:
+                    properties:
+                      function:
+                        const: phy2_led0
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio33, gpio34, gpio35, gpio42]
+                - if:
+                    properties:
+                      function:
+                        const: phy3_led0
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio33, gpio34, gpio35, gpio42]
+                - if:
+                    properties:
+                      function:
+                        const: phy4_led0
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio33, gpio34, gpio35, gpio42]
+                - if:
+                    properties:
+                      function:
+                        const: phy1_led1
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio43, gpio44, gpio45, gpio46]
+                - if:
+                    properties:
+                      function:
+                        const: phy2_led1
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio43, gpio44, gpio45, gpio46]
+                - if:
+                    properties:
+                      function:
+                        const: phy3_led1
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio43, gpio44, gpio45, gpio46]
+                - if:
+                    properties:
+                      function:
+                        const: phy4_led1
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio43, gpio44, gpio45, gpio46]
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: airoha,an7583-pinctrl
+    then:
+      patternProperties:
+        '-pins$':
+          type: object
+
+          patternProperties:
+            '^mux(-|$)':
+              type: object
+
+              allOf:
+                - if:
+                    properties:
+                      function:
+                        const: pcm_spi
+                  then:
+                    properties:
+                      groups:
+                        items:
+                          enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1,
+                                 pcm_spi_cs2, pcm_spi_cs3, pcm_spi_cs4]
+                        maxItems: 7
+                - if:
+                    properties:
+                      function:
+                        const: pcie_reset
+                  then:
+                    properties:
+                      groups:
+                        enum: [pcie_reset0, pcie_reset1]
+                - if:
+                    properties:
+                      function:
+                        const: phy1_led0
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio1, gpio2, gpio3, gpio4]
+                - if:
+                    properties:
+                      function:
+                        const: phy2_led0
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio1, gpio2, gpio3, gpio4]
+                - if:
+                    properties:
+                      function:
+                        const: phy3_led0
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio1, gpio2, gpio3, gpio4]
+                - if:
+                    properties:
+                      function:
+                        const: phy4_led0
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio1, gpio2, gpio3, gpio4]
+                - if:
+                    properties:
+                      function:
+                        const: phy1_led1
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio8, gpio9, gpio10, gpio11]
+                - if:
+                    properties:
+                      function:
+                        const: phy2_led1
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio8, gpio9, gpio10, gpio11]
+                - if:
+                    properties:
+                      function:
+                        const: phy3_led1
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio8, gpio9, gpio10, gpio11]
+                - if:
+                    properties:
+                      function:
+                        const: phy4_led1
+                  then:
+                    properties:
+                      groups:
+                        enum: [gpio8, gpio9, gpio10, gpio11]
+
 examples:
   - |
     #include <dt-bindings/interrupt-controller/arm-gic.h>
-- 
2.48.1



From ansuelsmth at gmail.com  Tue May 27 15:20:38 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Wed, 28 May 2025 00:20:38 +0200
Subject: [PATCH 6/6] pinctrl: airoha: add support for Airoha AN7583 PINs
In-Reply-To: <20250527222040.32000-1-ansuelsmth@gmail.com>
References: <20250527222040.32000-1-ansuelsmth@gmail.com>
Message-ID: <20250527222040.32000-7-ansuelsmth@gmail.com>

Add all the required entry to add suppot for Airoha AN7583 PINs.

Where possible the same function group are used from Airoha EN7581 to
reduce code duplication.

Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 drivers/pinctrl/mediatek/pinctrl-airoha.c | 733 ++++++++++++++++++++++
 1 file changed, 733 insertions(+)

diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
index 8c8d5b598f4f..0960649d5d66 100644
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
@@ -75,6 +75,7 @@
 #define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
 #define GPIO_PCM_SPI_CS2_MODE_P156_MASK		BIT(19)
 #define GPIO_PCM_SPI_CS2_MODE_P128_MASK		BIT(18)
+#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK	BIT(18)
 #define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
 #define GPIO_PCM_SPI_MODE_MASK			BIT(16)
 #define GPIO_PCM2_MODE_MASK			BIT(13)
@@ -129,6 +130,8 @@
 
 /* CONF */
 #define REG_I2C_SDA_E2				0x001c
+#define AN7583_I2C1_SCL_E2_MASK			BIT(16)
+#define AN7583_I2C1_SDA_E2_MASK			BIT(15)
 #define SPI_MISO_E2_MASK			BIT(14)
 #define SPI_MOSI_E2_MASK			BIT(13)
 #define SPI_CLK_E2_MASK				BIT(12)
@@ -136,12 +139,16 @@
 #define PCIE2_RESET_E2_MASK			BIT(10)
 #define PCIE1_RESET_E2_MASK			BIT(9)
 #define PCIE0_RESET_E2_MASK			BIT(8)
+#define AN7583_MDIO_0_E2_MASK			BIT(5)
+#define AN7583_MDC_0_E2_MASK			BIT(4)
 #define UART1_RXD_E2_MASK			BIT(3)
 #define UART1_TXD_E2_MASK			BIT(2)
 #define I2C_SCL_E2_MASK				BIT(1)
 #define I2C_SDA_E2_MASK				BIT(0)
 
 #define REG_I2C_SDA_E4				0x0020
+#define AN7583_I2C1_SCL_E4_MASK			BIT(16)
+#define AN7583_I2C1_SDA_E4_MASK			BIT(15)
 #define SPI_MISO_E4_MASK			BIT(14)
 #define SPI_MOSI_E4_MASK			BIT(13)
 #define SPI_CLK_E4_MASK				BIT(12)
@@ -149,6 +156,8 @@
 #define PCIE2_RESET_E4_MASK			BIT(10)
 #define PCIE1_RESET_E4_MASK			BIT(9)
 #define PCIE0_RESET_E4_MASK			BIT(8)
+#define AN7583_MDIO_0_E4_MASK			BIT(5)
+#define AN7583_MDC_0_E4_MASK			BIT(4)
 #define UART1_RXD_E4_MASK			BIT(3)
 #define UART1_TXD_E4_MASK			BIT(2)
 #define I2C_SCL_E4_MASK				BIT(1)
@@ -160,6 +169,8 @@
 #define REG_GPIO_H_E4				0x0030
 
 #define REG_I2C_SDA_PU				0x0044
+#define AN7583_I2C1_SCL_PU_MASK			BIT(16)
+#define AN7583_I2C1_SDA_PU_MASK			BIT(15)
 #define SPI_MISO_PU_MASK			BIT(14)
 #define SPI_MOSI_PU_MASK			BIT(13)
 #define SPI_CLK_PU_MASK				BIT(12)
@@ -167,12 +178,16 @@
 #define PCIE2_RESET_PU_MASK			BIT(10)
 #define PCIE1_RESET_PU_MASK			BIT(9)
 #define PCIE0_RESET_PU_MASK			BIT(8)
+#define AN7583_MDIO_0_PU_MASK			BIT(5)
+#define AN7583_MDC_0_PU_MASK			BIT(4)
 #define UART1_RXD_PU_MASK			BIT(3)
 #define UART1_TXD_PU_MASK			BIT(2)
 #define I2C_SCL_PU_MASK				BIT(1)
 #define I2C_SDA_PU_MASK				BIT(0)
 
 #define REG_I2C_SDA_PD				0x0048
+#define AN7583_I2C1_SDA_PD_MASK			BIT(16)
+#define AN7583_I2C1_SCL_PD_MASK			BIT(15)
 #define SPI_MISO_PD_MASK			BIT(14)
 #define SPI_MOSI_PD_MASK			BIT(13)
 #define SPI_CLK_PD_MASK				BIT(12)
@@ -180,6 +195,8 @@
 #define PCIE2_RESET_PD_MASK			BIT(10)
 #define PCIE1_RESET_PD_MASK			BIT(9)
 #define PCIE0_RESET_PD_MASK			BIT(8)
+#define AN7583_MDIO_0_PD_MASK			BIT(5)
+#define AN7583_MDC_0_PD_MASK			BIT(4)
 #define UART1_RXD_PD_MASK			BIT(3)
 #define UART1_TXD_PD_MASK			BIT(2)
 #define I2C_SCL_PD_MASK				BIT(1)
@@ -627,10 +644,223 @@ static const struct pingroup en7581_pinctrl_groups[] = {
 	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
 };
 
+static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
+	PINCTRL_PIN(2, "gpio0"),
+	PINCTRL_PIN(3, "gpio1"),
+	PINCTRL_PIN(4, "gpio2"),
+	PINCTRL_PIN(5, "gpio3"),
+	PINCTRL_PIN(6, "gpio4"),
+	PINCTRL_PIN(7, "gpio5"),
+	PINCTRL_PIN(8, "gpio6"),
+	PINCTRL_PIN(9, "gpio7"),
+	PINCTRL_PIN(10, "gpio8"),
+	PINCTRL_PIN(11, "gpio9"),
+	PINCTRL_PIN(12, "gpio10"),
+	PINCTRL_PIN(13, "gpio11"),
+	PINCTRL_PIN(14, "gpio12"),
+	PINCTRL_PIN(15, "gpio13"),
+	PINCTRL_PIN(16, "gpio14"),
+	PINCTRL_PIN(17, "gpio15"),
+	PINCTRL_PIN(18, "gpio16"),
+	PINCTRL_PIN(19, "gpio17"),
+	PINCTRL_PIN(20, "gpio18"),
+	PINCTRL_PIN(21, "gpio19"),
+	PINCTRL_PIN(22, "gpio20"),
+	PINCTRL_PIN(23, "gpio21"),
+	PINCTRL_PIN(24, "gpio22"),
+	PINCTRL_PIN(25, "gpio23"),
+	PINCTRL_PIN(26, "gpio24"),
+	PINCTRL_PIN(27, "gpio25"),
+	PINCTRL_PIN(28, "gpio26"),
+	PINCTRL_PIN(29, "gpio27"),
+	PINCTRL_PIN(30, "gpio28"),
+	PINCTRL_PIN(31, "gpio29"),
+	PINCTRL_PIN(32, "gpio30"),
+	PINCTRL_PIN(33, "gpio31"),
+	PINCTRL_PIN(34, "gpio32"),
+	PINCTRL_PIN(35, "gpio33"),
+	PINCTRL_PIN(36, "gpio34"),
+	PINCTRL_PIN(37, "gpio35"),
+	PINCTRL_PIN(38, "gpio36"),
+	PINCTRL_PIN(39, "gpio37"),
+	PINCTRL_PIN(40, "gpio38"),
+	PINCTRL_PIN(41, "i2c0_scl"),
+	PINCTRL_PIN(42, "i2c0_sda"),
+	PINCTRL_PIN(43, "i2c1_scl"),
+	PINCTRL_PIN(44, "i2c1_sda"),
+	PINCTRL_PIN(45, "spi_clk"),
+	PINCTRL_PIN(46, "spi_cs"),
+	PINCTRL_PIN(47, "spi_mosi"),
+	PINCTRL_PIN(48, "spi_miso"),
+	PINCTRL_PIN(49, "uart_txd"),
+	PINCTRL_PIN(50, "uart_rxd"),
+	PINCTRL_PIN(51, "pcie_reset0"),
+	PINCTRL_PIN(52, "pcie_reset1"),
+	PINCTRL_PIN(53, "mdc_0"),
+	PINCTRL_PIN(54, "mdio_0"),
+};
+
+static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
+static const int an7583_pon_tod_1pps_pins[] = { 32 };
+static const int an7583_gsw_tod_1pps_pins[] = { 32 };
+static const int an7583_sipo_pins[] = { 34, 35 };
+static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
+static const int an7583_mdio_pins[] = { 43, 44 };
+static const int an7583_uart2_pins[] = { 34, 35 };
+static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
+static const int an7583_hsuart_pins[] = { 30, 31 };
+static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
+static const int an7583_npu_uart_pins[] = { 7, 8 };
+static const int an7583_uart4_pins[] = { 7, 8 };
+static const int an7583_uart5_pins[] = { 23, 24 };
+static const int an7583_i2c0_pins[] = { 41, 42 };
+static const int an7583_i2c1_pins[] = { 43, 44 };
+static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
+static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
+static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
+static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
+static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
+static const int an7583_spi_quad_pins[] = { 25, 26 };
+static const int an7583_spi_cs1_pins[] = { 27 };
+static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
+static const int an7583_pcm_spi_rst_pins[] = { 14 };
+static const int an7583_pcm_spi_cs1_pins[] = { 24 };
+static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 };
+static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 };
+static const int an7583_gpio0_pins[] = { 2 };
+static const int an7583_gpio1_pins[] = { 3 };
+static const int an7583_gpio2_pins[] = { 4 };
+static const int an7583_gpio3_pins[] = { 5 };
+static const int an7583_gpio4_pins[] = { 6 };
+static const int an7583_gpio5_pins[] = { 7 };
+static const int an7583_gpio6_pins[] = { 8 };
+static const int an7583_gpio7_pins[] = { 9 };
+static const int an7583_gpio8_pins[] = { 10 };
+static const int an7583_gpio9_pins[] = { 11 };
+static const int an7583_gpio10_pins[] = { 12 };
+static const int an7583_gpio11_pins[] = { 13 };
+static const int an7583_gpio12_pins[] = { 14 };
+static const int an7583_gpio13_pins[] = { 15 };
+static const int an7583_gpio14_pins[] = { 16 };
+static const int an7583_gpio15_pins[] = { 17 };
+static const int an7583_gpio16_pins[] = { 18 };
+static const int an7583_gpio17_pins[] = { 19 };
+static const int an7583_gpio18_pins[] = { 20 };
+static const int an7583_gpio19_pins[] = { 21 };
+static const int an7583_gpio20_pins[] = { 22 };
+static const int an7583_gpio21_pins[] = { 24 };
+static const int an7583_gpio23_pins[] = { 25 };
+static const int an7583_gpio24_pins[] = { 26 };
+static const int an7583_gpio25_pins[] = { 27 };
+static const int an7583_gpio26_pins[] = { 28 };
+static const int an7583_gpio27_pins[] = { 29 };
+static const int an7583_gpio28_pins[] = { 30 };
+static const int an7583_gpio29_pins[] = { 31 };
+static const int an7583_gpio30_pins[] = { 32 };
+static const int an7583_gpio31_pins[] = { 33 };
+static const int an7583_gpio33_pins[] = { 35 };
+static const int an7583_gpio34_pins[] = { 36 };
+static const int an7583_gpio35_pins[] = { 37 };
+static const int an7583_gpio36_pins[] = { 38 };
+static const int an7583_gpio37_pins[] = { 39 };
+static const int an7583_gpio38_pins[] = { 40 };
+static const int an7583_gpio39_pins[] = { 41 };
+static const int an7583_gpio40_pins[] = { 42 };
+static const int an7583_gpio41_pins[] = { 43 };
+static const int an7583_gpio42_pins[] = { 44 };
+static const int an7583_gpio43_pins[] = { 45 };
+static const int an7583_gpio44_pins[] = { 46 };
+static const int an7583_gpio45_pins[] = { 47 };
+static const int an7583_gpio46_pins[] = { 48 };
+static const int an7583_gpio47_pins[] = { 49 };
+static const int an7583_gpio48_pins[] = { 50 };
+static const int an7583_pcie_reset0_pins[] = { 51 };
+static const int an7583_pcie_reset1_pins[] = { 52 };
+
+static const struct pingroup an7583_pinctrl_groups[] = {
+	PINCTRL_PIN_GROUP("pon", an7583_pon),
+	PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
+	PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
+	PINCTRL_PIN_GROUP("sipo", an7583_sipo),
+	PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
+	PINCTRL_PIN_GROUP("mdio", an7583_mdio),
+	PINCTRL_PIN_GROUP("uart2", an7583_uart2),
+	PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
+	PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
+	PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
+	PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
+	PINCTRL_PIN_GROUP("uart4", an7583_uart4),
+	PINCTRL_PIN_GROUP("uart5", an7583_uart5),
+	PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
+	PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
+	PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
+	PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
+	PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
+	PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
+	PINCTRL_PIN_GROUP("spi", an7583_spi),
+	PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
+	PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
+	PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
+	PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
+	PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
+	PINCTRL_PIN_GROUP("emmc", an7583_emmc),
+	PINCTRL_PIN_GROUP("pnand", an7583_pnand),
+	PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
+	PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
+	PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
+	PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
+	PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
+	PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
+	PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
+	PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
+	PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
+	PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
+	PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
+	PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
+	PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
+	PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
+	PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
+	PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
+	PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
+	PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
+	PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
+	PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
+	PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
+	PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
+	PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
+	PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
+	PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
+	PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
+	PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
+	PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
+	PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
+	PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
+	PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
+	PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
+	PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
+	PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
+	PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
+	PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
+	PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
+	PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
+	PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
+	PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
+	PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
+	PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
+	PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
+	PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
+	PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
+	PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
+	PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
+	PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
+	PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
+};
+
 static const char *const pon_groups[] = { "pon" };
 static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
 static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
 static const char *const mdio_groups[] = { "mdio" };
+static const char *const an7583_mdio_groups[] = { "mdio" };
 static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
 					   "hsuart_cts_rts", "uart4",
 					   "uart5" };
@@ -643,11 +873,16 @@ static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
 					      "pcm_spi_cs2_p156",
 					      "pcm_spi_cs2_p128",
 					      "pcm_spi_cs3", "pcm_spi_cs4" };
+static const char *const an7583_pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
+						     "pcm_spi_rst", "pcm_spi_cs1",
+						     "pcm_spi_cs2", "pcm_spi_cs3",
+						     "pcm_spi_cs4" };
 static const char *const i2s_groups[] = { "i2s" };
 static const char *const emmc_groups[] = { "emmc" };
 static const char *const pnand_groups[] = { "pnand" };
 static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
 						 "pcie_reset2" };
+static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
 static const char *const pwm_groups[] = { "gpio0", "gpio1",
 					  "gpio2", "gpio3",
 					  "gpio4", "gpio5",
@@ -686,6 +921,22 @@ static const char *const phy3_led1_groups[] = { "gpio43", "gpio44",
 						"gpio45", "gpio46" };
 static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
 						"gpio45", "gpio46" };
+static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2",
+						       "gpio3", "gpio4" };
+static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2",
+						       "gpio3", "gpio4" };
+static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2",
+						       "gpio3", "gpio4" };
+static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2",
+						       "gpio3", "gpio4" };
+static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9",
+						       "gpio10", "gpio11" };
+static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9",
+						       "gpio10", "gpio11" };
+static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9",
+						       "gpio10", "gpio11" };
+static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9",
+						       "gpio10", "gpio11" };
 
 static const struct airoha_pinctrl_func_group pon_func_group[] = {
 	{
@@ -763,6 +1014,25 @@ static const struct airoha_pinctrl_func_group mdio_func_group[] = {
 	},
 };
 
+static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
+	{
+		.name = "mdio",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_SGMII_MDIO_MODE_MASK,
+			GPIO_SGMII_MDIO_MODE_MASK
+		},
+		.regmap[1] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_MDC_IO_MASTER_MODE_MODE,
+			GPIO_MDC_IO_MASTER_MODE_MODE
+		},
+		.regmap_size = 2,
+	},
+};
+
 static const struct airoha_pinctrl_func_group uart_func_group[] = {
 	{
 		.name = "uart2",
@@ -1004,6 +1274,73 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
 	},
 };
 
+static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
+	{
+		.name = "pcm_spi",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_MODE_MASK,
+			GPIO_PCM_SPI_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_int",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_INT_MODE_MASK,
+			GPIO_PCM_INT_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_rst",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_RESET_MODE_MASK,
+			GPIO_PCM_RESET_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS1_MODE_MASK,
+			GPIO_PCM_SPI_CS1_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs2",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
+			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs3",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS3_MODE_MASK,
+			GPIO_PCM_SPI_CS3_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs4",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS4_MODE_MASK,
+			GPIO_PCM_SPI_CS4_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
 static const struct airoha_pinctrl_func_group i2s_func_group[] = {
 	{
 		.name = "i2s",
@@ -1074,6 +1411,28 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
 	},
 };
 
+static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
+	{
+		.name = "pcie_reset0",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PCIE_RESET0_MASK,
+			GPIO_PCIE_RESET0_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcie_reset1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PCIE_RESET1_MASK,
+			GPIO_PCIE_RESET1_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
 /* PWM */
 #define AIROHA_PINCTRL_PWM(gpio, mux_val)		\
 	{						\
@@ -1252,6 +1611,94 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
 			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
 };
 
+static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED("gpio1", GPIO_LAN3_LED1_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
 static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
 	PINCTRL_FUNC_DESC("pon", pon),
 	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
@@ -1278,6 +1725,31 @@ static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
 	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
 };
 
+static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
+	PINCTRL_FUNC_DESC("pon", pon),
+	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+	PINCTRL_FUNC_DESC("sipo", sipo),
+	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
+	PINCTRL_FUNC_DESC("uart", uart),
+	PINCTRL_FUNC_DESC("i2c", i2c),
+	PINCTRL_FUNC_DESC("jtag", jtag),
+	PINCTRL_FUNC_DESC("pcm", pcm),
+	PINCTRL_FUNC_DESC("spi", spi),
+	PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
+	PINCTRL_FUNC_DESC("emmc", emmc),
+	PINCTRL_FUNC_DESC("pnand", pnand),
+	PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
+	PINCTRL_FUNC_DESC("pwm", pwm),
+	PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
+	PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
+	PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
+	PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
+	PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
+	PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
+	PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
+	PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
+};
+
 static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
 	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
 	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
@@ -1339,6 +1811,62 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
 	PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
 };
 
+static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
+	PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
+	PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
+	PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
+	PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
+	PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
+	PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
+	PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
+	PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
+	PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
+	PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(18)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
+	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
+	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
+	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
+	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
+	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
+	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
+	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
+	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
+	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
+	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
+	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
+};
+
 static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
 	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
 	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
@@ -1400,6 +1928,62 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
 	PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
 };
 
+static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
+	PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
+	PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
+	PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
+	PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
+	PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
+	PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
+	PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
+	PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
+	PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
+	PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(18)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
+	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
+	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
+	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
+	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
+	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
+	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
+	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
+	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
+	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
+	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
+	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
+};
+
 static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
 	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
 	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
@@ -1461,6 +2045,62 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
 	PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
 };
 
+static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
+	PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
+	PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
+	PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
+	PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
+	PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
+	PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
+	PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
+	PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
+	PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
+	PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(18)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
+	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
+	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
+	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
+	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
+	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
+	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
+	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
+	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
+	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
+	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
+	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
+};
+
 static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
 	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
 	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
@@ -1522,12 +2162,73 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
 	PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
 };
 
+static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
+	PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
+	PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
+	PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
+	PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
+	PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
+	PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
+	PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
+	PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
+	PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
+	PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(18)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
+	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
+	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
+	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
+	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
+	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
+	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
+	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
+	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
+	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
+	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
+};
+
 static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
 	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
 	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
 	PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
 };
 
+static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
+	PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+	PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+};
+
 static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
 					    struct pinctrl_gpio_range *range,
 					    int pin)
@@ -2261,8 +2962,40 @@ static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
 	},
 };
 
+static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
+	.pins = an7583_pinctrl_pins,
+	.num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
+	.grps = an7583_pinctrl_groups,
+	.num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
+	.funcs = an7583_pinctrl_funcs,
+	.num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
+	.confs_info = {
+		[AIROHA_PINCTRL_CONFS_PULLUP] = {
+			.confs = an7583_pinctrl_pullup_conf,
+			.num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+			.confs = an7583_pinctrl_pulldown_conf,
+			.num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+			.confs = en7581_pinctrl_drive_e2_conf,
+			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+			.confs = an7583_pinctrl_drive_e4_conf,
+			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+			.confs = an7583_pinctrl_pcie_rst_od_conf,
+			.num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
+		},
+	},
+};
+
 static const struct of_device_id airoha_pinctrl_of_match[] = {
 	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
+	{ .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
-- 
2.48.1



From patchwork-bot+netdevbpf at kernel.org  Tue May 27 17:50:33 2025
From: patchwork-bot+netdevbpf at kernel.org (patchwork-bot+netdevbpf at kernel.org)
Date: Wed, 28 May 2025 00:50:33 +0000
Subject: [PATCH v4 net] net: airoha: Fix an error handling path in
 airoha_alloc_gdm_port()
In-Reply-To: <1b94b91345017429ed653e2f05d25620dc2823f9.1746715755.git.christophe.jaillet@wanadoo.fr>
References: <1b94b91345017429ed653e2f05d25620dc2823f9.1746715755.git.christophe.jaillet@wanadoo.fr>
Message-ID: <174839343325.1843884.14339456243155225714.git-patchwork-notify@kernel.org>

Hello:

This patch was applied to netdev/net.git (main)
by Jakub Kicinski <kuba at kernel.org>:

On Sat, 24 May 2025 09:29:11 +0200 you wrote:
> If register_netdev() fails, the error handling path of the probe will not
> free the memory allocated by the previous airoha_metadata_dst_alloc() call
> because port->dev->reg_state will not be NETREG_REGISTERED.
> 
> So, an explicit airoha_metadata_dst_free() call is needed in this case to
> avoid a memory leak.
> 
> [...]

Here is the summary with links:
  - [v4,net] net: airoha: Fix an error handling path in airoha_alloc_gdm_port()
    https://git.kernel.org/netdev/net/c/c59783780c8a

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html




From patchwork-bot+netdevbpf at kernel.org  Tue May 27 18:20:42 2025
From: patchwork-bot+netdevbpf at kernel.org (patchwork-bot+netdevbpf at kernel.org)
Date: Wed, 28 May 2025 01:20:42 +0000
Subject: [net-next PATCH 0/3] net: dsa: mt7530: Add AN7583 support + PHY
In-Reply-To: <20250522165313.6411-1-ansuelsmth@gmail.com>
References: <20250522165313.6411-1-ansuelsmth@gmail.com>
Message-ID: <174839524201.1849945.3988099260497875532.git-patchwork-notify@kernel.org>

Hello:

This series was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba at kernel.org>:

On Thu, 22 May 2025 18:53:08 +0200 you wrote:
> This small series add the required changes to make Airoha AN7583
> Switch and Internal PHY work due to strange default configuration.
> 
> Christian Marangi (3):
>   dt-bindings: net: dsa: mediatek,mt7530: Add airoha,an7583-switch
>   net: dsa: mt7530: Add AN7583 support
>   net: phy: mediatek: Add Airoha AN7583 PHY support
> 
> [...]

Here is the summary with links:
  - [net-next,1/3] dt-bindings: net: dsa: mediatek,mt7530: Add airoha,an7583-switch
    https://git.kernel.org/netdev/net-next/c/fef184880923
  - [net-next,2/3] net: dsa: mt7530: Add AN7583 support
    https://git.kernel.org/netdev/net-next/c/d76556db10bf
  - [net-next,3/3] net: phy: mediatek: Add Airoha AN7583 PHY support
    https://git.kernel.org/netdev/net-next/c/8bc3c234dcb6

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
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From ck.hu at mediatek.com  Tue May 27 18:52:04 2025
From: ck.hu at mediatek.com (=?utf-8?B?Q0sgSHUgKOiDoeS/iuWFiSk=?=)
Date: Wed, 28 May 2025 01:52:04 +0000
Subject: [PATCH 5/5] drm/mediatek: Add eDP phy driver for mt8196
In-Reply-To: <20250418065313.8972-6-bincai.liu@mediatek.com>
References: <20250418065313.8972-1-bincai.liu@mediatek.com>
	 <20250418065313.8972-6-bincai.liu@mediatek.com>
Message-ID: <912b07f99e5a8757fbd5934c0b72779b1be31bb4.camel@mediatek.com>

On Fri, 2025-04-18 at 14:52 +0800, Bincai Liu wrote:
> Add code to support eDP phy for mt8196.
> 
> Signed-off-by: Bincai Liu <bincai.liu at mediatek.com>
> ---
>  drivers/phy/mediatek/Makefile      |   1 +
>  drivers/phy/mediatek/phy-mtk-edp.c | 262 +++++++++++++++++++++++++++++
>  2 files changed, 263 insertions(+)
>  create mode 100644 drivers/phy/mediatek/phy-mtk-edp.c
> 
> diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
> index 1b8088df71e8..49d9ea42497a 100644
> --- a/drivers/phy/mediatek/Makefile
> +++ b/drivers/phy/mediatek/Makefile
> @@ -4,6 +4,7 @@
>  #
>  
>  obj-$(CONFIG_PHY_MTK_DP)		+= phy-mtk-dp.o
> +obj-$(CONFIG_PHY_MTK_DP)		+= phy-mtk-edp.o

phy-mtk-dp.c support mt8188 edp phy and mt8195 edp phy function.
phy-mtk-edp.c support mt8196 edp phy function.
So I would like to rename file as:

phy-mtk-dp-mt8188.c (support mt8188/mt8195 dp/edp phy function, use "mediatek-dp-phy-mt8188" as driver name)
phy-mtk-dp-mt8196.c (support mt8196 edp phy function, use "mediatek-dp-phy-mt8196" as driver name)

When dp driver register phy driver, use the according sub driver name.

Regards,
CK

>  obj-$(CONFIG_PHY_MTK_PCIE)		+= phy-mtk-pcie.o
>  obj-$(CONFIG_PHY_MTK_TPHY)		+= phy-mtk-tphy.o
>  obj-$(CONFIG_PHY_MTK_UFS)		+= phy-mtk-ufs.o
> 


From Nancy.Lin at mediatek.com  Tue May 27 21:01:55 2025
From: Nancy.Lin at mediatek.com (=?utf-8?B?TmFuY3kgTGluICjmnpfmrKPonqIp?=)
Date: Wed, 28 May 2025 04:01:55 +0000
Subject: [PATCH 1/2] dt-bindings: regulator: mediatek: Add MT8196 vmm
 controller
In-Reply-To: <d21e1775-d5d4-4f58-865e-0cb33d14f371@kernel.org>
References: <20250522150426.3418225-1-nancy.lin@mediatek.com>
	 <20250522150426.3418225-2-nancy.lin@mediatek.com>
	 <d21e1775-d5d4-4f58-865e-0cb33d14f371@kernel.org>
Message-ID: <9ada04bb73e980f981d3b933552f0eda47d4fd26.camel@mediatek.com>

Hi Krzysztof,

Thanks for your review.

On Thu, 2025-05-22 at 17:09 +0200, Krzysztof Kozlowski wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 22/05/2025 17:03, Nancy.Lin wrote:
> > From: Nancy Lin <nancy.lin at mediatek.com>
> > 
> > Add a device tree binding document for the MediaTek MT8196 VMM
> > (Vcore
> > for MultiMedia) regulator controller. The VMM controller acts as
> > the
> > main power supplier for multimedia power domains, such as those
> > used
> > by display, video encode and decode subsystems. It provides virtual
> > regulators that serve as the power sources for various multimedia
> > IPs,
> 
> Virtual regulators do not sound real, so feels like you want some
> sort
> of power domains?
> 
This regulator supplies power to the power domain. Before the power
domain can be powered up, the MediaTek PM driver first enables the
regulator that the power domain relies on, and then powers up the
domain. While "virtual" might not be the best term, it accurately
describes a regulator used to control the power switch.

Ultimately, the VCP (uP) handles the on/off control of the regulator.
Therefore, we encapsulate it as a standard regulator in the kernel.

The internal control of the VMM regulator is as follows:
   kernel                 HWCCF                          VCP (uP)
|--------------|      |--------------|   irq    |---------------------|
| VMM reglator | ---> | hardware     |  ----->  | get buck on/off irq |
|              |      | voter        |          | and then turn on/off|
|              |      |              |          | buck                |
|--------------|      |--------------|          |---------------------|

When the regulator needs to be turned on or off, it uses the voter
provided by hwccf to cast a vote for on/off. The VCP then receives the
corresponding IRQ for the regulator and performs the buck on/off
accordingly.

> A nit, subject: drop second/last, redundant "bindings". The
> "dt-bindings" prefix is already stating that these are bindings.
> See also:
> https://urldefense.com/v3/__https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst*L18__;Iw!!CTRNKA9wMg0ARbw!lBqtzZ8DmC6f2kNnLXRCpHsof7XOYvrIMG4o_DXuvjYbg1SyFRrXrtEMLjIxS31cq82hqQowrczWRg$
> 

OK, I will remove the binding/document word in commit message body.
And change title to
   regulator: dt-bindings: Add MT8196 vmm controller


> > and coordinates with the hardware common clock framework (hwccf)
> > and
> > the Video Companion Processor (VCP) to manage the power domains of
> > these components. The regulator is controlled by the VCP firmware,
> > and the operating system signals its requirement through a voting
> > hardware block (hwccf).
> > 
> > Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
> > ---
> > ?.../mediatek,mt8196-vmm-regulator.yaml??????? | 70
> > +++++++++++++++++++
> > ?1 file changed, 70 insertions(+)
> > ?create mode 100644
> > Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-
> > regulator.yaml
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-
> > regulator.yaml
> > b/Documentation/devicetree/bindings/regulator/mediatek,mt8196-vmm-
> > regulator.yaml
> > new file mode 100644
> > index 000000000000..a50e35c2e238
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt8196-
> > vmm-regulator.yaml
> > @@ -0,0 +1,70 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > "https://urldefense.com/v3/__http://devicetree.org/schemas/regulato
> > r/mediatek,mt8196-vmm-
> > regulator.yaml*__;Iw!!CTRNKA9wMg0ARbw!lBqtzZ8DmC6f2kNnLXRCpHsof7XOY
> > vrIMG4o_DXuvjYbg1SyFRrXrtEMLjIxS31cq82hqQrOgUATjA$?"
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!lBqtzZ8DmC6f2kNnLXRCpHsof7XOYvrIMG4o_DXuvjYbg1SyFRrXrtEMLjIxS31cq82hqQr4UitgLg$
> > +
> > +title: MediaTek MT8196 VMM (Vcore for MultiMedia) Regulator
> > Controller
> > +
> > +maintainers:
> > +? - Nancy Lin <nancy.lin at mediatek.com>
> > +
> > +description: |
> > +? The MediaTek MT8196 VMM (Vcore for Multi Media) controller acts
> > as the
> > +? main power supplier for multimedia power domains, such as those
> > used by
> > +? display, video encode and decode subsystems. The VMM hardware
> > block
> > +? provides virtual regulators that serve as the power sources
> > (suppliers)
> > +? for various multimedia IPs. It coordinates with the MediaTek
> > hardware
> > +? common clock framework (HWCCF) and the Video Companion Processor
> > (VCP)
> > +? to manage the power domains of these multimedia components.
> > +
> > +? Each child node under the VMM node represents a virtual
> > regulator
> > +? (e.g., vdisp, vdec-vcore) and must specify a 'regulator-name'.
> > +
> > +properties:
> > +? compatible:
> > +??? const: "mediatek,mt8196-vmm"
> 
> Not tested...
> 
My bad, I accidentally added extra quotation marks, but I ran
dt_binding_check and didn't see this error being                      
detected.

> > +
> > +? mediatek,hw-ccf:
> > +??? $ref: /schemas/types.yaml#/definitions/phandle
> > +??? description: Phandle to the hardware common clock framework
> > syscon controller.
> 
> No, you cannot express clocks with syscon.
> 
HWCCF is MediaTek's internal naming; the functionality of the hardware
IP is voter. We use the IP to vote for buck on/off, and the VCP will
get the voting result to perform buck on/off. I will refine the
naming/description to "voter."

> > +
> > +? mediatek,vcp:
> > +??? $ref: /schemas/types.yaml#/definitions/phandle
> > +??? description: Phandle to the Video Co-Processor (VCP) node.
> 
> For what purpose?
> 
This is used to ensure that the VCP uP is ready to receive the hwccf
IRQ and handle the corresponding buck on/off operations.

> > +
> > +patternProperties:
> > +? "^(vdisp|vdec-vcore)$":
> 
> Redundant nodes, useless. Drop these completely.
> 
OK.
> 
> > +??? type: object
> > +??? description: |
> > +????? Virtual regulator for a specific multimedia domain.
> > +????? The node name should match the supported regulator (e.g.,
> > vdisp, vdec-vcore).
> > +??? properties:
> > +????? regulator-name:
> 
> No, you cannot start redefining properties. This binding is nowhere
> close to hardware description. Looks like some copy-paste downstream
> driver, so binding to fulfill driver needs.
> 
> Please rework to match hardware. I suggest reaching internally to get
> some help how upstream drivers and bindings look like *prior* sending
> downstream code.
> 
I will review and refine the binding internally before submitting it.
Thanks!

Best regards,
Nancy

> Best regards,
> Krzysztof


From Nancy.Lin at mediatek.com  Tue May 27 21:24:26 2025
From: Nancy.Lin at mediatek.com (=?utf-8?B?TmFuY3kgTGluICjmnpfmrKPonqIp?=)
Date: Wed, 28 May 2025 04:24:26 +0000
Subject: [PATCH 2/2] soc: mediatek: Add MT8196 VMM driver support
In-Reply-To: <ea79d8fd-8134-4d14-92f6-f656be20cd9f@kernel.org>
References: <20250522150426.3418225-1-nancy.lin@mediatek.com>
	 <20250522150426.3418225-3-nancy.lin@mediatek.com>
	 <ea79d8fd-8134-4d14-92f6-f656be20cd9f@kernel.org>
Message-ID: <6c41738df74af4fc1e409cb781d55e765ff38529.camel@mediatek.com>

Hi Krzysztof,

Thanks for your review.

On Thu, 2025-05-22 at 17:10 +0200, Krzysztof Kozlowski wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 22/05/2025 17:03, Nancy.Lin wrote:
> > From: Nancy Lin <nancy.lin at mediatek.com>
> > 
> > Add a driver for the MediaTek MT8196 VMM (Vcore for MultiMedia)
> > controller, which acts as the main power supplier for multimedia
> > power
> > domains such as display, video encode, and video decode on MediaTek
> > SoCs.
> > 
> > The VMM controller provides virtual regulators for multimedia IPs
> > and
> > coordinates with the hardware common clock framework (hwccf) and
> > the
> > Video Companioin Processor (VCP) to manage power domains. The
> > driver
> > uses a hardware voter through HWCCF to notify the VCP to turn on or
> > off VMM-related bucks.
> > 
> > Signed-off-by: Nancy Lin <nancy.lin at mediatek.com>
> > ---
> > ?drivers/soc/mediatek/Kconfig?????? |? 12 +
> > ?drivers/soc/mediatek/Makefile????? |?? 1 +
> > ?drivers/soc/mediatek/mtk-vmm-drv.c | 471
> > +++++++++++++++++++++++++++++
> > ?3 files changed, 484 insertions(+)
> > ?create mode 100644 drivers/soc/mediatek/mtk-vmm-drv.c
> > 
> > diff --git a/drivers/soc/mediatek/Kconfig
> > b/drivers/soc/mediatek/Kconfig
> > index d7293977f06e..4db4a0876083 100644
> > --- a/drivers/soc/mediatek/Kconfig
> > +++ b/drivers/soc/mediatek/Kconfig
> > @@ -69,6 +69,18 @@ config MTK_MMSYS
> > ??????? Say yes here to add support for the MediaTek Multimedia
> > ??????? Subsystem (MMSYS).
> > 
> > +config MTK_VMM
> > +???? tristate "MediaTek VMM driver"
> > +???? help
> > +?????? Say Y here to enable support for the MediaTek VMM (Vcore
> > for
> > +?????? MultiMedia) controller, which acts as the main power
> > supplier
> > +?????? for multimedia power domains such as display, video encode
> > and
> > +?????? decode on MediaTek SoCs. The VMM controller provides
> > virtual
> > +?????? regulators for multimedia IPs and coordinates with the
> > hardware
> > +?????? common clock framework (hwccf) and the Video Companion
> > Processor
> > +?????? (VCP) to manage power domains. The VMM driver uses hardware
> > voter
> > +?????? through hwccf to notify VCP to turn on/off VMM-related
> > bucks.
> > +
> > ?config MTK_SVS
> > ????? tristate "MediaTek Smart Voltage Scaling(SVS)"
> > ????? depends on NVMEM_MTK_EFUSE && NVMEM
> > diff --git a/drivers/soc/mediatek/Makefile
> > b/drivers/soc/mediatek/Makefile
> > index 0665573e3c4b..2b2071614ac4 100644
> > --- a/drivers/soc/mediatek/Makefile
> > +++ b/drivers/soc/mediatek/Makefile
> > @@ -6,6 +6,7 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
> > ?obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> > ?obj-$(CONFIG_MTK_REGULATOR_COUPLER) += mtk-regulator-coupler.o
> > ?obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> > +obj-$(CONFIG_MTK_VMM) += mtk-vmm-drv.o
> > ?obj-$(CONFIG_MTK_MMSYS) += mtk-mutex.o
> > ?obj-$(CONFIG_MTK_SVS) += mtk-svs.o
> > ?obj-$(CONFIG_MTK_SOCINFO) += mtk-socinfo.o
> > diff --git a/drivers/soc/mediatek/mtk-vmm-drv.c
> > b/drivers/soc/mediatek/mtk-vmm-drv.c
> > new file mode 100644
> > index 000000000000..de4ceb7d59fa
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mtk-vmm-drv.c
> > @@ -0,0 +1,471 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (c) 2025 MediaTek Inc.
> > + * Author: Yunfei Dong <yunfei.dong at mediatek.com>
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/device.h>
> > +#include <linux/kthread.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_domain.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/regmap.h>
> > +#include <linux/regulator/driver.h>
> > +#if IS_ENABLED(CONFIG_MTK_VCP_RPROC)
> 
> And that's the proof you send some sort of downstream code.
> 
> This does not exist.
> 
Sorry, I forgot add reference patch. This patch is based on [1].

[1] Add vcp driver
https://patchwork.kernel.org/project/linux-mediatek/list/?series=949232



> > +#include <linux/remoteproc.h>
> > +#include <linux/remoteproc/mtk_vcp_public.h>
> > +#endif
> > +
> > +#define mtk_vmm_dbg(dev, fmt, args...) \
> > +???? dev_dbg(dev, "[vmm] %s(%d): " fmt "\n", __func__, __LINE__,
> > ##args)
> 
> No, you do not get your own debug code.
> 
> NAK.
> 
> This is nowhere close to upstream code. Don't send us downstream
> patterns please.
> 
OK, I will remove own debug code and refine it. Thanks!

Best regards,
Nancy


> Best regards,
> Krzysztof


From krzk at kernel.org  Tue May 27 23:29:33 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 08:29:33 +0200
Subject: [PATCH 1/2] dt-bindings: regulator: mediatek: Add MT8196 vmm
 controller
In-Reply-To: <9ada04bb73e980f981d3b933552f0eda47d4fd26.camel@mediatek.com>
References: <20250522150426.3418225-1-nancy.lin@mediatek.com>
 <20250522150426.3418225-2-nancy.lin@mediatek.com>
 <d21e1775-d5d4-4f58-865e-0cb33d14f371@kernel.org>
 <9ada04bb73e980f981d3b933552f0eda47d4fd26.camel@mediatek.com>
Message-ID: <5be237d3-5b8d-42ee-a492-d5d7b075fe81@kernel.org>

On 28/05/2025 06:01, Nancy Lin (???) wrote:
>>
>> Virtual regulators do not sound real, so feels like you want some
>> sort
>> of power domains?
>>
> This regulator supplies power to the power domain. Before the power
> domain can be powered up, the MediaTek PM driver first enables the
> regulator that the power domain relies on, and then powers up the
> domain. While "virtual" might not be the best term, it accurately
> describes a regulator used to control the power switch.
> 
> Ultimately, the VCP (uP) handles the on/off control of the regulator.
> Therefore, we encapsulate it as a standard regulator in the kernel.
> 
> The internal control of the VMM regulator is as follows:
>    kernel                 HWCCF                          VCP (uP)
> |--------------|      |--------------|   irq    |---------------------|
> | VMM reglator | ---> | hardware     |  ----->  | get buck on/off irq |
> |              |      | voter        |          | and then turn on/off|
> |              |      |              |          | buck                |
> |--------------|      |--------------|          |---------------------|
> 
> When the regulator needs to be turned on or off, it uses the voter
> provided by hwccf to cast a vote for on/off. The VCP then receives the
> corresponding IRQ for the regulator and performs the buck on/off
> accordingly.

OK, thanks for explanation.

> 
...

> 
>>> +
>>> +? mediatek,hw-ccf:
>>> +??? $ref: /schemas/types.yaml#/definitions/phandle
>>> +??? description: Phandle to the hardware common clock framework
>>> syscon controller.
>>
>> No, you cannot express clocks with syscon.
>>
> HWCCF is MediaTek's internal naming; the functionality of the hardware
> IP is voter. We use the IP to vote for buck on/off, and the VCP will
> get the voting result to perform buck on/off. I will refine the
> naming/description to "voter."


OK, that was a bit confusing, but now I have more questions:

Why isn't this a child of the HWCCF? You do not have here any resources,
so this looks just to instantiate device for Linux.

Looking at your diagram earlier (maybe include it in binding description
if this stays as is at the end) I would imagine phandle only to hwccf.
But you have two phandles - HWCCF and VCP.

So maybe this is part of VCP device, not HWCCF? I don't know. I am
afraid the moment I will suggest you something someone from Collabora
will be pointing out that my advice us wrong and I don't know this
hardware. Yeah, I don't know it. You should know it.

> 
>>> +
>>> +? mediatek,vcp:
>>> +??? $ref: /schemas/types.yaml#/definitions/phandle
>>> +??? description: Phandle to the Video Co-Processor (VCP) node.
>>
>> For what purpose?
>>
> This is used to ensure that the VCP uP is ready to receive the hwccf
> IRQ and handle the corresponding buck on/off operations.
> 
>>> +
>>> +patternProperties:
>>> +? "^(vdisp|vdec-vcore)$":
>>
>> Redundant nodes, useless. Drop these completely.
>>
> OK.
Best regards,
Krzysztof


From irui.wang at mediatek.com  Tue May 27 23:36:28 2025
From: irui.wang at mediatek.com (Irui Wang)
Date: Wed, 28 May 2025 14:36:28 +0800
Subject: [PATCH v2 2/6] media: mediatek: encoder: Add support for common firmware interface
In-Reply-To: <20250528063633.14054-1-irui.wang@mediatek.com>
References: <20250528063633.14054-1-irui.wang@mediatek.com>
Message-ID: <20250528063633.14054-3-irui.wang@mediatek.com>

The existing encoder firmware interface implied just one type of codec:
H.264. Future encoders may support additional codecs; however adding
entire sets of interfaces for them is not scalable.

Instead, a new "common" firmware interface is defined for non codec
specific messages. The new messages encapsulate the old ones for
backward compatibility.

This patch adds support for these new messages.

Signed-off-by: Irui Wang <irui.wang at mediatek.com>
---
 .../vcodec/encoder/mtk_vcodec_enc_drv.h       |  3 ++
 .../mediatek/vcodec/encoder/venc_drv_if.c     |  3 +-
 .../mediatek/vcodec/encoder/venc_ipi_msg.h    | 26 +++++++++++++
 .../mediatek/vcodec/encoder/venc_vpu_if.c     | 37 ++++++++++++-------
 4 files changed, 54 insertions(+), 15 deletions(-)

diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
index b1277bcfcf53..426b1398f815 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
@@ -16,6 +16,7 @@
 
 #define MTK_ENC_CTX_IS_EXT(ctx) ((ctx)->dev->venc_pdata->uses_ext)
 #define MTK_ENC_IOVA_IS_34BIT(ctx) ((ctx)->dev->venc_pdata->uses_34bit)
+#define MTK_ENC_DRV_IS_COMM(ctx) (((ctx)->dev->venc_pdata->uses_common_fw_iface))
 
 /**
  * struct mtk_vcodec_enc_pdata - compatible data for each IC
@@ -29,6 +30,7 @@
  * @num_output_formats: number of entries in output_formats
  * @core_id: stand for h264 or vp8 encode index
  * @uses_34bit: whether the encoder uses 34-bit iova
+ * @uses_common_fw_iface: whether the encoder uses common driver interface
  */
 struct mtk_vcodec_enc_pdata {
 	bool uses_ext;
@@ -40,6 +42,7 @@ struct mtk_vcodec_enc_pdata {
 	size_t num_output_formats;
 	u8 core_id;
 	bool uses_34bit;
+	bool uses_common_fw_iface;
 };
 
 /*
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c b/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c
index e83747b8d69a..f8c9349c18c0 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c
@@ -19,13 +19,14 @@
 int venc_if_init(struct mtk_vcodec_enc_ctx *ctx, unsigned int fourcc)
 {
 	int ret = 0;
+	const bool uses_common_fw_iface = MTK_ENC_DRV_IS_COMM(ctx);
 
 	switch (fourcc) {
 	case V4L2_PIX_FMT_VP8:
 		ctx->enc_if = &venc_vp8_if;
 		break;
 	case V4L2_PIX_FMT_H264:
-		ctx->enc_if = &venc_h264_if;
+		ctx->enc_if = uses_common_fw_iface ? &venc_if : &venc_h264_if;
 		break;
 	default:
 		return -EINVAL;
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_ipi_msg.h b/drivers/media/platform/mediatek/vcodec/encoder/venc_ipi_msg.h
index bb16d96a7f57..ce3c2c8059fb 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/venc_ipi_msg.h
+++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_ipi_msg.h
@@ -45,6 +45,20 @@ struct venc_ap_ipi_msg_init {
 	uint64_t venc_inst;
 };
 
+/**
+ * struct venc_ap_ipi_msg_init_comm - AP to VPU init cmd structure
+ * @base: AP to VPU init cmd structure
+ * @codec_type: encoder type
+ * @reserved: reserved field
+ * @shared_iova: shared iova
+ */
+struct venc_ap_ipi_msg_init_comm {
+	struct venc_ap_ipi_msg_init base;
+	u32 codec_type;
+	u32 reserved;
+	u64 shared_iova;
+};
+
 /**
  * struct venc_ap_ipi_msg_set_param - AP to VPU set_param cmd structure
  * @msg_id:	message id (AP_IPIMSG_XXX_ENC_SET_PARAM)
@@ -175,6 +189,18 @@ struct venc_vpu_ipi_msg_init {
 	uint32_t venc_abi_version;
 };
 
+/**
+ * struct venc_vpu_ipi_msg_init_comm - VPU ack AP init cmd structure
+ * @init_ack: AP init cmd structure
+ * @vpu_vsi_addr: VSI address from VPU
+ * @reserved: reserved field
+ */
+struct venc_vpu_ipi_msg_init_comm {
+	struct venc_vpu_ipi_msg_init init_ack;
+	u32 vpu_vsi_addr;
+	u32 reserved;
+};
+
 /**
  * struct venc_vpu_ipi_msg_set_param - VPU ack AP set_param cmd structure
  * @msg_id:	message id (VPU_IPIMSG_XXX_ENC_SET_PARAM_DONE)
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c b/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c
index 51bb7ee141b9..537b9955932e 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c
@@ -10,24 +10,25 @@
 
 static void handle_enc_init_msg(struct venc_vpu_inst *vpu, const void *data)
 {
-	const struct venc_vpu_ipi_msg_init *msg = data;
+	const struct venc_vpu_ipi_msg_init_comm *msg = data;
+	struct mtk_vcodec_fw *fw = vpu->ctx->dev->fw_handler;
 
-	vpu->inst_addr = msg->vpu_inst_addr;
-	vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler,
-					     msg->vpu_inst_addr);
+	vpu->inst_addr = msg->init_ack.vpu_inst_addr;
+	vpu->vsi = mtk_vcodec_fw_map_dm_addr(fw, vpu->inst_addr);
 
 	/* Firmware version field value is unspecified on MT8173. */
-	if (mtk_vcodec_fw_get_type(vpu->ctx->dev->fw_handler) == VPU)
+	if (mtk_vcodec_fw_get_type(fw) == VPU)
 		return;
 
 	/* Check firmware version. */
-	mtk_venc_debug(vpu->ctx, "firmware version: 0x%x\n", msg->venc_abi_version);
-	switch (msg->venc_abi_version) {
+	mtk_venc_debug(vpu->ctx, "firmware version: 0x%x\n",
+		       msg->init_ack.venc_abi_version);
+	switch (msg->init_ack.venc_abi_version) {
 	case 1:
 		break;
 	default:
 		mtk_venc_err(vpu->ctx, "unhandled firmware version 0x%x\n",
-			     msg->venc_abi_version);
+			     msg->init_ack.venc_abi_version);
 		vpu->failure = 1;
 		break;
 	}
@@ -132,7 +133,8 @@ static int vpu_enc_send_msg(struct venc_vpu_inst *vpu, void *msg,
 int vpu_enc_init(struct venc_vpu_inst *vpu)
 {
 	int status;
-	struct venc_ap_ipi_msg_init out;
+	size_t msg_size;
+	struct venc_ap_ipi_msg_init_comm out;
 
 	init_waitqueue_head(&vpu->wq_hd);
 	vpu->signaled = 0;
@@ -149,9 +151,16 @@ int vpu_enc_init(struct venc_vpu_inst *vpu)
 	}
 
 	memset(&out, 0, sizeof(out));
-	out.msg_id = AP_IPIMSG_ENC_INIT;
-	out.venc_inst = (unsigned long)vpu;
-	if (vpu_enc_send_msg(vpu, &out, sizeof(out))) {
+	out.base.msg_id = AP_IPIMSG_ENC_INIT;
+	out.base.venc_inst = (unsigned long)vpu;
+	if (MTK_ENC_DRV_IS_COMM(vpu->ctx)) {
+		out.codec_type = vpu->ctx->q_data[MTK_Q_DATA_DST].fmt->fourcc;
+		msg_size = sizeof(struct venc_ap_ipi_msg_init_comm);
+	} else {
+		msg_size = sizeof(struct venc_ap_ipi_msg_init);
+	}
+
+	if (vpu_enc_send_msg(vpu, &out, msg_size)) {
 		mtk_venc_err(vpu->ctx, "AP_IPIMSG_ENC_INIT fail");
 		return -EINVAL;
 	}
@@ -260,7 +269,7 @@ static int vpu_enc_encode_32bits(struct venc_vpu_inst *vpu,
 		sizeof(struct venc_ap_ipi_msg_enc);
 	struct venc_ap_ipi_msg_enc_ext out;
 
-	mtk_venc_debug(vpu->ctx, "bs_mode %d ->", bs_mode);
+	mtk_venc_debug(vpu->ctx, "%s, bs_mode %d ->", __func__, bs_mode);
 
 	memset(&out, 0, sizeof(out));
 	out.base.msg_id = AP_IPIMSG_ENC_ENCODE;
@@ -305,7 +314,7 @@ static int vpu_enc_encode_34bits(struct venc_vpu_inst *vpu,
 	struct venc_ap_ipi_msg_enc_ext_34 out;
 	size_t msg_size = sizeof(struct venc_ap_ipi_msg_enc_ext_34);
 
-	mtk_venc_debug(vpu->ctx, "bs_mode %d ->", bs_mode);
+	mtk_venc_debug(vpu->ctx, "%s, bs_mode %d ->", __func__, bs_mode);
 
 	memset(&out, 0, sizeof(out));
 	out.msg_id = AP_IPIMSG_ENC_ENCODE;
-- 
2.45.2



From irui.wang at mediatek.com  Tue May 27 23:36:26 2025
From: irui.wang at mediatek.com (Irui Wang)
Date: Wed, 28 May 2025 14:36:26 +0800
Subject: [PATCH v2 0/6] Add support for MT8196 video encoder
Message-ID: <20250528063633.14054-1-irui.wang@mediatek.com>

This patch series add support for MT8196 video encoder.
patch 1~3: Add a new encoder driver interface for new VCP firmware.
patch 4~6: Add MT8196 encoder driver platform data.

About adding new driver support, the v4l2-compliance report shows:
"Total for mtk-vcodec-enc device /dev/video3: 47, Succeeded: 46, Failed: 1, Warnings: 0"
The 1 Failed case is not caused by current patch set.

This patch set depends on "media: mediatek: vcodec: support video decoder in mt8196"[1]

[1] https://patchwork.linuxtv.org/project/linux-media/list/?series=15232

Change in v2:
 - Add support for VCP encode process.
 - Add MT8196 encoder driver platform data.
 - Rebase encoder patch onto decoder's patch set.
 - Fix some review comments in v1.

Irui Wang (6):
  media: mediatek: encoder: Add a new encoder driver interface
  media: mediatek: encoder: Add support for common firmware interface
  media: mediatek: encoder: Add support for VCP encode process
  media: mediatek: encoder: Add a new platform data member
  dt-bindings: media: mediatek: encoder: Add encoder dt-bindings for
    MT8196
  media: mediatek: encoder: Add MT8196 encoder compatible data

 .../media/mediatek,vcodec-encoder.yaml        |  12 +
 .../mediatek/vcodec/common/mtk_vcodec_fw.c    |  19 +
 .../mediatek/vcodec/common/mtk_vcodec_fw.h    |   2 +
 .../vcodec/common/mtk_vcodec_fw_priv.h        |   1 +
 .../vcodec/common/mtk_vcodec_fw_vcp.c         |   6 +
 .../platform/mediatek/vcodec/encoder/Makefile |   1 +
 .../mediatek/vcodec/encoder/mtk_vcodec_enc.c  |  37 +-
 .../vcodec/encoder/mtk_vcodec_enc_drv.c       |  28 +
 .../vcodec/encoder/mtk_vcodec_enc_drv.h       |  15 +-
 .../vcodec/encoder/venc/venc_common_if.c      | 678 ++++++++++++++++++
 .../vcodec/encoder/venc/venc_h264_if.c        |   8 +-
 .../mediatek/vcodec/encoder/venc_drv_if.c     |   3 +-
 .../mediatek/vcodec/encoder/venc_drv_if.h     |  11 +-
 .../mediatek/vcodec/encoder/venc_ipi_msg.h    |  26 +
 .../mediatek/vcodec/encoder/venc_vpu_if.c     |  51 +-
 15 files changed, 843 insertions(+), 55 deletions(-)
 create mode 100644 drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c

-- 
2.45.2



From irui.wang at mediatek.com  Tue May 27 23:36:29 2025
From: irui.wang at mediatek.com (Irui Wang)
Date: Wed, 28 May 2025 14:36:29 +0800
Subject: [PATCH v2 3/6] media: mediatek: encoder: Add support for VCP encode process
In-Reply-To: <20250528063633.14054-1-irui.wang@mediatek.com>
References: <20250528063633.14054-1-irui.wang@mediatek.com>
Message-ID: <20250528063633.14054-4-irui.wang@mediatek.com>

When encoding by VCP interface, encoder driver need change to VCP path:
Firstly, set encoder driver fw type to 'VCP'. Then, allocate RC buffers
by the VCP device. Finally, send the shared memory address into VCP and
map the encoder vsi address by the VCP shared memory address.

Signed-off-by: Irui Wang <irui.wang at mediatek.com>
---
 .../mediatek/vcodec/common/mtk_vcodec_fw.c    |  6 +++++
 .../mediatek/vcodec/common/mtk_vcodec_fw.h    |  1 +
 .../vcodec/common/mtk_vcodec_fw_priv.h        |  1 +
 .../vcodec/common/mtk_vcodec_fw_vcp.c         |  6 +++++
 .../vcodec/encoder/mtk_vcodec_enc_drv.c       |  3 +++
 .../vcodec/encoder/venc/venc_common_if.c      | 23 ++++++++++++++-----
 .../mediatek/vcodec/encoder/venc_vpu_if.c     | 14 ++++++++++-
 7 files changed, 47 insertions(+), 7 deletions(-)

diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
index 0381acceda25..7a504f093bd8 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
@@ -105,3 +105,9 @@ int mtk_vcodec_fw_get_type(struct mtk_vcodec_fw *fw)
 	return fw->type;
 }
 EXPORT_SYMBOL_GPL(mtk_vcodec_fw_get_type);
+
+struct device *mtk_vcodec_fw_get_dev(struct mtk_vcodec_fw *fw)
+{
+	return fw->ops->get_fw_dev(fw);
+}
+EXPORT_SYMBOL_GPL(mtk_vcodec_fw_get_dev);
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h
index e7304a7dd3e0..56c26b91651e 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h
@@ -43,5 +43,6 @@ int mtk_vcodec_fw_ipi_send(struct mtk_vcodec_fw *fw, int id,
 int mtk_vcodec_fw_get_type(struct mtk_vcodec_fw *fw);
 int mtk_vcodec_fw_get_ipi(enum mtk_vcodec_fw_type type, int hw_id);
 int mtk_vcodec_fw_get_venc_ipi(enum mtk_vcodec_fw_type type);
+struct device *mtk_vcodec_fw_get_dev(struct mtk_vcodec_fw *fw);
 
 #endif /* _MTK_VCODEC_FW_H_ */
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_priv.h b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_priv.h
index 0a2a9b010244..710c83c871f4 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_priv.h
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_priv.h
@@ -29,6 +29,7 @@ struct mtk_vcodec_fw_ops {
 	int (*ipi_send)(struct mtk_vcodec_fw *fw, int id, void *buf,
 			unsigned int len, unsigned int wait);
 	void (*release)(struct mtk_vcodec_fw *fw);
+	struct device *(*get_fw_dev)(struct mtk_vcodec_fw *fw);
 };
 
 #if IS_ENABLED(CONFIG_VIDEO_MEDIATEK_VCODEC_VPU)
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
index f6b93e1bcbf3..646e3944dd4f 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
@@ -432,6 +432,11 @@ static void mtk_vcodec_vcp_release(struct mtk_vcodec_fw *fw)
 {
 }
 
+static struct device *mtk_vcodec_vcp_get_fw_dev(struct mtk_vcodec_fw *fw)
+{
+	return fw->vcp->vcp_device->dev;
+}
+
 static const struct mtk_vcodec_fw_ops mtk_vcodec_vcp_msg = {
 	.load_firmware = mtk_vcodec_vcp_load_firmware,
 	.get_vdec_capa = mtk_vcodec_vcp_get_vdec_capa,
@@ -440,6 +445,7 @@ static const struct mtk_vcodec_fw_ops mtk_vcodec_vcp_msg = {
 	.ipi_register = mtk_vcodec_vcp_set_ipi_register,
 	.ipi_send = mtk_vcodec_vcp_ipi_send,
 	.release = mtk_vcodec_vcp_release,
+	.get_fw_dev = mtk_vcodec_vcp_get_fw_dev,
 };
 
 struct mtk_vcodec_fw *mtk_vcodec_fw_vcp_init(void *priv, enum mtk_vcodec_fw_use fw_use)
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
index a1e4483abcdb..bb913dfe5f04 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
@@ -252,6 +252,9 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
 	} else if (!of_property_read_u32(pdev->dev.of_node, "mediatek,scp",
 					 &rproc_phandle)) {
 		fw_type = SCP;
+	} else if (!of_property_read_u32(pdev->dev.of_node, "mediatek,vcp",
+					 &rproc_phandle)) {
+		fw_type = VCP;
 	} else {
 		dev_err(&pdev->dev, "[MTK VCODEC] Could not get venc IPI device");
 		return -ENODEV;
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c
index 8092929e9297..61aa7d9d70c9 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c
@@ -478,8 +478,13 @@ static void venc_free_rc_buf(struct venc_inst *inst,
 {
 	int i;
 	struct device *dev;
+	struct mtk_vcodec_fw *fw = inst->ctx->dev->fw_handler;
+
+	if (mtk_vcodec_fw_get_type(fw) == VCP)
+		dev = mtk_vcodec_fw_get_dev(fw);
+	else
+		dev = &inst->ctx->dev->plat_dev->dev;
 
-	dev = &inst->ctx->dev->plat_dev->dev;
 	mtk_venc_mem_free(inst, dev, &bufs->rc_code);
 
 	for (i = 0; i < core_num; i++)
@@ -528,12 +533,18 @@ static int venc_alloc_rc_buf(struct venc_inst *inst,
 	struct device *dev;
 	void *tmp_va;
 
-	dev = &inst->ctx->dev->plat_dev->dev;
-	if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_code))
-		return -ENOMEM;
+	if (mtk_vcodec_fw_get_type(fw) == VCP) {
+		dev = mtk_vcodec_fw_get_dev(fw);
+		if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_code))
+			return -ENOMEM;
+	} else {
+		dev = &inst->ctx->dev->plat_dev->dev;
+		if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_code))
+			return -ENOMEM;
 
-	tmp_va = mtk_vcodec_fw_map_dm_addr(fw, bufs->rc_code.pa);
-	memcpy(bufs->rc_code.va, tmp_va, bufs->rc_code.size);
+		tmp_va = mtk_vcodec_fw_map_dm_addr(fw, bufs->rc_code.pa);
+		memcpy(bufs->rc_code.va, tmp_va, bufs->rc_code.size);
+	}
 
 	for (i = 0; i < core_num; i++) {
 		if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_info[i]))
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c b/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c
index 537b9955932e..80db7d97ab3f 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c
@@ -8,13 +8,23 @@
 #include "venc_ipi_msg.h"
 #include "venc_vpu_if.h"
 
+#define VSI_OFFSET_MASK 0x0FFFFFFF
+
 static void handle_enc_init_msg(struct venc_vpu_inst *vpu, const void *data)
 {
 	const struct venc_vpu_ipi_msg_init_comm *msg = data;
 	struct mtk_vcodec_fw *fw = vpu->ctx->dev->fw_handler;
+	u64 pa_start, vsi_offset;
 
 	vpu->inst_addr = msg->init_ack.vpu_inst_addr;
-	vpu->vsi = mtk_vcodec_fw_map_dm_addr(fw, vpu->inst_addr);
+
+	if (mtk_vcodec_fw_get_type(fw) == VCP) {
+		pa_start = (u64)fw->vcp->iova_addr;
+		vsi_offset = (msg->vpu_vsi_addr & VSI_OFFSET_MASK) - (pa_start & VSI_OFFSET_MASK);
+		vpu->vsi = mtk_vcodec_fw_map_dm_addr(fw, ENCODER_MEM) + vsi_offset;
+	} else {
+		vpu->vsi = mtk_vcodec_fw_map_dm_addr(fw, vpu->inst_addr);
+	}
 
 	/* Firmware version field value is unspecified on MT8173. */
 	if (mtk_vcodec_fw_get_type(fw) == VPU)
@@ -155,6 +165,8 @@ int vpu_enc_init(struct venc_vpu_inst *vpu)
 	out.base.venc_inst = (unsigned long)vpu;
 	if (MTK_ENC_DRV_IS_COMM(vpu->ctx)) {
 		out.codec_type = vpu->ctx->q_data[MTK_Q_DATA_DST].fmt->fourcc;
+		if (mtk_vcodec_fw_get_type(vpu->ctx->dev->fw_handler) == VCP)
+			out.shared_iova = vpu->ctx->dev->fw_handler->vcp->iova_addr;
 		msg_size = sizeof(struct venc_ap_ipi_msg_init_comm);
 	} else {
 		msg_size = sizeof(struct venc_ap_ipi_msg_init);
-- 
2.45.2



From irui.wang at mediatek.com  Tue May 27 23:36:27 2025
From: irui.wang at mediatek.com (Irui Wang)
Date: Wed, 28 May 2025 14:36:27 +0800
Subject: [PATCH v2 1/6] media: mediatek: encoder: Add a new encoder driver interface
In-Reply-To: <20250528063633.14054-1-irui.wang@mediatek.com>
References: <20250528063633.14054-1-irui.wang@mediatek.com>
Message-ID: <20250528063633.14054-2-irui.wang@mediatek.com>

Introduce a new encoder kernel driver interface to ensure compatibility
with the updated encoder software driver running in firmware.
The new driver interface is expected to support more encoder formats,
share more encode parameters between kernel and firmware.

Signed-off-by: Irui Wang <irui.wang at mediatek.com>
---
 .../mediatek/vcodec/common/mtk_vcodec_fw.c    |  13 +
 .../mediatek/vcodec/common/mtk_vcodec_fw.h    |   1 +
 .../platform/mediatek/vcodec/encoder/Makefile |   1 +
 .../mediatek/vcodec/encoder/mtk_vcodec_enc.c  |  14 +-
 .../vcodec/encoder/mtk_vcodec_enc_drv.h       |   8 +-
 .../vcodec/encoder/venc/venc_common_if.c      | 667 ++++++++++++++++++
 .../vcodec/encoder/venc/venc_h264_if.c        |   8 +-
 .../mediatek/vcodec/encoder/venc_drv_if.h     |  11 +-
 8 files changed, 705 insertions(+), 18 deletions(-)
 create mode 100644 drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c

diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
index 4ed7639dfa30..0381acceda25 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
@@ -18,6 +18,19 @@ int mtk_vcodec_fw_get_ipi(enum mtk_vcodec_fw_type type, int hw_id)
 }
 EXPORT_SYMBOL_GPL(mtk_vcodec_fw_get_ipi);
 
+int mtk_vcodec_fw_get_venc_ipi(enum mtk_vcodec_fw_type type)
+{
+	switch (type) {
+	case SCP:
+		return SCP_IPI_VENC_H264;
+	case VCP:
+		return VCP_IPI_ENCODER;
+	default:
+		return -EINVAL;
+	}
+}
+EXPORT_SYMBOL_GPL(mtk_vcodec_fw_get_venc_ipi);
+
 struct mtk_vcodec_fw *mtk_vcodec_fw_select(void *priv, enum mtk_vcodec_fw_type type,
 					   enum mtk_vcodec_fw_use fw_use)
 {
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h
index 142e2e87905c..e7304a7dd3e0 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h
@@ -42,5 +42,6 @@ int mtk_vcodec_fw_ipi_send(struct mtk_vcodec_fw *fw, int id,
 			   void *buf, unsigned int len, unsigned int wait);
 int mtk_vcodec_fw_get_type(struct mtk_vcodec_fw *fw);
 int mtk_vcodec_fw_get_ipi(enum mtk_vcodec_fw_type type, int hw_id);
+int mtk_vcodec_fw_get_venc_ipi(enum mtk_vcodec_fw_type type);
 
 #endif /* _MTK_VCODEC_FW_H_ */
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/Makefile b/drivers/media/platform/mediatek/vcodec/encoder/Makefile
index e621b5b7e5e6..9d3229d56e39 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/Makefile
+++ b/drivers/media/platform/mediatek/vcodec/encoder/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_VIDEO_MEDIATEK_VCODEC) += mtk-vcodec-enc.o
 
 mtk-vcodec-enc-y := venc/venc_vp8_if.o \
 		venc/venc_h264_if.o \
+		venc/venc_common_if.o \
 		mtk_vcodec_enc.o \
 		mtk_vcodec_enc_drv.o \
 		mtk_vcodec_enc_pm.o \
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
index dcafb1303c29..03512bf7a072 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
@@ -81,11 +81,11 @@ static int vidioc_venc_s_ctrl(struct v4l2_ctrl *ctrl)
 		break;
 	case V4L2_CID_MPEG_VIDEO_H264_PROFILE:
 		mtk_v4l2_venc_dbg(2, ctx, "V4L2_CID_MPEG_VIDEO_H264_PROFILE val = %d", ctrl->val);
-		p->h264_profile = ctrl->val;
+		p->profile = ctrl->val;
 		break;
 	case V4L2_CID_MPEG_VIDEO_H264_LEVEL:
 		mtk_v4l2_venc_dbg(2, ctx, "V4L2_CID_MPEG_VIDEO_H264_LEVEL val = %d", ctrl->val);
-		p->h264_level = ctrl->val;
+		p->level = ctrl->val;
 		break;
 	case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD:
 		mtk_v4l2_venc_dbg(2, ctx, "V4L2_CID_MPEG_VIDEO_H264_I_PERIOD val = %d", ctrl->val);
@@ -386,8 +386,8 @@ static void mtk_venc_set_param(struct mtk_vcodec_enc_ctx *ctx,
 		mtk_v4l2_venc_err(ctx, "Unsupported fourcc =%d", q_data_src->fmt->fourcc);
 		break;
 	}
-	param->h264_profile = enc_params->h264_profile;
-	param->h264_level = enc_params->h264_level;
+	param->profile = enc_params->profile;
+	param->level = enc_params->level;
 
 	/* Config visible resolution */
 	param->width = q_data_src->visible_width;
@@ -403,8 +403,8 @@ static void mtk_venc_set_param(struct mtk_vcodec_enc_ctx *ctx,
 
 	mtk_v4l2_venc_dbg(0, ctx,
 			  "fmt 0x%x, P/L %d/%d w/h %d/%d buf %d/%d fps/bps %d/%d gop %d i_per %d",
-			  param->input_yuv_fmt, param->h264_profile,
-			  param->h264_level, param->width, param->height,
+			  param->input_yuv_fmt, param->profile,
+			  param->level, param->width, param->height,
 			  param->buf_width, param->buf_height,
 			  param->frm_rate, param->bitrate,
 			  param->gop_size, param->intra_period);
@@ -1174,6 +1174,8 @@ static void mtk_venc_worker(struct work_struct *work)
 		frm_buf.fb_addr[i].size =
 				(size_t)src_buf->vb2_buf.planes[i].length;
 	}
+	frm_buf.num_planes = src_buf->vb2_buf.num_planes;
+
 	bs_buf.va = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
 	bs_buf.dma_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
 	bs_buf.size = (size_t)dst_buf->vb2_buf.planes[0].length;
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
index 0bd85d0fb379..b1277bcfcf53 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
@@ -69,8 +69,8 @@ enum mtk_encode_param {
  * @framerate_denom: frame rate denominator. ex: framerate_num=30 and
  *		     framerate_denom=1 means FPS is 30
  * @h264_max_qp: Max value for H.264 quantization parameter
- * @h264_profile: V4L2 defined H.264 profile
- * @h264_level: V4L2 defined H.264 level
+ * @profile: V4L2 defined profile
+ * @level: V4L2 defined level
  * @force_intra: force/insert intra frame
  */
 struct mtk_enc_params {
@@ -84,8 +84,8 @@ struct mtk_enc_params {
 	unsigned int	framerate_num;
 	unsigned int	framerate_denom;
 	unsigned int	h264_max_qp;
-	unsigned int	h264_profile;
-	unsigned int	h264_level;
+	unsigned int	profile;
+	unsigned int	level;
 	unsigned int	force_intra;
 };
 
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c
new file mode 100644
index 000000000000..8092929e9297
--- /dev/null
+++ b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c
@@ -0,0 +1,667 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#include "../mtk_vcodec_enc.h"
+#include "../mtk_vcodec_enc_drv.h"
+#include "../venc_drv_base.h"
+#include "../venc_drv_if.h"
+#include "../venc_vpu_if.h"
+#include "../../common/mtk_vcodec_intr.h"
+#include "../../common/mtk_vcodec_util.h"
+
+#define SEQ_HEADER_SIZE 1024
+#define PPS_SIZE 128
+#define MAX_DPB_SIZE 16
+#define MAX_VENC_CORE 3
+#define VENC_CONFIG_LENGTH 115
+#define VENC_CONFIG_DATA 128
+#define VENC_PIC_BITSTREAM_BYTE_CNT 0x0098
+
+/**
+ * enum venc_bs_mode - encode bitstream mode
+ * @VENC_BS_MODE_SPS: encode sps
+ * @VENC_BS_MODE_PPS: encode pps
+ * @VENC_BS_MODE_VPS: encode vps
+ * @VENC_BS_MODE_SEQ_HDR: encode sequence header
+ * @VENC_BS_MODE_FRAME: encode frame
+ * @VENC_BS_MODE_FRAME_FINAL: encode final frame
+ * @VENC_BS_MODE_MAX: max value
+ */
+enum venc_bs_mode {
+	VENC_BS_MODE_SPS = 0,
+	VENC_BS_MODE_PPS,
+	VENC_BS_MODE_VPS,
+	VENC_BS_MODE_SEQ_HDR,
+	VENC_BS_MODE_FRAME,
+	VENC_BS_MODE_FRAME_FINAL,
+	VENC_BS_MODE_MAX
+};
+
+/**
+ * struct venc_config - Structure for encoder configuration
+ *                      AP-W/R : AP is writer/reader on this item
+ *                      MCU-W/R: MCU is write/reader on this item
+ * @input_fourcc: input format fourcc
+ * @bitrate: target bitrate (in bps)
+ * @pic_w: visible width of resolution
+ * @pic_h: visible height of resolution
+ * @buf_w: buffer alignment width of resolution
+ * @buf_h: buffer alignment height of resolution
+ * @gop_size: group of picture size (IDR frame period)
+ * @intra_period: I frame period
+ * @framerate: frame rate in fps
+ * @profile: profile_idc in SPS
+ * @level: level_idc in SPS
+ * @core_num: encoder core num
+ * @dpb_size: encode dpb size
+ * @reserved: reserved fields config
+ */
+struct venc_config {
+	__u32 input_fourcc;
+	__u32 bitrate;
+	__u32 pic_w;
+	__u32 pic_h;
+	__u32 buf_w;
+	__u32 buf_h;
+	__u32 gop_size;
+	__u32 intra_period;
+	__u32 framerate;
+	__u32 profile;
+	__u32 level;
+	__u32 core_num;
+	__u32 dpb_size;
+	__u32 reserved[VENC_CONFIG_LENGTH];
+};
+
+/**
+ * struct venc_config_data - Structure for configuration data
+ * @config_data: extended configuration data besides the basic configuration
+ */
+struct venc_config_data {
+	unsigned int config_data[VENC_CONFIG_DATA];
+};
+
+/**
+ * struct venc_work_buf - Structure for working buffer information
+ *                               AP-W/R : AP is writer/reader on this item
+ *                               MCU-W/R: MCU is write/reader on this item
+ * @iova: IO virtual address
+ * @pa: physical address
+ * @pa_64: for 64bit pa padding
+ * @va: virtual address
+ * @va_padding: for 64bit va padding
+ * @size: buffer size
+ * @size_padding: for 64bit size padding
+ */
+struct venc_work_buf {
+	unsigned long long iova;
+	union {
+		unsigned int pa;
+		unsigned long long pa_64;
+	};
+	union {
+		void *va;
+		unsigned long long va_padding;
+	};
+	union {
+		unsigned int size;
+		unsigned long long size_padding;
+	};
+};
+
+/**
+ * struct venc_work_buf_list - Structure for encode working buffer list
+ * @rc_code: RC code buffer
+ * @rc_info: RC info buffer
+ * @luma: luma buffer
+ * @chroma: chroma buffer
+ * @sub_luma: sub luma buffer
+ * @sub_write: sub write buffer
+ * @col_mv: col_mv buffer
+ * @wpp: wpp buffer
+ * @wpp_nbm: wpp nbm buffer
+ * @skip_frame: skip frame buffer
+ */
+struct venc_work_buf_list {
+	struct venc_work_buf rc_code;
+	struct venc_work_buf rc_info[MAX_VENC_CORE];
+	struct venc_work_buf luma[MAX_DPB_SIZE];
+	struct venc_work_buf chroma[MAX_DPB_SIZE];
+	struct venc_work_buf sub_luma[MAX_DPB_SIZE];
+	struct venc_work_buf sub_write[MAX_DPB_SIZE];
+	struct venc_work_buf col_mv[MAX_DPB_SIZE];
+	struct venc_work_buf wpp[MAX_VENC_CORE];
+	struct venc_work_buf wpp_nbm[MAX_VENC_CORE];
+	struct venc_work_buf skip_frame;
+};
+
+/**
+ * struct venc_info -  Structure for encode frame and bs information
+ * @fb_addr: frame buffer address array
+ * @fb_size: frame buffer size array
+ * @bs_addr: bitstream buffer address
+ * @bs_size: bitstream buffer size
+ */
+struct venc_info {
+	unsigned long long fb_addr[VIDEO_MAX_PLANES];
+	unsigned int fb_size[VIDEO_MAX_PLANES];
+	unsigned long long bs_addr;
+	unsigned long long bs_size;
+};
+
+/**
+ * struct venc_vsi - Structure for VCP driver control and info share
+ *                   AP-W/R : AP is writer/reader on this item
+ *                   VCP-W/R: VCP is write/reader on this item
+ * @config: encoder configuration
+ * @data: encoder configuration data
+ * @bufs: encoder working buffers
+ * @venc: encoder information
+ */
+struct venc_vsi {
+	struct venc_config config;
+	struct venc_config_data data;
+	struct venc_work_buf_list bufs;
+	struct venc_info venc;
+};
+
+/**
+ * struct venc_inst - Structure for encoder instance
+ * @hw_base: hardware io address
+ * @pps_buf: PPS buffer
+ * @seq_buf: sequence header buffer
+ * @work_buf_allocated: work buffer allocated or not
+ * @frm_cnt: encoded frame count
+ * @skip_frm_cnt: encoded skip frame count
+ * @prepend_hdr: prepend header flag
+ * @vpu_inst: vpu instance
+ * @vsi: encode vsi
+ * @ctx: encoder context
+ */
+struct venc_inst {
+	void __iomem *hw_base;
+	struct mtk_vcodec_mem pps_buf;
+	struct mtk_vcodec_mem seq_buf;
+	bool work_buf_allocated;
+	unsigned int frm_cnt;
+	unsigned int skip_frm_cnt;
+	unsigned int prepend_hdr;
+	struct venc_vpu_inst vpu_inst;
+	struct venc_vsi *vsi;
+	struct mtk_vcodec_enc_ctx *ctx;
+};
+
+static int venc_init(struct mtk_vcodec_enc_ctx *ctx)
+{
+	int ret = 0;
+	struct venc_inst *inst;
+
+	inst = kzalloc(sizeof(*inst), GFP_KERNEL);
+	if (!inst)
+		return -ENOMEM;
+
+	inst->ctx = ctx;
+	inst->vpu_inst.ctx = ctx;
+	inst->vpu_inst.id = mtk_vcodec_fw_get_venc_ipi(ctx->dev->fw_handler->type);
+	inst->hw_base = mtk_vcodec_get_reg_addr(inst->ctx->dev->reg_base, VENC_SYS);
+
+	ret = vpu_enc_init(&inst->vpu_inst);
+	inst->vsi = (struct venc_vsi *)inst->vpu_inst.vsi;
+
+	if (ret)
+		kfree(inst);
+	else
+		ctx->drv_handle = inst;
+
+	return ret;
+}
+
+static inline u32 venc_read_reg(struct venc_inst *inst, u32 addr)
+{
+	return readl(inst->hw_base + addr);
+}
+
+static unsigned int venc_wait_encode_done(struct venc_inst *inst)
+{
+	unsigned int irq_status = 0;
+	struct mtk_vcodec_enc_ctx *ctx = (struct mtk_vcodec_enc_ctx *)inst->ctx;
+
+	if (!mtk_vcodec_wait_for_done_ctx(ctx, MTK_INST_IRQ_RECEIVED,
+					  WAIT_INTR_TIMEOUT_MS, 0)) {
+		irq_status = ctx->irq_status;
+		mtk_venc_debug(ctx, "irq_status %x <-", irq_status);
+	}
+	return irq_status;
+}
+
+static void venc_set_bufs(struct venc_inst *inst,
+			  struct venc_frm_buf *frm_buf,
+			  struct mtk_vcodec_mem *bs_buf)
+{
+	unsigned int i;
+
+	if (frm_buf) {
+		for (i = 0; i < frm_buf->num_planes; i++) {
+			inst->vsi->venc.fb_addr[i] = frm_buf->fb_addr[i].dma_addr;
+			inst->vsi->venc.fb_size[i] = frm_buf->fb_addr[i].size;
+			mtk_venc_debug(inst->ctx, "%s: fb_buf[%d]: %llx(%d)\n",
+				       __func__, i,
+				       inst->vsi->venc.fb_addr[i],
+				       inst->vsi->venc.fb_size[i]);
+		}
+	}
+
+	if (bs_buf) {
+		inst->vsi->venc.bs_addr = bs_buf->dma_addr;
+		inst->vsi->venc.bs_size = bs_buf->size;
+		mtk_venc_debug(inst->ctx, "%s: bs_buf: %llx(%d)\n",
+			       __func__,
+			       inst->vsi->venc.bs_addr,
+			       (unsigned int)inst->vsi->venc.bs_size);
+	}
+}
+
+static int venc_encode_sps(struct venc_inst *inst,
+			   struct mtk_vcodec_mem *bs_buf,
+			   unsigned int *bs_size)
+{
+	int ret = 0;
+	unsigned int irq_status;
+
+	venc_set_bufs(inst, NULL, bs_buf);
+	ret = vpu_enc_encode(&inst->vpu_inst, VENC_BS_MODE_SPS, NULL, bs_buf, NULL);
+	if (ret)
+		return ret;
+
+	irq_status = venc_wait_encode_done(inst);
+	if (irq_status != MTK_VENC_IRQ_STATUS_SPS) {
+		mtk_venc_err(inst->ctx, "expect irq status %d", MTK_VENC_IRQ_STATUS_SPS);
+		return -EINVAL;
+	}
+
+	*bs_size = venc_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT);
+	mtk_venc_debug(inst->ctx, "sps bs size %d <-", *bs_size);
+
+	return ret;
+}
+
+static int venc_encode_pps(struct venc_inst *inst,
+			   struct mtk_vcodec_mem *bs_buf,
+			   unsigned int *bs_size)
+{
+	int ret = 0;
+	unsigned int irq_status;
+
+	venc_set_bufs(inst, NULL, bs_buf);
+	ret = vpu_enc_encode(&inst->vpu_inst, VENC_BS_MODE_PPS, NULL, bs_buf, NULL);
+	if (ret)
+		return ret;
+
+	irq_status = venc_wait_encode_done(inst);
+	if (irq_status != MTK_VENC_IRQ_STATUS_PPS) {
+		mtk_venc_err(inst->ctx, "expect irq status %d", MTK_VENC_IRQ_STATUS_PPS);
+		return -EINVAL;
+	}
+
+	*bs_size = venc_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT);
+	mtk_venc_debug(inst->ctx, "pps bs size %d <-", *bs_size);
+
+	return ret;
+}
+
+static int venc_encode_header(struct venc_inst *inst,
+			      struct mtk_vcodec_mem *bs_buf,
+			      unsigned int *bs_size)
+{
+	int ret = 0;
+	unsigned int bs_size_sps;
+	unsigned int bs_size_pps;
+
+	ret = venc_encode_sps(inst, bs_buf, &bs_size_sps);
+	if (ret)
+		return ret;
+
+	ret = venc_encode_pps(inst, &inst->pps_buf, &bs_size_pps);
+	if (ret)
+		return ret;
+
+	memcpy(bs_buf->va + bs_size_sps, inst->pps_buf.va, bs_size_pps);
+	*bs_size = bs_size_sps + bs_size_pps;
+
+	return ret;
+}
+
+static int venc_encode_frame(struct venc_inst *inst,
+			     struct venc_frm_buf *frm_buf,
+			     struct mtk_vcodec_mem *bs_buf,
+			     unsigned int *bs_size)
+{
+	int ret = 0;
+	unsigned int irq_status;
+
+	venc_set_bufs(inst, frm_buf, bs_buf);
+	ret = vpu_enc_encode(&inst->vpu_inst, VENC_BS_MODE_FRAME, frm_buf, bs_buf, NULL);
+	if (ret)
+		return ret;
+
+	irq_status = venc_wait_encode_done(inst);
+	if (irq_status != MTK_VENC_IRQ_STATUS_FRM) {
+		mtk_venc_err(inst->ctx, "expect irq status %d", MTK_VENC_IRQ_STATUS_FRM);
+		return -EINVAL;
+	}
+
+	*bs_size = venc_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT);
+
+	++inst->frm_cnt;
+
+	return ret;
+}
+
+static int venc_encode(void *handle,
+		       enum venc_start_opt opt,
+		       struct venc_frm_buf *frm_buf,
+		       struct mtk_vcodec_mem *bs_buf,
+		       struct venc_done_result *result)
+{
+	int ret = 0;
+	struct venc_inst *inst = (struct venc_inst *)handle;
+	struct mtk_vcodec_enc_ctx *ctx;
+	unsigned int bs_size_hdr;
+
+	if (WARN_ON(!inst || !inst->vsi))
+		return -EINVAL;
+
+	ctx = inst->ctx;
+
+	mtk_venc_debug(ctx, "%s: opt: %d\n", __func__, opt);
+
+	enable_irq(ctx->dev->enc_irq);
+	switch (opt) {
+	case VENC_START_OPT_ENCODE_SEQUENCE_HEADER: {
+		ret = venc_encode_header(inst, bs_buf, &bs_size_hdr);
+		if (ret)
+			goto encode_err;
+
+		result->bs_size = bs_size_hdr;
+		result->is_key_frm = false;
+		break;
+	}
+
+	case VENC_START_OPT_ENCODE_FRAME: {
+		if (!inst->prepend_hdr) {
+			ret = venc_encode_frame(inst, frm_buf, bs_buf, &result->bs_size);
+			if (ret)
+				goto encode_err;
+
+			result->is_key_frm = inst->vpu_inst.is_key_frm;
+			break;
+		}
+
+		ret = venc_encode_header(inst, &inst->seq_buf, &bs_size_hdr);
+		if (ret)
+			goto encode_err;
+
+		ret = venc_encode_frame(inst, frm_buf, bs_buf, &result->bs_size);
+		if (ret)
+			goto encode_err;
+
+		memmove(bs_buf->va + bs_size_hdr, bs_buf->va, result->bs_size);
+		memcpy(bs_buf->va, inst->seq_buf.va, bs_size_hdr);
+		result->bs_size += bs_size_hdr;
+
+		inst->prepend_hdr = 0;
+		result->is_key_frm = inst->vpu_inst.is_key_frm;
+		break;
+	}
+
+	default:
+		mtk_venc_err(inst->ctx, "venc_opt %d not supported", opt);
+		ret = -EINVAL;
+		break;
+	}
+
+encode_err:
+	disable_irq(ctx->dev->enc_irq);
+	mtk_venc_debug(ctx, "opt %d, return %d", opt, ret);
+
+	return ret;
+}
+
+static int mtk_venc_mem_alloc(struct venc_inst *inst,
+			      struct device *dev,
+			      struct venc_work_buf *buf)
+{
+	dma_addr_t dma_addr;
+
+	if (WARN_ON(!dev || !buf))
+		return -EINVAL;
+
+	if (buf->size == 0)
+		return 0;
+
+	buf->va = dma_alloc_coherent(dev, buf->size, &dma_addr, GFP_KERNEL);
+	if (!buf->va)
+		return -ENOMEM;
+
+	buf->iova = (unsigned long long)dma_addr;
+
+	mtk_venc_debug(inst->ctx, "allocate buffer, size: %d, va: %p, iova: 0x%llx",
+		       buf->size, buf->va, buf->iova);
+
+	return 0;
+}
+
+static void mtk_venc_mem_free(struct venc_inst *inst,
+			      struct device *dev,
+			      struct venc_work_buf *buf)
+{
+	if (WARN_ON(!dev || !buf))
+		return;
+
+	if (!buf->va)
+		return;
+
+	mtk_venc_debug(inst->ctx, "free buffer, size: %d, va: %p, iova: 0x%llx",
+		       buf->size, buf->va, buf->iova);
+
+	dma_free_coherent(dev, buf->size, buf->va, buf->iova);
+	buf->va = NULL;
+	buf->iova = 0;
+	buf->size = 0;
+}
+
+static void venc_free_rc_buf(struct venc_inst *inst,
+			     struct venc_work_buf_list *bufs,
+			     unsigned int core_num)
+{
+	int i;
+	struct device *dev;
+
+	dev = &inst->ctx->dev->plat_dev->dev;
+	mtk_venc_mem_free(inst, dev, &bufs->rc_code);
+
+	for (i = 0; i < core_num; i++)
+		mtk_venc_mem_free(inst, dev, &bufs->rc_info[i]);
+}
+
+static void venc_free_work_buf(struct venc_inst *inst)
+{
+	int i;
+	struct venc_work_buf_list *bufs = &inst->vsi->bufs;
+	unsigned int core_num = inst->vsi->config.core_num;
+	unsigned int dpb_size = inst->vsi->config.dpb_size;
+	struct device *dev;
+
+	if (bufs->rc_code.va)
+		venc_free_rc_buf(inst, bufs, core_num);
+
+	dev = &inst->ctx->dev->plat_dev->dev;
+
+	for (i = 0; i < core_num; i++) {
+		mtk_venc_mem_free(inst, dev, &bufs->wpp[i]);
+		mtk_venc_mem_free(inst, dev, &bufs->wpp_nbm[i]);
+	}
+
+	for (i = 0; i < dpb_size; i++) {
+		mtk_venc_mem_free(inst, dev, &bufs->luma[i]);
+		mtk_venc_mem_free(inst, dev, &bufs->chroma[i]);
+		mtk_venc_mem_free(inst, dev, &bufs->sub_luma[i]);
+		mtk_venc_mem_free(inst, dev, &bufs->sub_write[i]);
+		mtk_venc_mem_free(inst, dev, &bufs->col_mv[i]);
+	}
+
+	if (inst->pps_buf.va)
+		mtk_vcodec_mem_free(inst->ctx, &inst->pps_buf);
+
+	if (inst->seq_buf.va)
+		mtk_vcodec_mem_free(inst->ctx, &inst->seq_buf);
+}
+
+static int venc_alloc_rc_buf(struct venc_inst *inst,
+			     struct venc_work_buf_list *bufs,
+			     unsigned int core_num)
+{
+	int i;
+	struct mtk_vcodec_fw *fw = inst->ctx->dev->fw_handler;
+	struct device *dev;
+	void *tmp_va;
+
+	dev = &inst->ctx->dev->plat_dev->dev;
+	if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_code))
+		return -ENOMEM;
+
+	tmp_va = mtk_vcodec_fw_map_dm_addr(fw, bufs->rc_code.pa);
+	memcpy(bufs->rc_code.va, tmp_va, bufs->rc_code.size);
+
+	for (i = 0; i < core_num; i++) {
+		if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_info[i]))
+			return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static int venc_alloc_work_buf(struct venc_inst *inst)
+{
+	int i, ret;
+	struct venc_work_buf_list *bufs = &inst->vsi->bufs;
+	unsigned int core_num = inst->vsi->config.core_num;
+	unsigned int dpb_size = inst->vsi->config.dpb_size;
+	struct device *dev;
+
+	if (bufs->rc_code.size != 0) {
+		ret = venc_alloc_rc_buf(inst, bufs, core_num);
+		if (ret) {
+			mtk_venc_err(inst->ctx, "cannot allocate rc buf");
+			goto err_alloc;
+		}
+	}
+
+	dev = &inst->ctx->dev->plat_dev->dev;
+
+	for (i = 0; i < core_num; i++) {
+		if (mtk_venc_mem_alloc(inst, dev, &bufs->wpp[i]) ||
+		    mtk_venc_mem_alloc(inst, dev, &bufs->wpp_nbm[i]))
+			goto err_alloc;
+	}
+
+	for (i = 0; i < dpb_size; i++) {
+		if (mtk_venc_mem_alloc(inst, dev, &bufs->luma[i]) ||
+		    mtk_venc_mem_alloc(inst, dev, &bufs->chroma[i]) ||
+		    mtk_venc_mem_alloc(inst, dev, &bufs->sub_luma[i]) ||
+		    mtk_venc_mem_alloc(inst, dev, &bufs->sub_write[i]) ||
+		    mtk_venc_mem_alloc(inst, dev, &bufs->col_mv[i]))
+			goto err_alloc;
+	}
+
+	/* the pps_buf and seq_buf are used by AP side only */
+	inst->pps_buf.size = PPS_SIZE;
+	ret = mtk_vcodec_mem_alloc(inst->ctx, &inst->pps_buf);
+	if (ret) {
+		mtk_venc_err(inst->ctx, "cannot allocate pps_buf");
+		goto err_alloc;
+	}
+
+	inst->seq_buf.size = SEQ_HEADER_SIZE;
+	ret = mtk_vcodec_mem_alloc(inst->ctx, &inst->seq_buf);
+	if (ret) {
+		mtk_venc_err(inst->ctx, "cannot allocate seq_buf");
+		goto err_alloc;
+	}
+	return 0;
+
+err_alloc:
+	venc_free_work_buf(inst);
+	return -ENOMEM;
+}
+
+static int venc_set_param(void *handle,
+			  enum venc_set_param_type type,
+			  struct venc_enc_param *enc_prm)
+{
+	int ret = 0;
+	struct venc_inst *inst = (struct venc_inst *)handle;
+
+	switch (type) {
+	case VENC_SET_PARAM_ENC:
+		if (WARN_ON(!inst->vsi))
+			return -EINVAL;
+		inst->vsi->config.input_fourcc = enc_prm->input_yuv_fmt;
+		inst->vsi->config.bitrate = enc_prm->bitrate;
+		inst->vsi->config.pic_w = enc_prm->width;
+		inst->vsi->config.pic_h = enc_prm->height;
+		inst->vsi->config.buf_w = enc_prm->buf_width;
+		inst->vsi->config.buf_h = enc_prm->buf_height;
+		inst->vsi->config.gop_size = enc_prm->gop_size;
+		inst->vsi->config.framerate = enc_prm->frm_rate;
+		inst->vsi->config.intra_period = enc_prm->intra_period;
+		inst->vsi->config.profile = enc_prm->profile;
+		inst->vsi->config.level = enc_prm->level;
+
+		ret = vpu_enc_set_param(&inst->vpu_inst, type, enc_prm);
+		if (ret)
+			break;
+
+		if (inst->work_buf_allocated) {
+			venc_free_work_buf(inst);
+			inst->work_buf_allocated = false;
+		}
+		ret = venc_alloc_work_buf(inst);
+		if (ret)
+			break;
+		inst->work_buf_allocated = true;
+		break;
+	case VENC_SET_PARAM_PREPEND_HEADER:
+		inst->prepend_hdr = 1;
+		break;
+	default:
+		ret = vpu_enc_set_param(&inst->vpu_inst, type, enc_prm);
+		break;
+	}
+
+	return ret;
+}
+
+static int venc_deinit(void *handle)
+{
+	int ret = 0;
+	struct venc_inst *inst = (struct venc_inst *)handle;
+
+	ret = vpu_enc_deinit(&inst->vpu_inst);
+
+	if (inst->work_buf_allocated)
+		venc_free_work_buf(inst);
+
+	kfree(inst);
+
+	return ret;
+}
+
+const struct venc_common_if venc_if = {
+	.init = venc_init,
+	.encode = venc_encode,
+	.set_param = venc_set_param,
+	.deinit = venc_deinit,
+};
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
index 8522f71fc901..f201d116ed46 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
@@ -723,9 +723,9 @@ static void h264_enc_set_vsi_configs(struct venc_h264_inst *inst,
 	inst->vsi->config.framerate = enc_prm->frm_rate;
 	inst->vsi->config.intra_period = enc_prm->intra_period;
 	inst->vsi->config.profile =
-		h264_get_profile(inst, enc_prm->h264_profile);
+		h264_get_profile(inst, enc_prm->profile);
 	inst->vsi->config.level =
-		h264_get_level(inst, enc_prm->h264_level);
+		h264_get_level(inst, enc_prm->level);
 	inst->vsi->config.wfd = 0;
 }
 
@@ -742,9 +742,9 @@ static void h264_enc_set_vsi_34_configs(struct venc_h264_inst *inst,
 	inst->vsi_34->config.framerate = enc_prm->frm_rate;
 	inst->vsi_34->config.intra_period = enc_prm->intra_period;
 	inst->vsi_34->config.profile =
-		h264_get_profile(inst, enc_prm->h264_profile);
+		h264_get_profile(inst, enc_prm->profile);
 	inst->vsi_34->config.level =
-		h264_get_level(inst, enc_prm->h264_level);
+		h264_get_level(inst, enc_prm->level);
 	inst->vsi_34->config.wfd = 0;
 }
 
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.h b/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.h
index 889440a436b6..3c2a1b5e9312 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.h
+++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.h
@@ -66,8 +66,8 @@ enum venc_set_param_type {
  * struct venc_enc_prm - encoder settings for VENC_SET_PARAM_ENC used in
  *					  venc_if_set_param()
  * @input_fourcc: input yuv format
- * @h264_profile: V4L2 defined H.264 profile
- * @h264_level: V4L2 defined H.264 level
+ * @profile: V4L2 defined profile
+ * @level: V4L2 defined level
  * @width: image width
  * @height: image height
  * @buf_width: buffer width
@@ -79,8 +79,8 @@ enum venc_set_param_type {
  */
 struct venc_enc_param {
 	enum venc_yuv_fmt input_yuv_fmt;
-	unsigned int h264_profile;
-	unsigned int h264_level;
+	unsigned int profile;
+	unsigned int level;
 	unsigned int width;
 	unsigned int height;
 	unsigned int buf_width;
@@ -107,9 +107,11 @@ struct venc_frame_info {
 /*
  * struct venc_frm_buf - frame buffer information used in venc_if_encode()
  * @fb_addr: plane frame buffer addresses
+ * @num_planes: number of planes
  */
 struct venc_frm_buf {
 	struct mtk_vcodec_fb fb_addr[MTK_VCODEC_MAX_PLANES];
+	unsigned int num_planes;
 };
 
 /*
@@ -124,6 +126,7 @@ struct venc_done_result {
 
 extern const struct venc_common_if venc_h264_if;
 extern const struct venc_common_if venc_vp8_if;
+extern const struct venc_common_if venc_if;
 
 /*
  * venc_if_init - Create the driver handle
-- 
2.45.2



From irui.wang at mediatek.com  Tue May 27 23:36:32 2025
From: irui.wang at mediatek.com (Irui Wang)
Date: Wed, 28 May 2025 14:36:32 +0800
Subject: [PATCH v2 6/6] media: mediatek: encoder: Add MT8196 encoder compatible data
In-Reply-To: <20250528063633.14054-1-irui.wang@mediatek.com>
References: <20250528063633.14054-1-irui.wang@mediatek.com>
Message-ID: <20250528063633.14054-7-irui.wang@mediatek.com>

MT8196 encoder use common firmware interface, add compatible data to
support MT8196 encoding, and need set dma mask to support 34bit.

Signed-off-by: Irui Wang <irui.wang at mediatek.com>
---
 .../vcodec/encoder/mtk_vcodec_enc_drv.c       | 19 +++++++++++++++++++
 .../vcodec/encoder/mtk_vcodec_enc_drv.h       |  2 ++
 2 files changed, 21 insertions(+)

diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
index 50936949d527..c869c4245ebc 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
@@ -20,6 +20,8 @@
 #include "mtk_vcodec_enc_pm.h"
 #include "../common/mtk_vcodec_intr.h"
 
+#define VENC_DMA_BIT_MASK 34
+
 static const struct mtk_video_fmt mtk_video_formats_output[] = {
 	{
 		.fourcc = V4L2_PIX_FMT_NV12M,
@@ -299,6 +301,9 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
 		goto err_res;
 	}
 
+	if (dev->venc_pdata->set_dma_bit_mask)
+		dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(VENC_DMA_BIT_MASK));
+
 	mutex_init(&dev->enc_mutex);
 	mutex_init(&dev->dev_mutex);
 	mutex_init(&dev->dev_ctx_lock);
@@ -450,6 +455,19 @@ static const struct mtk_vcodec_enc_pdata mt8195_pdata = {
 	.core_id = VENC_SYS,
 };
 
+static const struct mtk_vcodec_enc_pdata mt8196_pdata = {
+	.venc_model_num = 8196,
+	.capture_formats = mtk_video_formats_capture_h264,
+	.num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
+	.output_formats = mtk_video_formats_output,
+	.num_output_formats = ARRAY_SIZE(mtk_video_formats_output),
+	.min_bitrate = 64,
+	.max_bitrate = 100000000,
+	.core_id = VENC_SYS,
+	.uses_common_fw_iface = true,
+	.set_dma_bit_mask = true,
+};
+
 static const struct of_device_id mtk_vcodec_enc_match[] = {
 	{.compatible = "mediatek,mt8173-vcodec-enc",
 			.data = &mt8173_avc_pdata},
@@ -459,6 +477,7 @@ static const struct of_device_id mtk_vcodec_enc_match[] = {
 	{.compatible = "mediatek,mt8188-vcodec-enc", .data = &mt8188_pdata},
 	{.compatible = "mediatek,mt8192-vcodec-enc", .data = &mt8192_pdata},
 	{.compatible = "mediatek,mt8195-vcodec-enc", .data = &mt8195_pdata},
+	{.compatible = "mediatek,mt8196-vcodec-enc", .data = &mt8196_pdata},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_vcodec_enc_match);
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
index b3206a7b592d..ded794f1b37a 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
@@ -32,6 +32,7 @@
  * @core_id: stand for h264 or vp8 encode index
  * @uses_34bit: whether the encoder uses 34-bit iova
  * @uses_common_fw_iface: whether the encoder uses common driver interface
+ * @set_dma_bit_mask: whether the encoder need set extra DMA bit mask
  */
 struct mtk_vcodec_enc_pdata {
 	u16 venc_model_num;
@@ -45,6 +46,7 @@ struct mtk_vcodec_enc_pdata {
 	u8 core_id;
 	bool uses_34bit;
 	bool uses_common_fw_iface;
+	bool set_dma_bit_mask;
 };
 
 /*
-- 
2.45.2



From irui.wang at mediatek.com  Tue May 27 23:36:31 2025
From: irui.wang at mediatek.com (Irui Wang)
Date: Wed, 28 May 2025 14:36:31 +0800
Subject: [PATCH v2 5/6] dt-bindings: media: mediatek: encoder: Add encoder dt-bindings for MT8196
In-Reply-To: <20250528063633.14054-1-irui.wang@mediatek.com>
References: <20250528063633.14054-1-irui.wang@mediatek.com>
Message-ID: <20250528063633.14054-6-irui.wang@mediatek.com>

Add MT8196 encoder compatible string, which will reference VCP device.

Signed-off-by: Irui Wang <irui.wang at mediatek.com>
---
 .../bindings/media/mediatek,vcodec-encoder.yaml      | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
index ebc615584f92..7675391d7eb0 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
@@ -24,6 +24,7 @@ properties:
               - mediatek,mt8188-vcodec-enc
               - mediatek,mt8192-vcodec-enc
               - mediatek,mt8195-vcodec-enc
+              - mediatek,mt8196-vcodec-enc
       - items:
           - const: mediatek,mt8186-vcodec-enc
           - const: mediatek,mt8183-vcodec-enc
@@ -76,6 +77,17 @@ required:
   - iommus
 
 allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - mediatek,mt8196-vcodec-enc
+
+    then:
+      required:
+        - mediatek,vcp
+
   - if:
       properties:
         compatible:
-- 
2.45.2



From irui.wang at mediatek.com  Tue May 27 23:36:30 2025
From: irui.wang at mediatek.com (Irui Wang)
Date: Wed, 28 May 2025 14:36:30 +0800
Subject: [PATCH v2 4/6] media: mediatek: encoder: Add a new platform data member
In-Reply-To: <20250528063633.14054-1-irui.wang@mediatek.com>
References: <20250528063633.14054-1-irui.wang@mediatek.com>
Message-ID: <20250528063633.14054-5-irui.wang@mediatek.com>

Add a new platform data member to indicate each encoder IC, so that the
get chip name function by 'of_device_is_compatible' can be removed.

Signed-off-by: Irui Wang <irui.wang at mediatek.com>
---
 .../mediatek/vcodec/encoder/mtk_vcodec_enc.c  | 23 ++-----------------
 .../vcodec/encoder/mtk_vcodec_enc_drv.c       |  6 +++++
 .../vcodec/encoder/mtk_vcodec_enc_drv.h       |  2 ++
 3 files changed, 10 insertions(+), 21 deletions(-)

diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
index 03512bf7a072..1a7be3e57eef 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
@@ -198,34 +198,15 @@ static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
 			       pdata->num_output_formats);
 }
 
-static int mtk_vcodec_enc_get_chip_name(void *priv)
-{
-	struct mtk_vcodec_enc_ctx *ctx = fh_to_enc_ctx(priv);
-	struct device *dev = &ctx->dev->plat_dev->dev;
-
-	if (of_device_is_compatible(dev->of_node, "mediatek,mt8173-vcodec-enc"))
-		return 8173;
-	else if (of_device_is_compatible(dev->of_node, "mediatek,mt8183-vcodec-enc"))
-		return 8183;
-	else if (of_device_is_compatible(dev->of_node, "mediatek,mt8192-vcodec-enc"))
-		return 8192;
-	else if (of_device_is_compatible(dev->of_node, "mediatek,mt8195-vcodec-enc"))
-		return 8195;
-	else if (of_device_is_compatible(dev->of_node, "mediatek,mt8188-vcodec-enc"))
-		return 8188;
-	else
-		return 8173;
-}
-
 static int vidioc_venc_querycap(struct file *file, void *priv,
 				struct v4l2_capability *cap)
 {
 	struct mtk_vcodec_enc_ctx *ctx = fh_to_enc_ctx(priv);
+	const struct mtk_vcodec_enc_pdata *pdata = ctx->dev->venc_pdata;
 	struct device *dev = &ctx->dev->plat_dev->dev;
-	int platform_name = mtk_vcodec_enc_get_chip_name(priv);
 
 	strscpy(cap->driver, dev->driver->name, sizeof(cap->driver));
-	snprintf(cap->card, sizeof(cap->card), "MT%d video encoder", platform_name);
+	snprintf(cap->card, sizeof(cap->card), "MT%d video encoder", pdata->venc_model_num);
 
 	return 0;
 }
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
index bb913dfe5f04..50936949d527 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
@@ -380,6 +380,7 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
 }
 
 static const struct mtk_vcodec_enc_pdata mt8173_avc_pdata = {
+	.venc_model_num = 8173,
 	.capture_formats = mtk_video_formats_capture_h264,
 	.num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
 	.output_formats = mtk_video_formats_output,
@@ -390,6 +391,7 @@ static const struct mtk_vcodec_enc_pdata mt8173_avc_pdata = {
 };
 
 static const struct mtk_vcodec_enc_pdata mt8173_vp8_pdata = {
+	.venc_model_num = 8173,
 	.capture_formats = mtk_video_formats_capture_vp8,
 	.num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_vp8),
 	.output_formats = mtk_video_formats_output,
@@ -400,6 +402,7 @@ static const struct mtk_vcodec_enc_pdata mt8173_vp8_pdata = {
 };
 
 static const struct mtk_vcodec_enc_pdata mt8183_pdata = {
+	.venc_model_num = 8183,
 	.uses_ext = true,
 	.capture_formats = mtk_video_formats_capture_h264,
 	.num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
@@ -411,6 +414,7 @@ static const struct mtk_vcodec_enc_pdata mt8183_pdata = {
 };
 
 static const struct mtk_vcodec_enc_pdata mt8188_pdata = {
+	.venc_model_num = 8188,
 	.uses_ext = true,
 	.capture_formats = mtk_video_formats_capture_h264,
 	.num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
@@ -423,6 +427,7 @@ static const struct mtk_vcodec_enc_pdata mt8188_pdata = {
 };
 
 static const struct mtk_vcodec_enc_pdata mt8192_pdata = {
+	.venc_model_num = 8192,
 	.uses_ext = true,
 	.capture_formats = mtk_video_formats_capture_h264,
 	.num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
@@ -434,6 +439,7 @@ static const struct mtk_vcodec_enc_pdata mt8192_pdata = {
 };
 
 static const struct mtk_vcodec_enc_pdata mt8195_pdata = {
+	.venc_model_num = 8195,
 	.uses_ext = true,
 	.capture_formats = mtk_video_formats_capture_h264,
 	.num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
index 426b1398f815..b3206a7b592d 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
@@ -21,6 +21,7 @@
 /**
  * struct mtk_vcodec_enc_pdata - compatible data for each IC
  *
+ * @venc_model_num: encoder model number
  * @uses_ext: whether the encoder uses the extended firmware messaging format
  * @min_bitrate: minimum supported encoding bitrate
  * @max_bitrate: maximum supported encoding bitrate
@@ -33,6 +34,7 @@
  * @uses_common_fw_iface: whether the encoder uses common driver interface
  */
 struct mtk_vcodec_enc_pdata {
+	u16 venc_model_num;
 	bool uses_ext;
 	u64 min_bitrate;
 	u64 max_bitrate;
-- 
2.45.2



From allan.wang at mediatek.com  Tue May 27 23:43:05 2025
From: allan.wang at mediatek.com (Allan Wang)
Date: Wed, 28 May 2025 14:43:05 +0800
Subject: [PATCH] linux-firmware: update firmware for MT7925 WiFi device
Message-ID: <20250528064305.532840-1-allan.wang@mediatek.com>

Update binary firmware for MT7925 WiFi devices

File: mediatek/mt7925/WIFI_MT7925_PATCH_MCU_1_1_hdr.bin
Version: 20250526152947a
File: mediatek/mt7925/WIFI_RAM_CODE_MT7925_1_1.bin
Version: 20250526152808

Signed-off-by: Allan Wang <allan.wang at mediatek.com>
---
 WHENCE                                        |   4 ++--
 .../mt7925/WIFI_MT7925_PATCH_MCU_1_1_hdr.bin  | Bin 212384 -> 212512 bytes
 mediatek/mt7925/WIFI_RAM_CODE_MT7925_1_1.bin  | Bin 1204648 -> 1204648 bytes
 3 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/WHENCE b/WHENCE
index 93f849c4..394c23d6 100644
--- a/WHENCE
+++ b/WHENCE
@@ -6214,9 +6214,9 @@ Licence: Redistributable. See LICENCE.mediatek for details.
 Driver: mt7925 - MediaTek MT7925 Wireless MACs
 
 File: mediatek/mt7925/WIFI_MT7925_PATCH_MCU_1_1_hdr.bin
-Version: 20250425072955a
+Version: 20250526152947a
 File: mediatek/mt7925/WIFI_RAM_CODE_MT7925_1_1.bin
-Version: 20250425072801
+Version: 20250526152808
 
 Licence: Redistributable. See LICENCE.mediatek for details.
 
diff --git a/mediatek/mt7925/WIFI_MT7925_PATCH_MCU_1_1_hdr.bin b/mediatek/mt7925/WIFI_MT7925_PATCH_MCU_1_1_hdr.bin
index 776e2b97dd4d710674c0f18e6bb65e41f7d94ae4..5c664f855f56a639224fd6e17e267b054b807226 100644
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diff --git a/mediatek/mt7925/WIFI_RAM_CODE_MT7925_1_1.bin b/mediatek/mt7925/WIFI_RAM_CODE_MT7925_1_1.bin
index 10463e7161c092031f7817b1a3047372267b3cad..4a821728cc8b9d3fafb969b1b4f5e4f245803945 100644
GIT binary patch
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-- 
2.45.2



From chris.lu at mediatek.com  Tue May 27 23:46:24 2025
From: chris.lu at mediatek.com (Chris Lu)
Date: Wed, 28 May 2025 14:46:24 +0800
Subject: [PATCH v1] mediatek MT7925: update bluetooth firmware to 20250526153203
Message-ID: <20250528064625.533578-1-chris.lu@mediatek.com>

Update binary firmware for MT7925 BT devices.

File: mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin
Version: 20250526153203

Signed-off-by: Chris Lu <chris.lu at mediatek.com>
---
 WHENCE                                        |   2 +-
 .../mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin     | Bin 459695 -> 459887 bytes
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/WHENCE b/WHENCE
index 93f849c4..c653db09 100644
--- a/WHENCE
+++ b/WHENCE
@@ -6225,7 +6225,7 @@ Licence: Redistributable. See LICENCE.mediatek for details.
 Driver: mt7925 - MediaTek MT7925 bluetooth chipset
 
 File: mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin
-Version: 20250425073330
+Version: 20250526153203
 
 Licence: Redistributable. See LICENCE.mediatek for details.
 
diff --git a/mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin b/mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin
index cce1ddaeefac5a70d7ac9172ef78ce6043bf1334..9263027786aa73ad3de420ff14131492ad7f16a6 100644
GIT binary patch
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UHZ3wRGBq$XGBq$aGB_|X3J3BFd;kCd

-- 
2.45.2



From ot_zhangchao.zhang at mediatek.com  Wed May 28 00:03:23 2025
From: ot_zhangchao.zhang at mediatek.com (Zhangchao Zhang)
Date: Wed, 28 May 2025 15:03:23 +0800
Subject: [PATCH] Bluetooth: BT Driver: mediatek: add gpio pin to reset bt
Message-ID: <20250528070323.14902-1-ot_zhangchao.zhang@mediatek.com>

This patch provides some methods btmtk_reset_by_gpio,
btmtk_reset_by_gpio_work_for mediatek controller.

The pin is configured in dts files, bluetooth is reset by pulling
the pin, when an exception or coredump occurs, the above method will
be used to reset the bluetooth.

Co-developed-by Hao qin <hao.qin at mediatek.com>
Co-developed-by Chirs lu <chris.lu at mediatek.com>
Co-developed-by Jiande lu <jiande.lu at mediatek.com>
Signed-off-by: Zhangchao Zhang <ot_zhangchao.zhang at mediatek.com>
---
 drivers/bluetooth/btmtk.c | 59 +++++++++++++++++++++++++++++++++++++++
 drivers/bluetooth/btmtk.h |  5 ++++
 2 files changed, 64 insertions(+)

diff --git a/drivers/bluetooth/btmtk.c b/drivers/bluetooth/btmtk.c
index 4390fd571dbd..16542c724b40 100644
--- a/drivers/bluetooth/btmtk.c
+++ b/drivers/bluetooth/btmtk.c
@@ -6,6 +6,8 @@
 #include <linux/firmware.h>
 #include <linux/usb.h>
 #include <linux/iopoll.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
 #include <linux/unaligned.h>
 
 #include <net/bluetooth/bluetooth.h>
@@ -109,6 +111,59 @@ static void btmtk_coredump_notify(struct hci_dev *hdev, int state)
 	}
 }
 
+static void btmtk_reset_by_gpio_work(struct work_struct *work)
+{
+	struct btmtk_reset_gpio *reset_gpio_data =
+			container_of(work, struct btmtk_reset_gpio, reset_work.work);
+
+	gpio_direction_output(reset_gpio_data->gpio_number, 1);
+	kfree(reset_gpio_data);
+}
+
+static int btmtk_reset_by_gpio(struct hci_dev *hdev)
+{
+	struct btmtk_data *data = hci_get_priv(hdev);
+	struct btmtk_reset_gpio *reset_gpio_data;
+	struct device_node *node;
+	int reset_gpio_number;
+
+	node = of_find_compatible_node(NULL, NULL, "mediatek,usb-bluetooth");
+	if (node) {
+		reset_gpio_number = of_get_named_gpio(node, "reset-gpios", 0);
+		if (!gpio_is_valid(reset_gpio_number)) {
+			bt_dev_warn(hdev, "invalid reset gpio, use SW reset");
+			return -EINVAL;
+		}
+	} else {
+		bt_dev_warn(hdev, "no reset gpio, use SW reet");
+		return -ENODEV;
+	}
+
+	/* Toggle the hard reset line. The Mediatek device is going to
+	 * yank itself off the USB and then replug. The cleanup is handled
+	 * correctly on the way out (standard USB disconnect), and the new
+	 * device is detected cleanly and bound to the driver again like
+	 * it should be.
+	 */
+
+	if (test_and_set_bit(BTMTK_HW_RESET_ACTIVE, &data->flags)) {
+		bt_dev_err(hdev, "last reset failed? Not resetting again");
+		return 0;
+	}
+
+	reset_gpio_data = kzalloc(sizeof(*reset_gpio_data), GFP_KERNEL);
+	if (!reset_gpio_data)
+		return -ENOMEM;
+
+	INIT_DELAYED_WORK(&reset_gpio_data->reset_work, btmtk_reset_by_gpio_work);
+	reset_gpio_data->gpio_number = reset_gpio_number;
+
+	gpio_direction_output(reset_gpio_number, 0);
+	schedule_delayed_work(&reset_gpio_data->reset_work, msecs_to_jiffies(200));
+
+	return 0;
+}
+
 void btmtk_fw_get_filename(char *buf, size_t size, u32 dev_id, u32 fw_ver,
 			   u32 fw_flavor)
 {
@@ -364,6 +419,10 @@ void btmtk_reset_sync(struct hci_dev *hdev)
 	struct btmtk_data *reset_work = hci_get_priv(hdev);
 	int err;
 
+	/*Toggle reset gpio if the platform provieds one*/
+	err = btmtk_reset_by_gpio(hdev);
+	if (!err)
+		return;
 	hci_dev_lock(hdev);
 
 	err = hci_cmd_sync_queue(hdev, reset_work->reset_sync, NULL, NULL);
diff --git a/drivers/bluetooth/btmtk.h b/drivers/bluetooth/btmtk.h
index 5df7c3296624..8a265ce367d1 100644
--- a/drivers/bluetooth/btmtk.h
+++ b/drivers/bluetooth/btmtk.h
@@ -179,6 +179,11 @@ struct btmtk_data {
 	spinlock_t isorxlock;
 };
 
+struct btmtk_reset_gpio {
+	struct delayed_work reset_work;
+	int gpio_number;
+};
+
 typedef int (*wmt_cmd_sync_func_t)(struct hci_dev *,
 				   struct btmtk_hci_wmt_params *);
 
-- 
2.46.0



From pmenzel at molgen.mpg.de  Wed May 28 00:07:21 2025
From: pmenzel at molgen.mpg.de (Paul Menzel)
Date: Wed, 28 May 2025 09:07:21 +0200
Subject: [PATCH v1] mediatek MT7925: update bluetooth firmware to
 20250526153203
In-Reply-To: <20250528064625.533578-1-chris.lu@mediatek.com>
References: <20250528064625.533578-1-chris.lu@mediatek.com>
Message-ID: <afe65c91-9120-4327-84a0-faf2d341ebb0@molgen.mpg.de>

Dear Chris,


Thank you for updating the firmware file


Am 28.05.25 um 08:46 schrieb Chris Lu:
> Update binary firmware for MT7925 BT devices.
> 
> File: mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin
> Version: 20250526153203

It?d be great if you could add some kind of change-log compared to the 
previous version 20250425073330.

> Signed-off-by: Chris Lu <chris.lu at mediatek.com>
> ---
>   WHENCE                                        |   2 +-
>   .../mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin     | Bin 459695 -> 459887 bytes
>   2 files changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/WHENCE b/WHENCE
> index 93f849c4..c653db09 100644
> --- a/WHENCE
> +++ b/WHENCE
> @@ -6225,7 +6225,7 @@ Licence: Redistributable. See LICENCE.mediatek for details.
>   Driver: mt7925 - MediaTek MT7925 bluetooth chipset
>   
>   File: mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin
> -Version: 20250425073330
> +Version: 20250526153203
>   
>   Licence: Redistributable. See LICENCE.mediatek for details.
>   
> diff --git a/mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin b/mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin
> index cce1ddaeefac5a70d7ac9172ef78ce6043bf1334..9263027786aa73ad3de420ff14131492ad7f16a6 100644

[?]


Kind regards,

Paul


From lorenzo at kernel.org  Wed May 28 00:16:04 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 28 May 2025 09:16:04 +0200
Subject: [PATCH 1/6] pinctrl: airoha: fix wrong PHY LED mux value for
 LED1 GPIO46
In-Reply-To: <20250527222040.32000-2-ansuelsmth@gmail.com>
References: <20250527222040.32000-1-ansuelsmth@gmail.com>
 <20250527222040.32000-2-ansuelsmth@gmail.com>
Message-ID: <aDa4NCTzyzw0mnfE@lore-desk>

> In all the MUX value for LED1 GPIO46 there is a Copy-Paste error where
> the MUX value is set to LED0_MODE_MASK instead of LED1_MODE_MASK.
> 
> This wasn't notice as there were no board that made use of the
> secondary PHY LED but looking at the internal Documentation the actual
> value should be LED1_MODE_MASK similar to the other GPIO entry.
> 
> Fix the wrong value to apply the correct MUX configuration.

Acked-by: Lorenzo Bianconi <lorenzo at kernel.org>

> 
> Cc: stable at vger.kernel.org
> Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---
>  drivers/pinctrl/mediatek/pinctrl-airoha.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> index b97b28ebb37a..8ef7f88477aa 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> @@ -1752,8 +1752,8 @@ static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
>  		.regmap[0] = {
>  			AIROHA_FUNC_MUX,
>  			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN3_LED0_MODE_MASK,
> -			GPIO_LAN3_LED0_MODE_MASK
> +			GPIO_LAN3_LED1_MODE_MASK,
> +			GPIO_LAN3_LED1_MODE_MASK
>  		},
>  		.regmap[1] = {
>  			AIROHA_FUNC_MUX,
> @@ -1816,8 +1816,8 @@ static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
>  		.regmap[0] = {
>  			AIROHA_FUNC_MUX,
>  			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN3_LED0_MODE_MASK,
> -			GPIO_LAN3_LED0_MODE_MASK
> +			GPIO_LAN3_LED1_MODE_MASK,
> +			GPIO_LAN3_LED1_MODE_MASK
>  		},
>  		.regmap[1] = {
>  			AIROHA_FUNC_MUX,
> @@ -1880,8 +1880,8 @@ static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
>  		.regmap[0] = {
>  			AIROHA_FUNC_MUX,
>  			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN3_LED0_MODE_MASK,
> -			GPIO_LAN3_LED0_MODE_MASK
> +			GPIO_LAN3_LED1_MODE_MASK,
> +			GPIO_LAN3_LED1_MODE_MASK
>  		},
>  		.regmap[1] = {
>  			AIROHA_FUNC_MUX,
> @@ -1944,8 +1944,8 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
>  		.regmap[0] = {
>  			AIROHA_FUNC_MUX,
>  			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN3_LED0_MODE_MASK,
> -			GPIO_LAN3_LED0_MODE_MASK
> +			GPIO_LAN3_LED1_MODE_MASK,
> +			GPIO_LAN3_LED1_MODE_MASK
>  		},
>  		.regmap[1] = {
>  			AIROHA_FUNC_MUX,
> -- 
> 2.48.1
> 
-------------- next part --------------
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From filip.ostrowski at profinix.pl  Wed May 28 00:36:07 2025
From: filip.ostrowski at profinix.pl (Filip Ostrowski)
Date: Wed, 28 May 2025 07:36:07 GMT
Subject: Prezentacja
Message-ID: <20250528084500-0.1.fu.5well.0.c62gh3n3nb@profinix.pl>

Dzie? dobry!

Czy m?g?bym przedstawi? rozwi?zanie, kt?re umo?liwia monitoring ka?dego auta w czasie rzeczywistym w tym jego pozycj?, zu?ycie paliwa i przebieg?

Dodatkowo nasze narz?dzie minimalizuje koszty utrzymania samochod?w, skraca czas przejazd?w, a tak?e umo?liwia tworzenie planu tras czy dostaw.

Z naszej wiedzy i do?wiadczenia korzysta ju? ponad 49 tys. Klient?w. Monitorujemy 809 000 pojazd?w na ca?ym ?wiecie, co jest nasz? najlepsz? wizyt?wk?.

Bardzo prosz? o e-maila zwrotnego, je?li mogliby?my wsp?lnie om?wi? potencja? wykorzystania takiego rozwi?zania w Pa?stwa firmie.


Pozdrawiam
Filip Ostrowski


From pmenzel at molgen.mpg.de  Wed May 28 00:46:09 2025
From: pmenzel at molgen.mpg.de (Paul Menzel)
Date: Wed, 28 May 2025 09:46:09 +0200
Subject: [PATCH] Bluetooth: BT Driver: mediatek: add gpio pin to reset bt
In-Reply-To: <20250528070323.14902-1-ot_zhangchao.zhang@mediatek.com>
References: <20250528070323.14902-1-ot_zhangchao.zhang@mediatek.com>
Message-ID: <140ac32d-432c-496d-b62d-d4254735dc4c@molgen.mpg.de>

Dear Zhangchao,


Thank you for your patch. For the summary, I?d just use:

Bluetooth: btmtk: Add gpio pin to reset bt


Am 28.05.25 um 09:03 schrieb Zhangchao Zhang:
> This patch provides some methods btmtk_reset_by_gpio,

some ? the two

> btmtk_reset_by_gpio_work_for mediatek controller.
> 
> The pin is configured in dts files, bluetooth is reset by pulling
> the pin, when an exception or coredump occurs, the above method will
> be used to reset the bluetooth.

How did you test this? Could you please add that to the commit message.

> Co-developed-by Hao qin <hao.qin at mediatek.com>

qin ? Qin

> Co-developed-by Chirs lu <chris.lu at mediatek.com>

Chirs ? Chris
lu ? Lu

> Co-developed-by Jiande lu <jiande.lu at mediatek.com>

lu ? Lu

> Signed-off-by: Zhangchao Zhang <ot_zhangchao.zhang at mediatek.com>
> ---
>   drivers/bluetooth/btmtk.c | 59 +++++++++++++++++++++++++++++++++++++++
>   drivers/bluetooth/btmtk.h |  5 ++++
>   2 files changed, 64 insertions(+)
> 
> diff --git a/drivers/bluetooth/btmtk.c b/drivers/bluetooth/btmtk.c
> index 4390fd571dbd..16542c724b40 100644
> --- a/drivers/bluetooth/btmtk.c
> +++ b/drivers/bluetooth/btmtk.c
> @@ -6,6 +6,8 @@
>   #include <linux/firmware.h>
>   #include <linux/usb.h>
>   #include <linux/iopoll.h>
> +#include <linux/of.h>
> +#include <linux/of_gpio.h>
>   #include <linux/unaligned.h>
>   
>   #include <net/bluetooth/bluetooth.h>
> @@ -109,6 +111,59 @@ static void btmtk_coredump_notify(struct hci_dev *hdev, int state)
>   	}
>   }
>   
> +static void btmtk_reset_by_gpio_work(struct work_struct *work)
> +{
> +	struct btmtk_reset_gpio *reset_gpio_data =
> +			container_of(work, struct btmtk_reset_gpio, reset_work.work);
> +
> +	gpio_direction_output(reset_gpio_data->gpio_number, 1);
> +	kfree(reset_gpio_data);
> +}
> +
> +static int btmtk_reset_by_gpio(struct hci_dev *hdev)
> +{
> +	struct btmtk_data *data = hci_get_priv(hdev);
> +	struct btmtk_reset_gpio *reset_gpio_data;
> +	struct device_node *node;
> +	int reset_gpio_number;
> +
> +	node = of_find_compatible_node(NULL, NULL, "mediatek,usb-bluetooth");
> +	if (node) {
> +		reset_gpio_number = of_get_named_gpio(node, "reset-gpios", 0);
> +		if (!gpio_is_valid(reset_gpio_number)) {
> +			bt_dev_warn(hdev, "invalid reset gpio, use SW reset");

gpio ? GPIO
SW ? software
reet ? reset?

Please also log the GPIO number. Also, a hint, what the user should do 
in this situation would be great.

> +			return -EINVAL;
> +		}
> +	} else {
> +		bt_dev_warn(hdev, "no reset gpio, use SW reet");

gpio ? GPIO
SW ? software
reet ? reset?

> +		return -ENODEV;
> +	}
> +
> +	/* Toggle the hard reset line. The Mediatek device is going to
> +	 * yank itself off the USB and then replug. The cleanup is handled
> +	 * correctly on the way out (standard USB disconnect), and the new
> +	 * device is detected cleanly and bound to the driver again like
> +	 * it should be.
> +	 */
> +
> +	if (test_and_set_bit(BTMTK_HW_RESET_ACTIVE, &data->flags)) {
> +		bt_dev_err(hdev, "last reset failed? Not resetting again");

It?d be great, if this error message could be rephrased, so users know 
what is wrong, and what to do.

> +		return 0;
> +	}
> +
> +	reset_gpio_data = kzalloc(sizeof(*reset_gpio_data), GFP_KERNEL);
> +	if (!reset_gpio_data)
> +		return -ENOMEM;
> +
> +	INIT_DELAYED_WORK(&reset_gpio_data->reset_work, btmtk_reset_by_gpio_work);
> +	reset_gpio_data->gpio_number = reset_gpio_number;
> +
> +	gpio_direction_output(reset_gpio_number, 0);
> +	schedule_delayed_work(&reset_gpio_data->reset_work, msecs_to_jiffies(200));

A 200 ms delay is quite long. Maybe add the datasheet section as a 
reference in a comment?

> +
> +	return 0;
> +}
> +
>   void btmtk_fw_get_filename(char *buf, size_t size, u32 dev_id, u32 fw_ver,
>   			   u32 fw_flavor)
>   {
> @@ -364,6 +419,10 @@ void btmtk_reset_sync(struct hci_dev *hdev)
>   	struct btmtk_data *reset_work = hci_get_priv(hdev);
>   	int err;
>   
> +	/*Toggle reset gpio if the platform provieds one*/

1.  Please add a space in the beginning and end.
2.  provides (A spell checker should have found this.)

> +	err = btmtk_reset_by_gpio(hdev);
> +	if (!err)
> +		return;
>   	hci_dev_lock(hdev);
>   
>   	err = hci_cmd_sync_queue(hdev, reset_work->reset_sync, NULL, NULL);
> diff --git a/drivers/bluetooth/btmtk.h b/drivers/bluetooth/btmtk.h
> index 5df7c3296624..8a265ce367d1 100644
> --- a/drivers/bluetooth/btmtk.h
> +++ b/drivers/bluetooth/btmtk.h
> @@ -179,6 +179,11 @@ struct btmtk_data {
>   	spinlock_t isorxlock;
>   };
>   
> +struct btmtk_reset_gpio {
> +	struct delayed_work reset_work;
> +	int gpio_number;
> +};
> +
>   typedef int (*wmt_cmd_sync_func_t)(struct hci_dev *,
>   				   struct btmtk_hci_wmt_params *);
>   


Kind regards,

Paul


From macpaul.lin at mediatek.com  Wed May 28 00:53:51 2025
From: macpaul.lin at mediatek.com (Macpaul Lin)
Date: Wed, 28 May 2025 15:53:51 +0800
Subject: [PATCH] driver: net: ethernet: mtk_star_emac: fix suspend/resume issue
Message-ID: <20250528075351.593068-1-macpaul.lin@mediatek.com>

From: Yanqing Wang <ot_yanqing.wang at mediatek.com>

Identify the cause of the suspend/resume hang: netif_carrier_off()
is called during link state changes and becomes stuck while
executing linkwatch_work().

To resolve this issue, call netif_device_detach() during the Ethernet
suspend process to temporarily detach the network device from the
kernel and prevent the suspend/resume hang.

Fixes: 8c7bd5a454ff ("net: ethernet: mtk-star-emac: new driver")
Signed-off-by: Yanqing Wang <ot_yanqing.wang at mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin at mediatek.com>
Signed-off-by: Biao Huang <biao.huang at mediatek.com>
---
 drivers/net/ethernet/mediatek/mtk_star_emac.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c
index b175119a6a7d..b83886a41121 100644
--- a/drivers/net/ethernet/mediatek/mtk_star_emac.c
+++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
@@ -1463,6 +1463,8 @@ static __maybe_unused int mtk_star_suspend(struct device *dev)
 	if (netif_running(ndev))
 		mtk_star_disable(ndev);
 
+	netif_device_detach(ndev);
+
 	clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks);
 
 	return 0;
@@ -1487,6 +1489,8 @@ static __maybe_unused int mtk_star_resume(struct device *dev)
 			clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks);
 	}
 
+	netif_device_attach(ndev);
+
 	return ret;
 }
 
-- 
2.45.2



From lorenzo at kernel.org  Wed May 28 01:07:37 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 28 May 2025 10:07:37 +0200
Subject: [PATCH 2/6] pinctrl: mediatek: airoha: generalize
 pins/group/function/confs handling
In-Reply-To: <20250527222040.32000-3-ansuelsmth@gmail.com>
References: <20250527222040.32000-1-ansuelsmth@gmail.com>
 <20250527222040.32000-3-ansuelsmth@gmail.com>
Message-ID: <aDbESUHdO4DgOtsm@lore-desk>

> In preparation for support of Airoha AN7583, generalize
> pins/group/function/confs handling and move them in match_data.
> Inner function will base the values on the pinctrl priv struct instead of
> relying on hardcoded struct.
> 
> This permits to use different PIN data while keeping the same logic.
> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>

Hi Christian,

I think the approach is fine, just some comments inline.

Regards,
Lorenzo

> ---
>  drivers/pinctrl/mediatek/pinctrl-airoha.c | 569 ++++++++++++----------
>  1 file changed, 319 insertions(+), 250 deletions(-)
> 
> diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> index 8ef7f88477aa..8af9109db992 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> @@ -30,20 +30,20 @@
>  #include "../pinconf.h"
>  #include "../pinmux.h"
>  
> -#define PINCTRL_PIN_GROUP(id)						\
> -	PINCTRL_PINGROUP(#id, id##_pins, ARRAY_SIZE(id##_pins))
> +#define PINCTRL_PIN_GROUP(id, table)					\

since this is now just used for the name pointer, I guess you can rename it in
"name".

> +	PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))
>  
> -#define PINCTRL_FUNC_DESC(id)						\
> +#define PINCTRL_FUNC_DESC(id, table)					\
>  	{								\
>  		.desc = {						\
>  			.func = {					\
> -				.name = #id,				\
> -				.groups = id##_groups,			\
> -				.ngroups = ARRAY_SIZE(id##_groups),	\
> +				.name = id,				\
> +				.groups = table##_groups,		\
> +				.ngroups = ARRAY_SIZE(table##_groups),	\
>  			}						\
>  		},							\
> -		.groups = id##_func_group,				\
> -		.group_size = ARRAY_SIZE(id##_func_group),		\
> +		.groups = table##_func_group,				\
> +		.group_size = ARRAY_SIZE(table##_func_group),		\
>  	}
>  
>  #define PINCTRL_CONF_DESC(p, offset, mask)				\
> @@ -359,16 +359,46 @@ struct airoha_pinctrl_gpiochip {
>  	u32 irq_type[AIROHA_NUM_PINS];
>  };
>  
> +struct airoha_pinctrl_confs_info {
> +	const struct airoha_pinctrl_conf *confs;
> +	unsigned int num_confs;
> +};
> +
> +enum airoha_pinctrl_confs_type {
> +	AIROHA_PINCTRL_CONFS_PULLUP,
> +	AIROHA_PINCTRL_CONFS_PULLDOWN,
> +	AIROHA_PINCTRL_CONFS_DRIVE_E2,
> +	AIROHA_PINCTRL_CONFS_DRIVE_E4,
> +	AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
> +
> +	AIROHA_PINCTRL_CONFS_MAX,

I guess with the approach suggested below we can get rid of AIROHA_PINCTRL_CONFS_MAX

> +};
> +
>  struct airoha_pinctrl {
>  	struct pinctrl_dev *ctrl;
>  
> +	struct pinctrl_desc desc;
> +	const struct pingroup *grps;
> +	const struct airoha_pinctrl_func *funcs;
> +	const struct airoha_pinctrl_confs_info *confs_info;
> +
>  	struct regmap *chip_scu;
>  	struct regmap *regmap;
>  
>  	struct airoha_pinctrl_gpiochip gpiochip;
>  };
>  
> -static struct pinctrl_pin_desc airoha_pinctrl_pins[] = {
> +struct airoha_pinctrl_match_data {
> +	const struct pinctrl_pin_desc *pins;
> +	const unsigned int num_pins;
> +	const struct pingroup *grps;
> +	const unsigned int num_grps;
> +	const struct airoha_pinctrl_func *funcs;
> +	const unsigned int num_funcs;
> +	const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];

In order to generalize the approach, I guess we can use a
airoha_pinctrl_confs_info pointer here, something like:

	const struct airoha_pinctrl_confs_info *confs_info;
	const unsigned int num_confs;

> +};
> +
> +static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
>  	PINCTRL_PIN(0, "uart1_txd"),
>  	PINCTRL_PIN(1, "uart1_rxd"),
>  	PINCTRL_PIN(2, "i2c_scl"),
> @@ -429,172 +459,172 @@ static struct pinctrl_pin_desc airoha_pinctrl_pins[] = {
>  	PINCTRL_PIN(63, "pcie_reset2"),
>  };
>  
> -static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 };
> -static const int pon_tod_1pps_pins[] = { 46 };
> -static const int gsw_tod_1pps_pins[] = { 46 };
> -static const int sipo_pins[] = { 16, 17 };
> -static const int sipo_rclk_pins[] = { 16, 17, 43 };
> -static const int mdio_pins[] = { 14, 15 };
> -static const int uart2_pins[] = { 48, 55 };
> -static const int uart2_cts_rts_pins[] = { 46, 47 };
> -static const int hsuart_pins[] = { 28, 29 };
> -static const int hsuart_cts_rts_pins[] = { 26, 27 };
> -static const int uart4_pins[] = { 38, 39 };
> -static const int uart5_pins[] = { 18, 19 };
> -static const int i2c0_pins[] = { 2, 3 };
> -static const int i2c1_pins[] = { 14, 15 };
> -static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
> -static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
> -static const int i2s_pins[] = { 26, 27, 28, 29 };
> -static const int pcm1_pins[] = { 22, 23, 24, 25 };
> -static const int pcm2_pins[] = { 18, 19, 20, 21 };
> -static const int spi_quad_pins[] = { 32, 33 };
> -static const int spi_pins[] = { 4, 5, 6, 7 };
> -static const int spi_cs1_pins[] = { 34 };
> -static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
> -static const int pcm_spi_int_pins[] = { 14 };
> -static const int pcm_spi_rst_pins[] = { 15 };
> -static const int pcm_spi_cs1_pins[] = { 43 };
> -static const int pcm_spi_cs2_pins[] = { 40 };
> -static const int pcm_spi_cs2_p128_pins[] = { 40 };
> -static const int pcm_spi_cs2_p156_pins[] = { 40 };
> -static const int pcm_spi_cs3_pins[] = { 41 };
> -static const int pcm_spi_cs4_pins[] = { 42 };
> -static const int emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
> -static const int pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
> -static const int gpio0_pins[] = { 13 };
> -static const int gpio1_pins[] = { 14 };
> -static const int gpio2_pins[] = { 15 };
> -static const int gpio3_pins[] = { 16 };
> -static const int gpio4_pins[] = { 17 };
> -static const int gpio5_pins[] = { 18 };
> -static const int gpio6_pins[] = { 19 };
> -static const int gpio7_pins[] = { 20 };
> -static const int gpio8_pins[] = { 21 };
> -static const int gpio9_pins[] = { 22 };
> -static const int gpio10_pins[] = { 23 };
> -static const int gpio11_pins[] = { 24 };
> -static const int gpio12_pins[] = { 25 };
> -static const int gpio13_pins[] = { 26 };
> -static const int gpio14_pins[] = { 27 };
> -static const int gpio15_pins[] = { 28 };
> -static const int gpio16_pins[] = { 29 };
> -static const int gpio17_pins[] = { 30 };
> -static const int gpio18_pins[] = { 31 };
> -static const int gpio19_pins[] = { 32 };
> -static const int gpio20_pins[] = { 33 };
> -static const int gpio21_pins[] = { 34 };
> -static const int gpio22_pins[] = { 35 };
> -static const int gpio23_pins[] = { 36 };
> -static const int gpio24_pins[] = { 37 };
> -static const int gpio25_pins[] = { 38 };
> -static const int gpio26_pins[] = { 39 };
> -static const int gpio27_pins[] = { 40 };
> -static const int gpio28_pins[] = { 41 };
> -static const int gpio29_pins[] = { 42 };
> -static const int gpio30_pins[] = { 43 };
> -static const int gpio31_pins[] = { 44 };
> -static const int gpio33_pins[] = { 46 };
> -static const int gpio34_pins[] = { 47 };
> -static const int gpio35_pins[] = { 48 };
> -static const int gpio36_pins[] = { 49 };
> -static const int gpio37_pins[] = { 50 };
> -static const int gpio38_pins[] = { 51 };
> -static const int gpio39_pins[] = { 52 };
> -static const int gpio40_pins[] = { 53 };
> -static const int gpio41_pins[] = { 54 };
> -static const int gpio42_pins[] = { 55 };
> -static const int gpio43_pins[] = { 56 };
> -static const int gpio44_pins[] = { 57 };
> -static const int gpio45_pins[] = { 58 };
> -static const int gpio46_pins[] = { 59 };
> -static const int pcie_reset0_pins[] = { 61 };
> -static const int pcie_reset1_pins[] = { 62 };
> -static const int pcie_reset2_pins[] = { 63 };
> -
> -static const struct pingroup airoha_pinctrl_groups[] = {
> -	PINCTRL_PIN_GROUP(pon),
> -	PINCTRL_PIN_GROUP(pon_tod_1pps),
> -	PINCTRL_PIN_GROUP(gsw_tod_1pps),
> -	PINCTRL_PIN_GROUP(sipo),
> -	PINCTRL_PIN_GROUP(sipo_rclk),
> -	PINCTRL_PIN_GROUP(mdio),
> -	PINCTRL_PIN_GROUP(uart2),
> -	PINCTRL_PIN_GROUP(uart2_cts_rts),
> -	PINCTRL_PIN_GROUP(hsuart),
> -	PINCTRL_PIN_GROUP(hsuart_cts_rts),
> -	PINCTRL_PIN_GROUP(uart4),
> -	PINCTRL_PIN_GROUP(uart5),
> -	PINCTRL_PIN_GROUP(i2c0),
> -	PINCTRL_PIN_GROUP(i2c1),
> -	PINCTRL_PIN_GROUP(jtag_udi),
> -	PINCTRL_PIN_GROUP(jtag_dfd),
> -	PINCTRL_PIN_GROUP(i2s),
> -	PINCTRL_PIN_GROUP(pcm1),
> -	PINCTRL_PIN_GROUP(pcm2),
> -	PINCTRL_PIN_GROUP(spi),
> -	PINCTRL_PIN_GROUP(spi_quad),
> -	PINCTRL_PIN_GROUP(spi_cs1),
> -	PINCTRL_PIN_GROUP(pcm_spi),
> -	PINCTRL_PIN_GROUP(pcm_spi_int),
> -	PINCTRL_PIN_GROUP(pcm_spi_rst),
> -	PINCTRL_PIN_GROUP(pcm_spi_cs1),
> -	PINCTRL_PIN_GROUP(pcm_spi_cs2_p128),
> -	PINCTRL_PIN_GROUP(pcm_spi_cs2_p156),
> -	PINCTRL_PIN_GROUP(pcm_spi_cs2),
> -	PINCTRL_PIN_GROUP(pcm_spi_cs3),
> -	PINCTRL_PIN_GROUP(pcm_spi_cs4),
> -	PINCTRL_PIN_GROUP(emmc),
> -	PINCTRL_PIN_GROUP(pnand),
> -	PINCTRL_PIN_GROUP(gpio0),
> -	PINCTRL_PIN_GROUP(gpio1),
> -	PINCTRL_PIN_GROUP(gpio2),
> -	PINCTRL_PIN_GROUP(gpio3),
> -	PINCTRL_PIN_GROUP(gpio4),
> -	PINCTRL_PIN_GROUP(gpio5),
> -	PINCTRL_PIN_GROUP(gpio6),
> -	PINCTRL_PIN_GROUP(gpio7),
> -	PINCTRL_PIN_GROUP(gpio8),
> -	PINCTRL_PIN_GROUP(gpio9),
> -	PINCTRL_PIN_GROUP(gpio10),
> -	PINCTRL_PIN_GROUP(gpio11),
> -	PINCTRL_PIN_GROUP(gpio12),
> -	PINCTRL_PIN_GROUP(gpio13),
> -	PINCTRL_PIN_GROUP(gpio14),
> -	PINCTRL_PIN_GROUP(gpio15),
> -	PINCTRL_PIN_GROUP(gpio16),
> -	PINCTRL_PIN_GROUP(gpio17),
> -	PINCTRL_PIN_GROUP(gpio18),
> -	PINCTRL_PIN_GROUP(gpio19),
> -	PINCTRL_PIN_GROUP(gpio20),
> -	PINCTRL_PIN_GROUP(gpio21),
> -	PINCTRL_PIN_GROUP(gpio22),
> -	PINCTRL_PIN_GROUP(gpio23),
> -	PINCTRL_PIN_GROUP(gpio24),
> -	PINCTRL_PIN_GROUP(gpio25),
> -	PINCTRL_PIN_GROUP(gpio26),
> -	PINCTRL_PIN_GROUP(gpio27),
> -	PINCTRL_PIN_GROUP(gpio28),
> -	PINCTRL_PIN_GROUP(gpio29),
> -	PINCTRL_PIN_GROUP(gpio30),
> -	PINCTRL_PIN_GROUP(gpio31),
> -	PINCTRL_PIN_GROUP(gpio33),
> -	PINCTRL_PIN_GROUP(gpio34),
> -	PINCTRL_PIN_GROUP(gpio35),
> -	PINCTRL_PIN_GROUP(gpio36),
> -	PINCTRL_PIN_GROUP(gpio37),
> -	PINCTRL_PIN_GROUP(gpio38),
> -	PINCTRL_PIN_GROUP(gpio39),
> -	PINCTRL_PIN_GROUP(gpio40),
> -	PINCTRL_PIN_GROUP(gpio41),
> -	PINCTRL_PIN_GROUP(gpio42),
> -	PINCTRL_PIN_GROUP(gpio43),
> -	PINCTRL_PIN_GROUP(gpio44),
> -	PINCTRL_PIN_GROUP(gpio45),
> -	PINCTRL_PIN_GROUP(gpio46),
> -	PINCTRL_PIN_GROUP(pcie_reset0),
> -	PINCTRL_PIN_GROUP(pcie_reset1),
> -	PINCTRL_PIN_GROUP(pcie_reset2),
> +static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
> +static const int en7581_pon_tod_1pps_pins[] = { 46 };
> +static const int en7581_gsw_tod_1pps_pins[] = { 46 };
> +static const int en7581_sipo_pins[] = { 16, 17 };
> +static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
> +static const int en7581_mdio_pins[] = { 14, 15 };
> +static const int en7581_uart2_pins[] = { 48, 55 };
> +static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
> +static const int en7581_hsuart_pins[] = { 28, 29 };
> +static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
> +static const int en7581_uart4_pins[] = { 38, 39 };
> +static const int en7581_uart5_pins[] = { 18, 19 };
> +static const int en7581_i2c0_pins[] = { 2, 3 };
> +static const int en7581_i2c1_pins[] = { 14, 15 };
> +static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
> +static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
> +static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
> +static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
> +static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
> +static const int en7581_spi_quad_pins[] = { 32, 33 };
> +static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
> +static const int en7581_spi_cs1_pins[] = { 34 };
> +static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
> +static const int en7581_pcm_spi_int_pins[] = { 14 };
> +static const int en7581_pcm_spi_rst_pins[] = { 15 };
> +static const int en7581_pcm_spi_cs1_pins[] = { 43 };
> +static const int en7581_pcm_spi_cs2_pins[] = { 40 };
> +static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
> +static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
> +static const int en7581_pcm_spi_cs3_pins[] = { 41 };
> +static const int en7581_pcm_spi_cs4_pins[] = { 42 };
> +static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
> +static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
> +static const int en7581_gpio0_pins[] = { 13 };
> +static const int en7581_gpio1_pins[] = { 14 };
> +static const int en7581_gpio2_pins[] = { 15 };
> +static const int en7581_gpio3_pins[] = { 16 };
> +static const int en7581_gpio4_pins[] = { 17 };
> +static const int en7581_gpio5_pins[] = { 18 };
> +static const int en7581_gpio6_pins[] = { 19 };
> +static const int en7581_gpio7_pins[] = { 20 };
> +static const int en7581_gpio8_pins[] = { 21 };
> +static const int en7581_gpio9_pins[] = { 22 };
> +static const int en7581_gpio10_pins[] = { 23 };
> +static const int en7581_gpio11_pins[] = { 24 };
> +static const int en7581_gpio12_pins[] = { 25 };
> +static const int en7581_gpio13_pins[] = { 26 };
> +static const int en7581_gpio14_pins[] = { 27 };
> +static const int en7581_gpio15_pins[] = { 28 };
> +static const int en7581_gpio16_pins[] = { 29 };
> +static const int en7581_gpio17_pins[] = { 30 };
> +static const int en7581_gpio18_pins[] = { 31 };
> +static const int en7581_gpio19_pins[] = { 32 };
> +static const int en7581_gpio20_pins[] = { 33 };
> +static const int en7581_gpio21_pins[] = { 34 };
> +static const int en7581_gpio22_pins[] = { 35 };
> +static const int en7581_gpio23_pins[] = { 36 };
> +static const int en7581_gpio24_pins[] = { 37 };
> +static const int en7581_gpio25_pins[] = { 38 };
> +static const int en7581_gpio26_pins[] = { 39 };
> +static const int en7581_gpio27_pins[] = { 40 };
> +static const int en7581_gpio28_pins[] = { 41 };
> +static const int en7581_gpio29_pins[] = { 42 };
> +static const int en7581_gpio30_pins[] = { 43 };
> +static const int en7581_gpio31_pins[] = { 44 };
> +static const int en7581_gpio33_pins[] = { 46 };
> +static const int en7581_gpio34_pins[] = { 47 };
> +static const int en7581_gpio35_pins[] = { 48 };
> +static const int en7581_gpio36_pins[] = { 49 };
> +static const int en7581_gpio37_pins[] = { 50 };
> +static const int en7581_gpio38_pins[] = { 51 };
> +static const int en7581_gpio39_pins[] = { 52 };
> +static const int en7581_gpio40_pins[] = { 53 };
> +static const int en7581_gpio41_pins[] = { 54 };
> +static const int en7581_gpio42_pins[] = { 55 };
> +static const int en7581_gpio43_pins[] = { 56 };
> +static const int en7581_gpio44_pins[] = { 57 };
> +static const int en7581_gpio45_pins[] = { 58 };
> +static const int en7581_gpio46_pins[] = { 59 };
> +static const int en7581_pcie_reset0_pins[] = { 61 };
> +static const int en7581_pcie_reset1_pins[] = { 62 };
> +static const int en7581_pcie_reset2_pins[] = { 63 };
> +
> +static const struct pingroup en7581_pinctrl_groups[] = {
> +	PINCTRL_PIN_GROUP("pon", en7581_pon),
> +	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
> +	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
> +	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
> +	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
> +	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
> +	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
> +	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
> +	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
> +	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
> +	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
> +	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
> +	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
> +	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
> +	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
> +	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
> +	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
> +	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
> +	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
> +	PINCTRL_PIN_GROUP("spi", en7581_spi),
> +	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
> +	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
> +	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
> +	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
> +	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
> +	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
> +	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
> +	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
> +	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
> +	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
> +	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
> +	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
> +	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
> +	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
> +	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
> +	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
> +	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
> +	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
> +	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
> +	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
> +	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
> +	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
> +	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
> +	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
> +	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
> +	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
> +	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
> +	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
> +	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
> +	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
> +	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
> +	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
> +	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
> +	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
> +	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
> +	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
> +	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
> +	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
> +	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
> +	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
> +	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
> +	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
> +	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
> +	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
> +	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
> +	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
> +	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
> +	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
> +	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
> +	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
> +	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
> +	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
> +	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
> +	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
> +	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
> +	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
> +	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
> +	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
> +	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
> +	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
> +	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
> +	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
>  };
>  
>  static const char *const pon_groups[] = { "pon" };
> @@ -1957,33 +1987,33 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
>  	},
>  };
>  
> -static const struct airoha_pinctrl_func airoha_pinctrl_funcs[] = {
> -	PINCTRL_FUNC_DESC(pon),
> -	PINCTRL_FUNC_DESC(tod_1pps),
> -	PINCTRL_FUNC_DESC(sipo),
> -	PINCTRL_FUNC_DESC(mdio),
> -	PINCTRL_FUNC_DESC(uart),
> -	PINCTRL_FUNC_DESC(i2c),
> -	PINCTRL_FUNC_DESC(jtag),
> -	PINCTRL_FUNC_DESC(pcm),
> -	PINCTRL_FUNC_DESC(spi),
> -	PINCTRL_FUNC_DESC(pcm_spi),
> -	PINCTRL_FUNC_DESC(i2s),
> -	PINCTRL_FUNC_DESC(emmc),
> -	PINCTRL_FUNC_DESC(pnand),
> -	PINCTRL_FUNC_DESC(pcie_reset),
> -	PINCTRL_FUNC_DESC(pwm),
> -	PINCTRL_FUNC_DESC(phy1_led0),
> -	PINCTRL_FUNC_DESC(phy2_led0),
> -	PINCTRL_FUNC_DESC(phy3_led0),
> -	PINCTRL_FUNC_DESC(phy4_led0),
> -	PINCTRL_FUNC_DESC(phy1_led1),
> -	PINCTRL_FUNC_DESC(phy2_led1),
> -	PINCTRL_FUNC_DESC(phy3_led1),
> -	PINCTRL_FUNC_DESC(phy4_led1),
> +static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
> +	PINCTRL_FUNC_DESC("pon", pon),
> +	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
> +	PINCTRL_FUNC_DESC("sipo", sipo),
> +	PINCTRL_FUNC_DESC("mdio", mdio),
> +	PINCTRL_FUNC_DESC("uart", uart),
> +	PINCTRL_FUNC_DESC("i2c", i2c),
> +	PINCTRL_FUNC_DESC("jtag", jtag),
> +	PINCTRL_FUNC_DESC("pcm", pcm),
> +	PINCTRL_FUNC_DESC("spi", spi),
> +	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
> +	PINCTRL_FUNC_DESC("i2s", i2s),
> +	PINCTRL_FUNC_DESC("emmc", emmc),
> +	PINCTRL_FUNC_DESC("pnand", pnand),
> +	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
> +	PINCTRL_FUNC_DESC("pwm", pwm),
> +	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
> +	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
> +	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
> +	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
> +	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
> +	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
> +	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
> +	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
>  };
>  
> -static const struct airoha_pinctrl_conf airoha_pinctrl_pullup_conf[] = {
> +static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
>  	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
>  	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
>  	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
> @@ -2044,7 +2074,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_pullup_conf[] = {
>  	PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
>  };
>  
> -static const struct airoha_pinctrl_conf airoha_pinctrl_pulldown_conf[] = {
> +static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
>  	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
>  	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
>  	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
> @@ -2105,7 +2135,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_pulldown_conf[] = {
>  	PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
>  };
>  
> -static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e2_conf[] = {
> +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
>  	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
>  	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
>  	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
> @@ -2166,7 +2196,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e2_conf[] = {
>  	PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
>  };
>  
> -static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e4_conf[] = {
> +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
>  	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
>  	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
>  	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
> @@ -2227,7 +2257,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e4_conf[] = {
>  	PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
>  };
>  
> -static const struct airoha_pinctrl_conf airoha_pinctrl_pcie_rst_od_conf[] = {
> +static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
>  	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
>  	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
>  	PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
> @@ -2548,12 +2578,17 @@ airoha_pinctrl_get_conf_reg(const struct airoha_pinctrl_conf *conf,
>  }
>  
>  static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,
> -				   const struct airoha_pinctrl_conf *conf,
> -				   int conf_size, int pin, u32 *val)
> +				   enum airoha_pinctrl_confs_type conf_type,
> +				   int pin, u32 *val)
>  {
> +	const struct airoha_pinctrl_confs_info *confs_info;
>  	const struct airoha_pinctrl_reg *reg;
>  
> -	reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
> +	confs_info = &pinctrl->confs_info[conf_type];
> +
> +	reg = airoha_pinctrl_get_conf_reg(confs_info->confs,
> +					  confs_info->num_confs,
> +					  pin);
>  	if (!reg)
>  		return -EINVAL;
>  
> @@ -2566,12 +2601,17 @@ static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,
>  }
>  
>  static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
> -				   const struct airoha_pinctrl_conf *conf,
> -				   int conf_size, int pin, u32 val)
> +				   enum airoha_pinctrl_confs_type conf_type,
> +				   int pin, u32 val)
>  {
> +	const struct airoha_pinctrl_confs_info *confs_info;
>  	const struct airoha_pinctrl_reg *reg = NULL;
>  
> -	reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
> +	confs_info = &pinctrl->confs_info[conf_type];
> +
> +	reg = airoha_pinctrl_get_conf_reg(confs_info->confs,
> +					  confs_info->num_confs,
> +					  pin);
>  	if (!reg)
>  		return -EINVAL;
>  
> @@ -2584,44 +2624,34 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
>  }
>  
>  #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)			\
> -	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pullup_conf,		\
> -				ARRAY_SIZE(airoha_pinctrl_pullup_conf),		\
> +	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
>  				(pin), (val))
>  #define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val)			\
> -	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pulldown_conf,	\
> -				ARRAY_SIZE(airoha_pinctrl_pulldown_conf),	\
> +	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,	\
>  				(pin), (val))
>  #define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val)			\
> -	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e2_conf,	\
> -				ARRAY_SIZE(airoha_pinctrl_drive_e2_conf),	\
> +	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,	\
>  				(pin), (val))
>  #define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val)			\
> -	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e4_conf,	\
> -				ARRAY_SIZE(airoha_pinctrl_drive_e4_conf),	\
> +	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,	\
>  				(pin), (val))
>  #define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val)			\
> -	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf,	\
> -				ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf),	\
> +	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,	\
>  				(pin), (val))
>  #define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val)			\
> -	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pullup_conf,		\
> -				ARRAY_SIZE(airoha_pinctrl_pullup_conf),		\
> +	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
>  				(pin), (val))
>  #define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val)			\
> -	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pulldown_conf,	\
> -				ARRAY_SIZE(airoha_pinctrl_pulldown_conf),	\
> +	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,	\
>  				(pin), (val))
>  #define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val)			\
> -	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e2_conf,	\
> -				ARRAY_SIZE(airoha_pinctrl_drive_e2_conf),	\
> +	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,	\
>  				(pin), (val))
>  #define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val)			\
> -	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e4_conf,	\
> -				ARRAY_SIZE(airoha_pinctrl_drive_e4_conf),	\
> +	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,	\
>  				(pin), (val))
>  #define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val)			\
> -	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf,	\
> -				ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf),	\
> +	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,	\
>  				(pin), (val))
>  
>  static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
> @@ -2798,12 +2828,13 @@ static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev,
>  static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev,
>  				    unsigned int group, unsigned long *config)
>  {
> +	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
>  	u32 cur_config = 0;
>  	int i;
>  
> -	for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
> +	for (i = 0; i < pinctrl->grps[group].npins; i++) {
>  		if (airoha_pinconf_get(pctrl_dev,
> -				       airoha_pinctrl_groups[group].pins[i],
> +				       pinctrl->grps[group].pins[i],
>  				       config))
>  			return -EOPNOTSUPP;
>  
> @@ -2820,13 +2851,14 @@ static int airoha_pinconf_group_set(struct pinctrl_dev *pctrl_dev,
>  				    unsigned int group, unsigned long *configs,
>  				    unsigned int num_configs)
>  {
> +	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
>  	int i;
>  
> -	for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
> +	for (i = 0; i < pinctrl->grps[group].npins; i++) {
>  		int err;
>  
>  		err = airoha_pinconf_set(pctrl_dev,
> -					 airoha_pinctrl_groups[group].pins[i],
> +					 pinctrl->grps[group].pins[i],
>  					 configs, num_configs);
>  		if (err)
>  			return err;
> @@ -2852,23 +2884,16 @@ static const struct pinctrl_ops airoha_pctlops = {
>  	.dt_free_map = pinconf_generic_dt_free_map,
>  };
>  
> -static struct pinctrl_desc airoha_pinctrl_desc = {
> -	.name = KBUILD_MODNAME,
> -	.owner = THIS_MODULE,
> -	.pctlops = &airoha_pctlops,
> -	.pmxops = &airoha_pmxops,
> -	.confops = &airoha_confops,
> -	.pins = airoha_pinctrl_pins,
> -	.npins = ARRAY_SIZE(airoha_pinctrl_pins),
> -};
> -
>  static int airoha_pinctrl_probe(struct platform_device *pdev)
>  {
> +	const struct airoha_pinctrl_match_data *data;
>  	struct device *dev = &pdev->dev;
>  	struct airoha_pinctrl *pinctrl;
>  	struct regmap *map;
>  	int err, i;
>  
> +	data = device_get_match_data(dev);
> +
>  	pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
>  	if (!pinctrl)
>  		return -ENOMEM;
> @@ -2883,14 +2908,23 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
>  
>  	pinctrl->chip_scu = map;
>  
> -	err = devm_pinctrl_register_and_init(dev, &airoha_pinctrl_desc,
> +	/* Init pinctrl desc struct */
> +	pinctrl->desc.name = KBUILD_MODNAME;
> +	pinctrl->desc.owner = THIS_MODULE,
> +	pinctrl->desc.pctlops = &airoha_pctlops,
> +	pinctrl->desc.pmxops = &airoha_pmxops,
> +	pinctrl->desc.confops = &airoha_confops,
> +	pinctrl->desc.pins = data->pins,
> +	pinctrl->desc.npins = data->num_pins,
> +
> +	err = devm_pinctrl_register_and_init(dev, &pinctrl->desc,
>  					     pinctrl, &pinctrl->ctrl);
>  	if (err)
>  		return err;
>  
>  	/* build pin groups */
> -	for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_groups); i++) {
> -		const struct pingroup *grp = &airoha_pinctrl_groups[i];
> +	for (i = 0; i < data->num_grps; i++) {
> +		const struct pingroup *grp = &data->grps[i];
>  
>  		err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name,
>  						grp->pins, grp->npins,
> @@ -2903,10 +2937,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
>  	}
>  
>  	/* build functions */
> -	for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_funcs); i++) {
> +	for (i = 0; i < data->num_funcs; i++) {
>  		const struct airoha_pinctrl_func *func;
>  
> -		func = &airoha_pinctrl_funcs[i];
> +		func = &data->funcs[i];
>  		err = pinmux_generic_add_function(pinctrl->ctrl,
>  						  func->desc.func.name,
>  						  func->desc.func.groups,
> @@ -2919,6 +2953,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
>  		}
>  	}
>  
> +	pinctrl->grps = data->grps;
> +	pinctrl->funcs = data->funcs;
> +	pinctrl->confs_info = data->confs_info;

I guess we can just use a airoha_pinctrl_match_data pointer here.

> +
>  	err = pinctrl_enable(pinctrl->ctrl);
>  	if (err)
>  		return err;
> @@ -2927,8 +2965,39 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
>  	return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
>  }
>  
> +static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
> +	.pins = en7581_pinctrl_pins,
> +	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
> +	.grps = en7581_pinctrl_groups,
> +	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
> +	.funcs = en7581_pinctrl_funcs,
> +	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
> +	.confs_info = {
> +		[AIROHA_PINCTRL_CONFS_PULLUP] = {
> +			.confs = en7581_pinctrl_pullup_conf,
> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
> +		},
> +		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
> +			.confs = en7581_pinctrl_pulldown_conf,
> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
> +		},
> +		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
> +			.confs = en7581_pinctrl_drive_e2_conf,
> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
> +		},
> +		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
> +			.confs = en7581_pinctrl_drive_e4_conf,
> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
> +		},
> +		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
> +			.confs = en7581_pinctrl_pcie_rst_od_conf,
> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
> +		},
> +	},
> +};
> +
>  static const struct of_device_id airoha_pinctrl_of_match[] = {
> -	{ .compatible = "airoha,en7581-pinctrl" },
> +	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
> -- 
> 2.48.1
> 
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From lorenzo at kernel.org  Wed May 28 01:21:03 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 28 May 2025 10:21:03 +0200
Subject: [PATCH 3/6] pinctrl: airoha: convert PHY LED GPIO to macro
In-Reply-To: <20250527222040.32000-4-ansuelsmth@gmail.com>
References: <20250527222040.32000-1-ansuelsmth@gmail.com>
 <20250527222040.32000-4-ansuelsmth@gmail.com>
Message-ID: <aDbHb4q44BWwHQpE@lore-desk>

> PHY LED GPIO pinctrl struct definition is very similar across the
> different 4 PHY and 2 LED and it can be generelized to a macro.
> 
> To reduce code size, convert them to a common macro.

Acked-by: Lorenzo Bianconi <lorenzo at kernel.org>

> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---
>  drivers/pinctrl/mediatek/pinctrl-airoha.c | 570 ++++------------------
>  1 file changed, 82 insertions(+), 488 deletions(-)
> 
> diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> index 8af9109db992..2b532334d759 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> @@ -1475,516 +1475,110 @@ static const struct airoha_pinctrl_func_group pwm_func_group[] = {
>  	},
>  };
>  
> +#define AIROHA_PINCTRL_PHY_LED(gpio, mux_val, map_mask, map_val)	\
> +	{								\
> +		.name = (gpio),						\
> +		.regmap[0] = {						\
> +			AIROHA_FUNC_MUX,				\
> +			REG_GPIO_2ND_I2C_MODE,				\
> +			(mux_val),					\
> +			(mux_val),					\
> +		},							\
> +		.regmap[1] = {						\
> +			AIROHA_FUNC_MUX,				\
> +			REG_LAN_LED0_MAPPING,				\
> +			(map_mask),					\
> +			(map_val),					\
> +		},							\
> +		.regmap_size = 2,					\
> +	}
> +
>  static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
> -	{
> -		.name = "gpio33",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN0_LED0_MODE_MASK,
> -			GPIO_LAN0_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN0_LED_MAPPING_MASK,
> -			LAN0_PHY_LED_MAP(0)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio34",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN1_LED0_MODE_MASK,
> -			GPIO_LAN1_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN1_LED_MAPPING_MASK,
> -			LAN1_PHY_LED_MAP(0)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio35",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN2_LED0_MODE_MASK,
> -			GPIO_LAN2_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN2_LED_MAPPING_MASK,
> -			LAN2_PHY_LED_MAP(0)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio42",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN3_LED0_MODE_MASK,
> -			GPIO_LAN3_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN3_LED_MAPPING_MASK,
> -			LAN3_PHY_LED_MAP(0)
> -		},
> -		.regmap_size = 2,
> -	},
> +	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> +			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> +			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> +			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> +			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>  };
>  
>  static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
> -	{
> -		.name = "gpio33",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN0_LED0_MODE_MASK,
> -			GPIO_LAN0_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN0_LED_MAPPING_MASK,
> -			LAN0_PHY_LED_MAP(1)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio34",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN1_LED0_MODE_MASK,
> -			GPIO_LAN1_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN1_LED_MAPPING_MASK,
> -			LAN1_PHY_LED_MAP(1)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio35",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN2_LED0_MODE_MASK,
> -			GPIO_LAN2_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN2_LED_MAPPING_MASK,
> -			LAN2_PHY_LED_MAP(1)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio42",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN3_LED0_MODE_MASK,
> -			GPIO_LAN3_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN3_LED_MAPPING_MASK,
> -			LAN3_PHY_LED_MAP(1)
> -		},
> -		.regmap_size = 2,
> -	},
> +	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> +			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> +			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> +			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> +			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>  };
>  
>  static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
> -	{
> -		.name = "gpio33",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN0_LED0_MODE_MASK,
> -			GPIO_LAN0_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN0_LED_MAPPING_MASK,
> -			LAN0_PHY_LED_MAP(2)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio34",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN1_LED0_MODE_MASK,
> -			GPIO_LAN1_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN1_LED_MAPPING_MASK,
> -			LAN1_PHY_LED_MAP(2)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio35",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN2_LED0_MODE_MASK,
> -			GPIO_LAN2_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN2_LED_MAPPING_MASK,
> -			LAN2_PHY_LED_MAP(2)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio42",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN3_LED0_MODE_MASK,
> -			GPIO_LAN3_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN3_LED_MAPPING_MASK,
> -			LAN3_PHY_LED_MAP(2)
> -		},
> -		.regmap_size = 2,
> -	},
> +	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> +			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> +			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> +			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> +			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>  };
>  
>  static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
> -	{
> -		.name = "gpio33",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN0_LED0_MODE_MASK,
> -			GPIO_LAN0_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN0_LED_MAPPING_MASK,
> -			LAN0_PHY_LED_MAP(3)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio34",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN1_LED0_MODE_MASK,
> -			GPIO_LAN1_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN1_LED_MAPPING_MASK,
> -			LAN1_PHY_LED_MAP(3)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio35",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN2_LED0_MODE_MASK,
> -			GPIO_LAN2_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN2_LED_MAPPING_MASK,
> -			LAN2_PHY_LED_MAP(3)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio42",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN3_LED0_MODE_MASK,
> -			GPIO_LAN3_LED0_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED0_MAPPING,
> -			LAN3_LED_MAPPING_MASK,
> -			LAN3_PHY_LED_MAP(3)
> -		},
> -		.regmap_size = 2,
> -	},
> +	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> +			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> +	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> +			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> +	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> +			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> +	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> +			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>  };
>  
>  static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
> -	{
> -		.name = "gpio43",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN0_LED1_MODE_MASK,
> -			GPIO_LAN0_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN0_LED_MAPPING_MASK,
> -			LAN0_PHY_LED_MAP(0)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio44",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN1_LED1_MODE_MASK,
> -			GPIO_LAN1_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN1_LED_MAPPING_MASK,
> -			LAN1_PHY_LED_MAP(0)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio45",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN2_LED1_MODE_MASK,
> -			GPIO_LAN2_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN2_LED_MAPPING_MASK,
> -			LAN2_PHY_LED_MAP(0)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio46",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN3_LED1_MODE_MASK,
> -			GPIO_LAN3_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN3_LED_MAPPING_MASK,
> -			LAN3_PHY_LED_MAP(0)
> -		},
> -		.regmap_size = 2,
> -	},
> +	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
> +			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
> +			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
> +			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
> +			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>  };
>  
>  static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
> -	{
> -		.name = "gpio43",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN0_LED1_MODE_MASK,
> -			GPIO_LAN0_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN0_LED_MAPPING_MASK,
> -			LAN0_PHY_LED_MAP(1)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio44",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN1_LED1_MODE_MASK,
> -			GPIO_LAN1_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN1_LED_MAPPING_MASK,
> -			LAN1_PHY_LED_MAP(1)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio45",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN2_LED1_MODE_MASK,
> -			GPIO_LAN2_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN2_LED_MAPPING_MASK,
> -			LAN2_PHY_LED_MAP(1)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio46",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN3_LED1_MODE_MASK,
> -			GPIO_LAN3_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN3_LED_MAPPING_MASK,
> -			LAN3_PHY_LED_MAP(1)
> -		},
> -		.regmap_size = 2,
> -	},
> +	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
> +			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
> +			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
> +			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
> +			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>  };
>  
>  static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
> -	{
> -		.name = "gpio43",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN0_LED1_MODE_MASK,
> -			GPIO_LAN0_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN0_LED_MAPPING_MASK,
> -			LAN0_PHY_LED_MAP(2)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio44",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN1_LED1_MODE_MASK,
> -			GPIO_LAN1_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN1_LED_MAPPING_MASK,
> -			LAN1_PHY_LED_MAP(2)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio45",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN2_LED1_MODE_MASK,
> -			GPIO_LAN2_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN2_LED_MAPPING_MASK,
> -			LAN2_PHY_LED_MAP(2)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio46",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN3_LED1_MODE_MASK,
> -			GPIO_LAN3_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN3_LED_MAPPING_MASK,
> -			LAN3_PHY_LED_MAP(2)
> -		},
> -		.regmap_size = 2,
> -	},
> +	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
> +			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
> +			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
> +			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
> +			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>  };
>  
>  static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
> -	{
> -		.name = "gpio43",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN0_LED1_MODE_MASK,
> -			GPIO_LAN0_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN0_LED_MAPPING_MASK,
> -			LAN0_PHY_LED_MAP(3)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio44",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN1_LED1_MODE_MASK,
> -			GPIO_LAN1_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN1_LED_MAPPING_MASK,
> -			LAN1_PHY_LED_MAP(3)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio45",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN2_LED1_MODE_MASK,
> -			GPIO_LAN2_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN2_LED_MAPPING_MASK,
> -			LAN2_PHY_LED_MAP(3)
> -		},
> -		.regmap_size = 2,
> -	}, {
> -		.name = "gpio46",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_LAN3_LED1_MODE_MASK,
> -			GPIO_LAN3_LED1_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_LAN_LED1_MAPPING,
> -			LAN3_LED_MAPPING_MASK,
> -			LAN3_PHY_LED_MAP(3)
> -		},
> -		.regmap_size = 2,
> -	},
> +	AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
> +			       LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
> +			       LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
> +			       LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
> +			       LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>  };
>  
>  static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
> -- 
> 2.48.1
> 
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From lorenzo at kernel.org  Wed May 28 01:22:22 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 28 May 2025 10:22:22 +0200
Subject: [PATCH 4/6] pinctrl: airoha: convert PWM GPIO to macro
In-Reply-To: <20250527222040.32000-5-ansuelsmth@gmail.com>
References: <20250527222040.32000-1-ansuelsmth@gmail.com>
 <20250527222040.32000-5-ansuelsmth@gmail.com>
Message-ID: <aDbHvjPII0jlua18@lore-desk>

> The PWM GPIO struct definition follow the same pattern for every GPIO
> pin hence it can be converted to a macro.
> 
> Create 2 macro one for normal mux and one for ext mux and convert all
> the entry to these new macro to reduce code size.
> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---

Acked-by: Lorenzo Bianconi <lorenzo at kernel.org>

>  drivers/pinctrl/mediatek/pinctrl-airoha.c | 465 ++++------------------
>  1 file changed, 68 insertions(+), 397 deletions(-)
> 
> diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> index 2b532334d759..8c8d5b598f4f 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> @@ -1075,404 +1075,75 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
>  };
>  
>  /* PWM */
> +#define AIROHA_PINCTRL_PWM(gpio, mux_val)		\
> +	{						\
> +		.name = (gpio),				\
> +		.regmap[0] = {				\
> +			AIROHA_FUNC_PWM_MUX,		\
> +			REG_GPIO_FLASH_MODE_CFG,	\
> +			(mux_val),			\
> +			(mux_val)			\
> +		},					\
> +		.regmap_size = 1,			\
> +	}						\
> +
> +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)		\
> +	{						\
> +		.name = (gpio),				\
> +		.regmap[0] = {				\
> +			AIROHA_FUNC_PWM_EXT_MUX,	\
> +			REG_GPIO_FLASH_MODE_CFG_EXT,	\
> +			(mux_val),			\
> +			(mux_val)			\
> +		},					\
> +		.regmap_size = 1,			\
> +	}						\
> +
>  static const struct airoha_pinctrl_func_group pwm_func_group[] = {
> -	{
> -		.name = "gpio0",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO0_FLASH_MODE_CFG,
> -			GPIO0_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio1",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO1_FLASH_MODE_CFG,
> -			GPIO1_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio2",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO2_FLASH_MODE_CFG,
> -			GPIO2_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio3",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO3_FLASH_MODE_CFG,
> -			GPIO3_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio4",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO4_FLASH_MODE_CFG,
> -			GPIO4_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio5",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO5_FLASH_MODE_CFG,
> -			GPIO5_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio6",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO6_FLASH_MODE_CFG,
> -			GPIO6_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio7",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO7_FLASH_MODE_CFG,
> -			GPIO7_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio8",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO8_FLASH_MODE_CFG,
> -			GPIO8_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio9",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO9_FLASH_MODE_CFG,
> -			GPIO9_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio10",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO10_FLASH_MODE_CFG,
> -			GPIO10_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio11",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO11_FLASH_MODE_CFG,
> -			GPIO11_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio12",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO12_FLASH_MODE_CFG,
> -			GPIO12_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio13",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO13_FLASH_MODE_CFG,
> -			GPIO13_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio14",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO14_FLASH_MODE_CFG,
> -			GPIO14_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio15",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_MUX,
> -			REG_GPIO_FLASH_MODE_CFG,
> -			GPIO15_FLASH_MODE_CFG,
> -			GPIO15_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio16",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO16_FLASH_MODE_CFG,
> -			GPIO16_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio17",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO17_FLASH_MODE_CFG,
> -			GPIO17_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio18",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO18_FLASH_MODE_CFG,
> -			GPIO18_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio19",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO19_FLASH_MODE_CFG,
> -			GPIO19_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio20",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO20_FLASH_MODE_CFG,
> -			GPIO20_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio21",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO21_FLASH_MODE_CFG,
> -			GPIO21_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio22",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO22_FLASH_MODE_CFG,
> -			GPIO22_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio23",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO23_FLASH_MODE_CFG,
> -			GPIO23_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio24",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO24_FLASH_MODE_CFG,
> -			GPIO24_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio25",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO25_FLASH_MODE_CFG,
> -			GPIO25_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio26",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO26_FLASH_MODE_CFG,
> -			GPIO26_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio27",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO27_FLASH_MODE_CFG,
> -			GPIO27_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio28",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO28_FLASH_MODE_CFG,
> -			GPIO28_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio29",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO29_FLASH_MODE_CFG,
> -			GPIO29_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio30",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO30_FLASH_MODE_CFG,
> -			GPIO30_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio31",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO31_FLASH_MODE_CFG,
> -			GPIO31_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio36",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO36_FLASH_MODE_CFG,
> -			GPIO36_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio37",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO37_FLASH_MODE_CFG,
> -			GPIO37_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio38",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO38_FLASH_MODE_CFG,
> -			GPIO38_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio39",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO39_FLASH_MODE_CFG,
> -			GPIO39_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio40",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO40_FLASH_MODE_CFG,
> -			GPIO40_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio41",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO41_FLASH_MODE_CFG,
> -			GPIO41_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio42",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO42_FLASH_MODE_CFG,
> -			GPIO42_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio43",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO43_FLASH_MODE_CFG,
> -			GPIO43_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio44",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO44_FLASH_MODE_CFG,
> -			GPIO44_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio45",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO45_FLASH_MODE_CFG,
> -			GPIO45_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio46",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO46_FLASH_MODE_CFG,
> -			GPIO46_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gpio47",
> -		.regmap[0] = {
> -			AIROHA_FUNC_PWM_EXT_MUX,
> -			REG_GPIO_FLASH_MODE_CFG_EXT,
> -			GPIO47_FLASH_MODE_CFG,
> -			GPIO47_FLASH_MODE_CFG
> -		},
> -		.regmap_size = 1,
> -	},
> +	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG),
>  };
>  
>  #define AIROHA_PINCTRL_PHY_LED(gpio, mux_val, map_mask, map_val)	\
> -- 
> 2.48.1
> 
-------------- next part --------------
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From tzimmermann at suse.de  Wed May 28 01:23:41 2025
From: tzimmermann at suse.de (Thomas Zimmermann)
Date: Wed, 28 May 2025 10:23:41 +0200
Subject: [PATCH v4 00/25] drm/dumb-buffers: Fix and improve buffer-size
 calculation
In-Reply-To: <20250311155120.442633-1-tzimmermann@suse.de>
References: <20250311155120.442633-1-tzimmermann@suse.de>
Message-ID: <1926848a-9334-4c15-a076-a93ef29c80d6@suse.de>

ping

I'm still looking for more reviews; especially patches 1 and 2.

Best regards
Thomas

Am 11.03.25 um 16:47 schrieb Thomas Zimmermann:
> Dumb-buffer pitch and size is specified by width, height, bits-per-pixel
> plus various hardware-specific alignments. The calculation of these
> values is inconsistent and duplicated among drivers. The results for
> formats with bpp < 8 are sometimes incorrect.
>
> This series fixes this for most drivers. Default scanline pitch and
> buffer size are now calculated with the existing 4CC helpers. There is
> a new helper drm_mode_size_dumb() that calculates scanline pitch and
> buffer size according to driver requirements.
>
> The series fixes the common GEM implementations for DMA, SHMEM and
> VRAM. It further changes most implementations of dumb_create to use
> the new helper. A small number of drivers has more complicated
> calculations and will be updated by a later patches.
>
> v4:
> - improve UAPI documentation
> - document bpp special cases
> - use drm_warn_once()
> - add TODO lists
> - armada: fix pitch alignment
> v3:
> - document UAPI semantics
> - fall back to bpp-based allocation for unknown color modes
> - cleanups
> v2:
> - rewrite series
> - convert many individual drivers besides the shared GEM helpers
>
> Thomas Zimmermann (25):
>    drm/dumb-buffers: Sanitize output on errors
>    drm/dumb-buffers: Provide helper to set pitch and size
>    drm/gem-dma: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/gem-shmem: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/gem-vram: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/armada: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/exynos: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/gma500: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/hibmc: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/imx/ipuv3: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/loongson: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/mediatek: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/msm: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/nouveau: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/omapdrm: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/qxl: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/renesas/rcar-du: Compute dumb-buffer sizes with
>      drm_mode_size_dumb()
>    drm/renesas/rz-du: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/rockchip: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/tegra: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/virtio: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/vmwgfx: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/xe: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/xen: Compute dumb-buffer sizes with drm_mode_size_dumb()
>    drm/xlnx: Compute dumb-buffer sizes with drm_mode_size_dumb()
>
>   Documentation/gpu/todo.rst                    |  28 +++
>   drivers/gpu/drm/armada/armada_gem.c           |  16 +-
>   drivers/gpu/drm/drm_dumb_buffers.c            | 172 ++++++++++++++++--
>   drivers/gpu/drm/drm_gem_dma_helper.c          |   7 +-
>   drivers/gpu/drm/drm_gem_shmem_helper.c        |  16 +-
>   drivers/gpu/drm/drm_gem_vram_helper.c         |  89 +++------
>   drivers/gpu/drm/exynos/exynos_drm_gem.c       |   8 +-
>   drivers/gpu/drm/gma500/gem.c                  |  21 +--
>   .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c   |  25 ++-
>   drivers/gpu/drm/imx/ipuv3/imx-drm-core.c      |  29 ++-
>   drivers/gpu/drm/loongson/lsdc_gem.c           |  29 +--
>   drivers/gpu/drm/mediatek/mtk_gem.c            |  13 +-
>   drivers/gpu/drm/msm/msm_gem.c                 |  27 ++-
>   drivers/gpu/drm/nouveau/nouveau_display.c     |   7 +-
>   drivers/gpu/drm/omapdrm/omap_gem.c            |  15 +-
>   drivers/gpu/drm/qxl/qxl_dumb.c                |  17 +-
>   drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c |   7 +-
>   drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c  |   7 +-
>   drivers/gpu/drm/rockchip/rockchip_drm_gem.c   |  12 +-
>   drivers/gpu/drm/tegra/gem.c                   |   8 +-
>   drivers/gpu/drm/virtio/virtgpu_gem.c          |  11 +-
>   drivers/gpu/drm/vmwgfx/vmwgfx_surface.c       |  21 +--
>   drivers/gpu/drm/xe/xe_bo.c                    |   8 +-
>   drivers/gpu/drm/xen/xen_drm_front.c           |   7 +-
>   drivers/gpu/drm/xlnx/zynqmp_kms.c             |   7 +-
>   include/drm/drm_dumb_buffers.h                |  14 ++
>   include/drm/drm_gem_vram_helper.h             |   6 -
>   include/uapi/drm/drm_mode.h                   |  50 ++++-
>   28 files changed, 449 insertions(+), 228 deletions(-)
>   create mode 100644 include/drm/drm_dumb_buffers.h
>

-- 
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)



From jinjian.song at fibocom.com  Wed May 28 01:28:27 2025
From: jinjian.song at fibocom.com (Jinjian Song)
Date: Wed, 28 May 2025 16:28:27 +0800
Subject: [net v2] net: wwan: t7xx: Fix napi rx poll issue
Message-ID: <20250528082827.4654-1-jinjian.song@fibocom.com>

When driver handles the napi rx polling requests, the netdev might
have been released by the dellink logic triggered by the disconnect
operation on user plane. However, in the logic of processing skb in
polling, an invalid netdev is still being used, which causes a panic.

BUG: kernel NULL pointer dereference, address: 00000000000000f1
Oops: 0000 [#1] PREEMPT SMP NOPTI
RIP: 0010:dev_gro_receive+0x3a/0x620
[...]
Call Trace:
 <IRQ>
 ? __die_body+0x68/0xb0
 ? page_fault_oops+0x379/0x3e0
 ? exc_page_fault+0x4f/0xa0
 ? asm_exc_page_fault+0x22/0x30
 ? __pfx_t7xx_ccmni_recv_skb+0x10/0x10 [mtk_t7xx (HASH:1400 7)]
 ? dev_gro_receive+0x3a/0x620
 napi_gro_receive+0xad/0x170
 t7xx_ccmni_recv_skb+0x48/0x70 [mtk_t7xx (HASH:1400 7)]
 t7xx_dpmaif_napi_rx_poll+0x590/0x800 [mtk_t7xx (HASH:1400 7)]
 net_rx_action+0x103/0x470
 irq_exit_rcu+0x13a/0x310
 sysvec_apic_timer_interrupt+0x56/0x90
 </IRQ>

Fixes: 5545b7b9f294 ("net: wwan: t7xx: Add NAPI support")
Signed-off-by: Jinjian Song <jinjian.song at fibocom.com>
---
 drivers/net/wwan/t7xx/t7xx_netdev.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/net/wwan/t7xx/t7xx_netdev.c b/drivers/net/wwan/t7xx/t7xx_netdev.c
index 91fa082e9cab..48007384c030 100644
--- a/drivers/net/wwan/t7xx/t7xx_netdev.c
+++ b/drivers/net/wwan/t7xx/t7xx_netdev.c
@@ -172,7 +172,7 @@ static void t7xx_ccmni_start(struct t7xx_ccmni_ctrl *ctlb)
 	int i;
 
 	for (i = 0; i < ctlb->nic_dev_num; i++) {
-		ccmni = ctlb->ccmni_inst[i];
+		ccmni = READ_ONCE(ctlb->ccmni_inst[i]);
 		if (!ccmni)
 			continue;
 
@@ -192,7 +192,7 @@ static void t7xx_ccmni_pre_stop(struct t7xx_ccmni_ctrl *ctlb)
 	int i;
 
 	for (i = 0; i < ctlb->nic_dev_num; i++) {
-		ccmni = ctlb->ccmni_inst[i];
+		ccmni = READ_ONCE(ctlb->ccmni_inst[i]);
 		if (!ccmni)
 			continue;
 
@@ -210,7 +210,7 @@ static void t7xx_ccmni_post_stop(struct t7xx_ccmni_ctrl *ctlb)
 		t7xx_ccmni_disable_napi(ctlb);
 
 	for (i = 0; i < ctlb->nic_dev_num; i++) {
-		ccmni = ctlb->ccmni_inst[i];
+		ccmni = READ_ONCE(ctlb->ccmni_inst[i]);
 		if (!ccmni)
 			continue;
 
@@ -302,7 +302,7 @@ static int t7xx_ccmni_wwan_newlink(void *ctxt, struct net_device *dev, u32 if_id
 	ccmni->ctlb = ctlb;
 	ccmni->dev = dev;
 	atomic_set(&ccmni->usage, 0);
-	ctlb->ccmni_inst[if_id] = ccmni;
+	WRITE_ONCE(ctlb->ccmni_inst[if_id], ccmni);
 
 	ret = register_netdevice(dev);
 	if (ret)
@@ -321,9 +321,10 @@ static void t7xx_ccmni_wwan_dellink(void *ctxt, struct net_device *dev, struct l
 	if (if_id >= ARRAY_SIZE(ctlb->ccmni_inst))
 		return;
 
-	if (WARN_ON(ctlb->ccmni_inst[if_id] != ccmni))
+	if (WARN_ON(READ_ONCE(ctlb->ccmni_inst[if_id]) != ccmni))
 		return;
 
+	WRITE_ONCE(ctlb->ccmni_inst[if_id], NULL);
 	unregister_netdevice(dev);
 }
 
@@ -419,7 +420,7 @@ static void t7xx_ccmni_recv_skb(struct t7xx_ccmni_ctrl *ccmni_ctlb, struct sk_bu
 
 	skb_cb = T7XX_SKB_CB(skb);
 	netif_id = skb_cb->netif_idx;
-	ccmni = ccmni_ctlb->ccmni_inst[netif_id];
+	ccmni = READ_ONCE(ccmni_ctlb->ccmni_inst[netif_id]);
 	if (!ccmni) {
 		dev_kfree_skb(skb);
 		return;
@@ -441,7 +442,7 @@ static void t7xx_ccmni_recv_skb(struct t7xx_ccmni_ctrl *ccmni_ctlb, struct sk_bu
 
 static void t7xx_ccmni_queue_tx_irq_notify(struct t7xx_ccmni_ctrl *ctlb, int qno)
 {
-	struct t7xx_ccmni *ccmni = ctlb->ccmni_inst[0];
+	struct t7xx_ccmni *ccmni = READ_ONCE(ctlb->ccmni_inst[0]);
 	struct netdev_queue *net_queue;
 
 	if (netif_running(ccmni->dev) && atomic_read(&ccmni->usage) > 0) {
@@ -453,7 +454,7 @@ static void t7xx_ccmni_queue_tx_irq_notify(struct t7xx_ccmni_ctrl *ctlb, int qno
 
 static void t7xx_ccmni_queue_tx_full_notify(struct t7xx_ccmni_ctrl *ctlb, int qno)
 {
-	struct t7xx_ccmni *ccmni = ctlb->ccmni_inst[0];
+	struct t7xx_ccmni *ccmni = READ_ONCE(ctlb->ccmni_inst[0]);
 	struct netdev_queue *net_queue;
 
 	if (atomic_read(&ccmni->usage) > 0) {
@@ -471,7 +472,7 @@ static void t7xx_ccmni_queue_state_notify(struct t7xx_pci_dev *t7xx_dev,
 	if (ctlb->md_sta != MD_STATE_READY)
 		return;
 
-	if (!ctlb->ccmni_inst[0]) {
+	if (!READ_ONCE(ctlb->ccmni_inst[0])) {
 		dev_warn(&t7xx_dev->pdev->dev, "No netdev registered yet\n");
 		return;
 	}
-- 
2.34.1



From benjamin.larsson at genexis.eu  Wed May 28 02:20:53 2025
From: benjamin.larsson at genexis.eu (Benjamin Larsson)
Date: Wed, 28 May 2025 11:20:53 +0200
Subject: [PATCH 6/6] pinctrl: airoha: add support for Airoha AN7583 PINs
In-Reply-To: <20250527222040.32000-7-ansuelsmth@gmail.com>
References: <20250527222040.32000-1-ansuelsmth@gmail.com>
 <20250527222040.32000-7-ansuelsmth@gmail.com>
Message-ID: <b1f58f49-83b3-48c3-8c44-4c82fcd2f69b@genexis.eu>

Hi.

On 28/05/2025 00:20, Christian Marangi wrote:
> Add all the required entry to add suppot for Airoha AN7583 PINs.
> 
> Where possible the same function group are used from Airoha EN7581 to
> reduce code duplication.
> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---
>   drivers/pinctrl/mediatek/pinctrl-airoha.c | 733 ++++++++++++++++++++++
>   1 file changed, 733 insertions(+)
> 
> diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> index 8c8d5b598f4f..0960649d5d66 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> @@ -75,6 +75,7 @@
>   #define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
>   #define GPIO_PCM_SPI_CS2_MODE_P156_MASK		BIT(19)
>   #define GPIO_PCM_SPI_CS2_MODE_P128_MASK		BIT(18)
> +#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK	BIT(18)
>   #define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
>   #define GPIO_PCM_SPI_MODE_MASK			BIT(16)
>   #define GPIO_PCM2_MODE_MASK			BIT(13)

Missing are the pinmuxes for the following:

	{ RG_BCDR_FLUSH_EN,	IOMUX3, 1<<28},
	{ RG_GPIO_PON2_MODE,	IOMUX3, 1<<27},
	{ RG_MDIO_0_GPIO_MODE,	IOMUX3, 1<<26},
	{ RG_MDC_0_GPIO_MODE,	IOMUX3, 1<<25},
	{ RG_UART_RXD_GPIO_MODE,	IOMUX3, 1<<24},
	{ RG_UART_TXD_GPIO_MODE,	IOMUX3, 1<<23},
	{ RG_SPI_MISO_GPIO_MODE,	IOMUX3, 1<<22},
	{ RG_SPI_MOSI_GPIO_MODE,	IOMUX3, 1<<21},
	{ RG_SPI_CS_GPIO_MODE,	IOMUX3, 1<<20},
	{ RG_SPI_CLK_GPIO_MODE,	IOMUX3, 1<<19},
	{ RG_I2C1_SDA_GPIO_MODE,	IOMUX3, 1<<18},
	{ RG_I2C1_SCL_GPIO_MODE,	IOMUX3, 1<<17},
	{ RG_I2C0_SDA_GPIO_MODE,	IOMUX3, 1<<16},
	{ RG_I2C0_SCL_GPIO_MODE,	IOMUX3, 1<<15},



> @@ -129,6 +130,8 @@
>   
>   /* CONF */
>   #define REG_I2C_SDA_E2				0x001c
> +#define AN7583_I2C1_SCL_E2_MASK			BIT(16)
> +#define AN7583_I2C1_SDA_E2_MASK			BIT(15)
>   #define SPI_MISO_E2_MASK			BIT(14)
>   #define SPI_MOSI_E2_MASK			BIT(13)
>   #define SPI_CLK_E2_MASK				BIT(12)
> @@ -136,12 +139,16 @@
>   #define PCIE2_RESET_E2_MASK			BIT(10)
>   #define PCIE1_RESET_E2_MASK			BIT(9)
>   #define PCIE0_RESET_E2_MASK			BIT(8)
> +#define AN7583_MDIO_0_E2_MASK			BIT(5)
> +#define AN7583_MDC_0_E2_MASK			BIT(4)
>   #define UART1_RXD_E2_MASK			BIT(3)
>   #define UART1_TXD_E2_MASK			BIT(2)
>   #define I2C_SCL_E2_MASK				BIT(1)
>   #define I2C_SDA_E2_MASK				BIT(0)
>   
>   #define REG_I2C_SDA_E4				0x0020
> +#define AN7583_I2C1_SCL_E4_MASK			BIT(16)
> +#define AN7583_I2C1_SDA_E4_MASK			BIT(15)
>   #define SPI_MISO_E4_MASK			BIT(14)
>   #define SPI_MOSI_E4_MASK			BIT(13)
>   #define SPI_CLK_E4_MASK				BIT(12)
> @@ -149,6 +156,8 @@
>   #define PCIE2_RESET_E4_MASK			BIT(10)
>   #define PCIE1_RESET_E4_MASK			BIT(9)
>   #define PCIE0_RESET_E4_MASK			BIT(8)
> +#define AN7583_MDIO_0_E4_MASK			BIT(5)
> +#define AN7583_MDC_0_E4_MASK			BIT(4)
>   #define UART1_RXD_E4_MASK			BIT(3)
>   #define UART1_TXD_E4_MASK			BIT(2)
>   #define I2C_SCL_E4_MASK				BIT(1)
> @@ -160,6 +169,8 @@
>   #define REG_GPIO_H_E4				0x0030
>   
>   #define REG_I2C_SDA_PU				0x0044
> +#define AN7583_I2C1_SCL_PU_MASK			BIT(16)
> +#define AN7583_I2C1_SDA_PU_MASK			BIT(15)
>   #define SPI_MISO_PU_MASK			BIT(14)
>   #define SPI_MOSI_PU_MASK			BIT(13)
>   #define SPI_CLK_PU_MASK				BIT(12)
> @@ -167,12 +178,16 @@
>   #define PCIE2_RESET_PU_MASK			BIT(10)
>   #define PCIE1_RESET_PU_MASK			BIT(9)
>   #define PCIE0_RESET_PU_MASK			BIT(8)
> +#define AN7583_MDIO_0_PU_MASK			BIT(5)
> +#define AN7583_MDC_0_PU_MASK			BIT(4)
>   #define UART1_RXD_PU_MASK			BIT(3)
>   #define UART1_TXD_PU_MASK			BIT(2)
>   #define I2C_SCL_PU_MASK				BIT(1)
>   #define I2C_SDA_PU_MASK				BIT(0)
>   
>   #define REG_I2C_SDA_PD				0x0048
> +#define AN7583_I2C1_SDA_PD_MASK			BIT(16)
> +#define AN7583_I2C1_SCL_PD_MASK			BIT(15)
>   #define SPI_MISO_PD_MASK			BIT(14)
>   #define SPI_MOSI_PD_MASK			BIT(13)
>   #define SPI_CLK_PD_MASK				BIT(12)
> @@ -180,6 +195,8 @@
>   #define PCIE2_RESET_PD_MASK			BIT(10)
>   #define PCIE1_RESET_PD_MASK			BIT(9)
>   #define PCIE0_RESET_PD_MASK			BIT(8)
> +#define AN7583_MDIO_0_PD_MASK			BIT(5)
> +#define AN7583_MDC_0_PD_MASK			BIT(4)
>   #define UART1_RXD_PD_MASK			BIT(3)
>   #define UART1_TXD_PD_MASK			BIT(2)
>   #define I2C_SCL_PD_MASK				BIT(1)
> @@ -627,10 +644,223 @@ static const struct pingroup en7581_pinctrl_groups[] = {
>   	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
>   };
>   
> +static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
> +	PINCTRL_PIN(2, "gpio0"),
> +	PINCTRL_PIN(3, "gpio1"),
> +	PINCTRL_PIN(4, "gpio2"),
> +	PINCTRL_PIN(5, "gpio3"),
> +	PINCTRL_PIN(6, "gpio4"),
> +	PINCTRL_PIN(7, "gpio5"),
> +	PINCTRL_PIN(8, "gpio6"),
> +	PINCTRL_PIN(9, "gpio7"),
> +	PINCTRL_PIN(10, "gpio8"),
> +	PINCTRL_PIN(11, "gpio9"),
> +	PINCTRL_PIN(12, "gpio10"),
> +	PINCTRL_PIN(13, "gpio11"),
> +	PINCTRL_PIN(14, "gpio12"),
> +	PINCTRL_PIN(15, "gpio13"),
> +	PINCTRL_PIN(16, "gpio14"),
> +	PINCTRL_PIN(17, "gpio15"),
> +	PINCTRL_PIN(18, "gpio16"),
> +	PINCTRL_PIN(19, "gpio17"),
> +	PINCTRL_PIN(20, "gpio18"),
> +	PINCTRL_PIN(21, "gpio19"),
> +	PINCTRL_PIN(22, "gpio20"),
> +	PINCTRL_PIN(23, "gpio21"),
> +	PINCTRL_PIN(24, "gpio22"),
> +	PINCTRL_PIN(25, "gpio23"),
> +	PINCTRL_PIN(26, "gpio24"),
> +	PINCTRL_PIN(27, "gpio25"),
> +	PINCTRL_PIN(28, "gpio26"),
> +	PINCTRL_PIN(29, "gpio27"),
> +	PINCTRL_PIN(30, "gpio28"),
> +	PINCTRL_PIN(31, "gpio29"),
> +	PINCTRL_PIN(32, "gpio30"),
> +	PINCTRL_PIN(33, "gpio31"),
> +	PINCTRL_PIN(34, "gpio32"),
> +	PINCTRL_PIN(35, "gpio33"),
> +	PINCTRL_PIN(36, "gpio34"),
> +	PINCTRL_PIN(37, "gpio35"),
> +	PINCTRL_PIN(38, "gpio36"),
> +	PINCTRL_PIN(39, "gpio37"),
> +	PINCTRL_PIN(40, "gpio38"),
> +	PINCTRL_PIN(41, "i2c0_scl"),
> +	PINCTRL_PIN(42, "i2c0_sda"),
> +	PINCTRL_PIN(43, "i2c1_scl"),
> +	PINCTRL_PIN(44, "i2c1_sda"),
> +	PINCTRL_PIN(45, "spi_clk"),
> +	PINCTRL_PIN(46, "spi_cs"),
> +	PINCTRL_PIN(47, "spi_mosi"),
> +	PINCTRL_PIN(48, "spi_miso"),
> +	PINCTRL_PIN(49, "uart_txd"),
> +	PINCTRL_PIN(50, "uart_rxd"),
> +	PINCTRL_PIN(51, "pcie_reset0"),
> +	PINCTRL_PIN(52, "pcie_reset1"),
> +	PINCTRL_PIN(53, "mdc_0"),
> +	PINCTRL_PIN(54, "mdio_0"),
> +};
> +
> +static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };

I have other pin numbers listed in my documentation (my numbers align 
with gpio number).

static const int pon_pins0[] = { 13, 14, 17, 18 };
static const int pon_pins1[] = { 36, 37, 38 };
static const int olt_pins0[] = { 34, 35, 36, 37, 38 };


MvH
Benjamin Larsson


From luca.ceresoli at bootlin.com  Wed May 28 02:29:36 2025
From: luca.ceresoli at bootlin.com (Luca Ceresoli)
Date: Wed, 28 May 2025 11:29:36 +0200
Subject: [PATCH v4] drm/bridge: tc358767: convert to
 devm_drm_bridge_alloc() API
Message-ID: <20250528-drm-bridge-convert-to-alloc-api-v4-1-f04e698c9a77@bootlin.com>

This is the new API for allocating DRM bridges.

Converting this driver is a bit complex because the drm_bridge funcs
pointer differs based on the bridge mode. So the current code does:

 * tc_probe()
   * devm_kzalloc() private struct embedding drm_bridge
   * call tc_probe_bridge_endpoint() which
     * parses DT description into struct fields
     * computes the mode
     * calls different bridge init functions based on the mode
       * each sets a different bridge.funcs pointer

The new API expects the funcs pointer to be known at alloc time, which does
not fit in the current code structure.

Solve this by splitting tc_probe_bridge_endpoint() in two functions:

 * tc_probe_get_mode(), computing the mode without needing the private
   driver structure
 * tc_probe_bridge_endpoint(), only initializing the endpoints

So now the mode is known before allocation and so
is the funcs pointer, while all other operations are still happening after
allocation, directly into the private struct data, as they used to.

The new code flow is:

 * tc_probe()
   * tc_probe_get_mode()
     * parses DT description
     * computes and returns the mode
   * based onf the mode, pick the funcs pointer
   * devm_drm_bridfge_alloc(..., funcs)
   * call tc_probe_bridge_endpoint() which
     * calls different bridge init functions based on the mode
       * these don't set the funcs pointer, it was done by _alloc

This solution is chosen to minimize the changes in the driver logical code
flow. The drawback is we now iterate twice over the endpoints during probe.

Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
---
devm_drm_bridge_alloc() [0] is the new API to allocate and initialize a DRM
bridge, and the only one supported from now on. It is the first milestone
towards removal of bridges from a still existing DRM pipeline without
use-after-free.

The steps in the grand plan [1] are:

 1. ? add refcounting to DRM bridges (struct drm_bridge)
 2. handle gracefully atomic updates during bridge removal
 3. avoid DSI host drivers to have dangling pointers to DSI devices
 4. finish the hotplug bridge work, removing the "always-disconnected"
    connector, moving code to the core and potentially removing the
    hotplug-bridge itself (this needs to be clarified as points 1-3 are
    developed)

This series is part of step 1 of the grand plan.

Current tasks in step 1 of the grand plan:

 A. ? add new alloc API and refcounting -> (now in drm-misc-next)
 B. ? convert all bridge drivers to new API (this series)
 C. ? documentation, kunit tests (v1 under discussion)
 D. after (B), add get/put to drm_bridge_add/remove() + attach/detech()
 E. after (B), convert accessors; this is a large work and can be done
    in chunks
 F. debugfs improvements

More info about this series in the v2 cover [2].

Luca

[0] https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/0cc6aadd7fc1e629b715ea3d1ba537ef2da95eec
[1] https://lore.kernel.org/lkml/20250206-hotplug-drm-bridge-v6-0-9d6f2c9c3058 at bootlin.com/t/#u
[2] https://lore.kernel.org/lkml/20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b at bootlin.com/
---
Changes in v4:
- Removed patches already in drm-misc-next -> only 1 left
- Improve commit message of patch 1
- Link to v3: https://lore.kernel.org/all/20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa at bootlin.com/

Changes in v3:
- Fixed issues reported for some patches
- Added review tags
- Removed patches that have been applied
- Added revert for the exynos patch, applied by mistake
- Update cover with grand plan info and trim some of it
- Updated bouncing e-mail address in Cc list
- Link to v2: https://lore.kernel.org/lkml/20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b at bootlin.com/

Changes in v2:
- Improved cover letter with link to commit adding devm_drm_bridge_alloc()
- add review tags
- fix bugs in zynqmp, vc4 patches
- fix patch 1 error code checking
- Link to v1: https://lore.kernel.org/r/20250407-drm-bridge-convert-to-alloc-api-v1-0-42113ff8d9c0 at bootlin.com
---

changes in v4:
- improved commit message
---
 drivers/gpu/drm/bridge/tc358767.c | 56 ++++++++++++++++++++++++++++-----------
 1 file changed, 40 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 7e5449fb86a3fcdae8255bc490d12c543ef3f8ae..61559467e2d22b4b1b4223c97766ca3bf58908fd 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -344,6 +344,14 @@
 #define COLOR_BAR_MODE_BARS	2
 #define PLL_DBG			0x0a04
 
+enum tc_mode {
+	mode_dpi_to_edp = BIT(1) | BIT(2),
+	mode_dpi_to_dp  = BIT(1),
+	mode_dsi_to_edp = BIT(0) | BIT(2),
+	mode_dsi_to_dp  = BIT(0),
+	mode_dsi_to_dpi = BIT(0) | BIT(1),
+};
+
 static bool tc_test_pattern;
 module_param_named(test, tc_test_pattern, bool, 0644);
 
@@ -2327,7 +2335,6 @@ static int tc_probe_dpi_bridge_endpoint(struct tc_data *tc)
 	if (bridge) {
 		tc->panel_bridge = bridge;
 		tc->bridge.type = DRM_MODE_CONNECTOR_DPI;
-		tc->bridge.funcs = &tc_dpi_bridge_funcs;
 
 		return 0;
 	}
@@ -2360,7 +2367,6 @@ static int tc_probe_edp_bridge_endpoint(struct tc_data *tc)
 		tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
 	}
 
-	tc->bridge.funcs = &tc_edp_bridge_funcs;
 	if (tc->hpd_pin >= 0)
 		tc->bridge.ops |= DRM_BRIDGE_OP_DETECT;
 	tc->bridge.ops |= DRM_BRIDGE_OP_EDID;
@@ -2368,17 +2374,11 @@ static int tc_probe_edp_bridge_endpoint(struct tc_data *tc)
 	return 0;
 }
 
-static int tc_probe_bridge_endpoint(struct tc_data *tc)
+static enum tc_mode tc_probe_get_mode(struct device *dev)
 {
-	struct device *dev = tc->dev;
 	struct of_endpoint endpoint;
 	struct device_node *node = NULL;
-	const u8 mode_dpi_to_edp = BIT(1) | BIT(2);
-	const u8 mode_dpi_to_dp = BIT(1);
-	const u8 mode_dsi_to_edp = BIT(0) | BIT(2);
-	const u8 mode_dsi_to_dp = BIT(0);
-	const u8 mode_dsi_to_dpi = BIT(0) | BIT(1);
-	u8 mode = 0;
+	enum tc_mode mode = 0;
 
 	/*
 	 * Determine bridge configuration.
@@ -2401,7 +2401,27 @@ static int tc_probe_bridge_endpoint(struct tc_data *tc)
 			return -EINVAL;
 		}
 		mode |= BIT(endpoint.port);
+	}
+
+	if (mode != mode_dpi_to_edp &&
+	    mode != mode_dpi_to_dp  &&
+	    mode != mode_dsi_to_dpi &&
+	    mode != mode_dsi_to_edp &&
+	    mode != mode_dsi_to_dp) {
+		dev_warn(dev, "Invalid mode (0x%x) is not supported!\n", mode);
+		return -EINVAL;
+	}
+
+	return mode;
+}
 
+static int tc_probe_bridge_endpoint(struct tc_data *tc, enum tc_mode mode)
+{
+	struct device *dev = tc->dev;
+	struct of_endpoint endpoint;
+	struct device_node *node = NULL;
+
+	for_each_endpoint_of_node(dev->of_node, node) {
 		if (endpoint.port == 2) {
 			of_property_read_u8_array(node, "toshiba,pre-emphasis",
 						  tc->pre_emphasis,
@@ -2427,24 +2447,28 @@ static int tc_probe_bridge_endpoint(struct tc_data *tc)
 		return tc_probe_edp_bridge_endpoint(tc);
 	}
 
-	dev_warn(dev, "Invalid mode (0x%x) is not supported!\n", mode);
-
+	/* Should never happen, mode was validated by tc_probe_get_mode() */
 	return -EINVAL;
 }
 
 static int tc_probe(struct i2c_client *client)
 {
 	struct device *dev = &client->dev;
+	const struct drm_bridge_funcs *funcs;
 	struct tc_data *tc;
+	int mode;
 	int ret;
 
-	tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
-	if (!tc)
-		return -ENOMEM;
+	mode = tc_probe_get_mode(dev);
+	funcs = (mode == mode_dsi_to_dpi) ? &tc_dpi_bridge_funcs : &tc_edp_bridge_funcs;
+
+	tc = devm_drm_bridge_alloc(dev, struct tc_data, bridge, funcs);
+	if (IS_ERR(tc))
+		return PTR_ERR(tc);
 
 	tc->dev = dev;
 
-	ret = tc_probe_bridge_endpoint(tc);
+	ret = tc_probe_bridge_endpoint(tc, mode);
 	if (ret)
 		return ret;
 

---
base-commit: 18fb864d3afccf7ecdf13d0435464465d31ccf1d
change-id: 20250404-drm-bridge-convert-to-alloc-api-614becf62294

Best regards,
-- 
Luca Ceresoli <luca.ceresoli at bootlin.com>



From jianhua.lin at mediatek.com  Wed May 28 02:57:46 2025
From: jianhua.lin at mediatek.com (Jianhua Lin)
Date: Wed, 28 May 2025 17:57:46 +0800
Subject: [PATCH 0/2] Add MT8189 jpeg encoder and decoder compatible
Message-ID: <20250528095748.17485-1-jianhua.lin@mediatek.com>

This series is based on tag: next-20250528, linux-next/master

jianhua.lin (2):
  dt-bindings: media: mediatek-jpeg-encoder: Add MT8189 compatible
    string
  dt-bindings: media: mediatek-jpeg-decoder: Add MT8189 compatible
    string

 .../devicetree/bindings/media/mediatek-jpeg-decoder.yaml         | 1 +
 .../devicetree/bindings/media/mediatek-jpeg-encoder.yaml         | 1 +
 2 files changed, 2 insertions(+)

-- 
2.46.0



From jianhua.lin at mediatek.com  Wed May 28 02:57:47 2025
From: jianhua.lin at mediatek.com (Jianhua Lin)
Date: Wed, 28 May 2025 17:57:47 +0800
Subject: [PATCH 1/2] dt-bindings: media: mediatek-jpeg-encoder: Add MT8189 compatible string
In-Reply-To: <20250528095748.17485-1-jianhua.lin@mediatek.com>
References: <20250528095748.17485-1-jianhua.lin@mediatek.com>
Message-ID: <20250528095748.17485-2-jianhua.lin@mediatek.com>

Add compatible for MT8189 jpeg encoder.

Signed-off-by: Jianhua Lin <jianhua.lin at mediatek.com>
---
 .../devicetree/bindings/media/mediatek-jpeg-encoder.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
index 5b15f8977f67..1d6589468d10 100644
--- a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
@@ -20,6 +20,7 @@ properties:
           - mediatek,mt8183-jpgenc
           - mediatek,mt8186-jpgenc
           - mediatek,mt8188-jpgenc
+          - mediatek,mt8189-jpgenc
       - const: mediatek,mtk-jpgenc
   reg:
     maxItems: 1
-- 
2.46.0



From jianhua.lin at mediatek.com  Wed May 28 02:57:48 2025
From: jianhua.lin at mediatek.com (Jianhua Lin)
Date: Wed, 28 May 2025 17:57:48 +0800
Subject: [PATCH 2/2] dt-bindings: media: mediatek-jpeg-decoder: Add MT8189 compatible string
In-Reply-To: <20250528095748.17485-1-jianhua.lin@mediatek.com>
References: <20250528095748.17485-1-jianhua.lin@mediatek.com>
Message-ID: <20250528095748.17485-3-jianhua.lin@mediatek.com>

Add compatible for MT8189 jpeg decoder.

Signed-off-by: Jianhua Lin <jianhua.lin at mediatek.com>
---
 .../devicetree/bindings/media/mediatek-jpeg-decoder.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
index a4aacd3eb189..33e7a6e5a069 100644
--- a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
@@ -23,6 +23,7 @@ properties:
           - enum:
               - mediatek,mt7623-jpgdec
               - mediatek,mt8188-jpgdec
+              - mediatek,mt8189-jpgdec
           - const: mediatek,mt2701-jpgdec
 
   reg:
-- 
2.46.0



From krzysztof.kozlowski at linaro.org  Wed May 28 03:40:56 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:40:56 +0200
Subject: [PATCH 00/17] pinctrl: Constify pointers to 'pinctrl_desc' and
 more
Message-ID: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>

In several drivers pointers to 'struct pinctrl_desc' is not modified, so
since core does not modify it, it can be made as const.

Dependencies/merging:
Patch #4 "pinctrl: Constify pointers to 'pinctrl_desc'" is a
prerequisite for all further patches, including RTC patch, therefore
probably everything should be via main pinctrl tree.

I split several patches, although not all, per SoC-submaintainers, so
reviewing will be easier.

Best regards,
Krzysztof

---
Krzysztof Kozlowski (17):
      pinctrl: starfive: Allow compile testing on other platforms
      pinctrl: Allow compile testing for K210, TB10X and ZYNQ
      pinctrl: amd: Constify pointers to 'pinctrl_desc'
      pinctrl: Constify pointers to 'pinctrl_desc'
      pinctrl: aspeed: Constify static 'pinctrl_desc'
      pinctrl: nuvoton: Constify static 'pinctrl_desc'
      pinctrl: bcm: Constify static 'pinctrl_desc'
      pinctrl: bcm: cygnus-mux: Move fixed assignments to 'pinctrl_desc' definition
      pinctrl: bcm: cygnus-ns2: Move fixed assignments to 'pinctrl_desc' definition
      pinctrl: bcm: cygnus-nsp: Move fixed assignments to 'pinctrl_desc' definition
      pinctrl: as3722: Move fixed assignments to 'pinctrl_desc' definition
      pinctrl: max77620: Move fixed assignments to 'pinctrl_desc' definition
      pinctrl: palmas: Move fixed assignments to 'pinctrl_desc' definition
      pinctrl: renesas: Move fixed assignments to 'pinctrl_desc' definition
      pinctrl: pistachio: Constify static 'pinctrl_desc'
      pinctrl: Constify static 'pinctrl_desc'
      rtc: stm32: Constify static 'pinctrl_desc'

 drivers/pinctrl/Kconfig                            |  8 ++++----
 drivers/pinctrl/Makefile                           |  2 +-
 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c         |  2 +-
 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c         |  2 +-
 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c         |  2 +-
 drivers/pinctrl/aspeed/pinctrl-aspeed.c            |  2 +-
 drivers/pinctrl/aspeed/pinctrl-aspeed.h            |  2 +-
 drivers/pinctrl/bcm/pinctrl-bcm4908.c              |  2 +-
 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c           |  8 ++++----
 drivers/pinctrl/bcm/pinctrl-ns.c                   |  2 +-
 drivers/pinctrl/bcm/pinctrl-ns2-mux.c              |  8 ++++----
 drivers/pinctrl/bcm/pinctrl-nsp-mux.c              |  8 ++++----
 drivers/pinctrl/berlin/berlin.c                    |  2 +-
 drivers/pinctrl/cirrus/pinctrl-cs42l43.c           |  2 +-
 drivers/pinctrl/core.c                             | 13 +++++++------
 drivers/pinctrl/core.h                             |  2 +-
 drivers/pinctrl/mediatek/pinctrl-airoha.c          |  2 +-
 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c          |  2 +-
 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c          |  2 +-
 drivers/pinctrl/nuvoton/pinctrl-wpcm450.c          |  2 +-
 drivers/pinctrl/pinctrl-amd.c                      |  8 ++++----
 drivers/pinctrl/pinctrl-artpec6.c                  |  2 +-
 drivers/pinctrl/pinctrl-as3722.c                   |  4 ++--
 drivers/pinctrl/pinctrl-bm1880.c                   |  2 +-
 drivers/pinctrl/pinctrl-k210.c                     |  2 +-
 drivers/pinctrl/pinctrl-lpc18xx.c                  |  2 +-
 drivers/pinctrl/pinctrl-max77620.c                 |  9 ++++-----
 drivers/pinctrl/pinctrl-mlxbf3.c                   |  2 +-
 drivers/pinctrl/pinctrl-palmas.c                   |  4 ++--
 drivers/pinctrl/pinctrl-pistachio.c                |  8 ++++----
 drivers/pinctrl/pinctrl-tb10x.c                    |  2 +-
 drivers/pinctrl/pinctrl-zynq.c                     |  2 +-
 drivers/pinctrl/renesas/pinctrl-rzn1.c             |  4 ++--
 drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c |  2 +-
 drivers/rtc/rtc-stm32.c                            |  2 +-
 include/linux/pinctrl/pinctrl.h                    |  8 ++++----
 36 files changed, 69 insertions(+), 69 deletions(-)
---
base-commit: 08ea0cc455fbf6f6719b7a4cdcd1d132ea34577b
change-id: 20250528-pinctrl-const-desc-3a40e39eca15

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>



From krzysztof.kozlowski at linaro.org  Wed May 28 03:40:57 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:40:57 +0200
Subject: [PATCH 01/17] pinctrl: starfive: Allow compile testing on other
 platforms
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-1-76fe97899945@linaro.org>

Always descent to drivers/pinctrl/starfive/ because limiting it with
SOC_STARFIVE is redundant since all of its Kconfig entries are already
have "depends on SOC_STARFIVE".  This allows compile testing on other
architectures with allyesconfig.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/pinctrl/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index ac27e88677d14f1c697e0d0be9f295c746556f4d..dcede70b25660833a158c298d1269d6ecea9dd8b 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -82,7 +82,7 @@ obj-y				+= sophgo/
 obj-y				+= spacemit/
 obj-$(CONFIG_PINCTRL_SPEAR)	+= spear/
 obj-y				+= sprd/
-obj-$(CONFIG_SOC_STARFIVE)	+= starfive/
+obj-y				+= starfive/
 obj-$(CONFIG_PINCTRL_STM32)	+= stm32/
 obj-y				+= sunplus/
 obj-$(CONFIG_PINCTRL_SUNXI)	+= sunxi/

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:40:58 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:40:58 +0200
Subject: [PATCH 02/17] pinctrl: Allow compile testing for K210, TB10X and
 ZYNQ
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-2-76fe97899945@linaro.org>

Pinctrl drivers for K210, TB10X and ZYNQ do not reference any machine
headers, thus can be compile tested for increased build coverage.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/pinctrl/Kconfig | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 33db9104df178e5a3148b60c3c6bd153113385d3..77a5d13e899f8c5251987c2c74df1d05dbd59128 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -269,7 +269,7 @@ config PINCTRL_INGENIC
 
 config PINCTRL_K210
 	bool "Pinctrl driver for the Canaan Kendryte K210 SoC"
-	depends on RISCV && SOC_CANAAN_K210 && OF
+	depends on RISCV && SOC_CANAAN_K210 && OF || COMPILE_TEST
 	select GENERIC_PINMUX_FUNCTIONS
 	select GENERIC_PINCONF
 	select GPIOLIB
@@ -554,8 +554,8 @@ config PINCTRL_SX150X
 	  - 16 bits: sx1509q, sx1506q
 
 config PINCTRL_TB10X
-	bool
-	depends on OF && ARC_PLAT_TB10X
+	bool "Pinctrl for TB10X" if COMPILE_TEST
+	depends on OF && ARC_PLAT_TB10X || COMPILE_TEST
 	select GPIOLIB
 
 config PINCTRL_TPS6594
@@ -590,7 +590,7 @@ config PINCTRL_TH1520
 
 config PINCTRL_ZYNQ
 	bool "Pinctrl driver for Xilinx Zynq"
-	depends on ARCH_ZYNQ
+	depends on ARCH_ZYNQ || COMPILE_TEST
 	select PINMUX
 	select GENERIC_PINCONF
 	help

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:40:59 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:40:59 +0200
Subject: [PATCH 03/17] pinctrl: amd: Constify pointers to 'pinctrl_desc'
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-3-76fe97899945@linaro.org>

Internal functions obtaining pointers to 'struct pinctrl_desc' do not
modify the contents so they can be made pointers to const.  This makes
code safer, explicit and later allows constifying 'pinctrl_desc' in
pinctrl core code.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/pinctrl/pinctrl-amd.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 5cf3db6d78b79af9ac5e7226de239a0d2f9aaacc..85617cfed2299e131c110e9d4084370790106404 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -872,7 +872,7 @@ static const struct pinconf_ops amd_pinconf_ops = {
 
 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
 {
-	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
+	const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
 	unsigned long flags;
 	u32 pin_reg, mask;
 	int i;
@@ -901,7 +901,7 @@ static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
 static void amd_gpio_check_pending(void)
 {
 	struct amd_gpio *gpio_dev = pinctrl_dev;
-	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
+	const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
 	int i;
 
 	if (!pm_debug_messages_on)
@@ -957,7 +957,7 @@ static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
 static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend)
 {
 	struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
-	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
+	const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
 	unsigned long flags;
 	int i;
 	u32 wake_mask = is_suspend ? WAKE_SOURCE_SUSPEND : WAKE_SOURCE_HIBERNATE;
@@ -1001,7 +1001,7 @@ static int amd_gpio_hibernate(struct device *dev)
 static int amd_gpio_resume(struct device *dev)
 {
 	struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
-	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
+	const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
 	unsigned long flags;
 	int i;
 

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:41:00 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:41:00 +0200
Subject: [PATCH 04/17] pinctrl: Constify pointers to 'pinctrl_desc'
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-4-76fe97899945@linaro.org>

Pin controller core code only stores the pointer to
'struct pinctrl_desc' and does not modify it anywhere.  The pointer can
be changed to pointer to const which makes the code safer, explicit and
later allows constifying 'pinctrl_desc' allocations in individual
drivers.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

---

This is the pre-requisite patch for all further patches.
---
 drivers/pinctrl/core.c          | 13 +++++++------
 drivers/pinctrl/core.h          |  2 +-
 include/linux/pinctrl/pinctrl.h |  8 ++++----
 3 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 9046292d1360218bc70eff418fb8d1028c22b11a..73b78d6eac672095c8556763af1744be6f558501 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -2062,7 +2062,7 @@ static int pinctrl_check_ops(struct pinctrl_dev *pctldev)
  * @driver_data: private pin controller data for this pin controller
  */
 static struct pinctrl_dev *
-pinctrl_init_controller(struct pinctrl_desc *pctldesc, struct device *dev,
+pinctrl_init_controller(const struct pinctrl_desc *pctldesc, struct device *dev,
 			void *driver_data)
 {
 	struct pinctrl_dev *pctldev;
@@ -2132,7 +2132,8 @@ pinctrl_init_controller(struct pinctrl_desc *pctldesc, struct device *dev,
 	return ERR_PTR(ret);
 }
 
-static void pinctrl_uninit_controller(struct pinctrl_dev *pctldev, struct pinctrl_desc *pctldesc)
+static void pinctrl_uninit_controller(struct pinctrl_dev *pctldev,
+				      const struct pinctrl_desc *pctldesc)
 {
 	pinctrl_free_pindescs(pctldev, pctldesc->pins,
 			      pctldesc->npins);
@@ -2209,7 +2210,7 @@ EXPORT_SYMBOL_GPL(pinctrl_enable);
  * struct pinctrl_dev handle. To avoid issues later on, please use the
  * new pinctrl_register_and_init() below instead.
  */
-struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
+struct pinctrl_dev *pinctrl_register(const struct pinctrl_desc *pctldesc,
 				    struct device *dev, void *driver_data)
 {
 	struct pinctrl_dev *pctldev;
@@ -2239,7 +2240,7 @@ EXPORT_SYMBOL_GPL(pinctrl_register);
  * Note that pinctrl_enable() still needs to be manually called after
  * this once the driver is ready.
  */
-int pinctrl_register_and_init(struct pinctrl_desc *pctldesc,
+int pinctrl_register_and_init(const struct pinctrl_desc *pctldesc,
 			      struct device *dev, void *driver_data,
 			      struct pinctrl_dev **pctldev)
 {
@@ -2330,7 +2331,7 @@ static int devm_pinctrl_dev_match(struct device *dev, void *res, void *data)
  * The pinctrl device will be automatically released when the device is unbound.
  */
 struct pinctrl_dev *devm_pinctrl_register(struct device *dev,
-					  struct pinctrl_desc *pctldesc,
+					  const struct pinctrl_desc *pctldesc,
 					  void *driver_data)
 {
 	struct pinctrl_dev **ptr, *pctldev;
@@ -2364,7 +2365,7 @@ EXPORT_SYMBOL_GPL(devm_pinctrl_register);
  * The pinctrl device will be automatically released when the device is unbound.
  */
 int devm_pinctrl_register_and_init(struct device *dev,
-				   struct pinctrl_desc *pctldesc,
+				   const struct pinctrl_desc *pctldesc,
 				   void *driver_data,
 				   struct pinctrl_dev **pctldev)
 {
diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index d6c24978e7081a663b8a0fa6cb9314670575b1bc..fc513a9cdd4f2f9dd4ec4a088eee53fdbd673285 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -51,7 +51,7 @@ struct pinctrl_state;
  */
 struct pinctrl_dev {
 	struct list_head node;
-	struct pinctrl_desc *desc;
+	const struct pinctrl_desc *desc;
 	struct radix_tree_root pin_desc_tree;
 #ifdef CONFIG_GENERIC_PINCTRL_GROUPS
 	struct radix_tree_root pin_group_tree;
diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h
index 9a8189ffd0f2c28c88640280deee194d17d18400..d138e18156452e008f24ca06358fcab45135632f 100644
--- a/include/linux/pinctrl/pinctrl.h
+++ b/include/linux/pinctrl/pinctrl.h
@@ -165,25 +165,25 @@ struct pinctrl_desc {
 
 /* External interface to pin controller */
 
-extern int pinctrl_register_and_init(struct pinctrl_desc *pctldesc,
+extern int pinctrl_register_and_init(const struct pinctrl_desc *pctldesc,
 				     struct device *dev, void *driver_data,
 				     struct pinctrl_dev **pctldev);
 extern int pinctrl_enable(struct pinctrl_dev *pctldev);
 
 /* Please use pinctrl_register_and_init() and pinctrl_enable() instead */
-extern struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
+extern struct pinctrl_dev *pinctrl_register(const struct pinctrl_desc *pctldesc,
 				struct device *dev, void *driver_data);
 
 extern void pinctrl_unregister(struct pinctrl_dev *pctldev);
 
 extern int devm_pinctrl_register_and_init(struct device *dev,
-				struct pinctrl_desc *pctldesc,
+				const struct pinctrl_desc *pctldesc,
 				void *driver_data,
 				struct pinctrl_dev **pctldev);
 
 /* Please use devm_pinctrl_register_and_init() instead */
 extern struct pinctrl_dev *devm_pinctrl_register(struct device *dev,
-				struct pinctrl_desc *pctldesc,
+				const struct pinctrl_desc *pctldesc,
 				void *driver_data);
 
 extern void devm_pinctrl_unregister(struct device *dev,

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:41:01 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:41:01 +0200
Subject: [PATCH 05/17] pinctrl: aspeed: Constify static 'pinctrl_desc'
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-5-76fe97899945@linaro.org>

The local static 'struct pinctrl_desc' is not modified, so can be made
const for code safety.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 2 +-
 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 2 +-
 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 2 +-
 drivers/pinctrl/aspeed/pinctrl-aspeed.c    | 2 +-
 drivers/pinctrl/aspeed/pinctrl-aspeed.h    | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
index 774f8d05142f2d90c238f8e6661eca4685601db7..cb295856dda1244f2205305cf4c505d4ea4a326f 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
@@ -2653,7 +2653,7 @@ static const struct pinconf_ops aspeed_g4_conf_ops = {
 	.pin_config_group_set = aspeed_pin_config_group_set,
 };
 
-static struct pinctrl_desc aspeed_g4_pinctrl_desc = {
+static const struct pinctrl_desc aspeed_g4_pinctrl_desc = {
 	.name = "aspeed-g4-pinctrl",
 	.pins = aspeed_g4_pins,
 	.npins = ARRAY_SIZE(aspeed_g4_pins),
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index 5bb8fd0d1e41bda799119a67887ccbc277e0f9f4..792089628362a1ed1c3eccd4e46c41a3ac7a79f6 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -2845,7 +2845,7 @@ static const struct pinconf_ops aspeed_g5_conf_ops = {
 	.pin_config_group_set = aspeed_pin_config_group_set,
 };
 
-static struct pinctrl_desc aspeed_g5_pinctrl_desc = {
+static const struct pinctrl_desc aspeed_g5_pinctrl_desc = {
 	.name = "aspeed-g5-pinctrl",
 	.pins = aspeed_g5_pins,
 	.npins = ARRAY_SIZE(aspeed_g5_pins),
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
index 5a7cd0a8868764dc5e3dc70f325c25ba29d50a64..51a63cf92023f7dc7a27466331c77bb5dcbaa9bb 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
@@ -2763,7 +2763,7 @@ static const struct pinconf_ops aspeed_g6_conf_ops = {
 	.pin_config_group_set = aspeed_pin_config_group_set,
 };
 
-static struct pinctrl_desc aspeed_g6_pinctrl_desc = {
+static const struct pinctrl_desc aspeed_g6_pinctrl_desc = {
 	.name = "aspeed-g6-pinctrl",
 	.pins = aspeed_g6_pins,
 	.npins = ARRAY_SIZE(aspeed_g6_pins),
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
index 9c6ee46ac7a096ce693639d88d387b089ffe5239..7e0ebf11af163c90184231686b1e0d9920755d76 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
@@ -441,7 +441,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
 }
 
 int aspeed_pinctrl_probe(struct platform_device *pdev,
-			 struct pinctrl_desc *pdesc,
+			 const struct pinctrl_desc *pdesc,
 			 struct aspeed_pinctrl_data *pdata)
 {
 	struct device *parent;
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
index 4dcde3bc29c825cbc6be954dae9a654a310b4cd8..28f3bde25081b2c8099977129acdcdfb3e4b1dd5 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
@@ -102,7 +102,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
 		struct pinctrl_gpio_range *range,
 		unsigned int offset);
 int aspeed_pinctrl_probe(struct platform_device *pdev,
-		struct pinctrl_desc *pdesc,
+		const struct pinctrl_desc *pdesc,
 		struct aspeed_pinctrl_data *pdata);
 int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset,
 		unsigned long *config);

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:41:02 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:41:02 +0200
Subject: [PATCH 06/17] pinctrl: nuvoton: Constify static 'pinctrl_desc'
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-6-76fe97899945@linaro.org>

The local static 'struct pinctrl_desc' is not modified, so can be made
const for code safety.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2 +-
 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 2 +-
 drivers/pinctrl/nuvoton/pinctrl-wpcm450.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
index dfd32feb34286b7a4d807e9033a11f507e277dce..b8872d8f5930ad931dad208afec4e08a23c3d653 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
@@ -1817,7 +1817,7 @@ static const struct pinconf_ops npcm7xx_pinconf_ops = {
 };
 
 /* pinctrl_desc */
-static struct pinctrl_desc npcm7xx_pinctrl_desc = {
+static const struct pinctrl_desc npcm7xx_pinctrl_desc = {
 	.name = "npcm7xx-pinctrl",
 	.pins = npcm7xx_pins,
 	.npins = ARRAY_SIZE(npcm7xx_pins),
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
index be3db8ab406c416f0709d06eb864e33e3208541a..3c3b9d8d3681c64c21927615e1bb49f157f156b5 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -2299,7 +2299,7 @@ static const struct pinconf_ops npcm8xx_pinconf_ops = {
 };
 
 /* pinctrl_desc */
-static struct pinctrl_desc npcm8xx_pinctrl_desc = {
+static const struct pinctrl_desc npcm8xx_pinctrl_desc = {
 	.name = "npcm8xx-pinctrl",
 	.pins = npcm8xx_pins,
 	.npins = ARRAY_SIZE(npcm8xx_pins),
diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
index 4264ca749175a2ce0f3603c1d7aa271d98e6cd89..8d8314ba0e4cb55db2b1d3adf2de07e6fb93c279 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
@@ -989,7 +989,7 @@ static const struct pinconf_ops wpcm450_pinconf_ops = {
 	.pin_config_set = wpcm450_config_set,
 };
 
-static struct pinctrl_desc wpcm450_pinctrl_desc = {
+static const struct pinctrl_desc wpcm450_pinctrl_desc = {
 	.name = "wpcm450-pinctrl",
 	.pins = wpcm450_pins,
 	.npins = ARRAY_SIZE(wpcm450_pins),

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:41:03 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:41:03 +0200
Subject: [PATCH 07/17] pinctrl: bcm: Constify static 'pinctrl_desc'
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-7-76fe97899945@linaro.org>

The local static 'struct pinctrl_desc' is not modified, so can be made
const for code safety.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/pinctrl/bcm/pinctrl-bcm4908.c | 2 +-
 drivers/pinctrl/bcm/pinctrl-ns.c      | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/bcm/pinctrl-bcm4908.c b/drivers/pinctrl/bcm/pinctrl-bcm4908.c
index f190e0997f1fa9fe8bf07fc3ae5700bc721e1651..12f7a253ea4d5bd0af5dbabc320fc2df32172e4f 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm4908.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm4908.c
@@ -456,7 +456,7 @@ static const struct pinmux_ops bcm4908_pinctrl_pmxops = {
  * Controller code
  */
 
-static struct pinctrl_desc bcm4908_pinctrl_desc = {
+static const struct pinctrl_desc bcm4908_pinctrl_desc = {
 	.name = "bcm4908-pinctrl",
 	.pctlops = &bcm4908_pinctrl_ops,
 	.pmxops = &bcm4908_pinctrl_pmxops,
diff --git a/drivers/pinctrl/bcm/pinctrl-ns.c b/drivers/pinctrl/bcm/pinctrl-ns.c
index 6bb2b461950bef5c420f1b250d48fcf6e907b98f..03bd01b4a945adf72445576a8a111f3c0637e095 100644
--- a/drivers/pinctrl/bcm/pinctrl-ns.c
+++ b/drivers/pinctrl/bcm/pinctrl-ns.c
@@ -192,7 +192,7 @@ static const struct pinmux_ops ns_pinctrl_pmxops = {
  * Controller code
  */
 
-static struct pinctrl_desc ns_pinctrl_desc = {
+static const struct pinctrl_desc ns_pinctrl_desc = {
 	.name = "pinctrl-ns",
 	.pctlops = &ns_pinctrl_ops,
 	.pmxops = &ns_pinctrl_pmxops,

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:41:04 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:41:04 +0200
Subject: [PATCH 08/17] pinctrl: bcm: cygnus-mux: Move fixed assignments to
 'pinctrl_desc' definition
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-8-76fe97899945@linaro.org>

Assign 'struct pinctrl_desc' .npins member in definition to make clear
that number of pins is fixed and have less code in the probe.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
index bf9597800954affd954e45a4baa01da4d5dbf420..e9aa99f85e05944a2a0cb9a3e6245c707dbc9b3a 100644
--- a/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
+++ b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
@@ -903,6 +903,7 @@ static struct pinctrl_desc cygnus_pinctrl_desc = {
 	.name = "cygnus-pinmux",
 	.pctlops = &cygnus_pinctrl_ops,
 	.pmxops = &cygnus_pinmux_ops,
+	.npins = ARRAY_SIZE(cygnus_pins),
 };
 
 static int cygnus_mux_log_init(struct cygnus_pinctrl *pinctrl)
@@ -935,7 +936,6 @@ static int cygnus_pinmux_probe(struct platform_device *pdev)
 	struct cygnus_pinctrl *pinctrl;
 	int i, ret;
 	struct pinctrl_pin_desc *pins;
-	unsigned num_pins = ARRAY_SIZE(cygnus_pins);
 
 	pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
 	if (!pinctrl)
@@ -963,11 +963,12 @@ static int cygnus_pinmux_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
+	pins = devm_kcalloc(&pdev->dev, ARRAY_SIZE(cygnus_pins), sizeof(*pins),
+			    GFP_KERNEL);
 	if (!pins)
 		return -ENOMEM;
 
-	for (i = 0; i < num_pins; i++) {
+	for (i = 0; i < ARRAY_SIZE(cygnus_pins); i++) {
 		pins[i].number = cygnus_pins[i].pin;
 		pins[i].name = cygnus_pins[i].name;
 		pins[i].drv_data = &cygnus_pins[i].gpio_mux;
@@ -978,7 +979,6 @@ static int cygnus_pinmux_probe(struct platform_device *pdev)
 	pinctrl->functions = cygnus_pin_functions;
 	pinctrl->num_functions = ARRAY_SIZE(cygnus_pin_functions);
 	cygnus_pinctrl_desc.pins = pins;
-	cygnus_pinctrl_desc.npins = num_pins;
 
 	pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &cygnus_pinctrl_desc,
 			pinctrl);

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:41:05 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:41:05 +0200
Subject: [PATCH 09/17] pinctrl: bcm: cygnus-ns2: Move fixed assignments to
 'pinctrl_desc' definition
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-9-76fe97899945@linaro.org>

Assign 'struct pinctrl_desc' .npins member in definition to make clear
that number of pins is fixed and have less code in the probe.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/pinctrl/bcm/pinctrl-ns2-mux.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/bcm/pinctrl-ns2-mux.c b/drivers/pinctrl/bcm/pinctrl-ns2-mux.c
index 04f4fca854cc05c6ccc75fbcb640b18fcfd37453..23ab3ab064b6f2b0aaa15afd6b9c582f1a1256b2 100644
--- a/drivers/pinctrl/bcm/pinctrl-ns2-mux.c
+++ b/drivers/pinctrl/bcm/pinctrl-ns2-mux.c
@@ -971,6 +971,7 @@ static struct pinctrl_desc ns2_pinctrl_desc = {
 	.pctlops = &ns2_pinctrl_ops,
 	.pmxops = &ns2_pinmux_ops,
 	.confops = &ns2_pinconf_ops,
+	.npins = ARRAY_SIZE(ns2_pins),
 };
 
 static int ns2_mux_log_init(struct ns2_pinctrl *pinctrl)
@@ -1026,7 +1027,6 @@ static int ns2_pinmux_probe(struct platform_device *pdev)
 	struct resource *res;
 	int i, ret;
 	struct pinctrl_pin_desc *pins;
-	unsigned int num_pins = ARRAY_SIZE(ns2_pins);
 
 	pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
 	if (!pinctrl)
@@ -1060,11 +1060,12 @@ static int ns2_pinmux_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
+	pins = devm_kcalloc(&pdev->dev, ARRAY_SIZE(ns2_pins), sizeof(*pins),
+			    GFP_KERNEL);
 	if (!pins)
 		return -ENOMEM;
 
-	for (i = 0; i < num_pins; i++) {
+	for (i = 0; i < ARRAY_SIZE(ns2_pins); i++) {
 		pins[i].number = ns2_pins[i].pin;
 		pins[i].name = ns2_pins[i].name;
 		pins[i].drv_data = &ns2_pins[i];
@@ -1075,7 +1076,6 @@ static int ns2_pinmux_probe(struct platform_device *pdev)
 	pinctrl->functions = ns2_pin_functions;
 	pinctrl->num_functions = ARRAY_SIZE(ns2_pin_functions);
 	ns2_pinctrl_desc.pins = pins;
-	ns2_pinctrl_desc.npins = num_pins;
 
 	pinctrl->pctl = pinctrl_register(&ns2_pinctrl_desc, &pdev->dev,
 			pinctrl);

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:41:06 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:41:06 +0200
Subject: [PATCH 10/17] pinctrl: bcm: cygnus-nsp: Move fixed assignments to
 'pinctrl_desc' definition
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-10-76fe97899945@linaro.org>

Assign 'struct pinctrl_desc' .npins member in definition to make clear
that number of pins is fixed and have less code in the probe.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/pinctrl/bcm/pinctrl-nsp-mux.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-mux.c b/drivers/pinctrl/bcm/pinctrl-nsp-mux.c
index eb6298507c1d1873f9d5a90ec724b36af6d4da48..9b716c0d2b9456b9e64ca1094375effefdf4817c 100644
--- a/drivers/pinctrl/bcm/pinctrl-nsp-mux.c
+++ b/drivers/pinctrl/bcm/pinctrl-nsp-mux.c
@@ -525,6 +525,7 @@ static struct pinctrl_desc nsp_pinctrl_desc = {
 	.name = "nsp-pinmux",
 	.pctlops = &nsp_pinctrl_ops,
 	.pmxops = &nsp_pinmux_ops,
+	.npins = ARRAY_SIZE(nsp_pins),
 };
 
 static int nsp_mux_log_init(struct nsp_pinctrl *pinctrl)
@@ -556,7 +557,6 @@ static int nsp_pinmux_probe(struct platform_device *pdev)
 	struct resource *res;
 	int i, ret;
 	struct pinctrl_pin_desc *pins;
-	unsigned int num_pins = ARRAY_SIZE(nsp_pins);
 
 	pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
 	if (!pinctrl)
@@ -589,11 +589,12 @@ static int nsp_pinmux_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
+	pins = devm_kcalloc(&pdev->dev, ARRAY_SIZE(nsp_pins), sizeof(*pins),
+			    GFP_KERNEL);
 	if (!pins)
 		return -ENOMEM;
 
-	for (i = 0; i < num_pins; i++) {
+	for (i = 0; i < ARRAY_SIZE(nsp_pins); i++) {
 		pins[i].number = nsp_pins[i].pin;
 		pins[i].name = nsp_pins[i].name;
 		pins[i].drv_data = &nsp_pins[i].gpio_select;
@@ -604,7 +605,6 @@ static int nsp_pinmux_probe(struct platform_device *pdev)
 	pinctrl->functions = nsp_pin_functions;
 	pinctrl->num_functions = ARRAY_SIZE(nsp_pin_functions);
 	nsp_pinctrl_desc.pins = pins;
-	nsp_pinctrl_desc.npins = num_pins;
 
 	pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &nsp_pinctrl_desc,
 					 pinctrl);

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:41:07 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:41:07 +0200
Subject: [PATCH 11/17] pinctrl: as3722: Move fixed assignments to
 'pinctrl_desc' definition
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-11-76fe97899945@linaro.org>

Assign 'struct pinctrl_desc' .pins and .npins members in definition to
make clear that number of pins is fixed and have less code in the probe.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/pinctrl/pinctrl-as3722.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c
index 0d8c75ce20eda97627aef773342a0b63ff6114a1..ed7b2c482ff0bb6a546955c083ef7046701527b0 100644
--- a/drivers/pinctrl/pinctrl-as3722.c
+++ b/drivers/pinctrl/pinctrl-as3722.c
@@ -422,6 +422,8 @@ static struct pinctrl_desc as3722_pinctrl_desc = {
 	.pmxops = &as3722_pinmux_ops,
 	.confops = &as3722_pinconf_ops,
 	.owner = THIS_MODULE,
+	.pins = as3722_pins_desc,
+	.npins = ARRAY_SIZE(as3722_pins_desc),
 };
 
 static int as3722_gpio_get(struct gpio_chip *chip, unsigned offset)
@@ -550,8 +552,6 @@ static int as3722_pinctrl_probe(struct platform_device *pdev)
 	as_pci->pin_groups = as3722_pingroups;
 	as_pci->num_pin_groups = ARRAY_SIZE(as3722_pingroups);
 	as3722_pinctrl_desc.name = dev_name(&pdev->dev);
-	as3722_pinctrl_desc.pins = as3722_pins_desc;
-	as3722_pinctrl_desc.npins = ARRAY_SIZE(as3722_pins_desc);
 	as_pci->pctl = devm_pinctrl_register(&pdev->dev, &as3722_pinctrl_desc,
 					     as_pci);
 	if (IS_ERR(as_pci->pctl)) {

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:41:08 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:41:08 +0200
Subject: [PATCH 12/17] pinctrl: max77620: Move fixed assignments to
 'pinctrl_desc' definition
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-12-76fe97899945@linaro.org>

Assign 'struct pinctrl_desc' .pins, .npins and other members in
definition to make clear that number of pins is fixed and have less code
in the probe.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/pinctrl/pinctrl-max77620.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-max77620.c b/drivers/pinctrl/pinctrl-max77620.c
index d236daa7c13ebbcaf7c4a8d1a8bed751aa111c0f..acb945a2574368b2e34659a902c34df8aad193d7 100644
--- a/drivers/pinctrl/pinctrl-max77620.c
+++ b/drivers/pinctrl/pinctrl-max77620.c
@@ -543,6 +543,10 @@ static struct pinctrl_desc max77620_pinctrl_desc = {
 	.pctlops = &max77620_pinctrl_ops,
 	.pmxops = &max77620_pinmux_ops,
 	.confops = &max77620_pinconf_ops,
+	.pins = max77620_pins_desc,
+	.npins = ARRAY_SIZE(max77620_pins_desc),
+	.num_custom_params = ARRAY_SIZE(max77620_cfg_params),
+	.custom_params = max77620_cfg_params,
 };
 
 static int max77620_pinctrl_probe(struct platform_device *pdev)
@@ -569,11 +573,6 @@ static int max77620_pinctrl_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, mpci);
 
 	max77620_pinctrl_desc.name = dev_name(&pdev->dev);
-	max77620_pinctrl_desc.pins = max77620_pins_desc;
-	max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
-	max77620_pinctrl_desc.num_custom_params =
-				ARRAY_SIZE(max77620_cfg_params);
-	max77620_pinctrl_desc.custom_params = max77620_cfg_params;
 
 	for (i = 0; i < MAX77620_PIN_NUM; ++i) {
 		mpci->fps_config[i].active_fps_src = -1;

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:41:09 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:41:09 +0200
Subject: [PATCH 13/17] pinctrl: palmas: Move fixed assignments to
 'pinctrl_desc' definition
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-13-76fe97899945@linaro.org>

Assign 'struct pinctrl_desc' .pins and .npins members in definition to
make clear that number of pins is fixed and have less code in the probe.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/pinctrl/pinctrl-palmas.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c
index 9e272f9deb4f8c49f91d2f09c2c100018a7617f8..d69f114e46426c345d9ffe7567a326eecdd91bb5 100644
--- a/drivers/pinctrl/pinctrl-palmas.c
+++ b/drivers/pinctrl/pinctrl-palmas.c
@@ -956,6 +956,8 @@ static struct pinctrl_desc palmas_pinctrl_desc = {
 	.pmxops = &palmas_pinmux_ops,
 	.confops = &palmas_pinconf_ops,
 	.owner = THIS_MODULE,
+	.pins = palmas_pins_desc,
+	.npins = ARRAY_SIZE(palmas_pins_desc),
 };
 
 struct palmas_pinctrl_data {
@@ -1023,8 +1025,6 @@ static int palmas_pinctrl_probe(struct platform_device *pdev)
 	}
 
 	palmas_pinctrl_desc.name = dev_name(&pdev->dev);
-	palmas_pinctrl_desc.pins = palmas_pins_desc;
-	palmas_pinctrl_desc.npins = ARRAY_SIZE(palmas_pins_desc);
 	pci->pctl = devm_pinctrl_register(&pdev->dev, &palmas_pinctrl_desc,
 					  pci);
 	if (IS_ERR(pci->pctl)) {

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:41:10 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:41:10 +0200
Subject: [PATCH 14/17] pinctrl: renesas: Move fixed assignments to
 'pinctrl_desc' definition
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-14-76fe97899945@linaro.org>

Assign 'struct pinctrl_desc' .pins and .npins members in definition to
make clear that number of pins is fixed and have less code in the probe.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/pinctrl/renesas/pinctrl-rzn1.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzn1.c b/drivers/pinctrl/renesas/pinctrl-rzn1.c
index d442d4f9981c908389407275522b936dbce294d3..fb874867dbfb9877b012988543ecbfd1bfb11270 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzn1.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzn1.c
@@ -680,6 +680,8 @@ static struct pinctrl_desc rzn1_pinctrl_desc = {
 	.pmxops = &rzn1_pmx_ops,
 	.confops = &rzn1_pinconf_ops,
 	.owner = THIS_MODULE,
+	.pins = rzn1_pins,
+	.npins = ARRAY_SIZE(rzn1_pins),
 };
 
 static int rzn1_pinctrl_parse_groups(struct device_node *np,
@@ -878,8 +880,6 @@ static int rzn1_pinctrl_probe(struct platform_device *pdev)
 
 	ipctl->dev = &pdev->dev;
 	rzn1_pinctrl_desc.name = dev_name(&pdev->dev);
-	rzn1_pinctrl_desc.pins = rzn1_pins;
-	rzn1_pinctrl_desc.npins = ARRAY_SIZE(rzn1_pins);
 
 	ret = rzn1_pinctrl_probe_dt(pdev, ipctl);
 	if (ret) {

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:41:11 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:41:11 +0200
Subject: [PATCH 15/17] pinctrl: pistachio: Constify static 'pinctrl_desc'
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-15-76fe97899945@linaro.org>

The local static 'struct pinctrl_desc' is not modified, so can be made
const for code safety after moving .pins and .npins assignment to
definition.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/pinctrl/pinctrl-pistachio.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-pistachio.c b/drivers/pinctrl/pinctrl-pistachio.c
index e7bf609609617d6af2f10a3df56c62e3bfe2dcd3..7f8b562c81c9cfd1ac3a0bd50018857450bdf609 100644
--- a/drivers/pinctrl/pinctrl-pistachio.c
+++ b/drivers/pinctrl/pinctrl-pistachio.c
@@ -1156,11 +1156,14 @@ static const struct pinconf_ops pistachio_pinconf_ops = {
 	.is_generic = true,
 };
 
-static struct pinctrl_desc pistachio_pinctrl_desc = {
+static const struct pinctrl_desc pistachio_pinctrl_desc = {
 	.name = "pistachio-pinctrl",
 	.pctlops = &pistachio_pinctrl_ops,
 	.pmxops = &pistachio_pinmux_ops,
 	.confops = &pistachio_pinconf_ops,
+	.pins = pistachio_pins,
+	.npins = ARRAY_SIZE(pistachio_pins),
+
 };
 
 static int pistachio_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
@@ -1474,9 +1477,6 @@ static int pistachio_pinctrl_probe(struct platform_device *pdev)
 	pctl->gpio_banks = pistachio_gpio_banks;
 	pctl->nbanks = ARRAY_SIZE(pistachio_gpio_banks);
 
-	pistachio_pinctrl_desc.pins = pctl->pins;
-	pistachio_pinctrl_desc.npins = pctl->npins;
-
 	pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pistachio_pinctrl_desc,
 					      pctl);
 	if (IS_ERR(pctl->pctldev)) {

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:41:12 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:41:12 +0200
Subject: [PATCH 16/17] pinctrl: Constify static 'pinctrl_desc'
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-16-76fe97899945@linaro.org>

The local static 'struct pinctrl_desc' is not modified, so can be made
const for code safety.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 drivers/pinctrl/berlin/berlin.c                    | 2 +-
 drivers/pinctrl/cirrus/pinctrl-cs42l43.c           | 2 +-
 drivers/pinctrl/mediatek/pinctrl-airoha.c          | 2 +-
 drivers/pinctrl/pinctrl-artpec6.c                  | 2 +-
 drivers/pinctrl/pinctrl-bm1880.c                   | 2 +-
 drivers/pinctrl/pinctrl-k210.c                     | 2 +-
 drivers/pinctrl/pinctrl-lpc18xx.c                  | 2 +-
 drivers/pinctrl/pinctrl-mlxbf3.c                   | 2 +-
 drivers/pinctrl/pinctrl-tb10x.c                    | 2 +-
 drivers/pinctrl/pinctrl-zynq.c                     | 2 +-
 drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c | 2 +-
 11 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c
index c372a2a24be4bb80b1f2475ef8512171c8e1326f..e5a35b803ce66d247c5e5ad78e6677570a1add60 100644
--- a/drivers/pinctrl/berlin/berlin.c
+++ b/drivers/pinctrl/berlin/berlin.c
@@ -283,7 +283,7 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
 	return 0;
 }
 
-static struct pinctrl_desc berlin_pctrl_desc = {
+static const struct pinctrl_desc berlin_pctrl_desc = {
 	.name		= "berlin-pinctrl",
 	.pctlops	= &berlin_pinctrl_ops,
 	.pmxops		= &berlin_pinmux_ops,
diff --git a/drivers/pinctrl/cirrus/pinctrl-cs42l43.c b/drivers/pinctrl/cirrus/pinctrl-cs42l43.c
index 628b60ccc2b07dc77e36da8919436fa348749e0c..a90beb986f5bb707c54552e1333802943a4b04bc 100644
--- a/drivers/pinctrl/cirrus/pinctrl-cs42l43.c
+++ b/drivers/pinctrl/cirrus/pinctrl-cs42l43.c
@@ -448,7 +448,7 @@ static const struct pinconf_ops cs42l43_pin_conf_ops = {
 	.pin_config_group_set	= cs42l43_pin_config_group_set,
 };
 
-static struct pinctrl_desc cs42l43_pin_desc = {
+static const struct pinctrl_desc cs42l43_pin_desc = {
 	.name		= "cs42l43-pinctrl",
 	.owner		= THIS_MODULE,
 
diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
index b97b28ebb37a6ec092360f8ea404dd67e6c43eac..ccd2b512e8365b3a5af0bb223329f39119bc7078 100644
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
@@ -2852,7 +2852,7 @@ static const struct pinctrl_ops airoha_pctlops = {
 	.dt_free_map = pinconf_generic_dt_free_map,
 };
 
-static struct pinctrl_desc airoha_pinctrl_desc = {
+static const struct pinctrl_desc airoha_pinctrl_desc = {
 	.name = KBUILD_MODNAME,
 	.owner = THIS_MODULE,
 	.pctlops = &airoha_pctlops,
diff --git a/drivers/pinctrl/pinctrl-artpec6.c b/drivers/pinctrl/pinctrl-artpec6.c
index 717f9592b28b51737e67aafc93664b1345511908..af67057128ff1e9e766b958fece9c71518c89081 100644
--- a/drivers/pinctrl/pinctrl-artpec6.c
+++ b/drivers/pinctrl/pinctrl-artpec6.c
@@ -907,7 +907,7 @@ static const struct pinconf_ops artpec6_pconf_ops = {
 	.pin_config_group_set	= artpec6_pconf_group_set,
 };
 
-static struct pinctrl_desc artpec6_desc = {
+static const struct pinctrl_desc artpec6_desc = {
 	.name	 = "artpec6-pinctrl",
 	.owner	 = THIS_MODULE,
 	.pins	 = artpec6_pins,
diff --git a/drivers/pinctrl/pinctrl-bm1880.c b/drivers/pinctrl/pinctrl-bm1880.c
index b0000fe5b31dfbcd6af6eaf0c01029f00cbd205b..387798fb09be51cabd5cb76e0d90a28b1d363050 100644
--- a/drivers/pinctrl/pinctrl-bm1880.c
+++ b/drivers/pinctrl/pinctrl-bm1880.c
@@ -1298,7 +1298,7 @@ static const struct pinmux_ops bm1880_pinmux_ops = {
 	.set_mux = bm1880_pinmux_set_mux,
 };
 
-static struct pinctrl_desc bm1880_desc = {
+static const struct pinctrl_desc bm1880_desc = {
 	.name = "bm1880_pinctrl",
 	.pins = bm1880_pins,
 	.npins = ARRAY_SIZE(bm1880_pins),
diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c
index eddb01796a83eb86c8c5bcf6788c999e8bf2926a..66c04120c29deccf53b21cbf8705f1d10c74ace5 100644
--- a/drivers/pinctrl/pinctrl-k210.c
+++ b/drivers/pinctrl/pinctrl-k210.c
@@ -879,7 +879,7 @@ static const struct pinctrl_ops k210_pinctrl_ops = {
 	.dt_free_map = pinconf_generic_dt_free_map,
 };
 
-static struct pinctrl_desc k210_pinctrl_desc = {
+static const struct pinctrl_desc k210_pinctrl_desc = {
 	.name = "k210-pinctrl",
 	.pins = k210_pins,
 	.npins = K210_NPINS,
diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c
index 0f5a7bed2f81b731714e3b65908df23f2ffdfd63..5e0201768323521754e7ecd27e878a81925c18a6 100644
--- a/drivers/pinctrl/pinctrl-lpc18xx.c
+++ b/drivers/pinctrl/pinctrl-lpc18xx.c
@@ -1257,7 +1257,7 @@ static const struct pinctrl_ops lpc18xx_pctl_ops = {
 	.dt_free_map		= pinctrl_utils_free_map,
 };
 
-static struct pinctrl_desc lpc18xx_scu_desc = {
+static const struct pinctrl_desc lpc18xx_scu_desc = {
 	.name = "lpc18xx/43xx-scu",
 	.pins = lpc18xx_pins,
 	.npins = ARRAY_SIZE(lpc18xx_pins),
diff --git a/drivers/pinctrl/pinctrl-mlxbf3.c b/drivers/pinctrl/pinctrl-mlxbf3.c
index ffb5dda364dc81808cfd5a168ce3f1e9f119357d..fcd9d46de89fb3e5215784109ba31b171fd15448 100644
--- a/drivers/pinctrl/pinctrl-mlxbf3.c
+++ b/drivers/pinctrl/pinctrl-mlxbf3.c
@@ -231,7 +231,7 @@ static const struct pinmux_ops mlxbf3_pmx_ops = {
 	.gpio_request_enable = mlxbf3_gpio_request_enable,
 };
 
-static struct pinctrl_desc mlxbf3_pin_desc = {
+static const struct pinctrl_desc mlxbf3_pin_desc = {
 	.name = "pinctrl-mlxbf3",
 	.pins = mlxbf3_pins,
 	.npins = ARRAY_SIZE(mlxbf3_pins),
diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c
index d6bb8f58978df1577db24f96c2174f47962b5520..2d2e9f697ff99b4209dda8d5511f478a18b26a21 100644
--- a/drivers/pinctrl/pinctrl-tb10x.c
+++ b/drivers/pinctrl/pinctrl-tb10x.c
@@ -735,7 +735,7 @@ static const struct pinmux_ops tb10x_pinmux_ops = {
 	.set_mux = tb10x_pctl_set_mux,
 };
 
-static struct pinctrl_desc tb10x_pindesc = {
+static const struct pinctrl_desc tb10x_pindesc = {
 	.name = "TB10x",
 	.pins = tb10x_pins,
 	.npins = ARRAY_SIZE(tb10x_pins),
diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c
index caa8a2ca3e681718fe213921deca8d130371b122..dcde86fed10db3e2dfebc19cb841ea7f63e74989 100644
--- a/drivers/pinctrl/pinctrl-zynq.c
+++ b/drivers/pinctrl/pinctrl-zynq.c
@@ -1143,7 +1143,7 @@ static const struct pinconf_ops zynq_pinconf_ops = {
 	.pin_config_group_set = zynq_pinconf_group_set,
 };
 
-static struct pinctrl_desc zynq_desc = {
+static const struct pinctrl_desc zynq_desc = {
 	.name = "zynq_pinctrl",
 	.pins = zynq_pins,
 	.npins = ARRAY_SIZE(zynq_pins),
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
index 27f99183d994dccb92aac81ca42228bdb9225e87..aeaa0ded7c1e5ee7f9c5e4113bfd208fb844ba7d 100644
--- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
@@ -898,7 +898,7 @@ static const struct pinconf_ops starfive_pinconf_ops = {
 	.is_generic = true,
 };
 
-static struct pinctrl_desc starfive_desc = {
+static const struct pinctrl_desc starfive_desc = {
 	.name = DRIVER_NAME,
 	.pins = starfive_pins,
 	.npins = ARRAY_SIZE(starfive_pins),

-- 
2.45.2



From krzysztof.kozlowski at linaro.org  Wed May 28 03:41:13 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 12:41:13 +0200
Subject: [PATCH 17/17] rtc: stm32: Constify static 'pinctrl_desc'
In-Reply-To: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
Message-ID: <20250528-pinctrl-const-desc-v1-17-76fe97899945@linaro.org>

The local static 'struct pinctrl_desc' is not modified, so can be made
const for code safety.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

---

Patch depends on this series - const in pinctrl core. Please ack and
this should go via pinctrl tree.
---
 drivers/rtc/rtc-stm32.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-stm32.c b/drivers/rtc/rtc-stm32.c
index ef8fb88aab48a0edad19ae5872421815aa04fe46..d4ebf3eb54aa9e91c8e9f8254f571c53794192fd 100644
--- a/drivers/rtc/rtc-stm32.c
+++ b/drivers/rtc/rtc-stm32.c
@@ -393,7 +393,7 @@ static const struct pinmux_ops stm32_rtc_pinmux_ops = {
 	.strict			= true,
 };
 
-static struct pinctrl_desc stm32_rtc_pdesc = {
+static const struct pinctrl_desc stm32_rtc_pdesc = {
 	.name = DRIVER_NAME,
 	.pins = stm32_rtc_pinctrl_pins,
 	.npins = ARRAY_SIZE(stm32_rtc_pinctrl_pins),

-- 
2.45.2



From dmitry.baryshkov at oss.qualcomm.com  Wed May 28 03:55:34 2025
From: dmitry.baryshkov at oss.qualcomm.com (Dmitry Baryshkov)
Date: Wed, 28 May 2025 13:55:34 +0300
Subject: [PATCH v4] drm/bridge: tc358767: convert to
 devm_drm_bridge_alloc() API
In-Reply-To: <20250528-drm-bridge-convert-to-alloc-api-v4-1-f04e698c9a77@bootlin.com>
References: <20250528-drm-bridge-convert-to-alloc-api-v4-1-f04e698c9a77@bootlin.com>
Message-ID: <y262e67gi5f53objugljkpyc3lzdaqtw3b7qr4546btqo7ehu4@qp2orsf6xd7t>

On Wed, May 28, 2025 at 11:29:36AM +0200, Luca Ceresoli wrote:
> This is the new API for allocating DRM bridges.
> 
> Converting this driver is a bit complex because the drm_bridge funcs
> pointer differs based on the bridge mode. So the current code does:
> 
>  * tc_probe()
>    * devm_kzalloc() private struct embedding drm_bridge
>    * call tc_probe_bridge_endpoint() which
>      * parses DT description into struct fields
>      * computes the mode
>      * calls different bridge init functions based on the mode
>        * each sets a different bridge.funcs pointer
> 
> The new API expects the funcs pointer to be known at alloc time, which does
> not fit in the current code structure.
> 
> Solve this by splitting tc_probe_bridge_endpoint() in two functions:
> 
>  * tc_probe_get_mode(), computing the mode without needing the private
>    driver structure
>  * tc_probe_bridge_endpoint(), only initializing the endpoints
> 
> So now the mode is known before allocation and so
> is the funcs pointer, while all other operations are still happening after
> allocation, directly into the private struct data, as they used to.
> 
> The new code flow is:
> 
>  * tc_probe()
>    * tc_probe_get_mode()
>      * parses DT description
>      * computes and returns the mode
>    * based onf the mode, pick the funcs pointer
>    * devm_drm_bridfge_alloc(..., funcs)
>    * call tc_probe_bridge_endpoint() which
>      * calls different bridge init functions based on the mode
>        * these don't set the funcs pointer, it was done by _alloc
> 
> This solution is chosen to minimize the changes in the driver logical code
> flow. The drawback is we now iterate twice over the endpoints during probe.
> 
> Signed-off-by: Luca Ceresoli <luca.ceresoli at bootlin.com>
> ---
> devm_drm_bridge_alloc() [0] is the new API to allocate and initialize a DRM
> bridge, and the only one supported from now on. It is the first milestone
> towards removal of bridges from a still existing DRM pipeline without
> use-after-free.
> 
> The steps in the grand plan [1] are:
> 
>  1. ? add refcounting to DRM bridges (struct drm_bridge)
>  2. handle gracefully atomic updates during bridge removal
>  3. avoid DSI host drivers to have dangling pointers to DSI devices
>  4. finish the hotplug bridge work, removing the "always-disconnected"
>     connector, moving code to the core and potentially removing the
>     hotplug-bridge itself (this needs to be clarified as points 1-3 are
>     developed)
> 
> This series is part of step 1 of the grand plan.
> 
> Current tasks in step 1 of the grand plan:
> 
>  A. ? add new alloc API and refcounting -> (now in drm-misc-next)
>  B. ? convert all bridge drivers to new API (this series)
>  C. ? documentation, kunit tests (v1 under discussion)
>  D. after (B), add get/put to drm_bridge_add/remove() + attach/detech()
>  E. after (B), convert accessors; this is a large work and can be done
>     in chunks
>  F. debugfs improvements
> 
> More info about this series in the v2 cover [2].
> 
> Luca
> 
> [0] https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/0cc6aadd7fc1e629b715ea3d1ba537ef2da95eec
> [1] https://lore.kernel.org/lkml/20250206-hotplug-drm-bridge-v6-0-9d6f2c9c3058 at bootlin.com/t/#u
> [2] https://lore.kernel.org/lkml/20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b at bootlin.com/
> ---
> Changes in v4:
> - Removed patches already in drm-misc-next -> only 1 left
> - Improve commit message of patch 1
> - Link to v3: https://lore.kernel.org/all/20250509-drm-bridge-convert-to-alloc-api-v3-0-b8bc1f16d7aa at bootlin.com/
> 
> Changes in v3:
> - Fixed issues reported for some patches
> - Added review tags
> - Removed patches that have been applied
> - Added revert for the exynos patch, applied by mistake
> - Update cover with grand plan info and trim some of it
> - Updated bouncing e-mail address in Cc list
> - Link to v2: https://lore.kernel.org/lkml/20250424-drm-bridge-convert-to-alloc-api-v2-0-8f91a404d86b at bootlin.com/
> 
> Changes in v2:
> - Improved cover letter with link to commit adding devm_drm_bridge_alloc()
> - add review tags
> - fix bugs in zynqmp, vc4 patches
> - fix patch 1 error code checking
> - Link to v1: https://lore.kernel.org/r/20250407-drm-bridge-convert-to-alloc-api-v1-0-42113ff8d9c0 at bootlin.com
> ---
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov at oss.qualcomm.com>

-- 
With best wishes
Dmitry


From krzk at kernel.org  Wed May 28 05:07:29 2025
From: krzk at kernel.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 14:07:29 +0200
Subject: [PATCH] Bluetooth: BT Driver: mediatek: add gpio pin to reset bt
In-Reply-To: <20250528070323.14902-1-ot_zhangchao.zhang@mediatek.com>
References: <20250528070323.14902-1-ot_zhangchao.zhang@mediatek.com>
Message-ID: <5a430a69-6182-4a34-b5df-5fd557411b68@kernel.org>

On 28/05/2025 09:03, Zhangchao Zhang wrote:
> +
> +static int btmtk_reset_by_gpio(struct hci_dev *hdev)
> +{
> +	struct btmtk_data *data = hci_get_priv(hdev);
> +	struct btmtk_reset_gpio *reset_gpio_data;
> +	struct device_node *node;
> +	int reset_gpio_number;
> +
> +	node = of_find_compatible_node(NULL, NULL, "mediatek,usb-bluetooth");

There is no such compatible. Just git grep for it.

> +	if (node) {
> +		reset_gpio_number = of_get_named_gpio(node, "reset-gpios", 0);

Where is the ABI documented? Anyway, you should not pick GPIOs from
random devices.


Best regards,
Krzysztof


From jwboyer at kernel.org  Wed May 28 05:38:12 2025
From: jwboyer at kernel.org (Josh Boyer)
Date: Wed, 28 May 2025 08:38:12 -0400
Subject: [PATCH] linux-firmware: update firmware for MT7925 WiFi device
In-Reply-To: <20250528064305.532840-1-allan.wang@mediatek.com>
References: <20250528064305.532840-1-allan.wang@mediatek.com>
Message-ID: <CA+5PVA5U8zZ-M=YQQg2KOECdQE=n1d8A=iiTAZcbXti4qurCFw@mail.gmail.com>

Merged and pushed out.

https://gitlab.com/kernel-firmware/linux-firmware/-/merge_requests/564

josh

On Wed, May 28, 2025 at 2:46?AM Allan Wang <allan.wang at mediatek.com> wrote:
>
> Update binary firmware for MT7925 WiFi devices
>
> File: mediatek/mt7925/WIFI_MT7925_PATCH_MCU_1_1_hdr.bin
> Version: 20250526152947a
> File: mediatek/mt7925/WIFI_RAM_CODE_MT7925_1_1.bin
> Version: 20250526152808
>
> Signed-off-by: Allan Wang <allan.wang at mediatek.com>
> ---
>  WHENCE                                        |   4 ++--
>  .../mt7925/WIFI_MT7925_PATCH_MCU_1_1_hdr.bin  | Bin 212384 -> 212512 bytes
>  mediatek/mt7925/WIFI_RAM_CODE_MT7925_1_1.bin  | Bin 1204648 -> 1204648 bytes
>  3 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/WHENCE b/WHENCE
> index 93f849c4..394c23d6 100644
> --- a/WHENCE
> +++ b/WHENCE
> @@ -6214,9 +6214,9 @@ Licence: Redistributable. See LICENCE.mediatek for details.
>  Driver: mt7925 - MediaTek MT7925 Wireless MACs
>
>  File: mediatek/mt7925/WIFI_MT7925_PATCH_MCU_1_1_hdr.bin
> -Version: 20250425072955a
> +Version: 20250526152947a
>  File: mediatek/mt7925/WIFI_RAM_CODE_MT7925_1_1.bin
> -Version: 20250425072801
> +Version: 20250526152808
>
>  Licence: Redistributable. See LICENCE.mediatek for details.
>
> diff --git a/mediatek/mt7925/WIFI_MT7925_PATCH_MCU_1_1_hdr.bin b/mediatek/mt7925/WIFI_MT7925_PATCH_MCU_1_1_hdr.bin
> index 776e2b97dd4d710674c0f18e6bb65e41f7d94ae4..5c664f855f56a639224fd6e17e267b054b807226 100644
> GIT binary patch
> literal 212512
> zcma%iLy#^|vt--0ZQHhu+qiApwr$(CZQIt at ylq?azc(}S7PFaLRAyyVM%3AyU9m8+
> zursl<a4 at s8aI<k5!U)SLsYW41A^rXbK>vXlD+%&{2<*S~e*gjm^uPW8-Tr at 6(ErK+
> z9RLBP1^^}e*L-RK at PE;N<A2oub^agz?|hm85J>sJ0T9)HHYgwXpVa at T|0nl<45Gt`
> zM|q-X#g*XM(8>vhzl!czGS9BsYlT_SjZ=*Y?v+<F?tG3JC|CN(k%5>8 at l3`lv45k8
> zyUlKxNeb3qS&DM-o|6_|oh+x&oGFSc#4OqUotG*=AE0rj8;iGCT>O%Q2E2VS-AbJa
> z+AId!GHN*>>|nO51$L-%F(=y;Kap$0q%mZ|lBkJ9CI-bqh~ej>TVQ at FP9jtRO0-z+
> z6ZOmEiD-IKOY~6p%fre$(rrvK*o|=QsO)j@<HwK3u%NR}u=NJ<PyY;m-fXH0G}^RL
> zEK9t-SB}NbQY#`Wjq=tbU^8nl<2(_#2$rEknJK at kPp}uy$D1L~z|ykH&05~#7OpCE
> zwMZIF-U2Jzo<$kE>MCY|l8n(Kq^(V&dlB7dk;cbiM^*&IhTJT4v<@F?nn_UA3|BcC
> z57$^7XHe4yZELfVu?r7{P|3i`20CN;{e2s@=v at HCw(ky+t2T{0Z|?5+k>@s)Uaqip
> zM#-JdnewUmw0 at _d&pI8nq9v0^hh%J(@~K#{LZ!%YWpqj8Wh9NxNGjk&$KKdi$?t9o
> ztrHF?HL2RHZ=*xX-pCl*eV*>ljpU|9Y at mnzw_X=-`FLuG^Ek^pl}4(tl0?J*TBH}X
> zP3vkF_X*rfO%to$u at w+n_0Gy6RU;jo6ZFOId?<0zcDH^V&4-x`b&Bk;OOpFVe3cSb
> zWE0-PTLUn{H1=j8mcO{s^ggBB2@#KVOsO{*D0~K6Uolj?*z at I*S$JdpJg?kBxdR`F
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>
> diff --git a/mediatek/mt7925/WIFI_RAM_CODE_MT7925_1_1.bin b/mediatek/mt7925/WIFI_RAM_CODE_MT7925_1_1.bin
> index 10463e7161c092031f7817b1a3047372267b3cad..4a821728cc8b9d3fafb969b1b4f5e4f245803945 100644
> GIT binary patch
> delta 1030772
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> zjP8p=y at u-?d$4+ED*=D5yt*VShlb6^xQCy%pp%UR^ycEk-J&3E-F}4wf4rJyQP5Uc
> zKth04MPy=LJ+Se>`e`o_DX2UONfVo6mQ)-OKxz!P=ntZyzzaMvuKX0A<a2&T(l^s3
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> kZ7T^iGBz<aGB_|ew{~C>BmoXJGBz<aGcYtW0BL038_8alxc~qF
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>
> --
> 2.45.2
>


From jwboyer at kernel.org  Wed May 28 05:41:32 2025
From: jwboyer at kernel.org (Josh Boyer)
Date: Wed, 28 May 2025 08:41:32 -0400
Subject: [PATCH v1] mediatek MT7925: update bluetooth firmware to 20250526153203
In-Reply-To: <20250528064625.533578-1-chris.lu@mediatek.com>
References: <20250528064625.533578-1-chris.lu@mediatek.com>
Message-ID: <CA+5PVA7jHsaY6YcOszW0LPECJjCNYj=31wum57=9yc6EAgCNzQ@mail.gmail.com>

Merged and pushed out.

https://gitlab.com/kernel-firmware/linux-firmware/-/merge_requests/565

josh

On Wed, May 28, 2025 at 2:47?AM Chris Lu <chris.lu at mediatek.com> wrote:
>
> Update binary firmware for MT7925 BT devices.
>
> File: mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin
> Version: 20250526153203
>
> Signed-off-by: Chris Lu <chris.lu at mediatek.com>
> ---
>  WHENCE                                        |   2 +-
>  .../mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin     | Bin 459695 -> 459887 bytes
>  2 files changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/WHENCE b/WHENCE
> index 93f849c4..c653db09 100644
> --- a/WHENCE
> +++ b/WHENCE
> @@ -6225,7 +6225,7 @@ Licence: Redistributable. See LICENCE.mediatek for details.
>  Driver: mt7925 - MediaTek MT7925 bluetooth chipset
>
>  File: mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin
> -Version: 20250425073330
> +Version: 20250526153203
>
>  Licence: Redistributable. See LICENCE.mediatek for details.
>
> diff --git a/mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin b/mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin
> index cce1ddaeefac5a70d7ac9172ef78ce6043bf1334..9263027786aa73ad3de420ff14131492ad7f16a6 100644
> GIT binary patch
> literal 459887
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> z=_!&suVvM_Js(*RHn=(;FKjgtW$!%}*r-l4V{rLBJ at uuh&R at Iy0F_*SzCx8oeYdG@
> zLBg#>bFYnJdA{(<I at b`Q`K?iDE^YDybqge}HKX%VC at sOc|HWfqM;hv_gP~s4p9D?l
> zq7I0F{1?350Pvihn^|A|_K0%Rnv^<K(?UeqRK<eI(?z(LCCrrBNA-*g<!R^c=Z|tV
> zvSV83Vi?#4xbB`4sSU<Oiu)r9WVziD-J+{C^#hudeiAkBg%WIO6Tb;;dp>x<C)A8?
> zrCIzufk#2&w<nwzzJr%ZvL94GL{U*UO{HD0zb~Oig8=n)DJ?*zJ`t`|Oeui024<Nb
> zpx5QzDfYM7If-Yq2e!wBy at KzOT614%?z$AXOuN^ckxE^SPNoye-Zmo$Vz~zh#kkyJ
> zVWuED1u$8hp0K52;~TST^R~voCmC7DjGEZ0A`{JUvg8NpXzxW3;l0e?H!&!`hMs$S
> zA4{HDMOQV&EVCC$toVuZed1wc=r3rYq0@}oYJgd3$8a4a-SRYYc-8n+MhUC`@**pX
> zC}23;<f*a=km=EcTYW;wHD{_u48+6wma_QWlsiM*Q!1^gIvKgEUFB!{R~hI!wCAB+
> z&K-7Ow*K>9KX8h;FxU3cI{DwQ%O`qT{r^7!XiEK^4e}JAOcF6oW=H4`dje|{jrX{e
> z&7!v!T)*DiA%7X;w+%9eUG^godzZKkRcp(k=^@MfLMi)UM#2Nm<@yP8$2VRz-ky!c
> z+MM+Q0g_*&EC;ZShm19|;n8{B=Fkx=_2LLhO7DeVu{l5Tyo?b!?C(tMTd&z$-#O|j
> zAzgYC1B;ifw03>MbrJi=OgDswqQonSH)=72o#Z<(5c9PqSpBVJ*gqnLvqoiVpW|D&
> zkSl!y54J#Ox5B?$8d<+6H6!3499n`gAi}wahJeb7 at lPSg%nQ?oy33EP5D1-o_ReX^
> z|0wNp%!Y`h{}Li5mzmGvW3qJ0vgyat)oojEtmcWO94wYXyI~Qah1$=<7n-TIA#e#e
> zSs^_z+-J*jPCgu;0zQ at j10X?wQ|ZVtD6vLiSLUbjsEY}fm3&uvV(q*~KQA-fb19n*
> z7<Z}dqMrS4yxl!39c<z+^jzPM((K1Dj`avNfILqEv9P5{h$TFINVvF>_-O<|v%zY9
> zv!`l_VbJ79;r5eOuKa(SEWWB)Q$Ut0eEub#C_VVXhX}KL&L62~Ps-j-jQc1vfHt^p
> zP!i`N%C&sMmiPE*qljB<fRr7*33rBw81Aq({A<Sl&5sa1=;ZL&dxvm6k$K>huRg#y
> z at 8n97D&l5xG6?avU~*kbF}{KSDHrFGK_${JfXvV!2 at 3|&=`DU9f-izZzz?XY>7X!L
> z#&cVDV)$y at -hi6b6^=_HEZ`9XvLkey601O6CS9=~qQBuD$+GYY*SuZ=Op_GS4%WAM
> z{veJSgYX~>hGWJF{YZLKW%-6QW}=i;^?ewa<Q_x@;}GqyEy at -mb9hpL`GWOknjuhr
> z|6juY!Y~w&#{hE8Jx9aw%|`Ot(q_Lnl|eXuH4 at S^oz1tUPiJbu>{wE#rYniLg)YQX
> zz9XQr4g-st70m<kc-Lap&-&tU*8gG%<Xy5KLlq5?)}#%(F3A~;38&G`TusEr??Tzj
> z=N{?kX^m^rHs{u(@v==)o9x$!fCXD4voLFHU_3TJa2WU7AaAZd7+G1~0&6=9{cj0r
> zBNfBN$cNR6I#T$ZuV(sw{&)N6j7FDF(mmlUL$ZNn7K%g{3MZy>o at N5)lsb!}gTKlQ
> zsCtC#PU<TNc=dZnR+3I@)HQ`^W)L17AA2Sj05uMFrKv?9Kkm?*n2}xO{p$;GM1IsT
> zPgJJ!dex~8l;DQxmkbr-EQw69+VY?aVPDbQ9Co182K&~%y)<m|H|5OzjA;$LHnbLi
> zq`TZ5S?xnyEUURsS9~~R-~OE)y!FiatlI^5FIB$AH)B$?e<3E3ulG|Jhzhc_7_Amp
> zN-%jz$ncd1;2yU%7I|01b3^O0N at c%HLA}n2w{UW{7g>9x)$VzR1Ohz9nui}=-q4|4
> zct;aF-$<oW6wE=CEE*4=sM{Bt1NuOothy at Xx$I`f6KR<I?rpk>ehFNNp_ZO3uAT**
> z0a8S6+V!NVp$eCNM>PP<MQ9J|Sv8iBNDHW at vih1VPH>yA=rpdw-L-khu7k|BhKy2<
> zna2S-*nR|3JD`xY;nTmWOih^>Lhnfmj#gNF<lYn`UPq5B?0>JAP!BVa2=j4uysp28
> zbwJ(z^E-g1dhB?|6}q|XY#xu;#L`|^&tqZSkyT_=P>GrxPWXIFrrci!y8kI0{JF36
> z`D9#(al0s6HA*&T<YRzuB=~tl+l}UBQ)8!S`awKBQ8(+gY)8N!)GyS~r{YtV&;9sJ
> zxnhzHPtQKT9K&Cro at BTIzJltkkx`kiKZ_pgOrwzhg489JAR+;d>=W1qYR%AK3%g<)
> zq4wv(R!Ow)^wCP>#L~jM{U?gr7+cU3xSzk+sG|xm8mVpm63j%I7FOLkWwWL(R!LI^
> zxIO?f8Xt{0Lhg|Rtcke5?J=HofkxrwDP%p3Mm)m=G5)ZR>ziEz-$@RqqSbCy$9({a
> zx>%gpmjxKFwr+8Q(ellNFPXdYC7TyE03jl<&vL2O1KcD124NGOV=9-ie(6iX>$oMU
> z8$_|!m>Zs{<5X<Vd5()krL!>_Sy63wrAvEI8jRP3!b2DeEa~+KiNqFd7}z!FJ1s~O
> z(IBj3YXRf?03F;~36}W_oMvj2zK;>jhY)?CWS-gkv at Q5R#>FvW)0xTve`$vWXPr{y
> z_mti|g8mP|pRAz at 4BQtyv0PfMI%i|wJYLP;;6<s>$>|gOu#wf};|j-K)+7lq?5@{;
> z-I<RZZ9NILaQPTYY85b{wzSdl;b;UNY!XD at Q_=yW#UEwur8Z%{)OrRwc2RUX7j)oh
> zSg-6ff4GXm=MJ&QKx06x&E&q{)aN-4Ht}fs9Iv?KHHw$2iip&&!T`HAo@$6d2uS%O
> zABQMxzYW3W!Ta264gkp|x?-V8@%lbiANq{+eCSar;^`NHU0zOq#9%|`x$NNS9Say!
> zXYm>(cZeD5%>GKl6H=fk|L^h`Q1Og*4v*j<-R2BKn(qFW7^Xd3a{rxnMi at qbGJ;b)
> zGwd|&W7p;-Qp?mp8ne2U7SD at Sr0o8=b&#KD>{hxZs>O?g>S_FcFUl(haky?Ix}_%^
> zSx<*1n at B8?l_sE4%Khfuh+odQBHdqm3Y)I?a|h{27k2ECRwkFBqc7tkkB_TzhiE&}
> zYTKsQ8<ufyPlhhJoHg`x(*$X`A=o_HqJFFH>(}de^i89e()|oNsadF*T`s4y>J;s;
> z%eUl$z_1V|JatTeX5dh#eqo8&ggdI&LFm{VvxoK?O8=3eDixM;NCe-`Tfc?tabCtj
> zA%7e3XTUU!rS<oEJ!BchNRZo{K*D57V;V$p at iZVp@7kPu5ILG<cNM?+{n6wlK~8Cn
> zUw(FTfWHbfF?fKJ|EY84lxH;iSQ3dgk{L_B#l$-h*iuZ6zs<vBqTz#hemLS$%pk*e
> zK~f$Bc#EX at +Cf@OAY5t at v^djC-%S;0Cpq8LG!Sod<h{@U4*^Er=y$-xb9Ztm8)G at F
> zbsRfiQU}6YE8-_w%*b(6qIs7T at v(TGq=o`4aK?fmsuMLwS1)k`drQzqH5smV7HozC
> zqid-<3fAIj<SG0Iu6Kr*soz^D=6Y(dRy-AK)OZTjP+f9he~nIIG=+IIMsDiB=WT}I
> z{-%Z`T^V{DeW(jzps%AHmY4ltjw78|+EjQ>0U(3#bsQcCUJ$n|BM)DaAxH~|E-^oG
> zBJ<ld+^)qKfO4 at jOFo{&YUWvdGkZ`{Vxro!;h8;6C(c|I(8}9}6QXo2Ze?(Eb#7%X
> zZDDC{Ep2o+IWjdZGBPwdElpH6IWje0MKNDNQ%OT#Qcq1^QbA2$Lq%UQGBi0~Lqkq6
> UHZ3wRGBq$XGBq$aGB_|X3J3BFd;kCd
>
> --
> 2.45.2
>


From geert at linux-m68k.org  Wed May 28 05:36:20 2025
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Wed, 28 May 2025 14:36:20 +0200
Subject: [PATCH 01/17] pinctrl: starfive: Allow compile testing on other platforms
In-Reply-To: <20250528-pinctrl-const-desc-v1-1-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org> <20250528-pinctrl-const-desc-v1-1-76fe97899945@linaro.org>
Message-ID: <CAMuHMdX7krbAssbYpJ1RA1EkpOP26nUhuhmtSW8X9nJkB5amBQ@mail.gmail.com>

Hi Krzysztof,

On Wed, 28 May 2025 at 12:41, Krzysztof Kozlowski
<krzysztof.kozlowski at linaro.org> wrote:
> Always descent to drivers/pinctrl/starfive/ because limiting it with
> SOC_STARFIVE is redundant since all of its Kconfig entries are already

... since its Makefile doesn't build anything if no Starfive-specific
pin control Kconfig options are enabled?

> have "depends on SOC_STARFIVE".  This allows compile testing on other
> architectures with allyesconfig.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> ---
>  drivers/pinctrl/Makefile | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> index ac27e88677d14f1c697e0d0be9f295c746556f4d..dcede70b25660833a158c298d1269d6ecea9dd8b 100644
> --- a/drivers/pinctrl/Makefile
> +++ b/drivers/pinctrl/Makefile
> @@ -82,7 +82,7 @@ obj-y                         += sophgo/
>  obj-y                          += spacemit/
>  obj-$(CONFIG_PINCTRL_SPEAR)    += spear/
>  obj-y                          += sprd/
> -obj-$(CONFIG_SOC_STARFIVE)     += starfive/
> +obj-y                          += starfive/
>  obj-$(CONFIG_PINCTRL_STM32)    += stm32/
>  obj-y                          += sunplus/
>  obj-$(CONFIG_PINCTRL_SUNXI)    += sunxi/

The actual change LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas at glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From krzysztof.kozlowski at linaro.org  Wed May 28 05:51:43 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 14:51:43 +0200
Subject: [PATCH 01/17] pinctrl: starfive: Allow compile testing on other
 platforms
In-Reply-To: <CAMuHMdX7krbAssbYpJ1RA1EkpOP26nUhuhmtSW8X9nJkB5amBQ@mail.gmail.com>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
 <20250528-pinctrl-const-desc-v1-1-76fe97899945@linaro.org>
 <CAMuHMdX7krbAssbYpJ1RA1EkpOP26nUhuhmtSW8X9nJkB5amBQ@mail.gmail.com>
Message-ID: <4a2a8504-310d-4b65-ba52-1854f461b604@linaro.org>

On 28/05/2025 14:36, Geert Uytterhoeven wrote:
> Hi Krzysztof,
> 
> On Wed, 28 May 2025 at 12:41, Krzysztof Kozlowski
> <krzysztof.kozlowski at linaro.org> wrote:
>> Always descent to drivers/pinctrl/starfive/ because limiting it with
>> SOC_STARFIVE is redundant since all of its Kconfig entries are already
> 
> ... since its Makefile doesn't build anything if no Starfive-specific
> pin control Kconfig options are enabled?

Yes, that's better. Thank you.

> 
>> have "depends on SOC_STARFIVE".  This allows compile testing on other
>> architectures with allyesconfig.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
>> ---
>>  drivers/pinctrl/Makefile | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
>> index ac27e88677d14f1c697e0d0be9f295c746556f4d..dcede70b25660833a158c298d1269d6ecea9dd8b 100644
>> --- a/drivers/pinctrl/Makefile
>> +++ b/drivers/pinctrl/Makefile
>> @@ -82,7 +82,7 @@ obj-y                         += sophgo/
>>  obj-y                          += spacemit/
>>  obj-$(CONFIG_PINCTRL_SPEAR)    += spear/
>>  obj-y                          += sprd/
>> -obj-$(CONFIG_SOC_STARFIVE)     += starfive/
>> +obj-y                          += starfive/
>>  obj-$(CONFIG_PINCTRL_STM32)    += stm32/
>>  obj-y                          += sunplus/
>>  obj-$(CONFIG_PINCTRL_SUNXI)    += sunxi/
> 
> The actual change LGTM, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas at glider.be>
> 
Ack

Best regards,
Krzysztof


From lorenzo at kernel.org  Wed May 28 05:51:51 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Wed, 28 May 2025 14:51:51 +0200
Subject: [PATCH 16/17] pinctrl: Constify static 'pinctrl_desc'
In-Reply-To: <20250528-pinctrl-const-desc-v1-16-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
 <20250528-pinctrl-const-desc-v1-16-76fe97899945@linaro.org>
Message-ID: <aDcG58lXUgtW7pRZ@lore-desk>

> The local static 'struct pinctrl_desc' is not modified, so can be made
> const for code safety.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

For airoha bits:

Acked-by: Lorenzo Bianconi <lorenzo at kernel.org>

> ---
>  drivers/pinctrl/berlin/berlin.c                    | 2 +-
>  drivers/pinctrl/cirrus/pinctrl-cs42l43.c           | 2 +-
>  drivers/pinctrl/mediatek/pinctrl-airoha.c          | 2 +-
>  drivers/pinctrl/pinctrl-artpec6.c                  | 2 +-
>  drivers/pinctrl/pinctrl-bm1880.c                   | 2 +-
>  drivers/pinctrl/pinctrl-k210.c                     | 2 +-
>  drivers/pinctrl/pinctrl-lpc18xx.c                  | 2 +-
>  drivers/pinctrl/pinctrl-mlxbf3.c                   | 2 +-
>  drivers/pinctrl/pinctrl-tb10x.c                    | 2 +-
>  drivers/pinctrl/pinctrl-zynq.c                     | 2 +-
>  drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c | 2 +-
>  11 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c
> index c372a2a24be4bb80b1f2475ef8512171c8e1326f..e5a35b803ce66d247c5e5ad78e6677570a1add60 100644
> --- a/drivers/pinctrl/berlin/berlin.c
> +++ b/drivers/pinctrl/berlin/berlin.c
> @@ -283,7 +283,7 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -static struct pinctrl_desc berlin_pctrl_desc = {
> +static const struct pinctrl_desc berlin_pctrl_desc = {
>  	.name		= "berlin-pinctrl",
>  	.pctlops	= &berlin_pinctrl_ops,
>  	.pmxops		= &berlin_pinmux_ops,
> diff --git a/drivers/pinctrl/cirrus/pinctrl-cs42l43.c b/drivers/pinctrl/cirrus/pinctrl-cs42l43.c
> index 628b60ccc2b07dc77e36da8919436fa348749e0c..a90beb986f5bb707c54552e1333802943a4b04bc 100644
> --- a/drivers/pinctrl/cirrus/pinctrl-cs42l43.c
> +++ b/drivers/pinctrl/cirrus/pinctrl-cs42l43.c
> @@ -448,7 +448,7 @@ static const struct pinconf_ops cs42l43_pin_conf_ops = {
>  	.pin_config_group_set	= cs42l43_pin_config_group_set,
>  };
>  
> -static struct pinctrl_desc cs42l43_pin_desc = {
> +static const struct pinctrl_desc cs42l43_pin_desc = {
>  	.name		= "cs42l43-pinctrl",
>  	.owner		= THIS_MODULE,
>  
> diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> index b97b28ebb37a6ec092360f8ea404dd67e6c43eac..ccd2b512e8365b3a5af0bb223329f39119bc7078 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> @@ -2852,7 +2852,7 @@ static const struct pinctrl_ops airoha_pctlops = {
>  	.dt_free_map = pinconf_generic_dt_free_map,
>  };
>  
> -static struct pinctrl_desc airoha_pinctrl_desc = {
> +static const struct pinctrl_desc airoha_pinctrl_desc = {
>  	.name = KBUILD_MODNAME,
>  	.owner = THIS_MODULE,
>  	.pctlops = &airoha_pctlops,
> diff --git a/drivers/pinctrl/pinctrl-artpec6.c b/drivers/pinctrl/pinctrl-artpec6.c
> index 717f9592b28b51737e67aafc93664b1345511908..af67057128ff1e9e766b958fece9c71518c89081 100644
> --- a/drivers/pinctrl/pinctrl-artpec6.c
> +++ b/drivers/pinctrl/pinctrl-artpec6.c
> @@ -907,7 +907,7 @@ static const struct pinconf_ops artpec6_pconf_ops = {
>  	.pin_config_group_set	= artpec6_pconf_group_set,
>  };
>  
> -static struct pinctrl_desc artpec6_desc = {
> +static const struct pinctrl_desc artpec6_desc = {
>  	.name	 = "artpec6-pinctrl",
>  	.owner	 = THIS_MODULE,
>  	.pins	 = artpec6_pins,
> diff --git a/drivers/pinctrl/pinctrl-bm1880.c b/drivers/pinctrl/pinctrl-bm1880.c
> index b0000fe5b31dfbcd6af6eaf0c01029f00cbd205b..387798fb09be51cabd5cb76e0d90a28b1d363050 100644
> --- a/drivers/pinctrl/pinctrl-bm1880.c
> +++ b/drivers/pinctrl/pinctrl-bm1880.c
> @@ -1298,7 +1298,7 @@ static const struct pinmux_ops bm1880_pinmux_ops = {
>  	.set_mux = bm1880_pinmux_set_mux,
>  };
>  
> -static struct pinctrl_desc bm1880_desc = {
> +static const struct pinctrl_desc bm1880_desc = {
>  	.name = "bm1880_pinctrl",
>  	.pins = bm1880_pins,
>  	.npins = ARRAY_SIZE(bm1880_pins),
> diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c
> index eddb01796a83eb86c8c5bcf6788c999e8bf2926a..66c04120c29deccf53b21cbf8705f1d10c74ace5 100644
> --- a/drivers/pinctrl/pinctrl-k210.c
> +++ b/drivers/pinctrl/pinctrl-k210.c
> @@ -879,7 +879,7 @@ static const struct pinctrl_ops k210_pinctrl_ops = {
>  	.dt_free_map = pinconf_generic_dt_free_map,
>  };
>  
> -static struct pinctrl_desc k210_pinctrl_desc = {
> +static const struct pinctrl_desc k210_pinctrl_desc = {
>  	.name = "k210-pinctrl",
>  	.pins = k210_pins,
>  	.npins = K210_NPINS,
> diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c
> index 0f5a7bed2f81b731714e3b65908df23f2ffdfd63..5e0201768323521754e7ecd27e878a81925c18a6 100644
> --- a/drivers/pinctrl/pinctrl-lpc18xx.c
> +++ b/drivers/pinctrl/pinctrl-lpc18xx.c
> @@ -1257,7 +1257,7 @@ static const struct pinctrl_ops lpc18xx_pctl_ops = {
>  	.dt_free_map		= pinctrl_utils_free_map,
>  };
>  
> -static struct pinctrl_desc lpc18xx_scu_desc = {
> +static const struct pinctrl_desc lpc18xx_scu_desc = {
>  	.name = "lpc18xx/43xx-scu",
>  	.pins = lpc18xx_pins,
>  	.npins = ARRAY_SIZE(lpc18xx_pins),
> diff --git a/drivers/pinctrl/pinctrl-mlxbf3.c b/drivers/pinctrl/pinctrl-mlxbf3.c
> index ffb5dda364dc81808cfd5a168ce3f1e9f119357d..fcd9d46de89fb3e5215784109ba31b171fd15448 100644
> --- a/drivers/pinctrl/pinctrl-mlxbf3.c
> +++ b/drivers/pinctrl/pinctrl-mlxbf3.c
> @@ -231,7 +231,7 @@ static const struct pinmux_ops mlxbf3_pmx_ops = {
>  	.gpio_request_enable = mlxbf3_gpio_request_enable,
>  };
>  
> -static struct pinctrl_desc mlxbf3_pin_desc = {
> +static const struct pinctrl_desc mlxbf3_pin_desc = {
>  	.name = "pinctrl-mlxbf3",
>  	.pins = mlxbf3_pins,
>  	.npins = ARRAY_SIZE(mlxbf3_pins),
> diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c
> index d6bb8f58978df1577db24f96c2174f47962b5520..2d2e9f697ff99b4209dda8d5511f478a18b26a21 100644
> --- a/drivers/pinctrl/pinctrl-tb10x.c
> +++ b/drivers/pinctrl/pinctrl-tb10x.c
> @@ -735,7 +735,7 @@ static const struct pinmux_ops tb10x_pinmux_ops = {
>  	.set_mux = tb10x_pctl_set_mux,
>  };
>  
> -static struct pinctrl_desc tb10x_pindesc = {
> +static const struct pinctrl_desc tb10x_pindesc = {
>  	.name = "TB10x",
>  	.pins = tb10x_pins,
>  	.npins = ARRAY_SIZE(tb10x_pins),
> diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c
> index caa8a2ca3e681718fe213921deca8d130371b122..dcde86fed10db3e2dfebc19cb841ea7f63e74989 100644
> --- a/drivers/pinctrl/pinctrl-zynq.c
> +++ b/drivers/pinctrl/pinctrl-zynq.c
> @@ -1143,7 +1143,7 @@ static const struct pinconf_ops zynq_pinconf_ops = {
>  	.pin_config_group_set = zynq_pinconf_group_set,
>  };
>  
> -static struct pinctrl_desc zynq_desc = {
> +static const struct pinctrl_desc zynq_desc = {
>  	.name = "zynq_pinctrl",
>  	.pins = zynq_pins,
>  	.npins = ARRAY_SIZE(zynq_pins),
> diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
> index 27f99183d994dccb92aac81ca42228bdb9225e87..aeaa0ded7c1e5ee7f9c5e4113bfd208fb844ba7d 100644
> --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
> +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
> @@ -898,7 +898,7 @@ static const struct pinconf_ops starfive_pinconf_ops = {
>  	.is_generic = true,
>  };
>  
> -static struct pinctrl_desc starfive_desc = {
> +static const struct pinctrl_desc starfive_desc = {
>  	.name = DRIVER_NAME,
>  	.pins = starfive_pins,
>  	.npins = ARRAY_SIZE(starfive_pins),
> 
> -- 
> 2.45.2
> 
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From geert at linux-m68k.org  Wed May 28 05:47:49 2025
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Wed, 28 May 2025 14:47:49 +0200
Subject: [PATCH 04/17] pinctrl: Constify pointers to 'pinctrl_desc'
In-Reply-To: <20250528-pinctrl-const-desc-v1-4-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org> <20250528-pinctrl-const-desc-v1-4-76fe97899945@linaro.org>
Message-ID: <CAMuHMdUWqvHGKHqUWf6xdVBzaungUq1Fq=g_+qFQRO5+fq4=vQ@mail.gmail.com>

On Wed, 28 May 2025 at 12:41, Krzysztof Kozlowski
<krzysztof.kozlowski at linaro.org> wrote:
> Pin controller core code only stores the pointer to
> 'struct pinctrl_desc' and does not modify it anywhere.  The pointer can
> be changed to pointer to const which makes the code safer, explicit and
> later allows constifying 'pinctrl_desc' allocations in individual
> drivers.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas at glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From geert at linux-m68k.org  Wed May 28 05:54:41 2025
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Wed, 28 May 2025 14:54:41 +0200
Subject: [PATCH 14/17] pinctrl: renesas: Move fixed assignments to
 'pinctrl_desc' definition
In-Reply-To: <20250528-pinctrl-const-desc-v1-14-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org> <20250528-pinctrl-const-desc-v1-14-76fe97899945@linaro.org>
Message-ID: <CAMuHMdUGDf5n_Fg7pwiPumm95nPUXyH15geAy2ULwY3U+OtZJA@mail.gmail.com>

Hi Krzysztof,

On Wed, 28 May 2025 at 12:42, Krzysztof Kozlowski
<krzysztof.kozlowski at linaro.org> wrote:
> Assign 'struct pinctrl_desc' .pins and .npins members in definition to
> make clear that number of pins is fixed and have less code in the probe.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas at glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas at glider.be>

> --- a/drivers/pinctrl/renesas/pinctrl-rzn1.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzn1.c
> @@ -680,6 +680,8 @@ static struct pinctrl_desc rzn1_pinctrl_desc = {

This structure could be made const...

>         .pmxops = &rzn1_pmx_ops,
>         .confops = &rzn1_pinconf_ops,
>         .owner = THIS_MODULE,
> +       .pins = rzn1_pins,
> +       .npins = ARRAY_SIZE(rzn1_pins),
>  };
>
>  static int rzn1_pinctrl_parse_groups(struct device_node *np,
> @@ -878,8 +880,6 @@ static int rzn1_pinctrl_probe(struct platform_device *pdev)
>
>         ipctl->dev = &pdev->dev;
>         rzn1_pinctrl_desc.name = dev_name(&pdev->dev);

... if you would replace this assignment by a hardcoded name
like "pinctrl-rzn1".

> -       rzn1_pinctrl_desc.pins = rzn1_pins;
> -       rzn1_pinctrl_desc.npins = ARRAY_SIZE(rzn1_pins);
>
>         ret = rzn1_pinctrl_probe_dt(pdev, ipctl);
>         if (ret) {

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From conor at kernel.org  Wed May 28 06:46:03 2025
From: conor at kernel.org (Conor Dooley)
Date: Wed, 28 May 2025 14:46:03 +0100
Subject: [PATCH 0/2] Add MT8189 jpeg encoder and decoder compatible
In-Reply-To: <20250528095748.17485-1-jianhua.lin@mediatek.com>
References: <20250528095748.17485-1-jianhua.lin@mediatek.com>
Message-ID: <20250528-energetic-voltage-b02704c14df8@spud>

On Wed, May 28, 2025 at 05:57:46PM +0800, Jianhua Lin wrote:
> This series is based on tag: next-20250528, linux-next/master
> 
> jianhua.lin (2):
>   dt-bindings: media: mediatek-jpeg-encoder: Add MT8189 compatible
>     string
>   dt-bindings: media: mediatek-jpeg-decoder: Add MT8189 compatible
>     string

Acked-by: Conor Dooley <conor.dooley at microchip.com>
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From linux at fw-web.de  Wed May 28 06:52:49 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Wed, 28 May 2025 15:52:49 +0200
Subject: [RFC v1] dt-bindings: interconnect: add mt7988-cci compatible
Message-ID: <20250528135251.6492-1-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Add compatible for Mediatek MT7988 SoC with mediatek,mt8183-cci fallback
which is taken by driver.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 .../bindings/interconnect/mediatek,cci.yaml          | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
index 58611ba2a0f4..2c6785c588e9 100644
--- a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
+++ b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
@@ -17,9 +17,15 @@ description: |
 
 properties:
   compatible:
-    enum:
-      - mediatek,mt8183-cci
-      - mediatek,mt8186-cci
+    oneOf:
+      - items:
+          - enum:
+              - mediatek,mt8183-cci
+              - mediatek,mt8186-cci
+      - items:
+          - enum:
+              - mediatek,mt7988-cci
+          - const: mediatek,mt8183-cci
 
   clocks:
     items:
-- 
2.43.0



From Frank.li at nxp.com  Wed May 28 09:00:40 2025
From: Frank.li at nxp.com (Frank Li)
Date: Wed, 28 May 2025 12:00:40 -0400
Subject: [PATCH] thermal: Constify struct thermal_zone_device_ops
In-Reply-To: <5bba3bf0139e2418b306a0f9a2f1f81ef49e88a6.1748165978.git.christophe.jaillet@wanadoo.fr>
References: <5bba3bf0139e2418b306a0f9a2f1f81ef49e88a6.1748165978.git.christophe.jaillet@wanadoo.fr>
Message-ID: <aDczKA71dqJscfUK@lizhi-Precision-Tower-5810>

On Sun, May 25, 2025 at 11:40:04AM +0200, Christophe JAILLET wrote:
> 'struct thermal_zone_device_ops' are not modified in these drivers.
>
> Constifying these structures moves some data to a read-only section, so
> increases overall security, especially when the structure holds some
> function pointers.
>
> On a x86_64, with allmodconfig, as an example:
> Before:
> ======
>    text	   data	    bss	    dec	    hex	filename
>   28116	   5168	    128	  33412	   8284	drivers/thermal/armada_thermal.o
>
> After:
> =====
>    text	   data	    bss	    dec	    hex	filename
>   28244	   5040	    128	  33412	   8284	drivers/thermal/armada_thermal.o
>
> Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
> ---
> Compile tested only
> ---
>  drivers/thermal/armada_thermal.c                        | 2 +-
>  drivers/thermal/da9062-thermal.c                        | 2 +-
>  drivers/thermal/dove_thermal.c                          | 2 +-
>  drivers/thermal/imx_thermal.c                           | 2 +-

for imx thermal part

Reviewed-by: Frank Li <Frank.Li at nxp.com>

>  drivers/thermal/intel/int340x_thermal/int3400_thermal.c | 2 +-
>  drivers/thermal/kirkwood_thermal.c                      | 2 +-
>  drivers/thermal/mediatek/lvts_thermal.c                 | 2 +-
>  drivers/thermal/renesas/rcar_thermal.c                  | 2 +-
>  drivers/thermal/spear_thermal.c                         | 2 +-
>  drivers/thermal/st/st_thermal.c                         | 2 +-
>  drivers/thermal/testing/zone.c                          | 2 +-
>  11 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c
> index 9bff21068721..c2fbdb534f61 100644
> --- a/drivers/thermal/armada_thermal.c
> +++ b/drivers/thermal/armada_thermal.c
> @@ -408,7 +408,7 @@ static int armada_get_temp_legacy(struct thermal_zone_device *thermal,
>  	return ret;
>  }
>
> -static struct thermal_zone_device_ops legacy_ops = {
> +static const struct thermal_zone_device_ops legacy_ops = {
>  	.get_temp = armada_get_temp_legacy,
>  };
>
> diff --git a/drivers/thermal/da9062-thermal.c b/drivers/thermal/da9062-thermal.c
> index 2077e85ef5ca..a8d4b766ba21 100644
> --- a/drivers/thermal/da9062-thermal.c
> +++ b/drivers/thermal/da9062-thermal.c
> @@ -137,7 +137,7 @@ static int da9062_thermal_get_temp(struct thermal_zone_device *z,
>  	return 0;
>  }
>
> -static struct thermal_zone_device_ops da9062_thermal_ops = {
> +static const struct thermal_zone_device_ops da9062_thermal_ops = {
>  	.get_temp	= da9062_thermal_get_temp,
>  };
>
> diff --git a/drivers/thermal/dove_thermal.c b/drivers/thermal/dove_thermal.c
> index f9157a47156b..723bc72f0626 100644
> --- a/drivers/thermal/dove_thermal.c
> +++ b/drivers/thermal/dove_thermal.c
> @@ -106,7 +106,7 @@ static int dove_get_temp(struct thermal_zone_device *thermal,
>  	return 0;
>  }
>
> -static struct thermal_zone_device_ops ops = {
> +static const struct thermal_zone_device_ops ops = {
>  	.get_temp = dove_get_temp,
>  };
>
> diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
> index bab52e6b3b15..38c993d1bcb3 100644
> --- a/drivers/thermal/imx_thermal.c
> +++ b/drivers/thermal/imx_thermal.c
> @@ -361,7 +361,7 @@ static bool imx_should_bind(struct thermal_zone_device *tz,
>  	return trip->type == THERMAL_TRIP_PASSIVE;
>  }
>
> -static struct thermal_zone_device_ops imx_tz_ops = {
> +static const struct thermal_zone_device_ops imx_tz_ops = {
>  	.should_bind = imx_should_bind,
>  	.get_temp = imx_get_temp,
>  	.change_mode = imx_change_mode,
> diff --git a/drivers/thermal/intel/int340x_thermal/int3400_thermal.c b/drivers/thermal/intel/int340x_thermal/int3400_thermal.c
> index 0e07693ecf59..5736638c586b 100644
> --- a/drivers/thermal/intel/int340x_thermal/int3400_thermal.c
> +++ b/drivers/thermal/intel/int340x_thermal/int3400_thermal.c
> @@ -515,7 +515,7 @@ static int int3400_thermal_change_mode(struct thermal_zone_device *thermal,
>  	return result;
>  }
>
> -static struct thermal_zone_device_ops int3400_thermal_ops = {
> +static const struct thermal_zone_device_ops int3400_thermal_ops = {
>  	.get_temp = int3400_thermal_get_temp,
>  	.change_mode = int3400_thermal_change_mode,
>  };
> diff --git a/drivers/thermal/kirkwood_thermal.c b/drivers/thermal/kirkwood_thermal.c
> index 7c2265231668..4619e090f756 100644
> --- a/drivers/thermal/kirkwood_thermal.c
> +++ b/drivers/thermal/kirkwood_thermal.c
> @@ -48,7 +48,7 @@ static int kirkwood_get_temp(struct thermal_zone_device *thermal,
>  	return 0;
>  }
>
> -static struct thermal_zone_device_ops ops = {
> +static const struct thermal_zone_device_ops ops = {
>  	.get_temp = kirkwood_get_temp,
>  };
>
> diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
> index 985925147ac0..acce8fde2cba 100644
> --- a/drivers/thermal/mediatek/lvts_thermal.c
> +++ b/drivers/thermal/mediatek/lvts_thermal.c
> @@ -571,7 +571,7 @@ static irqreturn_t lvts_irq_handler(int irq, void *data)
>  	return iret;
>  }
>
> -static struct thermal_zone_device_ops lvts_ops = {
> +static const struct thermal_zone_device_ops lvts_ops = {
>  	.get_temp = lvts_get_temp,
>  	.set_trips = lvts_set_trips,
>  };
> diff --git a/drivers/thermal/renesas/rcar_thermal.c b/drivers/thermal/renesas/rcar_thermal.c
> index 00a66ee0a5b0..fdd7afdc4ff6 100644
> --- a/drivers/thermal/renesas/rcar_thermal.c
> +++ b/drivers/thermal/renesas/rcar_thermal.c
> @@ -277,7 +277,7 @@ static int rcar_thermal_get_temp(struct thermal_zone_device *zone, int *temp)
>  	return rcar_thermal_get_current_temp(priv, temp);
>  }
>
> -static struct thermal_zone_device_ops rcar_thermal_zone_ops = {
> +static const struct thermal_zone_device_ops rcar_thermal_zone_ops = {
>  	.get_temp	= rcar_thermal_get_temp,
>  };
>
> diff --git a/drivers/thermal/spear_thermal.c b/drivers/thermal/spear_thermal.c
> index bb96be947521..603dadcd3df5 100644
> --- a/drivers/thermal/spear_thermal.c
> +++ b/drivers/thermal/spear_thermal.c
> @@ -41,7 +41,7 @@ static inline int thermal_get_temp(struct thermal_zone_device *thermal,
>  	return 0;
>  }
>
> -static struct thermal_zone_device_ops ops = {
> +static const struct thermal_zone_device_ops ops = {
>  	.get_temp = thermal_get_temp,
>  };
>
> diff --git a/drivers/thermal/st/st_thermal.c b/drivers/thermal/st/st_thermal.c
> index a14a37d54698..1470ca519def 100644
> --- a/drivers/thermal/st/st_thermal.c
> +++ b/drivers/thermal/st/st_thermal.c
> @@ -132,7 +132,7 @@ static int st_thermal_get_temp(struct thermal_zone_device *th, int *temperature)
>  	return 0;
>  }
>
> -static struct thermal_zone_device_ops st_tz_ops = {
> +static const struct thermal_zone_device_ops st_tz_ops = {
>  	.get_temp	= st_thermal_get_temp,
>  };
>
> diff --git a/drivers/thermal/testing/zone.c b/drivers/thermal/testing/zone.c
> index 1f4e450100e2..4257d813d572 100644
> --- a/drivers/thermal/testing/zone.c
> +++ b/drivers/thermal/testing/zone.c
> @@ -381,7 +381,7 @@ static int tt_zone_get_temp(struct thermal_zone_device *tz, int *temp)
>  	return 0;
>  }
>
> -static struct thermal_zone_device_ops tt_zone_ops = {
> +static const struct thermal_zone_device_ops tt_zone_ops = {
>  	.get_temp = tt_zone_get_temp,
>  };
>
> --
> 2.49.0
>


From frank-w at public-files.de  Wed May 28 09:10:14 2025
From: frank-w at public-files.de (Frank Wunderlich)
Date: Wed, 28 May 2025 16:10:14 +0000
Subject: Aw: [PATCH 2/3] thermal/drivers/mediatek/lvts_thermal: add lvts
 commands and their sizes to driver data
In-Reply-To: <20250526102659.30225-3-mason-cw.chang@mediatek.com>
References: <20250526102659.30225-1-mason-cw.chang@mediatek.com>
 <20250526102659.30225-3-mason-cw.chang@mediatek.com>
Message-ID: <trinity-319df51e-2ff3-42cd-8efd-139fda159824-1748448614514@trinity-msg-rest-gmx-gmx-live-6995845bd-wzmz6>

Hi Mason,

thank you for working on this.

I have not yet tested the series, but did not have the issue (which should be solved by it) reported [1].

So just my thoughts when looking through changes

> Gesendet: Montag, 26. Mai 2025 um 12:26
> Von: "Mason Chang" <mason-cw.chang at mediatek.com>
> Betreff: [PATCH 2/3] thermal/drivers/mediatek/lvts_thermal: add lvts commands and their sizes to driver data
>
> Add LVTS commands and their sizes to driver data in preparation for
> adding different commands.
> 
> Signed-off-by: Mason Chang <mason-cw.chang at mediatek.com>
> ---
>  drivers/thermal/mediatek/lvts_thermal.c | 65 ++++++++++++++++++++-----
>  1 file changed, 52 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
> index 7e4f56831..5b7bf29a7 100644
> --- a/drivers/thermal/mediatek/lvts_thermal.c
> +++ b/drivers/thermal/mediatek/lvts_thermal.c
> @@ -96,17 +96,6 @@
>  
>  #define LVTS_MINIMUM_THRESHOLD		20000
>  
> -static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 };
> -/*
> - * Write device mask: 0xC1030000
> - */
> -static const u32 default_init_cmds[] = {
> -	0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
> -	0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
> -	0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
> -	0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
> -};

could you please move this block in part 1 to the position used here in v2 to avoid deletion/adding again here?

Maybe magic numbers can be described a bit?

>  static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
>  static int golden_temp_offset;
>  
...
> @@ -1446,6 +1442,17 @@ static int lvts_resume(struct device *dev)
>  	return 0;
>  }
>  
> +static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 };
> +/*
> + * Write device mask: 0xC1030000
> + */
> +static const u32 default_init_cmds[] = {
> +	0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
> +	0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
> +	0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
> +	0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
> +};
> +
>  /*
>   * The MT8186 calibration data is stored as packed 3-byte little-endian
>   * values using a weird layout that makes sense only when viewed as a 32-bit
> @@ -1740,7 +1747,11 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {

regards Frank

[1] https://github.com/openwrt/openwrt/pull/18750#issuecomment-2877554514


From ckeepax at opensource.cirrus.com  Wed May 28 09:41:20 2025
From: ckeepax at opensource.cirrus.com (Charles Keepax)
Date: Wed, 28 May 2025 17:41:20 +0100
Subject: [PATCH 16/17] pinctrl: Constify static 'pinctrl_desc'
In-Reply-To: <20250528-pinctrl-const-desc-v1-16-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
 <20250528-pinctrl-const-desc-v1-16-76fe97899945@linaro.org>
Message-ID: <aDc8sEMh2UpcHzVr@opensource.cirrus.com>

On Wed, May 28, 2025 at 12:41:12PM +0200, Krzysztof Kozlowski wrote:
> The local static 'struct pinctrl_desc' is not modified, so can be made
> const for code safety.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> ---

For the cs42l43:

Reviewed-by: Charles Keepax <ckeepax at opensource.cirrus.com>

Thanks,
Charles


From florian.fainelli at broadcom.com  Wed May 28 09:45:49 2025
From: florian.fainelli at broadcom.com (Florian Fainelli)
Date: Wed, 28 May 2025 09:45:49 -0700
Subject: [PATCH 07/17] pinctrl: bcm: Constify static 'pinctrl_desc'
In-Reply-To: <20250528-pinctrl-const-desc-v1-7-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
 <20250528-pinctrl-const-desc-v1-7-76fe97899945@linaro.org>
Message-ID: <4474875f-bfd7-4f98-836c-0624f75c0f27@broadcom.com>

On 5/28/25 03:41, Krzysztof Kozlowski wrote:
> The local static 'struct pinctrl_desc' is not modified, so can be made
> const for code safety.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Reviewed-by: Florian Fainelli <florian.fainelli at broadcom.com>
-- 
Florian


From florian.fainelli at broadcom.com  Wed May 28 09:46:26 2025
From: florian.fainelli at broadcom.com (Florian Fainelli)
Date: Wed, 28 May 2025 09:46:26 -0700
Subject: [PATCH 08/17] pinctrl: bcm: cygnus-mux: Move fixed assignments to
 'pinctrl_desc' definition
In-Reply-To: <20250528-pinctrl-const-desc-v1-8-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
 <20250528-pinctrl-const-desc-v1-8-76fe97899945@linaro.org>
Message-ID: <0df6f879-f819-492b-b9c5-f91d544203ad@broadcom.com>

On 5/28/25 03:41, Krzysztof Kozlowski wrote:
> Assign 'struct pinctrl_desc' .npins member in definition to make clear
> that number of pins is fixed and have less code in the probe.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Reviewed-by: Florian Fainelli <florian.fainelli at broadcom.com>
-- 
Florian


From florian.fainelli at broadcom.com  Wed May 28 09:46:44 2025
From: florian.fainelli at broadcom.com (Florian Fainelli)
Date: Wed, 28 May 2025 09:46:44 -0700
Subject: [PATCH 09/17] pinctrl: bcm: cygnus-ns2: Move fixed assignments to
 'pinctrl_desc' definition
In-Reply-To: <20250528-pinctrl-const-desc-v1-9-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
 <20250528-pinctrl-const-desc-v1-9-76fe97899945@linaro.org>
Message-ID: <caa88dcb-148b-485d-ac77-b1ec9ca94f13@broadcom.com>

On 5/28/25 03:41, Krzysztof Kozlowski wrote:
> Assign 'struct pinctrl_desc' .npins member in definition to make clear
> that number of pins is fixed and have less code in the probe.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Reviewed-by: Florian Fainelli <florian.fainelli at broadcom.com>
-- 
Florian


From florian.fainelli at broadcom.com  Wed May 28 09:46:57 2025
From: florian.fainelli at broadcom.com (Florian Fainelli)
Date: Wed, 28 May 2025 09:46:57 -0700
Subject: [PATCH 10/17] pinctrl: bcm: cygnus-nsp: Move fixed assignments to
 'pinctrl_desc' definition
In-Reply-To: <20250528-pinctrl-const-desc-v1-10-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
 <20250528-pinctrl-const-desc-v1-10-76fe97899945@linaro.org>
Message-ID: <c92b138d-3c8a-4b14-978e-0274301768df@broadcom.com>

On 5/28/25 03:41, Krzysztof Kozlowski wrote:
> Assign 'struct pinctrl_desc' .npins member in definition to make clear
> that number of pins is fixed and have less code in the probe.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Reviewed-by: Florian Fainelli <florian.fainelli at broadcom.com>
-- 
Florian


From krzysztof.kozlowski at linaro.org  Wed May 28 10:55:07 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Wed, 28 May 2025 19:55:07 +0200
Subject: [PATCH 14/17] pinctrl: renesas: Move fixed assignments to
 'pinctrl_desc' definition
In-Reply-To: <CAMuHMdUGDf5n_Fg7pwiPumm95nPUXyH15geAy2ULwY3U+OtZJA@mail.gmail.com>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
 <20250528-pinctrl-const-desc-v1-14-76fe97899945@linaro.org>
 <CAMuHMdUGDf5n_Fg7pwiPumm95nPUXyH15geAy2ULwY3U+OtZJA@mail.gmail.com>
Message-ID: <b6b7fb61-878e-4407-b964-564efb3524b1@linaro.org>

On 28/05/2025 14:54, Geert Uytterhoeven wrote:
>>         .pmxops = &rzn1_pmx_ops,
>>         .confops = &rzn1_pinconf_ops,
>>         .owner = THIS_MODULE,
>> +       .pins = rzn1_pins,
>> +       .npins = ARRAY_SIZE(rzn1_pins),
>>  };
>>
>>  static int rzn1_pinctrl_parse_groups(struct device_node *np,
>> @@ -878,8 +880,6 @@ static int rzn1_pinctrl_probe(struct platform_device *pdev)
>>
>>         ipctl->dev = &pdev->dev;
>>         rzn1_pinctrl_desc.name = dev_name(&pdev->dev);
> 
> ... if you would replace this assignment by a hardcoded name
> like "pinctrl-rzn1".

I saw it, but this would not be equivalent. dev_name includes platform
bus id, e.g. pinctrl-rzn1.0 which might matter here - conflict of names.
Are you sure this would work fine?

Best regards,
Krzysztof


From andrew at codeconstruct.com.au  Wed May 28 17:39:06 2025
From: andrew at codeconstruct.com.au (Andrew Jeffery)
Date: Thu, 29 May 2025 10:09:06 +0930
Subject: [PATCH 05/17] pinctrl: aspeed: Constify static 'pinctrl_desc'
In-Reply-To: <20250528-pinctrl-const-desc-v1-5-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
	 <20250528-pinctrl-const-desc-v1-5-76fe97899945@linaro.org>
Message-ID: <af3edc0a454eecbe52608e0bc16d82b99be6bad7.camel@codeconstruct.com.au>

On Wed, 2025-05-28 at 12:41 +0200, Krzysztof Kozlowski wrote:
> The local static 'struct pinctrl_desc' is not modified, so can be made
> const for code safety.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Reviewed-by: Andrew Jeffery <andrew at codeconstruct.com.au>


From frank.li at vivo.com  Wed May 28 20:08:45 2025
From: frank.li at vivo.com (Yangtao Li)
Date: Wed, 28 May 2025 21:08:45 -0600
Subject: [PATCH v6] ufs: core: Add HID support
In-Reply-To: <20250523064604.800-1-tanghuan@vivo.com>
References: <20250523064604.800-1-tanghuan@vivo.com>
Message-ID: <20250529030846.2189709-1-frank.li@vivo.com>

Hi Huan,

LGTM!

Reviewed-by: Yangtao Li <frank.li at vivo.com>

Thx,
Yangtao


From mason-cw.chang at mediatek.com  Wed May 28 22:18:28 2025
From: mason-cw.chang at mediatek.com (Mason Chang)
Date: Thu, 29 May 2025 13:18:28 +0800
Subject: Aw: [PATCH 2/3] thermal/drivers/mediatek/lvts_thermal: add lvts
 commands and their sizes to driver data
In-Reply-To: <trinity-319df51e-2ff3-42cd-8efd-139fda159824-1748448614514@trinity-msg-rest-gmx-gmx-live-6995845bd-wzmz6>
References: <20250526102659.30225-1-mason-cw.chang@mediatek.com>
	 <20250526102659.30225-3-mason-cw.chang@mediatek.com>
	 <trinity-319df51e-2ff3-42cd-8efd-139fda159824-1748448614514@trinity-msg-rest-gmx-gmx-live-6995845bd-wzmz6>
Message-ID: <f0913ce328a2e501566dc311cf8e6c4539d492d3.camel@mediatek.com>


Hi Frank,

First of all, thank you for providing the link to the actual issue
case. This issue does not affect all MT7988 ICs. Based on the
information collected from users and production lines, we have found
that about 2% of the ICs show severe temperature anomalies without this
patch.

> Hi Mason,
> 
> thank you for working on this.
> 
> I have not yet tested the series, but did not have the issue (which
> should be solved by it) reported [1].
> 
> So just my thoughts when looking through changes
> 
> > Gesendet: Montag, 26. Mai 2025 um 12:26
> > Von: "Mason Chang" <mason-cw.chang at mediatek.com>
> > Betreff: [PATCH 2/3] thermal/drivers/mediatek/lvts_thermal: add
> > lvts commands and their sizes to driver data
> > 
> > Add LVTS commands and their sizes to driver data in preparation for
> > adding different commands.
> > 
> > Signed-off-by: Mason Chang <mason-cw.chang at mediatek.com>
> > ---
> > ?drivers/thermal/mediatek/lvts_thermal.c | 65 ++++++++++++++++++++-
> > ----
> > ?1 file changed, 52 insertions(+), 13 deletions(-)
> > 
> > diff --git a/drivers/thermal/mediatek/lvts_thermal.c
> > b/drivers/thermal/mediatek/lvts_thermal.c
> > index 7e4f56831..5b7bf29a7 100644
> > --- a/drivers/thermal/mediatek/lvts_thermal.c
> > +++ b/drivers/thermal/mediatek/lvts_thermal.c
> > @@ -96,17 +96,6 @@
> > 
> > ?#define LVTS_MINIMUM_THRESHOLD?????????????? 20000
> > 
> > -static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 };
> > -/*
> > - * Write device mask: 0xC1030000
> > - */
> > -static const u32 default_init_cmds[] = {
> > -???? 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
> > -???? 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
> > -???? 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
> > -???? 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
> > -};
> 
> could you please move this block in part 1 to the position used here
> in v2 to avoid deletion/adding again here?

To clearly separate changes and maintain the principle of minimal
modifications, you can see that in patch [1/3], the functions
lvts_ctrl_connect and lvts_ctrl_initialize call the commands.
Therefore, the commands cannot be moved to the part in patch [2/3].

> Maybe magic numbers can be described a bit?

This is just an initialization sequence, it cannot be adjusted.

> > ?static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
> > ?static int golden_temp_offset;
> > 
> ...
> > @@ -1446,6 +1442,17 @@ static int lvts_resume(struct device *dev)
> > ????? return 0;
> > ?}
> > 
> > +static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 };
> > +/*
> > + * Write device mask: 0xC1030000
> > + */
> > +static const u32 default_init_cmds[] = {
> > +???? 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
> > +???? 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
> > +???? 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
> > +???? 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
> > +};
> > +
> > ?/*
> > ? * The MT8186 calibration data is stored as packed 3-byte little-
> > endian
> > ? * values using a weird layout that makes sense only when viewed
> > as a 32-bit
> > @@ -1740,7 +1747,11 @@ static const struct lvts_ctrl_data
> > mt8195_lvts_ap_data_ctrl[] = {
>                                                                      
> regards Frank
> 
> [1]
> https://urldefense.com/v3/__https://github.com/openwrt/openwrt/pull/18750*issuecomment-2877554514__;Iw!!CTRNKA9wMg0ARbw!lVkeuQXjfQ1pWGSvoDCEmf0FEFQqqQDEb0ovZ5cSsNiXi7hud5epYUyl9xFjO6U7vukgfBY1Ue_-xJ78F5Qe7rw4UzwJyA$

Thank you for focusing on this issue!

Sincerely
Mason


From krzysztof.kozlowski at linaro.org  Wed May 28 23:26:21 2025
From: krzysztof.kozlowski at linaro.org (Krzysztof Kozlowski)
Date: Thu, 29 May 2025 08:26:21 +0200
Subject: [PATCH 02/17] pinctrl: Allow compile testing for K210, TB10X and
 ZYNQ
In-Reply-To: <20250528-pinctrl-const-desc-v1-2-76fe97899945@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
 <20250528-pinctrl-const-desc-v1-2-76fe97899945@linaro.org>
Message-ID: <6bb4f8f7-ef95-4f10-ad94-027fa18dada3@linaro.org>

On 28/05/2025 12:40, Krzysztof Kozlowski wrote:
> Pinctrl drivers for K210, TB10X and ZYNQ do not reference any machine
> headers, thus can be compile tested for increased build coverage.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> ---
>  drivers/pinctrl/Kconfig | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index 33db9104df178e5a3148b60c3c6bd153113385d3..77a5d13e899f8c5251987c2c74df1d05dbd59128 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -269,7 +269,7 @@ config PINCTRL_INGENIC
>  
>  config PINCTRL_K210
>  	bool "Pinctrl driver for the Canaan Kendryte K210 SoC"
> -	depends on RISCV && SOC_CANAAN_K210 && OF
> +	depends on RISCV && SOC_CANAAN_K210 && OF || COMPILE_TEST
>  	select GENERIC_PINMUX_FUNCTIONS
LKP reported here issue, so there will be v2 of this.


Best regards,
Krzysztof


From renata.nowacka at scalenook.pl  Thu May 29 00:51:03 2025
From: renata.nowacka at scalenook.pl (Renata Nowacka)
Date: Thu, 29 May 2025 07:51:03 GMT
Subject: =?UTF-8?Q?Ulga_na_sk=C5=82adki_ZUS?=
Message-ID: <20250529084500-0.1.gx.2225i.0.7p5ld3dofe@scalenook.pl>

Dzie? dobry, 

chcia?abym wskaza? Pa?stwu mo?liwo?? zarz?dzania benefitami w ?atwy spos?b, poprzez nasze intuicyjne narz?dzie, jakim jest karta lunchowa. 

Nasze karty oferuj? wygod?, oszcz?dno?ci i zdrowe wybory ?ywieniowe. Dofinansowanie posi?k?w jest korzystne dla obu stron. Karty lunch to dla pracodawcy realne oszcz?dno?ci w postaci zwolnienia z ZUS do 450 z? miesi?cznie na pracownika. 

Kart? mo?na do?adowa? dowoln? kwot?, a niewykorzystane ?rodki nie przepadaj?, lecz przechodz? na kolejny miesi?c. 

Mog? przedstawi? ofert?, kt?ra pozwoli zoptymalizowa? koszty i zapewni? pracownikom po??dany benefit?


Pozdrawiam
Renata Nowacka


From kuyo.chang at mediatek.com  Thu May 29 01:43:35 2025
From: kuyo.chang at mediatek.com (Kuyo Chang)
Date: Thu, 29 May 2025 16:43:35 +0800
Subject: [PATCH 1/1] stop_machine: Fix migrate_swap() vs. balance_push() racing
Message-ID: <20250529084614.885184-1-kuyo.chang@mediatek.com>

From: kuyo chang <kuyo.chang at mediatek.com>

Hi guys,

It encounters sporadic failures during CPU hotplug stress test.

[Syndrome]
The kernel log shows list add fail as below.

kmemleak: list_add corruption.
prev->next should be next (ffffff82812c7a00),
but was 0000000000000000. (prev=ffffff82812c3208).

kmemleak: kernel BUG at lib/list_debug.c:34!
kmemleak: Call trace:
kmemleak:  __list_add_valid_or_report+0x11c/0x144
kmemleak:  cpu_stop_queue_work+0x440/0x474
kmemleak:  stop_one_cpu_nowait+0xe4/0x138
kmemleak:  balance_push+0x1f4/0x3e4
kmemleak:  __schedule+0x1adc/0x23bc
kmemleak:  preempt_schedule_common+0x68/0xd0
kmemleak:  preempt_schedule+0x60/0x80
kmemleak:  _raw_spin_unlock_irqrestore+0x9c/0xa0
kmemleak:  scan_gray_list+0x220/0x3e4
kmemleak:  kmemleak_scan+0x410/0x740
kmemleak:  kmemleak_scan_thread+0xb0/0xdc
kmemleak:  kthread+0x2bc/0x494
kmemleak:  ret_from_fork+0x10/0x20

[Analysis]
In the failure case, by memory dump, we find
cpu_stopper.enabled = TRUE
but the wakeq is empty(the migrate/1 is at another wakeq)
static bool cpu_stop_queue_work(unsigned int cpu, struct cpu_stop_work *work)
{
...
..
	enabled = stopper->enabled;
	if (enabled)
		__cpu_stop_queue_work(stopper, work, &wakeq);
...
...
	wake_up_q(&wakeq);  -> wakeq is empty !!
	preempt_enable();
	return enabled;
}

Through analysis of the CPU0 call trace and memory dump

   CPU0: migration/0, pid: 43, priority: 99
   Native callstack:
	vmlinux  __kern_my_cpu_offset()           <arch/arm64/include/asm/percpu.h:40>
	vmlinux  ct_state_inc(incby=8)            <include/linux/context_tracking.h:137>
	vmlinux  rcu_momentary_eqs() + 72         <kernel/rcu/tree.c:375>
	vmlinux  multi_cpu_stop() + 316           <kernel/stop_machine.c:278>
	vmlinux  cpu_stopper_thread() + 676       <kernel/stop_machine.c:563>
	vmlinux  smpboot_thread_fn(data=0) + 1188 <kernel/smpboot.c:164>
	vmlinux  kthread() + 696                  <kernel/kthread.c:389>
	vmlinux  0xFFFFFFC08005941C()             <arch/arm64/kernel/entry.S:845>

  (struct migration_swap_arg *)0xFFFFFFC08FF87A40 (
    src_task = 0xFFFFFF80FF519740 ,
    dst_task = 0xFFFFFF802A579740 ,
    src_cpu = 0x0,
    dst_cpu = 0x1)

  (struct multi_stop_data)*    0xFFFFFFC08FF87930 = (
    fn = 0xFFFFFFC0802657F4 = migrate_swap_stop,
    data = 0xFFFFFFC08FF87A40
    num_threads = 0x2,
    active_cpus = cpu_bit_bitmap[1] -> (
      bits = (0x2)),
    state = MULTI_STOP_PREPARE = 0x1,
    thread_ack = (
      counter = 0x1))

By cpu mask memory dump:
  ((const struct cpumask *)&__cpu_online_mask) (
    bits = (0xFF))
  ((const struct cpumask *)&__cpu_dying_mask)  (
    bits = (0x2))
  ((const struct cpumask *)&__cpu_active_mask)(
    bits = (0xFD))
  ((const struct cpumask *)&__cpu_possible_mask) (
    bits = (0xFF))
->Imply cpu1 is dying & non-active

So, the potential race scenario is:

	CPU0							CPU1
	// doing migrate_swap(cpu0/cpu1)
	stop_two_cpus()
							  ...
							 // doing _cpu_down()
							      sched_cpu_deactivate()
								set_cpu_active(cpu, false);
								balance_push_set(cpu, true);
	cpu_stop_queue_two_works
	    __cpu_stop_queue_work(stopper1,...);
	    __cpu_stop_queue_work(stopper2,..);
	stop_cpus_in_progress -> true
		preempt_enable();
								...
							1st balance_push
							stop_one_cpu_nowait
							cpu_stop_queue_work
							__cpu_stop_queue_work
							list_add_tail  -> 1st add push_work
							wake_up_q(&wakeq);  -> "wakeq is empty. This implies that the stopper is at wakeq at migrate_swap."
	preempt_disable
	wake_up_q(&wakeq);
	        wake_up_process // wakeup migrate/0
		    try_to_wake_up
		        ttwu_queue
		            ttwu_queue_cond ->meet below case
		                if (cpu == smp_processor_id())
			         return false;
			ttwu_do_activate
			//migrate/0 wakeup done
		wake_up_process // wakeup migrate/1
	           try_to_wake_up
		    ttwu_queue
			ttwu_queue_cond
		        ttwu_queue_wakelist
			__ttwu_queue_wakelist
			__smp_call_single_queue
	preempt_enable();

							2nd balance_push
							stop_one_cpu_nowait
							cpu_stop_queue_work
							__cpu_stop_queue_work
							list_add_tail  -> 2nd add push_work, so the double list add is detected
							...
							...
							cpu1 get ipi, do sched_ttwu_pending, wakeup migrate/1

[Solution]
Maybe add queue status tracking in __cpu_stop_queue_work to avoid the corner case?
Or don't use ttwu_queu_wakelist while wakeup migrate?

Signed-off-by: kuyo chang <kuyo.chang at mediatek.com>
---
 include/linux/stop_machine.h |  7 +++++++
 kernel/stop_machine.c        | 12 +++++++++++-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/include/linux/stop_machine.h b/include/linux/stop_machine.h
index 3132262a404d..a0748416dd69 100644
--- a/include/linux/stop_machine.h
+++ b/include/linux/stop_machine.h
@@ -21,11 +21,18 @@ typedef int (*cpu_stop_fn_t)(void *arg);
 
 #ifdef CONFIG_SMP
 
+enum work_state {
+	WORK_INIT = 0,
+	WORK_QUEUE,
+	WORK_EXEC,
+};
+
 struct cpu_stop_work {
 	struct list_head	list;		/* cpu_stopper->works */
 	cpu_stop_fn_t		fn;
 	unsigned long		caller;
 	void			*arg;
+	enum work_state		state;
 	struct cpu_stop_done	*done;
 };
 
diff --git a/kernel/stop_machine.c b/kernel/stop_machine.c
index 5d2d0562115b..9ab6b07708e3 100644
--- a/kernel/stop_machine.c
+++ b/kernel/stop_machine.c
@@ -87,6 +87,7 @@ static void __cpu_stop_queue_work(struct cpu_stopper *stopper,
 {
 	list_add_tail(&work->list, &stopper->works);
 	wake_q_add(wakeq, stopper->thread);
+	work->state = WORK_QUEUE;
 }
 
 /* queue @work to @stopper.  if offline, @work is completed immediately */
@@ -385,7 +386,15 @@ int stop_two_cpus(unsigned int cpu1, unsigned int cpu2, cpu_stop_fn_t fn, void *
 bool stop_one_cpu_nowait(unsigned int cpu, cpu_stop_fn_t fn, void *arg,
 			struct cpu_stop_work *work_buf)
 {
-	*work_buf = (struct cpu_stop_work){ .fn = fn, .arg = arg, .caller = _RET_IP_, };
+	if (unlikely(work_buf->state == WORK_QUEUE))
+		return true;
+
+	*work_buf = (struct cpu_stop_work){
+	    .fn = fn,
+	    .arg = arg,
+	    .caller = _RET_IP_,
+	    .state = WORK_INIT
+	};
 	return cpu_stop_queue_work(cpu, work_buf);
 }
 
@@ -496,6 +505,7 @@ static void cpu_stopper_thread(unsigned int cpu)
 		work = list_first_entry(&stopper->works,
 					struct cpu_stop_work, list);
 		list_del_init(&work->list);
+		work->state = WORK_EXEC;
 	}
 	raw_spin_unlock_irq(&stopper->lock);
 
-- 
2.45.2



From patchwork-bot+netdevbpf at kernel.org  Thu May 29 03:30:30 2025
From: patchwork-bot+netdevbpf at kernel.org (patchwork-bot+netdevbpf at kernel.org)
Date: Thu, 29 May 2025 10:30:30 +0000
Subject: [PATCH] driver: net: ethernet: mtk_star_emac: fix suspend/resume
 issue
In-Reply-To: <20250528075351.593068-1-macpaul.lin@mediatek.com>
References: <20250528075351.593068-1-macpaul.lin@mediatek.com>
Message-ID: <174851463074.3219366.15490415696108954366.git-patchwork-notify@kernel.org>

Hello:

This patch was applied to netdev/net.git (main)
by Paolo Abeni <pabeni at redhat.com>:

On Wed, 28 May 2025 15:53:51 +0800 you wrote:
> From: Yanqing Wang <ot_yanqing.wang at mediatek.com>
> 
> Identify the cause of the suspend/resume hang: netif_carrier_off()
> is called during link state changes and becomes stuck while
> executing linkwatch_work().
> 
> To resolve this issue, call netif_device_detach() during the Ethernet
> suspend process to temporarily detach the network device from the
> kernel and prevent the suspend/resume hang.
> 
> [...]

Here is the summary with links:
  - driver: net: ethernet: mtk_star_emac: fix suspend/resume issue
    https://git.kernel.org/netdev/net/c/ba99c627aac8

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html




From pabeni at redhat.com  Thu May 29 03:52:32 2025
From: pabeni at redhat.com (Paolo Abeni)
Date: Thu, 29 May 2025 12:52:32 +0200
Subject: [net v2] net: wwan: t7xx: Fix napi rx poll issue
In-Reply-To: <20250528082827.4654-1-jinjian.song@fibocom.com>
References: <20250528082827.4654-1-jinjian.song@fibocom.com>
Message-ID: <6ae0ad5a-f560-43c5-a581-e4699634b65e@redhat.com>

On 5/28/25 10:28 AM, Jinjian Song wrote:
> When driver handles the napi rx polling requests, the netdev might
> have been released by the dellink logic triggered by the disconnect
> operation on user plane. However, in the logic of processing skb in
> polling, an invalid netdev is still being used, which causes a panic.
> 
> BUG: kernel NULL pointer dereference, address: 00000000000000f1
> Oops: 0000 [#1] PREEMPT SMP NOPTI
> RIP: 0010:dev_gro_receive+0x3a/0x620
> [...]
> Call Trace:
>  <IRQ>
>  ? __die_body+0x68/0xb0
>  ? page_fault_oops+0x379/0x3e0
>  ? exc_page_fault+0x4f/0xa0
>  ? asm_exc_page_fault+0x22/0x30
>  ? __pfx_t7xx_ccmni_recv_skb+0x10/0x10 [mtk_t7xx (HASH:1400 7)]
>  ? dev_gro_receive+0x3a/0x620
>  napi_gro_receive+0xad/0x170
>  t7xx_ccmni_recv_skb+0x48/0x70 [mtk_t7xx (HASH:1400 7)]
>  t7xx_dpmaif_napi_rx_poll+0x590/0x800 [mtk_t7xx (HASH:1400 7)]
>  net_rx_action+0x103/0x470
>  irq_exit_rcu+0x13a/0x310
>  sysvec_apic_timer_interrupt+0x56/0x90
>  </IRQ>
> 
> Fixes: 5545b7b9f294 ("net: wwan: t7xx: Add NAPI support")
> Signed-off-by: Jinjian Song <jinjian.song at fibocom.com>
> ---
>  drivers/net/wwan/t7xx/t7xx_netdev.c | 19 ++++++++++---------
>  1 file changed, 10 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/net/wwan/t7xx/t7xx_netdev.c b/drivers/net/wwan/t7xx/t7xx_netdev.c
> index 91fa082e9cab..48007384c030 100644
> --- a/drivers/net/wwan/t7xx/t7xx_netdev.c
> +++ b/drivers/net/wwan/t7xx/t7xx_netdev.c
> @@ -172,7 +172,7 @@ static void t7xx_ccmni_start(struct t7xx_ccmni_ctrl *ctlb)
>  	int i;
>  
>  	for (i = 0; i < ctlb->nic_dev_num; i++) {
> -		ccmni = ctlb->ccmni_inst[i];
> +		ccmni = READ_ONCE(ctlb->ccmni_inst[i]);
>  		if (!ccmni)
>  			continue;
>  
> @@ -192,7 +192,7 @@ static void t7xx_ccmni_pre_stop(struct t7xx_ccmni_ctrl *ctlb)
>  	int i;
>  
>  	for (i = 0; i < ctlb->nic_dev_num; i++) {
> -		ccmni = ctlb->ccmni_inst[i];
> +		ccmni = READ_ONCE(ctlb->ccmni_inst[i]);
>  		if (!ccmni)
>  			continue;
>  
> @@ -210,7 +210,7 @@ static void t7xx_ccmni_post_stop(struct t7xx_ccmni_ctrl *ctlb)
>  		t7xx_ccmni_disable_napi(ctlb);
>  
>  	for (i = 0; i < ctlb->nic_dev_num; i++) {
> -		ccmni = ctlb->ccmni_inst[i];
> +		ccmni = READ_ONCE(ctlb->ccmni_inst[i]);
>  		if (!ccmni)
>  			continue;
>  
> @@ -302,7 +302,7 @@ static int t7xx_ccmni_wwan_newlink(void *ctxt, struct net_device *dev, u32 if_id
>  	ccmni->ctlb = ctlb;
>  	ccmni->dev = dev;
>  	atomic_set(&ccmni->usage, 0);
> -	ctlb->ccmni_inst[if_id] = ccmni;
> +	WRITE_ONCE(ctlb->ccmni_inst[if_id], ccmni);
>  
>  	ret = register_netdevice(dev);
>  	if (ret)
> @@ -321,9 +321,10 @@ static void t7xx_ccmni_wwan_dellink(void *ctxt, struct net_device *dev, struct l
>  	if (if_id >= ARRAY_SIZE(ctlb->ccmni_inst))
>  		return;
>  
> -	if (WARN_ON(ctlb->ccmni_inst[if_id] != ccmni))
> +	if (WARN_ON(READ_ONCE(ctlb->ccmni_inst[if_id]) != ccmni))

READ_ONCE is only needed when the the lock protecting ctlb->ccmni_inst
is not held. It's not needed here, and likely in pre/post stop operations.

/P



From lorenzo at kernel.org  Thu May 29 08:52:36 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Thu, 29 May 2025 17:52:36 +0200
Subject: [PATCH net 0/2] net: airoha: Fix IPv6 hw acceleration
Message-ID: <20250529-airoha-flowtable-ipv6-fix-v1-0-7c7e53ae0854@kernel.org>

Fix IPv6 hw acceleration in bridge mode resolving ib2 and
airoha_foe_mac_info_common overwrite in
airoha_ppe_foe_commit_subflow_entry routine.
Introduce UPDMEM source-mac table used to set source mac address for
L3 IPv6 hw accelerated traffic.

---
Lorenzo Bianconi (2):
      net: airoha: Initialize PPE UPDMEM source-mac table
      net: airoha: Fix IPv6 hw acceleration in bridge mode

 drivers/net/ethernet/airoha/airoha_eth.c  |  2 ++
 drivers/net/ethernet/airoha/airoha_eth.h  |  1 +
 drivers/net/ethernet/airoha/airoha_ppe.c  | 52 ++++++++++++++++++++++++-------
 drivers/net/ethernet/airoha/airoha_regs.h | 10 ++++++
 4 files changed, 53 insertions(+), 12 deletions(-)
---
base-commit: 27eab4c644236a9324084a70fe79e511cbd07393
change-id: 20250529-airoha-flowtable-ipv6-fix-976a1ce80e7d

Best regards,
-- 
Lorenzo Bianconi <lorenzo at kernel.org>



From lorenzo at kernel.org  Thu May 29 08:52:37 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Thu, 29 May 2025 17:52:37 +0200
Subject: [PATCH net 1/2] net: airoha: Initialize PPE UPDMEM source-mac
 table
In-Reply-To: <20250529-airoha-flowtable-ipv6-fix-v1-0-7c7e53ae0854@kernel.org>
References: <20250529-airoha-flowtable-ipv6-fix-v1-0-7c7e53ae0854@kernel.org>
Message-ID: <20250529-airoha-flowtable-ipv6-fix-v1-1-7c7e53ae0854@kernel.org>

UPDMEM source-mac table is a key-value map used to store devices mac
addresses according to the port identifier. UPDMEM source mac table is
used during IPv6 traffic hw acceleration since PPE entries, for space
constraints, do not contain the full source mac address but just the
identifier in the UPDMEM source-mac table.

Fixes: 00a7678310fe ("net: airoha: Introduce flowtable offload support")
Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 drivers/net/ethernet/airoha/airoha_eth.c  |  2 ++
 drivers/net/ethernet/airoha/airoha_eth.h  |  1 +
 drivers/net/ethernet/airoha/airoha_ppe.c  | 26 +++++++++++++++++++++++++-
 drivers/net/ethernet/airoha/airoha_regs.h | 10 ++++++++++
 4 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index d1d3b854361e443d414876f79f59b3c64cbcbe16..a7ec609d64dee9c8e901c7eb650bb3fe144ee00a 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -84,6 +84,8 @@ static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
 	val = (addr[3] << 16) | (addr[4] << 8) | addr[5];
 	airoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), val);
 	airoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), val);
+
+	airoha_ppe_init_upd_mem(port);
 }
 
 static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr,
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index b815697302bfdf2a6d115a9bbbbadc05462dbadb..a970b789cf232c316e5ea27b0146493bf91c3767 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -614,6 +614,7 @@ void airoha_ppe_check_skb(struct airoha_ppe *ppe, struct sk_buff *skb,
 int airoha_ppe_setup_tc_block_cb(struct net_device *dev, void *type_data);
 int airoha_ppe_init(struct airoha_eth *eth);
 void airoha_ppe_deinit(struct airoha_eth *eth);
+void airoha_ppe_init_upd_mem(struct airoha_gdm_port *port);
 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe,
 						  u32 hash);
 void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash,
diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
index 12d32c92717a6b4ba74728ec02bb2e166d4d9407..a783f16980e6b7fdb69cec7ff09883a9c83d42d5 100644
--- a/drivers/net/ethernet/airoha/airoha_ppe.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe.c
@@ -223,6 +223,7 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
 	int dsa_port = airoha_get_dsa_port(&dev);
 	struct airoha_foe_mac_info_common *l2;
 	u32 qdata, ports_pad, val;
+	u8 smac_id = 0xf;
 
 	memset(hwe, 0, sizeof(*hwe));
 
@@ -257,6 +258,8 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
 		 */
 		if (airhoa_is_lan_gdm_port(port))
 			val |= AIROHA_FOE_IB2_FAST_PATH;
+
+		smac_id = port->id;
 	}
 
 	if (is_multicast_ether_addr(data->eth.h_dest))
@@ -291,7 +294,7 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
 		hwe->ipv4.l2.src_mac_lo =
 			get_unaligned_be16(data->eth.h_source + 4);
 	} else {
-		l2->src_mac_hi = FIELD_PREP(AIROHA_FOE_MAC_SMAC_ID, 0xf);
+		l2->src_mac_hi = FIELD_PREP(AIROHA_FOE_MAC_SMAC_ID, smac_id);
 	}
 
 	if (data->vlan.num) {
@@ -1238,6 +1241,27 @@ void airoha_ppe_check_skb(struct airoha_ppe *ppe, struct sk_buff *skb,
 	airoha_ppe_foe_insert_entry(ppe, skb, hash);
 }
 
+void airoha_ppe_init_upd_mem(struct airoha_gdm_port *port)
+{
+	struct airoha_eth *eth = port->qdma->eth;
+	struct net_device *dev = port->dev;
+	const u8 *addr = dev->dev_addr;
+	u32 val;
+
+	val = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
+	airoha_fe_wr(eth, REG_UPDMEM_DATA(0), val);
+	airoha_fe_wr(eth, REG_UPDMEM_CTRL(0),
+		     FIELD_PREP(PPE_UPDMEM_ADDR_MASK, port->id) |
+		     PPE_UPDMEM_WR_MASK | PPE_UPDMEM_REQ_MASK);
+
+	val = (addr[0] << 8) | addr[1];
+	airoha_fe_wr(eth, REG_UPDMEM_DATA(0), val);
+	airoha_fe_wr(eth, REG_UPDMEM_CTRL(0),
+		     FIELD_PREP(PPE_UPDMEM_ADDR_MASK, port->id) |
+		     FIELD_PREP(PPE_UPDMEM_OFFSET_MASK, 1) |
+		     PPE_UPDMEM_WR_MASK | PPE_UPDMEM_REQ_MASK);
+}
+
 int airoha_ppe_init(struct airoha_eth *eth)
 {
 	struct airoha_ppe *ppe;
diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
index d931530fc96fb00ada36a6ad37fa295865a6f0a8..04187eb40ec674ec5a4ccfc968bb4bd579a53095 100644
--- a/drivers/net/ethernet/airoha/airoha_regs.h
+++ b/drivers/net/ethernet/airoha/airoha_regs.h
@@ -313,6 +313,16 @@
 #define REG_PPE_RAM_BASE(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x320)
 #define REG_PPE_RAM_ENTRY(_m, _n)		(REG_PPE_RAM_BASE(_m) + ((_n) << 2))
 
+#define REG_UPDMEM_CTRL(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x370)
+#define PPE_UPDMEM_ACK_MASK			BIT(31)
+#define PPE_UPDMEM_ADDR_MASK			GENMASK(11, 8)
+#define PPE_UPDMEM_OFFSET_MASK			GENMASK(7, 4)
+#define PPE_UPDMEM_SEL_MASK			GENMASK(3, 2)
+#define PPE_UPDMEM_WR_MASK			BIT(1)
+#define PPE_UPDMEM_REQ_MASK			BIT(0)
+
+#define REG_UPDMEM_DATA(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x374)
+
 #define REG_FE_GDM_TX_OK_PKT_CNT_H(_n)		(GDM_BASE(_n) + 0x280)
 #define REG_FE_GDM_TX_OK_BYTE_CNT_H(_n)		(GDM_BASE(_n) + 0x284)
 #define REG_FE_GDM_TX_ETH_PKT_CNT_H(_n)		(GDM_BASE(_n) + 0x288)

-- 
2.49.0



From lorenzo at kernel.org  Thu May 29 08:52:38 2025
From: lorenzo at kernel.org (Lorenzo Bianconi)
Date: Thu, 29 May 2025 17:52:38 +0200
Subject: [PATCH net 2/2] net: airoha: Fix IPv6 hw acceleration in bridge
 mode
In-Reply-To: <20250529-airoha-flowtable-ipv6-fix-v1-0-7c7e53ae0854@kernel.org>
References: <20250529-airoha-flowtable-ipv6-fix-v1-0-7c7e53ae0854@kernel.org>
Message-ID: <20250529-airoha-flowtable-ipv6-fix-v1-2-7c7e53ae0854@kernel.org>

ib2 and airoha_foe_mac_info_common have not the same offsets in
airoha_foe_bridge and airoha_foe_ipv6 structures. Fix IPv6 hw
acceleration in bridge mode resolving ib2 and airoha_foe_mac_info_common
overwrite in airoha_ppe_foe_commit_subflow_entry routine. Moreover, set
AIROHA_FOE_MAC_SMAC_ID to 0xf in airoha_ppe_foe_commit_subflow_entry()
to configure the PPE module to keep original source mac address of the
bridged packets.

Fixes: cd53f622611f ("net: airoha: Add L2 hw acceleration support")
Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
 drivers/net/ethernet/airoha/airoha_ppe.c | 26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
index a783f16980e6b7fdb69cec7ff09883a9c83d42d5..d5dbcb556f2b10b23ebbdd32a66a3c4f32cfb460 100644
--- a/drivers/net/ethernet/airoha/airoha_ppe.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe.c
@@ -639,7 +639,6 @@ airoha_ppe_foe_commit_subflow_entry(struct airoha_ppe *ppe,
 	u32 mask = AIROHA_FOE_IB1_BIND_PACKET_TYPE | AIROHA_FOE_IB1_BIND_UDP;
 	struct airoha_foe_entry *hwe_p, hwe;
 	struct airoha_flow_table_entry *f;
-	struct airoha_foe_mac_info *l2;
 	int type;
 
 	hwe_p = airoha_ppe_foe_get_entry(ppe, hash);
@@ -656,18 +655,23 @@ airoha_ppe_foe_commit_subflow_entry(struct airoha_ppe *ppe,
 
 	memcpy(&hwe, hwe_p, sizeof(*hwe_p));
 	hwe.ib1 = (hwe.ib1 & mask) | (e->data.ib1 & ~mask);
-	l2 = &hwe.bridge.l2;
-	memcpy(l2, &e->data.bridge.l2, sizeof(*l2));
 
 	type = FIELD_GET(AIROHA_FOE_IB1_BIND_PACKET_TYPE, hwe.ib1);
-	if (type == PPE_PKT_TYPE_IPV4_HNAPT)
-		memcpy(&hwe.ipv4.new_tuple, &hwe.ipv4.orig_tuple,
-		       sizeof(hwe.ipv4.new_tuple));
-	else if (type >= PPE_PKT_TYPE_IPV6_ROUTE_3T &&
-		 l2->common.etype == ETH_P_IP)
-		l2->common.etype = ETH_P_IPV6;
-
-	hwe.bridge.ib2 = e->data.bridge.ib2;
+	if (type >= PPE_PKT_TYPE_IPV6_ROUTE_3T) {
+		memcpy(&hwe.ipv6.l2, &e->data.bridge.l2, sizeof(hwe.ipv6.l2));
+		hwe.ipv6.ib2 = e->data.bridge.ib2;
+		/* keep origianl source mac address */
+		hwe.ipv6.l2.src_mac_hi = FIELD_PREP(AIROHA_FOE_MAC_SMAC_ID,
+						    0xf);
+	} else {
+		memcpy(&hwe.bridge.l2, &e->data.bridge.l2,
+		       sizeof(hwe.bridge.l2));
+		hwe.bridge.ib2 = e->data.bridge.ib2;
+		if (type == PPE_PKT_TYPE_IPV4_HNAPT)
+			memcpy(&hwe.ipv4.new_tuple, &hwe.ipv4.orig_tuple,
+			       sizeof(hwe.ipv4.new_tuple));
+	}
+
 	hwe.bridge.data = e->data.bridge.data;
 	airoha_ppe_foe_commit_entry(ppe, &hwe, hash);
 

-- 
2.49.0



From nfraprado at collabora.com  Thu May 29 08:53:08 2025
From: nfraprado at collabora.com (=?utf-8?B?TsOtY29sYXMgRi4gUi4gQS4=?= Prado)
Date: Thu, 29 May 2025 11:53:08 -0400
Subject: [PATCH v2 1/3] dt-bindings: mfd: mediatek: mt6397: Add
 #sound-dai-cells property
In-Reply-To: <20250522-independent-ginger-bullfrog-4552d1@kuoka>
References: <20250514-mt8395-dtb-errors-v2-0-d67b9077c59a@collabora.com>
 <20250514-mt8395-dtb-errors-v2-1-d67b9077c59a@collabora.com>
 <20250522-independent-ginger-bullfrog-4552d1@kuoka>
Message-ID: <cee1e8bc-f4b0-49b9-a67b-2f54382c3d8e@notapiano>

On Thu, May 22, 2025 at 09:52:07AM +0200, Krzysztof Kozlowski wrote:
> On Wed, May 14, 2025 at 10:19:56AM GMT, Julien Massot wrote:
> > The 'mt6359.dtsi' file already uses the '#sound-dai-cells' property.
> > Add the corresponding property to the binding to fix the following
> > dtb-check error:
> > 
> > mediatek/mt8395-radxa-nio-12l.dtb: pmic: '#sound-dai-cells', 'mt6359rtc' do not match any of the regexes: 'pinctrl-[0-9]+'
> > from schema $id: http://devicetree.org/schemas/mfd/mediatek,mt6397.yaml#
> 
> If this is a random drive-by, would be fine, but if that's your platform
> which you should know, then I expect this to be a real reason instead
> something which can easily be rejected with: what if DTS is wrong?
> 
> I could not find the ASoC driver for that compatible and quick glance to
> MFD shown me no usage of dai cells, so you need proper explanation here.
> 
> Especially, that there is a subnode audio-codec, so adding dai cells to
> the parent node feels just wrong. One is wrong - either subnode or
> parent is a codec.

The driver is sound/soc/codecs/mt6359.c, which defines 2 DAIs. It's currently
probed by the MFD through the driver name, hence the parent MFD device is the
one used to register the audio component.

The right fix would probably be to add the compatible both to the ASoC and the
MFD drivers, and then move the dai-cells to the sound subnode in DT.

Thanks,
N?colas


From tjeznach at rivosinc.com  Thu May 29 13:46:17 2025
From: tjeznach at rivosinc.com (Tomasz Jeznach)
Date: Thu, 29 May 2025 13:46:17 -0700
Subject: [PATCH 3/7] iommu: Remove ops.pgsize_bitmap from drivers that
 don't use it
In-Reply-To: <3-v1-7c5282b0c334+2db-iommu_rm_ops_pgsize_jgg@nvidia.com>
References: <0-v1-7c5282b0c334+2db-iommu_rm_ops_pgsize_jgg@nvidia.com>
 <3-v1-7c5282b0c334+2db-iommu_rm_ops_pgsize_jgg@nvidia.com>
Message-ID: <aDjHmR7ZVTbsSITO@tjeznach.ba.rivosinc.com>

On Tue, Apr 29, 2025 at 11:34:13AM -0300, Jason Gunthorpe wrote:
> These drivers all set the domain->pgsize_bitmap in their
> domain_alloc_paging() functions, so the ops value is never used. Delete
> it.
> 
> Signed-off-by: Jason Gunthorpe <jgg at nvidia.com>
> ---
>  drivers/iommu/apple-dart.c       | 1 -
>  drivers/iommu/intel/iommu.c      | 1 -
>  drivers/iommu/iommufd/selftest.c | 1 -
>  drivers/iommu/riscv/iommu.c      | 1 -
>  drivers/iommu/virtio-iommu.c     | 6 ++----
>  5 files changed, 2 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
> index bb57092ca90110..2d0d31ba28860a 100644
> --- a/drivers/iommu/riscv/iommu.c
> +++ b/drivers/iommu/riscv/iommu.c
> @@ -1533,7 +1533,6 @@ static void riscv_iommu_release_device(struct device *dev)
>  }
>  
>  static const struct iommu_ops riscv_iommu_ops = {
> -	.pgsize_bitmap = SZ_4K,
>  	.of_xlate = riscv_iommu_of_xlate,
>  	.identity_domain = &riscv_iommu_identity_domain,
>  	.blocked_domain = &riscv_iommu_blocking_domain,

Reviewed-by: Tomasz Jeznach <tjeznach at rivosinc.com> # for RISC-V

Sorry for the delayed response.
- Tomasz


From jinjian.song at fibocom.com  Thu May 29 20:16:48 2025
From: jinjian.song at fibocom.com (Jinjian Song)
Date: Fri, 30 May 2025 11:16:48 +0800
Subject: [net v3] net: wwan: t7xx: Fix napi rx poll issue
Message-ID: <20250530031648.5592-1-jinjian.song@fibocom.com>

When driver handles the napi rx polling requests, the netdev might
have been released by the dellink logic triggered by the disconnect
operation on user plane. However, in the logic of processing skb in
polling, an invalid netdev is still being used, which causes a panic.

BUG: kernel NULL pointer dereference, address: 00000000000000f1
Oops: 0000 [#1] PREEMPT SMP NOPTI
RIP: 0010:dev_gro_receive+0x3a/0x620
[...]
Call Trace:
 <IRQ>
 ? __die_body+0x68/0xb0
 ? page_fault_oops+0x379/0x3e0
 ? exc_page_fault+0x4f/0xa0
 ? asm_exc_page_fault+0x22/0x30
 ? __pfx_t7xx_ccmni_recv_skb+0x10/0x10 [mtk_t7xx (HASH:1400 7)]
 ? dev_gro_receive+0x3a/0x620
 napi_gro_receive+0xad/0x170
 t7xx_ccmni_recv_skb+0x48/0x70 [mtk_t7xx (HASH:1400 7)]
 t7xx_dpmaif_napi_rx_poll+0x590/0x800 [mtk_t7xx (HASH:1400 7)]
 net_rx_action+0x103/0x470
 irq_exit_rcu+0x13a/0x310
 sysvec_apic_timer_interrupt+0x56/0x90
 </IRQ>

Fixes: 5545b7b9f294 ("net: wwan: t7xx: Add NAPI support")
Signed-off-by: Jinjian Song <jinjian.song at fibocom.com>
---
v3:
 * Only Use READ_ONCE/WRITE_ONCE when the lock protecting ctlb->ccmni_inst
   is not held.
---
 drivers/net/wwan/t7xx/t7xx_netdev.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/net/wwan/t7xx/t7xx_netdev.c b/drivers/net/wwan/t7xx/t7xx_netdev.c
index 91fa082e9cab..fc0a7cb181df 100644
--- a/drivers/net/wwan/t7xx/t7xx_netdev.c
+++ b/drivers/net/wwan/t7xx/t7xx_netdev.c
@@ -302,7 +302,7 @@ static int t7xx_ccmni_wwan_newlink(void *ctxt, struct net_device *dev, u32 if_id
 	ccmni->ctlb = ctlb;
 	ccmni->dev = dev;
 	atomic_set(&ccmni->usage, 0);
-	ctlb->ccmni_inst[if_id] = ccmni;
+	WRITE_ONCE(ctlb->ccmni_inst[if_id], ccmni);
 
 	ret = register_netdevice(dev);
 	if (ret)
@@ -324,6 +324,7 @@ static void t7xx_ccmni_wwan_dellink(void *ctxt, struct net_device *dev, struct l
 	if (WARN_ON(ctlb->ccmni_inst[if_id] != ccmni))
 		return;
 
+	WRITE_ONCE(ctlb->ccmni_inst[if_id], NULL);
 	unregister_netdevice(dev);
 }
 
@@ -419,7 +420,7 @@ static void t7xx_ccmni_recv_skb(struct t7xx_ccmni_ctrl *ccmni_ctlb, struct sk_bu
 
 	skb_cb = T7XX_SKB_CB(skb);
 	netif_id = skb_cb->netif_idx;
-	ccmni = ccmni_ctlb->ccmni_inst[netif_id];
+	ccmni = READ_ONCE(ccmni_ctlb->ccmni_inst[netif_id]);
 	if (!ccmni) {
 		dev_kfree_skb(skb);
 		return;
@@ -441,7 +442,7 @@ static void t7xx_ccmni_recv_skb(struct t7xx_ccmni_ctrl *ccmni_ctlb, struct sk_bu
 
 static void t7xx_ccmni_queue_tx_irq_notify(struct t7xx_ccmni_ctrl *ctlb, int qno)
 {
-	struct t7xx_ccmni *ccmni = ctlb->ccmni_inst[0];
+	struct t7xx_ccmni *ccmni = READ_ONCE(ctlb->ccmni_inst[0]);
 	struct netdev_queue *net_queue;
 
 	if (netif_running(ccmni->dev) && atomic_read(&ccmni->usage) > 0) {
@@ -453,7 +454,7 @@ static void t7xx_ccmni_queue_tx_irq_notify(struct t7xx_ccmni_ctrl *ctlb, int qno
 
 static void t7xx_ccmni_queue_tx_full_notify(struct t7xx_ccmni_ctrl *ctlb, int qno)
 {
-	struct t7xx_ccmni *ccmni = ctlb->ccmni_inst[0];
+	struct t7xx_ccmni *ccmni = READ_ONCE(ctlb->ccmni_inst[0]);
 	struct netdev_queue *net_queue;
 
 	if (atomic_read(&ccmni->usage) > 0) {
@@ -471,7 +472,7 @@ static void t7xx_ccmni_queue_state_notify(struct t7xx_pci_dev *t7xx_dev,
 	if (ctlb->md_sta != MD_STATE_READY)
 		return;
 
-	if (!ctlb->ccmni_inst[0]) {
+	if (!READ_ONCE(ctlb->ccmni_inst[0])) {
 		dev_warn(&t7xx_dev->pdev->dev, "No netdev registered yet\n");
 		return;
 	}
-- 
2.34.1



From kyrie.wu at mediatek.com  Fri May 30 00:45:27 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Fri, 30 May 2025 15:45:27 +0800
Subject: [PATCH v5 02/12] media: dt-bindings: mediatek,jpeg: Add mediatek, mt8196-jpgenc compatible
In-Reply-To: <20250530074537.26338-1-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
Message-ID: <20250530074537.26338-3-kyrie.wu@mediatek.com>

Compared to the previous generation IC, the MT8196 uses SMMU
instead of IOMMU and supports features such as dynamic voltage
and frequency scaling. Therefore, add "mediatek,mt8196-jpgenc"
compatible to the binding document.

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 .../bindings/media/mediatek,mt8195-jpegenc.yaml           | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml
index 596186497b68..e2d772ea0fb0 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml
@@ -14,7 +14,9 @@ description:
 
 properties:
   compatible:
-    const: mediatek,mt8195-jpgenc
+    enum:
+      - mediatek,mt8195-jpgenc
+      - mediatek,mt8196-jpgenc
 
   power-domains:
     maxItems: 1
@@ -44,7 +46,9 @@ patternProperties:
 
     properties:
       compatible:
-        const: mediatek,mt8195-jpgenc-hw
+        enum:
+          - mediatek,mt8195-jpgenc-hw
+          - mediatek,mt8196-jpgenc-hw
 
       reg:
         maxItems: 1
-- 
2.46.0



From kyrie.wu at mediatek.com  Fri May 30 00:45:25 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Fri, 30 May 2025 15:45:25 +0800
Subject: [PATCH v5 00/12] Enable jpeg enc & dec multi-hardwares for MT8196
Message-ID: <20250530074537.26338-1-kyrie.wu@mediatek.com>

This series adds support for mt8196 multi-hardwares jpeg enc & dec,
by first adding mt8196 jpegdec and jpegenc compatible to install
kernel driver. Add smmu setting to support smmu and iommu at the
same time.
Secondly refactor buffer and clock setting to support multi-hw jpeg
working.
Lastly, fix some bugs, including resolution change handleing, stop
streaming sw flow and others.

This series has been tested with MT8196 tast test.
Encoding and decoding worked for this chip.

Patches 1-3 Adds jpeg encoder and decoder compatible.
Patches 4 add jpeg smmu sid setting.
Patches 5 fix jpeg hw count setting to support different chips.
Patches 6 refactor jpeg buffer payload setting to handle buffer
size bug while resolution changed.
Patches 7 reconstruct jpeg dst buffer layout.
Patches 8 fix multi-core stop streaming flow
Patches 9 refactor multi-core clk suspend/resume setting
Patches 10 fix decoding buffer number setting timing issue
Patches 11 refactor decoding resolution change operation
Patches 12 fix remove buffer operation

---
This series patches dependent on:
[1]
https://patchwork.linuxtv.org/project/linux-media/patch/20250424090824.5309-1-jianhua.lin at mediatek.com/

Changes compared with v4:
--fix kernel robot build errors for patch 4.
--add reviewer for patch 1 and patch 2.

Changes compared with v3:
--change patch subject of jpeg encoder and decoder compatible.

Changes compared with v2:
--refactor smmu sid setting function interface
--Some modifications for patch v2's review comments.

Changes compared with v1:
--refine jpeg dt-bindings for MT8196
--optimize software code to manage jpeg HW count
--refactor smmu sid setting function interface
--Some modifications for patch v1's review comments.

Kyrie Wu (12):
  media: dt-bindings: mediatek,jpeg: Add mediatek, mt8196-jpgdec
    compatible
  media: dt-bindings: mediatek,jpeg: Add mediatek, mt8196-jpgenc
    compatible
  media: mediatek: jpeg: add jpeg compatible
  media: mediatek: jpeg: add jpeg smmu sid setting
  media: mediatek: jpeg: fix jpeg hw count setting
  media: mediatek: jpeg: refactor jpeg buffer payload setting
  media: mediatek: jpeg: refactor jpeg dst buffer layout
  media: mediatek: jpeg: fix stop streaming flow for multi-core
  media: mediatek: jpeg: refactor multi-core clk suspend and resume
    setting
  media: mediatek: jpeg: fix decoding buffer number setting timing issue
  media: mediatek: jpeg: refactor decoding resolution change operation
  media: mediatek: jpeg: fix remove buffer operation for multi-core

 .../media/mediatek,mt8195-jpegdec.yaml        |   8 +-
 .../media/mediatek,mt8195-jpegenc.yaml        |   8 +-
 .../platform/mediatek/jpeg/mtk_jpeg_core.c    | 169 +++++++++++++-----
 .../platform/mediatek/jpeg/mtk_jpeg_core.h    |  21 ++-
 .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c  | 112 +++++++++++-
 .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c  | 112 +++++++++++-
 6 files changed, 377 insertions(+), 53 deletions(-)

-- 
2.46.0



From kyrie.wu at mediatek.com  Fri May 30 00:45:28 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Fri, 30 May 2025 15:45:28 +0800
Subject: [PATCH v5 03/12] media: mediatek: jpeg: add jpeg compatible
In-Reply-To: <20250530074537.26338-1-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
Message-ID: <20250530074537.26338-4-kyrie.wu@mediatek.com>

Add jpeg dec and enc compatible for mt8196

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 .../platform/mediatek/jpeg/mtk_jpeg_core.c    | 34 +++++++++++++++++++
 .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c  |  3 ++
 .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c  |  3 ++
 3 files changed, 40 insertions(+)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 7eb12449b63a..e89ccb8c904c 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1918,6 +1918,19 @@ static struct mtk_jpeg_variant mtk8195_jpegenc_drvdata = {
 	.jpeg_worker = mtk_jpegenc_worker,
 };
 
+static struct mtk_jpeg_variant mtk8196_jpegenc_drvdata = {
+	.formats = mtk_jpeg_enc_formats,
+	.num_formats = MTK_JPEG_ENC_NUM_FORMATS,
+	.qops = &mtk_jpeg_enc_qops,
+	.m2m_ops = &mtk_jpeg_multicore_enc_m2m_ops,
+	.dev_name = "mtk-jpeg-enc",
+	.ioctl_ops = &mtk_jpeg_enc_ioctl_ops,
+	.out_q_default_fourcc = V4L2_PIX_FMT_YUYV,
+	.cap_q_default_fourcc = V4L2_PIX_FMT_JPEG,
+	.multi_core = true,
+	.jpeg_worker = mtk_jpegenc_worker,
+};
+
 static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata = {
 	.formats = mtk_jpeg_dec_formats,
 	.num_formats = MTK_JPEG_DEC_NUM_FORMATS,
@@ -1931,6 +1944,19 @@ static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata = {
 	.jpeg_worker = mtk_jpegdec_worker,
 };
 
+static const struct mtk_jpeg_variant mtk8196_jpegdec_drvdata = {
+	.formats = mtk_jpeg_dec_formats,
+	.num_formats = MTK_JPEG_DEC_NUM_FORMATS,
+	.qops = &mtk_jpeg_dec_qops,
+	.m2m_ops = &mtk_jpeg_multicore_dec_m2m_ops,
+	.dev_name = "mtk-jpeg-dec",
+	.ioctl_ops = &mtk_jpeg_dec_ioctl_ops,
+	.out_q_default_fourcc = V4L2_PIX_FMT_JPEG,
+	.cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M,
+	.multi_core = true,
+	.jpeg_worker = mtk_jpegdec_worker,
+};
+
 static const struct of_device_id mtk_jpeg_match[] = {
 	{
 		.compatible = "mediatek,mt8173-jpgdec",
@@ -1952,6 +1978,14 @@ static const struct of_device_id mtk_jpeg_match[] = {
 		.compatible = "mediatek,mt8195-jpgdec",
 		.data = &mtk8195_jpegdec_drvdata,
 	},
+	{
+		.compatible = "mediatek,mt8196-jpgenc",
+		.data = &mtk8196_jpegenc_drvdata,
+	},
+	{
+		.compatible = "mediatek,mt8196-jpgdec",
+		.data = &mtk8196_jpegdec_drvdata,
+	},
 	{},
 };
 
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index e78e1d11093c..20553bf541df 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -45,6 +45,9 @@ static const struct of_device_id mtk_jpegdec_hw_ids[] = {
 	{
 		.compatible = "mediatek,mt8195-jpgdec-hw",
 	},
+	{
+		.compatible = "mediatek,mt8196-jpgdec-hw",
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_jpegdec_hw_ids);
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
index 9ab27aee302a..69c95113f205 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
@@ -52,6 +52,9 @@ static const struct of_device_id mtk_jpegenc_drv_ids[] = {
 	{
 		.compatible = "mediatek,mt8195-jpgenc-hw",
 	},
+	{
+		.compatible = "mediatek,mt8196-jpgenc-hw",
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_jpegenc_drv_ids);
-- 
2.46.0



From kyrie.wu at mediatek.com  Fri May 30 00:45:26 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Fri, 30 May 2025 15:45:26 +0800
Subject: [PATCH v5 01/12] media: dt-bindings: mediatek,jpeg: Add mediatek, mt8196-jpgdec compatible
In-Reply-To: <20250530074537.26338-1-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
Message-ID: <20250530074537.26338-2-kyrie.wu@mediatek.com>

Compared to the previous generation IC, the MT8196 uses SMMU
instead of IOMMU and supports features such as dynamic voltage
and frequency scaling. Therefore, add "mediatek,mt8196-jpgdec"
compatible to the binding document.

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
 .../bindings/media/mediatek,mt8195-jpegdec.yaml           | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
index e5448c60e3eb..28a9a9bfdbf8 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
@@ -14,7 +14,9 @@ description:
 
 properties:
   compatible:
-    const: mediatek,mt8195-jpgdec
+    enum:
+      - mediatek,mt8195-jpgdec
+      - mediatek,mt8196-jpgdec
 
   power-domains:
     maxItems: 1
@@ -44,7 +46,9 @@ patternProperties:
 
     properties:
       compatible:
-        const: mediatek,mt8195-jpgdec-hw
+        enum:
+          - mediatek,mt8195-jpgdec-hw
+          - mediatek,mt8196-jpgdec-hw
 
       reg:
         maxItems: 1
-- 
2.46.0



From kyrie.wu at mediatek.com  Fri May 30 00:45:29 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Fri, 30 May 2025 15:45:29 +0800
Subject: [PATCH v5 04/12] media: mediatek: jpeg: add jpeg smmu sid setting
In-Reply-To: <20250530074537.26338-1-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
Message-ID: <20250530074537.26338-5-kyrie.wu@mediatek.com>

Add a configuration to set jpeg dec & enc smmu sid

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 .../platform/mediatek/jpeg/mtk_jpeg_core.c    | 37 +++++++++++++++++++
 .../platform/mediatek/jpeg/mtk_jpeg_core.h    | 15 ++++++++
 .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c  | 23 ++++++++++++
 .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c  | 23 ++++++++++++
 4 files changed, 98 insertions(+)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index e89ccb8c904c..ea890f01fa9e 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -15,6 +15,7 @@
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/regmap.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <media/v4l2-event.h>
@@ -1584,6 +1585,20 @@ static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg_dev *jpeg)
 	return IRQ_HANDLED;
 }
 
+static void mtk_jpeg_enc_set_smmu_sid(struct mtk_jpegenc_comp_dev *jpeg)
+{
+	struct mtk_jpeg_dev *mjpeg = jpeg->master_dev;
+
+	if (!mjpeg->variant->support_smmu || !jpeg->smmu_regmap)
+		return;
+
+	regmap_update_bits(jpeg->smmu_regmap, JPEG_ENC_SMMU_SID,
+			   JPG_REG_GUSER_ID_MASK <<
+			   JPG_REG_ENC_GUSER_ID_SHIFT,
+			   JPG_REG_GUSER_ID_ENC_SID <<
+			   JPG_REG_ENC_GUSER_ID_SHIFT);
+}
+
 static void mtk_jpegenc_worker(struct work_struct *work)
 {
 	struct mtk_jpegenc_comp_dev *comp_jpeg[MTK_JPEGENC_HW_MAX];
@@ -1655,6 +1670,9 @@ static void mtk_jpegenc_worker(struct work_struct *work)
 	jpeg_dst_buf->frame_num = ctx->total_frame_num;
 	ctx->total_frame_num++;
 	mtk_jpeg_enc_reset(comp_jpeg[hw_id]->reg_base);
+
+	mtk_jpeg_enc_set_smmu_sid(comp_jpeg[hw_id]);
+
 	mtk_jpeg_set_enc_dst(ctx,
 			     comp_jpeg[hw_id]->reg_base,
 			     &dst_buf->vb2_buf);
@@ -1679,6 +1697,20 @@ static void mtk_jpegenc_worker(struct work_struct *work)
 	v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
 }
 
+static void mtk_jpeg_dec_set_smmu_sid(struct mtk_jpegdec_comp_dev *jpeg)
+{
+	struct mtk_jpeg_dev *mjpeg = jpeg->master_dev;
+
+	if (!mjpeg->variant->support_smmu || !jpeg->smmu_regmap)
+		return;
+
+	regmap_update_bits(jpeg->smmu_regmap, JPEG_DEC_SMMU_SID,
+			   JPG_REG_GUSER_ID_MASK <<
+			   JPG_REG_DEC_GUSER_ID_SHIFT,
+			   JPG_REG_GUSER_ID_DEC_SID <<
+			   JPG_REG_DEC_GUSER_ID_SHIFT);
+}
+
 static void mtk_jpegdec_worker(struct work_struct *work)
 {
 	struct mtk_jpeg_ctx *ctx = container_of(work, struct mtk_jpeg_ctx,
@@ -1771,6 +1803,9 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 	spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags);
 	ctx->total_frame_num++;
 	mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base);
+
+	mtk_jpeg_dec_set_smmu_sid(comp_jpeg[hw_id]);
+
 	mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base,
 				jpeg->variant->support_34bit,
 				&jpeg_src_buf->dec_param,
@@ -1929,6 +1964,7 @@ static struct mtk_jpeg_variant mtk8196_jpegenc_drvdata = {
 	.cap_q_default_fourcc = V4L2_PIX_FMT_JPEG,
 	.multi_core = true,
 	.jpeg_worker = mtk_jpegenc_worker,
+	.support_smmu = true,
 };
 
 static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata = {
@@ -1955,6 +1991,7 @@ static const struct mtk_jpeg_variant mtk8196_jpegdec_drvdata = {
 	.cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M,
 	.multi_core = true,
 	.jpeg_worker = mtk_jpegdec_worker,
+	.support_smmu = true,
 };
 
 static const struct of_device_id mtk_jpeg_match[] = {
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
index 02ed0ed5b736..46899512a5e6 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
@@ -11,6 +11,7 @@
 
 #include <linux/clk.h>
 #include <linux/interrupt.h>
+#include <linux/mfd/syscon.h>
 #include <media/v4l2-ctrls.h>
 #include <media/v4l2-device.h>
 #include <media/v4l2-fh.h>
@@ -34,6 +35,14 @@
 
 #define MTK_JPEG_MAX_EXIF_SIZE	(64 * 1024)
 
+#define JPEG_DEC_SMMU_SID				0
+#define JPEG_ENC_SMMU_SID				0
+#define JPG_REG_GUSER_ID_MASK			0x7
+#define JPG_REG_GUSER_ID_DEC_SID		0x4
+#define JPG_REG_GUSER_ID_ENC_SID		0x5
+#define JPG_REG_DEC_GUSER_ID_SHIFT		8
+#define JPG_REG_ENC_GUSER_ID_SHIFT		4
+
 #define MTK_JPEG_ADDR_MASK GENMASK(1, 0)
 
 /**
@@ -65,6 +74,7 @@ enum mtk_jpeg_ctx_state {
  * @multi_core:		mark jpeg hw is multi_core or not
  * @jpeg_worker:		jpeg dec or enc worker
  * @support_34bit:	flag to check support for 34-bit DMA address
+ * @support_smmu:	flag to check if support smmu
  */
 struct mtk_jpeg_variant {
 	struct clk_bulk_data *clks;
@@ -82,6 +92,7 @@ struct mtk_jpeg_variant {
 	bool multi_core;
 	void (*jpeg_worker)(struct work_struct *work);
 	bool support_34bit;
+	bool support_smmu;
 };
 
 struct mtk_jpeg_src_buf {
@@ -150,6 +161,7 @@ struct mtk_jpegdec_clk {
  * @hw_param:		jpeg encode hw parameters
  * @hw_state:		record hw state
  * @hw_lock:		spinlock protecting the hw device resource
+ * @smmu_regmap:	SMMU registers mapping
  */
 struct mtk_jpegenc_comp_dev {
 	struct device *dev;
@@ -163,6 +175,7 @@ struct mtk_jpegenc_comp_dev {
 	enum mtk_jpeg_hw_state hw_state;
 	/* spinlock protecting the hw device resource */
 	spinlock_t hw_lock;
+	struct regmap *smmu_regmap;
 };
 
 /**
@@ -177,6 +190,7 @@ struct mtk_jpegenc_comp_dev {
  * @hw_param:			jpeg decode hw parameters
  * @hw_state:			record hw state
  * @hw_lock:			spinlock protecting hw
+ * @smmu_regmap:		SMMU registers mapping
  */
 struct mtk_jpegdec_comp_dev {
 	struct device *dev;
@@ -190,6 +204,7 @@ struct mtk_jpegdec_comp_dev {
 	enum mtk_jpeg_hw_state hw_state;
 	/* spinlock protecting the hw device resource */
 	spinlock_t hw_lock;
+	struct regmap *smmu_regmap;
 };
 
 /**
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index 20553bf541df..2538c49f8eda 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -616,6 +616,25 @@ static int mtk_jpegdec_hw_init_irq(struct mtk_jpegdec_comp_dev *dev)
 	return 0;
 }
 
+static int mtk_jpegdec_smmu_init(struct mtk_jpegdec_comp_dev *dev)
+{
+	struct mtk_jpeg_dev *master_dev = dev->master_dev;
+
+	if (!master_dev->variant->support_smmu)
+		return 0;
+
+	dev->smmu_regmap =
+		syscon_regmap_lookup_by_phandle(dev->plat_dev->dev.of_node,
+						"mediatek,smmu-config");
+	if (IS_ERR(dev->smmu_regmap)) {
+		return dev_err_probe(dev->dev, PTR_ERR(dev->smmu_regmap),
+				     "mmap smmu_base failed(%ld)\n",
+				     PTR_ERR(dev->smmu_regmap));
+	}
+
+	return 0;
+}
+
 static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
 {
 	struct mtk_jpegdec_clk *jpegdec_clk;
@@ -668,6 +687,10 @@ static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
 	master_dev->reg_decbase[i] = dev->reg_base;
 	dev->master_dev = master_dev;
 
+	ret = mtk_jpegdec_smmu_init(dev);
+	if (ret)
+		return ret;
+
 	platform_set_drvdata(pdev, dev);
 	pm_runtime_enable(&pdev->dev);
 
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
index 69c95113f205..fc7b7d404253 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
@@ -340,6 +340,25 @@ static int mtk_jpegenc_hw_init_irq(struct mtk_jpegenc_comp_dev *dev)
 	return 0;
 }
 
+static int mtk_jpegenc_smmu_init(struct mtk_jpegenc_comp_dev *dev)
+{
+	struct mtk_jpeg_dev *master_dev = dev->master_dev;
+
+	if (!master_dev->variant->support_smmu)
+		return 0;
+
+	dev->smmu_regmap =
+		syscon_regmap_lookup_by_phandle(dev->plat_dev->dev.of_node,
+						"mediatek,smmu-config");
+	if (IS_ERR(dev->smmu_regmap)) {
+		return dev_err_probe(dev->dev, PTR_ERR(dev->smmu_regmap),
+				     "mmap smmu_base failed(%ld)\n",
+				     PTR_ERR(dev->smmu_regmap));
+	}
+
+	return 0;
+}
+
 static int mtk_jpegenc_hw_probe(struct platform_device *pdev)
 {
 	struct mtk_jpegenc_clk *jpegenc_clk;
@@ -390,6 +409,10 @@ static int mtk_jpegenc_hw_probe(struct platform_device *pdev)
 	master_dev->reg_encbase[i] = dev->reg_base;
 	dev->master_dev = master_dev;
 
+	ret = mtk_jpegenc_smmu_init(dev);
+	if (ret)
+		return ret;
+
 	platform_set_drvdata(pdev, dev);
 	pm_runtime_enable(&pdev->dev);
 
-- 
2.46.0



From kyrie.wu at mediatek.com  Fri May 30 00:45:30 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Fri, 30 May 2025 15:45:30 +0800
Subject: [PATCH v5 05/12] media: mediatek: jpeg: fix jpeg hw count setting
In-Reply-To: <20250530074537.26338-1-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
Message-ID: <20250530074537.26338-6-kyrie.wu@mediatek.com>

1. different IC has different hw core;
2. use a parameter to set jpeg hw count.

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c   | 8 ++++----
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h   | 2 ++
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 1 +
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 1 +
 4 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index ea890f01fa9e..0074d1edb534 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1469,7 +1469,7 @@ static int mtk_jpegenc_get_hw(struct mtk_jpeg_ctx *ctx)
 	int i;
 
 	spin_lock_irqsave(&jpeg->hw_lock, flags);
-	for (i = 0; i < MTK_JPEGENC_HW_MAX; i++) {
+	for (i = 0; i < jpeg->max_hw_count; i++) {
 		comp_jpeg = jpeg->enc_hw_dev[i];
 		if (comp_jpeg->hw_state == MTK_JPEG_HW_IDLE) {
 			hw_id = i;
@@ -1516,7 +1516,7 @@ static int mtk_jpegdec_get_hw(struct mtk_jpeg_ctx *ctx)
 	int i;
 
 	spin_lock_irqsave(&jpeg->hw_lock, flags);
-	for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++) {
+	for (i = 0; i < jpeg->max_hw_count; i++) {
 		comp_jpeg = jpeg->dec_hw_dev[i];
 		if (comp_jpeg->hw_state == MTK_JPEG_HW_IDLE) {
 			hw_id = i;
@@ -1613,7 +1613,7 @@ static void mtk_jpegenc_worker(struct work_struct *work)
 		jpeg_work);
 	struct mtk_jpeg_dev *jpeg = ctx->jpeg;
 
-	for (i = 0; i < MTK_JPEGENC_HW_MAX; i++)
+	for (i = 0; i < jpeg->max_hw_count; i++)
 		comp_jpeg[i] = jpeg->enc_hw_dev[i];
 	i = 0;
 
@@ -1725,7 +1725,7 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 	struct mtk_jpeg_fb fb;
 	unsigned long flags;
 
-	for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++)
+	for (i = 0; i < jpeg->max_hw_count; i++)
 		comp_jpeg[i] = jpeg->dec_hw_dev[i];
 	i = 0;
 
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
index 46899512a5e6..655dc9c3280c 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
@@ -227,6 +227,7 @@ struct mtk_jpegdec_comp_dev {
  * @reg_decbase:	jpg decode register base addr
  * @dec_hw_dev:	jpg decode hardware device
  * @hw_index:		jpg hw index
+ * @max_hw_count:	jpeg hw-core count
  */
 struct mtk_jpeg_dev {
 	struct mutex		lock;
@@ -249,6 +250,7 @@ struct mtk_jpeg_dev {
 	void __iomem *reg_decbase[MTK_JPEGDEC_HW_MAX];
 	struct mtk_jpegdec_comp_dev *dec_hw_dev[MTK_JPEGDEC_HW_MAX];
 	atomic_t hw_index;
+	u32 max_hw_count;
 };
 
 /**
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index 2538c49f8eda..2200f3b628dc 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -686,6 +686,7 @@ static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
 	master_dev->dec_hw_dev[i] = dev;
 	master_dev->reg_decbase[i] = dev->reg_base;
 	dev->master_dev = master_dev;
+	master_dev->max_hw_count++;
 
 	ret = mtk_jpegdec_smmu_init(dev);
 	if (ret)
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
index fc7b7d404253..4c264c14ad83 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
@@ -408,6 +408,7 @@ static int mtk_jpegenc_hw_probe(struct platform_device *pdev)
 	master_dev->enc_hw_dev[i] = dev;
 	master_dev->reg_encbase[i] = dev->reg_base;
 	dev->master_dev = master_dev;
+	master_dev->max_hw_count++;
 
 	ret = mtk_jpegenc_smmu_init(dev);
 	if (ret)
-- 
2.46.0



From kyrie.wu at mediatek.com  Fri May 30 00:45:35 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Fri, 30 May 2025 15:45:35 +0800
Subject: [PATCH v5 10/12] media: mediatek: jpeg: fix decoding buffer number setting timing issue
In-Reply-To: <20250530074537.26338-1-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
Message-ID: <20250530074537.26338-11-kyrie.wu@mediatek.com>

move decoding buffer increase code into spinlock
protecting aera for multi-core

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c   | 9 +++------
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 1 +
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 1 +
 3 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index c1d2de92f125..795916206c7c 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1782,7 +1782,6 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 
 	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
 	jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(&src_buf->vb2_buf);
-	jpeg_dst_buf = mtk_jpeg_vb2_to_srcbuf(&dst_buf->vb2_buf);
 
 	if (mtk_jpeg_check_resolution_change(ctx,
 					     &jpeg_src_buf->dec_param)) {
@@ -1791,11 +1790,6 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 		goto getbuf_fail;
 	}
 
-	jpeg_src_buf->curr_ctx = ctx;
-	jpeg_src_buf->frame_num = ctx->total_frame_num;
-	jpeg_dst_buf->curr_ctx = ctx;
-	jpeg_dst_buf->frame_num = ctx->total_frame_num;
-
 	mtk_jpegdec_set_hw_param(ctx, hw_id, src_buf, dst_buf);
 	ret = pm_runtime_resume_and_get(comp_jpeg[hw_id]->dev);
 	if (ret < 0) {
@@ -1820,6 +1814,9 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 			      msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC));
 
 	spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags);
+	jpeg_dst_buf = mtk_jpeg_vb2_to_srcbuf(&dst_buf->vb2_buf);
+	jpeg_dst_buf->curr_ctx = ctx;
+	jpeg_dst_buf->frame_num = ctx->total_frame_num;
 	ctx->total_frame_num++;
 	mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base);
 
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index db2afc5151ad..da753a636eaa 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -516,6 +516,7 @@ static void mtk_jpegdec_put_buf(struct mtk_jpegdec_comp_dev *jpeg)
 				v4l2_m2m_buf_done(&tmp_dst_done_buf->b,
 						  VB2_BUF_STATE_DONE);
 				ctx->last_done_frame_num++;
+				break;
 			}
 		}
 	}
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
index 27da2a9922a6..5e8a5cb4850e 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
@@ -245,6 +245,7 @@ static void mtk_jpegenc_put_buf(struct mtk_jpegenc_comp_dev *jpeg)
 				v4l2_m2m_buf_done(&tmp_dst_done_buf->b,
 						  VB2_BUF_STATE_DONE);
 				ctx->last_done_frame_num++;
+				break;
 			}
 		}
 	}
-- 
2.46.0



From kyrie.wu at mediatek.com  Fri May 30 00:45:33 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Fri, 30 May 2025 15:45:33 +0800
Subject: [PATCH v5 08/12] media: mediatek: jpeg: fix stop streaming flow for multi-core
In-Reply-To: <20250530074537.26338-1-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
Message-ID: <20250530074537.26338-9-kyrie.wu@mediatek.com>

1. For multi-core jpegdec, the all hws may run at the same time,
if one hw decoded firstly, the function of mtk_jpeg_dec_stop_streaming
would be called, but others input buffers are decoding, this will
cause some running buffers to be buffer done, causing errors;
2. add a parameter to calculate the decoding buffer counts, it
wil decrease to 0 until the all buffers decoded and the
mtk_jpeg_dec_stop_streaming could continue to be executed.

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 .../media/platform/mediatek/jpeg/mtk_jpeg_core.c | 16 ++++++++++++++++
 .../media/platform/mediatek/jpeg/mtk_jpeg_core.h |  2 ++
 .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c     |  9 +++++++++
 .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c     |  9 +++++++++
 4 files changed, 36 insertions(+)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 7e3509be6f69..1d3df1230191 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -861,8 +861,12 @@ static struct vb2_v4l2_buffer *mtk_jpeg_buf_remove(struct mtk_jpeg_ctx *ctx,
 static void mtk_jpeg_enc_stop_streaming(struct vb2_queue *q)
 {
 	struct mtk_jpeg_ctx *ctx = vb2_get_drv_priv(q);
+	struct mtk_jpeg_dev *jpeg = ctx->jpeg;
 	struct vb2_v4l2_buffer *vb;
 
+	if (jpeg->variant->multi_core)
+		wait_event(jpeg->hw_wq, (atomic_read(&ctx->buf_list_cnt) == 0));
+
 	while ((vb = mtk_jpeg_buf_remove(ctx, q->type)))
 		v4l2_m2m_buf_done(vb, VB2_BUF_STATE_ERROR);
 }
@@ -870,6 +874,7 @@ static void mtk_jpeg_enc_stop_streaming(struct vb2_queue *q)
 static void mtk_jpeg_dec_stop_streaming(struct vb2_queue *q)
 {
 	struct mtk_jpeg_ctx *ctx = vb2_get_drv_priv(q);
+	struct mtk_jpeg_dev *jpeg = ctx->jpeg;
 	struct vb2_v4l2_buffer *vb;
 
 	/*
@@ -877,6 +882,9 @@ static void mtk_jpeg_dec_stop_streaming(struct vb2_queue *q)
 	 * Before STREAMOFF, we still have to return the old resolution and
 	 * subsampling. Update capture queue when the stream is off.
 	 */
+	if (jpeg->variant->multi_core)
+		wait_event(jpeg->hw_wq, (atomic_read(&ctx->buf_list_cnt) == 0));
+
 	if (ctx->state == MTK_JPEG_SOURCE_CHANGE &&
 	    V4L2_TYPE_IS_CAPTURE(q->type)) {
 		struct mtk_jpeg_src_buf *src_buf;
@@ -1186,6 +1194,7 @@ static int mtk_jpeg_open(struct file *file)
 	v4l2_fh_init(&ctx->fh, vfd);
 	file->private_data = &ctx->fh;
 	v4l2_fh_add(&ctx->fh);
+	atomic_set(&ctx->buf_list_cnt, 0);
 
 	ctx->jpeg = jpeg;
 	ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(jpeg->m2m_dev, ctx,
@@ -1568,6 +1577,11 @@ static int mtk_jpegdec_set_hw_param(struct mtk_jpeg_ctx *ctx,
 	return 0;
 }
 
+static void jpeg_buf_queue_inc(struct mtk_jpeg_ctx *ctx)
+{
+	atomic_inc(&ctx->buf_list_cnt);
+}
+
 static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg_dev *jpeg)
 {
 	struct mtk_jpeg_ctx *ctx;
@@ -1693,6 +1707,7 @@ static void mtk_jpegenc_worker(struct work_struct *work)
 			     &src_buf->vb2_buf);
 	mtk_jpeg_set_enc_params(ctx, comp_jpeg[hw_id]->reg_base);
 	mtk_jpeg_enc_start(comp_jpeg[hw_id]->reg_base);
+	jpeg_buf_queue_inc(ctx);
 	v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
 	spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags);
 
@@ -1825,6 +1840,7 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 				&bs,
 				&fb);
 	mtk_jpeg_dec_start(comp_jpeg[hw_id]->reg_base);
+	jpeg_buf_queue_inc(ctx);
 	v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
 	spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags);
 
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
index 186cd1862028..6e8304680393 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
@@ -303,6 +303,7 @@ struct mtk_jpeg_q_data {
  * @dst_done_queue:		encoded frame buffer queue
  * @done_queue_lock:		encoded frame operation spinlock
  * @last_done_frame_num:	the last encoded frame number
+ * @buf_list_cnt:		the frame buffer count own by jpeg driver
  */
 struct mtk_jpeg_ctx {
 	struct mtk_jpeg_dev		*jpeg;
@@ -321,6 +322,7 @@ struct mtk_jpeg_ctx {
 	/* spinlock protecting the encode done buffer */
 	spinlock_t done_queue_lock;
 	u32 last_done_frame_num;
+	atomic_t buf_list_cnt;
 };
 
 #endif /* _MTK_JPEG_CORE_H */
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index 2200f3b628dc..2e6da8617484 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -522,6 +522,11 @@ static void mtk_jpegdec_put_buf(struct mtk_jpegdec_comp_dev *jpeg)
 	spin_unlock_irqrestore(&ctx->done_queue_lock, flags);
 }
 
+static void jpeg_buf_queue_dec(struct mtk_jpeg_ctx *ctx)
+{
+	atomic_dec(&ctx->buf_list_cnt);
+}
+
 static void mtk_jpegdec_timeout_work(struct work_struct *work)
 {
 	enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
@@ -530,9 +535,11 @@ static void mtk_jpegdec_timeout_work(struct work_struct *work)
 			     job_timeout_work.work);
 	struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev;
 	struct vb2_v4l2_buffer *src_buf, *dst_buf;
+	struct mtk_jpeg_ctx *ctx;
 
 	src_buf = cjpeg->hw_param.src_buffer;
 	dst_buf = cjpeg->hw_param.dst_buffer;
+	ctx = cjpeg->hw_param.curr_ctx;
 	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
 
 	mtk_jpeg_dec_reset(cjpeg->reg_base);
@@ -543,6 +550,7 @@ static void mtk_jpegdec_timeout_work(struct work_struct *work)
 	wake_up(&master_jpeg->hw_wq);
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegdec_put_buf(cjpeg);
+	jpeg_buf_queue_dec(ctx);
 }
 
 static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
@@ -583,6 +591,7 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
 	buf_state = VB2_BUF_STATE_DONE;
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegdec_put_buf(jpeg);
+	jpeg_buf_queue_dec(ctx);
 	pm_runtime_put(ctx->jpeg->dev);
 	clk_disable_unprepare(jpeg->jdec_clk.clks->clk);
 
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
index 4c264c14ad83..ff73393a2417 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
@@ -251,6 +251,11 @@ static void mtk_jpegenc_put_buf(struct mtk_jpegenc_comp_dev *jpeg)
 	spin_unlock_irqrestore(&ctx->done_queue_lock, flags);
 }
 
+static void jpeg_buf_queue_dec(struct mtk_jpeg_ctx *ctx)
+{
+	atomic_dec(&ctx->buf_list_cnt);
+}
+
 static void mtk_jpegenc_timeout_work(struct work_struct *work)
 {
 	struct delayed_work *dly_work = to_delayed_work(work);
@@ -261,9 +266,11 @@ static void mtk_jpegenc_timeout_work(struct work_struct *work)
 	struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev;
 	enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
 	struct vb2_v4l2_buffer *src_buf, *dst_buf;
+	struct mtk_jpeg_ctx *ctx;
 
 	src_buf = cjpeg->hw_param.src_buffer;
 	dst_buf = cjpeg->hw_param.dst_buffer;
+	ctx = cjpeg->hw_param.curr_ctx;
 	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
 
 	mtk_jpeg_enc_reset(cjpeg->reg_base);
@@ -274,6 +281,7 @@ static void mtk_jpegenc_timeout_work(struct work_struct *work)
 	wake_up(&master_jpeg->hw_wq);
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegenc_put_buf(cjpeg);
+	jpeg_buf_queue_dec(ctx);
 }
 
 static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
@@ -307,6 +315,7 @@ static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
 	buf_state = VB2_BUF_STATE_DONE;
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegenc_put_buf(jpeg);
+	jpeg_buf_queue_dec(ctx);
 	pm_runtime_put(ctx->jpeg->dev);
 	clk_disable_unprepare(jpeg->venc_clk.clks->clk);
 
-- 
2.46.0



From kyrie.wu at mediatek.com  Fri May 30 00:45:31 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Fri, 30 May 2025 15:45:31 +0800
Subject: [PATCH v5 06/12] media: mediatek: jpeg: refactor jpeg buffer payload setting
In-Reply-To: <20250530074537.26338-1-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
Message-ID: <20250530074537.26338-7-kyrie.wu@mediatek.com>

1. for multi-core jpegdec:
   core0: |<-------- decoding buffer0 and resolution changed to smaller
   core1:  |<-------- decoding buffer1
   core0:   |<- handling resolution changing
   core0:    |<- vb2_set_plane_payload
2. the payload size is changed on the step of set format. Because core1
is running and streaming has not been stopped, the format cannot be
set again, resulting in no change in the payload size.
3. at this time, the payload size is bigger than buffer length,
it will print a warnning call trace
4. set payload size must less than buffer length

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 .../platform/mediatek/jpeg/mtk_jpeg_core.c     | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 0074d1edb534..52d59bb5c9ad 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -720,10 +720,22 @@ static int mtk_jpeg_buf_prepare(struct vb2_buffer *vb)
 		plane_fmt = q_data->pix_mp.plane_fmt[i];
 		if (ctx->enable_exif &&
 		    q_data->fmt->fourcc == V4L2_PIX_FMT_JPEG)
-			vb2_set_plane_payload(vb, i, plane_fmt.sizeimage +
-					      MTK_JPEG_MAX_EXIF_SIZE);
+			if (vb->planes[i].length > (plane_fmt.sizeimage +
+			    MTK_JPEG_MAX_EXIF_SIZE))
+				vb2_set_plane_payload(vb, i,
+						      plane_fmt.sizeimage +
+						      MTK_JPEG_MAX_EXIF_SIZE);
+			else
+				vb2_set_plane_payload(vb, i,
+						      vb->planes[i].length);
+
 		else
-			vb2_set_plane_payload(vb, i,  plane_fmt.sizeimage);
+			if (vb->planes[i].length > plane_fmt.sizeimage)
+				vb2_set_plane_payload(vb, i,
+						      plane_fmt.sizeimage);
+			else
+				vb2_set_plane_payload(vb, i,
+						      vb->planes[i].length);
 	}
 
 	return 0;
-- 
2.46.0



From kyrie.wu at mediatek.com  Fri May 30 00:45:34 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Fri, 30 May 2025 15:45:34 +0800
Subject: [PATCH v5 09/12] media: mediatek: jpeg: refactor multi-core clk suspend and resume setting
In-Reply-To: <20250530074537.26338-1-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
Message-ID: <20250530074537.26338-10-kyrie.wu@mediatek.com>

refactor jpeg clk suspend and resume setting for multi-core

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 .../platform/mediatek/jpeg/mtk_jpeg_core.c    | 28 +++----
 .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c  | 75 ++++++++++++++++++-
 .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c  | 75 ++++++++++++++++++-
 3 files changed, 151 insertions(+), 27 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 1d3df1230191..c1d2de92f125 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1126,6 +1126,9 @@ static void mtk_jpeg_clk_on(struct mtk_jpeg_dev *jpeg)
 {
 	int ret;
 
+	if (jpeg->variant->multi_core)
+		return;
+
 	ret = clk_bulk_prepare_enable(jpeg->variant->num_clks,
 				      jpeg->variant->clks);
 	if (ret)
@@ -1134,6 +1137,9 @@ static void mtk_jpeg_clk_on(struct mtk_jpeg_dev *jpeg)
 
 static void mtk_jpeg_clk_off(struct mtk_jpeg_dev *jpeg)
 {
+	if (jpeg->variant->multi_core)
+		return;
+
 	clk_bulk_disable_unprepare(jpeg->variant->num_clks,
 				   jpeg->variant->clks);
 }
@@ -1677,13 +1683,6 @@ static void mtk_jpegenc_worker(struct work_struct *work)
 		goto enc_end;
 	}
 
-	ret = clk_prepare_enable(comp_jpeg[hw_id]->venc_clk.clks->clk);
-	if (ret) {
-		dev_err(jpeg->dev, "%s : %d, jpegenc clk_prepare_enable fail\n",
-			__func__, __LINE__);
-		goto enc_end;
-	}
-
 	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
 	v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
 
@@ -1798,20 +1797,13 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 	jpeg_dst_buf->frame_num = ctx->total_frame_num;
 
 	mtk_jpegdec_set_hw_param(ctx, hw_id, src_buf, dst_buf);
-	ret = pm_runtime_get_sync(comp_jpeg[hw_id]->dev);
+	ret = pm_runtime_resume_and_get(comp_jpeg[hw_id]->dev);
 	if (ret < 0) {
 		dev_err(jpeg->dev, "%s : %d, pm_runtime_get_sync fail !!!\n",
 			__func__, __LINE__);
 		goto dec_end;
 	}
 
-	ret = clk_prepare_enable(comp_jpeg[hw_id]->jdec_clk.clks->clk);
-	if (ret) {
-		dev_err(jpeg->dev, "%s : %d, jpegdec clk_prepare_enable fail\n",
-			__func__, __LINE__);
-		goto clk_end;
-	}
-
 	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
 	v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
 
@@ -1821,7 +1813,7 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 				 &dst_buf->vb2_buf, &fb)) {
 		dev_err(jpeg->dev, "%s : %d, mtk_jpeg_set_dec_dst fail\n",
 			__func__, __LINE__);
-		goto setdst_end;
+		goto set_dst_fail;
 	}
 
 	schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work,
@@ -1846,9 +1838,7 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 
 	return;
 
-setdst_end:
-	clk_disable_unprepare(comp_jpeg[hw_id]->jdec_clk.clks->clk);
-clk_end:
+set_dst_fail:
 	pm_runtime_put(comp_jpeg[hw_id]->dev);
 dec_end:
 	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index 2e6da8617484..db2afc5151ad 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -543,14 +543,13 @@ static void mtk_jpegdec_timeout_work(struct work_struct *work)
 	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
 
 	mtk_jpeg_dec_reset(cjpeg->reg_base);
-	clk_disable_unprepare(cjpeg->jdec_clk.clks->clk);
-	pm_runtime_put(cjpeg->dev);
 	cjpeg->hw_state = MTK_JPEG_HW_IDLE;
 	atomic_inc(&master_jpeg->hw_rdy);
 	wake_up(&master_jpeg->hw_wq);
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegdec_put_buf(cjpeg);
 	jpeg_buf_queue_dec(ctx);
+	pm_runtime_put(cjpeg->dev);
 }
 
 static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
@@ -592,12 +591,11 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegdec_put_buf(jpeg);
 	jpeg_buf_queue_dec(ctx);
-	pm_runtime_put(ctx->jpeg->dev);
-	clk_disable_unprepare(jpeg->jdec_clk.clks->clk);
 
 	jpeg->hw_state = MTK_JPEG_HW_IDLE;
 	wake_up(&master_jpeg->hw_wq);
 	atomic_inc(&master_jpeg->hw_rdy);
+	pm_runtime_put(jpeg->dev);
 
 	return IRQ_HANDLED;
 }
@@ -703,15 +701,84 @@ static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, dev);
 	pm_runtime_enable(&pdev->dev);
+	ret = devm_clk_bulk_get(dev->dev,
+				jpegdec_clk->clk_num,
+				jpegdec_clk->clks);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to init clk\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void mtk_jpeg_clk_on(struct mtk_jpegdec_comp_dev *jpeg)
+{
+	int ret;
+
+	ret = clk_bulk_prepare_enable(jpeg->jdec_clk.clk_num,
+				      jpeg->jdec_clk.clks);
+	if (ret)
+		dev_err(jpeg->dev, "%s : %d, jpegdec clk_prepare_enable fail\n",
+			__func__, __LINE__);
+}
+
+static void mtk_jpeg_clk_off(struct mtk_jpegdec_comp_dev *jpeg)
+{
+	clk_bulk_disable_unprepare(jpeg->jdec_clk.clk_num,
+				   jpeg->jdec_clk.clks);
+}
+
+static __maybe_unused int mtk_jpegdec_pm_suspend(struct device *dev)
+{
+	struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev);
+
+	mtk_jpeg_clk_off(jpeg);
 
 	return 0;
 }
 
+static __maybe_unused int mtk_jpegdec_pm_resume(struct device *dev)
+{
+	struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev);
+
+	mtk_jpeg_clk_on(jpeg);
+
+	return 0;
+}
+
+static __maybe_unused int mtk_jpegdec_suspend(struct device *dev)
+{
+	struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev);
+
+	v4l2_m2m_suspend(jpeg->master_dev->m2m_dev);
+	return pm_runtime_force_suspend(dev);
+}
+
+static __maybe_unused int mtk_jpegdec_resume(struct device *dev)
+{
+	struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev);
+	int ret;
+
+	ret = pm_runtime_force_resume(dev);
+	if (ret < 0)
+		return ret;
+
+	v4l2_m2m_resume(jpeg->master_dev->m2m_dev);
+	return ret;
+}
+
+static const struct dev_pm_ops mtk_jpegdec_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(mtk_jpegdec_suspend, mtk_jpegdec_resume)
+	SET_RUNTIME_PM_OPS(mtk_jpegdec_pm_suspend, mtk_jpegdec_pm_resume, NULL)
+};
+
 static struct platform_driver mtk_jpegdec_hw_driver = {
 	.probe = mtk_jpegdec_hw_probe,
 	.driver = {
 		.name = "mtk-jpegdec-hw",
 		.of_match_table = mtk_jpegdec_hw_ids,
+		.pm             = &mtk_jpegdec_pm_ops,
 	},
 };
 
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
index ff73393a2417..27da2a9922a6 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
@@ -274,14 +274,13 @@ static void mtk_jpegenc_timeout_work(struct work_struct *work)
 	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
 
 	mtk_jpeg_enc_reset(cjpeg->reg_base);
-	clk_disable_unprepare(cjpeg->venc_clk.clks->clk);
-	pm_runtime_put(cjpeg->dev);
 	cjpeg->hw_state = MTK_JPEG_HW_IDLE;
 	atomic_inc(&master_jpeg->hw_rdy);
 	wake_up(&master_jpeg->hw_wq);
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegenc_put_buf(cjpeg);
 	jpeg_buf_queue_dec(ctx);
+	pm_runtime_put(cjpeg->dev);
 }
 
 static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
@@ -316,12 +315,11 @@ static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
 	v4l2_m2m_buf_done(src_buf, buf_state);
 	mtk_jpegenc_put_buf(jpeg);
 	jpeg_buf_queue_dec(ctx);
-	pm_runtime_put(ctx->jpeg->dev);
-	clk_disable_unprepare(jpeg->venc_clk.clks->clk);
 
 	jpeg->hw_state = MTK_JPEG_HW_IDLE;
 	wake_up(&master_jpeg->hw_wq);
 	atomic_inc(&master_jpeg->hw_rdy);
+	pm_runtime_put(jpeg->dev);
 
 	return IRQ_HANDLED;
 }
@@ -425,15 +423,84 @@ static int mtk_jpegenc_hw_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, dev);
 	pm_runtime_enable(&pdev->dev);
+	ret = devm_clk_bulk_get(dev->dev,
+				jpegenc_clk->clk_num,
+				jpegenc_clk->clks);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to init clk\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void mtk_jpeg_clk_on(struct mtk_jpegenc_comp_dev *jpeg)
+{
+	int ret;
+
+	ret = clk_bulk_prepare_enable(jpeg->venc_clk.clk_num,
+				      jpeg->venc_clk.clks);
+	if (ret)
+		dev_err(jpeg->dev, "%s : %d, jpegenc clk_prepare_enable fail\n",
+			__func__, __LINE__);
+}
+
+static void mtk_jpeg_clk_off(struct mtk_jpegenc_comp_dev *jpeg)
+{
+	clk_bulk_disable_unprepare(jpeg->venc_clk.clk_num,
+				   jpeg->venc_clk.clks);
+}
+
+static __maybe_unused int mtk_jpegenc_pm_suspend(struct device *dev)
+{
+	struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev);
+
+	mtk_jpeg_clk_off(jpeg);
 
 	return 0;
 }
 
+static __maybe_unused int mtk_jpegenc_pm_resume(struct device *dev)
+{
+	struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev);
+
+	mtk_jpeg_clk_on(jpeg);
+
+	return 0;
+}
+
+static __maybe_unused int mtk_jpegenc_suspend(struct device *dev)
+{
+	struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev);
+
+	v4l2_m2m_suspend(jpeg->master_dev->m2m_dev);
+	return pm_runtime_force_suspend(dev);
+}
+
+static __maybe_unused int mtk_jpegenc_resume(struct device *dev)
+{
+	struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev);
+	int ret;
+
+	ret = pm_runtime_force_resume(dev);
+	if (ret < 0)
+		return ret;
+
+	v4l2_m2m_resume(jpeg->master_dev->m2m_dev);
+	return ret;
+}
+
+static const struct dev_pm_ops mtk_jpegenc_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(mtk_jpegenc_suspend, mtk_jpegenc_resume)
+	SET_RUNTIME_PM_OPS(mtk_jpegenc_pm_suspend, mtk_jpegenc_pm_resume, NULL)
+};
+
 static struct platform_driver mtk_jpegenc_hw_driver = {
 	.probe = mtk_jpegenc_hw_probe,
 	.driver = {
 		.name = "mtk-jpegenc-hw",
 		.of_match_table = mtk_jpegenc_drv_ids,
+		.pm = &mtk_jpegenc_pm_ops,
 	},
 };
 
-- 
2.46.0



From kyrie.wu at mediatek.com  Fri May 30 00:45:32 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Fri, 30 May 2025 15:45:32 +0800
Subject: [PATCH v5 07/12] media: mediatek: jpeg: refactor jpeg dst buffer layout
In-Reply-To: <20250530074537.26338-1-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
Message-ID: <20250530074537.26338-8-kyrie.wu@mediatek.com>

1. change dst buffer size to same as struct mtk_jpeg_src_buf
to make sure all params of mtk_jpeg_src_buf could get a memory.
2. For memory alloc operation:
the v4l2 framework malloc a memory, the base addr is vb2_buffer and
the size is sizeof(struct mtk_jpeg_src_buf), mtk_jpeg_src_buf could get
itself addr by container_of like that:
vb2_buffer -> vb2_v4l2_buffer -> mtk_jpeg_src_buf.
vb2_v4l2_buffer must keep on the top of mtk_jpeg_src_buf.

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c | 2 +-
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 52d59bb5c9ad..7e3509be6f69 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1103,7 +1103,7 @@ static int mtk_jpeg_queue_init(void *priv, struct vb2_queue *src_vq,
 	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
 	dst_vq->io_modes = VB2_DMABUF | VB2_MMAP;
 	dst_vq->drv_priv = ctx;
-	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+	dst_vq->buf_struct_size = sizeof(struct mtk_jpeg_src_buf);
 	dst_vq->ops = jpeg->variant->qops;
 	dst_vq->mem_ops = &vb2_dma_contig_memops;
 	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
index 655dc9c3280c..186cd1862028 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
@@ -96,10 +96,10 @@ struct mtk_jpeg_variant {
 };
 
 struct mtk_jpeg_src_buf {
-	u32 frame_num;
 	struct vb2_v4l2_buffer b;
 	struct list_head list;
 	u32 bs_size;
+	u32 frame_num;
 	struct mtk_jpeg_dec_param dec_param;
 
 	struct mtk_jpeg_ctx *curr_ctx;
-- 
2.46.0



From kyrie.wu at mediatek.com  Fri May 30 00:45:37 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Fri, 30 May 2025 15:45:37 +0800
Subject: [PATCH v5 12/12] media: mediatek: jpeg: fix remove buffer operation for multi-core
In-Reply-To: <20250530074537.26338-1-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
Message-ID: <20250530074537.26338-13-kyrie.wu@mediatek.com>

move remove buffer code to spinlock protect area for multi-core

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index eba9f58b9198..34fa03bcfdd3 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1684,9 +1684,6 @@ static void mtk_jpegenc_worker(struct work_struct *work)
 		goto enc_end;
 	}
 
-	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
-	v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
-
 	schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work,
 			      msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC));
 
@@ -1707,6 +1704,8 @@ static void mtk_jpegenc_worker(struct work_struct *work)
 			     &src_buf->vb2_buf);
 	mtk_jpeg_set_enc_params(ctx, comp_jpeg[hw_id]->reg_base);
 	mtk_jpeg_enc_start(comp_jpeg[hw_id]->reg_base);
+	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+	v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
 	jpeg_buf_queue_inc(ctx);
 	v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
 	spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags);
@@ -1803,9 +1802,6 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 		goto dec_end;
 	}
 
-	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
-	v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
-
 	mtk_jpeg_set_dec_src(ctx, &src_buf->vb2_buf, &bs);
 	if (mtk_jpeg_set_dec_dst(ctx,
 				 &jpeg_src_buf->dec_param,
@@ -1833,6 +1829,8 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 				jpeg_src_buf->bs_size,
 				&bs,
 				&fb);
+	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+	v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
 	mtk_jpeg_dec_start(comp_jpeg[hw_id]->reg_base);
 	jpeg_buf_queue_inc(ctx);
 	v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
-- 
2.46.0



From kyrie.wu at mediatek.com  Fri May 30 00:45:36 2025
From: kyrie.wu at mediatek.com (Kyrie Wu)
Date: Fri, 30 May 2025 15:45:36 +0800
Subject: [PATCH v5 11/12] media: mediatek: jpeg: refactor decoding resolution change operation
In-Reply-To: <20250530074537.26338-1-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
Message-ID: <20250530074537.26338-12-kyrie.wu@mediatek.com>

For multi-core:
1.if there are only two src buffers, hw0 and hw1 are decoding
at the same time. When resolution change occurred on one hw,
the src buffer cannot be got in the stop streaming function,
which will cause a crash.
2.When a resolution change occurs, immediately set the new
resolution parameter to save the new resolution;
3.After a resolution change occurred, decoding should not continue,
needs to wait until new buffers are ready and the state machine
changed.

Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
---
 drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 795916206c7c..eba9f58b9198 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -891,7 +891,8 @@ static void mtk_jpeg_dec_stop_streaming(struct vb2_queue *q)
 
 		vb = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
 		src_buf = mtk_jpeg_vb2_to_srcbuf(&vb->vb2_buf);
-		mtk_jpeg_set_queue_data(ctx, &src_buf->dec_param);
+		if (!IS_ERR_OR_NULL(src_buf))
+			mtk_jpeg_set_queue_data(ctx, &src_buf->dec_param);
 		ctx->state = MTK_JPEG_RUNNING;
 	} else if (V4L2_TYPE_IS_OUTPUT(q->type)) {
 		ctx->state = MTK_JPEG_INIT;
@@ -1785,11 +1786,15 @@ static void mtk_jpegdec_worker(struct work_struct *work)
 
 	if (mtk_jpeg_check_resolution_change(ctx,
 					     &jpeg_src_buf->dec_param)) {
-		mtk_jpeg_queue_src_chg_event(ctx);
+		mtk_jpeg_set_queue_data(ctx, &jpeg_src_buf->dec_param);
 		ctx->state = MTK_JPEG_SOURCE_CHANGE;
+		mtk_jpeg_queue_src_chg_event(ctx);
 		goto getbuf_fail;
 	}
 
+	if (ctx->state == MTK_JPEG_SOURCE_CHANGE)
+		goto getbuf_fail;
+
 	mtk_jpegdec_set_hw_param(ctx, hw_id, src_buf, dst_buf);
 	ret = pm_runtime_resume_and_get(comp_jpeg[hw_id]->dev);
 	if (ret < 0) {
-- 
2.46.0



From geert at linux-m68k.org  Fri May 30 01:06:16 2025
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Fri, 30 May 2025 10:06:16 +0200
Subject: [PATCH 14/17] pinctrl: renesas: Move fixed assignments to
 'pinctrl_desc' definition
In-Reply-To: <b6b7fb61-878e-4407-b964-564efb3524b1@linaro.org>
References: <20250528-pinctrl-const-desc-v1-0-76fe97899945@linaro.org>
 <20250528-pinctrl-const-desc-v1-14-76fe97899945@linaro.org>
 <CAMuHMdUGDf5n_Fg7pwiPumm95nPUXyH15geAy2ULwY3U+OtZJA@mail.gmail.com> <b6b7fb61-878e-4407-b964-564efb3524b1@linaro.org>
Message-ID: <CAMuHMdUHyLYk0oSN8XDNCXUvLQLe2u0k0noVJLbR+pYWDTB4+w@mail.gmail.com>

Hi Krzysztof,

CC wsa

On Wed, 28 May 2025 at 19:55, Krzysztof Kozlowski
<krzysztof.kozlowski at linaro.org> wrote:
> On 28/05/2025 14:54, Geert Uytterhoeven wrote:
> >>         .pmxops = &rzn1_pmx_ops,
> >>         .confops = &rzn1_pinconf_ops,
> >>         .owner = THIS_MODULE,
> >> +       .pins = rzn1_pins,
> >> +       .npins = ARRAY_SIZE(rzn1_pins),
> >>  };
> >>
> >>  static int rzn1_pinctrl_parse_groups(struct device_node *np,
> >> @@ -878,8 +880,6 @@ static int rzn1_pinctrl_probe(struct platform_device *pdev)
> >>
> >>         ipctl->dev = &pdev->dev;
> >>         rzn1_pinctrl_desc.name = dev_name(&pdev->dev);
> >
> > ... if you would replace this assignment by a hardcoded name
> > like "pinctrl-rzn1".
>
> I saw it, but this would not be equivalent. dev_name includes platform
> bus id, e.g. pinctrl-rzn1.0 which might matter here - conflict of names.
> Are you sure this would work fine?

There can be only one anyway.
Most drivers used a fixed name:

drivers/pinctrl/renesas/pinctrl-rza1.c: rza1_pctl->desc.name = DRIVER_NAME;
drivers/pinctrl/renesas/pinctrl-rza2.c: priv->desc.name = DRIVER_NAME;
drivers/pinctrl/renesas/pinctrl-rzg2l.c: pctrl->desc.name = DRV_NAME;
drivers/pinctrl/renesas/pinctrl-rzn1.c: rzn1_pinctrl_desc.name =
dev_name(&pdev->dev);
drivers/pinctrl/renesas/pinctrl-rzt2h.c: desc->name = DRV_NAME;
drivers/pinctrl/renesas/pinctrl-rzv2m.c: pctrl->desc.name = DRV_NAME;
drivers/pinctrl/renesas/pinctrl.c: pmx->pctl_desc.name = DRV_NAME;

It might change the path in debugfs (/sys/kernel/debug/pinctrl/) though.
Wolfram?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From nicolas.dufresne at collabora.com  Fri May 30 07:40:54 2025
From: nicolas.dufresne at collabora.com (Nicolas Dufresne)
Date: Fri, 30 May 2025 10:40:54 -0400
Subject: [PATCH v2 0/6] Add support for MT8196 video encoder
In-Reply-To: <20250528063633.14054-1-irui.wang@mediatek.com>
References: <20250528063633.14054-1-irui.wang@mediatek.com>
Message-ID: <7a372c544c370d64b916a7092aabac555710d7c5.camel@collabora.com>

Hi,

Le mercredi 28 mai 2025 ? 14:36 +0800, Irui Wang a ?crit?:
> This patch series add support for MT8196 video encoder.
> patch 1~3: Add a new encoder driver interface for new VCP firmware.
> patch 4~6: Add MT8196 encoder driver platform data.
> 
> About adding new driver support, the v4l2-compliance report shows:
> "Total for mtk-vcodec-enc device /dev/video3: 47, Succeeded: 46, Failed: 1, Warnings: 0"
> The 1 Failed case is not caused by current patch set.

We really want to see the full report, simply reply to this cover letter with
the entire report to fix it.

Nicolas

> 
> This patch set depends on "media: mediatek: vcodec: support video decoder in mt8196"[1]
> 
> [1] https://patchwork.linuxtv.org/project/linux-media/list/?series=15232
> 
> Change in v2:
> ?- Add support for VCP encode process.
> ?- Add MT8196 encoder driver platform data.
> ?- Rebase encoder patch onto decoder's patch set.
> ?- Fix some review comments in v1.
> 
> Irui Wang (6):
> ? media: mediatek: encoder: Add a new encoder driver interface
> ? media: mediatek: encoder: Add support for common firmware interface
> ? media: mediatek: encoder: Add support for VCP encode process
> ? media: mediatek: encoder: Add a new platform data member
> ? dt-bindings: media: mediatek: encoder: Add encoder dt-bindings for
> ??? MT8196
> ? media: mediatek: encoder: Add MT8196 encoder compatible data
> 
> ?.../media/mediatek,vcodec-encoder.yaml??????? |? 12 +
> ?.../mediatek/vcodec/common/mtk_vcodec_fw.c??? |? 19 +
> ?.../mediatek/vcodec/common/mtk_vcodec_fw.h??? |?? 2 +
> ?.../vcodec/common/mtk_vcodec_fw_priv.h??????? |?? 1 +
> ?.../vcodec/common/mtk_vcodec_fw_vcp.c???????? |?? 6 +
> ?.../platform/mediatek/vcodec/encoder/Makefile |?? 1 +
> ?.../mediatek/vcodec/encoder/mtk_vcodec_enc.c? |? 37 +-
> ?.../vcodec/encoder/mtk_vcodec_enc_drv.c?????? |? 28 +
> ?.../vcodec/encoder/mtk_vcodec_enc_drv.h?????? |? 15 +-
> ?.../vcodec/encoder/venc/venc_common_if.c????? | 678 ++++++++++++++++++
> ?.../vcodec/encoder/venc/venc_h264_if.c??????? |?? 8 +-
> ?.../mediatek/vcodec/encoder/venc_drv_if.c???? |?? 3 +-
> ?.../mediatek/vcodec/encoder/venc_drv_if.h???? |? 11 +-
> ?.../mediatek/vcodec/encoder/venc_ipi_msg.h??? |? 26 +
> ?.../mediatek/vcodec/encoder/venc_vpu_if.c???? |? 51 +-
> ?15 files changed, 843 insertions(+), 55 deletions(-)
> ?create mode 100644 drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c


From conor at kernel.org  Fri May 30 08:57:20 2025
From: conor at kernel.org (Conor Dooley)
Date: Fri, 30 May 2025 16:57:20 +0100
Subject: [RFC v1] dt-bindings: interconnect: add mt7988-cci compatible
In-Reply-To: <20250528135251.6492-1-linux@fw-web.de>
References: <20250528135251.6492-1-linux@fw-web.de>
Message-ID: <20250530-naturist-swept-973a1f8f4b08@spud>

On Wed, May 28, 2025 at 03:52:49PM +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w at public-files.de>
> 
> Add compatible for Mediatek MT7988 SoC with mediatek,mt8183-cci fallback
> which is taken by driver.

What's RFC about the patch?

> 
> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> ---
>  .../bindings/interconnect/mediatek,cci.yaml          | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> index 58611ba2a0f4..2c6785c588e9 100644
> --- a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> @@ -17,9 +17,15 @@ description: |
>  
>  properties:
>    compatible:
> -    enum:
> -      - mediatek,mt8183-cci
> -      - mediatek,mt8186-cci
> +    oneOf:
> +      - items:

This "- items:" is redundant.

> +          - enum:
> +              - mediatek,mt8183-cci
> +              - mediatek,mt8186-cci
> +      - items:
> +          - enum:
> +              - mediatek,mt7988-cci
> +          - const: mediatek,mt8183-cci
>  
>    clocks:
>      items:
> -- 
> 2.43.0
> 
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From linux at fw-web.de  Fri May 30 09:11:58 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Fri, 30 May 2025 18:11:58 +0200
Subject: [RFC v1] dt-bindings: interconnect: add mt7988-cci compatible
In-Reply-To: <20250530-naturist-swept-973a1f8f4b08@spud>
References: <20250528135251.6492-1-linux@fw-web.de> <20250530-naturist-swept-973a1f8f4b08@spud>
Message-ID: <C75720B1-AD09-4A48-98FD-7FD8116934F7@fw-web.de>

Hi

Thank you for review.

Am 30. Mai 2025 17:57:20 MESZ schrieb Conor Dooley <conor at kernel.org>:
>On Wed, May 28, 2025 at 03:52:49PM +0200, Frank Wunderlich wrote:
>> From: Frank Wunderlich <frank-w at public-files.de>
>> 
>> Add compatible for Mediatek MT7988 SoC with mediatek,mt8183-cci fallback
>> which is taken by driver.
>
>What's RFC about the patch?

We have merge window,but maybe this rule is
net(-next) only. And i was unsure if enum for
new compatible is right or if i should use 2
const.

>> 
>> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
>> ---
>>  .../bindings/interconnect/mediatek,cci.yaml          | 12 +++++++++---
>>  1 file changed, 9 insertions(+), 3 deletions(-)
>> 
>> diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
>> index 58611ba2a0f4..2c6785c588e9 100644
>> --- a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
>> +++ b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
>> @@ -17,9 +17,15 @@ description: |
>>  
>>  properties:
>>    compatible:
>> -    enum:
>> -      - mediatek,mt8183-cci
>> -      - mediatek,mt8186-cci
>> +    oneOf:
>> +      - items:
>
>This "- items:" is redundant.

Ok,i try without it.

>> +          - enum:
>> +              - mediatek,mt8183-cci
>> +              - mediatek,mt8186-cci
>> +      - items:
>> +          - enum:
>> +              - mediatek,mt7988-cci
>> +          - const: mediatek,mt8183-cci
>>  
>>    clocks:
>>      items:
>> -- 
>> 2.43.0
>> 


regards Frank


From nicolas at ndufresne.ca  Fri May 30 10:33:58 2025
From: nicolas at ndufresne.ca (Nicolas Dufresne)
Date: Fri, 30 May 2025 13:33:58 -0400
Subject: [PATCH v5 06/12] media: mediatek: jpeg: refactor jpeg buffer
 payload setting
In-Reply-To: <20250530074537.26338-7-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
	 <20250530074537.26338-7-kyrie.wu@mediatek.com>
Message-ID: <ac655c582609b7887381e1b68ed99f6b128fd794.camel@ndufresne.ca>

Hi Kyrie,

Le vendredi 30 mai 2025 ? 15:45 +0800, Kyrie Wu a ?crit?:
> 1. for multi-core jpegdec:
> ?? core0: |<-------- decoding buffer0 and resolution changed to smaller
> ?? core1:? |<-------- decoding buffer1
> ?? core0:?? |<- handling resolution changing
> ?? core0:??? |<- vb2_set_plane_payload
> 2. the payload size is changed on the step of set format. Because core1
> is running and streaming has not been stopped, the format cannot be
> set again, resulting in no change in the payload size.
> 3. at this time, the payload size is bigger than buffer length,
> it will print a warnning call trace
> 4. set payload size must less than buffer length

You'll have to rework the text in this commit message, I must admit I don't
understand from this text what exactly the problem is, make it really hard to
review your solution.

> 
> Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
> ---
> ?.../platform/mediatek/jpeg/mtk_jpeg_core.c???? | 18 +++++++++++++++---
> ?1 file changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> index 0074d1edb534..52d59bb5c9ad 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> @@ -720,10 +720,22 @@ static int mtk_jpeg_buf_prepare(struct vb2_buffer *vb)
> ?		plane_fmt = q_data->pix_mp.plane_fmt[i];
> ?		if (ctx->enable_exif &&
> ?		??? q_data->fmt->fourcc == V4L2_PIX_FMT_JPEG)
> -			vb2_set_plane_payload(vb, i, plane_fmt.sizeimage +
> -					????? MTK_JPEG_MAX_EXIF_SIZE);
> +			if (vb->planes[i].length > (plane_fmt.sizeimage +
> +			??? MTK_JPEG_MAX_EXIF_SIZE))
> +				vb2_set_plane_payload(vb, i,
> +						????? plane_fmt.sizeimage +
> +						????? MTK_JPEG_MAX_EXIF_SIZE);
> +			else
> +				vb2_set_plane_payload(vb, i,
> +						????? vb->planes[i].length);
> +
> ?		else
> -			vb2_set_plane_payload(vb, i,? plane_fmt.sizeimage);
> +			if (vb->planes[i].length > plane_fmt.sizeimage)
> +				vb2_set_plane_payload(vb, i,
> +						????? plane_fmt.sizeimage);
> +			else
> +				vb2_set_plane_payload(vb, i,
> +						????? vb->planes[i].length);

Is this the same as ?

		unsigned long max_size = plane_fmt.sizeimage;

		if (ctx->enable_exif && q_data->fmt->fourcc == V4L2_PIX_FMT_JPEG)
			max_size += MTK_JPEG_MAX_EXIF_SIZE;

		vb2_set_plane_payload(vb, i, MIN(vb->planes[i].length, max_size));

It is unclear to me how this isn't just a workaround though, looking forward
your reworked commit message.

Nicolas

> ?	}
> ?
> ?	return 0;


From nicolas at ndufresne.ca  Fri May 30 10:38:14 2025
From: nicolas at ndufresne.ca (Nicolas Dufresne)
Date: Fri, 30 May 2025 13:38:14 -0400
Subject: [PATCH v5 07/12] media: mediatek: jpeg: refactor jpeg dst
 buffer layout
In-Reply-To: <20250530074537.26338-8-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
	 <20250530074537.26338-8-kyrie.wu@mediatek.com>
Message-ID: <8eadc152c3542c30fb31bb67093087f2bb0a6c31.camel@ndufresne.ca>

Hi,

Le vendredi 30 mai 2025 ? 15:45 +0800, Kyrie Wu a ?crit?:
> 1. change dst buffer size to same as struct mtk_jpeg_src_buf
> to make sure all params of mtk_jpeg_src_buf could get a memory.
> 2. For memory alloc operation:
> the v4l2 framework malloc a memory, the base addr is vb2_buffer and
> the size is sizeof(struct mtk_jpeg_src_buf), mtk_jpeg_src_buf could get
> itself addr by container_of like that:
> vb2_buffer -> vb2_v4l2_buffer -> mtk_jpeg_src_buf.
> vb2_v4l2_buffer must keep on the top of mtk_jpeg_src_buf.

The subject imply a refactoring, but the most important change in your
patch is to fix the wrong buf strut size. Can you rework the subject
and message to state what you are fixing please.

Add a Fixes tag, and moved it at the start of the series to show this
isn't a problem you have introduced in previous patch.

> 
> Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
> ---
> ?drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c | 2 +-
> ?drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h | 2 +-
> ?2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> index 52d59bb5c9ad..7e3509be6f69 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> @@ -1103,7 +1103,7 @@ static int mtk_jpeg_queue_init(void *priv, struct vb2_queue *src_vq,
> ?	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
> ?	dst_vq->io_modes = VB2_DMABUF | VB2_MMAP;
> ?	dst_vq->drv_priv = ctx;
> -	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
> +	dst_vq->buf_struct_size = sizeof(struct mtk_jpeg_src_buf);
> ?	dst_vq->ops = jpeg->variant->qops;
> ?	dst_vq->mem_ops = &vb2_dma_contig_memops;
> ?	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> index 655dc9c3280c..186cd1862028 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> @@ -96,10 +96,10 @@ struct mtk_jpeg_variant {
> ?};
> ?
> ?struct mtk_jpeg_src_buf {
> -	u32 frame_num;
> ?	struct vb2_v4l2_buffer b;
> ?	struct list_head list;
> ?	u32 bs_size;
> +	u32 frame_num;

This "refactoring" should be split, it does not fix anything.

Nicolas

> ?	struct mtk_jpeg_dec_param dec_param;
> ?
> ?	struct mtk_jpeg_ctx *curr_ctx;


From nicolas at ndufresne.ca  Fri May 30 10:40:35 2025
From: nicolas at ndufresne.ca (Nicolas Dufresne)
Date: Fri, 30 May 2025 13:40:35 -0400
Subject: [PATCH v5 08/12] media: mediatek: jpeg: fix stop streaming flow
 for multi-core
In-Reply-To: <20250530074537.26338-9-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
	 <20250530074537.26338-9-kyrie.wu@mediatek.com>
Message-ID: <8ff9cf88b2498e4bfd4c12b9c01cfaf046b92fd6.camel@ndufresne.ca>

Hi,

Le vendredi 30 mai 2025 ? 15:45 +0800, Kyrie Wu a ?crit?:
> 1. For multi-core jpegdec, the all hws may run at the same time,
> if one hw decoded firstly, the function of mtk_jpeg_dec_stop_streaming
> would be called, but others input buffers are decoding, this will
> cause some running buffers to be buffer done, causing errors;
> 2. add a parameter to calculate the decoding buffer counts, it
> wil decrease to 0 until the all buffers decoded and the
> mtk_jpeg_dec_stop_streaming could continue to be executed.

This one is equally unclear to me. If you run different queues per core,
why does this matter ?

Nicolas

> 
> Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
> ---
> ?.../media/platform/mediatek/jpeg/mtk_jpeg_core.c | 16 ++++++++++++++++
> ?.../media/platform/mediatek/jpeg/mtk_jpeg_core.h |? 2 ++
> ?.../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c???? |? 9 +++++++++
> ?.../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c???? |? 9 +++++++++
> ?4 files changed, 36 insertions(+)
> 
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> index 7e3509be6f69..1d3df1230191 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> @@ -861,8 +861,12 @@ static struct vb2_v4l2_buffer *mtk_jpeg_buf_remove(struct mtk_jpeg_ctx *ctx,
> ?static void mtk_jpeg_enc_stop_streaming(struct vb2_queue *q)
> ?{
> ?	struct mtk_jpeg_ctx *ctx = vb2_get_drv_priv(q);
> +	struct mtk_jpeg_dev *jpeg = ctx->jpeg;
> ?	struct vb2_v4l2_buffer *vb;
> ?
> +	if (jpeg->variant->multi_core)
> +		wait_event(jpeg->hw_wq, (atomic_read(&ctx->buf_list_cnt) == 0));
> +
> ?	while ((vb = mtk_jpeg_buf_remove(ctx, q->type)))
> ?		v4l2_m2m_buf_done(vb, VB2_BUF_STATE_ERROR);
> ?}
> @@ -870,6 +874,7 @@ static void mtk_jpeg_enc_stop_streaming(struct vb2_queue *q)
> ?static void mtk_jpeg_dec_stop_streaming(struct vb2_queue *q)
> ?{
> ?	struct mtk_jpeg_ctx *ctx = vb2_get_drv_priv(q);
> +	struct mtk_jpeg_dev *jpeg = ctx->jpeg;
> ?	struct vb2_v4l2_buffer *vb;
> ?
> ?	/*
> @@ -877,6 +882,9 @@ static void mtk_jpeg_dec_stop_streaming(struct vb2_queue *q)
> ?	 * Before STREAMOFF, we still have to return the old resolution and
> ?	 * subsampling. Update capture queue when the stream is off.
> ?	 */
> +	if (jpeg->variant->multi_core)
> +		wait_event(jpeg->hw_wq, (atomic_read(&ctx->buf_list_cnt) == 0));
> +
> ?	if (ctx->state == MTK_JPEG_SOURCE_CHANGE &&
> ?	??? V4L2_TYPE_IS_CAPTURE(q->type)) {
> ?		struct mtk_jpeg_src_buf *src_buf;
> @@ -1186,6 +1194,7 @@ static int mtk_jpeg_open(struct file *file)
> ?	v4l2_fh_init(&ctx->fh, vfd);
> ?	file->private_data = &ctx->fh;
> ?	v4l2_fh_add(&ctx->fh);
> +	atomic_set(&ctx->buf_list_cnt, 0);
> ?
> ?	ctx->jpeg = jpeg;
> ?	ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(jpeg->m2m_dev, ctx,
> @@ -1568,6 +1577,11 @@ static int mtk_jpegdec_set_hw_param(struct mtk_jpeg_ctx *ctx,
> ?	return 0;
> ?}
> ?
> +static void jpeg_buf_queue_inc(struct mtk_jpeg_ctx *ctx)
> +{
> +	atomic_inc(&ctx->buf_list_cnt);
> +}
> +
> ?static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg_dev *jpeg)
> ?{
> ?	struct mtk_jpeg_ctx *ctx;
> @@ -1693,6 +1707,7 @@ static void mtk_jpegenc_worker(struct work_struct *work)
> ?			???? &src_buf->vb2_buf);
> ?	mtk_jpeg_set_enc_params(ctx, comp_jpeg[hw_id]->reg_base);
> ?	mtk_jpeg_enc_start(comp_jpeg[hw_id]->reg_base);
> +	jpeg_buf_queue_inc(ctx);
> ?	v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
> ?	spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags);
> ?
> @@ -1825,6 +1840,7 @@ static void mtk_jpegdec_worker(struct work_struct *work)
> ?				&bs,
> ?				&fb);
> ?	mtk_jpeg_dec_start(comp_jpeg[hw_id]->reg_base);
> +	jpeg_buf_queue_inc(ctx);
> ?	v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
> ?	spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags);
> ?
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> index 186cd1862028..6e8304680393 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> @@ -303,6 +303,7 @@ struct mtk_jpeg_q_data {
> ? * @dst_done_queue:		encoded frame buffer queue
> ? * @done_queue_lock:		encoded frame operation spinlock
> ? * @last_done_frame_num:	the last encoded frame number
> + * @buf_list_cnt:		the frame buffer count own by jpeg driver
> ? */
> ?struct mtk_jpeg_ctx {
> ?	struct mtk_jpeg_dev		*jpeg;
> @@ -321,6 +322,7 @@ struct mtk_jpeg_ctx {
> ?	/* spinlock protecting the encode done buffer */
> ?	spinlock_t done_queue_lock;
> ?	u32 last_done_frame_num;
> +	atomic_t buf_list_cnt;
> ?};
> ?
> ?#endif /* _MTK_JPEG_CORE_H */
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> index 2200f3b628dc..2e6da8617484 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> @@ -522,6 +522,11 @@ static void mtk_jpegdec_put_buf(struct mtk_jpegdec_comp_dev *jpeg)
> ?	spin_unlock_irqrestore(&ctx->done_queue_lock, flags);
> ?}
> ?
> +static void jpeg_buf_queue_dec(struct mtk_jpeg_ctx *ctx)
> +{
> +	atomic_dec(&ctx->buf_list_cnt);
> +}
> +
> ?static void mtk_jpegdec_timeout_work(struct work_struct *work)
> ?{
> ?	enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
> @@ -530,9 +535,11 @@ static void mtk_jpegdec_timeout_work(struct work_struct *work)
> ?			???? job_timeout_work.work);
> ?	struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev;
> ?	struct vb2_v4l2_buffer *src_buf, *dst_buf;
> +	struct mtk_jpeg_ctx *ctx;
> ?
> ?	src_buf = cjpeg->hw_param.src_buffer;
> ?	dst_buf = cjpeg->hw_param.dst_buffer;
> +	ctx = cjpeg->hw_param.curr_ctx;
> ?	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
> ?
> ?	mtk_jpeg_dec_reset(cjpeg->reg_base);
> @@ -543,6 +550,7 @@ static void mtk_jpegdec_timeout_work(struct work_struct *work)
> ?	wake_up(&master_jpeg->hw_wq);
> ?	v4l2_m2m_buf_done(src_buf, buf_state);
> ?	mtk_jpegdec_put_buf(cjpeg);
> +	jpeg_buf_queue_dec(ctx);
> ?}
> ?
> ?static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
> @@ -583,6 +591,7 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
> ?	buf_state = VB2_BUF_STATE_DONE;
> ?	v4l2_m2m_buf_done(src_buf, buf_state);
> ?	mtk_jpegdec_put_buf(jpeg);
> +	jpeg_buf_queue_dec(ctx);
> ?	pm_runtime_put(ctx->jpeg->dev);
> ?	clk_disable_unprepare(jpeg->jdec_clk.clks->clk);
> ?
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
> index 4c264c14ad83..ff73393a2417 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
> @@ -251,6 +251,11 @@ static void mtk_jpegenc_put_buf(struct mtk_jpegenc_comp_dev *jpeg)
> ?	spin_unlock_irqrestore(&ctx->done_queue_lock, flags);
> ?}
> ?
> +static void jpeg_buf_queue_dec(struct mtk_jpeg_ctx *ctx)
> +{
> +	atomic_dec(&ctx->buf_list_cnt);
> +}
> +
> ?static void mtk_jpegenc_timeout_work(struct work_struct *work)
> ?{
> ?	struct delayed_work *dly_work = to_delayed_work(work);
> @@ -261,9 +266,11 @@ static void mtk_jpegenc_timeout_work(struct work_struct *work)
> ?	struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev;
> ?	enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
> ?	struct vb2_v4l2_buffer *src_buf, *dst_buf;
> +	struct mtk_jpeg_ctx *ctx;
> ?
> ?	src_buf = cjpeg->hw_param.src_buffer;
> ?	dst_buf = cjpeg->hw_param.dst_buffer;
> +	ctx = cjpeg->hw_param.curr_ctx;
> ?	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
> ?
> ?	mtk_jpeg_enc_reset(cjpeg->reg_base);
> @@ -274,6 +281,7 @@ static void mtk_jpegenc_timeout_work(struct work_struct *work)
> ?	wake_up(&master_jpeg->hw_wq);
> ?	v4l2_m2m_buf_done(src_buf, buf_state);
> ?	mtk_jpegenc_put_buf(cjpeg);
> +	jpeg_buf_queue_dec(ctx);
> ?}
> ?
> ?static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
> @@ -307,6 +315,7 @@ static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
> ?	buf_state = VB2_BUF_STATE_DONE;
> ?	v4l2_m2m_buf_done(src_buf, buf_state);
> ?	mtk_jpegenc_put_buf(jpeg);
> +	jpeg_buf_queue_dec(ctx);
> ?	pm_runtime_put(ctx->jpeg->dev);
> ?	clk_disable_unprepare(jpeg->venc_clk.clks->clk);
> ?


From nicolas at ndufresne.ca  Fri May 30 10:43:26 2025
From: nicolas at ndufresne.ca (Nicolas Dufresne)
Date: Fri, 30 May 2025 13:43:26 -0400
Subject: [PATCH v5 09/12] media: mediatek: jpeg: refactor multi-core clk
 suspend and resume setting
In-Reply-To: <20250530074537.26338-10-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
	 <20250530074537.26338-10-kyrie.wu@mediatek.com>
Message-ID: <8ab1b3166cbb972dbd5984fa591b42dbf984fc3b.camel@ndufresne.ca>

Hi,

Le vendredi 30 mai 2025 ? 15:45 +0800, Kyrie Wu a ?crit?:
> refactor jpeg clk suspend and resume setting for multi-core

You'll have to write a lot more to support such a large and I
must say slightly convoluted change. Why do you need a special
case for 1 core in the first place ? What about multi-core
design that support from 1 to N cores without using different
code path ?

Nicolas

> 
> Signed-off-by: Kyrie Wu <kyrie.wu at mediatek.com>
> ---
> ?.../platform/mediatek/jpeg/mtk_jpeg_core.c??? | 28 +++----
> ?.../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c? | 75 ++++++++++++++++++-
> ?.../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c? | 75 ++++++++++++++++++-
> ?3 files changed, 151 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> index 1d3df1230191..c1d2de92f125 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> @@ -1126,6 +1126,9 @@ static void mtk_jpeg_clk_on(struct mtk_jpeg_dev *jpeg)
> ?{
> ?	int ret;
> ?
> +	if (jpeg->variant->multi_core)
> +		return;
> +
> ?	ret = clk_bulk_prepare_enable(jpeg->variant->num_clks,
> ?				????? jpeg->variant->clks);
> ?	if (ret)
> @@ -1134,6 +1137,9 @@ static void mtk_jpeg_clk_on(struct mtk_jpeg_dev *jpeg)
> ?
> ?static void mtk_jpeg_clk_off(struct mtk_jpeg_dev *jpeg)
> ?{
> +	if (jpeg->variant->multi_core)
> +		return;
> +
> ?	clk_bulk_disable_unprepare(jpeg->variant->num_clks,
> ?				?? jpeg->variant->clks);
> ?}
> @@ -1677,13 +1683,6 @@ static void mtk_jpegenc_worker(struct work_struct *work)
> ?		goto enc_end;
> ?	}
> ?
> -	ret = clk_prepare_enable(comp_jpeg[hw_id]->venc_clk.clks->clk);
> -	if (ret) {
> -		dev_err(jpeg->dev, "%s : %d, jpegenc clk_prepare_enable fail\n",
> -			__func__, __LINE__);
> -		goto enc_end;
> -	}
> -
> ?	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
> ?	v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
> ?
> @@ -1798,20 +1797,13 @@ static void mtk_jpegdec_worker(struct work_struct *work)
> ?	jpeg_dst_buf->frame_num = ctx->total_frame_num;
> ?
> ?	mtk_jpegdec_set_hw_param(ctx, hw_id, src_buf, dst_buf);
> -	ret = pm_runtime_get_sync(comp_jpeg[hw_id]->dev);
> +	ret = pm_runtime_resume_and_get(comp_jpeg[hw_id]->dev);
> ?	if (ret < 0) {
> ?		dev_err(jpeg->dev, "%s : %d, pm_runtime_get_sync fail !!!\n",
> ?			__func__, __LINE__);
> ?		goto dec_end;
> ?	}
> ?
> -	ret = clk_prepare_enable(comp_jpeg[hw_id]->jdec_clk.clks->clk);
> -	if (ret) {
> -		dev_err(jpeg->dev, "%s : %d, jpegdec clk_prepare_enable fail\n",
> -			__func__, __LINE__);
> -		goto clk_end;
> -	}
> -
> ?	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
> ?	v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
> ?
> @@ -1821,7 +1813,7 @@ static void mtk_jpegdec_worker(struct work_struct *work)
> ?				 &dst_buf->vb2_buf, &fb)) {
> ?		dev_err(jpeg->dev, "%s : %d, mtk_jpeg_set_dec_dst fail\n",
> ?			__func__, __LINE__);
> -		goto setdst_end;
> +		goto set_dst_fail;
> ?	}
> ?
> ?	schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work,
> @@ -1846,9 +1838,7 @@ static void mtk_jpegdec_worker(struct work_struct *work)
> ?
> ?	return;
> ?
> -setdst_end:
> -	clk_disable_unprepare(comp_jpeg[hw_id]->jdec_clk.clks->clk);
> -clk_end:
> +set_dst_fail:
> ?	pm_runtime_put(comp_jpeg[hw_id]->dev);
> ?dec_end:
> ?	v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> index 2e6da8617484..db2afc5151ad 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> @@ -543,14 +543,13 @@ static void mtk_jpegdec_timeout_work(struct work_struct *work)
> ?	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
> ?
> ?	mtk_jpeg_dec_reset(cjpeg->reg_base);
> -	clk_disable_unprepare(cjpeg->jdec_clk.clks->clk);
> -	pm_runtime_put(cjpeg->dev);
> ?	cjpeg->hw_state = MTK_JPEG_HW_IDLE;
> ?	atomic_inc(&master_jpeg->hw_rdy);
> ?	wake_up(&master_jpeg->hw_wq);
> ?	v4l2_m2m_buf_done(src_buf, buf_state);
> ?	mtk_jpegdec_put_buf(cjpeg);
> ?	jpeg_buf_queue_dec(ctx);
> +	pm_runtime_put(cjpeg->dev);
> ?}
> ?
> ?static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
> @@ -592,12 +591,11 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
> ?	v4l2_m2m_buf_done(src_buf, buf_state);
> ?	mtk_jpegdec_put_buf(jpeg);
> ?	jpeg_buf_queue_dec(ctx);
> -	pm_runtime_put(ctx->jpeg->dev);
> -	clk_disable_unprepare(jpeg->jdec_clk.clks->clk);
> ?
> ?	jpeg->hw_state = MTK_JPEG_HW_IDLE;
> ?	wake_up(&master_jpeg->hw_wq);
> ?	atomic_inc(&master_jpeg->hw_rdy);
> +	pm_runtime_put(jpeg->dev);
> ?
> ?	return IRQ_HANDLED;
> ?}
> @@ -703,15 +701,84 @@ static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
> ?
> ?	platform_set_drvdata(pdev, dev);
> ?	pm_runtime_enable(&pdev->dev);
> +	ret = devm_clk_bulk_get(dev->dev,
> +				jpegdec_clk->clk_num,
> +				jpegdec_clk->clks);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Failed to init clk\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static void mtk_jpeg_clk_on(struct mtk_jpegdec_comp_dev *jpeg)
> +{
> +	int ret;
> +
> +	ret = clk_bulk_prepare_enable(jpeg->jdec_clk.clk_num,
> +				????? jpeg->jdec_clk.clks);
> +	if (ret)
> +		dev_err(jpeg->dev, "%s : %d, jpegdec clk_prepare_enable fail\n",
> +			__func__, __LINE__);
> +}
> +
> +static void mtk_jpeg_clk_off(struct mtk_jpegdec_comp_dev *jpeg)
> +{
> +	clk_bulk_disable_unprepare(jpeg->jdec_clk.clk_num,
> +				?? jpeg->jdec_clk.clks);
> +}
> +
> +static __maybe_unused int mtk_jpegdec_pm_suspend(struct device *dev)
> +{
> +	struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev);
> +
> +	mtk_jpeg_clk_off(jpeg);
> ?
> ?	return 0;
> ?}
> ?
> +static __maybe_unused int mtk_jpegdec_pm_resume(struct device *dev)
> +{
> +	struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev);
> +
> +	mtk_jpeg_clk_on(jpeg);
> +
> +	return 0;
> +}
> +
> +static __maybe_unused int mtk_jpegdec_suspend(struct device *dev)
> +{
> +	struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev);
> +
> +	v4l2_m2m_suspend(jpeg->master_dev->m2m_dev);
> +	return pm_runtime_force_suspend(dev);
> +}
> +
> +static __maybe_unused int mtk_jpegdec_resume(struct device *dev)
> +{
> +	struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev);
> +	int ret;
> +
> +	ret = pm_runtime_force_resume(dev);
> +	if (ret < 0)
> +		return ret;
> +
> +	v4l2_m2m_resume(jpeg->master_dev->m2m_dev);
> +	return ret;
> +}
> +
> +static const struct dev_pm_ops mtk_jpegdec_pm_ops = {
> +	SET_SYSTEM_SLEEP_PM_OPS(mtk_jpegdec_suspend, mtk_jpegdec_resume)
> +	SET_RUNTIME_PM_OPS(mtk_jpegdec_pm_suspend, mtk_jpegdec_pm_resume, NULL)
> +};
> +
> ?static struct platform_driver mtk_jpegdec_hw_driver = {
> ?	.probe = mtk_jpegdec_hw_probe,
> ?	.driver = {
> ?		.name = "mtk-jpegdec-hw",
> ?		.of_match_table = mtk_jpegdec_hw_ids,
> +		.pm???????????? = &mtk_jpegdec_pm_ops,
> ?	},
> ?};
> ?
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
> b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
> index ff73393a2417..27da2a9922a6 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
> @@ -274,14 +274,13 @@ static void mtk_jpegenc_timeout_work(struct work_struct *work)
> ?	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
> ?
> ?	mtk_jpeg_enc_reset(cjpeg->reg_base);
> -	clk_disable_unprepare(cjpeg->venc_clk.clks->clk);
> -	pm_runtime_put(cjpeg->dev);
> ?	cjpeg->hw_state = MTK_JPEG_HW_IDLE;
> ?	atomic_inc(&master_jpeg->hw_rdy);
> ?	wake_up(&master_jpeg->hw_wq);
> ?	v4l2_m2m_buf_done(src_buf, buf_state);
> ?	mtk_jpegenc_put_buf(cjpeg);
> ?	jpeg_buf_queue_dec(ctx);
> +	pm_runtime_put(cjpeg->dev);
> ?}
> ?
> ?static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
> @@ -316,12 +315,11 @@ static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
> ?	v4l2_m2m_buf_done(src_buf, buf_state);
> ?	mtk_jpegenc_put_buf(jpeg);
> ?	jpeg_buf_queue_dec(ctx);
> -	pm_runtime_put(ctx->jpeg->dev);
> -	clk_disable_unprepare(jpeg->venc_clk.clks->clk);
> ?
> ?	jpeg->hw_state = MTK_JPEG_HW_IDLE;
> ?	wake_up(&master_jpeg->hw_wq);
> ?	atomic_inc(&master_jpeg->hw_rdy);
> +	pm_runtime_put(jpeg->dev);
> ?
> ?	return IRQ_HANDLED;
> ?}
> @@ -425,15 +423,84 @@ static int mtk_jpegenc_hw_probe(struct platform_device *pdev)
> ?
> ?	platform_set_drvdata(pdev, dev);
> ?	pm_runtime_enable(&pdev->dev);
> +	ret = devm_clk_bulk_get(dev->dev,
> +				jpegenc_clk->clk_num,
> +				jpegenc_clk->clks);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Failed to init clk\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static void mtk_jpeg_clk_on(struct mtk_jpegenc_comp_dev *jpeg)
> +{
> +	int ret;
> +
> +	ret = clk_bulk_prepare_enable(jpeg->venc_clk.clk_num,
> +				????? jpeg->venc_clk.clks);
> +	if (ret)
> +		dev_err(jpeg->dev, "%s : %d, jpegenc clk_prepare_enable fail\n",
> +			__func__, __LINE__);
> +}
> +
> +static void mtk_jpeg_clk_off(struct mtk_jpegenc_comp_dev *jpeg)
> +{
> +	clk_bulk_disable_unprepare(jpeg->venc_clk.clk_num,
> +				?? jpeg->venc_clk.clks);
> +}
> +
> +static __maybe_unused int mtk_jpegenc_pm_suspend(struct device *dev)
> +{
> +	struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev);
> +
> +	mtk_jpeg_clk_off(jpeg);
> ?
> ?	return 0;
> ?}
> ?
> +static __maybe_unused int mtk_jpegenc_pm_resume(struct device *dev)
> +{
> +	struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev);
> +
> +	mtk_jpeg_clk_on(jpeg);
> +
> +	return 0;
> +}
> +
> +static __maybe_unused int mtk_jpegenc_suspend(struct device *dev)
> +{
> +	struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev);
> +
> +	v4l2_m2m_suspend(jpeg->master_dev->m2m_dev);
> +	return pm_runtime_force_suspend(dev);
> +}
> +
> +static __maybe_unused int mtk_jpegenc_resume(struct device *dev)
> +{
> +	struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev);
> +	int ret;
> +
> +	ret = pm_runtime_force_resume(dev);
> +	if (ret < 0)
> +		return ret;
> +
> +	v4l2_m2m_resume(jpeg->master_dev->m2m_dev);
> +	return ret;
> +}
> +
> +static const struct dev_pm_ops mtk_jpegenc_pm_ops = {
> +	SET_SYSTEM_SLEEP_PM_OPS(mtk_jpegenc_suspend, mtk_jpegenc_resume)
> +	SET_RUNTIME_PM_OPS(mtk_jpegenc_pm_suspend, mtk_jpegenc_pm_resume, NULL)
> +};
> +
> ?static struct platform_driver mtk_jpegenc_hw_driver = {
> ?	.probe = mtk_jpegenc_hw_probe,
> ?	.driver = {
> ?		.name = "mtk-jpegenc-hw",
> ?		.of_match_table = mtk_jpegenc_drv_ids,
> +		.pm = &mtk_jpegenc_pm_ops,
> ?	},
> ?};
> ?


From nicolas at ndufresne.ca  Fri May 30 10:45:46 2025
From: nicolas at ndufresne.ca (Nicolas Dufresne)
Date: Fri, 30 May 2025 13:45:46 -0400
Subject: [PATCH v5 00/12] Enable jpeg enc & dec multi-hardwares for
 MT8196
In-Reply-To: <20250530074537.26338-1-kyrie.wu@mediatek.com>
References: <20250530074537.26338-1-kyrie.wu@mediatek.com>
Message-ID: <23ace820d130e5d18c599d29e960652be49e1457.camel@ndufresne.ca>

Hi,

Le vendredi 30 mai 2025 ? 15:45 +0800, Kyrie Wu a ?crit?:
> This series adds support for mt8196 multi-hardwares jpeg enc & dec,
> by first adding mt8196 jpegdec and jpegenc compatible to install
> kernel driver. Add smmu setting to support smmu and iommu at the
> same time.
> Secondly refactor buffer and clock setting to support multi-hw jpeg
> working.
> Lastly, fix some bugs, including resolution change handleing, stop
> streaming sw flow and others.
> 
> This series has been tested with MT8196 tast test.
> Encoding and decoding worked for this chip.
> 
> Patches 1-3 Adds jpeg encoder and decoder compatible.
> Patches 4 add jpeg smmu sid setting.
> Patches 5 fix jpeg hw count setting to support different chips.
> Patches 6 refactor jpeg buffer payload setting to handle buffer
> size bug while resolution changed.
> Patches 7 reconstruct jpeg dst buffer layout.
> Patches 8 fix multi-core stop streaming flow
> Patches 9 refactor multi-core clk suspend/resume setting
> Patches 10 fix decoding buffer number setting timing issue
> Patches 11 refactor decoding resolution change operation
> Patches 12 fix remove buffer operation

Just general comment, you built your patchset up-side-down. Start
with the fixes of things that was already broken, then do your multi-core
support refactoring, and only then add MT8196. Looking for a v6 with
a re-organization of the set.

Nicolas

> 
> ---
> This series patches dependent on:
> [1]
> https://patchwork.linuxtv.org/project/linux-media/patch/20250424090824.5309-1-jianhua.lin at mediatek.com/
> 
> Changes compared with v4:
> --fix kernel robot build errors for patch 4.
> --add reviewer for patch 1 and patch 2.
> 
> Changes compared with v3:
> --change patch subject of jpeg encoder and decoder compatible.
> 
> Changes compared with v2:
> --refactor smmu sid setting function interface
> --Some modifications for patch v2's review comments.
> 
> Changes compared with v1:
> --refine jpeg dt-bindings for MT8196
> --optimize software code to manage jpeg HW count
> --refactor smmu sid setting function interface
> --Some modifications for patch v1's review comments.
> 
> Kyrie Wu (12):
> ? media: dt-bindings: mediatek,jpeg: Add mediatek, mt8196-jpgdec
> ??? compatible
> ? media: dt-bindings: mediatek,jpeg: Add mediatek, mt8196-jpgenc
> ??? compatible
> ? media: mediatek: jpeg: add jpeg compatible
> ? media: mediatek: jpeg: add jpeg smmu sid setting
> ? media: mediatek: jpeg: fix jpeg hw count setting
> ? media: mediatek: jpeg: refactor jpeg buffer payload setting
> ? media: mediatek: jpeg: refactor jpeg dst buffer layout
> ? media: mediatek: jpeg: fix stop streaming flow for multi-core
> ? media: mediatek: jpeg: refactor multi-core clk suspend and resume
> ??? setting
> ? media: mediatek: jpeg: fix decoding buffer number setting timing issue
> ? media: mediatek: jpeg: refactor decoding resolution change operation
> ? media: mediatek: jpeg: fix remove buffer operation for multi-core
> 
> ?.../media/mediatek,mt8195-jpegdec.yaml??????? |?? 8 +-
> ?.../media/mediatek,mt8195-jpegenc.yaml??????? |?? 8 +-
> ?.../platform/mediatek/jpeg/mtk_jpeg_core.c??? | 169 +++++++++++++-----
> ?.../platform/mediatek/jpeg/mtk_jpeg_core.h??? |? 21 ++-
> ?.../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c? | 112 +++++++++++-
> ?.../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c? | 112 +++++++++++-
> ?6 files changed, 377 insertions(+), 53 deletions(-)


From horms at kernel.org  Fri May 30 11:05:01 2025
From: horms at kernel.org (Simon Horman)
Date: Fri, 30 May 2025 19:05:01 +0100
Subject: [PATCH net 1/2] net: airoha: Initialize PPE UPDMEM source-mac
 table
In-Reply-To: <20250529-airoha-flowtable-ipv6-fix-v1-1-7c7e53ae0854@kernel.org>
References: <20250529-airoha-flowtable-ipv6-fix-v1-0-7c7e53ae0854@kernel.org>
 <20250529-airoha-flowtable-ipv6-fix-v1-1-7c7e53ae0854@kernel.org>
Message-ID: <20250530180501.GQ1484967@horms.kernel.org>

On Thu, May 29, 2025 at 05:52:37PM +0200, Lorenzo Bianconi wrote:
> UPDMEM source-mac table is a key-value map used to store devices mac
> addresses according to the port identifier. UPDMEM source mac table is
> used during IPv6 traffic hw acceleration since PPE entries, for space
> constraints, do not contain the full source mac address but just the
> identifier in the UPDMEM source-mac table.

Hi Lorenzo,

I think it would be nice to also mention a bit more clearly what (broken)
behaviour this fixes. Likewise for patch 2/2.

> 
> Fixes: 00a7678310fe ("net: airoha: Introduce flowtable offload support")
> Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>

...


From horms at kernel.org  Fri May 30 11:06:37 2025
From: horms at kernel.org (Simon Horman)
Date: Fri, 30 May 2025 19:06:37 +0100
Subject: [PATCH net 2/2] net: airoha: Fix IPv6 hw acceleration in bridge
 mode
In-Reply-To: <20250529-airoha-flowtable-ipv6-fix-v1-2-7c7e53ae0854@kernel.org>
References: <20250529-airoha-flowtable-ipv6-fix-v1-0-7c7e53ae0854@kernel.org>
 <20250529-airoha-flowtable-ipv6-fix-v1-2-7c7e53ae0854@kernel.org>
Message-ID: <20250530180637.GR1484967@horms.kernel.org>

On Thu, May 29, 2025 at 05:52:38PM +0200, Lorenzo Bianconi wrote:
> ib2 and airoha_foe_mac_info_common have not the same offsets in
> airoha_foe_bridge and airoha_foe_ipv6 structures. Fix IPv6 hw
> acceleration in bridge mode resolving ib2 and airoha_foe_mac_info_common
> overwrite in airoha_ppe_foe_commit_subflow_entry routine.

I'd lean towards splitting this into two patches. One to address the issue
described above, and one to address the issue described below.

> Moreover, set
> AIROHA_FOE_MAC_SMAC_ID to 0xf in airoha_ppe_foe_commit_subflow_entry()
> to configure the PPE module to keep original source mac address of the
> bridged packets.
> 
> Fixes: cd53f622611f ("net: airoha: Add L2 hw acceleration support")
> Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>

...


From linux at fw-web.de  Sat May 31 04:24:23 2025
From: linux at fw-web.de (Frank Wunderlich)
Date: Sat, 31 May 2025 13:24:23 +0200
Subject: [PATCH v2] dt-bindings: interconnect: add mt7988-cci compatible
Message-ID: <20250531112425.10525-1-linux@fw-web.de>

From: Frank Wunderlich <frank-w at public-files.de>

Add compatible for Mediatek MT7988 SoC with mediatek,mt8183-cci fallback
which is taken by driver.

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
v2:
- no RFC
- drop "items" as sugested by conor
---
 .../bindings/interconnect/mediatek,cci.yaml           | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
index 58611ba2a0f4..4d72525f407e 100644
--- a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
+++ b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
@@ -17,9 +17,14 @@ description: |
 
 properties:
   compatible:
-    enum:
-      - mediatek,mt8183-cci
-      - mediatek,mt8186-cci
+    oneOf:
+      - enum:
+          - mediatek,mt8183-cci
+          - mediatek,mt8186-cci
+      - items:
+          - enum:
+              - mediatek,mt7988-cci
+          - const: mediatek,mt8183-cci
 
   clocks:
     items:
-- 
2.43.0



From uwu at icenowy.me  Sat May 31 05:11:40 2025
From: uwu at icenowy.me (Icenowy Zheng)
Date: Sat, 31 May 2025 20:11:40 +0800
Subject: [PATCH] drm/mediatek: only announce AFBC if really supported
Message-ID: <20250531121140.387661-1-uwu@icenowy.me>

Currently even the SoC's OVL does not declare the support of AFBC, AFBC
is still announced to the userspace within the IN_FORMATS blob, which
breaks modern Wayland compositors like KWin Wayland and others.

Gate passing modifiers to drm_universal_plane_init() behind querying the
driver of the hardware block for AFBC support.

Fixes: c410fa9b07c3 ("drm/mediatek: Add AFBC support to Mediatek DRM driver")
Signed-off-by: Icenowy Zheng <uwu at icenowy.me>
---
Patch tested on MT8183, on which KWin Wayland 5.27.12 is fixed.

In addition, I tried to fake supports_afbc in mt8183_ovl_driver_data and
mt8183_ovl_2l_driver_data, then KWin Wayland gets broken again and
modetest also shows the AFBC modifier in IN_FORMATS.

 drivers/gpu/drm/mediatek/mtk_crtc.c     | 3 ++-
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 1 +
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 9 +++++++++
 drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 7 +++++++
 drivers/gpu/drm/mediatek/mtk_plane.c    | 7 +++++--
 drivers/gpu/drm/mediatek/mtk_plane.h    | 3 ++-
 7 files changed, 27 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c
index 8f6fba4217ece..53359c2465b65 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.c
@@ -930,7 +930,8 @@ static int mtk_crtc_init_comp_planes(struct drm_device *drm_dev,
 				mtk_ddp_comp_supported_rotations(comp),
 				mtk_ddp_comp_get_blend_modes(comp),
 				mtk_ddp_comp_get_formats(comp),
-				mtk_ddp_comp_get_num_formats(comp), i);
+				mtk_ddp_comp_get_num_formats(comp),
+				mtk_ddp_comp_is_afbc_supported(comp), i);
 		if (ret)
 			return ret;
 
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index edc6417639e64..ac6620e10262e 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -366,6 +366,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
 	.get_blend_modes = mtk_ovl_get_blend_modes,
 	.get_formats = mtk_ovl_get_formats,
 	.get_num_formats = mtk_ovl_get_num_formats,
+	.is_afbc_supported = mtk_ovl_is_afbc_supported,
 };
 
 static const struct mtk_ddp_comp_funcs ddp_postmask = {
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index 39720b27f4e9e..7289b3dcf22f2 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -83,6 +83,7 @@ struct mtk_ddp_comp_funcs {
 	u32 (*get_blend_modes)(struct device *dev);
 	const u32 *(*get_formats)(struct device *dev);
 	size_t (*get_num_formats)(struct device *dev);
+	bool (*is_afbc_supported)(struct device *dev);
 	void (*connect)(struct device *dev, struct device *mmsys_dev, unsigned int next);
 	void (*disconnect)(struct device *dev, struct device *mmsys_dev, unsigned int next);
 	void (*add)(struct device *dev, struct mtk_mutex *mutex);
@@ -294,6 +295,14 @@ size_t mtk_ddp_comp_get_num_formats(struct mtk_ddp_comp *comp)
 	return 0;
 }
 
+static inline bool mtk_ddp_comp_is_afbc_supported(struct mtk_ddp_comp *comp)
+{
+	if (comp->funcs && comp->funcs->is_afbc_supported)
+		return comp->funcs->is_afbc_supported(comp->dev);
+
+	return false;
+}
+
 static inline bool mtk_ddp_comp_add(struct mtk_ddp_comp *comp, struct mtk_mutex *mutex)
 {
 	if (comp->funcs && comp->funcs->add) {
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 04217a36939cd..679d413bf10be 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -106,6 +106,7 @@ void mtk_ovl_disable_vblank(struct device *dev);
 u32 mtk_ovl_get_blend_modes(struct device *dev);
 const u32 *mtk_ovl_get_formats(struct device *dev);
 size_t mtk_ovl_get_num_formats(struct device *dev);
+bool mtk_ovl_is_afbc_supported(struct device *dev);
 
 void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex);
 void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index d0581c4e3c999..e0236353d4997 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -236,6 +236,13 @@ size_t mtk_ovl_get_num_formats(struct device *dev)
 	return ovl->data->num_formats;
 }
 
+bool mtk_ovl_is_afbc_supported(struct device *dev)
+{
+	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
+
+	return ovl->data->supports_afbc;
+}
+
 int mtk_ovl_clk_enable(struct device *dev)
 {
 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediatek/mtk_plane.c
index 655106bbb76d3..e08b771bc25e9 100644
--- a/drivers/gpu/drm/mediatek/mtk_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_plane.c
@@ -321,7 +321,8 @@ static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = {
 int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
 		   unsigned long possible_crtcs, enum drm_plane_type type,
 		   unsigned int supported_rotations, const u32 blend_modes,
-		   const u32 *formats, size_t num_formats, unsigned int plane_idx)
+		   const u32 *formats, size_t num_formats,
+		   bool supports_afbc, unsigned int plane_idx)
 {
 	int err;
 
@@ -332,7 +333,9 @@ int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
 
 	err = drm_universal_plane_init(dev, plane, possible_crtcs,
 				       &mtk_plane_funcs, formats,
-				       num_formats, modifiers, type, NULL);
+				       num_formats,
+				       supports_afbc ? modifiers : NULL,
+				       type, NULL);
 	if (err) {
 		DRM_ERROR("failed to initialize plane\n");
 		return err;
diff --git a/drivers/gpu/drm/mediatek/mtk_plane.h b/drivers/gpu/drm/mediatek/mtk_plane.h
index 3b13b89989c7e..95c5fa5295d8a 100644
--- a/drivers/gpu/drm/mediatek/mtk_plane.h
+++ b/drivers/gpu/drm/mediatek/mtk_plane.h
@@ -49,5 +49,6 @@ to_mtk_plane_state(struct drm_plane_state *state)
 int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
 		   unsigned long possible_crtcs, enum drm_plane_type type,
 		   unsigned int supported_rotations, const u32 blend_modes,
-		   const u32 *formats, size_t num_formats, unsigned int plane_idx);
+		   const u32 *formats, size_t num_formats,
+		   bool supports_afbc, unsigned int plane_idx);
 #endif
-- 
2.49.0



From ansuelsmth at gmail.com  Sat May 31 06:29:48 2025
From: ansuelsmth at gmail.com (Christian Marangi)
Date: Sat, 31 May 2025 15:29:48 +0200
Subject: [PATCH 2/6] pinctrl: mediatek: airoha: generalize
 pins/group/function/confs handling
In-Reply-To: <aDbESUHdO4DgOtsm@lore-desk>
References: <20250527222040.32000-1-ansuelsmth@gmail.com>
 <20250527222040.32000-3-ansuelsmth@gmail.com>
 <aDbESUHdO4DgOtsm@lore-desk>
Message-ID: <683b044e.050a0220.11338b.f6c8@mx.google.com>

On Wed, May 28, 2025 at 10:07:37AM +0200, Lorenzo Bianconi wrote:
> > In preparation for support of Airoha AN7583, generalize
> > pins/group/function/confs handling and move them in match_data.
> > Inner function will base the values on the pinctrl priv struct instead of
> > relying on hardcoded struct.
> > 
> > This permits to use different PIN data while keeping the same logic.
> > 
> > Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> 
> Hi Christian,
> 
> I think the approach is fine, just some comments inline.
> 
> Regards,
> Lorenzo
> 
> > ---
> >  drivers/pinctrl/mediatek/pinctrl-airoha.c | 569 ++++++++++++----------
> >  1 file changed, 319 insertions(+), 250 deletions(-)
> > 
> > diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> > index 8ef7f88477aa..8af9109db992 100644
> > --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
> > +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> > @@ -30,20 +30,20 @@
> >  #include "../pinconf.h"
> >  #include "../pinmux.h"
> >  
> > -#define PINCTRL_PIN_GROUP(id)						\
> > -	PINCTRL_PINGROUP(#id, id##_pins, ARRAY_SIZE(id##_pins))
> > +#define PINCTRL_PIN_GROUP(id, table)					\
> 
> since this is now just used for the name pointer, I guess you can rename it in
> "name".
>

Sure.

> > +	PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))
> >  
> > -#define PINCTRL_FUNC_DESC(id)						\
> > +#define PINCTRL_FUNC_DESC(id, table)					\
> >  	{								\
> >  		.desc = {						\
> >  			.func = {					\
> > -				.name = #id,				\
> > -				.groups = id##_groups,			\
> > -				.ngroups = ARRAY_SIZE(id##_groups),	\
> > +				.name = id,				\
> > +				.groups = table##_groups,		\
> > +				.ngroups = ARRAY_SIZE(table##_groups),	\
> >  			}						\
> >  		},							\
> > -		.groups = id##_func_group,				\
> > -		.group_size = ARRAY_SIZE(id##_func_group),		\
> > +		.groups = table##_func_group,				\
> > +		.group_size = ARRAY_SIZE(table##_func_group),		\
> >  	}
> >  
> >  #define PINCTRL_CONF_DESC(p, offset, mask)				\
> > @@ -359,16 +359,46 @@ struct airoha_pinctrl_gpiochip {
> >  	u32 irq_type[AIROHA_NUM_PINS];
> >  };
> >  
> > +struct airoha_pinctrl_confs_info {
> > +	const struct airoha_pinctrl_conf *confs;
> > +	unsigned int num_confs;
> > +};
> > +
> > +enum airoha_pinctrl_confs_type {
> > +	AIROHA_PINCTRL_CONFS_PULLUP,
> > +	AIROHA_PINCTRL_CONFS_PULLDOWN,
> > +	AIROHA_PINCTRL_CONFS_DRIVE_E2,
> > +	AIROHA_PINCTRL_CONFS_DRIVE_E4,
> > +	AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
> > +
> > +	AIROHA_PINCTRL_CONFS_MAX,
> 
> I guess with the approach suggested below we can get rid of AIROHA_PINCTRL_CONFS_MAX
> 
> > +};
> > +
> >  struct airoha_pinctrl {
> >  	struct pinctrl_dev *ctrl;
> >  
> > +	struct pinctrl_desc desc;
> > +	const struct pingroup *grps;
> > +	const struct airoha_pinctrl_func *funcs;
> > +	const struct airoha_pinctrl_confs_info *confs_info;
> > +
> >  	struct regmap *chip_scu;
> >  	struct regmap *regmap;
> >  
> >  	struct airoha_pinctrl_gpiochip gpiochip;
> >  };
> >  
> > -static struct pinctrl_pin_desc airoha_pinctrl_pins[] = {
> > +struct airoha_pinctrl_match_data {
> > +	const struct pinctrl_pin_desc *pins;
> > +	const unsigned int num_pins;
> > +	const struct pingroup *grps;
> > +	const unsigned int num_grps;
> > +	const struct airoha_pinctrl_func *funcs;
> > +	const unsigned int num_funcs;
> > +	const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
> 
> In order to generalize the approach, I guess we can use a
> airoha_pinctrl_confs_info pointer here, something like:
> 
> 	const struct airoha_pinctrl_confs_info *confs_info;
> 	const unsigned int num_confs;
> 

You mean putting the entry on a dedicated table.

For num confs I'm not sure as we use the same function and in theory
every pinctrl needs to define them.

> > +};
> > +
> > +static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
> >  	PINCTRL_PIN(0, "uart1_txd"),
> >  	PINCTRL_PIN(1, "uart1_rxd"),
> >  	PINCTRL_PIN(2, "i2c_scl"),
> > @@ -429,172 +459,172 @@ static struct pinctrl_pin_desc airoha_pinctrl_pins[] = {
> >  	PINCTRL_PIN(63, "pcie_reset2"),
> >  };
> >  
> > -static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 };
> > -static const int pon_tod_1pps_pins[] = { 46 };
> > -static const int gsw_tod_1pps_pins[] = { 46 };
> > -static const int sipo_pins[] = { 16, 17 };
> > -static const int sipo_rclk_pins[] = { 16, 17, 43 };
> > -static const int mdio_pins[] = { 14, 15 };
> > -static const int uart2_pins[] = { 48, 55 };
> > -static const int uart2_cts_rts_pins[] = { 46, 47 };
> > -static const int hsuart_pins[] = { 28, 29 };
> > -static const int hsuart_cts_rts_pins[] = { 26, 27 };
> > -static const int uart4_pins[] = { 38, 39 };
> > -static const int uart5_pins[] = { 18, 19 };
> > -static const int i2c0_pins[] = { 2, 3 };
> > -static const int i2c1_pins[] = { 14, 15 };
> > -static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
> > -static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
> > -static const int i2s_pins[] = { 26, 27, 28, 29 };
> > -static const int pcm1_pins[] = { 22, 23, 24, 25 };
> > -static const int pcm2_pins[] = { 18, 19, 20, 21 };
> > -static const int spi_quad_pins[] = { 32, 33 };
> > -static const int spi_pins[] = { 4, 5, 6, 7 };
> > -static const int spi_cs1_pins[] = { 34 };
> > -static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
> > -static const int pcm_spi_int_pins[] = { 14 };
> > -static const int pcm_spi_rst_pins[] = { 15 };
> > -static const int pcm_spi_cs1_pins[] = { 43 };
> > -static const int pcm_spi_cs2_pins[] = { 40 };
> > -static const int pcm_spi_cs2_p128_pins[] = { 40 };
> > -static const int pcm_spi_cs2_p156_pins[] = { 40 };
> > -static const int pcm_spi_cs3_pins[] = { 41 };
> > -static const int pcm_spi_cs4_pins[] = { 42 };
> > -static const int emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
> > -static const int pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
> > -static const int gpio0_pins[] = { 13 };
> > -static const int gpio1_pins[] = { 14 };
> > -static const int gpio2_pins[] = { 15 };
> > -static const int gpio3_pins[] = { 16 };
> > -static const int gpio4_pins[] = { 17 };
> > -static const int gpio5_pins[] = { 18 };
> > -static const int gpio6_pins[] = { 19 };
> > -static const int gpio7_pins[] = { 20 };
> > -static const int gpio8_pins[] = { 21 };
> > -static const int gpio9_pins[] = { 22 };
> > -static const int gpio10_pins[] = { 23 };
> > -static const int gpio11_pins[] = { 24 };
> > -static const int gpio12_pins[] = { 25 };
> > -static const int gpio13_pins[] = { 26 };
> > -static const int gpio14_pins[] = { 27 };
> > -static const int gpio15_pins[] = { 28 };
> > -static const int gpio16_pins[] = { 29 };
> > -static const int gpio17_pins[] = { 30 };
> > -static const int gpio18_pins[] = { 31 };
> > -static const int gpio19_pins[] = { 32 };
> > -static const int gpio20_pins[] = { 33 };
> > -static const int gpio21_pins[] = { 34 };
> > -static const int gpio22_pins[] = { 35 };
> > -static const int gpio23_pins[] = { 36 };
> > -static const int gpio24_pins[] = { 37 };
> > -static const int gpio25_pins[] = { 38 };
> > -static const int gpio26_pins[] = { 39 };
> > -static const int gpio27_pins[] = { 40 };
> > -static const int gpio28_pins[] = { 41 };
> > -static const int gpio29_pins[] = { 42 };
> > -static const int gpio30_pins[] = { 43 };
> > -static const int gpio31_pins[] = { 44 };
> > -static const int gpio33_pins[] = { 46 };
> > -static const int gpio34_pins[] = { 47 };
> > -static const int gpio35_pins[] = { 48 };
> > -static const int gpio36_pins[] = { 49 };
> > -static const int gpio37_pins[] = { 50 };
> > -static const int gpio38_pins[] = { 51 };
> > -static const int gpio39_pins[] = { 52 };
> > -static const int gpio40_pins[] = { 53 };
> > -static const int gpio41_pins[] = { 54 };
> > -static const int gpio42_pins[] = { 55 };
> > -static const int gpio43_pins[] = { 56 };
> > -static const int gpio44_pins[] = { 57 };
> > -static const int gpio45_pins[] = { 58 };
> > -static const int gpio46_pins[] = { 59 };
> > -static const int pcie_reset0_pins[] = { 61 };
> > -static const int pcie_reset1_pins[] = { 62 };
> > -static const int pcie_reset2_pins[] = { 63 };
> > -
> > -static const struct pingroup airoha_pinctrl_groups[] = {
> > -	PINCTRL_PIN_GROUP(pon),
> > -	PINCTRL_PIN_GROUP(pon_tod_1pps),
> > -	PINCTRL_PIN_GROUP(gsw_tod_1pps),
> > -	PINCTRL_PIN_GROUP(sipo),
> > -	PINCTRL_PIN_GROUP(sipo_rclk),
> > -	PINCTRL_PIN_GROUP(mdio),
> > -	PINCTRL_PIN_GROUP(uart2),
> > -	PINCTRL_PIN_GROUP(uart2_cts_rts),
> > -	PINCTRL_PIN_GROUP(hsuart),
> > -	PINCTRL_PIN_GROUP(hsuart_cts_rts),
> > -	PINCTRL_PIN_GROUP(uart4),
> > -	PINCTRL_PIN_GROUP(uart5),
> > -	PINCTRL_PIN_GROUP(i2c0),
> > -	PINCTRL_PIN_GROUP(i2c1),
> > -	PINCTRL_PIN_GROUP(jtag_udi),
> > -	PINCTRL_PIN_GROUP(jtag_dfd),
> > -	PINCTRL_PIN_GROUP(i2s),
> > -	PINCTRL_PIN_GROUP(pcm1),
> > -	PINCTRL_PIN_GROUP(pcm2),
> > -	PINCTRL_PIN_GROUP(spi),
> > -	PINCTRL_PIN_GROUP(spi_quad),
> > -	PINCTRL_PIN_GROUP(spi_cs1),
> > -	PINCTRL_PIN_GROUP(pcm_spi),
> > -	PINCTRL_PIN_GROUP(pcm_spi_int),
> > -	PINCTRL_PIN_GROUP(pcm_spi_rst),
> > -	PINCTRL_PIN_GROUP(pcm_spi_cs1),
> > -	PINCTRL_PIN_GROUP(pcm_spi_cs2_p128),
> > -	PINCTRL_PIN_GROUP(pcm_spi_cs2_p156),
> > -	PINCTRL_PIN_GROUP(pcm_spi_cs2),
> > -	PINCTRL_PIN_GROUP(pcm_spi_cs3),
> > -	PINCTRL_PIN_GROUP(pcm_spi_cs4),
> > -	PINCTRL_PIN_GROUP(emmc),
> > -	PINCTRL_PIN_GROUP(pnand),
> > -	PINCTRL_PIN_GROUP(gpio0),
> > -	PINCTRL_PIN_GROUP(gpio1),
> > -	PINCTRL_PIN_GROUP(gpio2),
> > -	PINCTRL_PIN_GROUP(gpio3),
> > -	PINCTRL_PIN_GROUP(gpio4),
> > -	PINCTRL_PIN_GROUP(gpio5),
> > -	PINCTRL_PIN_GROUP(gpio6),
> > -	PINCTRL_PIN_GROUP(gpio7),
> > -	PINCTRL_PIN_GROUP(gpio8),
> > -	PINCTRL_PIN_GROUP(gpio9),
> > -	PINCTRL_PIN_GROUP(gpio10),
> > -	PINCTRL_PIN_GROUP(gpio11),
> > -	PINCTRL_PIN_GROUP(gpio12),
> > -	PINCTRL_PIN_GROUP(gpio13),
> > -	PINCTRL_PIN_GROUP(gpio14),
> > -	PINCTRL_PIN_GROUP(gpio15),
> > -	PINCTRL_PIN_GROUP(gpio16),
> > -	PINCTRL_PIN_GROUP(gpio17),
> > -	PINCTRL_PIN_GROUP(gpio18),
> > -	PINCTRL_PIN_GROUP(gpio19),
> > -	PINCTRL_PIN_GROUP(gpio20),
> > -	PINCTRL_PIN_GROUP(gpio21),
> > -	PINCTRL_PIN_GROUP(gpio22),
> > -	PINCTRL_PIN_GROUP(gpio23),
> > -	PINCTRL_PIN_GROUP(gpio24),
> > -	PINCTRL_PIN_GROUP(gpio25),
> > -	PINCTRL_PIN_GROUP(gpio26),
> > -	PINCTRL_PIN_GROUP(gpio27),
> > -	PINCTRL_PIN_GROUP(gpio28),
> > -	PINCTRL_PIN_GROUP(gpio29),
> > -	PINCTRL_PIN_GROUP(gpio30),
> > -	PINCTRL_PIN_GROUP(gpio31),
> > -	PINCTRL_PIN_GROUP(gpio33),
> > -	PINCTRL_PIN_GROUP(gpio34),
> > -	PINCTRL_PIN_GROUP(gpio35),
> > -	PINCTRL_PIN_GROUP(gpio36),
> > -	PINCTRL_PIN_GROUP(gpio37),
> > -	PINCTRL_PIN_GROUP(gpio38),
> > -	PINCTRL_PIN_GROUP(gpio39),
> > -	PINCTRL_PIN_GROUP(gpio40),
> > -	PINCTRL_PIN_GROUP(gpio41),
> > -	PINCTRL_PIN_GROUP(gpio42),
> > -	PINCTRL_PIN_GROUP(gpio43),
> > -	PINCTRL_PIN_GROUP(gpio44),
> > -	PINCTRL_PIN_GROUP(gpio45),
> > -	PINCTRL_PIN_GROUP(gpio46),
> > -	PINCTRL_PIN_GROUP(pcie_reset0),
> > -	PINCTRL_PIN_GROUP(pcie_reset1),
> > -	PINCTRL_PIN_GROUP(pcie_reset2),
> > +static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
> > +static const int en7581_pon_tod_1pps_pins[] = { 46 };
> > +static const int en7581_gsw_tod_1pps_pins[] = { 46 };
> > +static const int en7581_sipo_pins[] = { 16, 17 };
> > +static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
> > +static const int en7581_mdio_pins[] = { 14, 15 };
> > +static const int en7581_uart2_pins[] = { 48, 55 };
> > +static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
> > +static const int en7581_hsuart_pins[] = { 28, 29 };
> > +static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
> > +static const int en7581_uart4_pins[] = { 38, 39 };
> > +static const int en7581_uart5_pins[] = { 18, 19 };
> > +static const int en7581_i2c0_pins[] = { 2, 3 };
> > +static const int en7581_i2c1_pins[] = { 14, 15 };
> > +static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
> > +static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
> > +static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
> > +static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
> > +static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
> > +static const int en7581_spi_quad_pins[] = { 32, 33 };
> > +static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
> > +static const int en7581_spi_cs1_pins[] = { 34 };
> > +static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
> > +static const int en7581_pcm_spi_int_pins[] = { 14 };
> > +static const int en7581_pcm_spi_rst_pins[] = { 15 };
> > +static const int en7581_pcm_spi_cs1_pins[] = { 43 };
> > +static const int en7581_pcm_spi_cs2_pins[] = { 40 };
> > +static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
> > +static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
> > +static const int en7581_pcm_spi_cs3_pins[] = { 41 };
> > +static const int en7581_pcm_spi_cs4_pins[] = { 42 };
> > +static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
> > +static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
> > +static const int en7581_gpio0_pins[] = { 13 };
> > +static const int en7581_gpio1_pins[] = { 14 };
> > +static const int en7581_gpio2_pins[] = { 15 };
> > +static const int en7581_gpio3_pins[] = { 16 };
> > +static const int en7581_gpio4_pins[] = { 17 };
> > +static const int en7581_gpio5_pins[] = { 18 };
> > +static const int en7581_gpio6_pins[] = { 19 };
> > +static const int en7581_gpio7_pins[] = { 20 };
> > +static const int en7581_gpio8_pins[] = { 21 };
> > +static const int en7581_gpio9_pins[] = { 22 };
> > +static const int en7581_gpio10_pins[] = { 23 };
> > +static const int en7581_gpio11_pins[] = { 24 };
> > +static const int en7581_gpio12_pins[] = { 25 };
> > +static const int en7581_gpio13_pins[] = { 26 };
> > +static const int en7581_gpio14_pins[] = { 27 };
> > +static const int en7581_gpio15_pins[] = { 28 };
> > +static const int en7581_gpio16_pins[] = { 29 };
> > +static const int en7581_gpio17_pins[] = { 30 };
> > +static const int en7581_gpio18_pins[] = { 31 };
> > +static const int en7581_gpio19_pins[] = { 32 };
> > +static const int en7581_gpio20_pins[] = { 33 };
> > +static const int en7581_gpio21_pins[] = { 34 };
> > +static const int en7581_gpio22_pins[] = { 35 };
> > +static const int en7581_gpio23_pins[] = { 36 };
> > +static const int en7581_gpio24_pins[] = { 37 };
> > +static const int en7581_gpio25_pins[] = { 38 };
> > +static const int en7581_gpio26_pins[] = { 39 };
> > +static const int en7581_gpio27_pins[] = { 40 };
> > +static const int en7581_gpio28_pins[] = { 41 };
> > +static const int en7581_gpio29_pins[] = { 42 };
> > +static const int en7581_gpio30_pins[] = { 43 };
> > +static const int en7581_gpio31_pins[] = { 44 };
> > +static const int en7581_gpio33_pins[] = { 46 };
> > +static const int en7581_gpio34_pins[] = { 47 };
> > +static const int en7581_gpio35_pins[] = { 48 };
> > +static const int en7581_gpio36_pins[] = { 49 };
> > +static const int en7581_gpio37_pins[] = { 50 };
> > +static const int en7581_gpio38_pins[] = { 51 };
> > +static const int en7581_gpio39_pins[] = { 52 };
> > +static const int en7581_gpio40_pins[] = { 53 };
> > +static const int en7581_gpio41_pins[] = { 54 };
> > +static const int en7581_gpio42_pins[] = { 55 };
> > +static const int en7581_gpio43_pins[] = { 56 };
> > +static const int en7581_gpio44_pins[] = { 57 };
> > +static const int en7581_gpio45_pins[] = { 58 };
> > +static const int en7581_gpio46_pins[] = { 59 };
> > +static const int en7581_pcie_reset0_pins[] = { 61 };
> > +static const int en7581_pcie_reset1_pins[] = { 62 };
> > +static const int en7581_pcie_reset2_pins[] = { 63 };
> > +
> > +static const struct pingroup en7581_pinctrl_groups[] = {
> > +	PINCTRL_PIN_GROUP("pon", en7581_pon),
> > +	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
> > +	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
> > +	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
> > +	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
> > +	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
> > +	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
> > +	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
> > +	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
> > +	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
> > +	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
> > +	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
> > +	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
> > +	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
> > +	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
> > +	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
> > +	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
> > +	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
> > +	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
> > +	PINCTRL_PIN_GROUP("spi", en7581_spi),
> > +	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
> > +	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
> > +	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
> > +	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
> > +	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
> > +	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
> > +	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
> > +	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
> > +	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
> > +	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
> > +	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
> > +	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
> > +	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
> > +	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
> > +	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
> > +	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
> > +	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
> > +	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
> > +	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
> > +	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
> > +	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
> > +	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
> > +	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
> > +	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
> > +	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
> > +	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
> > +	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
> > +	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
> > +	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
> > +	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
> > +	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
> > +	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
> > +	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
> > +	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
> > +	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
> > +	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
> > +	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
> > +	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
> > +	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
> > +	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
> > +	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
> > +	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
> > +	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
> > +	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
> > +	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
> > +	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
> > +	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
> > +	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
> > +	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
> > +	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
> > +	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
> > +	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
> > +	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
> > +	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
> > +	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
> > +	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
> > +	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
> > +	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
> > +	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
> > +	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
> > +	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
> > +	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
> >  };
> >  
> >  static const char *const pon_groups[] = { "pon" };
> > @@ -1957,33 +1987,33 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
> >  	},
> >  };
> >  
> > -static const struct airoha_pinctrl_func airoha_pinctrl_funcs[] = {
> > -	PINCTRL_FUNC_DESC(pon),
> > -	PINCTRL_FUNC_DESC(tod_1pps),
> > -	PINCTRL_FUNC_DESC(sipo),
> > -	PINCTRL_FUNC_DESC(mdio),
> > -	PINCTRL_FUNC_DESC(uart),
> > -	PINCTRL_FUNC_DESC(i2c),
> > -	PINCTRL_FUNC_DESC(jtag),
> > -	PINCTRL_FUNC_DESC(pcm),
> > -	PINCTRL_FUNC_DESC(spi),
> > -	PINCTRL_FUNC_DESC(pcm_spi),
> > -	PINCTRL_FUNC_DESC(i2s),
> > -	PINCTRL_FUNC_DESC(emmc),
> > -	PINCTRL_FUNC_DESC(pnand),
> > -	PINCTRL_FUNC_DESC(pcie_reset),
> > -	PINCTRL_FUNC_DESC(pwm),
> > -	PINCTRL_FUNC_DESC(phy1_led0),
> > -	PINCTRL_FUNC_DESC(phy2_led0),
> > -	PINCTRL_FUNC_DESC(phy3_led0),
> > -	PINCTRL_FUNC_DESC(phy4_led0),
> > -	PINCTRL_FUNC_DESC(phy1_led1),
> > -	PINCTRL_FUNC_DESC(phy2_led1),
> > -	PINCTRL_FUNC_DESC(phy3_led1),
> > -	PINCTRL_FUNC_DESC(phy4_led1),
> > +static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
> > +	PINCTRL_FUNC_DESC("pon", pon),
> > +	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
> > +	PINCTRL_FUNC_DESC("sipo", sipo),
> > +	PINCTRL_FUNC_DESC("mdio", mdio),
> > +	PINCTRL_FUNC_DESC("uart", uart),
> > +	PINCTRL_FUNC_DESC("i2c", i2c),
> > +	PINCTRL_FUNC_DESC("jtag", jtag),
> > +	PINCTRL_FUNC_DESC("pcm", pcm),
> > +	PINCTRL_FUNC_DESC("spi", spi),
> > +	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
> > +	PINCTRL_FUNC_DESC("i2s", i2s),
> > +	PINCTRL_FUNC_DESC("emmc", emmc),
> > +	PINCTRL_FUNC_DESC("pnand", pnand),
> > +	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
> > +	PINCTRL_FUNC_DESC("pwm", pwm),
> > +	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
> > +	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
> > +	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
> > +	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
> > +	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
> > +	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
> > +	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
> > +	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
> >  };
> >  
> > -static const struct airoha_pinctrl_conf airoha_pinctrl_pullup_conf[] = {
> > +static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
> >  	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
> >  	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
> >  	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
> > @@ -2044,7 +2074,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_pullup_conf[] = {
> >  	PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
> >  };
> >  
> > -static const struct airoha_pinctrl_conf airoha_pinctrl_pulldown_conf[] = {
> > +static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
> >  	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
> >  	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
> >  	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
> > @@ -2105,7 +2135,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_pulldown_conf[] = {
> >  	PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
> >  };
> >  
> > -static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e2_conf[] = {
> > +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
> >  	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
> >  	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
> >  	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
> > @@ -2166,7 +2196,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e2_conf[] = {
> >  	PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
> >  };
> >  
> > -static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e4_conf[] = {
> > +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
> >  	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
> >  	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
> >  	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
> > @@ -2227,7 +2257,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e4_conf[] = {
> >  	PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
> >  };
> >  
> > -static const struct airoha_pinctrl_conf airoha_pinctrl_pcie_rst_od_conf[] = {
> > +static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
> >  	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
> >  	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
> >  	PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
> > @@ -2548,12 +2578,17 @@ airoha_pinctrl_get_conf_reg(const struct airoha_pinctrl_conf *conf,
> >  }
> >  
> >  static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,
> > -				   const struct airoha_pinctrl_conf *conf,
> > -				   int conf_size, int pin, u32 *val)
> > +				   enum airoha_pinctrl_confs_type conf_type,
> > +				   int pin, u32 *val)
> >  {
> > +	const struct airoha_pinctrl_confs_info *confs_info;
> >  	const struct airoha_pinctrl_reg *reg;
> >  
> > -	reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
> > +	confs_info = &pinctrl->confs_info[conf_type];
> > +
> > +	reg = airoha_pinctrl_get_conf_reg(confs_info->confs,
> > +					  confs_info->num_confs,
> > +					  pin);
> >  	if (!reg)
> >  		return -EINVAL;
> >  
> > @@ -2566,12 +2601,17 @@ static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,
> >  }
> >  
> >  static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
> > -				   const struct airoha_pinctrl_conf *conf,
> > -				   int conf_size, int pin, u32 val)
> > +				   enum airoha_pinctrl_confs_type conf_type,
> > +				   int pin, u32 val)
> >  {
> > +	const struct airoha_pinctrl_confs_info *confs_info;
> >  	const struct airoha_pinctrl_reg *reg = NULL;
> >  
> > -	reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
> > +	confs_info = &pinctrl->confs_info[conf_type];
> > +
> > +	reg = airoha_pinctrl_get_conf_reg(confs_info->confs,
> > +					  confs_info->num_confs,
> > +					  pin);
> >  	if (!reg)
> >  		return -EINVAL;
> >  
> > @@ -2584,44 +2624,34 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
> >  }
> >  
> >  #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)			\
> > -	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pullup_conf,		\
> > -				ARRAY_SIZE(airoha_pinctrl_pullup_conf),		\
> > +	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
> >  				(pin), (val))
> >  #define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val)			\
> > -	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pulldown_conf,	\
> > -				ARRAY_SIZE(airoha_pinctrl_pulldown_conf),	\
> > +	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,	\
> >  				(pin), (val))
> >  #define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val)			\
> > -	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e2_conf,	\
> > -				ARRAY_SIZE(airoha_pinctrl_drive_e2_conf),	\
> > +	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,	\
> >  				(pin), (val))
> >  #define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val)			\
> > -	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e4_conf,	\
> > -				ARRAY_SIZE(airoha_pinctrl_drive_e4_conf),	\
> > +	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,	\
> >  				(pin), (val))
> >  #define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val)			\
> > -	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf,	\
> > -				ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf),	\
> > +	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,	\
> >  				(pin), (val))
> >  #define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val)			\
> > -	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pullup_conf,		\
> > -				ARRAY_SIZE(airoha_pinctrl_pullup_conf),		\
> > +	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
> >  				(pin), (val))
> >  #define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val)			\
> > -	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pulldown_conf,	\
> > -				ARRAY_SIZE(airoha_pinctrl_pulldown_conf),	\
> > +	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,	\
> >  				(pin), (val))
> >  #define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val)			\
> > -	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e2_conf,	\
> > -				ARRAY_SIZE(airoha_pinctrl_drive_e2_conf),	\
> > +	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,	\
> >  				(pin), (val))
> >  #define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val)			\
> > -	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e4_conf,	\
> > -				ARRAY_SIZE(airoha_pinctrl_drive_e4_conf),	\
> > +	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,	\
> >  				(pin), (val))
> >  #define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val)			\
> > -	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf,	\
> > -				ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf),	\
> > +	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,	\
> >  				(pin), (val))
> >  
> >  static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
> > @@ -2798,12 +2828,13 @@ static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev,
> >  static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev,
> >  				    unsigned int group, unsigned long *config)
> >  {
> > +	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
> >  	u32 cur_config = 0;
> >  	int i;
> >  
> > -	for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
> > +	for (i = 0; i < pinctrl->grps[group].npins; i++) {
> >  		if (airoha_pinconf_get(pctrl_dev,
> > -				       airoha_pinctrl_groups[group].pins[i],
> > +				       pinctrl->grps[group].pins[i],
> >  				       config))
> >  			return -EOPNOTSUPP;
> >  
> > @@ -2820,13 +2851,14 @@ static int airoha_pinconf_group_set(struct pinctrl_dev *pctrl_dev,
> >  				    unsigned int group, unsigned long *configs,
> >  				    unsigned int num_configs)
> >  {
> > +	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
> >  	int i;
> >  
> > -	for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
> > +	for (i = 0; i < pinctrl->grps[group].npins; i++) {
> >  		int err;
> >  
> >  		err = airoha_pinconf_set(pctrl_dev,
> > -					 airoha_pinctrl_groups[group].pins[i],
> > +					 pinctrl->grps[group].pins[i],
> >  					 configs, num_configs);
> >  		if (err)
> >  			return err;
> > @@ -2852,23 +2884,16 @@ static const struct pinctrl_ops airoha_pctlops = {
> >  	.dt_free_map = pinconf_generic_dt_free_map,
> >  };
> >  
> > -static struct pinctrl_desc airoha_pinctrl_desc = {
> > -	.name = KBUILD_MODNAME,
> > -	.owner = THIS_MODULE,
> > -	.pctlops = &airoha_pctlops,
> > -	.pmxops = &airoha_pmxops,
> > -	.confops = &airoha_confops,
> > -	.pins = airoha_pinctrl_pins,
> > -	.npins = ARRAY_SIZE(airoha_pinctrl_pins),
> > -};
> > -
> >  static int airoha_pinctrl_probe(struct platform_device *pdev)
> >  {
> > +	const struct airoha_pinctrl_match_data *data;
> >  	struct device *dev = &pdev->dev;
> >  	struct airoha_pinctrl *pinctrl;
> >  	struct regmap *map;
> >  	int err, i;
> >  
> > +	data = device_get_match_data(dev);
> > +
> >  	pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
> >  	if (!pinctrl)
> >  		return -ENOMEM;
> > @@ -2883,14 +2908,23 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
> >  
> >  	pinctrl->chip_scu = map;
> >  
> > -	err = devm_pinctrl_register_and_init(dev, &airoha_pinctrl_desc,
> > +	/* Init pinctrl desc struct */
> > +	pinctrl->desc.name = KBUILD_MODNAME;
> > +	pinctrl->desc.owner = THIS_MODULE,
> > +	pinctrl->desc.pctlops = &airoha_pctlops,
> > +	pinctrl->desc.pmxops = &airoha_pmxops,
> > +	pinctrl->desc.confops = &airoha_confops,
> > +	pinctrl->desc.pins = data->pins,
> > +	pinctrl->desc.npins = data->num_pins,
> > +
> > +	err = devm_pinctrl_register_and_init(dev, &pinctrl->desc,
> >  					     pinctrl, &pinctrl->ctrl);
> >  	if (err)
> >  		return err;
> >  
> >  	/* build pin groups */
> > -	for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_groups); i++) {
> > -		const struct pingroup *grp = &airoha_pinctrl_groups[i];
> > +	for (i = 0; i < data->num_grps; i++) {
> > +		const struct pingroup *grp = &data->grps[i];
> >  
> >  		err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name,
> >  						grp->pins, grp->npins,
> > @@ -2903,10 +2937,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
> >  	}
> >  
> >  	/* build functions */
> > -	for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_funcs); i++) {
> > +	for (i = 0; i < data->num_funcs; i++) {
> >  		const struct airoha_pinctrl_func *func;
> >  
> > -		func = &airoha_pinctrl_funcs[i];
> > +		func = &data->funcs[i];
> >  		err = pinmux_generic_add_function(pinctrl->ctrl,
> >  						  func->desc.func.name,
> >  						  func->desc.func.groups,
> > @@ -2919,6 +2953,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
> >  		}
> >  	}
> >  
> > +	pinctrl->grps = data->grps;
> > +	pinctrl->funcs = data->funcs;
> > +	pinctrl->confs_info = data->confs_info;
> 
> I guess we can just use a airoha_pinctrl_match_data pointer here.
>

Yep it was to prevent too much redirection. Maybe I can just add to the
priv struct pointer to match_data ?

> > +
> >  	err = pinctrl_enable(pinctrl->ctrl);
> >  	if (err)
> >  		return err;
> > @@ -2927,8 +2965,39 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
> >  	return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
> >  }
> >  
> > +static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
> > +	.pins = en7581_pinctrl_pins,
> > +	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
> > +	.grps = en7581_pinctrl_groups,
> > +	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
> > +	.funcs = en7581_pinctrl_funcs,
> > +	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
> > +	.confs_info = {
> > +		[AIROHA_PINCTRL_CONFS_PULLUP] = {
> > +			.confs = en7581_pinctrl_pullup_conf,
> > +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
> > +		},
> > +		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
> > +			.confs = en7581_pinctrl_pulldown_conf,
> > +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
> > +		},
> > +		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
> > +			.confs = en7581_pinctrl_drive_e2_conf,
> > +			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
> > +		},
> > +		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
> > +			.confs = en7581_pinctrl_drive_e4_conf,
> > +			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
> > +		},
> > +		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
> > +			.confs = en7581_pinctrl_pcie_rst_od_conf,
> > +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
> > +		},
> > +	},
> > +};
> > +
> >  static const struct of_device_id airoha_pinctrl_of_match[] = {
> > -	{ .compatible = "airoha,en7581-pinctrl" },
> > +	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
> >  	{ /* sentinel */ }
> >  };
> >  MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
> > -- 
> > 2.48.1
> > 

-- 
	Ansuel


From xose.vazquez at gmail.com  Sat May 31 08:59:49 2025
From: xose.vazquez at gmail.com (Xose Vazquez Perez)
Date: Sat, 31 May 2025 17:59:49 +0200
Subject: [PATCH] ASoC: mt6660: delete MODULE_VERSION
Message-ID: <20250531155950.101164-1-xose.vazquez@gmail.com>

Cc: Liam Girdwood <lgirdwood at gmail.com>
Cc: Mark Brown <broonie at kernel.org>
Cc: Jaroslav Kysela <perex at perex.cz>
Cc: Takashi Iwai <tiwai at suse.com>
Cc: Matthias Brugger <matthias.bgg at gmail.com>
Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
Cc: SOUND ML <linux-sound at vger.kernel.org>
Cc: MEDIATEK ML <linux-mediatek at lists.infradead.org>
---
 sound/soc/codecs/mt6660.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/sound/soc/codecs/mt6660.c b/sound/soc/codecs/mt6660.c
index d16bccebae52..9415656f8285 100644
--- a/sound/soc/codecs/mt6660.c
+++ b/sound/soc/codecs/mt6660.c
@@ -578,4 +578,3 @@ module_i2c_driver(mt6660_i2c_driver);
 MODULE_AUTHOR("Jeff Chang <jeff_chang at richtek.com>");
 MODULE_DESCRIPTION("MT6660 SPKAMP Driver");
 MODULE_LICENSE("GPL");
-MODULE_VERSION("1.0.8_G");
-- 
2.49.0


From tglx at linutronix.de  Tue May  6 06:42:03 2025
From: tglx at linutronix.de (Thomas Gleixner)
Date: Tue, 06 May 2025 13:42:03 -0000
Subject: [PATCH v2 00/57] irqdomain: Cleanups and Documentation
In-Reply-To: <20250319092951.37667-1-jirislaby@kernel.org>
References: <20250319092951.37667-1-jirislaby@kernel.org>
Message-ID: <874ixxonyy.ffs@tglx>

On Wed, Mar 19 2025 at 10:28, Jiri Slaby wrote:

> Hi,
>
> tl;dr if patches are agreed upon, I ask subsys maintainers to take the
> respective ones via their trees (as they are split per subsys), so that
> the IRQ tree can take only the rest. That would minimize churn/conflicts
> during merges.

So. It's rc5 by now and I picked up everything which did not show up in
next yet. As there are some patches in next, I delayed the removal of
functions for the merge window so that we don't end up with merge
dependencies.

To reducde conflicts, I grabbed the irq branch from the PCI tree under
the assumption that this branch is stable.

The series sits now in

   git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/cleanups

and will be in next soon. If there are duplicates showing up in next,
I'm going to remove them from my branch, so the branch is not for basing
development on.

@Jiri, I fixed up all your subject prefixes as

  'irqdomain: subsys: Switch to foo()'

does not make any sense at all. These subsystems have their regular
prefixes and these changes do not justify made up irqdomain special
prefixes at all.

Thanks,

        tglx


From jirislaby at kernel.org  Mon May 12 02:56:22 2025
From: jirislaby at kernel.org (Jiri Slaby)
Date: Mon, 12 May 2025 09:56:22 -0000
Subject: [PATCH v2 00/57] irqdomain: Cleanups and Documentation
In-Reply-To: <874ixxonyy.ffs@tglx>
References: <20250319092951.37667-1-jirislaby@kernel.org>
 <874ixxonyy.ffs@tglx>
Message-ID: <a40c0dfc-b531-4cc0-80b2-5b972d9fb65c@kernel.org>

On 06. 05. 25, 15:41, Thomas Gleixner wrote:
> On Wed, Mar 19 2025 at 10:28, Jiri Slaby wrote:
> 
>> Hi,
>>
>> tl;dr if patches are agreed upon, I ask subsys maintainers to take the
>> respective ones via their trees (as they are split per subsys), so that
>> the IRQ tree can take only the rest. That would minimize churn/conflicts
>> during merges.
> 
> So. It's rc5 by now and I picked up everything

Good, thanks.

> which did not show up in next yet. 

Which is the majority -- routing through subsystems didn't work as well 
as I anticipated.

I planned to retry with v3 after the next merge window, but you were faster.

V3 contains a switch from nodes to dev_fwnode() in some cases. It 
simplifies the code there. This did not get lost, I will send this 
separately to maintainers once everything from this series settles in 
the tree. I.e. likely after the next merge window.

> @Jiri, I fixed up all your subject prefixes as
> 
>    'irqdomain: subsys: Switch to foo()'
> 
> does not make any sense at all. These subsystems have their regular
> prefixes and these changes do not justify made up irqdomain special
> prefixes at all.

Yes.

thanks,
-- 
js
suse labs


