[net PATCH] net: airoha: Fix wrong GDM4 register definition
Lorenzo Bianconi
lorenzo at kernel.org
Fri Jan 17 09:03:28 PST 2025
On Jan 17, Christian Marangi wrote:
> Fix wrong GDM4 register definition, in Airoha SDK GDM4 is defined at
> offset 0x2400 but this doesn't make sense as it does conflict with the
> CDM4 that is in the same location.
>
> Following the pattern where each GDM base is at the FWD_CFG, currently
> GDM4 base offset is set to 0x2500. This is correct but REG_GDM4_FWD_CFG
> and REG_GDM4_SRC_PORT_SET are still using the SDK reference with the
> 0x2400 offset. Fix these 2 define by subtracting 0x100 to each register
> to reflect the real address location.
Acked-by: Lorenzo Bianconi <lorenzo at kernel.org>
>
> Fixes: 23020f049327 ("net: airoha: Introduce ethernet support for EN7581 SoC")
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---
> drivers/net/ethernet/mediatek/airoha_regs.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/ethernet/mediatek/airoha_regs.h b/drivers/net/ethernet/mediatek/airoha_regs.h
> index e448b66b5334..30c96f679735 100644
> --- a/drivers/net/ethernet/mediatek/airoha_regs.h
> +++ b/drivers/net/ethernet/mediatek/airoha_regs.h
> @@ -249,11 +249,11 @@
> #define REG_GDM3_FWD_CFG GDM3_BASE
> #define GDM3_PAD_EN_MASK BIT(28)
>
> -#define REG_GDM4_FWD_CFG (GDM4_BASE + 0x100)
> +#define REG_GDM4_FWD_CFG GDM4_BASE
> #define GDM4_PAD_EN_MASK BIT(28)
> #define GDM4_SPORT_OFFSET0_MASK GENMASK(11, 8)
>
> -#define REG_GDM4_SRC_PORT_SET (GDM4_BASE + 0x33c)
> +#define REG_GDM4_SRC_PORT_SET (GDM4_BASE + 0x23c)
> #define GDM4_SPORT_OFF2_MASK GENMASK(19, 16)
> #define GDM4_SPORT_OFF1_MASK GENMASK(15, 12)
> #define GDM4_SPORT_OFF0_MASK GENMASK(11, 8)
> --
> 2.47.1
>
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