[PATCH v2 2/6] ASoC: dt-binding: Convert mt8183-afe-pcm binding to YAML

[Rob Herring]

On Wed, Aug 20, 2025 at 03:44:53PM +0200, Julien Massot wrote:
> Convert the MediaTek MT8183 AFE PCM Device Tree binding from the old
> .txt format to YAML schema format to improve validation.
> 
> While converting, also document all clock inputs and memory-region
> used by the AFE block.
> 
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Signed-off-by: Julien Massot <julien.massot at collabora.com>
> ---
>  .../bindings/sound/mediatek,mt8183-audio.yaml      | 228 +++++++++++++++++++++
>  .../devicetree/bindings/sound/mt8183-afe-pcm.txt   |  42 ----
>  2 files changed, 228 insertions(+), 42 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8183-audio.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8183-audio.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..93517565f0f3a692c824be0897bc88dfd59bd723
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8183-audio.yaml
> @@ -0,0 +1,228 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sound/mediatek,mt8183-audio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek AFE PCM controller for mt8183
> +
> +maintainers:
> +  - Julien Massot <jmassot at collabora.com>
> +
> +properties:
> +  compatible:
> +    const: mediatek,mt8183-audio
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  reset-names:
> +    const: audiosys
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  memory-region:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: AFE clock
> +      - description: ADDA DAC clock
> +      - description: ADDA DAC pre-distortion clock
> +      - description: ADDA ADC clock
> +      - description: ADDA6 ADC clock
> +      - description: Audio low-jitter 22.5792m clock
> +      - description: Audio low-jitter 24.576m clock
> +      - description: Audio PLL1 tuner clock
> +      - description: Audio PLL2 tuner clock
> +      - description: I2S1 bit clock
> +      - description: I2S2 bit clock
> +      - description: I2S3 bit clock
> +      - description: I2S4 bit clock
> +      - description: Audio Time-Division Multiplexing interface clock
> +      - description: Powerdown Audio test model clock
> +      - description: Audio infra sys clock
> +      - description: Audio infra 26M clock
> +      - description: Mux for audio clock
> +      - description: Mux for audio internal bus clock
> +      - description: Mux main divider by 4
> +      - description: Primary audio mux
> +      - description: Primary audio PLL
> +      - description: Secondary audio mux
> +      - description: Secondary audio PLL
> +      - description: Primary audio en-generator clock
> +      - description: Primary PLL divider by 4 for IEC
> +      - description: Secondary audio en-generator clock
> +      - description: Secondary PLL divider by 8 for IEC
> +      - description: Mux selector for I2S port 0
> +      - description: Mux selector for I2S port 1
> +      - description: Mux selector for I2S port 2
> +      - description: Mux selector for I2S port 3
> +      - description: Mux selector for I2S port 4
> +      - description: Mux selector for I2S port 5
> +      - description: APLL1 and APLL2 divider for I2S port 0
> +      - description: APLL1 and APLL2 divider for I2S port 1
> +      - description: APLL1 and APLL2 divider for I2S port 2
> +      - description: APLL1 and APLL2 divider for I2S port 3
> +      - description: APLL1 and APLL2 divider for I2S port 4
> +      - description: APLL1 and APLL2 divider for IEC
> +      - description: 26MHz clock for audio subsystem
> +
> +  clock-names:
> +    items:
> +      - const: aud_afe_clk
> +      - const: aud_dac_clk
> +      - const: aud_dac_predis_clk
> +      - const: aud_adc_clk
> +      - const: aud_adc_adda6_clk
> +      - const: aud_apll22m_clk
> +      - const: aud_apll24m_clk
> +      - const: aud_apll1_tuner_clk
> +      - const: aud_apll2_tuner_clk
> +      - const: aud_i2s1_bclk_sw
> +      - const: aud_i2s2_bclk_sw
> +      - const: aud_i2s3_bclk_sw
> +      - const: aud_i2s4_bclk_sw
> +      - const: aud_tdm_clk
> +      - const: aud_tml_clk
> +      - const: aud_infra_clk
> +      - const: mtkaif_26m_clk
> +      - const: top_mux_audio
> +      - const: top_mux_aud_intbus
> +      - const: top_syspll_d2_d4
> +      - const: top_mux_aud_1
> +      - const: top_apll1_ck
> +      - const: top_mux_aud_2
> +      - const: top_apll2_ck
> +      - const: top_mux_aud_eng1
> +      - const: top_apll1_d8
> +      - const: top_mux_aud_eng2
> +      - const: top_apll2_d8
> +      - const: top_i2s0_m_sel
> +      - const: top_i2s1_m_sel
> +      - const: top_i2s2_m_sel
> +      - const: top_i2s3_m_sel
> +      - const: top_i2s4_m_sel
> +      - const: top_i2s5_m_sel
> +      - const: top_apll12_div0
> +      - const: top_apll12_div1
> +      - const: top_apll12_div2
> +      - const: top_apll12_div3
> +      - const: top_apll12_div4
> +      - const: top_apll12_divb
> +      - const: top_clk26m_clk
> +
> +required:
> +  - compatible
> +  - interrupts
> +  - resets
> +  - reset-names
> +  - power-domains
> +  - clocks
> +  - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/mt8183-clk.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/power/mt8183-power.h>
> +    #include <dt-bindings/reset/mt8183-resets.h>
> +
> +    afe: mt8183-afe-pcm {

audio-controller {

like you changed the .dts.

With that,

Reviewed-by: Rob Herring (Arm) <robh at kernel.org>