[PATCH v4 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro

[Chen-Yu Tsai]

On Tue, Aug 5, 2025 at 10:55 PM Laura Nao <laura.nao at collabora.com> wrote:
>
> On MT8196, some clocks use one register for parent selection and
> gating, and a separate register for frequency division. Since composite
> clocks can combine a mux, divider, and gate in a single entity, add a
> macro to simplify registration of such clocks by combining parent
> selection, frequency scaling, and enable control into one definition.
>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado at collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Signed-off-by: Laura Nao <laura.nao at collabora.com>

Reviewed-by: Chen-Yu Tsai <wenst at chromium.org>