[PATCH v4 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control

[Chen-Yu Tsai]

On Tue, Aug 5, 2025 at 10:55 PM Laura Nao <laura.nao at collabora.com> wrote:
>
> On MT8196, there are set/clr registers to control a shared PLL enable
> register. These are intended to prevent different masters from
> manipulating the PLLs independently. Add the corresponding en_set_reg
> and en_clr_reg fields to the mtk_pll_data structure.
>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado at collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Signed-off-by: Laura Nao <laura.nao at collabora.com>

Reviewed-by: Chen-Yu Tsai <wenst at chromium.org>