[PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers

[Krzysztof Kozlowski]

On 01/08/2025 15:57, Rob Herring wrote:
>> +  reg:
>> +    maxItems: 1
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +  '#reset-cells':
>> +    const: 1
>> +    description:
>> +      Reset lines for PEXTP0/1 and UFS blocks.
>> +
>> +  mediatek,hardware-voter:
>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +    description:
>> +      On the MT8196 SoC, a Hardware Voter (HWV) backed by a fixed-function
>> +      MCU manages clock and power domain control across the AP and other
>> +      remote processors. By aggregating their votes, it ensures clocks are
>> +      safely enabled/disabled and power domains are active before register
>> +      access.
> 
> I thought this was going away based on v2 discussion?

Yes, I asked to drop it and do not include it in v3. There was also
discussion clarifying review.

I am really surprised that review meant nothing and code is still the same.

Best regards,
Krzysztof