[PATCH v5 0/8] Support Multi-frequency scale for UFS
Ziqi Chen
quic_ziqichen at quicinc.com
Mon Apr 28 01:06:19 PDT 2025
Hi Luca,
We made changes to fix this special platform issue and verified it can
fix this issue.
Could you help double check if attached 3 patched can fix it from you side?
If it is OK from you side as well, we will submit the final patches to
upstream
Thanks a lot~
BRs
Ziqi
On 4/27/2025 4:14 PM, Ziqi Chen wrote:
> Hi Luca,
>
> Thanks for your report.
> Really, 6350 is a special platform that the UFS_PHY_AXI_CLK doesn't
> match to the UFS_PHY_UNIPRO_CORE_CLK. We already found out the root
> cause and discussing the fix. We will submit change to fix this corner
> case.
>
> BRs
> Ziqi
>
> On 4/26/2025 3:48 AM, Luca Weiss wrote:
>> Hi Ziqi,
>>
>> On Thu Feb 13, 2025 at 9:00 AM CET, Ziqi Chen wrote:
>>> With OPP V2 enabled, devfreq can scale clocks amongst multiple frequency
>>> plans. However, the gear speed is only toggled between min and max
>>> during
>>> clock scaling. Enable multi-level gear scaling by mapping clock
>>> frequencies
>>> to gear speeds, so that when devfreq scales clock frequencies we can put
>>> the UFS link at the appropraite gear speeds accordingly.
>>
>> I believe this series is causing issues on SM6350:
>>
>> [ 0.859449] ufshcd-qcom 1d84000.ufshc: ufs_qcom_freq_to_gear_speed:
>> Unsupported clock freq : 200000000
>> [ 0.886668] ufshcd-qcom 1d84000.ufshc: UNIPRO clk freq 200 MHz not
>> supported
>> [ 0.903791] devfreq 1d84000.ufshc: dvfs failed with (-22) error
>>
>> That's with this patch, I actually haven't tried without on v6.15-rc3
>> https://lore.kernel.org/all/20250314-sm6350-ufs-things-
>> v1-2-3600362cc52c at fairphone.com/
>>
>> I believe the issue appears because core clk and unipro clk rates don't
>> match on this platform, so this 200 MHz for GCC_UFS_PHY_AXI_CLK is not a
>> valid unipro clock rate, but for GCC_UFS_PHY_UNIPRO_CORE_CLK it's
>> specified to 150 MHz in the opp table.
>>
>> Regards
>> Luca
>>
>>>
>>> This series has been tested on below platforms -
>>> sm8550 mtp + UFS3.1
>>> SM8650 MTP + UFS3.1
>>> SM8750 MTP + UFS4.0
>
-------------- next part --------------
From c36df86976b2d8d6c637f5a7872281c846866e43 Mon Sep 17 00:00:00 2001
From: Can Guo <quic_cang at quicinc.com>
Date: Sun, 27 Apr 2025 00:05:59 -0700
Subject: [PATCH 1/3] ufs: host: ufs-qcom: Map OPP freq to UniPro Core Clock
freq
Signed-off-by: Can Guo <quic_cang at quicinc.com>
---
drivers/ufs/host/ufs-qcom.c | 43 ++++++++++++++++++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index c0761ccc1381..8cb8f60e8c89 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -1922,11 +1922,52 @@ static int ufs_qcom_config_esi(struct ufs_hba *hba)
return ret;
}
+static unsigned long ufs_qcom_opp_to_clk_freq(struct ufs_hba *hba, unsigned long freq, char *name)
+{
+ struct ufs_clk_info *clki;
+ struct dev_pm_opp *opp;
+ unsigned long unipro_freq;
+ int idx = 0;
+ bool found = false;
+
+ opp = dev_pm_opp_find_freq_exact_indexed(hba->dev, freq, 0, true);
+ if (IS_ERR(opp)) {
+ dev_err(hba->dev, "Failed to find OPP for exact frequency %lu\n", freq);
+ return 0;
+ }
+
+ list_for_each_entry(clki, &hba->clk_list_head, list) {
+ if (!strcmp(cliki->name, name)) {
+ found = true;
+ break;
+ }
+
+ idx ++;
+ }
+
+ if (!found) {
+ dev_err(hba->dev, "Failed to find %s in clk list\n", name);
+ dev_pm_opp_put(opp);
+ return 0;
+ }
+
+ unipro_freq = dev_pm_opp_get_freq_indexed(opp, idx);
+
+ dev_pm_opp_put(opp);
+
+ return unipro_freq;
+}
+
static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq)
{
u32 gear = 0;
+ unsigned long unipro_freq;
+
+ if (!hba->use_pm_opp)
+ return gear;
- switch (freq) {
+ unipro_freq = ufs_qcom_opp_to_clk_freq(hba, freq, "core_clk_unipro");
+ switch (unipro_freq) {
case 403000000:
gear = UFS_HS_G5;
break;
--
2.34.1
-------------- next part --------------
From 655ed70ea2e439ba73f0ed950c924f7ad59cc83f Mon Sep 17 00:00:00 2001
From: Can Guo <quic_cang at quicinc.com>
Date: Sun, 27 Apr 2025 00:22:38 -0700
Subject: [PATCH 2/3] ufs: host: ufs-qcom: Fix ufs_qcom_core_clk_ctrl()
Signed-off-by: Can Guo <quic_cang at quicinc.com>
---
drivers/ufs/host/ufs-qcom.c | 35 +++++++++++++++++++++++++----------
1 file changed, 25 insertions(+), 10 deletions(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 8cb8f60e8c89..398cc21f2ce4 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -103,7 +103,8 @@ static const struct __ufs_qcom_bw_table {
};
static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
-static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq);
+static unsigned long ufs_qcom_opp_to_clk_freq(struct ufs_hba *hba, unsigned long freq, char *name);
+static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq);
static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
{
@@ -602,7 +603,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
return -EINVAL;
}
- err = ufs_qcom_set_core_clk_ctrl(hba, ULONG_MAX);
+ err = ufs_qcom_set_core_clk_ctrl(hba, true, ULONG_MAX);
if (err)
dev_err(hba->dev, "cfg core clk ctrl failed\n");
/*
@@ -1360,24 +1361,38 @@ static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba,
return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg);
}
-static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq)
+static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
struct list_head *head = &hba->clk_list_head;
struct ufs_clk_info *clki;
u32 cycles_in_1us = 0;
u32 core_clk_ctrl_reg;
+ unsigned long clk_freq;
int err;
list_for_each_entry(clki, head, list) {
if (!IS_ERR_OR_NULL(clki->clk) &&
!strcmp(clki->name, "core_clk_unipro")) {
- if (!clki->max_freq)
+ if (!clki->max_freq) {
cycles_in_1us = 150; /* default for backwards compatibility */
- else if (freq == ULONG_MAX)
+ break;
+ }
+
+ if (freq == ULONG_MAX) {
cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ);
- else
- cycles_in_1us = ceil(freq, HZ_PER_MHZ);
+ break;
+ }
+
+ if (!hba->use_pm_opp) {
+ if (is_scale_up)
+ cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ);
+ else
+ cycles_in_1us = ceil(clk_get_rate(clki->clk), HZ_PER_MHZ);
+ } else {
+ clk_freq = ufs_qcom_opp_to_clk_freq(hba, freq, "core_clk_unipro");
+ cycles_in_1us = ceil(clk_freq, HZ_PER_MHZ);
+ }
break;
}
@@ -1425,7 +1440,7 @@ static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long f
return ret;
}
/* set unipro core clock attributes and clear clock divider */
- return ufs_qcom_set_core_clk_ctrl(hba, freq);
+ return ufs_qcom_set_core_clk_ctrl(hba, true, freq);
}
static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
@@ -1457,7 +1472,7 @@ static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba, unsigned long freq)
{
/* set unipro core clock attributes and clear clock divider */
- return ufs_qcom_set_core_clk_ctrl(hba, freq);
+ return ufs_qcom_set_core_clk_ctrl(hba, false, freq);
}
static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up,
@@ -1937,7 +1952,7 @@ static unsigned long ufs_qcom_opp_to_clk_freq(struct ufs_hba *hba, unsigned long
}
list_for_each_entry(clki, &hba->clk_list_head, list) {
- if (!strcmp(cliki->name, name)) {
+ if (!strcmp(clki->name, name)) {
found = true;
break;
}
--
2.34.1
-------------- next part --------------
From 7655132c9e5436a637aeafb273a639236122533a Mon Sep 17 00:00:00 2001
From: Can Guo <quic_cang at quicinc.com>
Date: Sun, 27 Apr 2025 00:37:39 -0700
Subject: [PATCH 3/3] ufs: host: ufs-qcom: Fix ufs_qcom_cfg_timers()
Signed-off-by: Can Guo <quic_cang at quicinc.com>
---
drivers/ufs/host/ufs-qcom.c | 51 +++++++++++++++++++++----------------
1 file changed, 29 insertions(+), 22 deletions(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 398cc21f2ce4..b2bf80070711 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -544,13 +544,14 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
*
* @hba: host controller instance
* @is_pre_scale_up: flag to check if pre scale up condition.
+ * @freq: target opp freq
* Return: zero for success and non-zero in case of a failure.
*/
-static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up)
+static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsigned long freq)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
struct ufs_clk_info *clki;
- unsigned long core_clk_rate = 0;
+ unsigned long clk_freq = 0;
u32 core_clk_cycles_per_us;
/*
@@ -564,20 +565,30 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up)
list_for_each_entry(clki, &hba->clk_list_head, list) {
if (!strcmp(clki->name, "core_clk")) {
- if (is_pre_scale_up)
- core_clk_rate = clki->max_freq;
- else
- core_clk_rate = clk_get_rate(clki->clk);
+ if (freq == ULONG_MAX) {
+ clk_freq = clki->max_freq;
+ break;
+ }
+
+ if (!hba->use_pm_opp) {
+ if (is_pre_scale_up)
+ clk_freq = clki->max_freq;
+ else
+ clk_freq = clk_get_rate(clki->clk);
+ } else {
+ clk_freq = ufs_qcom_opp_to_clk_freq(hba, freq, "core_clk");
+ }
+
break;
}
}
/* If frequency is smaller than 1MHz, set to 1MHz */
- if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
- core_clk_rate = DEFAULT_CLK_RATE_HZ;
+ if (clk_freq < DEFAULT_CLK_RATE_HZ)
+ clk_freq = DEFAULT_CLK_RATE_HZ;
- core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
+ core_clk_cycles_per_us = clk_freq / USEC_PER_SEC;
if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
/*
@@ -597,7 +608,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
switch (status) {
case PRE_CHANGE:
- if (ufs_qcom_cfg_timers(hba, false)) {
+ if (ufs_qcom_cfg_timers(hba, false, ULONG_MAX)) {
dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
__func__);
return -EINVAL;
@@ -875,17 +886,6 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
break;
case POST_CHANGE:
- if (ufs_qcom_cfg_timers(hba, false)) {
- dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
- __func__);
- /*
- * we return error code at the end of the routine,
- * but continue to configure UFS_PHY_TX_LANE_ENABLE
- * and bus voting as usual
- */
- ret = -EINVAL;
- }
-
/* cache the power mode parameters to use internally */
memcpy(&host->dev_req_params,
dev_req_params, sizeof(*dev_req_params));
@@ -1434,7 +1434,7 @@ static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long f
{
int ret;
- ret = ufs_qcom_cfg_timers(hba, true);
+ ret = ufs_qcom_cfg_timers(hba, true, freq);
if (ret) {
dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__);
return ret;
@@ -1471,6 +1471,13 @@ static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba, unsigned long freq)
{
+ int ret;
+
+ ret = ufs_qcom_cfg_timers(hba, false, freq);
+ if (ret) {
+ dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__);
+ ret = -EINVAL;
+ }
/* set unipro core clock attributes and clear clock divider */
return ufs_qcom_set_core_clk_ctrl(hba, false, freq);
}
--
2.34.1
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