[PATCH 3/5] drm/mediatek: Add dvo driver for mt8196
kernel test robot
lkp at intel.com
Sat Apr 19 00:19:05 PDT 2025
Hi Bincai,
kernel test robot noticed the following build errors:
[auto build test ERROR on robh/for-next]
[also build test ERROR on pza/reset/next linus/master v6.15-rc2 next-20250417]
[cannot apply to pza/imx-drm/next drm-misc/drm-misc-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Bincai-Liu/dt-bindings-eDP-mediatek-add-eDP-yaml-for-mt8196/20250418-145911
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20250418065313.8972-4-bincai.liu%40mediatek.com
patch subject: [PATCH 3/5] drm/mediatek: Add dvo driver for mt8196
config: i386-buildonly-randconfig-006-20250419 (https://download.01.org/0day-ci/archive/20250419/202504191551.u0FJoQ3O-lkp@intel.com/config)
compiler: clang version 20.1.2 (https://github.com/llvm/llvm-project 58df0ef89dd64126512e4ee27b4ac3fd8ddf6247)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250419/202504191551.u0FJoQ3O-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202504191551.u0FJoQ3O-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/mediatek/mtk_ddp_comp.c:476:3: error: use of undeclared identifier 'DDP_COMPONENT_DVO0'
476 | [DDP_COMPONENT_DVO0] = { MTK_DVO, 0, &ddp_dpi },
| ^
1 error generated.
vim +/DDP_COMPONENT_DVO0 +476 drivers/gpu/drm/mediatek/mtk_ddp_comp.c
456
457 static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX] = {
458 [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
459 [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
460 [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
461 [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
462 [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
463 [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
464 [DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
465 [DDP_COMPONENT_DP_INTF0] = { MTK_DP_INTF, 0, &ddp_dpi },
466 [DDP_COMPONENT_DP_INTF1] = { MTK_DP_INTF, 1, &ddp_dpi },
467 [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
468 [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
469 [DDP_COMPONENT_DRM_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor },
470 [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
471 [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
472 [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
473 [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
474 [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
475 [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
> 476 [DDP_COMPONENT_DVO0] = { MTK_DVO, 0, &ddp_dpi },
477 [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
478 [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
479 [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
480 [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
481 [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
482 [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
483 [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
484 [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
485 [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
486 [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
487 [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
488 [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
489 [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
490 [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
491 [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
492 [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
493 [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
494 [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
495 [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
496 [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
497 [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
498 [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma },
499 [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
500 [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
501 [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
502 };
503
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